LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenAsmMatcher.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 859 1598 53.8 %
Date: 2018-02-25 19:55:18 Functions: 12 13 92.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Assembly Matcher Source Fragment                                           *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_ASSEMBLER_HEADER
      11             : #undef GET_ASSEMBLER_HEADER
      12             :   // This should be included into the middle of the declaration of
      13             :   // your subclasses implementation of MCTargetAsmParser.
      14             :   uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
      15             :   void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
      16             :                        const OperandVector &Operands);
      17             :   void convertToMapAndConstraints(unsigned Kind,
      18             :                            const OperandVector &Operands) override;
      19             :   unsigned MatchInstructionImpl(const OperandVector &Operands,
      20             :                                 MCInst &Inst,
      21             :                                 uint64_t &ErrorInfo,
      22             :                                 bool matchingInlineAsm,
      23             :                                 unsigned VariantID = 0);
      24             :   OperandMatchResultTy MatchOperandParserImpl(
      25             :     OperandVector &Operands,
      26             :     StringRef Mnemonic,
      27             :     bool ParseForAllFeatures = false);
      28             :   OperandMatchResultTy tryCustomParseOperand(
      29             :     OperandVector &Operands,
      30             :     unsigned MCK);
      31             : 
      32             : #endif // GET_ASSEMBLER_HEADER_INFO
      33             : 
      34             : 
      35             : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
      36             : #undef GET_OPERAND_DIAGNOSTIC_TYPES
      37             : 
      38             :   Match_AddSubRegExtendLarge,
      39             :   Match_AddSubRegExtendSmall,
      40             :   Match_AddSubRegShift32,
      41             :   Match_AddSubRegShift64,
      42             :   Match_AddSubSecondSource,
      43             :   Match_InvalidComplexRotationEven,
      44             :   Match_InvalidComplexRotationOdd,
      45             :   Match_InvalidCondCode,
      46             :   Match_InvalidFPImm,
      47             :   Match_InvalidImm0_1,
      48             :   Match_InvalidImm0_127,
      49             :   Match_InvalidImm0_15,
      50             :   Match_InvalidImm0_255,
      51             :   Match_InvalidImm0_31,
      52             :   Match_InvalidImm0_63,
      53             :   Match_InvalidImm0_65535,
      54             :   Match_InvalidImm0_7,
      55             :   Match_InvalidImm1_16,
      56             :   Match_InvalidImm1_32,
      57             :   Match_InvalidImm1_64,
      58             :   Match_InvalidImm1_8,
      59             :   Match_InvalidIndex1,
      60             :   Match_InvalidIndexB,
      61             :   Match_InvalidIndexD,
      62             :   Match_InvalidIndexH,
      63             :   Match_InvalidIndexS,
      64             :   Match_InvalidLabel,
      65             :   Match_InvalidMemoryIndexed1,
      66             :   Match_InvalidMemoryIndexed16,
      67             :   Match_InvalidMemoryIndexed16SImm7,
      68             :   Match_InvalidMemoryIndexed2,
      69             :   Match_InvalidMemoryIndexed4,
      70             :   Match_InvalidMemoryIndexed4SImm7,
      71             :   Match_InvalidMemoryIndexed8,
      72             :   Match_InvalidMemoryIndexed8SImm7,
      73             :   Match_InvalidMemoryIndexedSImm10,
      74             :   Match_InvalidMemoryIndexedSImm6,
      75             :   Match_InvalidMemoryIndexedSImm9,
      76             :   Match_InvalidMemoryWExtend128,
      77             :   Match_InvalidMemoryWExtend16,
      78             :   Match_InvalidMemoryWExtend32,
      79             :   Match_InvalidMemoryWExtend64,
      80             :   Match_InvalidMemoryWExtend8,
      81             :   Match_InvalidMemoryXExtend128,
      82             :   Match_InvalidMemoryXExtend16,
      83             :   Match_InvalidMemoryXExtend32,
      84             :   Match_InvalidMemoryXExtend64,
      85             :   Match_InvalidMemoryXExtend8,
      86             :   Match_InvalidMovImm32Shift,
      87             :   Match_InvalidMovImm64Shift,
      88             :   Match_InvalidSVEPattern,
      89             :   Match_InvalidSVEPredicate3bAnyReg,
      90             :   Match_InvalidSVEPredicate3bBReg,
      91             :   Match_InvalidSVEPredicate3bDReg,
      92             :   Match_InvalidSVEPredicate3bHReg,
      93             :   Match_InvalidSVEPredicate3bSReg,
      94             :   Match_InvalidSVEPredicateAnyReg,
      95             :   Match_InvalidSVEPredicateBReg,
      96             :   Match_InvalidSVEPredicateDReg,
      97             :   Match_InvalidSVEPredicateHReg,
      98             :   Match_InvalidSVEPredicateSReg,
      99             :   Match_LogicalSecondSource,
     100             :   Match_MRS,
     101             :   Match_MSR,
     102             :   END_OPERAND_DIAGNOSTIC_TYPES
     103             : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
     104             : 
     105             : 
     106             : #ifdef GET_REGISTER_MATCHER
     107             : #undef GET_REGISTER_MATCHER
     108             : 
     109             : // Flags for subtarget features that participate in instruction matching.
     110             : enum SubtargetFeatureFlag : uint32_t {
     111             :   Feature_HasV8_1a = (1ULL << 13),
     112             :   Feature_HasV8_2a = (1ULL << 14),
     113             :   Feature_HasV8_3a = (1ULL << 15),
     114             :   Feature_HasFPARMv8 = (1ULL << 3),
     115             :   Feature_HasNEON = (1ULL << 7),
     116             :   Feature_HasCrypto = (1ULL << 1),
     117             :   Feature_HasDotProd = (1ULL << 2),
     118             :   Feature_HasCRC = (1ULL << 0),
     119             :   Feature_HasLSE = (1ULL << 6),
     120             :   Feature_HasRAS = (1ULL << 8),
     121             :   Feature_HasRDM = (1ULL << 10),
     122             :   Feature_HasFullFP16 = (1ULL << 4),
     123             :   Feature_HasSPE = (1ULL << 11),
     124             :   Feature_HasFuseAES = (1ULL << 5),
     125             :   Feature_HasSVE = (1ULL << 12),
     126             :   Feature_HasRCPC = (1ULL << 9),
     127             :   Feature_UseNegativeImmediates = (1ULL << 16),
     128             :   Feature_None = 0
     129             : };
     130             : 
     131       78051 : static unsigned MatchRegisterName(StringRef Name) {
     132       78051 :   switch (Name.size()) {
     133             :   default: break;
     134       57825 :   case 2:        // 91 strings to match.
     135       57825 :     switch (Name[0]) {
     136             :     default: break;
     137        3931 :     case 'b':    // 10 strings to match.
     138        3931 :       switch (Name[1]) {
     139             :       default: break;
     140             :       case '0':  // 1 string to match.
     141             :         return 8;        // "b0"
     142             :       case '1':  // 1 string to match.
     143             :         return 9;        // "b1"
     144             :       case '2':  // 1 string to match.
     145             :         return 10;       // "b2"
     146             :       case '3':  // 1 string to match.
     147             :         return 11;       // "b3"
     148             :       case '4':  // 1 string to match.
     149             :         return 12;       // "b4"
     150             :       case '5':  // 1 string to match.
     151             :         return 13;       // "b5"
     152             :       case '6':  // 1 string to match.
     153             :         return 14;       // "b6"
     154             :       case '7':  // 1 string to match.
     155             :         return 15;       // "b7"
     156             :       case '8':  // 1 string to match.
     157             :         return 16;       // "b8"
     158             :       case '9':  // 1 string to match.
     159             :         return 17;       // "b9"
     160             :       }
     161             :       break;
     162        1551 :     case 'd':    // 10 strings to match.
     163        1551 :       switch (Name[1]) {
     164             :       default: break;
     165             :       case '0':  // 1 string to match.
     166             :         return 40;       // "d0"
     167             :       case '1':  // 1 string to match.
     168             :         return 41;       // "d1"
     169             :       case '2':  // 1 string to match.
     170             :         return 42;       // "d2"
     171             :       case '3':  // 1 string to match.
     172             :         return 43;       // "d3"
     173             :       case '4':  // 1 string to match.
     174             :         return 44;       // "d4"
     175             :       case '5':  // 1 string to match.
     176             :         return 45;       // "d5"
     177             :       case '6':  // 1 string to match.
     178             :         return 46;       // "d6"
     179             :       case '7':  // 1 string to match.
     180             :         return 47;       // "d7"
     181             :       case '8':  // 1 string to match.
     182             :         return 48;       // "d8"
     183             :       case '9':  // 1 string to match.
     184             :         return 49;       // "d9"
     185             :       }
     186             :       break;
     187        4207 :     case 'h':    // 10 strings to match.
     188        4207 :       switch (Name[1]) {
     189             :       default: break;
     190             :       case '0':  // 1 string to match.
     191             :         return 72;       // "h0"
     192             :       case '1':  // 1 string to match.
     193             :         return 73;       // "h1"
     194             :       case '2':  // 1 string to match.
     195             :         return 74;       // "h2"
     196             :       case '3':  // 1 string to match.
     197             :         return 75;       // "h3"
     198             :       case '4':  // 1 string to match.
     199             :         return 76;       // "h4"
     200             :       case '5':  // 1 string to match.
     201             :         return 77;       // "h5"
     202             :       case '6':  // 1 string to match.
     203             :         return 78;       // "h6"
     204             :       case '7':  // 1 string to match.
     205             :         return 79;       // "h7"
     206             :       case '8':  // 1 string to match.
     207             :         return 80;       // "h8"
     208             :       case '9':  // 1 string to match.
     209             :         return 81;       // "h9"
     210             :       }
     211             :       break;
     212           0 :     case 'p':    // 10 strings to match.
     213           0 :       switch (Name[1]) {
     214             :       default: break;
     215             :       case '0':  // 1 string to match.
     216             :         return 104;      // "p0"
     217             :       case '1':  // 1 string to match.
     218             :         return 105;      // "p1"
     219             :       case '2':  // 1 string to match.
     220             :         return 106;      // "p2"
     221             :       case '3':  // 1 string to match.
     222             :         return 107;      // "p3"
     223             :       case '4':  // 1 string to match.
     224             :         return 108;      // "p4"
     225             :       case '5':  // 1 string to match.
     226             :         return 109;      // "p5"
     227             :       case '6':  // 1 string to match.
     228             :         return 110;      // "p6"
     229             :       case '7':  // 1 string to match.
     230             :         return 111;      // "p7"
     231             :       case '8':  // 1 string to match.
     232             :         return 112;      // "p8"
     233             :       case '9':  // 1 string to match.
     234             :         return 113;      // "p9"
     235             :       }
     236             :       break;
     237         265 :     case 'q':    // 10 strings to match.
     238         265 :       switch (Name[1]) {
     239             :       default: break;
     240             :       case '0':  // 1 string to match.
     241             :         return 120;      // "q0"
     242             :       case '1':  // 1 string to match.
     243             :         return 121;      // "q1"
     244             :       case '2':  // 1 string to match.
     245             :         return 122;      // "q2"
     246             :       case '3':  // 1 string to match.
     247             :         return 123;      // "q3"
     248             :       case '4':  // 1 string to match.
     249             :         return 124;      // "q4"
     250             :       case '5':  // 1 string to match.
     251             :         return 125;      // "q5"
     252             :       case '6':  // 1 string to match.
     253             :         return 126;      // "q6"
     254             :       case '7':  // 1 string to match.
     255             :         return 127;      // "q7"
     256             :       case '8':  // 1 string to match.
     257             :         return 128;      // "q8"
     258             :       case '9':  // 1 string to match.
     259             :         return 129;      // "q9"
     260             :       }
     261             :       break;
     262        6685 :     case 's':    // 11 strings to match.
     263        6685 :       switch (Name[1]) {
     264             :       default: break;
     265             :       case '0':  // 1 string to match.
     266             :         return 152;      // "s0"
     267             :       case '1':  // 1 string to match.
     268             :         return 153;      // "s1"
     269             :       case '2':  // 1 string to match.
     270             :         return 154;      // "s2"
     271             :       case '3':  // 1 string to match.
     272             :         return 155;      // "s3"
     273             :       case '4':  // 1 string to match.
     274             :         return 156;      // "s4"
     275             :       case '5':  // 1 string to match.
     276             :         return 157;      // "s5"
     277             :       case '6':  // 1 string to match.
     278             :         return 158;      // "s6"
     279             :       case '7':  // 1 string to match.
     280             :         return 159;      // "s7"
     281             :       case '8':  // 1 string to match.
     282             :         return 160;      // "s8"
     283             :       case '9':  // 1 string to match.
     284             :         return 161;      // "s9"
     285             :       case 'p':  // 1 string to match.
     286             :         return 4;        // "sp"
     287             :       }
     288             :       break;
     289       15568 :     case 'w':    // 10 strings to match.
     290       15568 :       switch (Name[1]) {
     291             :       default: break;
     292             :       case '0':  // 1 string to match.
     293             :         return 184;      // "w0"
     294             :       case '1':  // 1 string to match.
     295             :         return 185;      // "w1"
     296             :       case '2':  // 1 string to match.
     297             :         return 186;      // "w2"
     298             :       case '3':  // 1 string to match.
     299             :         return 187;      // "w3"
     300             :       case '4':  // 1 string to match.
     301             :         return 188;      // "w4"
     302             :       case '5':  // 1 string to match.
     303             :         return 189;      // "w5"
     304             :       case '6':  // 1 string to match.
     305             :         return 190;      // "w6"
     306             :       case '7':  // 1 string to match.
     307             :         return 191;      // "w7"
     308             :       case '8':  // 1 string to match.
     309             :         return 192;      // "w8"
     310             :       case '9':  // 1 string to match.
     311             :         return 193;      // "w9"
     312             :       }
     313             :       break;
     314       25451 :     case 'x':    // 10 strings to match.
     315       25451 :       switch (Name[1]) {
     316             :       default: break;
     317             :       case '0':  // 1 string to match.
     318             :         return 215;      // "x0"
     319             :       case '1':  // 1 string to match.
     320             :         return 216;      // "x1"
     321             :       case '2':  // 1 string to match.
     322             :         return 217;      // "x2"
     323             :       case '3':  // 1 string to match.
     324             :         return 218;      // "x3"
     325             :       case '4':  // 1 string to match.
     326             :         return 219;      // "x4"
     327             :       case '5':  // 1 string to match.
     328             :         return 220;      // "x5"
     329             :       case '6':  // 1 string to match.
     330             :         return 221;      // "x6"
     331             :       case '7':  // 1 string to match.
     332             :         return 222;      // "x7"
     333             :       case '8':  // 1 string to match.
     334             :         return 223;      // "x8"
     335             :       case '9':  // 1 string to match.
     336             :         return 224;      // "x9"
     337             :       }
     338             :       break;
     339           0 :     case 'z':    // 10 strings to match.
     340           0 :       switch (Name[1]) {
     341             :       default: break;
     342             :       case '0':  // 1 string to match.
     343             :         return 244;      // "z0"
     344             :       case '1':  // 1 string to match.
     345             :         return 245;      // "z1"
     346             :       case '2':  // 1 string to match.
     347             :         return 246;      // "z2"
     348             :       case '3':  // 1 string to match.
     349             :         return 247;      // "z3"
     350             :       case '4':  // 1 string to match.
     351             :         return 248;      // "z4"
     352             :       case '5':  // 1 string to match.
     353             :         return 249;      // "z5"
     354             :       case '6':  // 1 string to match.
     355             :         return 250;      // "z6"
     356             :       case '7':  // 1 string to match.
     357             :         return 251;      // "z7"
     358             :       case '8':  // 1 string to match.
     359             :         return 252;      // "z8"
     360             :       case '9':  // 1 string to match.
     361             :         return 253;      // "z9"
     362             :       }
     363             :       break;
     364             :     }
     365             :     break;
     366       19090 :   case 3:        // 183 strings to match.
     367       19090 :     switch (Name[0]) {
     368             :     default: break;
     369         182 :     case 'b':    // 22 strings to match.
     370         182 :       switch (Name[1]) {
     371             :       default: break;
     372         130 :       case '1':  // 10 strings to match.
     373         130 :         switch (Name[2]) {
     374             :         default: break;
     375             :         case '0':        // 1 string to match.
     376             :           return 18;     // "b10"
     377             :         case '1':        // 1 string to match.
     378             :           return 19;     // "b11"
     379             :         case '2':        // 1 string to match.
     380             :           return 20;     // "b12"
     381             :         case '3':        // 1 string to match.
     382             :           return 21;     // "b13"
     383             :         case '4':        // 1 string to match.
     384             :           return 22;     // "b14"
     385             :         case '5':        // 1 string to match.
     386             :           return 23;     // "b15"
     387             :         case '6':        // 1 string to match.
     388             :           return 24;     // "b16"
     389             :         case '7':        // 1 string to match.
     390             :           return 25;     // "b17"
     391             :         case '8':        // 1 string to match.
     392             :           return 26;     // "b18"
     393             :         case '9':        // 1 string to match.
     394             :           return 27;     // "b19"
     395             :         }
     396             :         break;
     397          22 :       case '2':  // 10 strings to match.
     398          22 :         switch (Name[2]) {
     399             :         default: break;
     400             :         case '0':        // 1 string to match.
     401             :           return 28;     // "b20"
     402             :         case '1':        // 1 string to match.
     403             :           return 29;     // "b21"
     404             :         case '2':        // 1 string to match.
     405             :           return 30;     // "b22"
     406             :         case '3':        // 1 string to match.
     407             :           return 31;     // "b23"
     408             :         case '4':        // 1 string to match.
     409             :           return 32;     // "b24"
     410             :         case '5':        // 1 string to match.
     411             :           return 33;     // "b25"
     412             :         case '6':        // 1 string to match.
     413             :           return 34;     // "b26"
     414             :         case '7':        // 1 string to match.
     415             :           return 35;     // "b27"
     416             :         case '8':        // 1 string to match.
     417             :           return 36;     // "b28"
     418             :         case '9':        // 1 string to match.
     419             :           return 37;     // "b29"
     420             :         }
     421             :         break;
     422           2 :       case '3':  // 2 strings to match.
     423           2 :         switch (Name[2]) {
     424             :         default: break;
     425             :         case '0':        // 1 string to match.
     426             :           return 38;     // "b30"
     427           2 :         case '1':        // 1 string to match.
     428           2 :           return 39;     // "b31"
     429             :         }
     430             :         break;
     431             :       }
     432             :       break;
     433         944 :     case 'd':    // 22 strings to match.
     434         944 :       switch (Name[1]) {
     435             :       default: break;
     436         396 :       case '1':  // 10 strings to match.
     437         396 :         switch (Name[2]) {
     438             :         default: break;
     439             :         case '0':        // 1 string to match.
     440             :           return 50;     // "d10"
     441             :         case '1':        // 1 string to match.
     442             :           return 51;     // "d11"
     443             :         case '2':        // 1 string to match.
     444             :           return 52;     // "d12"
     445             :         case '3':        // 1 string to match.
     446             :           return 53;     // "d13"
     447             :         case '4':        // 1 string to match.
     448             :           return 54;     // "d14"
     449             :         case '5':        // 1 string to match.
     450             :           return 55;     // "d15"
     451             :         case '6':        // 1 string to match.
     452             :           return 56;     // "d16"
     453             :         case '7':        // 1 string to match.
     454             :           return 57;     // "d17"
     455             :         case '8':        // 1 string to match.
     456             :           return 58;     // "d18"
     457             :         case '9':        // 1 string to match.
     458             :           return 59;     // "d19"
     459             :         }
     460             :         break;
     461         448 :       case '2':  // 10 strings to match.
     462         448 :         switch (Name[2]) {
     463             :         default: break;
     464             :         case '0':        // 1 string to match.
     465             :           return 60;     // "d20"
     466             :         case '1':        // 1 string to match.
     467             :           return 61;     // "d21"
     468             :         case '2':        // 1 string to match.
     469             :           return 62;     // "d22"
     470             :         case '3':        // 1 string to match.
     471             :           return 63;     // "d23"
     472             :         case '4':        // 1 string to match.
     473             :           return 64;     // "d24"
     474             :         case '5':        // 1 string to match.
     475             :           return 65;     // "d25"
     476             :         case '6':        // 1 string to match.
     477             :           return 66;     // "d26"
     478             :         case '7':        // 1 string to match.
     479             :           return 67;     // "d27"
     480             :         case '8':        // 1 string to match.
     481             :           return 68;     // "d28"
     482             :         case '9':        // 1 string to match.
     483             :           return 69;     // "d29"
     484             :         }
     485             :         break;
     486         100 :       case '3':  // 2 strings to match.
     487         100 :         switch (Name[2]) {
     488             :         default: break;
     489             :         case '0':        // 1 string to match.
     490             :           return 70;     // "d30"
     491          80 :         case '1':        // 1 string to match.
     492          80 :           return 71;     // "d31"
     493             :         }
     494             :         break;
     495             :       }
     496             :       break;
     497         852 :     case 'h':    // 22 strings to match.
     498         852 :       switch (Name[1]) {
     499             :       default: break;
     500         690 :       case '1':  // 10 strings to match.
     501         690 :         switch (Name[2]) {
     502             :         default: break;
     503             :         case '0':        // 1 string to match.
     504             :           return 82;     // "h10"
     505             :         case '1':        // 1 string to match.
     506             :           return 83;     // "h11"
     507             :         case '2':        // 1 string to match.
     508             :           return 84;     // "h12"
     509             :         case '3':        // 1 string to match.
     510             :           return 85;     // "h13"
     511             :         case '4':        // 1 string to match.
     512             :           return 86;     // "h14"
     513             :         case '5':        // 1 string to match.
     514             :           return 87;     // "h15"
     515             :         case '6':        // 1 string to match.
     516             :           return 88;     // "h16"
     517             :         case '7':        // 1 string to match.
     518             :           return 89;     // "h17"
     519             :         case '8':        // 1 string to match.
     520             :           return 90;     // "h18"
     521             :         case '9':        // 1 string to match.
     522             :           return 91;     // "h19"
     523             :         }
     524             :         break;
     525         142 :       case '2':  // 10 strings to match.
     526         142 :         switch (Name[2]) {
     527             :         default: break;
     528             :         case '0':        // 1 string to match.
     529             :           return 92;     // "h20"
     530             :         case '1':        // 1 string to match.
     531             :           return 93;     // "h21"
     532             :         case '2':        // 1 string to match.
     533             :           return 94;     // "h22"
     534             :         case '3':        // 1 string to match.
     535             :           return 95;     // "h23"
     536             :         case '4':        // 1 string to match.
     537             :           return 96;     // "h24"
     538             :         case '5':        // 1 string to match.
     539             :           return 97;     // "h25"
     540             :         case '6':        // 1 string to match.
     541             :           return 98;     // "h26"
     542             :         case '7':        // 1 string to match.
     543             :           return 99;     // "h27"
     544             :         case '8':        // 1 string to match.
     545             :           return 100;    // "h28"
     546             :         case '9':        // 1 string to match.
     547             :           return 101;    // "h29"
     548             :         }
     549             :         break;
     550          20 :       case '3':  // 2 strings to match.
     551          20 :         switch (Name[2]) {
     552             :         default: break;
     553             :         case '0':        // 1 string to match.
     554             :           return 102;    // "h30"
     555          10 :         case '1':        // 1 string to match.
     556          10 :           return 103;    // "h31"
     557             :         }
     558             :         break;
     559             :       }
     560             :       break;
     561          34 :     case 'p':    // 6 strings to match.
     562          34 :       if (Name[1] != '1')
     563             :         break;
     564          34 :       switch (Name[2]) {
     565             :       default: break;
     566             :       case '0':  // 1 string to match.
     567             :         return 114;      // "p10"
     568             :       case '1':  // 1 string to match.
     569             :         return 115;      // "p11"
     570             :       case '2':  // 1 string to match.
     571             :         return 116;      // "p12"
     572             :       case '3':  // 1 string to match.
     573             :         return 117;      // "p13"
     574             :       case '4':  // 1 string to match.
     575             :         return 118;      // "p14"
     576             :       case '5':  // 1 string to match.
     577             :         return 119;      // "p15"
     578             :       }
     579             :       break;
     580         214 :     case 'q':    // 22 strings to match.
     581         214 :       switch (Name[1]) {
     582             :       default: break;
     583          62 :       case '1':  // 10 strings to match.
     584          62 :         switch (Name[2]) {
     585             :         default: break;
     586             :         case '0':        // 1 string to match.
     587             :           return 130;    // "q10"
     588             :         case '1':        // 1 string to match.
     589             :           return 131;    // "q11"
     590             :         case '2':        // 1 string to match.
     591             :           return 132;    // "q12"
     592             :         case '3':        // 1 string to match.
     593             :           return 133;    // "q13"
     594             :         case '4':        // 1 string to match.
     595             :           return 134;    // "q14"
     596             :         case '5':        // 1 string to match.
     597             :           return 135;    // "q15"
     598             :         case '6':        // 1 string to match.
     599             :           return 136;    // "q16"
     600             :         case '7':        // 1 string to match.
     601             :           return 137;    // "q17"
     602             :         case '8':        // 1 string to match.
     603             :           return 138;    // "q18"
     604             :         case '9':        // 1 string to match.
     605             :           return 139;    // "q19"
     606             :         }
     607             :         break;
     608         144 :       case '2':  // 10 strings to match.
     609         144 :         switch (Name[2]) {
     610             :         default: break;
     611             :         case '0':        // 1 string to match.
     612             :           return 140;    // "q20"
     613             :         case '1':        // 1 string to match.
     614             :           return 141;    // "q21"
     615             :         case '2':        // 1 string to match.
     616             :           return 142;    // "q22"
     617             :         case '3':        // 1 string to match.
     618             :           return 143;    // "q23"
     619             :         case '4':        // 1 string to match.
     620             :           return 144;    // "q24"
     621             :         case '5':        // 1 string to match.
     622             :           return 145;    // "q25"
     623             :         case '6':        // 1 string to match.
     624             :           return 146;    // "q26"
     625             :         case '7':        // 1 string to match.
     626             :           return 147;    // "q27"
     627             :         case '8':        // 1 string to match.
     628             :           return 148;    // "q28"
     629             :         case '9':        // 1 string to match.
     630             :           return 149;    // "q29"
     631             :         }
     632             :         break;
     633           8 :       case '3':  // 2 strings to match.
     634           8 :         switch (Name[2]) {
     635             :         default: break;
     636             :         case '0':        // 1 string to match.
     637             :           return 150;    // "q30"
     638           0 :         case '1':        // 1 string to match.
     639           0 :           return 151;    // "q31"
     640             :         }
     641             :         break;
     642             :       }
     643             :       break;
     644         966 :     case 's':    // 22 strings to match.
     645         966 :       switch (Name[1]) {
     646             :       default: break;
     647         498 :       case '1':  // 10 strings to match.
     648         498 :         switch (Name[2]) {
     649             :         default: break;
     650             :         case '0':        // 1 string to match.
     651             :           return 162;    // "s10"
     652             :         case '1':        // 1 string to match.
     653             :           return 163;    // "s11"
     654             :         case '2':        // 1 string to match.
     655             :           return 164;    // "s12"
     656             :         case '3':        // 1 string to match.
     657             :           return 165;    // "s13"
     658             :         case '4':        // 1 string to match.
     659             :           return 166;    // "s14"
     660             :         case '5':        // 1 string to match.
     661             :           return 167;    // "s15"
     662             :         case '6':        // 1 string to match.
     663             :           return 168;    // "s16"
     664             :         case '7':        // 1 string to match.
     665             :           return 169;    // "s17"
     666             :         case '8':        // 1 string to match.
     667             :           return 170;    // "s18"
     668             :         case '9':        // 1 string to match.
     669             :           return 171;    // "s19"
     670             :         }
     671             :         break;
     672         360 :       case '2':  // 10 strings to match.
     673         360 :         switch (Name[2]) {
     674             :         default: break;
     675             :         case '0':        // 1 string to match.
     676             :           return 172;    // "s20"
     677             :         case '1':        // 1 string to match.
     678             :           return 173;    // "s21"
     679             :         case '2':        // 1 string to match.
     680             :           return 174;    // "s22"
     681             :         case '3':        // 1 string to match.
     682             :           return 175;    // "s23"
     683             :         case '4':        // 1 string to match.
     684             :           return 176;    // "s24"
     685             :         case '5':        // 1 string to match.
     686             :           return 177;    // "s25"
     687             :         case '6':        // 1 string to match.
     688             :           return 178;    // "s26"
     689             :         case '7':        // 1 string to match.
     690             :           return 179;    // "s27"
     691             :         case '8':        // 1 string to match.
     692             :           return 180;    // "s28"
     693             :         case '9':        // 1 string to match.
     694             :           return 181;    // "s29"
     695             :         }
     696             :         break;
     697         100 :       case '3':  // 2 strings to match.
     698         100 :         switch (Name[2]) {
     699             :         default: break;
     700             :         case '0':        // 1 string to match.
     701             :           return 182;    // "s30"
     702          72 :         case '1':        // 1 string to match.
     703          72 :           return 183;    // "s31"
     704             :         }
     705             :         break;
     706             :       }
     707             :       break;
     708        5339 :     case 'w':    // 23 strings to match.
     709        5339 :       switch (Name[1]) {
     710             :       default: break;
     711        2039 :       case '1':  // 10 strings to match.
     712        2039 :         switch (Name[2]) {
     713             :         default: break;
     714             :         case '0':        // 1 string to match.
     715             :           return 194;    // "w10"
     716             :         case '1':        // 1 string to match.
     717             :           return 195;    // "w11"
     718             :         case '2':        // 1 string to match.
     719             :           return 196;    // "w12"
     720             :         case '3':        // 1 string to match.
     721             :           return 197;    // "w13"
     722             :         case '4':        // 1 string to match.
     723             :           return 198;    // "w14"
     724             :         case '5':        // 1 string to match.
     725             :           return 199;    // "w15"
     726             :         case '6':        // 1 string to match.
     727             :           return 200;    // "w16"
     728             :         case '7':        // 1 string to match.
     729             :           return 201;    // "w17"
     730             :         case '8':        // 1 string to match.
     731             :           return 202;    // "w18"
     732             :         case '9':        // 1 string to match.
     733             :           return 203;    // "w19"
     734             :         }
     735             :         break;
     736        1814 :       case '2':  // 10 strings to match.
     737        1814 :         switch (Name[2]) {
     738             :         default: break;
     739             :         case '0':        // 1 string to match.
     740             :           return 204;    // "w20"
     741             :         case '1':        // 1 string to match.
     742             :           return 205;    // "w21"
     743             :         case '2':        // 1 string to match.
     744             :           return 206;    // "w22"
     745             :         case '3':        // 1 string to match.
     746             :           return 207;    // "w23"
     747             :         case '4':        // 1 string to match.
     748             :           return 208;    // "w24"
     749             :         case '5':        // 1 string to match.
     750             :           return 209;    // "w25"
     751             :         case '6':        // 1 string to match.
     752             :           return 210;    // "w26"
     753             :         case '7':        // 1 string to match.
     754             :           return 211;    // "w27"
     755             :         case '8':        // 1 string to match.
     756             :           return 212;    // "w28"
     757             :         case '9':        // 1 string to match.
     758             :           return 213;    // "w29"
     759             :         }
     760             :         break;
     761         176 :       case '3':  // 1 string to match.
     762         176 :         if (Name[2] != '0')
     763             :           break;
     764             :         return 214;      // "w30"
     765         638 :       case 's':  // 1 string to match.
     766         638 :         if (Name[2] != 'p')
     767             :           break;
     768             :         return 5;        // "wsp"
     769         672 :       case 'z':  // 1 string to match.
     770         672 :         if (Name[2] != 'r')
     771             :           break;
     772             :         return 6;        // "wzr"
     773             :       }
     774             :       break;
     775        9177 :     case 'x':    // 22 strings to match.
     776        9177 :       switch (Name[1]) {
     777             :       default: break;
     778        4920 :       case '1':  // 10 strings to match.
     779        4920 :         switch (Name[2]) {
     780             :         default: break;
     781             :         case '0':        // 1 string to match.
     782             :           return 225;    // "x10"
     783             :         case '1':        // 1 string to match.
     784             :           return 226;    // "x11"
     785             :         case '2':        // 1 string to match.
     786             :           return 227;    // "x12"
     787             :         case '3':        // 1 string to match.
     788             :           return 228;    // "x13"
     789             :         case '4':        // 1 string to match.
     790             :           return 229;    // "x14"
     791             :         case '5':        // 1 string to match.
     792             :           return 230;    // "x15"
     793             :         case '6':        // 1 string to match.
     794             :           return 231;    // "x16"
     795             :         case '7':        // 1 string to match.
     796             :           return 232;    // "x17"
     797             :         case '8':        // 1 string to match.
     798             :           return 233;    // "x18"
     799             :         case '9':        // 1 string to match.
     800             :           return 234;    // "x19"
     801             :         }
     802             :         break;
     803        3169 :       case '2':  // 10 strings to match.
     804        3169 :         switch (Name[2]) {
     805             :         default: break;
     806             :         case '0':        // 1 string to match.
     807             :           return 235;    // "x20"
     808             :         case '1':        // 1 string to match.
     809             :           return 236;    // "x21"
     810             :         case '2':        // 1 string to match.
     811             :           return 237;    // "x22"
     812             :         case '3':        // 1 string to match.
     813             :           return 238;    // "x23"
     814             :         case '4':        // 1 string to match.
     815             :           return 239;    // "x24"
     816             :         case '5':        // 1 string to match.
     817             :           return 240;    // "x25"
     818             :         case '6':        // 1 string to match.
     819             :           return 241;    // "x26"
     820             :         case '7':        // 1 string to match.
     821             :           return 242;    // "x27"
     822             :         case '8':        // 1 string to match.
     823             :           return 243;    // "x28"
     824             :         case '9':        // 1 string to match.
     825             :           return 1;      // "x29"
     826             :         }
     827             :         break;
     828         428 :       case '3':  // 1 string to match.
     829         428 :         if (Name[2] != '0')
     830             :           break;
     831             :         return 2;        // "x30"
     832         622 :       case 'z':  // 1 string to match.
     833         622 :         if (Name[2] != 'r')
     834             :           break;
     835             :         return 7;        // "xzr"
     836             :       }
     837             :       break;
     838          70 :     case 'z':    // 22 strings to match.
     839          70 :       switch (Name[1]) {
     840             :       default: break;
     841           0 :       case '1':  // 10 strings to match.
     842           0 :         switch (Name[2]) {
     843             :         default: break;
     844             :         case '0':        // 1 string to match.
     845             :           return 254;    // "z10"
     846             :         case '1':        // 1 string to match.
     847             :           return 255;    // "z11"
     848             :         case '2':        // 1 string to match.
     849             :           return 256;    // "z12"
     850             :         case '3':        // 1 string to match.
     851             :           return 257;    // "z13"
     852             :         case '4':        // 1 string to match.
     853             :           return 258;    // "z14"
     854             :         case '5':        // 1 string to match.
     855             :           return 259;    // "z15"
     856             :         case '6':        // 1 string to match.
     857             :           return 260;    // "z16"
     858             :         case '7':        // 1 string to match.
     859             :           return 261;    // "z17"
     860             :         case '8':        // 1 string to match.
     861             :           return 262;    // "z18"
     862             :         case '9':        // 1 string to match.
     863             :           return 263;    // "z19"
     864             :         }
     865             :         break;
     866           0 :       case '2':  // 10 strings to match.
     867           0 :         switch (Name[2]) {
     868             :         default: break;
     869             :         case '0':        // 1 string to match.
     870             :           return 264;    // "z20"
     871             :         case '1':        // 1 string to match.
     872             :           return 265;    // "z21"
     873             :         case '2':        // 1 string to match.
     874             :           return 266;    // "z22"
     875             :         case '3':        // 1 string to match.
     876             :           return 267;    // "z23"
     877             :         case '4':        // 1 string to match.
     878             :           return 268;    // "z24"
     879             :         case '5':        // 1 string to match.
     880             :           return 269;    // "z25"
     881             :         case '6':        // 1 string to match.
     882             :           return 270;    // "z26"
     883             :         case '7':        // 1 string to match.
     884             :           return 271;    // "z27"
     885             :         case '8':        // 1 string to match.
     886             :           return 272;    // "z28"
     887             :         case '9':        // 1 string to match.
     888             :           return 273;    // "z29"
     889             :         }
     890             :         break;
     891          52 :       case '3':  // 2 strings to match.
     892          52 :         switch (Name[2]) {
     893             :         default: break;
     894             :         case '0':        // 1 string to match.
     895             :           return 274;    // "z30"
     896           0 :         case '1':        // 1 string to match.
     897           0 :           return 275;    // "z31"
     898             :         }
     899             :         break;
     900             :       }
     901             :       break;
     902             :     }
     903             :     break;
     904             :   case 4:        // 1 string to match.
     905         623 :     if (memcmp(Name.data()+0, "nzcv", 4) != 0)
     906             :       break;
     907             :     return 3;    // "nzcv"
     908         150 :   case 5:        // 10 strings to match.
     909         150 :     if (Name[0] != 'z')
     910             :       break;
     911           4 :     switch (Name[1]) {
     912             :     default: break;
     913             :     case '0':    // 1 string to match.
     914           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     915             :         break;
     916             :       return 276;        // "z0_hi"
     917             :     case '1':    // 1 string to match.
     918           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     919             :         break;
     920             :       return 277;        // "z1_hi"
     921             :     case '2':    // 1 string to match.
     922           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     923             :         break;
     924             :       return 278;        // "z2_hi"
     925             :     case '3':    // 1 string to match.
     926           4 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     927             :         break;
     928             :       return 279;        // "z3_hi"
     929             :     case '4':    // 1 string to match.
     930           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     931             :         break;
     932             :       return 280;        // "z4_hi"
     933             :     case '5':    // 1 string to match.
     934           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     935             :         break;
     936             :       return 281;        // "z5_hi"
     937             :     case '6':    // 1 string to match.
     938           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     939             :         break;
     940             :       return 282;        // "z6_hi"
     941             :     case '7':    // 1 string to match.
     942           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     943             :         break;
     944             :       return 283;        // "z7_hi"
     945             :     case '8':    // 1 string to match.
     946           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     947             :         break;
     948             :       return 284;        // "z8_hi"
     949             :     case '9':    // 1 string to match.
     950           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     951             :         break;
     952             :       return 285;        // "z9_hi"
     953             :     }
     954             :     break;
     955          56 :   case 6:        // 22 strings to match.
     956          56 :     if (Name[0] != 'z')
     957             :       break;
     958           0 :     switch (Name[1]) {
     959             :     default: break;
     960           0 :     case '1':    // 10 strings to match.
     961           0 :       switch (Name[2]) {
     962             :       default: break;
     963             :       case '0':  // 1 string to match.
     964           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     965             :           break;
     966             :         return 286;      // "z10_hi"
     967             :       case '1':  // 1 string to match.
     968           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     969             :           break;
     970             :         return 287;      // "z11_hi"
     971             :       case '2':  // 1 string to match.
     972           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     973             :           break;
     974             :         return 288;      // "z12_hi"
     975             :       case '3':  // 1 string to match.
     976           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     977             :           break;
     978             :         return 289;      // "z13_hi"
     979             :       case '4':  // 1 string to match.
     980           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     981             :           break;
     982             :         return 290;      // "z14_hi"
     983             :       case '5':  // 1 string to match.
     984           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     985             :           break;
     986             :         return 291;      // "z15_hi"
     987             :       case '6':  // 1 string to match.
     988           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     989             :           break;
     990             :         return 292;      // "z16_hi"
     991             :       case '7':  // 1 string to match.
     992           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     993             :           break;
     994             :         return 293;      // "z17_hi"
     995             :       case '8':  // 1 string to match.
     996           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
     997             :           break;
     998             :         return 294;      // "z18_hi"
     999             :       case '9':  // 1 string to match.
    1000           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1001             :           break;
    1002             :         return 295;      // "z19_hi"
    1003             :       }
    1004             :       break;
    1005           0 :     case '2':    // 10 strings to match.
    1006           0 :       switch (Name[2]) {
    1007             :       default: break;
    1008             :       case '0':  // 1 string to match.
    1009           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1010             :           break;
    1011             :         return 296;      // "z20_hi"
    1012             :       case '1':  // 1 string to match.
    1013           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1014             :           break;
    1015             :         return 297;      // "z21_hi"
    1016             :       case '2':  // 1 string to match.
    1017           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1018             :           break;
    1019             :         return 298;      // "z22_hi"
    1020             :       case '3':  // 1 string to match.
    1021           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1022             :           break;
    1023             :         return 299;      // "z23_hi"
    1024             :       case '4':  // 1 string to match.
    1025           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1026             :           break;
    1027             :         return 300;      // "z24_hi"
    1028             :       case '5':  // 1 string to match.
    1029           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1030             :           break;
    1031             :         return 301;      // "z25_hi"
    1032             :       case '6':  // 1 string to match.
    1033           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1034             :           break;
    1035             :         return 302;      // "z26_hi"
    1036             :       case '7':  // 1 string to match.
    1037           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1038             :           break;
    1039             :         return 303;      // "z27_hi"
    1040             :       case '8':  // 1 string to match.
    1041           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1042             :           break;
    1043             :         return 304;      // "z28_hi"
    1044             :       case '9':  // 1 string to match.
    1045           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1046             :           break;
    1047             :         return 305;      // "z29_hi"
    1048             :       }
    1049             :       break;
    1050           0 :     case '3':    // 2 strings to match.
    1051           0 :       switch (Name[2]) {
    1052             :       default: break;
    1053             :       case '0':  // 1 string to match.
    1054           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1055             :           break;
    1056             :         return 306;      // "z30_hi"
    1057             :       case '1':  // 1 string to match.
    1058           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1059             :           break;
    1060             :         return 307;      // "z31_hi"
    1061             :       }
    1062             :       break;
    1063             :     }
    1064             :     break;
    1065             :   }
    1066             :   return 0;
    1067             : }
    1068             : 
    1069             : #endif // GET_REGISTER_MATCHER
    1070             : 
    1071             : 
    1072             : #ifdef GET_SUBTARGET_FEATURE_NAME
    1073             : #undef GET_SUBTARGET_FEATURE_NAME
    1074             : 
    1075             : // User-level names for subtarget features that participate in
    1076             : // instruction matching.
    1077         915 : static const char *getSubtargetFeatureName(uint64_t Val) {
    1078         915 :   switch(Val) {
    1079             :   case Feature_HasV8_1a: return "armv8.1a";
    1080           0 :   case Feature_HasV8_2a: return "armv8.2a";
    1081          80 :   case Feature_HasV8_3a: return "armv8.3a";
    1082           3 :   case Feature_HasFPARMv8: return "fp-armv8";
    1083         199 :   case Feature_HasNEON: return "neon";
    1084          17 :   case Feature_HasCrypto: return "crypto";
    1085          10 :   case Feature_HasDotProd: return "dotprod";
    1086          19 :   case Feature_HasCRC: return "crc";
    1087           4 :   case Feature_HasLSE: return "lse";
    1088           1 :   case Feature_HasRAS: return "ras";
    1089           0 :   case Feature_HasRDM: return "rdm";
    1090         335 :   case Feature_HasFullFP16: return "fullfp16";
    1091           1 :   case Feature_HasSPE: return "spe";
    1092           0 :   case Feature_HasFuseAES: return "fuse-aes";
    1093         212 :   case Feature_HasSVE: return "sve";
    1094           6 :   case Feature_HasRCPC: return "rcpc";
    1095          28 :   case Feature_UseNegativeImmediates: return "NegativeImmediates";
    1096           0 :   default: return "(unknown)";
    1097             :   }
    1098             : }
    1099             : 
    1100             : #endif // GET_SUBTARGET_FEATURE_NAME
    1101             : 
    1102             : 
    1103             : #ifdef GET_MATCHER_IMPLEMENTATION
    1104             : #undef GET_MATCHER_IMPLEMENTATION
    1105             : 
    1106             : enum {
    1107             :   Tie0_1_1,
    1108             :   Tie0_1_2,
    1109             :   Tie0_1_5,
    1110             :   Tie0_2_2,
    1111             :   Tie0_3_3,
    1112             :   Tie0_4_4,
    1113             :   Tie0_5_5,
    1114             :   Tie1_1_1,
    1115             :   Tie1_2_2,
    1116             : };
    1117             : 
    1118             : const char TiedAsmOperandTable[][3] = {
    1119             :   /* Tie0_1_1 */ { 0, 1, 1 },
    1120             :   /* Tie0_1_2 */ { 0, 1, 2 },
    1121             :   /* Tie0_1_5 */ { 0, 1, 5 },
    1122             :   /* Tie0_2_2 */ { 0, 2, 2 },
    1123             :   /* Tie0_3_3 */ { 0, 3, 3 },
    1124             :   /* Tie0_4_4 */ { 0, 4, 4 },
    1125             :   /* Tie0_5_5 */ { 0, 5, 5 },
    1126             :   /* Tie1_1_1 */ { 1, 1, 1 },
    1127             :   /* Tie1_2_2 */ { 1, 2, 2 },
    1128             : };
    1129             : 
    1130             : namespace {
    1131             : enum OperatorConversionKind {
    1132             :   CVT_Done,
    1133             :   CVT_Reg,
    1134             :   CVT_Tied,
    1135             :   CVT_95_Reg,
    1136             :   CVT_95_addVectorReg128Operands,
    1137             :   CVT_95_addVectorReg64Operands,
    1138             :   CVT_imm_95_16,
    1139             :   CVT_imm_95_24,
    1140             :   CVT_imm_95_0,
    1141             :   CVT_95_addAddSubImmNegOperands,
    1142             :   CVT_95_addAddSubImmOperands,
    1143             :   CVT_95_addRegOperands,
    1144             :   CVT_95_addShifterOperands,
    1145             :   CVT_95_addExtendOperands,
    1146             :   CVT_95_addExtend64Operands,
    1147             :   CVT_95_addImmOperands,
    1148             :   CVT_95_addAdrLabelOperands,
    1149             :   CVT_95_addAdrpLabelOperands,
    1150             :   CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_,
    1151             :   CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_,
    1152             :   CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_,
    1153             :   CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_,
    1154             :   CVT_95_addImm0_95_31Operands,
    1155             :   CVT_imm_95_31,
    1156             :   CVT_95_addImm0_95_63Operands,
    1157             :   CVT_imm_95_63,
    1158             :   CVT_95_addBranchTarget26Operands,
    1159             :   CVT_95_addCondCodeOperands,
    1160             :   CVT_95_addPCRelLabel19Operands,
    1161             :   CVT_95_addImm0_95_255Operands,
    1162             :   CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_,
    1163             :   CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_,
    1164             :   CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_,
    1165             :   CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_,
    1166             :   CVT_95_addImm0_95_65535Operands,
    1167             :   CVT_95_addImm0_95_15Operands,
    1168             :   CVT_imm_95_15,
    1169             :   CVT_regWZR,
    1170             :   CVT_regXZR,
    1171             :   CVT_imm_95_20,
    1172             :   CVT_95_addBarrierOperands,
    1173             :   CVT_95_addVectorIndexHOperands,
    1174             :   CVT_95_addVectorIndexSOperands,
    1175             :   CVT_95_addVectorIndexDOperands,
    1176             :   CVT_95_addVectorIndexBOperands,
    1177             :   CVT_95_addComplexRotationOddOperands,
    1178             :   CVT_95_addComplexRotationEvenOperands,
    1179             :   CVT_95_addImm1_95_16Operands,
    1180             :   CVT_95_addImm1_95_32Operands,
    1181             :   CVT_95_addImm1_95_64Operands,
    1182             :   CVT_95_addVectorRegLoOperands,
    1183             :   CVT_95_addFPImmOperands,
    1184             :   CVT_95_addVectorIndex1Operands,
    1185             :   CVT_95_addImm0_95_127Operands,
    1186             :   CVT_95_addVectorList128Operands_LT_4_GT_,
    1187             :   CVT_95_addVectorList64Operands_LT_4_GT_,
    1188             :   CVT_95_addVectorList128Operands_LT_1_GT_,
    1189             :   CVT_95_addVectorList64Operands_LT_1_GT_,
    1190             :   CVT_95_addVectorList128Operands_LT_3_GT_,
    1191             :   CVT_95_addVectorList64Operands_LT_3_GT_,
    1192             :   CVT_95_addVectorList128Operands_LT_2_GT_,
    1193             :   CVT_95_addVectorList64Operands_LT_2_GT_,
    1194             :   CVT_95_addSImm7s16Operands,
    1195             :   CVT_95_addSImm7s4Operands,
    1196             :   CVT_95_addSImm7s8Operands,
    1197             :   CVT_95_addUImm12OffsetOperands_LT_16_GT_,
    1198             :   CVT_95_addUImm12OffsetOperands_LT_2_GT_,
    1199             :   CVT_95_addUImm12OffsetOperands_LT_4_GT_,
    1200             :   CVT_95_addUImm12OffsetOperands_LT_8_GT_,
    1201             :   CVT_95_addUImm12OffsetOperands_LT_1_GT_,
    1202             :   CVT_95_addMemExtendOperands,
    1203             :   CVT_95_addMemExtend8Operands,
    1204             :   CVT_95_addSImm10s8Operands,
    1205             :   CVT_95_addMOVZMovAliasOperands_LT_0_GT_,
    1206             :   CVT_95_addMOVZMovAliasOperands_LT_16_GT_,
    1207             :   CVT_95_addMOVNMovAliasOperands_LT_0_GT_,
    1208             :   CVT_95_addMOVNMovAliasOperands_LT_16_GT_,
    1209             :   CVT_95_addMOVZMovAliasOperands_LT_32_GT_,
    1210             :   CVT_imm_95_32,
    1211             :   CVT_95_addMOVZMovAliasOperands_LT_48_GT_,
    1212             :   CVT_imm_95_48,
    1213             :   CVT_95_addMOVNMovAliasOperands_LT_32_GT_,
    1214             :   CVT_95_addMOVNMovAliasOperands_LT_48_GT_,
    1215             :   CVT_95_addSIMDImmType10Operands,
    1216             :   CVT_95_addMRSSystemRegisterOperands,
    1217             :   CVT_95_addMSRSystemRegisterOperands,
    1218             :   CVT_95_addSystemPStateFieldWithImm0_95_15Operands,
    1219             :   CVT_95_addSystemPStateFieldWithImm0_95_1Operands,
    1220             :   CVT_95_addImm0_95_1Operands,
    1221             :   CVT_95_addPrefetchOperands,
    1222             :   CVT_95_addPSBHintOperands,
    1223             :   CVT_regLR,
    1224             :   CVT_95_addImm1_95_8Operands,
    1225             :   CVT_imm_95_4,
    1226             :   CVT_imm_95_5,
    1227             :   CVT_95_addImm0_95_7Operands,
    1228             :   CVT_imm_95_7,
    1229             :   CVT_95_addSysCROperands,
    1230             :   CVT_95_addBranchTarget14Operands,
    1231             :   CVT_95_addImm32_95_63Operands,
    1232             :   CVT_95_addGPR32as64Operands,
    1233             :   CVT_imm_95_2,
    1234             :   CVT_imm_95_3,
    1235             :   CVT_imm_95_1,
    1236             :   CVT_NUM_CONVERTERS
    1237             : };
    1238             : 
    1239             : enum InstructionConversionKind {
    1240             :   Convert__Reg1_0__Reg1_1,
    1241             :   Convert__VectorReg1281_1__VectorReg1281_2,
    1242             :   Convert__VectorReg641_1__VectorReg641_2,
    1243             :   Convert__VectorReg1281_0__VectorReg1281_2,
    1244             :   Convert__VectorReg641_0__VectorReg641_2,
    1245             :   Convert__Reg1_0__Reg1_1__Reg1_2,
    1246             :   Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16,
    1247             :   Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24,
    1248             :   Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
    1249             :   Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2,
    1250             :   Convert__Reg1_0__Reg1_1__AddSubImm2_2,
    1251             :   Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2,
    1252             :   Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2,
    1253             :   Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2,
    1254             :   Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2,
    1255             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3,
    1256             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3,
    1257             :   Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3,
    1258             :   Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3,
    1259             :   Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3,
    1260             :   Convert__Reg1_0__Reg1_1__Reg1_2__Extend641_3,
    1261             :   Convert__Reg1_0__Reg1_1__Reg1_2__ExtendLSL641_3,
    1262             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4,
    1263             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4,
    1264             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5,
    1265             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5,
    1266             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5,
    1267             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorBReg1_5,
    1268             :   Convert__VectorReg641_1__VectorReg1281_2__VectorReg1281_3,
    1269             :   Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4,
    1270             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3,
    1271             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4,
    1272             :   Convert__Reg1_1__VectorReg1281_2,
    1273             :   Convert__Reg1_0__VectorReg1281_1,
    1274             :   Convert__Reg1_0__Reg1_1__SImm61_2,
    1275             :   Convert__Reg1_1__VectorReg641_2,
    1276             :   Convert__Reg1_0__VectorReg641_1,
    1277             :   Convert__Reg1_0__AdrLabel1_1,
    1278             :   Convert__Reg1_0__AdrpLabel1_1,
    1279             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2,
    1280             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2,
    1281             :   Convert__Reg1_0__Reg1_1__LogicalImm321_2,
    1282             :   Convert__Reg1_0__Reg1_1__LogicalImm641_2,
    1283             :   Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2,
    1284             :   Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2,
    1285             :   Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2,
    1286             :   Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2,
    1287             :   Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3,
    1288             :   Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3,
    1289             :   Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31,
    1290             :   Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63,
    1291             :   Convert__Reg1_0,
    1292             :   Convert_NoOperands,
    1293             :   Convert__BranchTarget261_0,
    1294             :   Convert__CondCode1_1__PCRelLabel191_2,
    1295             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_311_2__Imm0_311_3,
    1296             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2__Imm0_631_3,
    1297             :   Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__imm_95_0,
    1298             :   Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__imm_95_0,
    1299             :   Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2,
    1300             :   Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2,
    1301             :   Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__imm_95_0,
    1302             :   Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__imm_95_0,
    1303             :   Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2,
    1304             :   Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2,
    1305             :   Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2,
    1306             :   Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2,
    1307             :   Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3,
    1308             :   Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1309             :   Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3,
    1310             :   Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1311             :   Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3,
    1312             :   Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1313             :   Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3,
    1314             :   Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1315             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3,
    1316             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4,
    1317             :   Convert__Imm0_655351_0,
    1318             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3,
    1319             :   Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3,
    1320             :   Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3,
    1321             :   Convert__Reg1_0__PCRelLabel191_1,
    1322             :   Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3,
    1323             :   Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3,
    1324             :   Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2,
    1325             :   Convert__imm_95_15,
    1326             :   Convert__Imm0_151_0,
    1327             :   Convert__Reg1_0__Reg1_2__Reg1_1,
    1328             :   Convert__VectorReg1281_1__VectorReg1281_3__VectorReg1281_2,
    1329             :   Convert__VectorReg641_1__VectorReg641_3__VectorReg641_2,
    1330             :   Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2,
    1331             :   Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2,
    1332             :   Convert__regWZR__Reg1_0__Reg1_1__imm_95_16,
    1333             :   Convert__regXZR__Reg1_0__Reg1_1__imm_95_24,
    1334             :   Convert__regWZR__Reg1_0__Reg1_1__imm_95_0,
    1335             :   Convert__regWZR__Reg1_0__AddSubImmNeg2_1,
    1336             :   Convert__regWZR__Reg1_0__AddSubImm2_1,
    1337             :   Convert__regXZR__Reg1_0__Reg1_1__imm_95_0,
    1338             :   Convert__regXZR__Reg1_0__AddSubImmNeg2_1,
    1339             :   Convert__regXZR__Reg1_0__AddSubImm2_1,
    1340             :   Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2,
    1341             :   Convert__regWZR__Reg1_0__Reg1_1__Extend1_2,
    1342             :   Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2,
    1343             :   Convert__regXZR__Reg1_0__Reg1_1__Extend1_2,
    1344             :   Convert__regXZR__Reg1_0__Reg1_1__ExtendLSL641_2,
    1345             :   Convert__imm_95_20,
    1346             :   Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3,
    1347             :   Convert__Reg1_0__regWZR__regWZR__CondCode1_1,
    1348             :   Convert__Reg1_0__regXZR__regXZR__CondCode1_1,
    1349             :   Convert__imm_95_0,
    1350             :   Convert__Barrier1_0,
    1351             :   Convert__SVEVectorHReg1_0__Reg1_1,
    1352             :   Convert__SVEVectorSReg1_0__Reg1_1,
    1353             :   Convert__SVEVectorDReg1_0__Reg1_1,
    1354             :   Convert__SVEVectorBReg1_0__Reg1_1,
    1355             :   Convert__VectorReg1281_1__Reg1_2,
    1356             :   Convert__VectorReg641_1__Reg1_2,
    1357             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_2,
    1358             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_2,
    1359             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_2,
    1360             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_2,
    1361             :   Convert__VectorReg1281_0__Reg1_2,
    1362             :   Convert__VectorReg641_0__Reg1_2,
    1363             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexB1_3,
    1364             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexD1_3,
    1365             :   Convert__VectorReg641_1__VectorReg1281_2__VectorIndexS1_3,
    1366             :   Convert__VectorReg641_1__VectorReg1281_2__VectorIndexH1_3,
    1367             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexS1_3,
    1368             :   Convert__VectorReg641_1__VectorReg1281_2__VectorIndexB1_3,
    1369             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexH1_3,
    1370             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_3,
    1371             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_3,
    1372             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_3,
    1373             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_3,
    1374             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexB1_4,
    1375             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexD1_4,
    1376             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexS1_4,
    1377             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexH1_4,
    1378             :   Convert__VectorReg641_0__VectorReg1281_2__VectorIndexS1_4,
    1379             :   Convert__VectorReg641_0__VectorReg1281_2__VectorIndexH1_4,
    1380             :   Convert__VectorReg641_0__VectorReg1281_2__VectorIndexB1_4,
    1381             :   Convert__imm_95_16,
    1382             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__Imm1_4,
    1383             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__Imm1_4,
    1384             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__Imm1_6,
    1385             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__Imm1_6,
    1386             :   Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_311_3,
    1387             :   Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_631_3,
    1388             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__ComplexRotationOdd1_4,
    1389             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__ComplexRotationOdd1_4,
    1390             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6,
    1391             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__ComplexRotationOdd1_6,
    1392             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__ComplexRotationEven1_4,
    1393             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3__ComplexRotationEven1_4,
    1394             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexD1_4__ComplexRotationEven1_5,
    1395             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4__ComplexRotationEven1_5,
    1396             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4__ComplexRotationEven1_5,
    1397             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6,
    1398             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4__ComplexRotationEven1_6,
    1399             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7,
    1400             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6__ComplexRotationEven1_7,
    1401             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7,
    1402             :   Convert__VectorReg1281_0__VectorReg641_2,
    1403             :   Convert__VectorReg641_0__VectorReg1281_2,
    1404             :   Convert__Reg1_0__Reg1_1__Imm1_161_2,
    1405             :   Convert__Reg1_0__Reg1_1__Imm1_321_2,
    1406             :   Convert__Reg1_0__Reg1_1__Imm1_641_2,
    1407             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm1_641_3,
    1408             :   Convert__VectorReg641_1__VectorReg641_2__Imm1_321_3,
    1409             :   Convert__VectorReg641_1__VectorReg641_2__Imm1_161_3,
    1410             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm1_321_3,
    1411             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm1_161_3,
    1412             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm1_641_4,
    1413             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm1_321_4,
    1414             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm1_161_4,
    1415             :   Convert__VectorReg641_0__VectorReg641_2__Imm1_321_4,
    1416             :   Convert__VectorReg641_0__VectorReg641_2__Imm1_161_4,
    1417             :   Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
    1418             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4,
    1419             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4,
    1420             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4,
    1421             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4,
    1422             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__VectorIndexH1_4,
    1423             :   Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3__VectorIndexD1_4,
    1424             :   Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorRegLo1_3__VectorIndexH1_4,
    1425             :   Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3__VectorIndexS1_4,
    1426             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorRegLo1_2__VectorIndexH1_4,
    1427             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2__VectorIndexS1_4,
    1428             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2__VectorIndexD1_4,
    1429             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6,
    1430             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6,
    1431             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorRegLo1_4__VectorIndexH1_6,
    1432             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6,
    1433             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6,
    1434             :   Convert__Reg1_0__FPImm1_1,
    1435             :   Convert__VectorReg1281_1__FPImm1_2,
    1436             :   Convert__VectorReg641_1__FPImm1_2,
    1437             :   Convert__Reg1_0__regWZR,
    1438             :   Convert__Reg1_0__regXZR,
    1439             :   Convert__VectorReg1281_0__FPImm1_2,
    1440             :   Convert__VectorReg641_0__FPImm1_2,
    1441             :   Convert__Reg1_1__VectorReg1281_2__VectorIndex11_3,
    1442             :   Convert__VectorReg1281_1__Reg1_3__VectorIndex11_2,
    1443             :   Convert__Reg1_0__VectorReg1281_1__VectorIndex11_3,
    1444             :   Convert__VectorReg1281_0__Reg1_3__VectorIndex11_2,
    1445             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4,
    1446             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4,
    1447             :   Convert__VectorReg641_1__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4,
    1448             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4,
    1449             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorRegLo1_3__VectorIndexH1_4,
    1450             :   Convert__Reg1_1__Reg1_2__VectorReg1281_3__VectorIndexD1_4,
    1451             :   Convert__Reg1_1__Reg1_2__VectorRegLo1_3__VectorIndexH1_4,
    1452             :   Convert__Reg1_1__Reg1_2__VectorReg1281_3__VectorIndexS1_4,
    1453             :   Convert__Reg1_0__Reg1_1__VectorRegLo1_2__VectorIndexH1_4,
    1454             :   Convert__Reg1_0__Reg1_1__VectorReg1281_2__VectorIndexS1_4,
    1455             :   Convert__Reg1_0__Reg1_1__VectorReg1281_2__VectorIndexD1_4,
    1456             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6,
    1457             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6,
    1458             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorRegLo1_4__VectorIndexH1_6,
    1459             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6,
    1460             :   Convert__VectorReg641_0__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6,
    1461             :   Convert__Imm0_1271_0,
    1462             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_3,
    1463             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_3,
    1464             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_3,
    1465             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_3,
    1466             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexB1_2__Reg1_3,
    1467             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexD1_2__Reg1_3,
    1468             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexH1_2__Reg1_3,
    1469             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexS1_2__Reg1_3,
    1470             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexB1_2__VectorReg1281_3__VectorIndexB1_4,
    1471             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexD1_2__VectorReg1281_3__VectorIndexD1_4,
    1472             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexH1_2__VectorReg1281_3__VectorIndexH1_4,
    1473             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexS1_2__VectorReg1281_3__VectorIndexS1_4,
    1474             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexB1_2__VectorReg1281_3__VectorIndexB1_5,
    1475             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexD1_2__VectorReg1281_3__VectorIndexD1_5,
    1476             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexH1_2__VectorReg1281_3__VectorIndexH1_5,
    1477             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexS1_2__VectorReg1281_3__VectorIndexS1_5,
    1478             :   Convert__TypedVectorList4_16b1_0__Reg1_2,
    1479             :   Convert__TypedVectorList4_1d1_0__Reg1_2,
    1480             :   Convert__TypedVectorList4_2d1_0__Reg1_2,
    1481             :   Convert__TypedVectorList4_2s1_0__Reg1_2,
    1482             :   Convert__TypedVectorList4_4h1_0__Reg1_2,
    1483             :   Convert__TypedVectorList4_4s1_0__Reg1_2,
    1484             :   Convert__TypedVectorList4_8b1_0__Reg1_2,
    1485             :   Convert__TypedVectorList4_8h1_0__Reg1_2,
    1486             :   Convert__TypedVectorList1_16b1_0__Reg1_2,
    1487             :   Convert__TypedVectorList1_1d1_0__Reg1_2,
    1488             :   Convert__TypedVectorList1_2d1_0__Reg1_2,
    1489             :   Convert__TypedVectorList1_2s1_0__Reg1_2,
    1490             :   Convert__TypedVectorList1_4h1_0__Reg1_2,
    1491             :   Convert__TypedVectorList1_4s1_0__Reg1_2,
    1492             :   Convert__TypedVectorList1_8b1_0__Reg1_2,
    1493             :   Convert__TypedVectorList1_8h1_0__Reg1_2,
    1494             :   Convert__TypedVectorList3_16b1_0__Reg1_2,
    1495             :   Convert__TypedVectorList3_1d1_0__Reg1_2,
    1496             :   Convert__TypedVectorList3_2d1_0__Reg1_2,
    1497             :   Convert__TypedVectorList3_2s1_0__Reg1_2,
    1498             :   Convert__TypedVectorList3_4h1_0__Reg1_2,
    1499             :   Convert__TypedVectorList3_4s1_0__Reg1_2,
    1500             :   Convert__TypedVectorList3_8b1_0__Reg1_2,
    1501             :   Convert__TypedVectorList3_8h1_0__Reg1_2,
    1502             :   Convert__TypedVectorList2_16b1_0__Reg1_2,
    1503             :   Convert__TypedVectorList2_1d1_0__Reg1_2,
    1504             :   Convert__TypedVectorList2_2d1_0__Reg1_2,
    1505             :   Convert__TypedVectorList2_2s1_0__Reg1_2,
    1506             :   Convert__TypedVectorList2_4h1_0__Reg1_2,
    1507             :   Convert__TypedVectorList2_4s1_0__Reg1_2,
    1508             :   Convert__TypedVectorList2_8b1_0__Reg1_2,
    1509             :   Convert__TypedVectorList2_8h1_0__Reg1_2,
    1510             :   Convert__VecListFour1281_1__Reg1_3,
    1511             :   Convert__VecListOne1281_1__Reg1_3,
    1512             :   Convert__VecListThree1281_1__Reg1_3,
    1513             :   Convert__VecListTwo1281_1__Reg1_3,
    1514             :   Convert__VecListFour641_1__Reg1_3,
    1515             :   Convert__VecListOne641_1__Reg1_3,
    1516             :   Convert__VecListThree641_1__Reg1_3,
    1517             :   Convert__VecListTwo641_1__Reg1_3,
    1518             :   Convert__Reg1_2__TypedVectorList4_16b1_0__Tie0_3_3__regXZR,
    1519             :   Convert__Reg1_2__TypedVectorList4_16b1_0__Tie0_3_3__Reg1_4,
    1520             :   Convert__Reg1_2__TypedVectorList4_1d1_0__Tie0_3_3__regXZR,
    1521             :   Convert__Reg1_2__TypedVectorList4_1d1_0__Tie0_3_3__Reg1_4,
    1522             :   Convert__Reg1_2__TypedVectorList4_2d1_0__Tie0_3_3__regXZR,
    1523             :   Convert__Reg1_2__TypedVectorList4_2d1_0__Tie0_3_3__Reg1_4,
    1524             :   Convert__Reg1_2__TypedVectorList4_2s1_0__Tie0_3_3__regXZR,
    1525             :   Convert__Reg1_2__TypedVectorList4_2s1_0__Tie0_3_3__Reg1_4,
    1526             :   Convert__Reg1_2__TypedVectorList4_4h1_0__Tie0_3_3__regXZR,
    1527             :   Convert__Reg1_2__TypedVectorList4_4h1_0__Tie0_3_3__Reg1_4,
    1528             :   Convert__Reg1_2__TypedVectorList4_4s1_0__Tie0_3_3__regXZR,
    1529             :   Convert__Reg1_2__TypedVectorList4_4s1_0__Tie0_3_3__Reg1_4,
    1530             :   Convert__Reg1_2__TypedVectorList4_8b1_0__Tie0_3_3__regXZR,
    1531             :   Convert__Reg1_2__TypedVectorList4_8b1_0__Tie0_3_3__Reg1_4,
    1532             :   Convert__Reg1_2__TypedVectorList4_8h1_0__Tie0_3_3__regXZR,
    1533             :   Convert__Reg1_2__TypedVectorList4_8h1_0__Tie0_3_3__Reg1_4,
    1534             :   Convert__Reg1_2__TypedVectorList1_16b1_0__Tie0_3_3__regXZR,
    1535             :   Convert__Reg1_2__TypedVectorList1_16b1_0__Tie0_3_3__Reg1_4,
    1536             :   Convert__Reg1_2__TypedVectorList1_1d1_0__Tie0_3_3__regXZR,
    1537             :   Convert__Reg1_2__TypedVectorList1_1d1_0__Tie0_3_3__Reg1_4,
    1538             :   Convert__Reg1_2__TypedVectorList1_2d1_0__Tie0_3_3__regXZR,
    1539             :   Convert__Reg1_2__TypedVectorList1_2d1_0__Tie0_3_3__Reg1_4,
    1540             :   Convert__Reg1_2__TypedVectorList1_2s1_0__Tie0_3_3__regXZR,
    1541             :   Convert__Reg1_2__TypedVectorList1_2s1_0__Tie0_3_3__Reg1_4,
    1542             :   Convert__Reg1_2__TypedVectorList1_4h1_0__Tie0_3_3__regXZR,
    1543             :   Convert__Reg1_2__TypedVectorList1_4h1_0__Tie0_3_3__Reg1_4,
    1544             :   Convert__Reg1_2__TypedVectorList1_4s1_0__Tie0_3_3__regXZR,
    1545             :   Convert__Reg1_2__TypedVectorList1_4s1_0__Tie0_3_3__Reg1_4,
    1546             :   Convert__Reg1_2__TypedVectorList1_8b1_0__Tie0_3_3__regXZR,
    1547             :   Convert__Reg1_2__TypedVectorList1_8b1_0__Tie0_3_3__Reg1_4,
    1548             :   Convert__Reg1_2__TypedVectorList1_8h1_0__Tie0_3_3__regXZR,
    1549             :   Convert__Reg1_2__TypedVectorList1_8h1_0__Tie0_3_3__Reg1_4,
    1550             :   Convert__TypedVectorList1_0b1_0__Tie0_1_1__VectorIndexB1_1__Reg1_3,
    1551             :   Convert__TypedVectorList1_0d1_0__Tie0_1_1__VectorIndexD1_1__Reg1_3,
    1552             :   Convert__TypedVectorList1_0h1_0__Tie0_1_1__VectorIndexH1_1__Reg1_3,
    1553             :   Convert__TypedVectorList1_0s1_0__Tie0_1_1__VectorIndexS1_1__Reg1_3,
    1554             :   Convert__Reg1_2__TypedVectorList3_16b1_0__Tie0_3_3__regXZR,
    1555             :   Convert__Reg1_2__TypedVectorList3_16b1_0__Tie0_3_3__Reg1_4,
    1556             :   Convert__Reg1_2__TypedVectorList3_1d1_0__Tie0_3_3__regXZR,
    1557             :   Convert__Reg1_2__TypedVectorList3_1d1_0__Tie0_3_3__Reg1_4,
    1558             :   Convert__Reg1_2__TypedVectorList3_2d1_0__Tie0_3_3__regXZR,
    1559             :   Convert__Reg1_2__TypedVectorList3_2d1_0__Tie0_3_3__Reg1_4,
    1560             :   Convert__Reg1_2__TypedVectorList3_2s1_0__Tie0_3_3__regXZR,
    1561             :   Convert__Reg1_2__TypedVectorList3_2s1_0__Tie0_3_3__Reg1_4,
    1562             :   Convert__Reg1_2__TypedVectorList3_4h1_0__Tie0_3_3__regXZR,
    1563             :   Convert__Reg1_2__TypedVectorList3_4h1_0__Tie0_3_3__Reg1_4,
    1564             :   Convert__Reg1_2__TypedVectorList3_4s1_0__Tie0_3_3__regXZR,
    1565             :   Convert__Reg1_2__TypedVectorList3_4s1_0__Tie0_3_3__Reg1_4,
    1566             :   Convert__Reg1_2__TypedVectorList3_8b1_0__Tie0_3_3__regXZR,
    1567             :   Convert__Reg1_2__TypedVectorList3_8b1_0__Tie0_3_3__Reg1_4,
    1568             :   Convert__Reg1_2__TypedVectorList3_8h1_0__Tie0_3_3__regXZR,
    1569             :   Convert__Reg1_2__TypedVectorList3_8h1_0__Tie0_3_3__Reg1_4,
    1570             :   Convert__Reg1_2__TypedVectorList2_16b1_0__Tie0_3_3__regXZR,
    1571             :   Convert__Reg1_2__TypedVectorList2_16b1_0__Tie0_3_3__Reg1_4,
    1572             :   Convert__Reg1_2__TypedVectorList2_1d1_0__Tie0_3_3__regXZR,
    1573             :   Convert__Reg1_2__TypedVectorList2_1d1_0__Tie0_3_3__Reg1_4,
    1574             :   Convert__Reg1_2__TypedVectorList2_2d1_0__Tie0_3_3__regXZR,
    1575             :   Convert__Reg1_2__TypedVectorList2_2d1_0__Tie0_3_3__Reg1_4,
    1576             :   Convert__Reg1_2__TypedVectorList2_2s1_0__Tie0_3_3__regXZR,
    1577             :   Convert__Reg1_2__TypedVectorList2_2s1_0__Tie0_3_3__Reg1_4,
    1578             :   Convert__Reg1_2__TypedVectorList2_4h1_0__Tie0_3_3__regXZR,
    1579             :   Convert__Reg1_2__TypedVectorList2_4h1_0__Tie0_3_3__Reg1_4,
    1580             :   Convert__Reg1_2__TypedVectorList2_4s1_0__Tie0_3_3__regXZR,
    1581             :   Convert__Reg1_2__TypedVectorList2_4s1_0__Tie0_3_3__Reg1_4,
    1582             :   Convert__Reg1_2__TypedVectorList2_8b1_0__Tie0_3_3__regXZR,
    1583             :   Convert__Reg1_2__TypedVectorList2_8b1_0__Tie0_3_3__Reg1_4,
    1584             :   Convert__Reg1_2__TypedVectorList2_8h1_0__Tie0_3_3__regXZR,
    1585             :   Convert__Reg1_2__TypedVectorList2_8h1_0__Tie0_3_3__Reg1_4,
    1586             :   Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR,
    1587             :   Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5,
    1588             :   Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__regXZR,
    1589             :   Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__Reg1_5,
    1590             :   Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR,
    1591             :   Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5,
    1592             :   Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR,
    1593             :   Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5,
    1594             :   Convert__Reg1_3__VecListFour641_1__Tie0_4_4__regXZR,
    1595             :   Convert__Reg1_3__VecListFour641_1__Tie0_4_4__Reg1_5,
    1596             :   Convert__Reg1_3__VecListOne641_1__Tie0_4_4__regXZR,
    1597             :   Convert__Reg1_3__VecListOne641_1__Tie0_4_4__Reg1_5,
    1598             :   Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR,
    1599             :   Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5,
    1600             :   Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__regXZR,
    1601             :   Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__Reg1_5,
    1602             :   Convert__VecListOne1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4,
    1603             :   Convert__VecListOne1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4,
    1604             :   Convert__VecListOne1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4,
    1605             :   Convert__VecListOne1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4,
    1606             :   Convert__Reg1_3__TypedVectorList1_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR,
    1607             :   Convert__Reg1_3__TypedVectorList1_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1608             :   Convert__Reg1_3__TypedVectorList1_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR,
    1609             :   Convert__Reg1_3__TypedVectorList1_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1610             :   Convert__Reg1_3__TypedVectorList1_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR,
    1611             :   Convert__Reg1_3__TypedVectorList1_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1612             :   Convert__Reg1_3__TypedVectorList1_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR,
    1613             :   Convert__Reg1_3__TypedVectorList1_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1614             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR,
    1615             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1616             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR,
    1617             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1618             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR,
    1619             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1620             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR,
    1621             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1622             :   Convert__TypedVectorList2_0b1_0__Tie0_1_1__VectorIndexB1_1__Reg1_3,
    1623             :   Convert__TypedVectorList2_0d1_0__Tie0_1_1__VectorIndexD1_1__Reg1_3,
    1624             :   Convert__TypedVectorList2_0h1_0__Tie0_1_1__VectorIndexH1_1__Reg1_3,
    1625             :   Convert__TypedVectorList2_0s1_0__Tie0_1_1__VectorIndexS1_1__Reg1_3,
    1626             :   Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4,
    1627             :   Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4,
    1628             :   Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4,
    1629             :   Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4,
    1630             :   Convert__Reg1_3__TypedVectorList2_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR,
    1631             :   Convert__Reg1_3__TypedVectorList2_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1632             :   Convert__Reg1_3__TypedVectorList2_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR,
    1633             :   Convert__Reg1_3__TypedVectorList2_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1634             :   Convert__Reg1_3__TypedVectorList2_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR,
    1635             :   Convert__Reg1_3__TypedVectorList2_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1636             :   Convert__Reg1_3__TypedVectorList2_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR,
    1637             :   Convert__Reg1_3__TypedVectorList2_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1638             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR,
    1639             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1640             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR,
    1641             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1642             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR,
    1643             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1644             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR,
    1645             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1646             :   Convert__TypedVectorList3_0b1_0__Tie0_1_1__VectorIndexB1_1__Reg1_3,
    1647             :   Convert__TypedVectorList3_0d1_0__Tie0_1_1__VectorIndexD1_1__Reg1_3,
    1648             :   Convert__TypedVectorList3_0h1_0__Tie0_1_1__VectorIndexH1_1__Reg1_3,
    1649             :   Convert__TypedVectorList3_0s1_0__Tie0_1_1__VectorIndexS1_1__Reg1_3,
    1650             :   Convert__VecListThree1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4,
    1651             :   Convert__VecListThree1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4,
    1652             :   Convert__VecListThree1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4,
    1653             :   Convert__VecListThree1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4,
    1654             :   Convert__Reg1_3__TypedVectorList3_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR,
    1655             :   Convert__Reg1_3__TypedVectorList3_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1656             :   Convert__Reg1_3__TypedVectorList3_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR,
    1657             :   Convert__Reg1_3__TypedVectorList3_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1658             :   Convert__Reg1_3__TypedVectorList3_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR,
    1659             :   Convert__Reg1_3__TypedVectorList3_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1660             :   Convert__Reg1_3__TypedVectorList3_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR,
    1661             :   Convert__Reg1_3__TypedVectorList3_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1662             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR,
    1663             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1664             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR,
    1665             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1666             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR,
    1667             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1668             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR,
    1669             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1670             :   Convert__TypedVectorList4_0b1_0__Tie0_1_1__VectorIndexB1_1__Reg1_3,
    1671             :   Convert__TypedVectorList4_0d1_0__Tie0_1_1__VectorIndexD1_1__Reg1_3,
    1672             :   Convert__TypedVectorList4_0h1_0__Tie0_1_1__VectorIndexH1_1__Reg1_3,
    1673             :   Convert__TypedVectorList4_0s1_0__Tie0_1_1__VectorIndexS1_1__Reg1_3,
    1674             :   Convert__VecListFour1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4,
    1675             :   Convert__VecListFour1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4,
    1676             :   Convert__VecListFour1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4,
    1677             :   Convert__VecListFour1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4,
    1678             :   Convert__Reg1_3__TypedVectorList4_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR,
    1679             :   Convert__Reg1_3__TypedVectorList4_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1680             :   Convert__Reg1_3__TypedVectorList4_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR,
    1681             :   Convert__Reg1_3__TypedVectorList4_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1682             :   Convert__Reg1_3__TypedVectorList4_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR,
    1683             :   Convert__Reg1_3__TypedVectorList4_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1684             :   Convert__Reg1_3__TypedVectorList4_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR,
    1685             :   Convert__Reg1_3__TypedVectorList4_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1686             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR,
    1687             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1688             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR,
    1689             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1690             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR,
    1691             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1692             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR,
    1693             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1694             :   Convert__Reg1_1__Reg1_0__Reg1_3,
    1695             :   Convert__Reg1_0__GPR64sp01_2,
    1696             :   Convert__Reg1_0__Reg1_1__GPR64sp01_3,
    1697             :   Convert__Reg1_0__Reg1_1__Reg1_3__imm_95_0,
    1698             :   Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s161_4,
    1699             :   Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4,
    1700             :   Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s81_4,
    1701             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s161_5,
    1702             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5,
    1703             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_5,
    1704             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s161_4,
    1705             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4,
    1706             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_4,
    1707             :   Convert__Reg1_0__Reg1_2__imm_95_0,
    1708             :   Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_4,
    1709             :   Convert__Reg1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    1710             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB1281_3,
    1711             :   Convert__Reg1_0__Reg1_2__UImm12Offset161_3,
    1712             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB161_3,
    1713             :   Convert__Reg1_0__Reg1_2__UImm12Offset21_3,
    1714             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB321_3,
    1715             :   Convert__Reg1_0__Reg1_2__UImm12Offset41_3,
    1716             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB641_3,
    1717             :   Convert__Reg1_0__Reg1_2__UImm12Offset81_3,
    1718             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB81_3,
    1719             :   Convert__Reg1_0__Reg1_2__UImm12Offset11_3,
    1720             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend1282_4,
    1721             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend1282_4,
    1722             :   Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_3,
    1723             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend162_4,
    1724             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend162_4,
    1725             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend322_4,
    1726             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend322_4,
    1727             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend642_4,
    1728             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend642_4,
    1729             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend82_4,
    1730             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend82_4,
    1731             :   Convert__Reg1_0__Reg1_2__SImm10s81_3,
    1732             :   Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm10s81_3,
    1733             :   Convert__Reg1_0__Reg1_2__SImm91_3,
    1734             :   Convert__Reg1_0__Reg1_1__Reg1_2__regWZR,
    1735             :   Convert__Reg1_0__Reg1_1__Reg1_2__regXZR,
    1736             :   Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0,
    1737             :   Convert__Reg1_0__regWZR__Reg1_1__imm_95_0,
    1738             :   Convert__Reg1_0__MOVZ32_lsl0MovAlias1_1__imm_95_0,
    1739             :   Convert__Reg1_0__MOVZ32_lsl16MovAlias1_1__imm_95_16,
    1740             :   Convert__Reg1_0__MOVN32_lsl0MovAlias1_1__imm_95_0,
    1741             :   Convert__Reg1_0__MOVN32_lsl16MovAlias1_1__imm_95_16,
    1742             :   Convert__Reg1_0__regWZR__LogicalImm321_1,
    1743             :   Convert__Reg1_0__regXZR__Reg1_1__imm_95_0,
    1744             :   Convert__Reg1_0__MOVZ64_lsl0MovAlias1_1__imm_95_0,
    1745             :   Convert__Reg1_0__MOVZ64_lsl16MovAlias1_1__imm_95_16,
    1746             :   Convert__Reg1_0__MOVZ64_lsl32MovAlias1_1__imm_95_32,
    1747             :   Convert__Reg1_0__MOVZ64_lsl48MovAlias1_1__imm_95_48,
    1748             :   Convert__Reg1_0__MOVN64_lsl0MovAlias1_1__imm_95_0,
    1749             :   Convert__Reg1_0__MOVN64_lsl16MovAlias1_1__imm_95_16,
    1750             :   Convert__Reg1_0__MOVN64_lsl32MovAlias1_1__imm_95_32,
    1751             :   Convert__Reg1_0__MOVN64_lsl48MovAlias1_1__imm_95_48,
    1752             :   Convert__Reg1_0__regXZR__LogicalImm641_1,
    1753             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_2,
    1754             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg641_2,
    1755             :   Convert__Reg1_1__VectorReg1281_2__VectorIndexD1_3,
    1756             :   Convert__Reg1_1__VectorReg1281_2__VectorIndexS1_3,
    1757             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_2,
    1758             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg641_2,
    1759             :   Convert__Reg1_0__SIMDImmType101_1,
    1760             :   Convert__VectorReg1281_1__Imm0_2551_2,
    1761             :   Convert__VectorReg1281_1__SIMDImmType101_2,
    1762             :   Convert__VectorReg641_1__Imm0_2551_2__imm_95_0,
    1763             :   Convert__VectorReg1281_1__Imm0_2551_2__imm_95_0,
    1764             :   Convert__VectorReg641_1__Imm0_2551_2,
    1765             :   Convert__VectorReg1281_0__Imm0_2551_2,
    1766             :   Convert__VectorReg1281_0__SIMDImmType101_2,
    1767             :   Convert__VectorReg1281_0__Imm0_2551_2__imm_95_0,
    1768             :   Convert__VectorReg641_0__Imm0_2551_2__imm_95_0,
    1769             :   Convert__VectorReg641_0__Imm0_2551_2,
    1770             :   Convert__VectorReg641_1__Imm0_2551_2__LogicalVecShifter1_3,
    1771             :   Convert__VectorReg641_1__Imm0_2551_2__MoveVecShifter1_3,
    1772             :   Convert__VectorReg641_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1773             :   Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecShifter1_3,
    1774             :   Convert__VectorReg1281_1__Imm0_2551_2__MoveVecShifter1_3,
    1775             :   Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1776             :   Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecShifter1_3,
    1777             :   Convert__VectorReg1281_0__Imm0_2551_2__MoveVecShifter1_3,
    1778             :   Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1779             :   Convert__VectorReg641_0__Imm0_2551_2__LogicalVecShifter1_3,
    1780             :   Convert__VectorReg641_0__Imm0_2551_2__MoveVecShifter1_3,
    1781             :   Convert__VectorReg641_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1782             :   Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0,
    1783             :   Convert__Reg1_0__Tie0_1_1__MovKSymbolG01_1__imm_95_0,
    1784             :   Convert__Reg1_0__Tie0_1_1__MovKSymbolG11_1__imm_95_16,
    1785             :   Convert__Reg1_0__Tie0_1_1__MovKSymbolG21_1__imm_95_32,
    1786             :   Convert__Reg1_0__Tie0_1_1__MovKSymbolG31_1__imm_95_48,
    1787             :   Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm32Shifter1_2,
    1788             :   Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm64Shifter1_2,
    1789             :   Convert__Reg1_0__Imm0_655351_1__imm_95_0,
    1790             :   Convert__Reg1_0__MovZSymbolG01_1__imm_95_0,
    1791             :   Convert__Reg1_0__MovZSymbolG11_1__imm_95_16,
    1792             :   Convert__Reg1_0__MovZSymbolG21_1__imm_95_32,
    1793             :   Convert__Reg1_0__MovZSymbolG31_1__imm_95_48,
    1794             :   Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2,
    1795             :   Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2,
    1796             :   Convert__Reg1_0__MRSSystemRegister1_1,
    1797             :   Convert__MSRSystemRegister1_0__Reg1_1,
    1798             :   Convert__SystemPStateFieldWithImm0_151_0__Imm0_151_1,
    1799             :   Convert__SystemPStateFieldWithImm0_11_0__Imm0_11_1,
    1800             :   Convert__Reg1_0__regWZR__Reg1_1__LogicalShifter321_2,
    1801             :   Convert__Reg1_0__regXZR__Reg1_1__LogicalShifter641_2,
    1802             :   Convert__Reg1_0__regWZR__Reg1_1__ArithmeticShifter321_2,
    1803             :   Convert__Reg1_0__regXZR__Reg1_1__ArithmeticShifter641_2,
    1804             :   Convert__Reg1_0__regWZR__Reg1_1,
    1805             :   Convert__Reg1_0__regXZR__Reg1_1,
    1806             :   Convert__VectorReg1281_1__VectorReg641_2__VectorReg641_3,
    1807             :   Convert__VectorReg1281_0__VectorReg641_2__VectorReg641_4,
    1808             :   Convert__Prefetch1_0__PCRelLabel191_1,
    1809             :   Convert__Prefetch1_0__Reg1_2__imm_95_0,
    1810             :   Convert__Prefetch1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    1811             :   Convert__Prefetch1_0__Reg1_2__UImm12Offset81_3,
    1812             :   Convert__Prefetch1_0__Reg1_2__Reg1_3__MemWExtend642_4,
    1813             :   Convert__Prefetch1_0__Reg1_2__Reg1_3__MemXExtend642_4,
    1814             :   Convert__Prefetch1_0__Reg1_2__SImm91_3,
    1815             :   Convert__PSBHint1_0,
    1816             :   Convert__SVEPredicateHReg1_0__imm_95_31,
    1817             :   Convert__SVEPredicateSReg1_0__imm_95_31,
    1818             :   Convert__SVEPredicateDReg1_0__imm_95_31,
    1819             :   Convert__SVEPredicateBReg1_0__imm_95_31,
    1820             :   Convert__SVEPredicateHReg1_0__SVEPattern1_1,
    1821             :   Convert__SVEPredicateSReg1_0__SVEPattern1_1,
    1822             :   Convert__SVEPredicateDReg1_0__SVEPattern1_1,
    1823             :   Convert__SVEPredicateBReg1_0__SVEPattern1_1,
    1824             :   Convert__Reg1_0__SImm61_1,
    1825             :   Convert__regLR,
    1826             :   Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_311_2,
    1827             :   Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_631_2,
    1828             :   Convert__VectorReg641_1__VectorReg1281_2__Imm1_321_3,
    1829             :   Convert__VectorReg641_1__VectorReg1281_2__Imm1_161_3,
    1830             :   Convert__VectorReg641_1__VectorReg1281_2__Imm1_81_3,
    1831             :   Convert__VectorReg641_0__VectorReg1281_2__Imm1_321_4,
    1832             :   Convert__VectorReg641_0__VectorReg1281_2__Imm1_161_4,
    1833             :   Convert__VectorReg641_0__VectorReg1281_2__Imm1_81_4,
    1834             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_81_3,
    1835             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3,
    1836             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_161_3,
    1837             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4,
    1838             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4,
    1839             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4,
    1840             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg641_3,
    1841             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg641_4,
    1842             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2,
    1843             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2,
    1844             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg641_3,
    1845             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg641_4,
    1846             :   Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3,
    1847             :   Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3,
    1848             :   Convert__imm_95_0__imm_95_0__imm_95_0,
    1849             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_1__VectorReg1281_2__VectorIndexS1_3,
    1850             :   Convert__imm_95_4,
    1851             :   Convert__imm_95_5,
    1852             :   Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3,
    1853             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2,
    1854             :   Convert__Reg1_0__Reg1_1__Imm0_631_2,
    1855             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm0_71_3,
    1856             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm0_631_3,
    1857             :   Convert__VectorReg641_1__VectorReg641_2__Imm0_311_3,
    1858             :   Convert__VectorReg641_1__VectorReg641_2__Imm0_151_3,
    1859             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm0_311_3,
    1860             :   Convert__VectorReg641_1__VectorReg641_2__Imm0_71_3,
    1861             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm0_151_3,
    1862             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm0_71_4,
    1863             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm0_631_4,
    1864             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm0_311_4,
    1865             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm0_151_4,
    1866             :   Convert__VectorReg641_0__VectorReg641_2__Imm0_311_4,
    1867             :   Convert__VectorReg641_0__VectorReg641_2__Imm0_151_4,
    1868             :   Convert__VectorReg641_0__VectorReg641_2__Imm0_71_4,
    1869             :   Convert__VectorReg1281_1__VectorReg641_2,
    1870             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2,
    1871             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_71_3,
    1872             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_631_3,
    1873             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_311_3,
    1874             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_151_3,
    1875             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_311_3,
    1876             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_71_3,
    1877             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_151_3,
    1878             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_71_4,
    1879             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_631_4,
    1880             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_311_4,
    1881             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_151_4,
    1882             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_311_4,
    1883             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_151_4,
    1884             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_71_4,
    1885             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4,
    1886             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4,
    1887             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6,
    1888             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6,
    1889             :   Convert__Reg1_1__VectorReg1281_2__VectorIndexB1_3,
    1890             :   Convert__Reg1_1__VectorReg1281_2__VectorIndexH1_3,
    1891             :   Convert__VectorReg1281_1__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4,
    1892             :   Convert__VectorReg1281_1__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4,
    1893             :   Convert__VectorReg1281_0__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6,
    1894             :   Convert__VectorReg1281_0__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6,
    1895             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
    1896             :   Convert__Reg1_0__Reg1_1__Imm1_81_2,
    1897             :   Convert__Reg1_0__Reg1_1__Imm0_151_2,
    1898             :   Convert__Reg1_0__Reg1_1__Imm0_311_2,
    1899             :   Convert__Reg1_0__Reg1_1__Imm0_71_2,
    1900             :   Convert__VectorReg641_1__VectorReg1281_2,
    1901             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm1_641_2,
    1902             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_641_3,
    1903             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_321_3,
    1904             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_161_3,
    1905             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_81_3,
    1906             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_641_4,
    1907             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_321_4,
    1908             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_161_4,
    1909             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_81_4,
    1910             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm1_81_3,
    1911             :   Convert__VectorReg641_1__VectorReg641_2__Imm1_81_3,
    1912             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm1_81_4,
    1913             :   Convert__VectorReg641_0__VectorReg641_2__Imm1_81_4,
    1914             :   Convert__VectorReg1281_1__VectorReg641_2__Imm0_311_3,
    1915             :   Convert__VectorReg1281_1__VectorReg641_2__Imm0_151_3,
    1916             :   Convert__VectorReg1281_1__VectorReg641_2__Imm0_71_3,
    1917             :   Convert__VectorReg1281_0__VectorReg641_2__Imm0_311_4,
    1918             :   Convert__VectorReg1281_0__VectorReg641_2__Imm0_151_4,
    1919             :   Convert__VectorReg1281_0__VectorReg641_2__Imm0_71_4,
    1920             :   Convert__TypedVectorList1_0b1_0__VectorIndexB1_1__Reg1_3,
    1921             :   Convert__TypedVectorList1_0d1_0__VectorIndexD1_1__Reg1_3,
    1922             :   Convert__TypedVectorList1_0h1_0__VectorIndexH1_1__Reg1_3,
    1923             :   Convert__TypedVectorList1_0s1_0__VectorIndexS1_1__Reg1_3,
    1924             :   Convert__VecListOne1281_1__VectorIndexB1_2__Reg1_4,
    1925             :   Convert__VecListOne1281_1__VectorIndexD1_2__Reg1_4,
    1926             :   Convert__VecListOne1281_1__VectorIndexH1_2__Reg1_4,
    1927             :   Convert__VecListOne1281_1__VectorIndexS1_2__Reg1_4,
    1928             :   Convert__Reg1_3__TypedVectorList1_0b1_0__VectorIndexB1_1__Tie0_4_4__regXZR,
    1929             :   Convert__Reg1_3__TypedVectorList1_0b1_0__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1930             :   Convert__Reg1_3__TypedVectorList1_0d1_0__VectorIndexD1_1__Tie0_4_4__regXZR,
    1931             :   Convert__Reg1_3__TypedVectorList1_0d1_0__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1932             :   Convert__Reg1_3__TypedVectorList1_0h1_0__VectorIndexH1_1__Tie0_4_4__regXZR,
    1933             :   Convert__Reg1_3__TypedVectorList1_0h1_0__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1934             :   Convert__Reg1_3__TypedVectorList1_0s1_0__VectorIndexS1_1__Tie0_4_4__regXZR,
    1935             :   Convert__Reg1_3__TypedVectorList1_0s1_0__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1936             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexB1_2__Tie0_5_5__regXZR,
    1937             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1938             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexD1_2__Tie0_5_5__regXZR,
    1939             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1940             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexH1_2__Tie0_5_5__regXZR,
    1941             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1942             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexS1_2__Tie0_5_5__regXZR,
    1943             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1944             :   Convert__TypedVectorList2_0b1_0__VectorIndexB1_1__Reg1_3,
    1945             :   Convert__TypedVectorList2_0d1_0__VectorIndexD1_1__Reg1_3,
    1946             :   Convert__TypedVectorList2_0h1_0__VectorIndexH1_1__Reg1_3,
    1947             :   Convert__TypedVectorList2_0s1_0__VectorIndexS1_1__Reg1_3,
    1948             :   Convert__VecListTwo1281_1__VectorIndexB1_2__Reg1_4,
    1949             :   Convert__VecListTwo1281_1__VectorIndexD1_2__Reg1_4,
    1950             :   Convert__VecListTwo1281_1__VectorIndexH1_2__Reg1_4,
    1951             :   Convert__VecListTwo1281_1__VectorIndexS1_2__Reg1_4,
    1952             :   Convert__Reg1_3__TypedVectorList2_0b1_0__VectorIndexB1_1__Tie0_4_4__regXZR,
    1953             :   Convert__Reg1_3__TypedVectorList2_0b1_0__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1954             :   Convert__Reg1_3__TypedVectorList2_0d1_0__VectorIndexD1_1__Tie0_4_4__regXZR,
    1955             :   Convert__Reg1_3__TypedVectorList2_0d1_0__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1956             :   Convert__Reg1_3__TypedVectorList2_0h1_0__VectorIndexH1_1__Tie0_4_4__regXZR,
    1957             :   Convert__Reg1_3__TypedVectorList2_0h1_0__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1958             :   Convert__Reg1_3__TypedVectorList2_0s1_0__VectorIndexS1_1__Tie0_4_4__regXZR,
    1959             :   Convert__Reg1_3__TypedVectorList2_0s1_0__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1960             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexB1_2__Tie0_5_5__regXZR,
    1961             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1962             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexD1_2__Tie0_5_5__regXZR,
    1963             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1964             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexH1_2__Tie0_5_5__regXZR,
    1965             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1966             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexS1_2__Tie0_5_5__regXZR,
    1967             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1968             :   Convert__TypedVectorList3_0b1_0__VectorIndexB1_1__Reg1_3,
    1969             :   Convert__TypedVectorList3_0d1_0__VectorIndexD1_1__Reg1_3,
    1970             :   Convert__TypedVectorList3_0h1_0__VectorIndexH1_1__Reg1_3,
    1971             :   Convert__TypedVectorList3_0s1_0__VectorIndexS1_1__Reg1_3,
    1972             :   Convert__VecListThree1281_1__VectorIndexB1_2__Reg1_4,
    1973             :   Convert__VecListThree1281_1__VectorIndexD1_2__Reg1_4,
    1974             :   Convert__VecListThree1281_1__VectorIndexH1_2__Reg1_4,
    1975             :   Convert__VecListThree1281_1__VectorIndexS1_2__Reg1_4,
    1976             :   Convert__Reg1_3__TypedVectorList3_0b1_0__VectorIndexB1_1__Tie0_4_4__regXZR,
    1977             :   Convert__Reg1_3__TypedVectorList3_0b1_0__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1978             :   Convert__Reg1_3__TypedVectorList3_0d1_0__VectorIndexD1_1__Tie0_4_4__regXZR,
    1979             :   Convert__Reg1_3__TypedVectorList3_0d1_0__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1980             :   Convert__Reg1_3__TypedVectorList3_0h1_0__VectorIndexH1_1__Tie0_4_4__regXZR,
    1981             :   Convert__Reg1_3__TypedVectorList3_0h1_0__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1982             :   Convert__Reg1_3__TypedVectorList3_0s1_0__VectorIndexS1_1__Tie0_4_4__regXZR,
    1983             :   Convert__Reg1_3__TypedVectorList3_0s1_0__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1984             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexB1_2__Tie0_5_5__regXZR,
    1985             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1986             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexD1_2__Tie0_5_5__regXZR,
    1987             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1988             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexH1_2__Tie0_5_5__regXZR,
    1989             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1990             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexS1_2__Tie0_5_5__regXZR,
    1991             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1992             :   Convert__TypedVectorList4_0b1_0__VectorIndexB1_1__Reg1_3,
    1993             :   Convert__TypedVectorList4_0d1_0__VectorIndexD1_1__Reg1_3,
    1994             :   Convert__TypedVectorList4_0h1_0__VectorIndexH1_1__Reg1_3,
    1995             :   Convert__TypedVectorList4_0s1_0__VectorIndexS1_1__Reg1_3,
    1996             :   Convert__VecListFour1281_1__VectorIndexB1_2__Reg1_4,
    1997             :   Convert__VecListFour1281_1__VectorIndexD1_2__Reg1_4,
    1998             :   Convert__VecListFour1281_1__VectorIndexH1_2__Reg1_4,
    1999             :   Convert__VecListFour1281_1__VectorIndexS1_2__Reg1_4,
    2000             :   Convert__Reg1_3__TypedVectorList4_0b1_0__VectorIndexB1_1__Tie0_4_4__regXZR,
    2001             :   Convert__Reg1_3__TypedVectorList4_0b1_0__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    2002             :   Convert__Reg1_3__TypedVectorList4_0d1_0__VectorIndexD1_1__Tie0_4_4__regXZR,
    2003             :   Convert__Reg1_3__TypedVectorList4_0d1_0__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    2004             :   Convert__Reg1_3__TypedVectorList4_0h1_0__VectorIndexH1_1__Tie0_4_4__regXZR,
    2005             :   Convert__Reg1_3__TypedVectorList4_0h1_0__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    2006             :   Convert__Reg1_3__TypedVectorList4_0s1_0__VectorIndexS1_1__Tie0_4_4__regXZR,
    2007             :   Convert__Reg1_3__TypedVectorList4_0s1_0__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    2008             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexB1_2__Tie0_5_5__regXZR,
    2009             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    2010             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexD1_2__Tie0_5_5__regXZR,
    2011             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    2012             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexH1_2__Tie0_5_5__regXZR,
    2013             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    2014             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexS1_2__Tie0_5_5__regXZR,
    2015             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    2016             :   Convert__regWZR__Reg1_0__Reg1_2,
    2017             :   Convert__regXZR__Reg1_0__Reg1_2,
    2018             :   Convert__Reg1_0__Reg1_1__Reg1_2__GPR64sp01_4,
    2019             :   Convert__Reg1_0__Tie0_1_1__Reg1_1,
    2020             :   Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7,
    2021             :   Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15,
    2022             :   Convert__VectorReg1281_1__VectorReg641_2__imm_95_0,
    2023             :   Convert__VectorReg1281_0__VectorReg641_2__imm_95_0,
    2024             :   Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0,
    2025             :   Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0,
    2026             :   Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_31,
    2027             :   Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__regXZR,
    2028             :   Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__Reg1_4,
    2029             :   Convert__Reg1_0__Imm0_71_1__SysCR1_2__SysCR1_3__Imm0_71_4,
    2030             :   Convert__VectorReg1281_1__VecListFour1281_2__VectorReg1281_3,
    2031             :   Convert__VectorReg1281_1__VecListOne1281_2__VectorReg1281_3,
    2032             :   Convert__VectorReg1281_1__VecListThree1281_2__VectorReg1281_3,
    2033             :   Convert__VectorReg1281_1__VecListTwo1281_2__VectorReg1281_3,
    2034             :   Convert__VectorReg641_1__VecListFour1281_2__VectorReg641_3,
    2035             :   Convert__VectorReg641_1__VecListOne1281_2__VectorReg641_3,
    2036             :   Convert__VectorReg641_1__VecListThree1281_2__VectorReg641_3,
    2037             :   Convert__VectorReg641_1__VecListTwo1281_2__VectorReg641_3,
    2038             :   Convert__VectorReg1281_0__TypedVectorList4_16b1_2__VectorReg1281_3,
    2039             :   Convert__VectorReg1281_0__TypedVectorList1_16b1_2__VectorReg1281_3,
    2040             :   Convert__VectorReg1281_0__TypedVectorList3_16b1_2__VectorReg1281_3,
    2041             :   Convert__VectorReg1281_0__TypedVectorList2_16b1_2__VectorReg1281_3,
    2042             :   Convert__VectorReg641_0__TypedVectorList4_16b1_2__VectorReg641_3,
    2043             :   Convert__VectorReg641_0__TypedVectorList1_16b1_2__VectorReg641_3,
    2044             :   Convert__VectorReg641_0__TypedVectorList3_16b1_2__VectorReg641_3,
    2045             :   Convert__VectorReg641_0__TypedVectorList2_16b1_2__VectorReg641_3,
    2046             :   Convert__Reg1_0__Imm0_311_1__BranchTarget141_2,
    2047             :   Convert__Reg1_0__Imm32_631_1__BranchTarget141_2,
    2048             :   Convert__GPR32as641_0__TBZImm0_311_1__BranchTarget141_2,
    2049             :   Convert__VectorReg1281_1__Tie0_2_2__VecListFour1281_2__VectorReg1281_3,
    2050             :   Convert__VectorReg1281_1__Tie0_2_2__VecListOne1281_2__VectorReg1281_3,
    2051             :   Convert__VectorReg1281_1__Tie0_2_2__VecListThree1281_2__VectorReg1281_3,
    2052             :   Convert__VectorReg1281_1__Tie0_2_2__VecListTwo1281_2__VectorReg1281_3,
    2053             :   Convert__VectorReg641_1__Tie0_2_2__VecListFour1281_2__VectorReg641_3,
    2054             :   Convert__VectorReg641_1__Tie0_2_2__VecListOne1281_2__VectorReg641_3,
    2055             :   Convert__VectorReg641_1__Tie0_2_2__VecListThree1281_2__VectorReg641_3,
    2056             :   Convert__VectorReg641_1__Tie0_2_2__VecListTwo1281_2__VectorReg641_3,
    2057             :   Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList4_16b1_2__VectorReg1281_3,
    2058             :   Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList1_16b1_2__VectorReg1281_3,
    2059             :   Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList3_16b1_2__VectorReg1281_3,
    2060             :   Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList2_16b1_2__VectorReg1281_3,
    2061             :   Convert__VectorReg641_0__Tie0_1_1__TypedVectorList4_16b1_2__VectorReg641_3,
    2062             :   Convert__VectorReg641_0__Tie0_1_1__TypedVectorList1_16b1_2__VectorReg641_3,
    2063             :   Convert__VectorReg641_0__Tie0_1_1__TypedVectorList3_16b1_2__VectorReg641_3,
    2064             :   Convert__VectorReg641_0__Tie0_1_1__TypedVectorList2_16b1_2__VectorReg641_3,
    2065             :   Convert__regWZR__Reg1_0__LogicalImm321_1,
    2066             :   Convert__regXZR__Reg1_0__LogicalImm641_1,
    2067             :   Convert__regWZR__Reg1_0__Reg1_1__LogicalShifter321_2,
    2068             :   Convert__regXZR__Reg1_0__Reg1_1__LogicalShifter641_2,
    2069             :   Convert__imm_95_2,
    2070             :   Convert__imm_95_3,
    2071             :   Convert__imm_95_1,
    2072             :   Convert__SVEPredicateHReg1_0__SVEPredicateHReg1_1__SVEPredicateHReg1_2,
    2073             :   Convert__SVEPredicateSReg1_0__SVEPredicateSReg1_1__SVEPredicateSReg1_2,
    2074             :   Convert__SVEPredicateDReg1_0__SVEPredicateDReg1_1__SVEPredicateDReg1_2,
    2075             :   Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1__SVEPredicateBReg1_2,
    2076             :   CVT_NUM_SIGNATURES
    2077             : };
    2078             : 
    2079             : } // end anonymous namespace
    2080             : 
    2081             : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
    2082             :   // Convert__Reg1_0__Reg1_1
    2083             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
    2084             :   // Convert__VectorReg1281_1__VectorReg1281_2
    2085             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2086             :   // Convert__VectorReg641_1__VectorReg641_2
    2087             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2088             :   // Convert__VectorReg1281_0__VectorReg1281_2
    2089             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2090             :   // Convert__VectorReg641_0__VectorReg641_2
    2091             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2092             :   // Convert__Reg1_0__Reg1_1__Reg1_2
    2093             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    2094             :   // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16
    2095             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_16, 0, CVT_Done },
    2096             :   // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24
    2097             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_24, 0, CVT_Done },
    2098             :   // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
    2099             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    2100             :   // Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2
    2101             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addAddSubImmNegOperands, 3, CVT_Done },
    2102             :   // Convert__Reg1_0__Reg1_1__AddSubImm2_2
    2103             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addAddSubImmOperands, 3, CVT_Done },
    2104             :   // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2
    2105             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    2106             :   // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2
    2107             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    2108             :   // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2
    2109             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    2110             :   // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2
    2111             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    2112             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3
    2113             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    2114             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3
    2115             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    2116             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3
    2117             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2118             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3
    2119             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtendOperands, 4, CVT_Done },
    2120             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3
    2121             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2122             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Extend641_3
    2123             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtend64Operands, 4, CVT_Done },
    2124             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ExtendLSL641_3
    2125             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtend64Operands, 4, CVT_Done },
    2126             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4
    2127             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
    2128             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4
    2129             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    2130             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5
    2131             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
    2132             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5
    2133             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
    2134             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5
    2135             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
    2136             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorBReg1_5
    2137             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
    2138             :   // Convert__VectorReg641_1__VectorReg1281_2__VectorReg1281_3
    2139             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    2140             :   // Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4
    2141             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
    2142             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3
    2143             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    2144             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4
    2145             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
    2146             :   // Convert__Reg1_1__VectorReg1281_2
    2147             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2148             :   // Convert__Reg1_0__VectorReg1281_1
    2149             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_Done },
    2150             :   // Convert__Reg1_0__Reg1_1__SImm61_2
    2151             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    2152             :   // Convert__Reg1_1__VectorReg641_2
    2153             :   { CVT_95_Reg, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2154             :   // Convert__Reg1_0__VectorReg641_1
    2155             :   { CVT_95_Reg, 1, CVT_95_addVectorReg64Operands, 2, CVT_Done },
    2156             :   // Convert__Reg1_0__AdrLabel1_1
    2157             :   { CVT_95_Reg, 1, CVT_95_addAdrLabelOperands, 2, CVT_Done },
    2158             :   // Convert__Reg1_0__AdrpLabel1_1
    2159             :   { CVT_95_Reg, 1, CVT_95_addAdrpLabelOperands, 2, CVT_Done },
    2160             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2
    2161             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2162             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2
    2163             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2164             :   // Convert__Reg1_0__Reg1_1__LogicalImm321_2
    2165             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 3, CVT_Done },
    2166             :   // Convert__Reg1_0__Reg1_1__LogicalImm641_2
    2167             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 3, CVT_Done },
    2168             :   // Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2
    2169             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_, 3, CVT_Done },
    2170             :   // Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2
    2171             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 3, CVT_Done },
    2172             :   // Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2
    2173             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 3, CVT_Done },
    2174             :   // Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2
    2175             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_, 3, CVT_Done },
    2176             :   // Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3
    2177             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2178             :   // Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3
    2179             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2180             :   // Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31
    2181             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_31Operands, 3, CVT_imm_95_31, 0, CVT_Done },
    2182             :   // Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63
    2183             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_63Operands, 3, CVT_imm_95_63, 0, CVT_Done },
    2184             :   // Convert__Reg1_0
    2185             :   { CVT_95_Reg, 1, CVT_Done },
    2186             :   // Convert_NoOperands
    2187             :   { CVT_Done },
    2188             :   // Convert__BranchTarget261_0
    2189             :   { CVT_95_addBranchTarget26Operands, 1, CVT_Done },
    2190             :   // Convert__CondCode1_1__PCRelLabel191_2
    2191             :   { CVT_95_addCondCodeOperands, 2, CVT_95_addPCRelLabel19Operands, 3, CVT_Done },
    2192             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_311_2__Imm0_311_3
    2193             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImm0_95_31Operands, 3, CVT_95_addImm0_95_31Operands, 4, CVT_Done },
    2194             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2__Imm0_631_3
    2195             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImm0_95_63Operands, 3, CVT_95_addImm0_95_63Operands, 4, CVT_Done },
    2196             :   // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__imm_95_0
    2197             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImm0_95_255Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    2198             :   // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__imm_95_0
    2199             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImm0_95_255Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    2200             :   // Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2
    2201             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_, 3, CVT_Done },
    2202             :   // Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2
    2203             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_, 3, CVT_Done },
    2204             :   // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__imm_95_0
    2205             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_255Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    2206             :   // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__imm_95_0
    2207             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_255Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    2208             :   // Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2
    2209             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_, 3, CVT_Done },
    2210             :   // Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2
    2211             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_, 3, CVT_Done },
    2212             :   // Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2
    2213             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_, 3, CVT_Done },
    2214             :   // Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2
    2215             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_, 3, CVT_Done },
    2216             :   // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3
    2217             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2218             :   // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    2219             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2220             :   // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3
    2221             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2222             :   // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    2223             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2224             :   // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3
    2225             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2226             :   // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    2227             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2228             :   // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3
    2229             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2230             :   // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    2231             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2232             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3
    2233             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    2234             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4
    2235             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    2236             :   // Convert__Imm0_655351_0
    2237             :   { CVT_95_addImm0_95_65535Operands, 1, CVT_Done },
    2238             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3
    2239             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Done },
    2240             :   // Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3
    2241             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2242             :   // Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3
    2243             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2244             :   // Convert__Reg1_0__PCRelLabel191_1
    2245             :   { CVT_95_Reg, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
    2246             :   // Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3
    2247             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_15Operands, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
    2248             :   // Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3
    2249             :   { CVT_95_Reg, 1, CVT_95_addImm0_95_31Operands, 2, CVT_95_addImm0_95_15Operands, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
    2250             :   // Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2
    2251             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 3, CVT_Done },
    2252             :   // Convert__imm_95_15
    2253             :   { CVT_imm_95_15, 0, CVT_Done },
    2254             :   // Convert__Imm0_151_0
    2255             :   { CVT_95_addImm0_95_15Operands, 1, CVT_Done },
    2256             :   // Convert__Reg1_0__Reg1_2__Reg1_1
    2257             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
    2258             :   // Convert__VectorReg1281_1__VectorReg1281_3__VectorReg1281_2
    2259             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2260             :   // Convert__VectorReg641_1__VectorReg641_3__VectorReg641_2
    2261             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 4, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2262             :   // Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2
    2263             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2264             :   // Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2
    2265             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 5, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2266             :   // Convert__regWZR__Reg1_0__Reg1_1__imm_95_16
    2267             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_16, 0, CVT_Done },
    2268             :   // Convert__regXZR__Reg1_0__Reg1_1__imm_95_24
    2269             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_24, 0, CVT_Done },
    2270             :   // Convert__regWZR__Reg1_0__Reg1_1__imm_95_0
    2271             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
    2272             :   // Convert__regWZR__Reg1_0__AddSubImmNeg2_1
    2273             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addAddSubImmNegOperands, 2, CVT_Done },
    2274             :   // Convert__regWZR__Reg1_0__AddSubImm2_1
    2275             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addAddSubImmOperands, 2, CVT_Done },
    2276             :   // Convert__regXZR__Reg1_0__Reg1_1__imm_95_0
    2277             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
    2278             :   // Convert__regXZR__Reg1_0__AddSubImmNeg2_1
    2279             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addAddSubImmNegOperands, 2, CVT_Done },
    2280             :   // Convert__regXZR__Reg1_0__AddSubImm2_1
    2281             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addAddSubImmOperands, 2, CVT_Done },
    2282             :   // Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2
    2283             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    2284             :   // Convert__regWZR__Reg1_0__Reg1_1__Extend1_2
    2285             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtendOperands, 3, CVT_Done },
    2286             :   // Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2
    2287             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    2288             :   // Convert__regXZR__Reg1_0__Reg1_1__Extend1_2
    2289             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtendOperands, 3, CVT_Done },
    2290             :   // Convert__regXZR__Reg1_0__Reg1_1__ExtendLSL641_2
    2291             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtend64Operands, 3, CVT_Done },
    2292             :   // Convert__imm_95_20
    2293             :   { CVT_imm_95_20, 0, CVT_Done },
    2294             :   // Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3
    2295             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
    2296             :   // Convert__Reg1_0__regWZR__regWZR__CondCode1_1
    2297             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_regWZR, 0, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2298             :   // Convert__Reg1_0__regXZR__regXZR__CondCode1_1
    2299             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_regXZR, 0, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2300             :   // Convert__imm_95_0
    2301             :   { CVT_imm_95_0, 0, CVT_Done },
    2302             :   // Convert__Barrier1_0
    2303             :   { CVT_95_addBarrierOperands, 1, CVT_Done },
    2304             :   // Convert__SVEVectorHReg1_0__Reg1_1
    2305             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2306             :   // Convert__SVEVectorSReg1_0__Reg1_1
    2307             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2308             :   // Convert__SVEVectorDReg1_0__Reg1_1
    2309             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2310             :   // Convert__SVEVectorBReg1_0__Reg1_1
    2311             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2312             :   // Convert__VectorReg1281_1__Reg1_2
    2313             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_Reg, 3, CVT_Done },
    2314             :   // Convert__VectorReg641_1__Reg1_2
    2315             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_Reg, 3, CVT_Done },
    2316             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_2
    2317             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Done },
    2318             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_2
    2319             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Done },
    2320             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_2
    2321             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Done },
    2322             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_2
    2323             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Done },
    2324             :   // Convert__VectorReg1281_0__Reg1_2
    2325             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_Reg, 3, CVT_Done },
    2326             :   // Convert__VectorReg641_0__Reg1_2
    2327             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_Reg, 3, CVT_Done },
    2328             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexB1_3
    2329             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexBOperands, 4, CVT_Done },
    2330             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexD1_3
    2331             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexDOperands, 4, CVT_Done },
    2332             :   // Convert__VectorReg641_1__VectorReg1281_2__VectorIndexS1_3
    2333             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexSOperands, 4, CVT_Done },
    2334             :   // Convert__VectorReg641_1__VectorReg1281_2__VectorIndexH1_3
    2335             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexHOperands, 4, CVT_Done },
    2336             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexS1_3
    2337             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexSOperands, 4, CVT_Done },
    2338             :   // Convert__VectorReg641_1__VectorReg1281_2__VectorIndexB1_3
    2339             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexBOperands, 4, CVT_Done },
    2340             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexH1_3
    2341             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexHOperands, 4, CVT_Done },
    2342             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_3
    2343             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexHOperands, 4, CVT_Done },
    2344             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_3
    2345             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexSOperands, 4, CVT_Done },
    2346             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_3
    2347             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexDOperands, 4, CVT_Done },
    2348             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_3
    2349             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexBOperands, 4, CVT_Done },
    2350             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexB1_4
    2351             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexBOperands, 5, CVT_Done },
    2352             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexD1_4
    2353             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexDOperands, 5, CVT_Done },
    2354             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexS1_4
    2355             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2356             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexH1_4
    2357             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2358             :   // Convert__VectorReg641_0__VectorReg1281_2__VectorIndexS1_4
    2359             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2360             :   // Convert__VectorReg641_0__VectorReg1281_2__VectorIndexH1_4
    2361             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2362             :   // Convert__VectorReg641_0__VectorReg1281_2__VectorIndexB1_4
    2363             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexBOperands, 5, CVT_Done },
    2364             :   // Convert__imm_95_16
    2365             :   { CVT_imm_95_16, 0, CVT_Done },
    2366             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__Imm1_4
    2367             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    2368             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__Imm1_4
    2369             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    2370             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__Imm1_6
    2371             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addImmOperands, 7, CVT_Done },
    2372             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__Imm1_6
    2373             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addImmOperands, 7, CVT_Done },
    2374             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_311_3
    2375             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_31Operands, 4, CVT_Done },
    2376             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_631_3
    2377             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_63Operands, 4, CVT_Done },
    2378             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__ComplexRotationOdd1_4
    2379             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
    2380             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__ComplexRotationOdd1_4
    2381             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
    2382             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6
    2383             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
    2384             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__ComplexRotationOdd1_6
    2385             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
    2386             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__ComplexRotationEven1_4
    2387             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
    2388             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3__ComplexRotationEven1_4
    2389             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
    2390             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexD1_4__ComplexRotationEven1_5
    2391             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexDOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
    2392             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4__ComplexRotationEven1_5
    2393             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexDOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
    2394             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4__ComplexRotationEven1_5
    2395             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
    2396             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6
    2397             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
    2398             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4__ComplexRotationEven1_6
    2399             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
    2400             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7
    2401             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexDOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
    2402             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6__ComplexRotationEven1_7
    2403             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexSOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
    2404             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7
    2405             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexDOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
    2406             :   // Convert__VectorReg1281_0__VectorReg641_2
    2407             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2408             :   // Convert__VectorReg641_0__VectorReg1281_2
    2409             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2410             :   // Convert__Reg1_0__Reg1_1__Imm1_161_2
    2411             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_Done },
    2412             :   // Convert__Reg1_0__Reg1_1__Imm1_321_2
    2413             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_Done },
    2414             :   // Convert__Reg1_0__Reg1_1__Imm1_641_2
    2415             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm1_95_64Operands, 3, CVT_Done },
    2416             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_641_3
    2417             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_64Operands, 4, CVT_Done },
    2418             :   // Convert__VectorReg641_1__VectorReg641_2__Imm1_321_3
    2419             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_32Operands, 4, CVT_Done },
    2420             :   // Convert__VectorReg641_1__VectorReg641_2__Imm1_161_3
    2421             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_16Operands, 4, CVT_Done },
    2422             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_321_3
    2423             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_32Operands, 4, CVT_Done },
    2424             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_161_3
    2425             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_16Operands, 4, CVT_Done },
    2426             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_641_4
    2427             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_64Operands, 5, CVT_Done },
    2428             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_321_4
    2429             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_32Operands, 5, CVT_Done },
    2430             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_161_4
    2431             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_16Operands, 5, CVT_Done },
    2432             :   // Convert__VectorReg641_0__VectorReg641_2__Imm1_321_4
    2433             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_32Operands, 5, CVT_Done },
    2434             :   // Convert__VectorReg641_0__VectorReg641_2__Imm1_161_4
    2435             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_16Operands, 5, CVT_Done },
    2436             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
    2437             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
    2438             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4
    2439             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexDOperands, 5, CVT_Done },
    2440             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4
    2441             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2442             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4
    2443             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2444             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4
    2445             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2446             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__VectorIndexH1_4
    2447             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2448             :   // Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3__VectorIndexD1_4
    2449             :   { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexDOperands, 5, CVT_Done },
    2450             :   // Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorRegLo1_3__VectorIndexH1_4
    2451             :   { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2452             :   // Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3__VectorIndexS1_4
    2453             :   { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2454             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorRegLo1_2__VectorIndexH1_4
    2455             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2456             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2__VectorIndexS1_4
    2457             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2458             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2__VectorIndexD1_4
    2459             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexDOperands, 5, CVT_Done },
    2460             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6
    2461             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexDOperands, 7, CVT_Done },
    2462             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6
    2463             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexSOperands, 7, CVT_Done },
    2464             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorRegLo1_4__VectorIndexH1_6
    2465             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexHOperands, 7, CVT_Done },
    2466             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6
    2467             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexSOperands, 7, CVT_Done },
    2468             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6
    2469             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexHOperands, 7, CVT_Done },
    2470             :   // Convert__Reg1_0__FPImm1_1
    2471             :   { CVT_95_Reg, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
    2472             :   // Convert__VectorReg1281_1__FPImm1_2
    2473             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addFPImmOperands, 3, CVT_Done },
    2474             :   // Convert__VectorReg641_1__FPImm1_2
    2475             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addFPImmOperands, 3, CVT_Done },
    2476             :   // Convert__Reg1_0__regWZR
    2477             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_Done },
    2478             :   // Convert__Reg1_0__regXZR
    2479             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_Done },
    2480             :   // Convert__VectorReg1281_0__FPImm1_2
    2481             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addFPImmOperands, 3, CVT_Done },
    2482             :   // Convert__VectorReg641_0__FPImm1_2
    2483             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addFPImmOperands, 3, CVT_Done },
    2484             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndex11_3
    2485             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndex1Operands, 4, CVT_Done },
    2486             :   // Convert__VectorReg1281_1__Reg1_3__VectorIndex11_2
    2487             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_Reg, 4, CVT_95_addVectorIndex1Operands, 3, CVT_Done },
    2488             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndex11_3
    2489             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndex1Operands, 4, CVT_Done },
    2490             :   // Convert__VectorReg1281_0__Reg1_3__VectorIndex11_2
    2491             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_Reg, 4, CVT_95_addVectorIndex1Operands, 3, CVT_Done },
    2492             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4
    2493             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexDOperands, 5, CVT_Done },
    2494             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4
    2495             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2496             :   // Convert__VectorReg641_1__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4
    2497             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2498             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4
    2499             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2500             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorRegLo1_3__VectorIndexH1_4
    2501             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2502             :   // Convert__Reg1_1__Reg1_2__VectorReg1281_3__VectorIndexD1_4
    2503             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexDOperands, 5, CVT_Done },
    2504             :   // Convert__Reg1_1__Reg1_2__VectorRegLo1_3__VectorIndexH1_4
    2505             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2506             :   // Convert__Reg1_1__Reg1_2__VectorReg1281_3__VectorIndexS1_4
    2507             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2508             :   // Convert__Reg1_0__Reg1_1__VectorRegLo1_2__VectorIndexH1_4
    2509             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2510             :   // Convert__Reg1_0__Reg1_1__VectorReg1281_2__VectorIndexS1_4
    2511             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2512             :   // Convert__Reg1_0__Reg1_1__VectorReg1281_2__VectorIndexD1_4
    2513             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexDOperands, 5, CVT_Done },
    2514             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6
    2515             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexDOperands, 7, CVT_Done },
    2516             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6
    2517             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexSOperands, 7, CVT_Done },
    2518             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorRegLo1_4__VectorIndexH1_6
    2519             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexHOperands, 7, CVT_Done },
    2520             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6
    2521             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexSOperands, 7, CVT_Done },
    2522             :   // Convert__VectorReg641_0__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6
    2523             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexHOperands, 7, CVT_Done },
    2524             :   // Convert__Imm0_1271_0
    2525             :   { CVT_95_addImm0_95_127Operands, 1, CVT_Done },
    2526             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_3
    2527             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 4, CVT_Done },
    2528             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_3
    2529             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 4, CVT_Done },
    2530             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_3
    2531             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 4, CVT_Done },
    2532             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_3
    2533             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 4, CVT_Done },
    2534             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexB1_2__Reg1_3
    2535             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 4, CVT_Done },
    2536             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexD1_2__Reg1_3
    2537             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 4, CVT_Done },
    2538             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexH1_2__Reg1_3
    2539             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 4, CVT_Done },
    2540             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexS1_2__Reg1_3
    2541             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 4, CVT_Done },
    2542             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexB1_2__VectorReg1281_3__VectorIndexB1_4
    2543             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexBOperands, 5, CVT_Done },
    2544             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexD1_2__VectorReg1281_3__VectorIndexD1_4
    2545             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexDOperands, 5, CVT_Done },
    2546             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexH1_2__VectorReg1281_3__VectorIndexH1_4
    2547             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    2548             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexS1_2__VectorReg1281_3__VectorIndexS1_4
    2549             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    2550             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexB1_2__VectorReg1281_3__VectorIndexB1_5
    2551             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexBOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexBOperands, 6, CVT_Done },
    2552             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexD1_2__VectorReg1281_3__VectorIndexD1_5
    2553             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexDOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexDOperands, 6, CVT_Done },
    2554             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexH1_2__VectorReg1281_3__VectorIndexH1_5
    2555             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexHOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexHOperands, 6, CVT_Done },
    2556             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexS1_2__VectorReg1281_3__VectorIndexS1_5
    2557             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexSOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 6, CVT_Done },
    2558             :   // Convert__TypedVectorList4_16b1_0__Reg1_2
    2559             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2560             :   // Convert__TypedVectorList4_1d1_0__Reg1_2
    2561             :   { CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2562             :   // Convert__TypedVectorList4_2d1_0__Reg1_2
    2563             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2564             :   // Convert__TypedVectorList4_2s1_0__Reg1_2
    2565             :   { CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2566             :   // Convert__TypedVectorList4_4h1_0__Reg1_2
    2567             :   { CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2568             :   // Convert__TypedVectorList4_4s1_0__Reg1_2
    2569             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2570             :   // Convert__TypedVectorList4_8b1_0__Reg1_2
    2571             :   { CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2572             :   // Convert__TypedVectorList4_8h1_0__Reg1_2
    2573             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2574             :   // Convert__TypedVectorList1_16b1_0__Reg1_2
    2575             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2576             :   // Convert__TypedVectorList1_1d1_0__Reg1_2
    2577             :   { CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2578             :   // Convert__TypedVectorList1_2d1_0__Reg1_2
    2579             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2580             :   // Convert__TypedVectorList1_2s1_0__Reg1_2
    2581             :   { CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2582             :   // Convert__TypedVectorList1_4h1_0__Reg1_2
    2583             :   { CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2584             :   // Convert__TypedVectorList1_4s1_0__Reg1_2
    2585             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2586             :   // Convert__TypedVectorList1_8b1_0__Reg1_2
    2587             :   { CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2588             :   // Convert__TypedVectorList1_8h1_0__Reg1_2
    2589             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2590             :   // Convert__TypedVectorList3_16b1_0__Reg1_2
    2591             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2592             :   // Convert__TypedVectorList3_1d1_0__Reg1_2
    2593             :   { CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2594             :   // Convert__TypedVectorList3_2d1_0__Reg1_2
    2595             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2596             :   // Convert__TypedVectorList3_2s1_0__Reg1_2
    2597             :   { CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2598             :   // Convert__TypedVectorList3_4h1_0__Reg1_2
    2599             :   { CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2600             :   // Convert__TypedVectorList3_4s1_0__Reg1_2
    2601             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2602             :   // Convert__TypedVectorList3_8b1_0__Reg1_2
    2603             :   { CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2604             :   // Convert__TypedVectorList3_8h1_0__Reg1_2
    2605             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2606             :   // Convert__TypedVectorList2_16b1_0__Reg1_2
    2607             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2608             :   // Convert__TypedVectorList2_1d1_0__Reg1_2
    2609             :   { CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2610             :   // Convert__TypedVectorList2_2d1_0__Reg1_2
    2611             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2612             :   // Convert__TypedVectorList2_2s1_0__Reg1_2
    2613             :   { CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2614             :   // Convert__TypedVectorList2_4h1_0__Reg1_2
    2615             :   { CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2616             :   // Convert__TypedVectorList2_4s1_0__Reg1_2
    2617             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2618             :   // Convert__TypedVectorList2_8b1_0__Reg1_2
    2619             :   { CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2620             :   // Convert__TypedVectorList2_8h1_0__Reg1_2
    2621             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    2622             :   // Convert__VecListFour1281_1__Reg1_3
    2623             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    2624             :   // Convert__VecListOne1281_1__Reg1_3
    2625             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    2626             :   // Convert__VecListThree1281_1__Reg1_3
    2627             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    2628             :   // Convert__VecListTwo1281_1__Reg1_3
    2629             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    2630             :   // Convert__VecListFour641_1__Reg1_3
    2631             :   { CVT_95_addVectorList64Operands_LT_4_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    2632             :   // Convert__VecListOne641_1__Reg1_3
    2633             :   { CVT_95_addVectorList64Operands_LT_1_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    2634             :   // Convert__VecListThree641_1__Reg1_3
    2635             :   { CVT_95_addVectorList64Operands_LT_3_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    2636             :   // Convert__VecListTwo641_1__Reg1_3
    2637             :   { CVT_95_addVectorList64Operands_LT_2_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    2638             :   // Convert__Reg1_2__TypedVectorList4_16b1_0__Tie0_3_3__regXZR
    2639             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2640             :   // Convert__Reg1_2__TypedVectorList4_16b1_0__Tie0_3_3__Reg1_4
    2641             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2642             :   // Convert__Reg1_2__TypedVectorList4_1d1_0__Tie0_3_3__regXZR
    2643             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2644             :   // Convert__Reg1_2__TypedVectorList4_1d1_0__Tie0_3_3__Reg1_4
    2645             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2646             :   // Convert__Reg1_2__TypedVectorList4_2d1_0__Tie0_3_3__regXZR
    2647             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2648             :   // Convert__Reg1_2__TypedVectorList4_2d1_0__Tie0_3_3__Reg1_4
    2649             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2650             :   // Convert__Reg1_2__TypedVectorList4_2s1_0__Tie0_3_3__regXZR
    2651             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2652             :   // Convert__Reg1_2__TypedVectorList4_2s1_0__Tie0_3_3__Reg1_4
    2653             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2654             :   // Convert__Reg1_2__TypedVectorList4_4h1_0__Tie0_3_3__regXZR
    2655             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2656             :   // Convert__Reg1_2__TypedVectorList4_4h1_0__Tie0_3_3__Reg1_4
    2657             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2658             :   // Convert__Reg1_2__TypedVectorList4_4s1_0__Tie0_3_3__regXZR
    2659             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2660             :   // Convert__Reg1_2__TypedVectorList4_4s1_0__Tie0_3_3__Reg1_4
    2661             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2662             :   // Convert__Reg1_2__TypedVectorList4_8b1_0__Tie0_3_3__regXZR
    2663             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2664             :   // Convert__Reg1_2__TypedVectorList4_8b1_0__Tie0_3_3__Reg1_4
    2665             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2666             :   // Convert__Reg1_2__TypedVectorList4_8h1_0__Tie0_3_3__regXZR
    2667             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2668             :   // Convert__Reg1_2__TypedVectorList4_8h1_0__Tie0_3_3__Reg1_4
    2669             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2670             :   // Convert__Reg1_2__TypedVectorList1_16b1_0__Tie0_3_3__regXZR
    2671             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2672             :   // Convert__Reg1_2__TypedVectorList1_16b1_0__Tie0_3_3__Reg1_4
    2673             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2674             :   // Convert__Reg1_2__TypedVectorList1_1d1_0__Tie0_3_3__regXZR
    2675             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2676             :   // Convert__Reg1_2__TypedVectorList1_1d1_0__Tie0_3_3__Reg1_4
    2677             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2678             :   // Convert__Reg1_2__TypedVectorList1_2d1_0__Tie0_3_3__regXZR
    2679             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2680             :   // Convert__Reg1_2__TypedVectorList1_2d1_0__Tie0_3_3__Reg1_4
    2681             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2682             :   // Convert__Reg1_2__TypedVectorList1_2s1_0__Tie0_3_3__regXZR
    2683             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2684             :   // Convert__Reg1_2__TypedVectorList1_2s1_0__Tie0_3_3__Reg1_4
    2685             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2686             :   // Convert__Reg1_2__TypedVectorList1_4h1_0__Tie0_3_3__regXZR
    2687             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2688             :   // Convert__Reg1_2__TypedVectorList1_4h1_0__Tie0_3_3__Reg1_4
    2689             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2690             :   // Convert__Reg1_2__TypedVectorList1_4s1_0__Tie0_3_3__regXZR
    2691             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2692             :   // Convert__Reg1_2__TypedVectorList1_4s1_0__Tie0_3_3__Reg1_4
    2693             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2694             :   // Convert__Reg1_2__TypedVectorList1_8b1_0__Tie0_3_3__regXZR
    2695             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2696             :   // Convert__Reg1_2__TypedVectorList1_8b1_0__Tie0_3_3__Reg1_4
    2697             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2698             :   // Convert__Reg1_2__TypedVectorList1_8h1_0__Tie0_3_3__regXZR
    2699             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2700             :   // Convert__Reg1_2__TypedVectorList1_8h1_0__Tie0_3_3__Reg1_4
    2701             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2702             :   // Convert__TypedVectorList1_0b1_0__Tie0_1_1__VectorIndexB1_1__Reg1_3
    2703             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2704             :   // Convert__TypedVectorList1_0d1_0__Tie0_1_1__VectorIndexD1_1__Reg1_3
    2705             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2706             :   // Convert__TypedVectorList1_0h1_0__Tie0_1_1__VectorIndexH1_1__Reg1_3
    2707             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2708             :   // Convert__TypedVectorList1_0s1_0__Tie0_1_1__VectorIndexS1_1__Reg1_3
    2709             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2710             :   // Convert__Reg1_2__TypedVectorList3_16b1_0__Tie0_3_3__regXZR
    2711             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2712             :   // Convert__Reg1_2__TypedVectorList3_16b1_0__Tie0_3_3__Reg1_4
    2713             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2714             :   // Convert__Reg1_2__TypedVectorList3_1d1_0__Tie0_3_3__regXZR
    2715             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2716             :   // Convert__Reg1_2__TypedVectorList3_1d1_0__Tie0_3_3__Reg1_4
    2717             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2718             :   // Convert__Reg1_2__TypedVectorList3_2d1_0__Tie0_3_3__regXZR
    2719             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2720             :   // Convert__Reg1_2__TypedVectorList3_2d1_0__Tie0_3_3__Reg1_4
    2721             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2722             :   // Convert__Reg1_2__TypedVectorList3_2s1_0__Tie0_3_3__regXZR
    2723             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2724             :   // Convert__Reg1_2__TypedVectorList3_2s1_0__Tie0_3_3__Reg1_4
    2725             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2726             :   // Convert__Reg1_2__TypedVectorList3_4h1_0__Tie0_3_3__regXZR
    2727             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2728             :   // Convert__Reg1_2__TypedVectorList3_4h1_0__Tie0_3_3__Reg1_4
    2729             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2730             :   // Convert__Reg1_2__TypedVectorList3_4s1_0__Tie0_3_3__regXZR
    2731             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2732             :   // Convert__Reg1_2__TypedVectorList3_4s1_0__Tie0_3_3__Reg1_4
    2733             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2734             :   // Convert__Reg1_2__TypedVectorList3_8b1_0__Tie0_3_3__regXZR
    2735             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2736             :   // Convert__Reg1_2__TypedVectorList3_8b1_0__Tie0_3_3__Reg1_4
    2737             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2738             :   // Convert__Reg1_2__TypedVectorList3_8h1_0__Tie0_3_3__regXZR
    2739             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2740             :   // Convert__Reg1_2__TypedVectorList3_8h1_0__Tie0_3_3__Reg1_4
    2741             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2742             :   // Convert__Reg1_2__TypedVectorList2_16b1_0__Tie0_3_3__regXZR
    2743             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2744             :   // Convert__Reg1_2__TypedVectorList2_16b1_0__Tie0_3_3__Reg1_4
    2745             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2746             :   // Convert__Reg1_2__TypedVectorList2_1d1_0__Tie0_3_3__regXZR
    2747             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2748             :   // Convert__Reg1_2__TypedVectorList2_1d1_0__Tie0_3_3__Reg1_4
    2749             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2750             :   // Convert__Reg1_2__TypedVectorList2_2d1_0__Tie0_3_3__regXZR
    2751             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2752             :   // Convert__Reg1_2__TypedVectorList2_2d1_0__Tie0_3_3__Reg1_4
    2753             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2754             :   // Convert__Reg1_2__TypedVectorList2_2s1_0__Tie0_3_3__regXZR
    2755             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2756             :   // Convert__Reg1_2__TypedVectorList2_2s1_0__Tie0_3_3__Reg1_4
    2757             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2758             :   // Convert__Reg1_2__TypedVectorList2_4h1_0__Tie0_3_3__regXZR
    2759             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2760             :   // Convert__Reg1_2__TypedVectorList2_4h1_0__Tie0_3_3__Reg1_4
    2761             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2762             :   // Convert__Reg1_2__TypedVectorList2_4s1_0__Tie0_3_3__regXZR
    2763             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2764             :   // Convert__Reg1_2__TypedVectorList2_4s1_0__Tie0_3_3__Reg1_4
    2765             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2766             :   // Convert__Reg1_2__TypedVectorList2_8b1_0__Tie0_3_3__regXZR
    2767             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2768             :   // Convert__Reg1_2__TypedVectorList2_8b1_0__Tie0_3_3__Reg1_4
    2769             :   { CVT_95_Reg, 3, CVT_95_addVectorList64Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2770             :   // Convert__Reg1_2__TypedVectorList2_8h1_0__Tie0_3_3__regXZR
    2771             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    2772             :   // Convert__Reg1_2__TypedVectorList2_8h1_0__Tie0_3_3__Reg1_4
    2773             :   { CVT_95_Reg, 3, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    2774             :   // Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR
    2775             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2776             :   // Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5
    2777             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2778             :   // Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__regXZR
    2779             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2780             :   // Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__Reg1_5
    2781             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2782             :   // Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR
    2783             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2784             :   // Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5
    2785             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2786             :   // Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR
    2787             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2788             :   // Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5
    2789             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2790             :   // Convert__Reg1_3__VecListFour641_1__Tie0_4_4__regXZR
    2791             :   { CVT_95_Reg, 4, CVT_95_addVectorList64Operands_LT_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2792             :   // Convert__Reg1_3__VecListFour641_1__Tie0_4_4__Reg1_5
    2793             :   { CVT_95_Reg, 4, CVT_95_addVectorList64Operands_LT_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2794             :   // Convert__Reg1_3__VecListOne641_1__Tie0_4_4__regXZR
    2795             :   { CVT_95_Reg, 4, CVT_95_addVectorList64Operands_LT_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2796             :   // Convert__Reg1_3__VecListOne641_1__Tie0_4_4__Reg1_5
    2797             :   { CVT_95_Reg, 4, CVT_95_addVectorList64Operands_LT_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2798             :   // Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR
    2799             :   { CVT_95_Reg, 4, CVT_95_addVectorList64Operands_LT_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2800             :   // Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5
    2801             :   { CVT_95_Reg, 4, CVT_95_addVectorList64Operands_LT_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2802             :   // Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__regXZR
    2803             :   { CVT_95_Reg, 4, CVT_95_addVectorList64Operands_LT_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2804             :   // Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__Reg1_5
    2805             :   { CVT_95_Reg, 4, CVT_95_addVectorList64Operands_LT_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2806             :   // Convert__VecListOne1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4
    2807             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2808             :   // Convert__VecListOne1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4
    2809             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2810             :   // Convert__VecListOne1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4
    2811             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2812             :   // Convert__VecListOne1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4
    2813             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2814             :   // Convert__Reg1_3__TypedVectorList1_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR
    2815             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2816             :   // Convert__Reg1_3__TypedVectorList1_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5
    2817             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2818             :   // Convert__Reg1_3__TypedVectorList1_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR
    2819             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2820             :   // Convert__Reg1_3__TypedVectorList1_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5
    2821             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2822             :   // Convert__Reg1_3__TypedVectorList1_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR
    2823             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2824             :   // Convert__Reg1_3__TypedVectorList1_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5
    2825             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2826             :   // Convert__Reg1_3__TypedVectorList1_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR
    2827             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2828             :   // Convert__Reg1_3__TypedVectorList1_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5
    2829             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2830             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR
    2831             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2832             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6
    2833             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2834             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR
    2835             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2836             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6
    2837             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2838             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR
    2839             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2840             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6
    2841             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2842             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR
    2843             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2844             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6
    2845             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2846             :   // Convert__TypedVectorList2_0b1_0__Tie0_1_1__VectorIndexB1_1__Reg1_3
    2847             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2848             :   // Convert__TypedVectorList2_0d1_0__Tie0_1_1__VectorIndexD1_1__Reg1_3
    2849             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2850             :   // Convert__TypedVectorList2_0h1_0__Tie0_1_1__VectorIndexH1_1__Reg1_3
    2851             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2852             :   // Convert__TypedVectorList2_0s1_0__Tie0_1_1__VectorIndexS1_1__Reg1_3
    2853             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2854             :   // Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4
    2855             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2856             :   // Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4
    2857             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2858             :   // Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4
    2859             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2860             :   // Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4
    2861             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2862             :   // Convert__Reg1_3__TypedVectorList2_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR
    2863             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2864             :   // Convert__Reg1_3__TypedVectorList2_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5
    2865             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2866             :   // Convert__Reg1_3__TypedVectorList2_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR
    2867             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2868             :   // Convert__Reg1_3__TypedVectorList2_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5
    2869             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2870             :   // Convert__Reg1_3__TypedVectorList2_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR
    2871             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2872             :   // Convert__Reg1_3__TypedVectorList2_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5
    2873             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2874             :   // Convert__Reg1_3__TypedVectorList2_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR
    2875             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2876             :   // Convert__Reg1_3__TypedVectorList2_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5
    2877             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2878             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR
    2879             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2880             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6
    2881             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2882             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR
    2883             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2884             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6
    2885             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2886             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR
    2887             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2888             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6
    2889             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2890             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR
    2891             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2892             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6
    2893             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2894             :   // Convert__TypedVectorList3_0b1_0__Tie0_1_1__VectorIndexB1_1__Reg1_3
    2895             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2896             :   // Convert__TypedVectorList3_0d1_0__Tie0_1_1__VectorIndexD1_1__Reg1_3
    2897             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2898             :   // Convert__TypedVectorList3_0h1_0__Tie0_1_1__VectorIndexH1_1__Reg1_3
    2899             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2900             :   // Convert__TypedVectorList3_0s1_0__Tie0_1_1__VectorIndexS1_1__Reg1_3
    2901             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2902             :   // Convert__VecListThree1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4
    2903             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2904             :   // Convert__VecListThree1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4
    2905             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2906             :   // Convert__VecListThree1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4
    2907             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2908             :   // Convert__VecListThree1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4
    2909             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2910             :   // Convert__Reg1_3__TypedVectorList3_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR
    2911             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2912             :   // Convert__Reg1_3__TypedVectorList3_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5
    2913             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2914             :   // Convert__Reg1_3__TypedVectorList3_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR
    2915             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2916             :   // Convert__Reg1_3__TypedVectorList3_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5
    2917             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2918             :   // Convert__Reg1_3__TypedVectorList3_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR
    2919             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2920             :   // Convert__Reg1_3__TypedVectorList3_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5
    2921             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2922             :   // Convert__Reg1_3__TypedVectorList3_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR
    2923             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2924             :   // Convert__Reg1_3__TypedVectorList3_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5
    2925             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2926             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR
    2927             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2928             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6
    2929             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2930             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR
    2931             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2932             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6
    2933             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2934             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR
    2935             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2936             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6
    2937             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2938             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR
    2939             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2940             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6
    2941             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2942             :   // Convert__TypedVectorList4_0b1_0__Tie0_1_1__VectorIndexB1_1__Reg1_3
    2943             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2944             :   // Convert__TypedVectorList4_0d1_0__Tie0_1_1__VectorIndexD1_1__Reg1_3
    2945             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2946             :   // Convert__TypedVectorList4_0h1_0__Tie0_1_1__VectorIndexH1_1__Reg1_3
    2947             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2948             :   // Convert__TypedVectorList4_0s1_0__Tie0_1_1__VectorIndexS1_1__Reg1_3
    2949             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2950             :   // Convert__VecListFour1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4
    2951             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2952             :   // Convert__VecListFour1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4
    2953             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2954             :   // Convert__VecListFour1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4
    2955             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2956             :   // Convert__VecListFour1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4
    2957             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 5, CVT_Done },
    2958             :   // Convert__Reg1_3__TypedVectorList4_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR
    2959             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2960             :   // Convert__Reg1_3__TypedVectorList4_0b1_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5
    2961             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2962             :   // Convert__Reg1_3__TypedVectorList4_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR
    2963             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2964             :   // Convert__Reg1_3__TypedVectorList4_0d1_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5
    2965             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2966             :   // Convert__Reg1_3__TypedVectorList4_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR
    2967             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2968             :   // Convert__Reg1_3__TypedVectorList4_0h1_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5
    2969             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2970             :   // Convert__Reg1_3__TypedVectorList4_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR
    2971             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    2972             :   // Convert__Reg1_3__TypedVectorList4_0s1_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5
    2973             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    2974             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR
    2975             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2976             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6
    2977             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2978             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR
    2979             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2980             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6
    2981             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2982             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR
    2983             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2984             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6
    2985             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2986             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR
    2987             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    2988             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6
    2989             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    2990             :   // Convert__Reg1_1__Reg1_0__Reg1_3
    2991             :   { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_Done },
    2992             :   // Convert__Reg1_0__GPR64sp01_2
    2993             :   { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_Done },
    2994             :   // Convert__Reg1_0__Reg1_1__GPR64sp01_3
    2995             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands, 4, CVT_Done },
    2996             :   // Convert__Reg1_0__Reg1_1__Reg1_3__imm_95_0
    2997             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    2998             :   // Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s161_4
    2999             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addSImm7s16Operands, 5, CVT_Done },
    3000             :   // Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4
    3001             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addSImm7s4Operands, 5, CVT_Done },
    3002             :   // Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s81_4
    3003             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addSImm7s8Operands, 5, CVT_Done },
    3004             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s161_5
    3005             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addSImm7s16Operands, 6, CVT_Done },
    3006             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5
    3007             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addSImm7s4Operands, 6, CVT_Done },
    3008             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_5
    3009             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addSImm7s8Operands, 6, CVT_Done },
    3010             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s161_4
    3011             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addSImm7s16Operands, 5, CVT_Done },
    3012             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4
    3013             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addSImm7s4Operands, 5, CVT_Done },
    3014             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_4
    3015             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addSImm7s8Operands, 5, CVT_Done },
    3016             :   // Convert__Reg1_0__Reg1_2__imm_95_0
    3017             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3018             :   // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_4
    3019             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
    3020             :   // Convert__Reg1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    3021             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    3022             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB1281_3
    3023             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3024             :   // Convert__Reg1_0__Reg1_2__UImm12Offset161_3
    3025             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_16_GT_, 4, CVT_Done },
    3026             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB161_3
    3027             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3028             :   // Convert__Reg1_0__Reg1_2__UImm12Offset21_3
    3029             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_2_GT_, 4, CVT_Done },
    3030             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB321_3
    3031             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3032             :   // Convert__Reg1_0__Reg1_2__UImm12Offset41_3
    3033             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_4_GT_, 4, CVT_Done },
    3034             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB641_3
    3035             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3036             :   // Convert__Reg1_0__Reg1_2__UImm12Offset81_3
    3037             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_8_GT_, 4, CVT_Done },
    3038             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB81_3
    3039             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3040             :   // Convert__Reg1_0__Reg1_2__UImm12Offset11_3
    3041             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_1_GT_, 4, CVT_Done },
    3042             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend1282_4
    3043             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3044             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend1282_4
    3045             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3046             :   // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_3
    3047             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
    3048             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend162_4
    3049             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3050             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend162_4
    3051             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3052             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend322_4
    3053             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3054             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend322_4
    3055             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3056             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend642_4
    3057             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3058             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend642_4
    3059             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3060             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend82_4
    3061             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
    3062             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend82_4
    3063             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
    3064             :   // Convert__Reg1_0__Reg1_2__SImm10s81_3
    3065             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addSImm10s8Operands, 4, CVT_Done },
    3066             :   // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm10s81_3
    3067             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addSImm10s8Operands, 4, CVT_Done },
    3068             :   // Convert__Reg1_0__Reg1_2__SImm91_3
    3069             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3070             :   // Convert__Reg1_0__Reg1_1__Reg1_2__regWZR
    3071             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_regWZR, 0, CVT_Done },
    3072             :   // Convert__Reg1_0__Reg1_1__Reg1_2__regXZR
    3073             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_regXZR, 0, CVT_Done },
    3074             :   // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0
    3075             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    3076             :   // Convert__Reg1_0__regWZR__Reg1_1__imm_95_0
    3077             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
    3078             :   // Convert__Reg1_0__MOVZ32_lsl0MovAlias1_1__imm_95_0
    3079             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
    3080             :   // Convert__Reg1_0__MOVZ32_lsl16MovAlias1_1__imm_95_16
    3081             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
    3082             :   // Convert__Reg1_0__MOVN32_lsl0MovAlias1_1__imm_95_0
    3083             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
    3084             :   // Convert__Reg1_0__MOVN32_lsl16MovAlias1_1__imm_95_16
    3085             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
    3086             :   // Convert__Reg1_0__regWZR__LogicalImm321_1
    3087             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 2, CVT_Done },
    3088             :   // Convert__Reg1_0__regXZR__Reg1_1__imm_95_0
    3089             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
    3090             :   // Convert__Reg1_0__MOVZ64_lsl0MovAlias1_1__imm_95_0
    3091             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
    3092             :   // Convert__Reg1_0__MOVZ64_lsl16MovAlias1_1__imm_95_16
    3093             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
    3094             :   // Convert__Reg1_0__MOVZ64_lsl32MovAlias1_1__imm_95_32
    3095             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_32_GT_, 2, CVT_imm_95_32, 0, CVT_Done },
    3096             :   // Convert__Reg1_0__MOVZ64_lsl48MovAlias1_1__imm_95_48
    3097             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_48_GT_, 2, CVT_imm_95_48, 0, CVT_Done },
    3098             :   // Convert__Reg1_0__MOVN64_lsl0MovAlias1_1__imm_95_0
    3099             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
    3100             :   // Convert__Reg1_0__MOVN64_lsl16MovAlias1_1__imm_95_16
    3101             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
    3102             :   // Convert__Reg1_0__MOVN64_lsl32MovAlias1_1__imm_95_32
    3103             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_32_GT_, 2, CVT_imm_95_32, 0, CVT_Done },
    3104             :   // Convert__Reg1_0__MOVN64_lsl48MovAlias1_1__imm_95_48
    3105             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_48_GT_, 2, CVT_imm_95_48, 0, CVT_Done },
    3106             :   // Convert__Reg1_0__regXZR__LogicalImm641_1
    3107             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 2, CVT_Done },
    3108             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_2
    3109             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    3110             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_2
    3111             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    3112             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndexD1_3
    3113             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexDOperands, 4, CVT_Done },
    3114             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndexS1_3
    3115             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexSOperands, 4, CVT_Done },
    3116             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_2
    3117             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    3118             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_2
    3119             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    3120             :   // Convert__Reg1_0__SIMDImmType101_1
    3121             :   { CVT_95_Reg, 1, CVT_95_addSIMDImmType10Operands, 2, CVT_Done },
    3122             :   // Convert__VectorReg1281_1__Imm0_2551_2
    3123             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_Done },
    3124             :   // Convert__VectorReg1281_1__SIMDImmType101_2
    3125             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addSIMDImmType10Operands, 3, CVT_Done },
    3126             :   // Convert__VectorReg641_1__Imm0_2551_2__imm_95_0
    3127             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    3128             :   // Convert__VectorReg1281_1__Imm0_2551_2__imm_95_0
    3129             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    3130             :   // Convert__VectorReg641_1__Imm0_2551_2
    3131             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_Done },
    3132             :   // Convert__VectorReg1281_0__Imm0_2551_2
    3133             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_Done },
    3134             :   // Convert__VectorReg1281_0__SIMDImmType101_2
    3135             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addSIMDImmType10Operands, 3, CVT_Done },
    3136             :   // Convert__VectorReg1281_0__Imm0_2551_2__imm_95_0
    3137             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    3138             :   // Convert__VectorReg641_0__Imm0_2551_2__imm_95_0
    3139             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    3140             :   // Convert__VectorReg641_0__Imm0_2551_2
    3141             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_Done },
    3142             :   // Convert__VectorReg641_1__Imm0_2551_2__LogicalVecShifter1_3
    3143             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3144             :   // Convert__VectorReg641_1__Imm0_2551_2__MoveVecShifter1_3
    3145             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3146             :   // Convert__VectorReg641_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    3147             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3148             :   // Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecShifter1_3
    3149             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3150             :   // Convert__VectorReg1281_1__Imm0_2551_2__MoveVecShifter1_3
    3151             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3152             :   // Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    3153             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3154             :   // Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecShifter1_3
    3155             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3156             :   // Convert__VectorReg1281_0__Imm0_2551_2__MoveVecShifter1_3
    3157             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3158             :   // Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    3159             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3160             :   // Convert__VectorReg641_0__Imm0_2551_2__LogicalVecShifter1_3
    3161             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3162             :   // Convert__VectorReg641_0__Imm0_2551_2__MoveVecShifter1_3
    3163             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3164             :   // Convert__VectorReg641_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    3165             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImm0_95_255Operands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    3166             :   // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0
    3167             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_65535Operands, 2, CVT_imm_95_0, 0, CVT_Done },
    3168             :   // Convert__Reg1_0__Tie0_1_1__MovKSymbolG01_1__imm_95_0
    3169             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    3170             :   // Convert__Reg1_0__Tie0_1_1__MovKSymbolG11_1__imm_95_16
    3171             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_16, 0, CVT_Done },
    3172             :   // Convert__Reg1_0__Tie0_1_1__MovKSymbolG21_1__imm_95_32
    3173             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_32, 0, CVT_Done },
    3174             :   // Convert__Reg1_0__Tie0_1_1__MovKSymbolG31_1__imm_95_48
    3175             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_48, 0, CVT_Done },
    3176             :   // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm32Shifter1_2
    3177             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_65535Operands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3178             :   // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm64Shifter1_2
    3179             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_65535Operands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3180             :   // Convert__Reg1_0__Imm0_655351_1__imm_95_0
    3181             :   { CVT_95_Reg, 1, CVT_95_addImm0_95_65535Operands, 2, CVT_imm_95_0, 0, CVT_Done },
    3182             :   // Convert__Reg1_0__MovZSymbolG01_1__imm_95_0
    3183             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    3184             :   // Convert__Reg1_0__MovZSymbolG11_1__imm_95_16
    3185             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_16, 0, CVT_Done },
    3186             :   // Convert__Reg1_0__MovZSymbolG21_1__imm_95_32
    3187             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_32, 0, CVT_Done },
    3188             :   // Convert__Reg1_0__MovZSymbolG31_1__imm_95_48
    3189             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_48, 0, CVT_Done },
    3190             :   // Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2
    3191             :   { CVT_95_Reg, 1, CVT_95_addImm0_95_65535Operands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3192             :   // Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2
    3193             :   { CVT_95_Reg, 1, CVT_95_addImm0_95_65535Operands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3194             :   // Convert__Reg1_0__MRSSystemRegister1_1
    3195             :   { CVT_95_Reg, 1, CVT_95_addMRSSystemRegisterOperands, 2, CVT_Done },
    3196             :   // Convert__MSRSystemRegister1_0__Reg1_1
    3197             :   { CVT_95_addMSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
    3198             :   // Convert__SystemPStateFieldWithImm0_151_0__Imm0_151_1
    3199             :   { CVT_95_addSystemPStateFieldWithImm0_95_15Operands, 1, CVT_95_addImm0_95_15Operands, 2, CVT_Done },
    3200             :   // Convert__SystemPStateFieldWithImm0_11_0__Imm0_11_1
    3201             :   { CVT_95_addSystemPStateFieldWithImm0_95_1Operands, 1, CVT_95_addImm0_95_1Operands, 2, CVT_Done },
    3202             :   // Convert__Reg1_0__regWZR__Reg1_1__LogicalShifter321_2
    3203             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3204             :   // Convert__Reg1_0__regXZR__Reg1_1__LogicalShifter641_2
    3205             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3206             :   // Convert__Reg1_0__regWZR__Reg1_1__ArithmeticShifter321_2
    3207             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3208             :   // Convert__Reg1_0__regXZR__Reg1_1__ArithmeticShifter641_2
    3209             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3210             :   // Convert__Reg1_0__regWZR__Reg1_1
    3211             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_Done },
    3212             :   // Convert__Reg1_0__regXZR__Reg1_1
    3213             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_Done },
    3214             :   // Convert__VectorReg1281_1__VectorReg641_2__VectorReg641_3
    3215             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3216             :   // Convert__VectorReg1281_0__VectorReg641_2__VectorReg641_4
    3217             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    3218             :   // Convert__Prefetch1_0__PCRelLabel191_1
    3219             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
    3220             :   // Convert__Prefetch1_0__Reg1_2__imm_95_0
    3221             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3222             :   // Convert__Prefetch1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    3223             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    3224             :   // Convert__Prefetch1_0__Reg1_2__UImm12Offset81_3
    3225             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_8_GT_, 4, CVT_Done },
    3226             :   // Convert__Prefetch1_0__Reg1_2__Reg1_3__MemWExtend642_4
    3227             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3228             :   // Convert__Prefetch1_0__Reg1_2__Reg1_3__MemXExtend642_4
    3229             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    3230             :   // Convert__Prefetch1_0__Reg1_2__SImm91_3
    3231             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3232             :   // Convert__PSBHint1_0
    3233             :   { CVT_95_addPSBHintOperands, 1, CVT_Done },
    3234             :   // Convert__SVEPredicateHReg1_0__imm_95_31
    3235             :   { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    3236             :   // Convert__SVEPredicateSReg1_0__imm_95_31
    3237             :   { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    3238             :   // Convert__SVEPredicateDReg1_0__imm_95_31
    3239             :   { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    3240             :   // Convert__SVEPredicateBReg1_0__imm_95_31
    3241             :   { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    3242             :   // Convert__SVEPredicateHReg1_0__SVEPattern1_1
    3243             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    3244             :   // Convert__SVEPredicateSReg1_0__SVEPattern1_1
    3245             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    3246             :   // Convert__SVEPredicateDReg1_0__SVEPattern1_1
    3247             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    3248             :   // Convert__SVEPredicateBReg1_0__SVEPattern1_1
    3249             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    3250             :   // Convert__Reg1_0__SImm61_1
    3251             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
    3252             :   // Convert__regLR
    3253             :   { CVT_regLR, 0, CVT_Done },
    3254             :   // Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_311_2
    3255             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_31Operands, 3, CVT_Done },
    3256             :   // Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_631_2
    3257             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_63Operands, 3, CVT_Done },
    3258             :   // Convert__VectorReg641_1__VectorReg1281_2__Imm1_321_3
    3259             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_32Operands, 4, CVT_Done },
    3260             :   // Convert__VectorReg641_1__VectorReg1281_2__Imm1_161_3
    3261             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_16Operands, 4, CVT_Done },
    3262             :   // Convert__VectorReg641_1__VectorReg1281_2__Imm1_81_3
    3263             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_8Operands, 4, CVT_Done },
    3264             :   // Convert__VectorReg641_0__VectorReg1281_2__Imm1_321_4
    3265             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_32Operands, 5, CVT_Done },
    3266             :   // Convert__VectorReg641_0__VectorReg1281_2__Imm1_161_4
    3267             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_16Operands, 5, CVT_Done },
    3268             :   // Convert__VectorReg641_0__VectorReg1281_2__Imm1_81_4
    3269             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_8Operands, 5, CVT_Done },
    3270             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_81_3
    3271             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_8Operands, 4, CVT_Done },
    3272             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3
    3273             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_32Operands, 4, CVT_Done },
    3274             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_161_3
    3275             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_16Operands, 4, CVT_Done },
    3276             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4
    3277             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_8Operands, 5, CVT_Done },
    3278             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4
    3279             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_32Operands, 5, CVT_Done },
    3280             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4
    3281             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_16Operands, 5, CVT_Done },
    3282             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg641_3
    3283             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3284             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg641_4
    3285             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    3286             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2
    3287             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    3288             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2
    3289             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    3290             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg641_3
    3291             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3292             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg641_4
    3293             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    3294             :   // Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3
    3295             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_31Operands, 3, CVT_95_addImm0_95_31Operands, 4, CVT_Done },
    3296             :   // Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3
    3297             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_63Operands, 3, CVT_95_addImm0_95_63Operands, 4, CVT_Done },
    3298             :   // Convert__imm_95_0__imm_95_0__imm_95_0
    3299             :   { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    3300             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_1__VectorReg1281_2__VectorIndexS1_3
    3301             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexSOperands, 4, CVT_Done },
    3302             :   // Convert__imm_95_4
    3303             :   { CVT_imm_95_4, 0, CVT_Done },
    3304             :   // Convert__imm_95_5
    3305             :   { CVT_imm_95_5, 0, CVT_Done },
    3306             :   // Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3
    3307             :   { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3308             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2
    3309             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    3310             :   // Convert__Reg1_0__Reg1_1__Imm0_631_2
    3311             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_63Operands, 3, CVT_Done },
    3312             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_71_3
    3313             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_7Operands, 4, CVT_Done },
    3314             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_631_3
    3315             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_63Operands, 4, CVT_Done },
    3316             :   // Convert__VectorReg641_1__VectorReg641_2__Imm0_311_3
    3317             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_31Operands, 4, CVT_Done },
    3318             :   // Convert__VectorReg641_1__VectorReg641_2__Imm0_151_3
    3319             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_15Operands, 4, CVT_Done },
    3320             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_311_3
    3321             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_31Operands, 4, CVT_Done },
    3322             :   // Convert__VectorReg641_1__VectorReg641_2__Imm0_71_3
    3323             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_7Operands, 4, CVT_Done },
    3324             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_151_3
    3325             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_15Operands, 4, CVT_Done },
    3326             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_71_4
    3327             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_7Operands, 5, CVT_Done },
    3328             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_631_4
    3329             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_63Operands, 5, CVT_Done },
    3330             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_311_4
    3331             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_31Operands, 5, CVT_Done },
    3332             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_151_4
    3333             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_15Operands, 5, CVT_Done },
    3334             :   // Convert__VectorReg641_0__VectorReg641_2__Imm0_311_4
    3335             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_31Operands, 5, CVT_Done },
    3336             :   // Convert__VectorReg641_0__VectorReg641_2__Imm0_151_4
    3337             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_15Operands, 5, CVT_Done },
    3338             :   // Convert__VectorReg641_0__VectorReg641_2__Imm0_71_4
    3339             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_7Operands, 5, CVT_Done },
    3340             :   // Convert__VectorReg1281_1__VectorReg641_2
    3341             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    3342             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2
    3343             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImm0_95_63Operands, 3, CVT_Done },
    3344             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_71_3
    3345             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_7Operands, 4, CVT_Done },
    3346             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_631_3
    3347             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_63Operands, 4, CVT_Done },
    3348             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_311_3
    3349             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_31Operands, 4, CVT_Done },
    3350             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_151_3
    3351             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_15Operands, 4, CVT_Done },
    3352             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_311_3
    3353             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_31Operands, 4, CVT_Done },
    3354             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_71_3
    3355             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_7Operands, 4, CVT_Done },
    3356             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_151_3
    3357             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_15Operands, 4, CVT_Done },
    3358             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_71_4
    3359             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_7Operands, 5, CVT_Done },
    3360             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_631_4
    3361             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_63Operands, 5, CVT_Done },
    3362             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_311_4
    3363             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_31Operands, 5, CVT_Done },
    3364             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_151_4
    3365             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm0_95_15Operands, 5, CVT_Done },
    3366             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_311_4
    3367             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_31Operands, 5, CVT_Done },
    3368             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_151_4
    3369             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_15Operands, 5, CVT_Done },
    3370             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_71_4
    3371             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_7Operands, 5, CVT_Done },
    3372             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4
    3373             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    3374             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4
    3375             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    3376             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6
    3377             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexSOperands, 7, CVT_Done },
    3378             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6
    3379             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexHOperands, 7, CVT_Done },
    3380             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndexB1_3
    3381             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexBOperands, 4, CVT_Done },
    3382             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndexH1_3
    3383             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexHOperands, 4, CVT_Done },
    3384             :   // Convert__VectorReg1281_1__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4
    3385             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexSOperands, 5, CVT_Done },
    3386             :   // Convert__VectorReg1281_1__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4
    3387             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexHOperands, 5, CVT_Done },
    3388             :   // Convert__VectorReg1281_0__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6
    3389             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexSOperands, 7, CVT_Done },
    3390             :   // Convert__VectorReg1281_0__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6
    3391             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexHOperands, 7, CVT_Done },
    3392             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
    3393             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    3394             :   // Convert__Reg1_0__Reg1_1__Imm1_81_2
    3395             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm1_95_8Operands, 3, CVT_Done },
    3396             :   // Convert__Reg1_0__Reg1_1__Imm0_151_2
    3397             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_15Operands, 3, CVT_Done },
    3398             :   // Convert__Reg1_0__Reg1_1__Imm0_311_2
    3399             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_31Operands, 3, CVT_Done },
    3400             :   // Convert__Reg1_0__Reg1_1__Imm0_71_2
    3401             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImm0_95_7Operands, 3, CVT_Done },
    3402             :   // Convert__VectorReg641_1__VectorReg1281_2
    3403             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    3404             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm1_641_2
    3405             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImm1_95_64Operands, 3, CVT_Done },
    3406             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_641_3
    3407             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_64Operands, 4, CVT_Done },
    3408             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_321_3
    3409             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_32Operands, 4, CVT_Done },
    3410             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_161_3
    3411             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_16Operands, 4, CVT_Done },
    3412             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_81_3
    3413             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_8Operands, 4, CVT_Done },
    3414             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_641_4
    3415             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_64Operands, 5, CVT_Done },
    3416             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_321_4
    3417             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_32Operands, 5, CVT_Done },
    3418             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_161_4
    3419             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_16Operands, 5, CVT_Done },
    3420             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_81_4
    3421             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_8Operands, 5, CVT_Done },
    3422             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_81_3
    3423             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_8Operands, 4, CVT_Done },
    3424             :   // Convert__VectorReg641_1__VectorReg641_2__Imm1_81_3
    3425             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_8Operands, 4, CVT_Done },
    3426             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_81_4
    3427             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImm1_95_8Operands, 5, CVT_Done },
    3428             :   // Convert__VectorReg641_0__VectorReg641_2__Imm1_81_4
    3429             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm1_95_8Operands, 5, CVT_Done },
    3430             :   // Convert__VectorReg1281_1__VectorReg641_2__Imm0_311_3
    3431             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_31Operands, 4, CVT_Done },
    3432             :   // Convert__VectorReg1281_1__VectorReg641_2__Imm0_151_3
    3433             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_15Operands, 4, CVT_Done },
    3434             :   // Convert__VectorReg1281_1__VectorReg641_2__Imm0_71_3
    3435             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_7Operands, 4, CVT_Done },
    3436             :   // Convert__VectorReg1281_0__VectorReg641_2__Imm0_311_4
    3437             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_31Operands, 5, CVT_Done },
    3438             :   // Convert__VectorReg1281_0__VectorReg641_2__Imm0_151_4
    3439             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_15Operands, 5, CVT_Done },
    3440             :   // Convert__VectorReg1281_0__VectorReg641_2__Imm0_71_4
    3441             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImm0_95_7Operands, 5, CVT_Done },
    3442             :   // Convert__TypedVectorList1_0b1_0__VectorIndexB1_1__Reg1_3
    3443             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3444             :   // Convert__TypedVectorList1_0d1_0__VectorIndexD1_1__Reg1_3
    3445             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3446             :   // Convert__TypedVectorList1_0h1_0__VectorIndexH1_1__Reg1_3
    3447             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3448             :   // Convert__TypedVectorList1_0s1_0__VectorIndexS1_1__Reg1_3
    3449             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3450             :   // Convert__VecListOne1281_1__VectorIndexB1_2__Reg1_4
    3451             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3452             :   // Convert__VecListOne1281_1__VectorIndexD1_2__Reg1_4
    3453             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3454             :   // Convert__VecListOne1281_1__VectorIndexH1_2__Reg1_4
    3455             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3456             :   // Convert__VecListOne1281_1__VectorIndexS1_2__Reg1_4
    3457             :   { CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3458             :   // Convert__Reg1_3__TypedVectorList1_0b1_0__VectorIndexB1_1__Tie0_4_4__regXZR
    3459             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3460             :   // Convert__Reg1_3__TypedVectorList1_0b1_0__VectorIndexB1_1__Tie0_4_4__Reg1_5
    3461             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3462             :   // Convert__Reg1_3__TypedVectorList1_0d1_0__VectorIndexD1_1__Tie0_4_4__regXZR
    3463             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3464             :   // Convert__Reg1_3__TypedVectorList1_0d1_0__VectorIndexD1_1__Tie0_4_4__Reg1_5
    3465             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3466             :   // Convert__Reg1_3__TypedVectorList1_0h1_0__VectorIndexH1_1__Tie0_4_4__regXZR
    3467             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3468             :   // Convert__Reg1_3__TypedVectorList1_0h1_0__VectorIndexH1_1__Tie0_4_4__Reg1_5
    3469             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3470             :   // Convert__Reg1_3__TypedVectorList1_0s1_0__VectorIndexS1_1__Tie0_4_4__regXZR
    3471             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3472             :   // Convert__Reg1_3__TypedVectorList1_0s1_0__VectorIndexS1_1__Tie0_4_4__Reg1_5
    3473             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_1_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3474             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexB1_2__Tie0_5_5__regXZR
    3475             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3476             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6
    3477             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3478             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexD1_2__Tie0_5_5__regXZR
    3479             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3480             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6
    3481             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3482             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexH1_2__Tie0_5_5__regXZR
    3483             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3484             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6
    3485             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3486             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexS1_2__Tie0_5_5__regXZR
    3487             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3488             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6
    3489             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_1_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3490             :   // Convert__TypedVectorList2_0b1_0__VectorIndexB1_1__Reg1_3
    3491             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3492             :   // Convert__TypedVectorList2_0d1_0__VectorIndexD1_1__Reg1_3
    3493             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3494             :   // Convert__TypedVectorList2_0h1_0__VectorIndexH1_1__Reg1_3
    3495             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3496             :   // Convert__TypedVectorList2_0s1_0__VectorIndexS1_1__Reg1_3
    3497             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3498             :   // Convert__VecListTwo1281_1__VectorIndexB1_2__Reg1_4
    3499             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3500             :   // Convert__VecListTwo1281_1__VectorIndexD1_2__Reg1_4
    3501             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3502             :   // Convert__VecListTwo1281_1__VectorIndexH1_2__Reg1_4
    3503             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3504             :   // Convert__VecListTwo1281_1__VectorIndexS1_2__Reg1_4
    3505             :   { CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3506             :   // Convert__Reg1_3__TypedVectorList2_0b1_0__VectorIndexB1_1__Tie0_4_4__regXZR
    3507             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3508             :   // Convert__Reg1_3__TypedVectorList2_0b1_0__VectorIndexB1_1__Tie0_4_4__Reg1_5
    3509             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3510             :   // Convert__Reg1_3__TypedVectorList2_0d1_0__VectorIndexD1_1__Tie0_4_4__regXZR
    3511             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3512             :   // Convert__Reg1_3__TypedVectorList2_0d1_0__VectorIndexD1_1__Tie0_4_4__Reg1_5
    3513             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3514             :   // Convert__Reg1_3__TypedVectorList2_0h1_0__VectorIndexH1_1__Tie0_4_4__regXZR
    3515             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3516             :   // Convert__Reg1_3__TypedVectorList2_0h1_0__VectorIndexH1_1__Tie0_4_4__Reg1_5
    3517             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3518             :   // Convert__Reg1_3__TypedVectorList2_0s1_0__VectorIndexS1_1__Tie0_4_4__regXZR
    3519             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3520             :   // Convert__Reg1_3__TypedVectorList2_0s1_0__VectorIndexS1_1__Tie0_4_4__Reg1_5
    3521             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_2_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3522             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexB1_2__Tie0_5_5__regXZR
    3523             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3524             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6
    3525             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3526             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexD1_2__Tie0_5_5__regXZR
    3527             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3528             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6
    3529             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3530             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexH1_2__Tie0_5_5__regXZR
    3531             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3532             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6
    3533             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3534             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexS1_2__Tie0_5_5__regXZR
    3535             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3536             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6
    3537             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_2_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3538             :   // Convert__TypedVectorList3_0b1_0__VectorIndexB1_1__Reg1_3
    3539             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3540             :   // Convert__TypedVectorList3_0d1_0__VectorIndexD1_1__Reg1_3
    3541             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3542             :   // Convert__TypedVectorList3_0h1_0__VectorIndexH1_1__Reg1_3
    3543             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3544             :   // Convert__TypedVectorList3_0s1_0__VectorIndexS1_1__Reg1_3
    3545             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3546             :   // Convert__VecListThree1281_1__VectorIndexB1_2__Reg1_4
    3547             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3548             :   // Convert__VecListThree1281_1__VectorIndexD1_2__Reg1_4
    3549             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3550             :   // Convert__VecListThree1281_1__VectorIndexH1_2__Reg1_4
    3551             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3552             :   // Convert__VecListThree1281_1__VectorIndexS1_2__Reg1_4
    3553             :   { CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3554             :   // Convert__Reg1_3__TypedVectorList3_0b1_0__VectorIndexB1_1__Tie0_4_4__regXZR
    3555             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3556             :   // Convert__Reg1_3__TypedVectorList3_0b1_0__VectorIndexB1_1__Tie0_4_4__Reg1_5
    3557             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3558             :   // Convert__Reg1_3__TypedVectorList3_0d1_0__VectorIndexD1_1__Tie0_4_4__regXZR
    3559             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3560             :   // Convert__Reg1_3__TypedVectorList3_0d1_0__VectorIndexD1_1__Tie0_4_4__Reg1_5
    3561             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3562             :   // Convert__Reg1_3__TypedVectorList3_0h1_0__VectorIndexH1_1__Tie0_4_4__regXZR
    3563             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3564             :   // Convert__Reg1_3__TypedVectorList3_0h1_0__VectorIndexH1_1__Tie0_4_4__Reg1_5
    3565             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3566             :   // Convert__Reg1_3__TypedVectorList3_0s1_0__VectorIndexS1_1__Tie0_4_4__regXZR
    3567             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3568             :   // Convert__Reg1_3__TypedVectorList3_0s1_0__VectorIndexS1_1__Tie0_4_4__Reg1_5
    3569             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_3_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3570             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexB1_2__Tie0_5_5__regXZR
    3571             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3572             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6
    3573             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3574             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexD1_2__Tie0_5_5__regXZR
    3575             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3576             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6
    3577             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3578             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexH1_2__Tie0_5_5__regXZR
    3579             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3580             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6
    3581             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3582             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexS1_2__Tie0_5_5__regXZR
    3583             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3584             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6
    3585             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_3_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3586             :   // Convert__TypedVectorList4_0b1_0__VectorIndexB1_1__Reg1_3
    3587             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3588             :   // Convert__TypedVectorList4_0d1_0__VectorIndexD1_1__Reg1_3
    3589             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3590             :   // Convert__TypedVectorList4_0h1_0__VectorIndexH1_1__Reg1_3
    3591             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3592             :   // Convert__TypedVectorList4_0s1_0__VectorIndexS1_1__Reg1_3
    3593             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3594             :   // Convert__VecListFour1281_1__VectorIndexB1_2__Reg1_4
    3595             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3596             :   // Convert__VecListFour1281_1__VectorIndexD1_2__Reg1_4
    3597             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3598             :   // Convert__VecListFour1281_1__VectorIndexH1_2__Reg1_4
    3599             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3600             :   // Convert__VecListFour1281_1__VectorIndexS1_2__Reg1_4
    3601             :   { CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3602             :   // Convert__Reg1_3__TypedVectorList4_0b1_0__VectorIndexB1_1__Tie0_4_4__regXZR
    3603             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3604             :   // Convert__Reg1_3__TypedVectorList4_0b1_0__VectorIndexB1_1__Tie0_4_4__Reg1_5
    3605             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexBOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3606             :   // Convert__Reg1_3__TypedVectorList4_0d1_0__VectorIndexD1_1__Tie0_4_4__regXZR
    3607             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3608             :   // Convert__Reg1_3__TypedVectorList4_0d1_0__VectorIndexD1_1__Tie0_4_4__Reg1_5
    3609             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexDOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3610             :   // Convert__Reg1_3__TypedVectorList4_0h1_0__VectorIndexH1_1__Tie0_4_4__regXZR
    3611             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3612             :   // Convert__Reg1_3__TypedVectorList4_0h1_0__VectorIndexH1_1__Tie0_4_4__Reg1_5
    3613             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexHOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3614             :   // Convert__Reg1_3__TypedVectorList4_0s1_0__VectorIndexS1_1__Tie0_4_4__regXZR
    3615             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3616             :   // Convert__Reg1_3__TypedVectorList4_0s1_0__VectorIndexS1_1__Tie0_4_4__Reg1_5
    3617             :   { CVT_95_Reg, 4, CVT_95_addVectorList128Operands_LT_4_GT_, 1, CVT_95_addVectorIndexSOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3618             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexB1_2__Tie0_5_5__regXZR
    3619             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3620             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6
    3621             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexBOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3622             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexD1_2__Tie0_5_5__regXZR
    3623             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3624             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6
    3625             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexDOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3626             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexH1_2__Tie0_5_5__regXZR
    3627             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3628             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6
    3629             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexHOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3630             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexS1_2__Tie0_5_5__regXZR
    3631             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3632             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6
    3633             :   { CVT_95_Reg, 5, CVT_95_addVectorList128Operands_LT_4_GT_, 2, CVT_95_addVectorIndexSOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3634             :   // Convert__regWZR__Reg1_0__Reg1_2
    3635             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
    3636             :   // Convert__regXZR__Reg1_0__Reg1_2
    3637             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
    3638             :   // Convert__Reg1_0__Reg1_1__Reg1_2__GPR64sp01_4
    3639             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 5, CVT_Done },
    3640             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1
    3641             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
    3642             :   // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7
    3643             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_7, 0, CVT_Done },
    3644             :   // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15
    3645             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_15, 0, CVT_Done },
    3646             :   // Convert__VectorReg1281_1__VectorReg641_2__imm_95_0
    3647             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    3648             :   // Convert__VectorReg1281_0__VectorReg641_2__imm_95_0
    3649             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    3650             :   // Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0
    3651             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    3652             :   // Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0
    3653             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    3654             :   // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_31
    3655             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done },
    3656             :   // Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__regXZR
    3657             :   { CVT_95_addImm0_95_7Operands, 1, CVT_95_addSysCROperands, 2, CVT_95_addSysCROperands, 3, CVT_95_addImm0_95_7Operands, 4, CVT_regXZR, 0, CVT_Done },
    3658             :   // Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__Reg1_4
    3659             :   { CVT_95_addImm0_95_7Operands, 1, CVT_95_addSysCROperands, 2, CVT_95_addSysCROperands, 3, CVT_95_addImm0_95_7Operands, 4, CVT_95_Reg, 5, CVT_Done },
    3660             :   // Convert__Reg1_0__Imm0_71_1__SysCR1_2__SysCR1_3__Imm0_71_4
    3661             :   { CVT_95_Reg, 1, CVT_95_addImm0_95_7Operands, 2, CVT_95_addSysCROperands, 3, CVT_95_addSysCROperands, 4, CVT_95_addImm0_95_7Operands, 5, CVT_Done },
    3662             :   // Convert__VectorReg1281_1__VecListFour1281_2__VectorReg1281_3
    3663             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorList128Operands_LT_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3664             :   // Convert__VectorReg1281_1__VecListOne1281_2__VectorReg1281_3
    3665             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorList128Operands_LT_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3666             :   // Convert__VectorReg1281_1__VecListThree1281_2__VectorReg1281_3
    3667             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorList128Operands_LT_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3668             :   // Convert__VectorReg1281_1__VecListTwo1281_2__VectorReg1281_3
    3669             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorList128Operands_LT_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3670             :   // Convert__VectorReg641_1__VecListFour1281_2__VectorReg641_3
    3671             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorList128Operands_LT_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3672             :   // Convert__VectorReg641_1__VecListOne1281_2__VectorReg641_3
    3673             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorList128Operands_LT_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3674             :   // Convert__VectorReg641_1__VecListThree1281_2__VectorReg641_3
    3675             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorList128Operands_LT_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3676             :   // Convert__VectorReg641_1__VecListTwo1281_2__VectorReg641_3
    3677             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorList128Operands_LT_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3678             :   // Convert__VectorReg1281_0__TypedVectorList4_16b1_2__VectorReg1281_3
    3679             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorList128Operands_LT_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3680             :   // Convert__VectorReg1281_0__TypedVectorList1_16b1_2__VectorReg1281_3
    3681             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorList128Operands_LT_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3682             :   // Convert__VectorReg1281_0__TypedVectorList3_16b1_2__VectorReg1281_3
    3683             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorList128Operands_LT_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3684             :   // Convert__VectorReg1281_0__TypedVectorList2_16b1_2__VectorReg1281_3
    3685             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorList128Operands_LT_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3686             :   // Convert__VectorReg641_0__TypedVectorList4_16b1_2__VectorReg641_3
    3687             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorList128Operands_LT_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3688             :   // Convert__VectorReg641_0__TypedVectorList1_16b1_2__VectorReg641_3
    3689             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorList128Operands_LT_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3690             :   // Convert__VectorReg641_0__TypedVectorList3_16b1_2__VectorReg641_3
    3691             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorList128Operands_LT_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3692             :   // Convert__VectorReg641_0__TypedVectorList2_16b1_2__VectorReg641_3
    3693             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorList128Operands_LT_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3694             :   // Convert__Reg1_0__Imm0_311_1__BranchTarget141_2
    3695             :   { CVT_95_Reg, 1, CVT_95_addImm0_95_31Operands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
    3696             :   // Convert__Reg1_0__Imm32_631_1__BranchTarget141_2
    3697             :   { CVT_95_Reg, 1, CVT_95_addImm32_95_63Operands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
    3698             :   // Convert__GPR32as641_0__TBZImm0_311_1__BranchTarget141_2
    3699             :   { CVT_95_addGPR32as64Operands, 1, CVT_95_addImm0_95_31Operands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
    3700             :   // Convert__VectorReg1281_1__Tie0_2_2__VecListFour1281_2__VectorReg1281_3
    3701             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorList128Operands_LT_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3702             :   // Convert__VectorReg1281_1__Tie0_2_2__VecListOne1281_2__VectorReg1281_3
    3703             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorList128Operands_LT_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3704             :   // Convert__VectorReg1281_1__Tie0_2_2__VecListThree1281_2__VectorReg1281_3
    3705             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorList128Operands_LT_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3706             :   // Convert__VectorReg1281_1__Tie0_2_2__VecListTwo1281_2__VectorReg1281_3
    3707             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorList128Operands_LT_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3708             :   // Convert__VectorReg641_1__Tie0_2_2__VecListFour1281_2__VectorReg641_3
    3709             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorList128Operands_LT_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3710             :   // Convert__VectorReg641_1__Tie0_2_2__VecListOne1281_2__VectorReg641_3
    3711             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorList128Operands_LT_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3712             :   // Convert__VectorReg641_1__Tie0_2_2__VecListThree1281_2__VectorReg641_3
    3713             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorList128Operands_LT_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3714             :   // Convert__VectorReg641_1__Tie0_2_2__VecListTwo1281_2__VectorReg641_3
    3715             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorList128Operands_LT_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3716             :   // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList4_16b1_2__VectorReg1281_3
    3717             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorList128Operands_LT_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3718             :   // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList1_16b1_2__VectorReg1281_3
    3719             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorList128Operands_LT_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3720             :   // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList3_16b1_2__VectorReg1281_3
    3721             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorList128Operands_LT_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3722             :   // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList2_16b1_2__VectorReg1281_3
    3723             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorList128Operands_LT_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    3724             :   // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList4_16b1_2__VectorReg641_3
    3725             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorList128Operands_LT_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3726             :   // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList1_16b1_2__VectorReg641_3
    3727             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorList128Operands_LT_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3728             :   // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList3_16b1_2__VectorReg641_3
    3729             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorList128Operands_LT_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3730             :   // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList2_16b1_2__VectorReg641_3
    3731             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorList128Operands_LT_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    3732             :   // Convert__regWZR__Reg1_0__LogicalImm321_1
    3733             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 2, CVT_Done },
    3734             :   // Convert__regXZR__Reg1_0__LogicalImm641_1
    3735             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 2, CVT_Done },
    3736             :   // Convert__regWZR__Reg1_0__Reg1_1__LogicalShifter321_2
    3737             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3738             :   // Convert__regXZR__Reg1_0__Reg1_1__LogicalShifter641_2
    3739             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    3740             :   // Convert__imm_95_2
    3741             :   { CVT_imm_95_2, 0, CVT_Done },
    3742             :   // Convert__imm_95_3
    3743             :   { CVT_imm_95_3, 0, CVT_Done },
    3744             :   // Convert__imm_95_1
    3745             :   { CVT_imm_95_1, 0, CVT_Done },
    3746             :   // Convert__SVEPredicateHReg1_0__SVEPredicateHReg1_1__SVEPredicateHReg1_2
    3747             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    3748             :   // Convert__SVEPredicateSReg1_0__SVEPredicateSReg1_1__SVEPredicateSReg1_2
    3749             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    3750             :   // Convert__SVEPredicateDReg1_0__SVEPredicateDReg1_1__SVEPredicateDReg1_2
    3751             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    3752             :   // Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1__SVEPredicateBReg1_2
    3753             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    3754             : };
    3755             : 
    3756       13323 : void AArch64AsmParser::
    3757             : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
    3758             :                 const OperandVector &Operands) {
    3759             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    3760       13323 :   const uint8_t *Converter = ConversionTable[Kind];
    3761             :   unsigned OpIdx;
    3762             :   Inst.setOpcode(Opcode);
    3763       92345 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    3764       39511 :     OpIdx = *(p + 1);
    3765       39511 :     switch (*p) {
    3766           0 :     default: llvm_unreachable("invalid conversion entry!");
    3767           0 :     case CVT_Reg:
    3768           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    3769             :       break;
    3770        2408 :     case CVT_Tied: {
    3771             :       assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
    3772             :                           std::begin(TiedAsmOperandTable)) &&
    3773             :              "Tied operand not found");
    3774        2408 :       unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
    3775             :       Inst.addOperand(Inst.getOperand(TiedResOpnd));
    3776             :       break;
    3777             :     }
    3778       17772 :     case CVT_95_Reg:
    3779       35544 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    3780             :       break;
    3781        3694 :     case CVT_95_addVectorReg128Operands:
    3782        7388 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorReg128Operands(Inst, 1);
    3783             :       break;
    3784        2371 :     case CVT_95_addVectorReg64Operands:
    3785        4742 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorReg64Operands(Inst, 1);
    3786             :       break;
    3787             :     case CVT_imm_95_16:
    3788         164 :       Inst.addOperand(MCOperand::createImm(16));
    3789             :       break;
    3790             :     case CVT_imm_95_24:
    3791           8 :       Inst.addOperand(MCOperand::createImm(24));
    3792             :       break;
    3793             :     case CVT_imm_95_0:
    3794        1180 :       Inst.addOperand(MCOperand::createImm(0));
    3795             :       break;
    3796          20 :     case CVT_95_addAddSubImmNegOperands:
    3797          40 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addAddSubImmNegOperands(Inst, 2);
    3798             :       break;
    3799         454 :     case CVT_95_addAddSubImmOperands:
    3800         908 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addAddSubImmOperands(Inst, 2);
    3801             :       break;
    3802        1428 :     case CVT_95_addRegOperands:
    3803        2856 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    3804             :       break;
    3805         396 :     case CVT_95_addShifterOperands:
    3806         792 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addShifterOperands(Inst, 1);
    3807             :       break;
    3808         155 :     case CVT_95_addExtendOperands:
    3809         310 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addExtendOperands(Inst, 1);
    3810             :       break;
    3811          54 :     case CVT_95_addExtend64Operands:
    3812         108 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addExtend64Operands(Inst, 1);
    3813             :       break;
    3814         747 :     case CVT_95_addImmOperands:
    3815         747 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    3816             :       break;
    3817          25 :     case CVT_95_addAdrLabelOperands:
    3818          25 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
    3819             :       break;
    3820         171 :     case CVT_95_addAdrpLabelOperands:
    3821         342 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addAdrpLabelOperands(Inst, 1);
    3822             :       break;
    3823          45 :     case CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_:
    3824          90 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int32_t>(Inst, 1);
    3825             :       break;
    3826          51 :     case CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_:
    3827         102 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int64_t>(Inst, 1);
    3828             :       break;
    3829           3 :     case CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_:
    3830           6 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int16_t>(Inst, 1);
    3831             :       break;
    3832           3 :     case CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_:
    3833           6 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int8_t>(Inst, 1);
    3834             :       break;
    3835         185 :     case CVT_95_addImm0_95_31Operands:
    3836         185 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm0_31Operands(Inst, 1);
    3837             :       break;
    3838             :     case CVT_imm_95_31:
    3839          70 :       Inst.addOperand(MCOperand::createImm(31));
    3840             :       break;
    3841         134 :     case CVT_95_addImm0_95_63Operands:
    3842         134 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm0_63Operands(Inst, 1);
    3843             :       break;
    3844             :     case CVT_imm_95_63:
    3845           4 :       Inst.addOperand(MCOperand::createImm(63));
    3846             :       break;
    3847          63 :     case CVT_95_addBranchTarget26Operands:
    3848         126 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addBranchTarget26Operands(Inst, 1);
    3849             :       break;
    3850         241 :     case CVT_95_addCondCodeOperands:
    3851         241 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 1);
    3852             :       break;
    3853         177 :     case CVT_95_addPCRelLabel19Operands:
    3854         354 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addPCRelLabel19Operands(Inst, 1);
    3855             :       break;
    3856         144 :     case CVT_95_addImm0_95_255Operands:
    3857         144 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm0_255Operands(Inst, 1);
    3858             :       break;
    3859           7 :     case CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_:
    3860          14 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int32_t>(Inst, 1);
    3861             :       break;
    3862           9 :     case CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_:
    3863          18 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int64_t>(Inst, 1);
    3864             :       break;
    3865           3 :     case CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_:
    3866           6 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int16_t>(Inst, 1);
    3867             :       break;
    3868           3 :     case CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_:
    3869           6 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int8_t>(Inst, 1);
    3870             :       break;
    3871          65 :     case CVT_95_addImm0_95_65535Operands:
    3872          65 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm0_65535Operands(Inst, 1);
    3873             :       break;
    3874         103 :     case CVT_95_addImm0_95_15Operands:
    3875         103 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm0_15Operands(Inst, 1);
    3876             :       break;
    3877             :     case CVT_imm_95_15:
    3878          22 :       Inst.addOperand(MCOperand::createImm(15));
    3879             :       break;
    3880             :     case CVT_regWZR:
    3881         944 :       Inst.addOperand(MCOperand::createReg(AArch64::WZR));
    3882             :       break;
    3883             :     case CVT_regXZR:
    3884        1506 :       Inst.addOperand(MCOperand::createReg(AArch64::XZR));
    3885             :       break;
    3886             :     case CVT_imm_95_20:
    3887           2 :       Inst.addOperand(MCOperand::createImm(20));
    3888             :       break;
    3889          45 :     case CVT_95_addBarrierOperands:
    3890          45 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addBarrierOperands(Inst, 1);
    3891             :       break;
    3892         203 :     case CVT_95_addVectorIndexHOperands:
    3893         203 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorIndexHOperands(Inst, 1);
    3894             :       break;
    3895         278 :     case CVT_95_addVectorIndexSOperands:
    3896         278 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorIndexSOperands(Inst, 1);
    3897             :       break;
    3898         135 :     case CVT_95_addVectorIndexDOperands:
    3899         135 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorIndexDOperands(Inst, 1);
    3900             :       break;
    3901         101 :     case CVT_95_addVectorIndexBOperands:
    3902         101 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorIndexBOperands(Inst, 1);
    3903             :       break;
    3904          12 :     case CVT_95_addComplexRotationOddOperands:
    3905          24 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
    3906             :       break;
    3907          30 :     case CVT_95_addComplexRotationEvenOperands:
    3908          30 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
    3909             :       break;
    3910         108 :     case CVT_95_addImm1_95_16Operands:
    3911         108 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1);
    3912             :       break;
    3913         164 :     case CVT_95_addImm1_95_32Operands:
    3914         164 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1);
    3915             :       break;
    3916          96 :     case CVT_95_addImm1_95_64Operands:
    3917          96 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm1_64Operands(Inst, 1);
    3918             :       break;
    3919         101 :     case CVT_95_addVectorRegLoOperands:
    3920         202 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorRegLoOperands(Inst, 1);
    3921             :       break;
    3922          31 :     case CVT_95_addFPImmOperands:
    3923          31 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
    3924             :       break;
    3925          11 :     case CVT_95_addVectorIndex1Operands:
    3926          11 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorIndex1Operands(Inst, 1);
    3927             :       break;
    3928           2 :     case CVT_95_addImm0_95_127Operands:
    3929           2 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm0_127Operands(Inst, 1);
    3930             :       break;
    3931         253 :     case CVT_95_addVectorList128Operands_LT_4_GT_:
    3932         506 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorList128Operands<4>(Inst, 1);
    3933             :       break;
    3934         161 :     case CVT_95_addVectorList64Operands_LT_4_GT_:
    3935         322 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorList64Operands<4>(Inst, 1);
    3936             :       break;
    3937         174 :     case CVT_95_addVectorList128Operands_LT_1_GT_:
    3938         348 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorList128Operands<1>(Inst, 1);
    3939             :       break;
    3940          97 :     case CVT_95_addVectorList64Operands_LT_1_GT_:
    3941         194 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorList64Operands<1>(Inst, 1);
    3942             :       break;
    3943         258 :     case CVT_95_addVectorList128Operands_LT_3_GT_:
    3944         516 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorList128Operands<3>(Inst, 1);
    3945             :       break;
    3946         165 :     case CVT_95_addVectorList64Operands_LT_3_GT_:
    3947         330 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorList64Operands<3>(Inst, 1);
    3948             :       break;
    3949         251 :     case CVT_95_addVectorList128Operands_LT_2_GT_:
    3950         502 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorList128Operands<2>(Inst, 1);
    3951             :       break;
    3952         159 :     case CVT_95_addVectorList64Operands_LT_2_GT_:
    3953         318 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorList64Operands<2>(Inst, 1);
    3954             :       break;
    3955          16 :     case CVT_95_addSImm7s16Operands:
    3956          16 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSImm7s16Operands(Inst, 1);
    3957             :       break;
    3958          63 :     case CVT_95_addSImm7s4Operands:
    3959          63 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSImm7s4Operands(Inst, 1);
    3960             :       break;
    3961          68 :     case CVT_95_addSImm7s8Operands:
    3962          68 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSImm7s8Operands(Inst, 1);
    3963             :       break;
    3964          52 :     case CVT_95_addUImm12OffsetOperands_LT_16_GT_:
    3965         104 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<16>(Inst, 1);
    3966             :       break;
    3967         116 :     case CVT_95_addUImm12OffsetOperands_LT_2_GT_:
    3968         232 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<2>(Inst, 1);
    3969             :       break;
    3970         125 :     case CVT_95_addUImm12OffsetOperands_LT_4_GT_:
    3971         250 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<4>(Inst, 1);
    3972             :       break;
    3973         225 :     case CVT_95_addUImm12OffsetOperands_LT_8_GT_:
    3974         450 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<8>(Inst, 1);
    3975             :       break;
    3976         113 :     case CVT_95_addUImm12OffsetOperands_LT_1_GT_:
    3977         226 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<1>(Inst, 1);
    3978             :       break;
    3979          58 :     case CVT_95_addMemExtendOperands:
    3980         116 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMemExtendOperands(Inst, 2);
    3981             :       break;
    3982           8 :     case CVT_95_addMemExtend8Operands:
    3983          16 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMemExtend8Operands(Inst, 2);
    3984             :       break;
    3985           8 :     case CVT_95_addSImm10s8Operands:
    3986           8 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSImm10s8Operands(Inst, 1);
    3987             :       break;
    3988           8 :     case CVT_95_addMOVZMovAliasOperands_LT_0_GT_:
    3989           8 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<0>(Inst, 1);
    3990             :       break;
    3991           0 :     case CVT_95_addMOVZMovAliasOperands_LT_16_GT_:
    3992           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<16>(Inst, 1);
    3993             :       break;
    3994           5 :     case CVT_95_addMOVNMovAliasOperands_LT_0_GT_:
    3995          10 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<0>(Inst, 1);
    3996             :       break;
    3997           0 :     case CVT_95_addMOVNMovAliasOperands_LT_16_GT_:
    3998           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<16>(Inst, 1);
    3999             :       break;
    4000           1 :     case CVT_95_addMOVZMovAliasOperands_LT_32_GT_:
    4001           2 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<32>(Inst, 1);
    4002             :       break;
    4003             :     case CVT_imm_95_32:
    4004          84 :       Inst.addOperand(MCOperand::createImm(32));
    4005             :       break;
    4006           0 :     case CVT_95_addMOVZMovAliasOperands_LT_48_GT_:
    4007           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<48>(Inst, 1);
    4008             :       break;
    4009             :     case CVT_imm_95_48:
    4010          24 :       Inst.addOperand(MCOperand::createImm(48));
    4011             :       break;
    4012           0 :     case CVT_95_addMOVNMovAliasOperands_LT_32_GT_:
    4013           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<32>(Inst, 1);
    4014             :       break;
    4015           0 :     case CVT_95_addMOVNMovAliasOperands_LT_48_GT_:
    4016           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<48>(Inst, 1);
    4017             :       break;
    4018           6 :     case CVT_95_addSIMDImmType10Operands:
    4019          12 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSIMDImmType10Operands(Inst, 1);
    4020             :       break;
    4021        1033 :     case CVT_95_addMRSSystemRegisterOperands:
    4022        2066 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMRSSystemRegisterOperands(Inst, 1);
    4023             :       break;
    4024         750 :     case CVT_95_addMSRSystemRegisterOperands:
    4025        1500 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMSRSystemRegisterOperands(Inst, 1);
    4026             :       break;
    4027           5 :     case CVT_95_addSystemPStateFieldWithImm0_95_15Operands:
    4028          10 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSystemPStateFieldWithImm0_15Operands(Inst, 1);
    4029             :       break;
    4030           4 :     case CVT_95_addSystemPStateFieldWithImm0_95_1Operands:
    4031           8 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSystemPStateFieldWithImm0_1Operands(Inst, 1);
    4032             :       break;
    4033           4 :     case CVT_95_addImm0_95_1Operands:
    4034           4 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm0_1Operands(Inst, 1);
    4035             :       break;
    4036          44 :     case CVT_95_addPrefetchOperands:
    4037          44 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addPrefetchOperands(Inst, 1);
    4038             :       break;
    4039           1 :     case CVT_95_addPSBHintOperands:
    4040           1 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addPSBHintOperands(Inst, 1);
    4041             :       break;
    4042             :     case CVT_regLR:
    4043         232 :       Inst.addOperand(MCOperand::createReg(AArch64::LR));
    4044             :       break;
    4045          96 :     case CVT_95_addImm1_95_8Operands:
    4046          96 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm1_8Operands(Inst, 1);
    4047             :       break;
    4048             :     case CVT_imm_95_4:
    4049           6 :       Inst.addOperand(MCOperand::createImm(4));
    4050             :       break;
    4051             :     case CVT_imm_95_5:
    4052           6 :       Inst.addOperand(MCOperand::createImm(5));
    4053             :       break;
    4054         394 :     case CVT_95_addImm0_95_7Operands:
    4055         394 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm0_7Operands(Inst, 1);
    4056             :       break;
    4057             :     case CVT_imm_95_7:
    4058          18 :       Inst.addOperand(MCOperand::createImm(7));
    4059             :       break;
    4060         356 :     case CVT_95_addSysCROperands:
    4061         356 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSysCROperands(Inst, 1);
    4062             :       break;
    4063          27 :     case CVT_95_addBranchTarget14Operands:
    4064          54 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addBranchTarget14Operands(Inst, 1);
    4065             :       break;
    4066           7 :     case CVT_95_addImm32_95_63Operands:
    4067           7 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImm32_63Operands(Inst, 1);
    4068             :       break;
    4069           8 :     case CVT_95_addGPR32as64Operands:
    4070          16 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addGPR32as64Operands(Inst, 1);
    4071             :       break;
    4072             :     case CVT_imm_95_2:
    4073           6 :       Inst.addOperand(MCOperand::createImm(2));
    4074             :       break;
    4075             :     case CVT_imm_95_3:
    4076           6 :       Inst.addOperand(MCOperand::createImm(3));
    4077             :       break;
    4078             :     case CVT_imm_95_1:
    4079           6 :       Inst.addOperand(MCOperand::createImm(1));
    4080             :       break;
    4081             :     }
    4082             :   }
    4083       13323 : }
    4084             : 
    4085           0 : void AArch64AsmParser::
    4086             : convertToMapAndConstraints(unsigned Kind,
    4087             :                            const OperandVector &Operands) {
    4088             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    4089             :   unsigned NumMCOperands = 0;
    4090           0 :   const uint8_t *Converter = ConversionTable[Kind];
    4091           0 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    4092           0 :     switch (*p) {
    4093           0 :     default: llvm_unreachable("invalid conversion entry!");
    4094           0 :     case CVT_Reg:
    4095           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4096           0 :       Operands[*(p + 1)]->setConstraint("r");
    4097           0 :       ++NumMCOperands;
    4098           0 :       break;
    4099           0 :     case CVT_Tied:
    4100           0 :       ++NumMCOperands;
    4101           0 :       break;
    4102           0 :     case CVT_95_Reg:
    4103           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4104           0 :       Operands[*(p + 1)]->setConstraint("r");
    4105           0 :       NumMCOperands += 1;
    4106           0 :       break;
    4107           0 :     case CVT_95_addVectorReg128Operands:
    4108           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4109           0 :       Operands[*(p + 1)]->setConstraint("m");
    4110           0 :       NumMCOperands += 1;
    4111           0 :       break;
    4112           0 :     case CVT_95_addVectorReg64Operands:
    4113           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4114           0 :       Operands[*(p + 1)]->setConstraint("m");
    4115           0 :       NumMCOperands += 1;
    4116           0 :       break;
    4117           0 :     case CVT_imm_95_16:
    4118           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4119           0 :       Operands[*(p + 1)]->setConstraint("");
    4120           0 :       ++NumMCOperands;
    4121           0 :       break;
    4122           0 :     case CVT_imm_95_24:
    4123           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4124           0 :       Operands[*(p + 1)]->setConstraint("");
    4125           0 :       ++NumMCOperands;
    4126           0 :       break;
    4127           0 :     case CVT_imm_95_0:
    4128           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4129           0 :       Operands[*(p + 1)]->setConstraint("");
    4130           0 :       ++NumMCOperands;
    4131           0 :       break;
    4132           0 :     case CVT_95_addAddSubImmNegOperands:
    4133           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4134           0 :       Operands[*(p + 1)]->setConstraint("m");
    4135           0 :       NumMCOperands += 2;
    4136           0 :       break;
    4137           0 :     case CVT_95_addAddSubImmOperands:
    4138           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4139           0 :       Operands[*(p + 1)]->setConstraint("m");
    4140           0 :       NumMCOperands += 2;
    4141           0 :       break;
    4142           0 :     case CVT_95_addRegOperands:
    4143           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4144           0 :       Operands[*(p + 1)]->setConstraint("m");
    4145           0 :       NumMCOperands += 1;
    4146           0 :       break;
    4147           0 :     case CVT_95_addShifterOperands:
    4148           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4149           0 :       Operands[*(p + 1)]->setConstraint("m");
    4150           0 :       NumMCOperands += 1;
    4151           0 :       break;
    4152           0 :     case CVT_95_addExtendOperands:
    4153           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4154           0 :       Operands[*(p + 1)]->setConstraint("m");
    4155           0 :       NumMCOperands += 1;
    4156           0 :       break;
    4157           0 :     case CVT_95_addExtend64Operands:
    4158           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4159           0 :       Operands[*(p + 1)]->setConstraint("m");
    4160           0 :       NumMCOperands += 1;
    4161           0 :       break;
    4162           0 :     case CVT_95_addImmOperands:
    4163           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4164           0 :       Operands[*(p + 1)]->setConstraint("m");
    4165           0 :       NumMCOperands += 1;
    4166           0 :       break;
    4167           0 :     case CVT_95_addAdrLabelOperands:
    4168           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4169           0 :       Operands[*(p + 1)]->setConstraint("m");
    4170           0 :       NumMCOperands += 1;
    4171           0 :       break;
    4172           0 :     case CVT_95_addAdrpLabelOperands:
    4173           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4174           0 :       Operands[*(p + 1)]->setConstraint("m");
    4175           0 :       NumMCOperands += 1;
    4176           0 :       break;
    4177           0 :     case CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_:
    4178           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4179           0 :       Operands[*(p + 1)]->setConstraint("m");
    4180           0 :       NumMCOperands += 1;
    4181           0 :       break;
    4182           0 :     case CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_:
    4183           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4184           0 :       Operands[*(p + 1)]->setConstraint("m");
    4185           0 :       NumMCOperands += 1;
    4186           0 :       break;
    4187           0 :     case CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_:
    4188           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4189           0 :       Operands[*(p + 1)]->setConstraint("m");
    4190           0 :       NumMCOperands += 1;
    4191           0 :       break;
    4192           0 :     case CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_:
    4193           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4194           0 :       Operands[*(p + 1)]->setConstraint("m");
    4195           0 :       NumMCOperands += 1;
    4196           0 :       break;
    4197           0 :     case CVT_95_addImm0_95_31Operands:
    4198           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4199           0 :       Operands[*(p + 1)]->setConstraint("m");
    4200           0 :       NumMCOperands += 1;
    4201           0 :       break;
    4202           0 :     case CVT_imm_95_31:
    4203           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4204           0 :       Operands[*(p + 1)]->setConstraint("");
    4205           0 :       ++NumMCOperands;
    4206           0 :       break;
    4207           0 :     case CVT_95_addImm0_95_63Operands:
    4208           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4209           0 :       Operands[*(p + 1)]->setConstraint("m");
    4210           0 :       NumMCOperands += 1;
    4211           0 :       break;
    4212           0 :     case CVT_imm_95_63:
    4213           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4214           0 :       Operands[*(p + 1)]->setConstraint("");
    4215           0 :       ++NumMCOperands;
    4216           0 :       break;
    4217           0 :     case CVT_95_addBranchTarget26Operands:
    4218           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4219           0 :       Operands[*(p + 1)]->setConstraint("m");
    4220           0 :       NumMCOperands += 1;
    4221           0 :       break;
    4222           0 :     case CVT_95_addCondCodeOperands:
    4223           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4224           0 :       Operands[*(p + 1)]->setConstraint("m");
    4225           0 :       NumMCOperands += 1;
    4226           0 :       break;
    4227           0 :     case CVT_95_addPCRelLabel19Operands:
    4228           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4229           0 :       Operands[*(p + 1)]->setConstraint("m");
    4230           0 :       NumMCOperands += 1;
    4231           0 :       break;
    4232           0 :     case CVT_95_addImm0_95_255Operands:
    4233           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4234           0 :       Operands[*(p + 1)]->setConstraint("m");
    4235           0 :       NumMCOperands += 1;
    4236           0 :       break;
    4237           0 :     case CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_:
    4238           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4239           0 :       Operands[*(p + 1)]->setConstraint("m");
    4240           0 :       NumMCOperands += 1;
    4241           0 :       break;
    4242           0 :     case CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_:
    4243           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4244           0 :       Operands[*(p + 1)]->setConstraint("m");
    4245           0 :       NumMCOperands += 1;
    4246           0 :       break;
    4247           0 :     case CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_:
    4248           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4249           0 :       Operands[*(p + 1)]->setConstraint("m");
    4250           0 :       NumMCOperands += 1;
    4251           0 :       break;
    4252           0 :     case CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_:
    4253           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4254           0 :       Operands[*(p + 1)]->setConstraint("m");
    4255           0 :       NumMCOperands += 1;
    4256           0 :       break;
    4257           0 :     case CVT_95_addImm0_95_65535Operands:
    4258           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4259           0 :       Operands[*(p + 1)]->setConstraint("m");
    4260           0 :       NumMCOperands += 1;
    4261           0 :       break;
    4262           0 :     case CVT_95_addImm0_95_15Operands:
    4263           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4264           0 :       Operands[*(p + 1)]->setConstraint("m");
    4265           0 :       NumMCOperands += 1;
    4266           0 :       break;
    4267           0 :     case CVT_imm_95_15:
    4268           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4269           0 :       Operands[*(p + 1)]->setConstraint("");
    4270           0 :       ++NumMCOperands;
    4271           0 :       break;
    4272           0 :     case CVT_regWZR:
    4273           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4274           0 :       Operands[*(p + 1)]->setConstraint("m");
    4275           0 :       ++NumMCOperands;
    4276           0 :       break;
    4277           0 :     case CVT_regXZR:
    4278           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4279           0 :       Operands[*(p + 1)]->setConstraint("m");
    4280           0 :       ++NumMCOperands;
    4281           0 :       break;
    4282           0 :     case CVT_imm_95_20:
    4283           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4284           0 :       Operands[*(p + 1)]->setConstraint("");
    4285           0 :       ++NumMCOperands;
    4286           0 :       break;
    4287           0 :     case CVT_95_addBarrierOperands:
    4288           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4289           0 :       Operands[*(p + 1)]->setConstraint("m");
    4290           0 :       NumMCOperands += 1;
    4291           0 :       break;
    4292           0 :     case CVT_95_addVectorIndexHOperands:
    4293           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4294           0 :       Operands[*(p + 1)]->setConstraint("m");
    4295           0 :       NumMCOperands += 1;
    4296           0 :       break;
    4297           0 :     case CVT_95_addVectorIndexSOperands:
    4298           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4299           0 :       Operands[*(p + 1)]->setConstraint("m");
    4300           0 :       NumMCOperands += 1;
    4301           0 :       break;
    4302           0 :     case CVT_95_addVectorIndexDOperands:
    4303           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4304           0 :       Operands[*(p + 1)]->setConstraint("m");
    4305           0 :       NumMCOperands += 1;
    4306           0 :       break;
    4307           0 :     case CVT_95_addVectorIndexBOperands:
    4308           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4309           0 :       Operands[*(p + 1)]->setConstraint("m");
    4310           0 :       NumMCOperands += 1;
    4311           0 :       break;
    4312           0 :     case CVT_95_addComplexRotationOddOperands:
    4313           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4314           0 :       Operands[*(p + 1)]->setConstraint("m");
    4315           0 :       NumMCOperands += 1;
    4316           0 :       break;
    4317           0 :     case CVT_95_addComplexRotationEvenOperands:
    4318           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4319           0 :       Operands[*(p + 1)]->setConstraint("m");
    4320           0 :       NumMCOperands += 1;
    4321           0 :       break;
    4322           0 :     case CVT_95_addImm1_95_16Operands:
    4323           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4324           0 :       Operands[*(p + 1)]->setConstraint("m");
    4325           0 :       NumMCOperands += 1;
    4326           0 :       break;
    4327           0 :     case CVT_95_addImm1_95_32Operands:
    4328           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4329           0 :       Operands[*(p + 1)]->setConstraint("m");
    4330           0 :       NumMCOperands += 1;
    4331           0 :       break;
    4332           0 :     case CVT_95_addImm1_95_64Operands:
    4333           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4334           0 :       Operands[*(p + 1)]->setConstraint("m");
    4335           0 :       NumMCOperands += 1;
    4336           0 :       break;
    4337           0 :     case CVT_95_addVectorRegLoOperands:
    4338           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4339           0 :       Operands[*(p + 1)]->setConstraint("m");
    4340           0 :       NumMCOperands += 1;
    4341           0 :       break;
    4342           0 :     case CVT_95_addFPImmOperands:
    4343           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4344           0 :       Operands[*(p + 1)]->setConstraint("m");
    4345           0 :       NumMCOperands += 1;
    4346           0 :       break;
    4347           0 :     case CVT_95_addVectorIndex1Operands:
    4348           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4349           0 :       Operands[*(p + 1)]->setConstraint("m");
    4350           0 :       NumMCOperands += 1;
    4351           0 :       break;
    4352           0 :     case CVT_95_addImm0_95_127Operands:
    4353           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4354           0 :       Operands[*(p + 1)]->setConstraint("m");
    4355           0 :       NumMCOperands += 1;
    4356           0 :       break;
    4357           0 :     case CVT_95_addVectorList128Operands_LT_4_GT_:
    4358           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4359           0 :       Operands[*(p + 1)]->setConstraint("m");
    4360           0 :       NumMCOperands += 1;
    4361           0 :       break;
    4362           0 :     case CVT_95_addVectorList64Operands_LT_4_GT_:
    4363           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4364           0 :       Operands[*(p + 1)]->setConstraint("m");
    4365           0 :       NumMCOperands += 1;
    4366           0 :       break;
    4367           0 :     case CVT_95_addVectorList128Operands_LT_1_GT_:
    4368           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4369           0 :       Operands[*(p + 1)]->setConstraint("m");
    4370           0 :       NumMCOperands += 1;
    4371           0 :       break;
    4372           0 :     case CVT_95_addVectorList64Operands_LT_1_GT_:
    4373           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4374           0 :       Operands[*(p + 1)]->setConstraint("m");
    4375           0 :       NumMCOperands += 1;
    4376           0 :       break;
    4377           0 :     case CVT_95_addVectorList128Operands_LT_3_GT_:
    4378           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4379           0 :       Operands[*(p + 1)]->setConstraint("m");
    4380           0 :       NumMCOperands += 1;
    4381           0 :       break;
    4382           0 :     case CVT_95_addVectorList64Operands_LT_3_GT_:
    4383           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4384           0 :       Operands[*(p + 1)]->setConstraint("m");
    4385           0 :       NumMCOperands += 1;
    4386           0 :       break;
    4387           0 :     case CVT_95_addVectorList128Operands_LT_2_GT_:
    4388           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4389           0 :       Operands[*(p + 1)]->setConstraint("m");
    4390           0 :       NumMCOperands += 1;
    4391           0 :       break;
    4392           0 :     case CVT_95_addVectorList64Operands_LT_2_GT_:
    4393           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4394           0 :       Operands[*(p + 1)]->setConstraint("m");
    4395           0 :       NumMCOperands += 1;
    4396           0 :       break;
    4397           0 :     case CVT_95_addSImm7s16Operands:
    4398           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4399           0 :       Operands[*(p + 1)]->setConstraint("m");
    4400           0 :       NumMCOperands += 1;
    4401           0 :       break;
    4402           0 :     case CVT_95_addSImm7s4Operands:
    4403           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4404           0 :       Operands[*(p + 1)]->setConstraint("m");
    4405           0 :       NumMCOperands += 1;
    4406           0 :       break;
    4407           0 :     case CVT_95_addSImm7s8Operands:
    4408           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4409           0 :       Operands[*(p + 1)]->setConstraint("m");
    4410           0 :       NumMCOperands += 1;
    4411           0 :       break;
    4412           0 :     case CVT_95_addUImm12OffsetOperands_LT_16_GT_:
    4413           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4414           0 :       Operands[*(p + 1)]->setConstraint("m");
    4415           0 :       NumMCOperands += 1;
    4416           0 :       break;
    4417           0 :     case CVT_95_addUImm12OffsetOperands_LT_2_GT_:
    4418           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4419           0 :       Operands[*(p + 1)]->setConstraint("m");
    4420           0 :       NumMCOperands += 1;
    4421           0 :       break;
    4422           0 :     case CVT_95_addUImm12OffsetOperands_LT_4_GT_:
    4423           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4424           0 :       Operands[*(p + 1)]->setConstraint("m");
    4425           0 :       NumMCOperands += 1;
    4426           0 :       break;
    4427           0 :     case CVT_95_addUImm12OffsetOperands_LT_8_GT_:
    4428           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4429           0 :       Operands[*(p + 1)]->setConstraint("m");
    4430           0 :       NumMCOperands += 1;
    4431           0 :       break;
    4432           0 :     case CVT_95_addUImm12OffsetOperands_LT_1_GT_:
    4433           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4434           0 :       Operands[*(p + 1)]->setConstraint("m");
    4435           0 :       NumMCOperands += 1;
    4436           0 :       break;
    4437           0 :     case CVT_95_addMemExtendOperands:
    4438           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4439           0 :       Operands[*(p + 1)]->setConstraint("m");
    4440           0 :       NumMCOperands += 2;
    4441           0 :       break;
    4442           0 :     case CVT_95_addMemExtend8Operands:
    4443           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4444           0 :       Operands[*(p + 1)]->setConstraint("m");
    4445           0 :       NumMCOperands += 2;
    4446           0 :       break;
    4447           0 :     case CVT_95_addSImm10s8Operands:
    4448           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4449           0 :       Operands[*(p + 1)]->setConstraint("m");
    4450           0 :       NumMCOperands += 1;
    4451           0 :       break;
    4452           0 :     case CVT_95_addMOVZMovAliasOperands_LT_0_GT_:
    4453           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4454           0 :       Operands[*(p + 1)]->setConstraint("m");
    4455           0 :       NumMCOperands += 1;
    4456           0 :       break;
    4457           0 :     case CVT_95_addMOVZMovAliasOperands_LT_16_GT_:
    4458           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4459           0 :       Operands[*(p + 1)]->setConstraint("m");
    4460           0 :       NumMCOperands += 1;
    4461           0 :       break;
    4462           0 :     case CVT_95_addMOVNMovAliasOperands_LT_0_GT_:
    4463           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4464           0 :       Operands[*(p + 1)]->setConstraint("m");
    4465           0 :       NumMCOperands += 1;
    4466           0 :       break;
    4467           0 :     case CVT_95_addMOVNMovAliasOperands_LT_16_GT_:
    4468           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4469           0 :       Operands[*(p + 1)]->setConstraint("m");
    4470           0 :       NumMCOperands += 1;
    4471           0 :       break;
    4472           0 :     case CVT_95_addMOVZMovAliasOperands_LT_32_GT_:
    4473           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4474           0 :       Operands[*(p + 1)]->setConstraint("m");
    4475           0 :       NumMCOperands += 1;
    4476           0 :       break;
    4477           0 :     case CVT_imm_95_32:
    4478           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4479           0 :       Operands[*(p + 1)]->setConstraint("");
    4480           0 :       ++NumMCOperands;
    4481           0 :       break;
    4482           0 :     case CVT_95_addMOVZMovAliasOperands_LT_48_GT_:
    4483           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4484           0 :       Operands[*(p + 1)]->setConstraint("m");
    4485           0 :       NumMCOperands += 1;
    4486           0 :       break;
    4487           0 :     case CVT_imm_95_48:
    4488           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4489           0 :       Operands[*(p + 1)]->setConstraint("");
    4490           0 :       ++NumMCOperands;
    4491           0 :       break;
    4492           0 :     case CVT_95_addMOVNMovAliasOperands_LT_32_GT_:
    4493           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4494           0 :       Operands[*(p + 1)]->setConstraint("m");
    4495           0 :       NumMCOperands += 1;
    4496           0 :       break;
    4497           0 :     case CVT_95_addMOVNMovAliasOperands_LT_48_GT_:
    4498           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4499           0 :       Operands[*(p + 1)]->setConstraint("m");
    4500           0 :       NumMCOperands += 1;
    4501           0 :       break;
    4502           0 :     case CVT_95_addSIMDImmType10Operands:
    4503           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4504           0 :       Operands[*(p + 1)]->setConstraint("m");
    4505           0 :       NumMCOperands += 1;
    4506           0 :       break;
    4507           0 :     case CVT_95_addMRSSystemRegisterOperands:
    4508           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4509           0 :       Operands[*(p + 1)]->setConstraint("m");
    4510           0 :       NumMCOperands += 1;
    4511           0 :       break;
    4512           0 :     case CVT_95_addMSRSystemRegisterOperands:
    4513           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4514           0 :       Operands[*(p + 1)]->setConstraint("m");
    4515           0 :       NumMCOperands += 1;
    4516           0 :       break;
    4517           0 :     case CVT_95_addSystemPStateFieldWithImm0_95_15Operands:
    4518           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4519           0 :       Operands[*(p + 1)]->setConstraint("m");
    4520           0 :       NumMCOperands += 1;
    4521           0 :       break;
    4522           0 :     case CVT_95_addSystemPStateFieldWithImm0_95_1Operands:
    4523           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4524           0 :       Operands[*(p + 1)]->setConstraint("m");
    4525           0 :       NumMCOperands += 1;
    4526           0 :       break;
    4527           0 :     case CVT_95_addImm0_95_1Operands:
    4528           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4529           0 :       Operands[*(p + 1)]->setConstraint("m");
    4530           0 :       NumMCOperands += 1;
    4531           0 :       break;
    4532           0 :     case CVT_95_addPrefetchOperands:
    4533           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4534           0 :       Operands[*(p + 1)]->setConstraint("m");
    4535           0 :       NumMCOperands += 1;
    4536           0 :       break;
    4537           0 :     case CVT_95_addPSBHintOperands:
    4538           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4539           0 :       Operands[*(p + 1)]->setConstraint("m");
    4540           0 :       NumMCOperands += 1;
    4541           0 :       break;
    4542           0 :     case CVT_regLR:
    4543           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4544           0 :       Operands[*(p + 1)]->setConstraint("m");
    4545           0 :       ++NumMCOperands;
    4546           0 :       break;
    4547           0 :     case CVT_95_addImm1_95_8Operands:
    4548           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4549           0 :       Operands[*(p + 1)]->setConstraint("m");
    4550           0 :       NumMCOperands += 1;
    4551           0 :       break;
    4552           0 :     case CVT_imm_95_4:
    4553           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4554           0 :       Operands[*(p + 1)]->setConstraint("");
    4555           0 :       ++NumMCOperands;
    4556           0 :       break;
    4557           0 :     case CVT_imm_95_5:
    4558           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4559           0 :       Operands[*(p + 1)]->setConstraint("");
    4560           0 :       ++NumMCOperands;
    4561           0 :       break;
    4562           0 :     case CVT_95_addImm0_95_7Operands:
    4563           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4564           0 :       Operands[*(p + 1)]->setConstraint("m");
    4565           0 :       NumMCOperands += 1;
    4566           0 :       break;
    4567           0 :     case CVT_imm_95_7:
    4568           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4569           0 :       Operands[*(p + 1)]->setConstraint("");
    4570           0 :       ++NumMCOperands;
    4571           0 :       break;
    4572           0 :     case CVT_95_addSysCROperands:
    4573           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4574           0 :       Operands[*(p + 1)]->setConstraint("m");
    4575           0 :       NumMCOperands += 1;
    4576           0 :       break;
    4577           0 :     case CVT_95_addBranchTarget14Operands:
    4578           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4579           0 :       Operands[*(p + 1)]->setConstraint("m");
    4580           0 :       NumMCOperands += 1;
    4581           0 :       break;
    4582           0 :     case CVT_95_addImm32_95_63Operands:
    4583           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4584           0 :       Operands[*(p + 1)]->setConstraint("m");
    4585           0 :       NumMCOperands += 1;
    4586           0 :       break;
    4587           0 :     case CVT_95_addGPR32as64Operands:
    4588           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4589           0 :       Operands[*(p + 1)]->setConstraint("m");
    4590           0 :       NumMCOperands += 1;
    4591           0 :       break;
    4592           0 :     case CVT_imm_95_2:
    4593           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4594           0 :       Operands[*(p + 1)]->setConstraint("");
    4595           0 :       ++NumMCOperands;
    4596           0 :       break;
    4597           0 :     case CVT_imm_95_3:
    4598           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4599           0 :       Operands[*(p + 1)]->setConstraint("");
    4600           0 :       ++NumMCOperands;
    4601           0 :       break;
    4602           0 :     case CVT_imm_95_1:
    4603           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4604           0 :       Operands[*(p + 1)]->setConstraint("");
    4605           0 :       ++NumMCOperands;
    4606           0 :       break;
    4607             :     }
    4608             :   }
    4609           0 : }
    4610             : 
    4611             : namespace {
    4612             : 
    4613             : /// MatchClassKind - The kinds of classes which participate in
    4614             : /// instruction matching.
    4615             : enum MatchClassKind {
    4616             :   InvalidMatchClass = 0,
    4617             :   OptionalMatchClass = 1,
    4618             :   MCK__DOT_16B, // '.16B'
    4619             :   MCK__DOT_1D, // '.1D'
    4620             :   MCK__DOT_1Q, // '.1Q'
    4621             :   MCK__DOT_2D, // '.2D'
    4622             :   MCK__DOT_2H, // '.2H'
    4623             :   MCK__DOT_2S, // '.2S'
    4624             :   MCK__DOT_4B, // '.4B'
    4625             :   MCK__DOT_4H, // '.4H'
    4626             :   MCK__DOT_4S, // '.4S'
    4627             :   MCK__DOT_8B, // '.8B'
    4628             :   MCK__DOT_8H, // '.8H'
    4629             :   MCK__DOT_B, // '.B'
    4630             :   MCK__DOT_D, // '.D'
    4631             :   MCK__DOT_H, // '.H'
    4632             :   MCK__DOT_Q, // '.Q'
    4633             :   MCK__DOT_S, // '.S'
    4634             :   MCK__EXCLAIM_, // '!'
    4635             :   MCK__35_0, // '#0'
    4636             :   MCK__35_1, // '#1'
    4637             :   MCK__35_12, // '#12'
    4638             :   MCK__35_16, // '#16'
    4639             :   MCK__35_2, // '#2'
    4640             :   MCK__35_24, // '#24'
    4641             :   MCK__35_3, // '#3'
    4642             :   MCK__35_32, // '#32'
    4643             :   MCK__35_4, // '#4'
    4644             :   MCK__35_48, // '#48'
    4645             :   MCK__35_6, // '#6'
    4646             :   MCK__35_64, // '#64'
    4647             :   MCK__35_8, // '#8'
    4648             :   MCK__DOT_, // '.'
    4649             :   MCK__DOT_0, // '.0'
    4650             :   MCK__DOT_16b, // '.16b'
    4651             :   MCK__DOT_1d, // '.1d'
    4652             :   MCK__DOT_1q, // '.1q'
    4653             :   MCK__DOT_2d, // '.2d'
    4654             :   MCK__DOT_2h, // '.2h'
    4655             :   MCK__DOT_2s, // '.2s'
    4656             :   MCK__DOT_4b, // '.4b'
    4657             :   MCK__DOT_4h, // '.4h'
    4658             :   MCK__DOT_4s, // '.4s'
    4659             :   MCK__DOT_8b, // '.8b'
    4660             :   MCK__DOT_8h, // '.8h'
    4661             :   MCK__DOT_b, // '.b'
    4662             :   MCK__DOT_d, // '.d'
    4663             :   MCK__DOT_h, // '.h'
    4664             :   MCK__DOT_q, // '.q'
    4665             :   MCK__DOT_s, // '.s'
    4666             :   MCK__47_, // '/'
    4667             :   MCK__91_, // '['
    4668             :   MCK__93_, // ']'
    4669             :   MCK_m, // 'm'
    4670             :   MCK_LAST_TOKEN = MCK_m,
    4671             :   MCK_CCR, // register class 'CCR'
    4672             :   MCK_GPR32sponly, // register class 'GPR32sponly'
    4673             :   MCK_GPR64sponly, // register class 'GPR64sponly'
    4674             :   MCK_PPR_3b, // register class 'PPR_3b'
    4675             :   MCK_Reg29, // derived register class
    4676             :   MCK_Reg30, // derived register class
    4677             :   MCK_Reg39, // derived register class
    4678             :   MCK_Reg40, // derived register class
    4679             :   MCK_Reg25, // derived register class
    4680             :   MCK_Reg31, // derived register class
    4681             :   MCK_Reg36, // derived register class
    4682             :   MCK_Reg38, // derived register class
    4683             :   MCK_Reg41, // derived register class
    4684             :   MCK_Reg46, // derived register class
    4685             :   MCK_Reg20, // derived register class
    4686             :   MCK_Reg26, // derived register class
    4687             :   MCK_Reg28, // derived register class
    4688             :   MCK_Reg32, // derived register class
    4689             :   MCK_Reg34, // derived register class
    4690             :   MCK_Reg35, // derived register class
    4691             :   MCK_Reg37, // derived register class
    4692             :   MCK_Reg42, // derived register class
    4693             :   MCK_Reg44, // derived register class
    4694             :   MCK_Reg45, // derived register class
    4695             :   MCK_FPR128_lo, // register class 'FPR128_lo'
    4696             :   MCK_PPR, // register class 'PPR'
    4697             :   MCK_Reg51, // derived register class
    4698             :   MCK_Reg52, // derived register class
    4699             :   MCK_Reg57, // derived register class
    4700             :   MCK_tcGPR64, // register class 'tcGPR64'
    4701             :   MCK_Reg47, // derived register class
    4702             :   MCK_Reg53, // derived register class
    4703             :   MCK_Reg48, // derived register class
    4704             :   MCK_Reg50, // derived register class
    4705             :   MCK_Reg54, // derived register class
    4706             :   MCK_Reg56, // derived register class
    4707             :   MCK_GPR32common, // register class 'GPR32common'
    4708             :   MCK_GPR64common, // register class 'GPR64common'
    4709             :   MCK_DD, // register class 'DD'
    4710             :   MCK_DDD, // register class 'DDD'
    4711             :   MCK_DDDD, // register class 'DDDD'
    4712             :   MCK_FPR128, // register class 'FPR128'
    4713             :   MCK_FPR16, // register class 'FPR16'
    4714             :   MCK_FPR32, // register class 'FPR32'
    4715             :   MCK_FPR64, // register class 'FPR64'
    4716             :   MCK_FPR8, // register class 'FPR8'
    4717             :   MCK_GPR32, // register class 'GPR32'
    4718             :   MCK_GPR32sp, // register class 'GPR32sp'
    4719             :   MCK_GPR64, // register class 'GPR64'
    4720             :   MCK_GPR64sp, // register class 'GPR64sp'
    4721             :   MCK_QQ, // register class 'QQ'
    4722             :   MCK_QQQ, // register class 'QQQ'
    4723             :   MCK_QQQQ, // register class 'QQQQ'
    4724             :   MCK_WSeqPairsClass, // register class 'WSeqPairsClass'
    4725             :   MCK_XSeqPairsClass, // register class 'XSeqPairsClass'
    4726             :   MCK_ZPR, // register class 'ZPR'
    4727             :   MCK_GPR32all, // register class 'GPR32all'
    4728             :   MCK_GPR64all, // register class 'GPR64all'
    4729             :   MCK_LAST_REGISTER = MCK_GPR64all,
    4730             :   MCK_AddSubImmNeg, // user defined class 'AddSubImmNegOperand'
    4731             :   MCK_AddSubImm, // user defined class 'AddSubImmOperand'
    4732             :   MCK_AdrLabel, // user defined class 'AdrOperand'
    4733             :   MCK_AdrpLabel, // user defined class 'AdrpOperand'
    4734             :   MCK_Barrier, // user defined class 'BarrierAsmOperand'
    4735             :   MCK_BranchTarget14, // user defined class 'BranchTarget14Operand'
    4736             :   MCK_BranchTarget26, // user defined class 'BranchTarget26Operand'
    4737             :   MCK_CondCode, // user defined class 'CondCode'
    4738             :   MCK_Extend64, // user defined class 'ExtendOperand64'
    4739             :   MCK_ExtendLSL64, // user defined class 'ExtendOperandLSL64'
    4740             :   MCK_Extend, // user defined class 'ExtendOperand'
    4741             :   MCK_FPImm, // user defined class 'FPImmOperand'
    4742             :   MCK_GPR32as64, // user defined class 'GPR32as64Operand'
    4743             :   MCK_GPR64sp0, // user defined class 'GPR64spPlus0Operand'
    4744             :   MCK_Imm0_127, // user defined class 'Imm0_127Operand'
    4745             :   MCK_Imm0_15, // user defined class 'Imm0_15Operand'
    4746             :   MCK_Imm0_1, // user defined class 'Imm0_1Operand'
    4747             :   MCK_Imm0_255, // user defined class 'Imm0_255Operand'
    4748             :   MCK_Imm0_31, // user defined class 'Imm0_31Operand'
    4749             :   MCK_Imm0_63, // user defined class 'Imm0_63Operand'
    4750             :   MCK_Imm0_65535, // user defined class 'Imm0_65535Operand'
    4751             :   MCK_Imm0_7, // user defined class 'Imm0_7Operand'
    4752             :   MCK_Imm1_16, // user defined class 'Imm1_16Operand'
    4753             :   MCK_Imm1_32, // user defined class 'Imm1_32Operand'
    4754             :   MCK_Imm1_64, // user defined class 'Imm1_64Operand'
    4755             :   MCK_Imm1_8, // user defined class 'Imm1_8Operand'
    4756             :   MCK_Imm, // user defined class 'ImmAsmOperand'
    4757             :   MCK_LogicalImm32Not, // user defined class 'LogicalImm32NotOperand'
    4758             :   MCK_LogicalImm32, // user defined class 'LogicalImm32Operand'
    4759             :   MCK_LogicalImm64Not, // user defined class 'LogicalImm64NotOperand'
    4760             :   MCK_LogicalImm64, // user defined class 'LogicalImm64Operand'
    4761             :   MCK_MRSSystemRegister, // user defined class 'MRSSystemRegisterOperand'
    4762             :   MCK_MSRSystemRegister, // user defined class 'MSRSystemRegisterOperand'
    4763             :   MCK_MemWExtend128, // user defined class 'MemWExtend128Operand'
    4764             :   MCK_MemWExtend16, // user defined class 'MemWExtend16Operand'
    4765             :   MCK_MemWExtend32, // user defined class 'MemWExtend32Operand'
    4766             :   MCK_MemWExtend64, // user defined class 'MemWExtend64Operand'
    4767             :   MCK_MemWExtend8, // user defined class 'MemWExtend8Operand'
    4768             :   MCK_MemXExtend128, // user defined class 'MemXExtend128Operand'
    4769             :   MCK_MemXExtend16, // user defined class 'MemXExtend16Operand'
    4770             :   MCK_MemXExtend32, // user defined class 'MemXExtend32Operand'
    4771             :   MCK_MemXExtend64, // user defined class 'MemXExtend64Operand'
    4772             :   MCK_MemXExtend8, // user defined class 'MemXExtend8Operand'
    4773             :   MCK_MovKSymbolG0, // user defined class 'MovKSymbolG0AsmOperand'
    4774             :   MCK_MovKSymbolG1, // user defined class 'MovKSymbolG1AsmOperand'
    4775             :   MCK_MovKSymbolG2, // user defined class 'MovKSymbolG2AsmOperand'
    4776             :   MCK_MovKSymbolG3, // user defined class 'MovKSymbolG3AsmOperand'
    4777             :   MCK_MovZSymbolG0, // user defined class 'MovZSymbolG0AsmOperand'
    4778             :   MCK_MovZSymbolG1, // user defined class 'MovZSymbolG1AsmOperand'
    4779             :   MCK_MovZSymbolG2, // user defined class 'MovZSymbolG2AsmOperand'
    4780             :   MCK_MovZSymbolG3, // user defined class 'MovZSymbolG3AsmOperand'
    4781             :   MCK_PCRelLabel19, // user defined class 'PCRelLabel19Operand'
    4782             :   MCK_SVEPredicateHReg, // user defined class 'PPRAsmOp16'
    4783             :   MCK_SVEPredicateSReg, // user defined class 'PPRAsmOp32'
    4784             :   MCK_SVEPredicate3bHReg, // user defined class 'PPRAsmOp3b16'
    4785             :   MCK_SVEPredicate3bSReg, // user defined class 'PPRAsmOp3b32'
    4786             :   MCK_SVEPredicate3bDReg, // user defined class 'PPRAsmOp3b64'
    4787             :   MCK_SVEPredicate3bBReg, // user defined class 'PPRAsmOp3b8'
    4788             :   MCK_SVEPredicate3bAnyReg, // user defined class 'PPRAsmOp3bAny'
    4789             :   MCK_SVEPredicateDReg, // user defined class 'PPRAsmOp64'
    4790             :   MCK_SVEPredicateBReg, // user defined class 'PPRAsmOp8'
    4791             :   MCK_SVEPredicateAnyReg, // user defined class 'PPRAsmOpAny'
    4792             :   MCK_PSBHint, // user defined class 'PSBHintOperand'
    4793             :   MCK_Prefetch, // user defined class 'PrefetchOperand'
    4794             :   MCK_SIMDImmType10, // user defined class 'SIMDImmType10Operand'
    4795             :   MCK_SImm10s8, // user defined class 'SImm10s8Operand'
    4796             :   MCK_SImm6, // user defined class 'SImm6Operand'
    4797             :   MCK_SImm7s16, // user defined class 'SImm7s16Operand'
    4798             :   MCK_SImm7s4, // user defined class 'SImm7s4Operand'
    4799             :   MCK_SImm7s8, // user defined class 'SImm7s8Operand'
    4800             :   MCK_SImm9OffsetFB128, // user defined class 'SImm9OffsetFB128Operand'
    4801             :   MCK_SImm9OffsetFB16, // user defined class 'SImm9OffsetFB16Operand'
    4802             :   MCK_SImm9OffsetFB32, // user defined class 'SImm9OffsetFB32Operand'
    4803             :   MCK_SImm9OffsetFB64, // user defined class 'SImm9OffsetFB64Operand'
    4804             :   MCK_SImm9OffsetFB8, // user defined class 'SImm9OffsetFB8Operand'
    4805             :   MCK_SImm9, // user defined class 'SImm9Operand'
    4806             :   MCK_SVEPattern, // user defined class 'SVEPatternOperand'
    4807             :   MCK_LogicalVecHalfWordShifter, // user defined class 'LogicalVecHalfWordShifterOperand'
    4808             :   MCK_ArithmeticShifter32, // user defined class 'ArithmeticShifterOperand32'
    4809             :   MCK_ArithmeticShifter64, // user defined class 'ArithmeticShifterOperand64'
    4810             :   MCK_LogicalShifter32, // user defined class 'LogicalShifterOperand32'
    4811             :   MCK_LogicalShifter64, // user defined class 'LogicalShifterOperand64'
    4812             :   MCK_LogicalVecShifter, // user defined class 'LogicalVecShifterOperand'
    4813             :   MCK_MovImm32Shifter, // user defined class 'MovImm32ShifterOperand'
    4814             :   MCK_MovImm64Shifter, // user defined class 'MovImm64ShifterOperand'
    4815             :   MCK_MoveVecShifter, // user defined class 'MoveVecShifterOperand'
    4816             :   MCK_Shifter, // user defined class 'ShifterOperand'
    4817             :   MCK_SysCR, // user defined class 'SysCRAsmOperand'
    4818             :   MCK_SystemPStateFieldWithImm0_15, // user defined class 'SystemPStateFieldWithImm0_15Operand'
    4819             :   MCK_SystemPStateFieldWithImm0_1, // user defined class 'SystemPStateFieldWithImm0_1Operand'
    4820             :   MCK_TBZImm0_31, // user defined class 'TBZImm0_31Operand'
    4821             :   MCK_Imm32_63, // user defined class 'TBZImm32_63Operand'
    4822             :   MCK_UImm12Offset16, // user defined class 'UImm12OffsetScale16Operand'
    4823             :   MCK_UImm12Offset1, // user defined class 'UImm12OffsetScale1Operand'
    4824             :   MCK_UImm12Offset2, // user defined class 'UImm12OffsetScale2Operand'
    4825             :   MCK_UImm12Offset4, // user defined class 'UImm12OffsetScale4Operand'
    4826             :   MCK_UImm12Offset8, // user defined class 'UImm12OffsetScale8Operand'
    4827             :   MCK_VecListFour128, // user defined class 'VecListFour_128AsmOperand'
    4828             :   MCK_TypedVectorList4_16b, // user defined class 'VecListFour_16bAsmOperand'
    4829             :   MCK_TypedVectorList4_1d, // user defined class 'VecListFour_1dAsmOperand'
    4830             :   MCK_TypedVectorList4_2d, // user defined class 'VecListFour_2dAsmOperand'
    4831             :   MCK_TypedVectorList4_2s, // user defined class 'VecListFour_2sAsmOperand'
    4832             :   MCK_TypedVectorList4_4h, // user defined class 'VecListFour_4hAsmOperand'
    4833             :   MCK_TypedVectorList4_4s, // user defined class 'VecListFour_4sAsmOperand'
    4834             :   MCK_VecListFour64, // user defined class 'VecListFour_64AsmOperand'
    4835             :   MCK_TypedVectorList4_8b, // user defined class 'VecListFour_8bAsmOperand'
    4836             :   MCK_TypedVectorList4_8h, // user defined class 'VecListFour_8hAsmOperand'
    4837             :   MCK_TypedVectorList4_0b, // user defined class 'VecListFour_bAsmOperand'
    4838             :   MCK_TypedVectorList4_0d, // user defined class 'VecListFour_dAsmOperand'
    4839             :   MCK_TypedVectorList4_0h, // user defined class 'VecListFour_hAsmOperand'
    4840             :   MCK_TypedVectorList4_0s, // user defined class 'VecListFour_sAsmOperand'
    4841             :   MCK_VecListOne128, // user defined class 'VecListOne_128AsmOperand'
    4842             :   MCK_TypedVectorList1_16b, // user defined class 'VecListOne_16bAsmOperand'
    4843             :   MCK_TypedVectorList1_1d, // user defined class 'VecListOne_1dAsmOperand'
    4844             :   MCK_TypedVectorList1_2d, // user defined class 'VecListOne_2dAsmOperand'
    4845             :   MCK_TypedVectorList1_2s, // user defined class 'VecListOne_2sAsmOperand'
    4846             :   MCK_TypedVectorList1_4h, // user defined class 'VecListOne_4hAsmOperand'
    4847             :   MCK_TypedVectorList1_4s, // user defined class 'VecListOne_4sAsmOperand'
    4848             :   MCK_VecListOne64, // user defined class 'VecListOne_64AsmOperand'
    4849             :   MCK_TypedVectorList1_8b, // user defined class 'VecListOne_8bAsmOperand'
    4850             :   MCK_TypedVectorList1_8h, // user defined class 'VecListOne_8hAsmOperand'
    4851             :   MCK_TypedVectorList1_0b, // user defined class 'VecListOne_bAsmOperand'
    4852             :   MCK_TypedVectorList1_0d, // user defined class 'VecListOne_dAsmOperand'
    4853             :   MCK_TypedVectorList1_0h, // user defined class 'VecListOne_hAsmOperand'
    4854             :   MCK_TypedVectorList1_0s, // user defined class 'VecListOne_sAsmOperand'
    4855             :   MCK_VecListThree128, // user defined class 'VecListThree_128AsmOperand'
    4856             :   MCK_TypedVectorList3_16b, // user defined class 'VecListThree_16bAsmOperand'
    4857             :   MCK_TypedVectorList3_1d, // user defined class 'VecListThree_1dAsmOperand'
    4858             :   MCK_TypedVectorList3_2d, // user defined class 'VecListThree_2dAsmOperand'
    4859             :   MCK_TypedVectorList3_2s, // user defined class 'VecListThree_2sAsmOperand'
    4860             :   MCK_TypedVectorList3_4h, // user defined class 'VecListThree_4hAsmOperand'
    4861             :   MCK_TypedVectorList3_4s, // user defined class 'VecListThree_4sAsmOperand'
    4862             :   MCK_VecListThree64, // user defined class 'VecListThree_64AsmOperand'
    4863             :   MCK_TypedVectorList3_8b, // user defined class 'VecListThree_8bAsmOperand'
    4864             :   MCK_TypedVectorList3_8h, // user defined class 'VecListThree_8hAsmOperand'
    4865             :   MCK_TypedVectorList3_0b, // user defined class 'VecListThree_bAsmOperand'
    4866             :   MCK_TypedVectorList3_0d, // user defined class 'VecListThree_dAsmOperand'
    4867             :   MCK_TypedVectorList3_0h, // user defined class 'VecListThree_hAsmOperand'
    4868             :   MCK_TypedVectorList3_0s, // user defined class 'VecListThree_sAsmOperand'
    4869             :   MCK_VecListTwo128, // user defined class 'VecListTwo_128AsmOperand'
    4870             :   MCK_TypedVectorList2_16b, // user defined class 'VecListTwo_16bAsmOperand'
    4871             :   MCK_TypedVectorList2_1d, // user defined class 'VecListTwo_1dAsmOperand'
    4872             :   MCK_TypedVectorList2_2d, // user defined class 'VecListTwo_2dAsmOperand'
    4873             :   MCK_TypedVectorList2_2s, // user defined class 'VecListTwo_2sAsmOperand'
    4874             :   MCK_TypedVectorList2_4h, // user defined class 'VecListTwo_4hAsmOperand'
    4875             :   MCK_TypedVectorList2_4s, // user defined class 'VecListTwo_4sAsmOperand'
    4876             :   MCK_VecListTwo64, // user defined class 'VecListTwo_64AsmOperand'
    4877             :   MCK_TypedVectorList2_8b, // user defined class 'VecListTwo_8bAsmOperand'
    4878             :   MCK_TypedVectorList2_8h, // user defined class 'VecListTwo_8hAsmOperand'
    4879             :   MCK_TypedVectorList2_0b, // user defined class 'VecListTwo_bAsmOperand'
    4880             :   MCK_TypedVectorList2_0d, // user defined class 'VecListTwo_dAsmOperand'
    4881             :   MCK_TypedVectorList2_0h, // user defined class 'VecListTwo_hAsmOperand'
    4882             :   MCK_TypedVectorList2_0s, // user defined class 'VecListTwo_sAsmOperand'
    4883             :   MCK_VectorIndex1, // user defined class 'VectorIndex1Operand'
    4884             :   MCK_VectorIndexB, // user defined class 'VectorIndexBOperand'
    4885             :   MCK_VectorIndexD, // user defined class 'VectorIndexDOperand'
    4886             :   MCK_VectorIndexH, // user defined class 'VectorIndexHOperand'
    4887             :   MCK_VectorIndexS, // user defined class 'VectorIndexSOperand'
    4888             :   MCK_VectorReg128, // user defined class 'VectorReg128AsmOperand'
    4889             :   MCK_VectorReg64, // user defined class 'VectorReg64AsmOperand'
    4890             :   MCK_VectorRegLo, // user defined class 'VectorRegLoAsmOperand'
    4891             :   MCK_WSeqPair, // user defined class 'WSeqPairsAsmOperandClass'
    4892             :   MCK_XSeqPair, // user defined class 'XSeqPairsAsmOperandClass'
    4893             :   MCK_SVEVectorQReg, // user defined class 'ZPRAsmOp128'
    4894             :   MCK_SVEVectorHReg, // user defined class 'ZPRAsmOp16'
    4895             :   MCK_SVEVectorSReg, // user defined class 'ZPRAsmOp32'
    4896             :   MCK_SVEVectorDReg, // user defined class 'ZPRAsmOp64'
    4897             :   MCK_SVEVectorBReg, // user defined class 'ZPRAsmOp8'
    4898             :   MCK_SVEVectorAnyReg, // user defined class 'ZPRAsmOpAny'
    4899             :   MCK_ComplexRotationEven, // user defined class 'anonymous_1183'
    4900             :   MCK_ComplexRotationOdd, // user defined class 'anonymous_1184'
    4901             :   MCK_SVELogicalImm8, // user defined class 'anonymous_1234'
    4902             :   MCK_SVELogicalImm16, // user defined class 'anonymous_1235'
    4903             :   MCK_SVELogicalImm32, // user defined class 'anonymous_1236'
    4904             :   MCK_SVELogicalImm8Not, // user defined class 'anonymous_1237'
    4905             :   MCK_SVELogicalImm16Not, // user defined class 'anonymous_1238'
    4906             :   MCK_SVELogicalImm32Not, // user defined class 'anonymous_1239'
    4907             :   MCK_MOVZ32_lsl0MovAlias, // user defined class 'anonymous_1296_asmoperand'
    4908             :   MCK_MOVZ32_lsl16MovAlias, // user defined class 'anonymous_1297_asmoperand'
    4909             :   MCK_MOVZ64_lsl0MovAlias, // user defined class 'anonymous_1298_asmoperand'
    4910             :   MCK_MOVZ64_lsl16MovAlias, // user defined class 'anonymous_1299_asmoperand'
    4911             :   MCK_MOVZ64_lsl32MovAlias, // user defined class 'anonymous_1300_asmoperand'
    4912             :   MCK_MOVZ64_lsl48MovAlias, // user defined class 'anonymous_1301_asmoperand'
    4913             :   MCK_MOVN32_lsl0MovAlias, // user defined class 'anonymous_1302_asmoperand'
    4914             :   MCK_MOVN32_lsl16MovAlias, // user defined class 'anonymous_1303_asmoperand'
    4915             :   MCK_MOVN64_lsl0MovAlias, // user defined class 'anonymous_1304_asmoperand'
    4916             :   MCK_MOVN64_lsl16MovAlias, // user defined class 'anonymous_1305_asmoperand'
    4917             :   MCK_MOVN64_lsl32MovAlias, // user defined class 'anonymous_1306_asmoperand'
    4918             :   MCK_MOVN64_lsl48MovAlias, // user defined class 'anonymous_1307_asmoperand'
    4919             :   NumMatchClassKinds
    4920             : };
    4921             : 
    4922             : }
    4923             : 
    4924             : static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
    4925             :   return MCTargetAsmParser::Match_InvalidOperand;
    4926             : }
    4927             : 
    4928       62778 : static MatchClassKind matchTokenString(StringRef Name) {
    4929       62778 :   switch (Name.size()) {
    4930             :   default: break;
    4931       19410 :   case 1:        // 6 strings to match.
    4932       19410 :     switch (Name[0]) {
    4933             :     default: break;
    4934             :     case '!':    // 1 string to match.
    4935             :       return MCK__EXCLAIM_;      // "!"
    4936         100 :     case '.':    // 1 string to match.
    4937         100 :       return MCK__DOT_;  // "."
    4938         176 :     case '/':    // 1 string to match.
    4939         176 :       return MCK__47_;   // "/"
    4940       12535 :     case '[':    // 1 string to match.
    4941       12535 :       return MCK__91_;   // "["
    4942        6283 :     case ']':    // 1 string to match.
    4943        6283 :       return MCK__93_;   // "]"
    4944         176 :     case 'm':    // 1 string to match.
    4945         176 :       return MCK_m;      // "m"
    4946             :     }
    4947             :     break;
    4948        6397 :   case 2:        // 18 strings to match.
    4949        6397 :     switch (Name[0]) {
    4950             :     default: break;
    4951         234 :     case '#':    // 7 strings to match.
    4952         234 :       switch (Name[1]) {
    4953             :       default: break;
    4954             :       case '0':  // 1 string to match.
    4955             :         return MCK__35_0;        // "#0"
    4956             :       case '1':  // 1 string to match.
    4957             :         return MCK__35_1;        // "#1"
    4958             :       case '2':  // 1 string to match.
    4959             :         return MCK__35_2;        // "#2"
    4960             :       case '3':  // 1 string to match.
    4961             :         return MCK__35_3;        // "#3"
    4962             :       case '4':  // 1 string to match.
    4963             :         return MCK__35_4;        // "#4"
    4964             :       case '6':  // 1 string to match.
    4965             :         return MCK__35_6;        // "#6"
    4966             :       case '8':  // 1 string to match.
    4967             :         return MCK__35_8;        // "#8"
    4968             :       }
    4969             :       break;
    4970        6163 :     case '.':    // 11 strings to match.
    4971        6163 :       switch (Name[1]) {
    4972             :       default: break;
    4973             :       case '0':  // 1 string to match.
    4974             :         return MCK__DOT_0;       // ".0"
    4975             :       case 'B':  // 1 string to match.
    4976             :         return MCK__DOT_B;       // ".B"
    4977             :       case 'D':  // 1 string to match.
    4978             :         return MCK__DOT_D;       // ".D"
    4979             :       case 'H':  // 1 string to match.
    4980             :         return MCK__DOT_H;       // ".H"
    4981             :       case 'Q':  // 1 string to match.
    4982             :         return MCK__DOT_Q;       // ".Q"
    4983             :       case 'S':  // 1 string to match.
    4984             :         return MCK__DOT_S;       // ".S"
    4985             :       case 'b':  // 1 string to match.
    4986             :         return MCK__DOT_b;       // ".b"
    4987             :       case 'd':  // 1 string to match.
    4988             :         return MCK__DOT_d;       // ".d"
    4989             :       case 'h':  // 1 string to match.
    4990             :         return MCK__DOT_h;       // ".h"
    4991             :       case 'q':  // 1 string to match.
    4992             :         return MCK__DOT_q;       // ".q"
    4993             :       case 's':  // 1 string to match.
    4994             :         return MCK__DOT_s;       // ".s"
    4995             :       }
    4996             :       break;
    4997             :     }
    4998             :     break;
    4999       34782 :   case 3:        // 26 strings to match.
    5000       34782 :     switch (Name[0]) {
    5001             :     default: break;
    5002           0 :     case '#':    // 6 strings to match.
    5003           0 :       switch (Name[1]) {
    5004             :       default: break;
    5005           0 :       case '1':  // 2 strings to match.
    5006           0 :         switch (Name[2]) {
    5007             :         default: break;
    5008             :         case '2':        // 1 string to match.
    5009             :           return MCK__35_12;     // "#12"
    5010           0 :         case '6':        // 1 string to match.
    5011           0 :           return MCK__35_16;     // "#16"
    5012             :         }
    5013             :         break;
    5014           0 :       case '2':  // 1 string to match.
    5015           0 :         if (Name[2] != '4')
    5016             :           break;
    5017             :         return MCK__35_24;       // "#24"
    5018           0 :       case '3':  // 1 string to match.
    5019           0 :         if (Name[2] != '2')
    5020             :           break;
    5021             :         return MCK__35_32;       // "#32"
    5022           0 :       case '4':  // 1 string to match.
    5023           0 :         if (Name[2] != '8')
    5024             :           break;
    5025             :         return MCK__35_48;       // "#48"
    5026           0 :       case '6':  // 1 string to match.
    5027           0 :         if (Name[2] != '4')
    5028             :           break;
    5029             :         return MCK__35_64;       // "#64"
    5030             :       }
    5031             :       break;
    5032       34782 :     case '.':    // 20 strings to match.
    5033       34782 :       switch (Name[1]) {
    5034             :       default: break;
    5035        1021 :       case '1':  // 4 strings to match.
    5036        1021 :         switch (Name[2]) {
    5037             :         default: break;
    5038             :         case 'D':        // 1 string to match.
    5039             :           return MCK__DOT_1D;    // ".1D"
    5040           2 :         case 'Q':        // 1 string to match.
    5041           2 :           return MCK__DOT_1Q;    // ".1Q"
    5042        1003 :         case 'd':        // 1 string to match.
    5043        1003 :           return MCK__DOT_1d;    // ".1d"
    5044          14 :         case 'q':        // 1 string to match.
    5045          14 :           return MCK__DOT_1q;    // ".1q"
    5046             :         }
    5047             :         break;
    5048        8910 :       case '2':  // 6 strings to match.
    5049        8910 :         switch (Name[2]) {
    5050             :         default: break;
    5051             :         case 'D':        // 1 string to match.
    5052             :           return MCK__DOT_2D;    // ".2D"
    5053             :         case 'H':        // 1 string to match.
    5054             :           return MCK__DOT_2H;    // ".2H"
    5055             :         case 'S':        // 1 string to match.
    5056             :           return MCK__DOT_2S;    // ".2S"
    5057             :         case 'd':        // 1 string to match.
    5058             :           return MCK__DOT_2d;    // ".2d"
    5059             :         case 'h':        // 1 string to match.
    5060             :           return MCK__DOT_2h;    // ".2h"
    5061             :         case 's':        // 1 string to match.
    5062             :           return MCK__DOT_2s;    // ".2s"
    5063             :         }
    5064             :         break;
    5065       12411 :       case '4':  // 6 strings to match.
    5066       12411 :         switch (Name[2]) {
    5067             :         default: break;
    5068             :         case 'B':        // 1 string to match.
    5069             :           return MCK__DOT_4B;    // ".4B"
    5070           0 :         case 'H':        // 1 string to match.
    5071           0 :           return MCK__DOT_4H;    // ".4H"
    5072          16 :         case 'S':        // 1 string to match.
    5073          16 :           return MCK__DOT_4S;    // ".4S"
    5074          52 :         case 'b':        // 1 string to match.
    5075          52 :           return MCK__DOT_4b;    // ".4b"
    5076        6467 :         case 'h':        // 1 string to match.
    5077        6467 :           return MCK__DOT_4h;    // ".4h"
    5078        5860 :         case 's':        // 1 string to match.
    5079        5860 :           return MCK__DOT_4s;    // ".4s"
    5080             :         }
    5081             :         break;
    5082       12224 :       case '8':  // 4 strings to match.
    5083       12224 :         switch (Name[2]) {
    5084             :         default: break;
    5085             :         case 'B':        // 1 string to match.
    5086             :           return MCK__DOT_8B;    // ".8B"
    5087           4 :         case 'H':        // 1 string to match.
    5088           4 :           return MCK__DOT_8H;    // ".8H"
    5089        4919 :         case 'b':        // 1 string to match.
    5090        4919 :           return MCK__DOT_8b;    // ".8b"
    5091        7280 :         case 'h':        // 1 string to match.
    5092        7280 :           return MCK__DOT_8h;    // ".8h"
    5093             :         }
    5094             :         break;
    5095             :       }
    5096             :       break;
    5097             :     }
    5098             :     break;
    5099             :   case 4:        // 2 strings to match.
    5100        2189 :     if (memcmp(Name.data()+0, ".16", 3) != 0)
    5101             :       break;
    5102        2189 :     switch (Name[3]) {
    5103             :     default: break;
    5104             :     case 'B':    // 1 string to match.
    5105             :       return MCK__DOT_16B;       // ".16B"
    5106        2174 :     case 'b':    // 1 string to match.
    5107        2174 :       return MCK__DOT_16b;       // ".16b"
    5108             :     }
    5109             :     break;
    5110             :   }
    5111             :   return InvalidMatchClass;
    5112             : }
    5113             : 
    5114             : /// isSubclass - Compute whether \p A is a subclass of \p B.
    5115      486015 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
    5116      486015 :   if (A == B)
    5117             :     return true;
    5118             : 
    5119      445945 :   switch (A) {
    5120             :   default:
    5121             :     return false;
    5122             : 
    5123          15 :   case MCK__DOT_16B:
    5124          15 :     return B == MCK__DOT_16b;
    5125             : 
    5126           2 :   case MCK__DOT_1D:
    5127           2 :     return B == MCK__DOT_1d;
    5128             : 
    5129           2 :   case MCK__DOT_1Q:
    5130           2 :     return B == MCK__DOT_1q;
    5131             : 
    5132           8 :   case MCK__DOT_2D:
    5133           8 :     return B == MCK__DOT_2d;
    5134             : 
    5135           1 :   case MCK__DOT_2H:
    5136           1 :     return B == MCK__DOT_2h;
    5137             : 
    5138          13 :   case MCK__DOT_2S:
    5139          13 :     return B == MCK__DOT_2s;
    5140             : 
    5141          16 :   case MCK__DOT_4B:
    5142          16 :     return B == MCK__DOT_4b;
    5143             : 
    5144           0 :   case MCK__DOT_4H:
    5145           0 :     return B == MCK__DOT_4h;
    5146             : 
    5147          16 :   case MCK__DOT_4S:
    5148          16 :     return B == MCK__DOT_4s;
    5149             : 
    5150          21 :   case MCK__DOT_8B:
    5151          21 :     return B == MCK__DOT_8b;
    5152             : 
    5153           4 :   case MCK__DOT_8H:
    5154           4 :     return B == MCK__DOT_8h;
    5155             : 
    5156           0 :   case MCK__DOT_B:
    5157           0 :     return B == MCK__DOT_b;
    5158             : 
    5159           0 :   case MCK__DOT_D:
    5160           0 :     return B == MCK__DOT_d;
    5161             : 
    5162           0 :   case MCK__DOT_H:
    5163           0 :     return B == MCK__DOT_h;
    5164             : 
    5165           0 :   case MCK__DOT_Q:
    5166           0 :     return B == MCK__DOT_q;
    5167             : 
    5168           0 :   case MCK__DOT_S:
    5169           0 :     return B == MCK__DOT_s;
    5170             : 
    5171        2822 :   case MCK_GPR32sponly:
    5172        2822 :     switch (B) {
    5173             :     default: return false;
    5174         155 :     case MCK_GPR32sp: return true;
    5175           0 :     case MCK_GPR32all: return true;
    5176             :     }
    5177             : 
    5178        5169 :   case MCK_GPR64sponly:
    5179        5169 :     switch (B) {
    5180             :     default: return false;
    5181        2024 :     case MCK_GPR64sp: return true;
    5182           0 :     case MCK_GPR64all: return true;
    5183             :     }
    5184             : 
    5185         448 :   case MCK_PPR_3b:
    5186         448 :     return B == MCK_PPR;
    5187             : 
    5188           0 :   case MCK_Reg29:
    5189             :     switch (B) {
    5190             :     default: return false;
    5191             :     case MCK_Reg30: return true;
    5192             :     case MCK_Reg39: return true;
    5193             :     case MCK_Reg31: return true;
    5194             :     case MCK_Reg36: return true;
    5195             :     case MCK_Reg38: return true;
    5196             :     case MCK_Reg32: return true;
    5197             :     case MCK_Reg34: return true;
    5198             :     case MCK_Reg35: return true;
    5199             :     case MCK_Reg37: return true;
    5200             :     case MCK_QQQQ: return true;
    5201             :     }
    5202             : 
    5203           0 :   case MCK_Reg30:
    5204             :     switch (B) {
    5205             :     default: return false;
    5206             :     case MCK_Reg31: return true;
    5207             :     case MCK_Reg36: return true;
    5208             :     case MCK_Reg32: return true;
    5209             :     case MCK_Reg34: return true;
    5210             :     case MCK_Reg35: return true;
    5211             :     case MCK_QQQQ: return true;
    5212             :     }
    5213             : 
    5214           0 :   case MCK_Reg39:
    5215             :     switch (B) {
    5216             :     default: return false;
    5217             :     case MCK_Reg36: return true;
    5218             :     case MCK_Reg38: return true;
    5219             :     case MCK_Reg34: return true;
    5220             :     case MCK_Reg35: return true;
    5221             :     case MCK_Reg37: return true;
    5222             :     case MCK_QQQQ: return true;
    5223             :     }
    5224             : 
    5225           0 :   case MCK_Reg40:
    5226             :     switch (B) {
    5227             :     default: return false;
    5228             :     case MCK_Reg41: return true;
    5229             :     case MCK_Reg46: return true;
    5230             :     case MCK_Reg42: return true;
    5231             :     case MCK_Reg44: return true;
    5232             :     case MCK_Reg45: return true;
    5233             :     case MCK_QQQ: return true;
    5234             :     }
    5235             : 
    5236           0 :   case MCK_Reg25:
    5237           0 :     switch (B) {
    5238             :     default: return false;
    5239           0 :     case MCK_Reg26: return true;
    5240           0 :     case MCK_Reg28: return true;
    5241           0 :     case MCK_QQ: return true;
    5242             :     }
    5243             : 
    5244           0 :   case MCK_Reg31:
    5245           0 :     switch (B) {
    5246             :     default: return false;
    5247           0 :     case MCK_Reg32: return true;
    5248           0 :     case MCK_Reg34: return true;
    5249           0 :     case MCK_QQQQ: return true;
    5250             :     }
    5251             : 
    5252           0 :   case MCK_Reg36:
    5253           0 :     switch (B) {
    5254             :     default: return false;
    5255           0 :     case MCK_Reg34: return true;
    5256           0 :     case MCK_Reg35: return true;
    5257           0 :     case MCK_QQQQ: return true;
    5258             :     }
    5259             : 
    5260           0 :   case MCK_Reg38:
    5261           0 :     switch (B) {
    5262             :     default: return false;
    5263           0 :     case MCK_Reg35: return true;
    5264           0 :     case MCK_Reg37: return true;
    5265           0 :     case MCK_QQQQ: return true;
    5266             :     }
    5267             : 
    5268           0 :   case MCK_Reg41:
    5269           0 :     switch (B) {
    5270             :     default: return false;
    5271           0 :     case MCK_Reg42: return true;
    5272           0 :     case MCK_Reg44: return true;
    5273           0 :     case MCK_QQQ: return true;
    5274             :     }
    5275             : 
    5276           0 :   case MCK_Reg46:
    5277           0 :     switch (B) {
    5278             :     default: return false;
    5279           0 :     case MCK_Reg44: return true;
    5280           0 :     case MCK_Reg45: return true;
    5281           0 :     case MCK_QQQ: return true;
    5282             :     }
    5283             : 
    5284        4484 :   case MCK_Reg20:
    5285        4484 :     return B == MCK_ZPR;
    5286             : 
    5287           0 :   case MCK_Reg26:
    5288           0 :     return B == MCK_QQ;
    5289             : 
    5290           0 :   case MCK_Reg28:
    5291           0 :     return B == MCK_QQ;
    5292             : 
    5293           0 :   case MCK_Reg32:
    5294           0 :     return B == MCK_QQQQ;
    5295             : 
    5296           0 :   case MCK_Reg34:
    5297           0 :     return B == MCK_QQQQ;
    5298             : 
    5299           0 :   case MCK_Reg35:
    5300           0 :     return B == MCK_QQQQ;
    5301             : 
    5302           0 :   case MCK_Reg37:
    5303           0 :     return B == MCK_QQQQ;
    5304             : 
    5305           0 :   case MCK_Reg42:
    5306           0 :     return B == MCK_QQQ;
    5307             : 
    5308           0 :   case MCK_Reg44:
    5309           0 :     return B == MCK_QQQ;
    5310             : 
    5311           0 :   case MCK_Reg45:
    5312           0 :     return B == MCK_QQQ;
    5313             : 
    5314       40783 :   case MCK_FPR128_lo:
    5315       40783 :     return B == MCK_FPR128;
    5316             : 
    5317          27 :   case MCK_Reg51:
    5318             :     switch (B) {
    5319             :     default: return false;
    5320             :     case MCK_Reg52: return true;
    5321             :     case MCK_Reg57: return true;
    5322             :     case MCK_Reg53: return true;
    5323             :     case MCK_Reg54: return true;
    5324             :     case MCK_Reg56: return true;
    5325             :     case MCK_XSeqPairsClass: return true;
    5326             :     }
    5327             : 
    5328           0 :   case MCK_Reg52:
    5329             :     switch (B) {
    5330             :     default: return false;
    5331             :     case MCK_Reg53: return true;
    5332             :     case MCK_Reg54: return true;
    5333             :     case MCK_Reg56: return true;
    5334             :     case MCK_XSeqPairsClass: return true;
    5335             :     }
    5336             : 
    5337           0 :   case MCK_Reg57:
    5338           0 :     switch (B) {
    5339             :     default: return false;
    5340           0 :     case MCK_Reg56: return true;
    5341           0 :     case MCK_XSeqPairsClass: return true;
    5342             :     }
    5343             : 
    5344       39120 :   case MCK_tcGPR64:
    5345             :     switch (B) {
    5346             :     default: return false;
    5347             :     case MCK_GPR64common: return true;
    5348             :     case MCK_GPR64: return true;
    5349             :     case MCK_GPR64sp: return true;
    5350             :     case MCK_GPR64all: return true;
    5351             :     }
    5352             : 
    5353           2 :   case MCK_Reg47:
    5354             :     switch (B) {
    5355             :     default: return false;
    5356             :     case MCK_Reg48: return true;
    5357             :     case MCK_Reg50: return true;
    5358             :     case MCK_WSeqPairsClass: return true;
    5359             :     }
    5360             : 
    5361           0 :   case MCK_Reg53:
    5362             :     switch (B) {
    5363             :     default: return false;
    5364             :     case MCK_Reg54: return true;
    5365             :     case MCK_Reg56: return true;
    5366             :     case MCK_XSeqPairsClass: return true;
    5367             :     }
    5368             : 
    5369           0 :   case MCK_Reg48:
    5370           0 :     return B == MCK_WSeqPairsClass;
    5371             : 
    5372           0 :   case MCK_Reg50:
    5373           0 :     return B == MCK_WSeqPairsClass;
    5374             : 
    5375           0 :   case MCK_Reg54:
    5376           0 :     return B == MCK_XSeqPairsClass;
    5377             : 
    5378           0 :   case MCK_Reg56:
    5379           0 :     return B == MCK_XSeqPairsClass;
    5380             : 
    5381       25155 :   case MCK_GPR32common:
    5382             :     switch (B) {
    5383             :     default: return false;
    5384             :     case MCK_GPR32: return true;
    5385             :     case MCK_GPR32sp: return true;
    5386             :     case MCK_GPR32all: return true;
    5387             :     }
    5388             : 
    5389        8196 :   case MCK_GPR64common:
    5390             :     switch (B) {
    5391             :     default: return false;
    5392             :     case MCK_GPR64: return true;
    5393             :     case MCK_GPR64sp: return true;
    5394             :     case MCK_GPR64all: return true;
    5395             :     }
    5396             : 
    5397       19233 :   case MCK_GPR32:
    5398       19233 :     return B == MCK_GPR32all;
    5399             : 
    5400        3632 :   case MCK_GPR32sp:
    5401        3632 :     return B == MCK_GPR32all;
    5402             : 
    5403       14113 :   case MCK_GPR64:
    5404       14113 :     return B == MCK_GPR64all;
    5405             : 
    5406        3246 :   case MCK_GPR64sp:
    5407        3246 :     return B == MCK_GPR64all;
    5408             : 
    5409           0 :   case MCK_Extend64:
    5410           0 :     return B == MCK_Extend;
    5411             : 
    5412           0 :   case MCK_ExtendLSL64:
    5413           0 :     return B == MCK_Extend;
    5414             : 
    5415           3 :   case MCK_LogicalVecHalfWordShifter:
    5416           3 :     switch (B) {
    5417             :     default: return false;
    5418           0 :     case MCK_LogicalVecShifter: return true;
    5419           0 :     case MCK_Shifter: return true;
    5420             :     }
    5421             : 
    5422           0 :   case MCK_ArithmeticShifter32:
    5423           0 :     return B == MCK_Shifter;
    5424             : 
    5425           0 :   case MCK_ArithmeticShifter64:
    5426           0 :     return B == MCK_Shifter;
    5427             : 
    5428           0 :   case MCK_LogicalShifter32:
    5429           0 :     return B == MCK_Shifter;
    5430             : 
    5431           0 :   case MCK_LogicalShifter64:
    5432           0 :     return B == MCK_Shifter;
    5433             : 
    5434          19 :   case MCK_LogicalVecShifter:
    5435          19 :     return B == MCK_Shifter;
    5436             : 
    5437           0 :   case MCK_MovImm32Shifter:
    5438           0 :     return B == MCK_Shifter;
    5439             : 
    5440           0 :   case MCK_MovImm64Shifter:
    5441           0 :     return B == MCK_Shifter;
    5442             : 
    5443           2 :   case MCK_MoveVecShifter:
    5444           2 :     return B == MCK_Shifter;
    5445             :   }
    5446             : }
    5447             : 
    5448      375180 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
    5449             :   AArch64Operand &Operand = (AArch64Operand&)GOp;
    5450      375180 :   if (Kind == InvalidMatchClass)
    5451             :     return MCTargetAsmParser::Match_InvalidOperand;
    5452             : 
    5453      372135 :   if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
    5454      125556 :     return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
    5455             :              MCTargetAsmParser::Match_Success :
    5456             :              MCTargetAsmParser::Match_InvalidOperand;
    5457             : 
    5458      309357 :   switch (Kind) {
    5459             :   default: break;
    5460             :   // 'AddSubImmNeg' class
    5461         970 :   case MCK_AddSubImmNeg:
    5462         970 :     if (Operand.isAddSubImmNeg())
    5463             :       return MCTargetAsmParser::Match_Success;
    5464         910 :     return AArch64AsmParser::Match_AddSubSecondSource;
    5465             :   // 'AddSubImm' class
    5466         950 :   case MCK_AddSubImm:
    5467         950 :     if (Operand.isAddSubImm())
    5468             :       return MCTargetAsmParser::Match_Success;
    5469         496 :     return AArch64AsmParser::Match_AddSubSecondSource;
    5470             :   // 'AdrLabel' class
    5471          31 :   case MCK_AdrLabel:
    5472          14 :     if (Operand.isAdrLabel())
    5473             :       return MCTargetAsmParser::Match_Success;
    5474           6 :     return AArch64AsmParser::Match_InvalidLabel;
    5475             :   // 'AdrpLabel' class
    5476         181 :   case MCK_AdrpLabel:
    5477             :     if (Operand.isAdrpLabel())
    5478             :       return MCTargetAsmParser::Match_Success;
    5479             :     return AArch64AsmParser::Match_InvalidLabel;
    5480             :   // 'Barrier' class
    5481          45 :   case MCK_Barrier:
    5482          45 :     if (Operand.isBarrier())
    5483             :       return MCTargetAsmParser::Match_Success;
    5484             :     break;
    5485             :   // 'BranchTarget14' class
    5486             :   case MCK_BranchTarget14:
    5487           3 :     if (Operand.isBranchTarget<14>())
    5488             :       return MCTargetAsmParser::Match_Success;
    5489           0 :     return AArch64AsmParser::Match_InvalidLabel;
    5490             :   // 'BranchTarget26' class
    5491             :   case MCK_BranchTarget26:
    5492          11 :     if (Operand.isBranchTarget<26>())
    5493             :       return MCTargetAsmParser::Match_Success;
    5494         106 :     return AArch64AsmParser::Match_InvalidLabel;
    5495             :   // 'CondCode' class
    5496         263 :   case MCK_CondCode:
    5497         263 :     if (Operand.isCondCode())
    5498             :       return MCTargetAsmParser::Match_Success;
    5499           4 :     return AArch64AsmParser::Match_InvalidCondCode;
    5500             :   // 'Extend64' class
    5501             :   case MCK_Extend64:
    5502          32 :     if (Operand.isExtend64())
    5503             :       return MCTargetAsmParser::Match_Success;
    5504           4 :     return AArch64AsmParser::Match_AddSubRegExtendSmall;
    5505             :   // 'ExtendLSL64' class
    5506          64 :   case MCK_ExtendLSL64:
    5507          64 :     if (Operand.isExtendLSL64())
    5508             :       return MCTargetAsmParser::Match_Success;
    5509          40 :     return AArch64AsmParser::Match_AddSubRegExtendLarge;
    5510             :   // 'Extend' class
    5511         191 :   case MCK_Extend:
    5512         191 :     if (Operand.isExtend())
    5513             :       return MCTargetAsmParser::Match_Success;
    5514          36 :     return AArch64AsmParser::Match_AddSubRegExtendLarge;
    5515             :   // 'FPImm' class
    5516          52 :   case MCK_FPImm:
    5517          52 :     if (Operand.isFPImm())
    5518             :       return MCTargetAsmParser::Match_Success;
    5519          16 :     return AArch64AsmParser::Match_InvalidFPImm;
    5520             :   // 'GPR32as64' class
    5521          24 :   case MCK_GPR32as64:
    5522          24 :     if (Operand.isGPR32as64())
    5523             :       return MCTargetAsmParser::Match_Success;
    5524             :     break;
    5525             :   // 'GPR64sp0' class
    5526         117 :   case MCK_GPR64sp0:
    5527         117 :     if (Operand.isGPR64sp0())
    5528             :       return MCTargetAsmParser::Match_Success;
    5529             :     break;
    5530             :   // 'Imm0_127' class
    5531             :   case MCK_Imm0_127:
    5532           6 :     if (Operand.isImmInRange<0,127>())
    5533             :       return MCTargetAsmParser::Match_Success;
    5534           4 :     return AArch64AsmParser::Match_InvalidImm0_127;
    5535             :   // 'Imm0_15' class
    5536             :   case MCK_Imm0_15:
    5537         175 :     if (Operand.isImmInRange<0,15>())
    5538             :       return MCTargetAsmParser::Match_Success;
    5539          76 :     return AArch64AsmParser::Match_InvalidImm0_15;
    5540             :   // 'Imm0_1' class
    5541             :   case MCK_Imm0_1:
    5542          10 :     if (Operand.isImmInRange<0,1>())
    5543             :       return MCTargetAsmParser::Match_Success;
    5544           8 :     return AArch64AsmParser::Match_InvalidImm0_1;
    5545             :   // 'Imm0_255' class
    5546             :   case MCK_Imm0_255:
    5547         335 :     if (Operand.isImmInRange<0,255>())
    5548             :       return MCTargetAsmParser::Match_Success;
    5549          21 :     return AArch64AsmParser::Match_InvalidImm0_255;
    5550             :   // 'Imm0_31' class
    5551             :   case MCK_Imm0_31:
    5552         256 :     if (Operand.isImmInRange<0,31>())
    5553             :       return MCTargetAsmParser::Match_Success;
    5554          85 :     return AArch64AsmParser::Match_InvalidImm0_31;
    5555             :   // 'Imm0_63' class
    5556             :   case MCK_Imm0_63:
    5557         183 :     if (Operand.isImmInRange<0,63>())
    5558             :       return MCTargetAsmParser::Match_Success;
    5559          43 :     return AArch64AsmParser::Match_InvalidImm0_63;
    5560             :   // 'Imm0_65535' class
    5561             :   case MCK_Imm0_65535:
    5562         122 :     if (Operand.isImmInRange<0,65535>())
    5563             :       return MCTargetAsmParser::Match_Success;
    5564         307 :     return AArch64AsmParser::Match_InvalidImm0_65535;
    5565             :   // 'Imm0_7' class
    5566             :   case MCK_Imm0_7:
    5567         611 :     if (Operand.isImmInRange<0,7>())
    5568             :       return MCTargetAsmParser::Match_Success;
    5569          33 :     return AArch64AsmParser::Match_InvalidImm0_7;
    5570             :   // 'Imm1_16' class
    5571             :   case MCK_Imm1_16:
    5572         146 :     if (Operand.isImmInRange<1,16>())
    5573             :       return MCTargetAsmParser::Match_Success;
    5574          30 :     return AArch64AsmParser::Match_InvalidImm1_16;
    5575             :   // 'Imm1_32' class
    5576             :   case MCK_Imm1_32:
    5577         224 :     if (Operand.isImmInRange<1,32>())
    5578             :       return MCTargetAsmParser::Match_Success;
    5579          52 :     return AArch64AsmParser::Match_InvalidImm1_32;
    5580             :   // 'Imm1_64' class
    5581             :   case MCK_Imm1_64:
    5582         149 :     if (Operand.isImmInRange<1,64>())
    5583             :       return MCTargetAsmParser::Match_Success;
    5584          45 :     return AArch64AsmParser::Match_InvalidImm1_64;
    5585             :   // 'Imm1_8' class
    5586             :   case MCK_Imm1_8:
    5587         128 :     if (Operand.isImmInRange<1,8>())
    5588             :       return MCTargetAsmParser::Match_Success;
    5589          32 :     return AArch64AsmParser::Match_InvalidImm1_8;
    5590             :   // 'Imm' class
    5591           2 :   case MCK_Imm:
    5592           2 :     if (Operand.isImm())
    5593             :       return MCTargetAsmParser::Match_Success;
    5594             :     break;
    5595             :   // 'LogicalImm32Not' class
    5596          32 :   case MCK_LogicalImm32Not:
    5597          32 :     if (Operand.isLogicalImm<int32_t>())
    5598             :       return MCTargetAsmParser::Match_Success;
    5599          20 :     return AArch64AsmParser::Match_LogicalSecondSource;
    5600             :   // 'LogicalImm32' class
    5601         104 :   case MCK_LogicalImm32:
    5602         104 :     if (Operand.isLogicalImm<int32_t>())
    5603             :       return MCTargetAsmParser::Match_Success;
    5604          62 :     return AArch64AsmParser::Match_LogicalSecondSource;
    5605             :   // 'LogicalImm64Not' class
    5606          40 :   case MCK_LogicalImm64Not:
    5607          40 :     if (Operand.isLogicalImm<int64_t>())
    5608             :       return MCTargetAsmParser::Match_Success;
    5609          21 :     return AArch64AsmParser::Match_LogicalSecondSource;
    5610             :   // 'LogicalImm64' class
    5611          95 :   case MCK_LogicalImm64:
    5612          95 :     if (Operand.isLogicalImm<int64_t>())
    5613             :       return MCTargetAsmParser::Match_Success;
    5614          42 :     return AArch64AsmParser::Match_LogicalSecondSource;
    5615             :   // 'MRSSystemRegister' class
    5616             :   case MCK_MRSSystemRegister:
    5617        1123 :     if (Operand.isMRSSystemRegister())
    5618             :       return MCTargetAsmParser::Match_Success;
    5619          90 :     return AArch64AsmParser::Match_MRS;
    5620             :   // 'MSRSystemRegister' class
    5621             :   case MCK_MSRSystemRegister:
    5622        1029 :     if (Operand.isMSRSystemRegister())
    5623             :       return MCTargetAsmParser::Match_Success;
    5624         253 :     return AArch64AsmParser::Match_MSR;
    5625             :   // 'MemWExtend128' class
    5626          13 :   case MCK_MemWExtend128:
    5627          13 :     if (Operand.isMemWExtend<128>())
    5628             :       return MCTargetAsmParser::Match_Success;
    5629           6 :     return AArch64AsmParser::Match_InvalidMemoryWExtend128;
    5630             :   // 'MemWExtend16' class
    5631          12 :   case MCK_MemWExtend16:
    5632          12 :     if (Operand.isMemWExtend<16>())
    5633             :       return MCTargetAsmParser::Match_Success;
    5634           6 :     return AArch64AsmParser::Match_InvalidMemoryWExtend16;
    5635             :   // 'MemWExtend32' class
    5636          16 :   case MCK_MemWExtend32:
    5637          16 :     if (Operand.isMemWExtend<32>())
    5638             :       return MCTargetAsmParser::Match_Success;
    5639          10 :     return AArch64AsmParser::Match_InvalidMemoryWExtend32;
    5640             :   // 'MemWExtend64' class
    5641          15 :   case MCK_MemWExtend64:
    5642          15 :     if (Operand.isMemWExtend<64>())
    5643             :       return MCTargetAsmParser::Match_Success;
    5644           8 :     return AArch64AsmParser::Match_InvalidMemoryWExtend64;
    5645             :   // 'MemWExtend8' class
    5646           8 :   case MCK_MemWExtend8:
    5647           8 :     if (Operand.isMemWExtend<8>())
    5648             :       return MCTargetAsmParser::Match_Success;
    5649           4 :     return AArch64AsmParser::Match_InvalidMemoryWExtend8;
    5650             :   // 'MemXExtend128' class
    5651           6 :   case MCK_MemXExtend128:
    5652           6 :     if (Operand.isMemXExtend<128>())
    5653             :       return MCTargetAsmParser::Match_Success;
    5654           0 :     return AArch64AsmParser::Match_InvalidMemoryXExtend128;
    5655             :   // 'MemXExtend16' class
    5656           6 :   case MCK_MemXExtend16:
    5657           6 :     if (Operand.isMemXExtend<16>())
    5658             :       return MCTargetAsmParser::Match_Success;
    5659           0 :     return AArch64AsmParser::Match_InvalidMemoryXExtend16;
    5660             :   // 'MemXExtend32' class
    5661          15 :   case MCK_MemXExtend32:
    5662          15 :     if (Operand.isMemXExtend<32>())
    5663             :       return MCTargetAsmParser::Match_Success;
    5664           6 :     return AArch64AsmParser::Match_InvalidMemoryXExtend32;
    5665             :   // 'MemXExtend64' class
    5666          13 :   case MCK_MemXExtend64:
    5667          13 :     if (Operand.isMemXExtend<64>())
    5668             :       return MCTargetAsmParser::Match_Success;
    5669           2 :     return AArch64AsmParser::Match_InvalidMemoryXExtend64;
    5670             :   // 'MemXExtend8' class
    5671           6 :   case MCK_MemXExtend8:
    5672           6 :     if (Operand.isMemXExtend<8>())
    5673             :       return MCTargetAsmParser::Match_Success;
    5674           2 :     return AArch64AsmParser::Match_InvalidMemoryXExtend8;
    5675             :   // 'MovKSymbolG0' class
    5676             :   case MCK_MovKSymbolG0:
    5677          94 :     if (Operand.isMovKSymbolG0())
    5678             :       return MCTargetAsmParser::Match_Success;
    5679             :     break;
    5680             :   // 'MovKSymbolG1' class
    5681             :   case MCK_MovKSymbolG1:
    5682          64 :     if (Operand.isMovKSymbolG1())
    5683             :       return MCTargetAsmParser::Match_Success;
    5684             :     break;
    5685             :   // 'MovKSymbolG2' class
    5686             :   case MCK_MovKSymbolG2:
    5687          21 :     if (Operand.isMovKSymbolG2())
    5688             :       return MCTargetAsmParser::Match_Success;
    5689             :     break;
    5690             :   // 'MovKSymbolG3' class
    5691             :   case MCK_MovKSymbolG3:
    5692          13 :     if (Operand.isMovKSymbolG3())
    5693             :       return MCTargetAsmParser::Match_Success;
    5694             :     break;
    5695             :   // 'MovZSymbolG0' class
    5696             :   case MCK_MovZSymbolG0:
    5697         186 :     if (Operand.isMovZSymbolG0())
    5698             :       return MCTargetAsmParser::Match_Success;
    5699             :     break;
    5700             :   // 'MovZSymbolG1' class
    5701             :   case MCK_MovZSymbolG1:
    5702         147 :     if (Operand.isMovZSymbolG1())
    5703             :       return MCTargetAsmParser::Match_Success;
    5704             :     break;
    5705             :   // 'MovZSymbolG2' class
    5706             :   case MCK_MovZSymbolG2:
    5707          74 :     if (Operand.isMovZSymbolG2())
    5708             :       return MCTargetAsmParser::Match_Success;
    5709             :     break;
    5710             :   // 'MovZSymbolG3' class
    5711             :   case MCK_MovZSymbolG3:
    5712          41 :     if (Operand.isMovZSymbolG3())
    5713             :       return MCTargetAsmParser::Match_Success;
    5714             :     break;
    5715             :   // 'PCRelLabel19' class
    5716             :   case MCK_PCRelLabel19:
    5717          29 :     if (Operand.isBranchTarget<19>())
    5718             :       return MCTargetAsmParser::Match_Success;
    5719         650 :     return AArch64AsmParser::Match_InvalidLabel;
    5720             :   // 'SVEPredicateHReg' class
    5721             :   case MCK_SVEPredicateHReg:
    5722             :     if (Operand.isSVEVectorRegOfWidth<16, AArch64::PPRRegClassID>())
    5723             :       return MCTargetAsmParser::Match_Success;
    5724             :     return AArch64AsmParser::Match_InvalidSVEPredicateHReg;
    5725             :   // 'SVEPredicateSReg' class
    5726             :   case MCK_SVEPredicateSReg:
    5727             :     if (Operand.isSVEVectorRegOfWidth<32, AArch64::PPRRegClassID>())
    5728             :       return MCTargetAsmParser::Match_Success;
    5729             :     return AArch64AsmParser::Match_InvalidSVEPredicateSReg;
    5730             :   // 'SVEPredicate3bHReg' class
    5731             :   case MCK_SVEPredicate3bHReg:
    5732             :     if (Operand.isSVEVectorRegOfWidth<16, AArch64::PPR_3bRegClassID>())
    5733             :       return MCTargetAsmParser::Match_Success;
    5734             :     return AArch64AsmParser::Match_InvalidSVEPredicate3bHReg;
    5735             :   // 'SVEPredicate3bSReg' class
    5736             :   case MCK_SVEPredicate3bSReg:
    5737             :     if (Operand.isSVEVectorRegOfWidth<32, AArch64::PPR_3bRegClassID>())
    5738             :       return MCTargetAsmParser::Match_Success;
    5739             :     return AArch64AsmParser::Match_InvalidSVEPredicate3bSReg;
    5740             :   // 'SVEPredicate3bDReg' class
    5741             :   case MCK_SVEPredicate3bDReg:
    5742             :     if (Operand.isSVEVectorRegOfWidth<64, AArch64::PPR_3bRegClassID>())
    5743             :       return MCTargetAsmParser::Match_Success;
    5744             :     return AArch64AsmParser::Match_InvalidSVEPredicate3bDReg;
    5745             :   // 'SVEPredicate3bBReg' class
    5746             :   case MCK_SVEPredicate3bBReg:
    5747             :     if (Operand.isSVEVectorRegOfWidth<8, AArch64::PPR_3bRegClassID>())
    5748             :       return MCTargetAsmParser::Match_Success;
    5749             :     return AArch64AsmParser::Match_InvalidSVEPredicate3bBReg;
    5750             :   // 'SVEPredicate3bAnyReg' class
    5751             :   case MCK_SVEPredicate3bAnyReg:
    5752             :     if (Operand.isSVEVectorRegOfWidth<-1, AArch64::PPR_3bRegClassID>())
    5753             :       return MCTargetAsmParser::Match_Success;
    5754             :     return AArch64AsmParser::Match_InvalidSVEPredicate3bAnyReg;
    5755             :   // 'SVEPredicateDReg' class
    5756             :   case MCK_SVEPredicateDReg:
    5757             :     if (Operand.isSVEVectorRegOfWidth<64, AArch64::PPRRegClassID>())
    5758             :       return MCTargetAsmParser::Match_Success;
    5759             :     return AArch64AsmParser::Match_InvalidSVEPredicateDReg;
    5760             :   // 'SVEPredicateBReg' class
    5761             :   case MCK_SVEPredicateBReg:
    5762             :     if (Operand.isSVEVectorRegOfWidth<8, AArch64::PPRRegClassID>())
    5763             :       return MCTargetAsmParser::Match_Success;
    5764             :     return AArch64AsmParser::Match_InvalidSVEPredicateBReg;
    5765             :   // 'SVEPredicateAnyReg' class
    5766             :   case MCK_SVEPredicateAnyReg:
    5767             :     if (Operand.isSVEVectorRegOfWidth<-1, AArch64::PPRRegClassID>())
    5768             :       return MCTargetAsmParser::Match_Success;
    5769             :     return AArch64AsmParser::Match_InvalidSVEPredicateAnyReg;
    5770             :   // 'PSBHint' class
    5771           3 :   case MCK_PSBHint:
    5772           3 :     if (Operand.isPSBHint())
    5773             :       return MCTargetAsmParser::Match_Success;
    5774             :     break;
    5775             :   // 'Prefetch' class
    5776         139 :   case MCK_Prefetch:
    5777         139 :     if (Operand.isPrefetch())
    5778             :       return MCTargetAsmParser::Match_Success;
    5779             :     break;
    5780             :   // 'SIMDImmType10' class
    5781             :   case MCK_SIMDImmType10:
    5782           8 :     if (Operand.isSIMDImmType10())
    5783             :       return MCTargetAsmParser::Match_Success;
    5784             :     break;
    5785             :   // 'SImm10s8' class
    5786             :   case MCK_SImm10s8:
    5787             :     if (Operand.isSImmScaled<10, 8>())
    5788             :       return MCTargetAsmParser::Match_Success;
    5789             :     return AArch64AsmParser::Match_InvalidMemoryIndexedSImm10;
    5790             :   // 'SImm6' class
    5791             :   case MCK_SImm6:
    5792          66 :     if (Operand.isSImm<6>())
    5793             :       return MCTargetAsmParser::Match_Success;
    5794          12 :     return AArch64AsmParser::Match_InvalidMemoryIndexedSImm6;
    5795             :   // 'SImm7s16' class
    5796             :   case MCK_SImm7s16:
    5797             :     if (Operand.isSImmScaled<7, 16>())
    5798             :       return MCTargetAsmParser::Match_Success;
    5799             :     return AArch64AsmParser::Match_InvalidMemoryIndexed16SImm7;
    5800             :   // 'SImm7s4' class
    5801             :   case MCK_SImm7s4:
    5802             :     if (Operand.isSImmScaled<7, 4>())
    5803             :       return MCTargetAsmParser::Match_Success;
    5804             :     return AArch64AsmParser::Match_InvalidMemoryIndexed4SImm7;
    5805             :   // 'SImm7s8' class
    5806             :   case MCK_SImm7s8:
    5807             :     if (Operand.isSImmScaled<7, 8>())
    5808             :       return MCTargetAsmParser::Match_Success;
    5809             :     return AArch64AsmParser::Match_InvalidMemoryIndexed8SImm7;
    5810             :   // 'SImm9OffsetFB128' class
    5811          94 :   case MCK_SImm9OffsetFB128:
    5812          94 :     if (Operand.isSImm9OffsetFB<128>())
    5813             :       return MCTargetAsmParser::Match_Success;
    5814             :     break;
    5815             :   // 'SImm9OffsetFB16' class
    5816         218 :   case MCK_SImm9OffsetFB16:
    5817         218 :     if (Operand.isSImm9OffsetFB<16>())
    5818             :       return MCTargetAsmParser::Match_Success;
    5819             :     break;
    5820             :   // 'SImm9OffsetFB32' class
    5821         235 :   case MCK_SImm9OffsetFB32:
    5822         235 :     if (Operand.isSImm9OffsetFB<32>())
    5823             :       return MCTargetAsmParser::Match_Success;
    5824             :     break;
    5825             :   // 'SImm9OffsetFB64' class
    5826         302 :   case MCK_SImm9OffsetFB64:
    5827         302 :     if (Operand.isSImm9OffsetFB<64>())
    5828             :       return MCTargetAsmParser::Match_Success;
    5829             :     break;
    5830             :   // 'SImm9OffsetFB8' class
    5831         203 :   case MCK_SImm9OffsetFB8:
    5832         203 :     if (Operand.isSImm9OffsetFB<8>())
    5833             :       return MCTargetAsmParser::Match_Success;
    5834             :     break;
    5835             :   // 'SImm9' class
    5836             :   case MCK_SImm9:
    5837         469 :     if (Operand.isSImm<9>())
    5838             :       return MCTargetAsmParser::Match_Success;
    5839         346 :     return AArch64AsmParser::Match_InvalidMemoryIndexedSImm9;
    5840             :   // 'SVEPattern' class
    5841             :   case MCK_SVEPattern:
    5842         368 :     if (Operand.isSVEPattern())
    5843             :       return MCTargetAsmParser::Match_Success;
    5844          16 :     return AArch64AsmParser::Match_InvalidSVEPattern;
    5845             :   // 'LogicalVecHalfWordShifter' class
    5846          27 :   case MCK_LogicalVecHalfWordShifter:
    5847          27 :     if (Operand.isLogicalVecHalfWordShifter())
    5848             :       return MCTargetAsmParser::Match_Success;
    5849             :     break;
    5850             :   // 'ArithmeticShifter32' class
    5851             :   case MCK_ArithmeticShifter32:
    5852             :     if (Operand.isArithmeticShifter<32>())
    5853             :       return MCTargetAsmParser::Match_Success;
    5854             :     return AArch64AsmParser::Match_AddSubRegShift32;
    5855             :   // 'ArithmeticShifter64' class
    5856             :   case MCK_ArithmeticShifter64:
    5857             :     if (Operand.isArithmeticShifter<64>())
    5858             :       return MCTargetAsmParser::Match_Success;
    5859             :     return AArch64AsmParser::Match_AddSubRegShift64;
    5860             :   // 'LogicalShifter32' class
    5861             :   case MCK_LogicalShifter32:
    5862             :     if (Operand.isLogicalShifter<32>())
    5863             :       return MCTargetAsmParser::Match_Success;
    5864             :     return AArch64AsmParser::Match_AddSubRegShift32;
    5865             :   // 'LogicalShifter64' class
    5866             :   case MCK_LogicalShifter64:
    5867             :     if (Operand.isLogicalShifter<64>())
    5868             :       return MCTargetAsmParser::Match_Success;
    5869             :     return AArch64AsmParser::Match_AddSubRegShift64;
    5870             :   // 'LogicalVecShifter' class
    5871          75 :   case MCK_LogicalVecShifter:
    5872          75 :     if (Operand.isLogicalVecShifter())
    5873             :       return MCTargetAsmParser::Match_Success;
    5874             :     break;
    5875             :   // 'MovImm32Shifter' class
    5876             :   case MCK_MovImm32Shifter:
    5877          15 :     if (Operand.isMovImm32Shifter())
    5878             :       return MCTargetAsmParser::Match_Success;
    5879           4 :     return AArch64AsmParser::Match_InvalidMovImm32Shift;
    5880             :   // 'MovImm64Shifter' class
    5881          16 :   case MCK_MovImm64Shifter:
    5882          16 :     if (Operand.isMovImm64Shifter())
    5883             :       return MCTargetAsmParser::Match_Success;
    5884           2 :     return AArch64AsmParser::Match_InvalidMovImm64Shift;
    5885             :   // 'MoveVecShifter' class
    5886             :   case MCK_MoveVecShifter:
    5887             :     if (Operand.isMoveVecShifter())
    5888             :       return MCTargetAsmParser::Match_Success;
    5889             :     break;
    5890             :   // 'Shifter' class
    5891             :   case MCK_Shifter:
    5892           0 :     if (Operand.isShifter())
    5893             :       return MCTargetAsmParser::Match_Success;
    5894             :     break;
    5895             :   // 'SysCR' class
    5896         552 :   case MCK_SysCR:
    5897         552 :     if (Operand.isSysCR())
    5898             :       return MCTargetAsmParser::Match_Success;
    5899             :     break;
    5900             :   // 'SystemPStateFieldWithImm0_15' class
    5901             :   case MCK_SystemPStateFieldWithImm0_15:
    5902         267 :     if (Operand.isSystemPStateFieldWithImm0_15())
    5903             :       return MCTargetAsmParser::Match_Success;
    5904             :     break;
    5905             :   // 'SystemPStateFieldWithImm0_1' class
    5906             :   case MCK_SystemPStateFieldWithImm0_1:
    5907         274 :     if (Operand.isSystemPStateFieldWithImm0_1())
    5908             :       return MCTargetAsmParser::Match_Success;
    5909             :     break;
    5910             :   // 'TBZImm0_31' class
    5911             :   case MCK_TBZImm0_31:
    5912          16 :     if (Operand.isImmInRange<0,31>())
    5913             :       return MCTargetAsmParser::Match_Success;
    5914             :     break;
    5915             :   // 'Imm32_63' class
    5916             :   case MCK_Imm32_63:
    5917          23 :     if (Operand.isImmInRange<32,63>())
    5918             :       return MCTargetAsmParser::Match_Success;
    5919          16 :     return AArch64AsmParser::Match_InvalidImm0_63;
    5920             :   // 'UImm12Offset16' class
    5921          89 :   case MCK_UImm12Offset16:
    5922          89 :     if (Operand.isUImm12Offset<16>())
    5923             :       return MCTargetAsmParser::Match_Success;
    5924          36 :     return AArch64AsmParser::Match_InvalidMemoryIndexed16;
    5925             :   // 'UImm12Offset1' class
    5926         197 :   case MCK_UImm12Offset1:
    5927         197 :     if (Operand.isUImm12Offset<1>())
    5928             :       return MCTargetAsmParser::Match_Success;
    5929          59 :     return AArch64AsmParser::Match_InvalidMemoryIndexed1;
    5930             :   // 'UImm12Offset2' class
    5931         204 :   case MCK_UImm12Offset2:
    5932         204 :     if (Operand.isUImm12Offset<2>())
    5933             :       return MCTargetAsmParser::Match_Success;
    5934          75 :     return AArch64AsmParser::Match_InvalidMemoryIndexed2;
    5935             :   // 'UImm12Offset4' class
    5936         224 :   case MCK_UImm12Offset4:
    5937         224 :     if (Operand.isUImm12Offset<4>())
    5938             :       return MCTargetAsmParser::Match_Success;
    5939          85 :     return AArch64AsmParser::Match_InvalidMemoryIndexed4;
    5940             :   // 'UImm12Offset8' class
    5941         306 :   case MCK_UImm12Offset8:
    5942         306 :     if (Operand.isUImm12Offset<8>())
    5943             :       return MCTargetAsmParser::Match_Success;
    5944          68 :     return AArch64AsmParser::Match_InvalidMemoryIndexed8;
    5945             :   // 'VecListFour128' class
    5946             :   case MCK_VecListFour128:
    5947             :     if (Operand.isImplicitlyTypedVectorList<4>())
    5948             :       return MCTargetAsmParser::Match_Success;
    5949             :     break;
    5950             :   // 'TypedVectorList4_16b' class
    5951             :   case MCK_TypedVectorList4_16b:
    5952         175 :     if (Operand.isTypedVectorList<4, 16, 'b'>())
    5953             :       return MCTargetAsmParser::Match_Success;
    5954             :     break;
    5955             :   // 'TypedVectorList4_1d' class
    5956             :   case MCK_TypedVectorList4_1d:
    5957          71 :     if (Operand.isTypedVectorList<4, 1, 'd'>())
    5958             :       return MCTargetAsmParser::Match_Success;
    5959             :     break;
    5960             :   // 'TypedVectorList4_2d' class
    5961             :   case MCK_TypedVectorList4_2d:
    5962         112 :     if (Operand.isTypedVectorList<4, 2, 'd'>())
    5963             :       return MCTargetAsmParser::Match_Success;
    5964             :     break;
    5965             :   // 'TypedVectorList4_2s' class
    5966             :   case MCK_TypedVectorList4_2s:
    5967         139 :     if (Operand.isTypedVectorList<4, 2, 's'>())
    5968             :       return MCTargetAsmParser::Match_Success;
    5969             :     break;
    5970             :   // 'TypedVectorList4_4h' class
    5971             :   case MCK_TypedVectorList4_4h:
    5972         144 :     if (Operand.isTypedVectorList<4, 4, 'h'>())
    5973             :       return MCTargetAsmParser::Match_Success;
    5974             :     break;
    5975             :   // 'TypedVectorList4_4s' class
    5976             :   case MCK_TypedVectorList4_4s:
    5977          94 :     if (Operand.isTypedVectorList<4, 4, 's'>())
    5978             :       return MCTargetAsmParser::Match_Success;
    5979             :     break;
    5980             :   // 'VecListFour64' class
    5981             :   case MCK_VecListFour64:
    5982             :     if (Operand.isImplicitlyTypedVectorList<4>())
    5983             :       return MCTargetAsmParser::Match_Success;
    5984             :     break;
    5985             :   // 'TypedVectorList4_8b' class
    5986             :   case MCK_TypedVectorList4_8b:
    5987         118 :     if (Operand.isTypedVectorList<4, 8, 'b'>())
    5988             :       return MCTargetAsmParser::Match_Success;
    5989             :     break;
    5990             :   // 'TypedVectorList4_8h' class
    5991             :   case MCK_TypedVectorList4_8h:
    5992          98 :     if (Operand.isTypedVectorList<4, 8, 'h'>())
    5993             :       return MCTargetAsmParser::Match_Success;
    5994             :     break;
    5995             :   // 'TypedVectorList4_0b' class
    5996             :   case MCK_TypedVectorList4_0b:
    5997          26 :     if (Operand.isTypedVectorList<4, 0, 'b'>())
    5998             :       return MCTargetAsmParser::Match_Success;
    5999             :     break;
    6000             :   // 'TypedVectorList4_0d' class
    6001             :   case MCK_TypedVectorList4_0d:
    6002          36 :     if (Operand.isTypedVectorList<4, 0, 'd'>())
    6003             :       return MCTargetAsmParser::Match_Success;
    6004             :     break;
    6005             :   // 'TypedVectorList4_0h' class
    6006             :   case MCK_TypedVectorList4_0h:
    6007          20 :     if (Operand.isTypedVectorList<4, 0, 'h'>())
    6008             :       return MCTargetAsmParser::Match_Success;
    6009             :     break;
    6010             :   // 'TypedVectorList4_0s' class
    6011             :   case MCK_TypedVectorList4_0s:
    6012          18 :     if (Operand.isTypedVectorList<4, 0, 's'>())
    6013             :       return MCTargetAsmParser::Match_Success;
    6014             :     break;
    6015             :   // 'VecListOne128' class
    6016             :   case MCK_VecListOne128:
    6017             :     if (Operand.isImplicitlyTypedVectorList<1>())
    6018             :       return MCTargetAsmParser::Match_Success;
    6019             :     break;
    6020             :   // 'TypedVectorList1_16b' class
    6021             :   case MCK_TypedVectorList1_16b:
    6022         139 :     if (Operand.isTypedVectorList<1, 16, 'b'>())
    6023             :       return MCTargetAsmParser::Match_Success;
    6024             :     break;
    6025             :   // 'TypedVectorList1_1d' class
    6026             :   case MCK_TypedVectorList1_1d:
    6027         103 :     if (Operand.isTypedVectorList<1, 1, 'd'>())
    6028             :       return MCTargetAsmParser::Match_Success;
    6029             :     break;
    6030             :   // 'TypedVectorList1_2d' class
    6031             :   case MCK_TypedVectorList1_2d:
    6032          78 :     if (Operand.isTypedVectorList<1, 2, 'd'>())
    6033             :       return MCTargetAsmParser::Match_Success;
    6034             :     break;
    6035             :   // 'TypedVectorList1_2s' class
    6036             :   case MCK_TypedVectorList1_2s:
    6037          91 :     if (Operand.isTypedVectorList<1, 2, 's'>())
    6038             :       return MCTargetAsmParser::Match_Success;
    6039             :     break;
    6040             :   // 'TypedVectorList1_4h' class
    6041             :   case MCK_TypedVectorList1_4h:
    6042         111 :     if (Operand.isTypedVectorList<1, 4, 'h'>())
    6043             :       return MCTargetAsmParser::Match_Success;
    6044             :     break;
    6045             :   // 'TypedVectorList1_4s' class
    6046             :   case MCK_TypedVectorList1_4s:
    6047          66 :     if (Operand.isTypedVectorList<1, 4, 's'>())
    6048             :       return MCTargetAsmParser::Match_Success;
    6049             :     break;
    6050             :   // 'VecListOne64' class
    6051             :   case MCK_VecListOne64:
    6052             :     if (Operand.isImplicitlyTypedVectorList<1>())
    6053             :       return MCTargetAsmParser::Match_Success;
    6054             :     break;
    6055             :   // 'TypedVectorList1_8b' class
    6056             :   case MCK_TypedVectorList1_8b:
    6057          97 :     if (Operand.isTypedVectorList<1, 8, 'b'>())
    6058             :       return MCTargetAsmParser::Match_Success;
    6059             :     break;
    6060             :   // 'TypedVectorList1_8h' class
    6061             :   case MCK_TypedVectorList1_8h:
    6062          86 :     if (Operand.isTypedVectorList<1, 8, 'h'>())
    6063             :       return MCTargetAsmParser::Match_Success;
    6064             :     break;
    6065             :   // 'TypedVectorList1_0b' class
    6066             :   case MCK_TypedVectorList1_0b:
    6067          42 :     if (Operand.isTypedVectorList<1, 0, 'b'>())
    6068             :       return MCTargetAsmParser::Match_Success;
    6069             :     break;
    6070             :   // 'TypedVectorList1_0d' class
    6071             :   case MCK_TypedVectorList1_0d:
    6072          30 :     if (Operand.isTypedVectorList<1, 0, 'd'>())
    6073             :       return MCTargetAsmParser::Match_Success;
    6074             :     break;
    6075             :   // 'TypedVectorList1_0h' class
    6076             :   case MCK_TypedVectorList1_0h:
    6077          32 :     if (Operand.isTypedVectorList<1, 0, 'h'>())
    6078             :       return MCTargetAsmParser::Match_Success;
    6079             :     break;
    6080             :   // 'TypedVectorList1_0s' class
    6081             :   case MCK_TypedVectorList1_0s:
    6082          20 :     if (Operand.isTypedVectorList<1, 0, 's'>())
    6083             :       return MCTargetAsmParser::Match_Success;
    6084             :     break;
    6085             :   // 'VecListThree128' class
    6086             :   case MCK_VecListThree128:
    6087             :     if (Operand.isImplicitlyTypedVectorList<3>())
    6088             :       return MCTargetAsmParser::Match_Success;
    6089             :     break;
    6090             :   // 'TypedVectorList3_16b' class
    6091             :   case MCK_TypedVectorList3_16b:
    6092         160 :     if (Operand.isTypedVectorList<3, 16, 'b'>())
    6093             :       return MCTargetAsmParser::Match_Success;
    6094             :     break;
    6095             :   // 'TypedVectorList3_1d' class
    6096             :   case MCK_TypedVectorList3_1d:
    6097          64 :     if (Operand.isTypedVectorList<3, 1, 'd'>())
    6098             :       return MCTargetAsmParser::Match_Success;
    6099             :     break;
    6100             :   // 'TypedVectorList3_2d' class
    6101             :   case MCK_TypedVectorList3_2d:
    6102          89 :     if (Operand.isTypedVectorList<3, 2, 'd'>())
    6103             :       return MCTargetAsmParser::Match_Success;
    6104             :     break;
    6105             :   // 'TypedVectorList3_2s' class
    6106             :   case MCK_TypedVectorList3_2s:
    6107         156 :     if (Operand.isTypedVectorList<3, 2, 's'>())
    6108             :       return MCTargetAsmParser::Match_Success;
    6109             :     break;
    6110             :   // 'TypedVectorList3_4h' class
    6111             :   case MCK_TypedVectorList3_4h:
    6112         160 :     if (Operand.isTypedVectorList<3, 4, 'h'>())
    6113             :       return MCTargetAsmParser::Match_Success;
    6114             :     break;
    6115             :   // 'TypedVectorList3_4s' class
    6116             :   case MCK_TypedVectorList3_4s:
    6117         113 :     if (Operand.isTypedVectorList<3, 4, 's'>())
    6118             :       return MCTargetAsmParser::Match_Success;
    6119             :     break;
    6120             :   // 'VecListThree64' class
    6121             :   case MCK_VecListThree64:
    6122             :     if (Operand.isImplicitlyTypedVectorList<3>())
    6123             :       return MCTargetAsmParser::Match_Success;
    6124             :     break;
    6125             :   // 'TypedVectorList3_8b' class
    6126             :   case MCK_TypedVectorList3_8b:
    6127          99 :     if (Operand.isTypedVectorList<3, 8, 'b'>())
    6128             :       return MCTargetAsmParser::Match_Success;
    6129             :     break;
    6130             :   // 'TypedVectorList3_8h' class
    6131             :   case MCK_TypedVectorList3_8h:
    6132         117 :     if (Operand.isTypedVectorList<3, 8, 'h'>())
    6133             :       return MCTargetAsmParser::Match_Success;
    6134             :     break;
    6135             :   // 'TypedVectorList3_0b' class
    6136             :   case MCK_TypedVectorList3_0b:
    6137          18 :     if (Operand.isTypedVectorList<3, 0, 'b'>())
    6138             :       return MCTargetAsmParser::Match_Success;
    6139             :     break;
    6140             :   // 'TypedVectorList3_0d' class
    6141             :   case MCK_TypedVectorList3_0d:
    6142          20 :     if (Operand.isTypedVectorList<3, 0, 'd'>())
    6143             :       return MCTargetAsmParser::Match_Success;
    6144             :     break;
    6145             :   // 'TypedVectorList3_0h' class
    6146             :   case MCK_TypedVectorList3_0h:
    6147          30 :     if (Operand.isTypedVectorList<3, 0, 'h'>())
    6148             :       return MCTargetAsmParser::Match_Success;
    6149             :     break;
    6150             :   // 'TypedVectorList3_0s' class
    6151             :   case MCK_TypedVectorList3_0s:
    6152          38 :     if (Operand.isTypedVectorList<3, 0, 's'>())
    6153             :       return MCTargetAsmParser::Match_Success;
    6154             :     break;
    6155             :   // 'VecListTwo128' class
    6156             :   case MCK_VecListTwo128:
    6157             :     if (Operand.isImplicitlyTypedVectorList<2>())
    6158             :       return MCTargetAsmParser::Match_Success;
    6159             :     break;
    6160             :   // 'TypedVectorList2_16b' class
    6161             :   case MCK_TypedVectorList2_16b:
    6162         166 :     if (Operand.isTypedVectorList<2, 16, 'b'>())
    6163             :       return MCTargetAsmParser::Match_Success;
    6164             :     break;
    6165             :   // 'TypedVectorList2_1d' class
    6166             :   case MCK_TypedVectorList2_1d:
    6167          71 :     if (Operand.isTypedVectorList<2, 1, 'd'>())
    6168             :       return MCTargetAsmParser::Match_Success;
    6169             :     break;
    6170             :   // 'TypedVectorList2_2d' class
    6171             :   case MCK_TypedVectorList2_2d:
    6172          94 :     if (Operand.isTypedVectorList<2, 2, 'd'>())
    6173             :       return MCTargetAsmParser::Match_Success;
    6174             :     break;
    6175             :   // 'TypedVectorList2_2s' class
    6176             :   case MCK_TypedVectorList2_2s:
    6177         151 :     if (Operand.isTypedVectorList<2, 2, 's'>())
    6178             :       return MCTargetAsmParser::Match_Success;
    6179             :     break;
    6180             :   // 'TypedVectorList2_4h' class
    6181             :   case MCK_TypedVectorList2_4h:
    6182         155 :     if (Operand.isTypedVectorList<2, 4, 'h'>())
    6183             :       return MCTargetAsmParser::Match_Success;
    6184             :     break;
    6185             :   // 'TypedVectorList2_4s' class
    6186             :   case MCK_TypedVectorList2_4s:
    6187         106 :     if (Operand.isTypedVectorList<2, 4, 's'>())
    6188             :       return MCTargetAsmParser::Match_Success;
    6189             :     break;
    6190             :   // 'VecListTwo64' class
    6191             :   case MCK_VecListTwo64:
    6192             :     if (Operand.isImplicitlyTypedVectorList<2>())
    6193             :       return MCTargetAsmParser::Match_Success;
    6194             :     break;
    6195             :   // 'TypedVectorList2_8b' class
    6196             :   case MCK_TypedVectorList2_8b:
    6197         111 :     if (Operand.isTypedVectorList<2, 8, 'b'>())
    6198             :       return MCTargetAsmParser::Match_Success;
    6199             :     break;
    6200             :   // 'TypedVectorList2_8h' class
    6201             :   case MCK_TypedVectorList2_8h:
    6202         110 :     if (Operand.isTypedVectorList<2, 8, 'h'>())
    6203             :       return MCTargetAsmParser::Match_Success;
    6204             :     break;
    6205             :   // 'TypedVectorList2_0b' class
    6206             :   case MCK_TypedVectorList2_0b:
    6207          32 :     if (Operand.isTypedVectorList<2, 0, 'b'>())
    6208             :       return MCTargetAsmParser::Match_Success;
    6209             :     break;
    6210             :   // 'TypedVectorList2_0d' class
    6211             :   case MCK_TypedVectorList2_0d:
    6212          20 :     if (Operand.isTypedVectorList<2, 0, 'd'>())
    6213             :       return MCTargetAsmParser::Match_Success;
    6214             :     break;
    6215             :   // 'TypedVectorList2_0h' class
    6216             :   case MCK_TypedVectorList2_0h:
    6217          30 :     if (Operand.isTypedVectorList<2, 0, 'h'>())
    6218             :       return MCTargetAsmParser::Match_Success;
    6219             :     break;
    6220             :   // 'TypedVectorList2_0s' class
    6221             :   case MCK_TypedVectorList2_0s:
    6222          30 :     if (Operand.isTypedVectorList<2, 0, 's'>())
    6223             :       return MCTargetAsmParser::Match_Success;
    6224             :     break;
    6225             :   // 'VectorIndex1' class
    6226          13 :   case MCK_VectorIndex1:
    6227             :     if (Operand.isVectorIndex1())
    6228             :       return MCTargetAsmParser::Match_Success;
    6229             :     return AArch64AsmParser::Match_InvalidIndex1;
    6230             :   // 'VectorIndexB' class
    6231         203 :   case MCK_VectorIndexB:
    6232             :     if (Operand.isVectorIndexB())
    6233             :       return MCTargetAsmParser::Match_Success;
    6234             :     return AArch64AsmParser::Match_InvalidIndexB;
    6235             :   // 'VectorIndexD' class
    6236         283 :   case MCK_VectorIndexD:
    6237             :     if (Operand.isVectorIndexD())
    6238             :       return MCTargetAsmParser::Match_Success;
    6239             :     return AArch64AsmParser::Match_InvalidIndexD;
    6240             :   // 'VectorIndexH' class
    6241         377 :   case MCK_VectorIndexH:
    6242             :     if (Operand.isVectorIndexH())
    6243             :       return MCTargetAsmParser::Match_Success;
    6244             :     return AArch64AsmParser::Match_InvalidIndexH;
    6245             :   // 'VectorIndexS' class
    6246         470 :   case MCK_VectorIndexS:
    6247             :     if (Operand.isVectorIndexS())
    6248             :       return MCTargetAsmParser::Match_Success;
    6249             :     return AArch64AsmParser::Match_InvalidIndexS;
    6250             :   // 'VectorReg128' class
    6251       19772 :   case MCK_VectorReg128:
    6252             :     if (Operand.isNeonVectorReg())
    6253             :       return MCTargetAsmParser::Match_Success;
    6254             :     break;
    6255             :   // 'VectorReg64' class
    6256       11309 :   case MCK_VectorReg64:
    6257             :     if (Operand.isNeonVectorReg())
    6258             :       return MCTargetAsmParser::Match_Success;
    6259             :     break;
    6260             :   // 'VectorRegLo' class
    6261         237 :   case MCK_VectorRegLo:
    6262         237 :     if (Operand.isNeonVectorRegLo())
    6263             :       return MCTargetAsmParser::Match_Success;
    6264             :     break;
    6265             :   // 'WSeqPair' class
    6266          77 :   case MCK_WSeqPair:
    6267          77 :     if (Operand.isWSeqPair())
    6268             :       return MCTargetAsmParser::Match_Success;
    6269             :     break;
    6270             :   // 'XSeqPair' class
    6271          54 :   case MCK_XSeqPair:
    6272          54 :     if (Operand.isXSeqPair())
    6273             :       return MCTargetAsmParser::Match_Success;
    6274             :     break;
    6275             :   // 'SVEVectorQReg' class
    6276             :   case MCK_SVEVectorQReg:
    6277             :     if (Operand.isSVEVectorRegOfWidth<128, AArch64::ZPRRegClassID>())
    6278             :       return MCTargetAsmParser::Match_Success;
    6279             :     break;
    6280             :   // 'SVEVectorHReg' class
    6281             :   case MCK_SVEVectorHReg:
    6282             :     if (Operand.isSVEVectorRegOfWidth<16, AArch64::ZPRRegClassID>())
    6283             :       return MCTargetAsmParser::Match_Success;
    6284             :     break;
    6285             :   // 'SVEVectorSReg' class
    6286             :   case MCK_SVEVectorSReg:
    6287             :     if (Operand.isSVEVectorRegOfWidth<32, AArch64::ZPRRegClassID>())
    6288             :       return MCTargetAsmParser::Match_Success;
    6289             :     break;
    6290             :   // 'SVEVectorDReg' class
    6291             :   case MCK_SVEVectorDReg:
    6292             :     if (Operand.isSVEVectorRegOfWidth<64, AArch64::ZPRRegClassID>())
    6293             :       return MCTargetAsmParser::Match_Success;
    6294             :     break;
    6295             :   // 'SVEVectorBReg' class
    6296             :   case MCK_SVEVectorBReg:
    6297             :     if (Operand.isSVEVectorRegOfWidth<8, AArch64::ZPRRegClassID>())
    6298             :       return MCTargetAsmParser::Match_Success;
    6299             :     break;
    6300             :   // 'SVEVectorAnyReg' class
    6301             :   case MCK_SVEVectorAnyReg:
    6302             :     if (Operand.isSVEVectorRegOfWidth<-1, AArch64::ZPRRegClassID>())
    6303             :       return MCTargetAsmParser::Match_Success;
    6304             :     break;
    6305             :   // 'ComplexRotationEven' class
    6306             :   case MCK_ComplexRotationEven:
    6307             :     if (Operand.isComplexRotation<90, 0>())
    6308             :       return MCTargetAsmParser::Match_Success;
    6309             :     return AArch64AsmParser::Match_InvalidComplexRotationEven;
    6310             :   // 'ComplexRotationOdd' class
    6311             :   case MCK_ComplexRotationOdd:
    6312             :     if (Operand.isComplexRotation<180, 90>())
    6313             :       return MCTargetAsmParser::Match_Success;
    6314             :     return AArch64AsmParser::Match_InvalidComplexRotationOdd;
    6315             :   // 'SVELogicalImm8' class
    6316           9 :   case MCK_SVELogicalImm8:
    6317           9 :     if (Operand.isLogicalImm<int8_t>())
    6318             :       return MCTargetAsmParser::Match_Success;
    6319           4 :     return AArch64AsmParser::Match_LogicalSecondSource;
    6320             :   // 'SVELogicalImm16' class
    6321           9 :   case MCK_SVELogicalImm16:
    6322           9 :     if (Operand.isLogicalImm<int16_t>())
    6323             :       return MCTargetAsmParser::Match_Success;
    6324           4 :     return AArch64AsmParser::Match_LogicalSecondSource;
    6325             :   // 'SVELogicalImm32' class
    6326           9 :   case MCK_SVELogicalImm32:
    6327           9 :     if (Operand.isLogicalImm<int32_t>())
    6328             :       return MCTargetAsmParser::Match_Success;
    6329           4 :     return AArch64AsmParser::Match_LogicalSecondSource;
    6330             :   // 'SVELogicalImm8Not' class
    6331           5 :   case MCK_SVELogicalImm8Not:
    6332           5 :     if (Operand.isLogicalImm<int8_t>())
    6333             :       return MCTargetAsmParser::Match_Success;
    6334           0 :     return AArch64AsmParser::Match_LogicalSecondSource;
    6335             :   // 'SVELogicalImm16Not' class
    6336           5 :   case MCK_SVELogicalImm16Not:
    6337           5 :     if (Operand.isLogicalImm<int16_t>())
    6338             :       return MCTargetAsmParser::Match_Success;
    6339           0 :     return AArch64AsmParser::Match_LogicalSecondSource;
    6340             :   // 'SVELogicalImm32Not' class
    6341           5 :   case MCK_SVELogicalImm32Not:
    6342           5 :     if (Operand.isLogicalImm<int32_t>())
    6343             :       return MCTargetAsmParser::Match_Success;
    6344           0 :     return AArch64AsmParser::Match_LogicalSecondSource;
    6345             :   // 'MOVZ32_lsl0MovAlias' class
    6346             :   case MCK_MOVZ32_lsl0MovAlias:
    6347           5 :     if (Operand.isMOVZMovAlias<32, 0>())
    6348             :       return MCTargetAsmParser::Match_Success;
    6349             :     break;
    6350             :   // 'MOVZ32_lsl16MovAlias' class
    6351             :   case MCK_MOVZ32_lsl16MovAlias:
    6352           5 :     if (Operand.isMOVZMovAlias<32, 16>())
    6353             :       return MCTargetAsmParser::Match_Success;
    6354             :     break;
    6355             :   // 'MOVZ64_lsl0MovAlias' class
    6356             :   case MCK_MOVZ64_lsl0MovAlias:
    6357          11 :     if (Operand.isMOVZMovAlias<64, 0>())
    6358             :       return MCTargetAsmParser::Match_Success;
    6359             :     break;
    6360             :   // 'MOVZ64_lsl16MovAlias' class
    6361             :   case MCK_MOVZ64_lsl16MovAlias:
    6362           3 :     if (Operand.isMOVZMovAlias<64, 16>())
    6363             :       return MCTargetAsmParser::Match_Success;
    6364             :     break;
    6365             :   // 'MOVZ64_lsl32MovAlias' class
    6366             :   case MCK_MOVZ64_lsl32MovAlias:
    6367           3 :     if (Operand.isMOVZMovAlias<64, 32>())
    6368             :       return MCTargetAsmParser::Match_Success;
    6369             :     break;
    6370             :   // 'MOVZ64_lsl48MovAlias' class
    6371             :   case MCK_MOVZ64_lsl48MovAlias:
    6372           2 :     if (Operand.isMOVZMovAlias<64, 48>())
    6373             :       return MCTargetAsmParser::Match_Success;
    6374             :     break;
    6375             :   // 'MOVN32_lsl0MovAlias' class
    6376          13 :   case MCK_MOVN32_lsl0MovAlias:
    6377          13 :     if (Operand.isMOVNMovAlias<32, 0>())
    6378             :       return MCTargetAsmParser::Match_Success;
    6379             :     break;
    6380             :   // 'MOVN32_lsl16MovAlias' class
    6381           9 :   case MCK_MOVN32_lsl16MovAlias:
    6382           9 :     if (Operand.isMOVNMovAlias<32, 16>())
    6383             :       return MCTargetAsmParser::Match_Success;
    6384             :     break;
    6385             :   // 'MOVN64_lsl0MovAlias' class
    6386          13 :   case MCK_MOVN64_lsl0MovAlias:
    6387          13 :     if (Operand.isMOVNMovAlias<64, 0>())
    6388             :       return MCTargetAsmParser::Match_Success;
    6389             :     break;
    6390             :   // 'MOVN64_lsl16MovAlias' class
    6391          12 :   case MCK_MOVN64_lsl16MovAlias:
    6392          12 :     if (Operand.isMOVNMovAlias<64, 16>())
    6393             :       return MCTargetAsmParser::Match_Success;
    6394             :     break;
    6395             :   // 'MOVN64_lsl32MovAlias' class
    6396          12 :   case MCK_MOVN64_lsl32MovAlias:
    6397          12 :     if (Operand.isMOVNMovAlias<64, 32>())
    6398             :       return MCTargetAsmParser::Match_Success;
    6399             :     break;
    6400             :   // 'MOVN64_lsl48MovAlias' class
    6401          12 :   case MCK_MOVN64_lsl48MovAlias:
    6402          12 :     if (Operand.isMOVNMovAlias<64, 48>())
    6403             :       return MCTargetAsmParser::Match_Success;
    6404             :     break;
    6405             :   } // end switch (Kind)
    6406             : 
    6407      260619 :   if (Operand.isReg()) {
    6408             :     MatchClassKind OpKind;
    6409             :     switch (Operand.getReg()) {
    6410             :     default: OpKind = InvalidMatchClass; break;
    6411             :     case AArch64::W0: OpKind = MCK_GPR32common; break;
    6412             :     case AArch64::W1: OpKind = MCK_GPR32common; break;
    6413             :     case AArch64::W2: OpKind = MCK_GPR32common; break;
    6414             :     case AArch64::W3: OpKind = MCK_GPR32common; break;
    6415             :     case AArch64::W4: OpKind = MCK_GPR32common; break;
    6416             :     case AArch64::W5: OpKind = MCK_GPR32common; break;
    6417             :     case AArch64::W6: OpKind = MCK_GPR32common; break;
    6418             :     case AArch64::W7: OpKind = MCK_GPR32common; break;
    6419             :     case AArch64::W8: OpKind = MCK_GPR32common; break;
    6420             :     case AArch64::W9: OpKind = MCK_GPR32common; break;
    6421             :     case AArch64::W10: OpKind = MCK_GPR32common; break;
    6422             :     case AArch64::W11: OpKind = MCK_GPR32common; break;
    6423             :     case AArch64::W12: OpKind = MCK_GPR32common; break;
    6424             :     case AArch64::W13: OpKind = MCK_GPR32common; break;
    6425             :     case AArch64::W14: OpKind = MCK_GPR32common; break;
    6426             :     case AArch64::W15: OpKind = MCK_GPR32common; break;
    6427             :     case AArch64::W16: OpKind = MCK_GPR32common; break;
    6428             :     case AArch64::W17: OpKind = MCK_GPR32common; break;
    6429             :     case AArch64::W18: OpKind = MCK_GPR32common; break;
    6430             :     case AArch64::W19: OpKind = MCK_GPR32common; break;
    6431             :     case AArch64::W20: OpKind = MCK_GPR32common; break;
    6432             :     case AArch64::W21: OpKind = MCK_GPR32common; break;
    6433             :     case AArch64::W22: OpKind = MCK_GPR32common; break;
    6434             :     case AArch64::W23: OpKind = MCK_GPR32common; break;
    6435             :     case AArch64::W24: OpKind = MCK_GPR32common; break;
    6436             :     case AArch64::W25: OpKind = MCK_GPR32common; break;
    6437             :     case AArch64::W26: OpKind = MCK_GPR32common; break;
    6438             :     case AArch64::W27: OpKind = MCK_GPR32common; break;
    6439             :     case AArch64::W28: OpKind = MCK_GPR32common; break;
    6440             :     case AArch64::W29: OpKind = MCK_GPR32common; break;
    6441             :     case AArch64::W30: OpKind = MCK_GPR32common; break;
    6442             :     case AArch64::WSP: OpKind = MCK_GPR32sponly; break;
    6443             :     case AArch64::WZR: OpKind = MCK_GPR32; break;
    6444             :     case AArch64::X0: OpKind = MCK_tcGPR64; break;
    6445             :     case AArch64::X1: OpKind = MCK_tcGPR64; break;
    6446             :     case AArch64::X2: OpKind = MCK_tcGPR64; break;
    6447             :     case AArch64::X3: OpKind = MCK_tcGPR64; break;
    6448             :     case AArch64::X4: OpKind = MCK_tcGPR64; break;
    6449             :     case AArch64::X5: OpKind = MCK_tcGPR64; break;
    6450             :     case AArch64::X6: OpKind = MCK_tcGPR64; break;
    6451             :     case AArch64::X7: OpKind = MCK_tcGPR64; break;
    6452             :     case AArch64::X8: OpKind = MCK_tcGPR64; break;
    6453             :     case AArch64::X9: OpKind = MCK_tcGPR64; break;
    6454             :     case AArch64::X10: OpKind = MCK_tcGPR64; break;
    6455             :     case AArch64::X11: OpKind = MCK_tcGPR64; break;
    6456             :     case AArch64::X12: OpKind = MCK_tcGPR64; break;
    6457             :     case AArch64::X13: OpKind = MCK_tcGPR64; break;
    6458             :     case AArch64::X14: OpKind = MCK_tcGPR64; break;
    6459             :     case AArch64::X15: OpKind = MCK_tcGPR64; break;
    6460             :     case AArch64::X16: OpKind = MCK_tcGPR64; break;
    6461             :     case AArch64::X17: OpKind = MCK_tcGPR64; break;
    6462             :     case AArch64::X18: OpKind = MCK_tcGPR64; break;
    6463             :     case AArch64::X19: OpKind = MCK_GPR64common; break;
    6464             :     case AArch64::X20: OpKind = MCK_GPR64common; break;
    6465             :     case AArch64::X21: OpKind = MCK_GPR64common; break;
    6466             :     case AArch64::X22: OpKind = MCK_GPR64common; break;
    6467             :     case AArch64::X23: OpKind = MCK_GPR64common; break;
    6468             :     case AArch64::X24: OpKind = MCK_GPR64common; break;
    6469             :     case AArch64::X25: OpKind = MCK_GPR64common; break;
    6470             :     case AArch64::X26: OpKind = MCK_GPR64common; break;
    6471             :     case AArch64::X27: OpKind = MCK_GPR64common; break;
    6472             :     case AArch64::X28: OpKind = MCK_GPR64common; break;
    6473             :     case AArch64::FP: OpKind = MCK_GPR64common; break;
    6474             :     case AArch64::LR: OpKind = MCK_GPR64common; break;
    6475             :     case AArch64::SP: OpKind = MCK_GPR64sponly; break;
    6476             :     case AArch64::XZR: OpKind = MCK_GPR64; break;
    6477             :     case AArch64::NZCV: OpKind = MCK_CCR; break;
    6478             :     case AArch64::B0: OpKind = MCK_FPR8; break;
    6479             :     case AArch64::B1: OpKind = MCK_FPR8; break;
    6480             :     case AArch64::B2: OpKind = MCK_FPR8; break;
    6481             :     case AArch64::B3: OpKind = MCK_FPR8; break;
    6482             :     case AArch64::B4: OpKind = MCK_FPR8; break;
    6483             :     case AArch64::B5: OpKind = MCK_FPR8; break;
    6484             :     case AArch64::B6: OpKind = MCK_FPR8; break;
    6485             :     case AArch64::B7: OpKind = MCK_FPR8; break;
    6486             :     case AArch64::B8: OpKind = MCK_FPR8; break;
    6487             :     case AArch64::B9: OpKind = MCK_FPR8; break;
    6488             :     case AArch64::B10: OpKind = MCK_FPR8; break;
    6489             :     case AArch64::B11: OpKind = MCK_FPR8; break;
    6490             :     case AArch64::B12: OpKind = MCK_FPR8; break;
    6491             :     case AArch64::B13: OpKind = MCK_FPR8; break;
    6492             :     case AArch64::B14: OpKind = MCK_FPR8; break;
    6493             :     case AArch64::B15: OpKind = MCK_FPR8; break;
    6494             :     case AArch64::B16: OpKind = MCK_FPR8; break;
    6495             :     case AArch64::B17: OpKind = MCK_FPR8; break;
    6496             :     case AArch64::B18: OpKind = MCK_FPR8; break;
    6497             :     case AArch64::B19: OpKind = MCK_FPR8; break;
    6498             :     case AArch64::B20: OpKind = MCK_FPR8; break;
    6499             :     case AArch64::B21: OpKind = MCK_FPR8; break;
    6500             :     case AArch64::B22: OpKind = MCK_FPR8; break;
    6501             :     case AArch64::B23: OpKind = MCK_FPR8; break;
    6502             :     case AArch64::B24: OpKind = MCK_FPR8; break;
    6503             :     case AArch64::B25: OpKind = MCK_FPR8; break;
    6504             :     case AArch64::B26: OpKind = MCK_FPR8; break;
    6505             :     case AArch64::B27: OpKind = MCK_FPR8; break;
    6506             :     case AArch64::B28: OpKind = MCK_FPR8; break;
    6507             :     case AArch64::B29: OpKind = MCK_FPR8; break;
    6508             :     case AArch64::B30: OpKind = MCK_FPR8; break;
    6509             :     case AArch64::B31: OpKind = MCK_FPR8; break;
    6510             :     case AArch64::H0: OpKind = MCK_FPR16; break;
    6511             :     case AArch64::H1: OpKind = MCK_FPR16; break;
    6512             :     case AArch64::H2: OpKind = MCK_FPR16; break;
    6513             :     case AArch64::H3: OpKind = MCK_FPR16; break;
    6514             :     case AArch64::H4: OpKind = MCK_FPR16; break;
    6515             :     case AArch64::H5: OpKind = MCK_FPR16; break;
    6516             :     case AArch64::H6: OpKind = MCK_FPR16; break;
    6517             :     case AArch64::H7: OpKind = MCK_FPR16; break;
    6518             :     case AArch64::H8: OpKind = MCK_FPR16; break;
    6519             :     case AArch64::H9: OpKind = MCK_FPR16; break;
    6520             :     case AArch64::H10: OpKind = MCK_FPR16; break;
    6521             :     case AArch64::H11: OpKind = MCK_FPR16; break;
    6522             :     case AArch64::H12: OpKind = MCK_FPR16; break;
    6523             :     case AArch64::H13: OpKind = MCK_FPR16; break;
    6524             :     case AArch64::H14: OpKind = MCK_FPR16; break;
    6525             :     case AArch64::H15: OpKind = MCK_FPR16; break;
    6526             :     case AArch64::H16: OpKind = MCK_FPR16; break;
    6527             :     case AArch64::H17: OpKind = MCK_FPR16; break;
    6528             :     case AArch64::H18: OpKind = MCK_FPR16; break;
    6529             :     case AArch64::H19: OpKind = MCK_FPR16; break;
    6530             :     case AArch64::H20: OpKind = MCK_FPR16; break;
    6531             :     case AArch64::H21: OpKind = MCK_FPR16; break;
    6532             :     case AArch64::H22: OpKind = MCK_FPR16; break;
    6533             :     case AArch64::H23: OpKind = MCK_FPR16; break;
    6534             :     case AArch64::H24: OpKind = MCK_FPR16; break;
    6535             :     case AArch64::H25: OpKind = MCK_FPR16; break;
    6536             :     case AArch64::H26: OpKind = MCK_FPR16; break;
    6537             :     case AArch64::H27: OpKind = MCK_FPR16; break;
    6538             :     case AArch64::H28: OpKind = MCK_FPR16; break;
    6539             :     case AArch64::H29: OpKind = MCK_FPR16; break;
    6540             :     case AArch64::H30: OpKind = MCK_FPR16; break;
    6541             :     case AArch64::H31: OpKind = MCK_FPR16; break;
    6542             :     case AArch64::S0: OpKind = MCK_FPR32; break;
    6543             :     case AArch64::S1: OpKind = MCK_FPR32; break;
    6544             :     case AArch64::S2: OpKind = MCK_FPR32; break;
    6545             :     case AArch64::S3: OpKind = MCK_FPR32; break;
    6546             :     case AArch64::S4: OpKind = MCK_FPR32; break;
    6547             :     case AArch64::S5: OpKind = MCK_FPR32; break;
    6548             :     case AArch64::S6: OpKind = MCK_FPR32; break;
    6549             :     case AArch64::S7: OpKind = MCK_FPR32; break;
    6550             :     case AArch64::S8: OpKind = MCK_FPR32; break;
    6551             :     case AArch64::S9: OpKind = MCK_FPR32; break;
    6552             :     case AArch64::S10: OpKind = MCK_FPR32; break;
    6553             :     case AArch64::S11: OpKind = MCK_FPR32; break;
    6554             :     case AArch64::S12: OpKind = MCK_FPR32; break;
    6555             :     case AArch64::S13: OpKind = MCK_FPR32; break;
    6556             :     case AArch64::S14: OpKind = MCK_FPR32; break;
    6557             :     case AArch64::S15: OpKind = MCK_FPR32; break;
    6558             :     case AArch64::S16: OpKind = MCK_FPR32; break;
    6559             :     case AArch64::S17: OpKind = MCK_FPR32; break;
    6560             :     case AArch64::S18: OpKind = MCK_FPR32; break;
    6561             :     case AArch64::S19: OpKind = MCK_FPR32; break;
    6562             :     case AArch64::S20: OpKind = MCK_FPR32; break;
    6563             :     case AArch64::S21: OpKind = MCK_FPR32; break;
    6564             :     case AArch64::S22: OpKind = MCK_FPR32; break;
    6565             :     case AArch64::S23: OpKind = MCK_FPR32; break;
    6566             :     case AArch64::S24: OpKind = MCK_FPR32; break;
    6567             :     case AArch64::S25: OpKind = MCK_FPR32; break;
    6568             :     case AArch64::S26: OpKind = MCK_FPR32; break;
    6569             :     case AArch64::S27: OpKind = MCK_FPR32; break;
    6570             :     case AArch64::S28: OpKind = MCK_FPR32; break;
    6571             :     case AArch64::S29: OpKind = MCK_FPR32; break;
    6572             :     case AArch64::S30: OpKind = MCK_FPR32; break;
    6573             :     case AArch64::S31: OpKind = MCK_FPR32; break;
    6574             :     case AArch64::D0: OpKind = MCK_FPR64; break;
    6575             :     case AArch64::D1: OpKind = MCK_FPR64; break;
    6576             :     case AArch64::D2: OpKind = MCK_FPR64; break;
    6577             :     case AArch64::D3: OpKind = MCK_FPR64; break;
    6578             :     case AArch64::D4: OpKind = MCK_FPR64; break;
    6579             :     case AArch64::D5: OpKind = MCK_FPR64; break;
    6580             :     case AArch64::D6: OpKind = MCK_FPR64; break;
    6581             :     case AArch64::D7: OpKind = MCK_FPR64; break;
    6582             :     case AArch64::D8: OpKind = MCK_FPR64; break;
    6583             :     case AArch64::D9: OpKind = MCK_FPR64; break;
    6584             :     case AArch64::D10: OpKind = MCK_FPR64; break;
    6585             :     case AArch64::D11: OpKind = MCK_FPR64; break;
    6586             :     case AArch64::D12: OpKind = MCK_FPR64; break;
    6587             :     case AArch64::D13: OpKind = MCK_FPR64; break;
    6588             :     case AArch64::D14: OpKind = MCK_FPR64; break;
    6589             :     case AArch64::D15: OpKind = MCK_FPR64; break;
    6590             :     case AArch64::D16: OpKind = MCK_FPR64; break;
    6591             :     case AArch64::D17: OpKind = MCK_FPR64; break;
    6592             :     case AArch64::D18: OpKind = MCK_FPR64; break;
    6593             :     case AArch64::D19: OpKind = MCK_FPR64; break;
    6594             :     case AArch64::D20: OpKind = MCK_FPR64; break;
    6595             :     case AArch64::D21: OpKind = MCK_FPR64; break;
    6596             :     case AArch64::D22: OpKind = MCK_FPR64; break;
    6597             :     case AArch64::D23: OpKind = MCK_FPR64; break;
    6598             :     case AArch64::D24: OpKind = MCK_FPR64; break;
    6599             :     case AArch64::D25: OpKind = MCK_FPR64; break;
    6600             :     case AArch64::D26: OpKind = MCK_FPR64; break;
    6601             :     case AArch64::D27: OpKind = MCK_FPR64; break;
    6602             :     case AArch64::D28: OpKind = MCK_FPR64; break;
    6603             :     case AArch64::D29: OpKind = MCK_FPR64; break;
    6604             :     case AArch64::D30: OpKind = MCK_FPR64; break;
    6605             :     case AArch64::D31: OpKind = MCK_FPR64; break;
    6606             :     case AArch64::Q0: OpKind = MCK_FPR128_lo; break;
    6607             :     case AArch64::Q1: OpKind = MCK_FPR128_lo; break;
    6608             :     case AArch64::Q2: OpKind = MCK_FPR128_lo; break;
    6609             :     case AArch64::Q3: OpKind = MCK_FPR128_lo; break;
    6610             :     case AArch64::Q4: OpKind = MCK_FPR128_lo; break;
    6611             :     case AArch64::Q5: OpKind = MCK_FPR128_lo; break;
    6612             :     case AArch64::Q6: OpKind = MCK_FPR128_lo; break;
    6613             :     case AArch64::Q7: OpKind = MCK_FPR128_lo; break;
    6614             :     case AArch64::Q8: OpKind = MCK_FPR128_lo; break;
    6615             :     case AArch64::Q9: OpKind = MCK_FPR128_lo; break;
    6616             :     case AArch64::Q10: OpKind = MCK_FPR128_lo; break;
    6617             :     case AArch64::Q11: OpKind = MCK_FPR128_lo; break;
    6618             :     case AArch64::Q12: OpKind = MCK_FPR128_lo; break;
    6619             :     case AArch64::Q13: OpKind = MCK_FPR128_lo; break;
    6620             :     case AArch64::Q14: OpKind = MCK_FPR128_lo; break;
    6621             :     case AArch64::Q15: OpKind = MCK_FPR128_lo; break;
    6622             :     case AArch64::Q16: OpKind = MCK_FPR128; break;
    6623             :     case AArch64::Q17: OpKind = MCK_FPR128; break;
    6624             :     case AArch64::Q18: OpKind = MCK_FPR128; break;
    6625             :     case AArch64::Q19: OpKind = MCK_FPR128; break;
    6626             :     case AArch64::Q20: OpKind = MCK_FPR128; break;
    6627             :     case AArch64::Q21: OpKind = MCK_FPR128; break;
    6628             :     case AArch64::Q22: OpKind = MCK_FPR128; break;
    6629             :     case AArch64::Q23: OpKind = MCK_FPR128; break;
    6630             :     case AArch64::Q24: OpKind = MCK_FPR128; break;
    6631             :     case AArch64::Q25: OpKind = MCK_FPR128; break;
    6632             :     case AArch64::Q26: OpKind = MCK_FPR128; break;
    6633             :     case AArch64::Q27: OpKind = MCK_FPR128; break;
    6634             :     case AArch64::Q28: OpKind = MCK_FPR128; break;
    6635             :     case AArch64::Q29: OpKind = MCK_FPR128; break;
    6636             :     case AArch64::Q30: OpKind = MCK_FPR128; break;
    6637             :     case AArch64::Q31: OpKind = MCK_FPR128; break;
    6638             :     case AArch64::P0: OpKind = MCK_PPR_3b; break;
    6639             :     case AArch64::P1: OpKind = MCK_PPR_3b; break;
    6640             :     case AArch64::P2: OpKind = MCK_PPR_3b; break;
    6641             :     case AArch64::P3: OpKind = MCK_PPR_3b; break;
    6642             :     case AArch64::P4: OpKind = MCK_PPR_3b; break;
    6643             :     case AArch64::P5: OpKind = MCK_PPR_3b; break;
    6644             :     case AArch64::P6: OpKind = MCK_PPR_3b; break;
    6645             :     case AArch64::P7: OpKind = MCK_PPR_3b; break;
    6646             :     case AArch64::P8: OpKind = MCK_PPR; break;
    6647             :     case AArch64::P9: OpKind = MCK_PPR; break;
    6648             :     case AArch64::P10: OpKind = MCK_PPR; break;
    6649             :     case AArch64::P11: OpKind = MCK_PPR; break;
    6650             :     case AArch64::P12: OpKind = MCK_PPR; break;
    6651             :     case AArch64::P13: OpKind = MCK_PPR; break;
    6652             :     case AArch64::P14: OpKind = MCK_PPR; break;
    6653             :     case AArch64::P15: OpKind = MCK_PPR; break;
    6654             :     case AArch64::Z0: OpKind = MCK_Reg20; break;
    6655             :     case AArch64::Z1: OpKind = MCK_Reg20; break;
    6656             :     case AArch64::Z2: OpKind = MCK_Reg20; break;
    6657             :     case AArch64::Z3: OpKind = MCK_Reg20; break;
    6658             :     case AArch64::Z4: OpKind = MCK_Reg20; break;
    6659             :     case AArch64::Z5: OpKind = MCK_Reg20; break;
    6660             :     case AArch64::Z6: OpKind = MCK_Reg20; break;
    6661             :     case AArch64::Z7: OpKind = MCK_Reg20; break;
    6662             :     case AArch64::Z8: OpKind = MCK_Reg20; break;
    6663             :     case AArch64::Z9: OpKind = MCK_Reg20; break;
    6664             :     case AArch64::Z10: OpKind = MCK_Reg20; break;
    6665             :     case AArch64::Z11: OpKind = MCK_Reg20; break;
    6666             :     case AArch64::Z12: OpKind = MCK_Reg20; break;
    6667             :     case AArch64::Z13: OpKind = MCK_Reg20; break;
    6668             :     case AArch64::Z14: OpKind = MCK_Reg20; break;
    6669             :     case AArch64::Z15: OpKind = MCK_Reg20; break;
    6670             :     case AArch64::Z16: OpKind = MCK_ZPR; break;
    6671             :     case AArch64::Z17: OpKind = MCK_ZPR; break;
    6672             :     case AArch64::Z18: OpKind = MCK_ZPR; break;
    6673             :     case AArch64::Z19: OpKind = MCK_ZPR; break;
    6674             :     case AArch64::Z20: OpKind = MCK_ZPR; break;
    6675             :     case AArch64::Z21: OpKind = MCK_ZPR; break;
    6676             :     case AArch64::Z22: OpKind = MCK_ZPR; break;
    6677             :     case AArch64::Z23: OpKind = MCK_ZPR; break;
    6678             :     case AArch64::Z24: OpKind = MCK_ZPR; break;
    6679             :     case AArch64::Z25: OpKind = MCK_ZPR; break;
    6680             :     case AArch64::Z26: OpKind = MCK_ZPR; break;
    6681             :     case AArch64::Z27: OpKind = MCK_ZPR; break;
    6682             :     case AArch64::Z28: OpKind = MCK_ZPR; break;
    6683             :     case AArch64::Z29: OpKind = MCK_ZPR; break;
    6684             :     case AArch64::Z30: OpKind = MCK_ZPR; break;
    6685             :     case AArch64::Z31: OpKind = MCK_ZPR; break;
    6686             :     case AArch64::D0_D1: OpKind = MCK_DD; break;
    6687             :     case AArch64::D1_D2: OpKind = MCK_DD; break;
    6688             :     case AArch64::D2_D3: OpKind = MCK_DD; break;
    6689             :     case AArch64::D3_D4: OpKind = MCK_DD; break;
    6690             :     case AArch64::D4_D5: OpKind = MCK_DD; break;
    6691             :     case AArch64::D5_D6: OpKind = MCK_DD; break;
    6692             :     case AArch64::D6_D7: OpKind = MCK_DD; break;
    6693             :     case AArch64::D7_D8: OpKind = MCK_DD; break;
    6694             :     case AArch64::D8_D9: OpKind = MCK_DD; break;
    6695             :     case AArch64::D9_D10: OpKind = MCK_DD; break;
    6696             :     case AArch64::D10_D11: OpKind = MCK_DD; break;
    6697             :     case AArch64::D11_D12: OpKind = MCK_DD; break;
    6698             :     case AArch64::D12_D13: OpKind = MCK_DD; break;
    6699             :     case AArch64::D13_D14: OpKind = MCK_DD; break;
    6700             :     case AArch64::D14_D15: OpKind = MCK_DD; break;
    6701             :     case AArch64::D15_D16: OpKind = MCK_DD; break;
    6702             :     case AArch64::D16_D17: OpKind = MCK_DD; break;
    6703             :     case AArch64::D17_D18: OpKind = MCK_DD; break;
    6704             :     case AArch64::D18_D19: OpKind = MCK_DD; break;
    6705             :     case AArch64::D19_D20: OpKind = MCK_DD; break;
    6706             :     case AArch64::D20_D21: OpKind = MCK_DD; break;
    6707             :     case AArch64::D21_D22: OpKind = MCK_DD; break;
    6708             :     case AArch64::D22_D23: OpKind = MCK_DD; break;
    6709             :     case AArch64::D23_D24: OpKind = MCK_DD; break;
    6710             :     case AArch64::D24_D25: OpKind = MCK_DD; break;
    6711             :     case AArch64::D25_D26: OpKind = MCK_DD; break;
    6712             :     case AArch64::D26_D27: OpKind = MCK_DD; break;
    6713             :     case AArch64::D27_D28: OpKind = MCK_DD; break;
    6714             :     case AArch64::D28_D29: OpKind = MCK_DD; break;
    6715             :     case AArch64::D29_D30: OpKind = MCK_DD; break;
    6716             :     case AArch64::D30_D31: OpKind = MCK_DD; break;
    6717             :     case AArch64::D31_D0: OpKind = MCK_DD; break;
    6718             :     case AArch64::D0_D1_D2_D3: OpKind = MCK_DDDD; break;
    6719             :     case AArch64::D1_D2_D3_D4: OpKind = MCK_DDDD; break;
    6720             :     case AArch64::D2_D3_D4_D5: OpKind = MCK_DDDD; break;
    6721             :     case AArch64::D3_D4_D5_D6: OpKind = MCK_DDDD; break;
    6722             :     case AArch64::D4_D5_D6_D7: OpKind = MCK_DDDD; break;
    6723             :     case AArch64::D5_D6_D7_D8: OpKind = MCK_DDDD; break;
    6724             :     case AArch64::D6_D7_D8_D9: OpKind = MCK_DDDD; break;
    6725             :     case AArch64::D7_D8_D9_D10: OpKind = MCK_DDDD; break;
    6726             :     case AArch64::D8_D9_D10_D11: OpKind = MCK_DDDD; break;
    6727             :     case AArch64::D9_D10_D11_D12: OpKind = MCK_DDDD; break;
    6728             :     case AArch64::D10_D11_D12_D13: OpKind = MCK_DDDD; break;
    6729             :     case AArch64::D11_D12_D13_D14: OpKind = MCK_DDDD; break;
    6730             :     case AArch64::D12_D13_D14_D15: OpKind = MCK_DDDD; break;
    6731             :     case AArch64::D13_D14_D15_D16: OpKind = MCK_DDDD; break;
    6732             :     case AArch64::D14_D15_D16_D17: OpKind = MCK_DDDD; break;
    6733             :     case AArch64::D15_D16_D17_D18: OpKind = MCK_DDDD; break;
    6734             :     case AArch64::D16_D17_D18_D19: OpKind = MCK_DDDD; break;
    6735             :     case AArch64::D17_D18_D19_D20: OpKind = MCK_DDDD; break;
    6736             :     case AArch64::D18_D19_D20_D21: OpKind = MCK_DDDD; break;
    6737             :     case AArch64::D19_D20_D21_D22: OpKind = MCK_DDDD; break;
    6738             :     case AArch64::D20_D21_D22_D23: OpKind = MCK_DDDD; break;
    6739             :     case AArch64::D21_D22_D23_D24: OpKind = MCK_DDDD; break;
    6740             :     case AArch64::D22_D23_D24_D25: OpKind = MCK_DDDD; break;
    6741             :     case AArch64::D23_D24_D25_D26: OpKind = MCK_DDDD; break;
    6742             :     case AArch64::D24_D25_D26_D27: OpKind = MCK_DDDD; break;
    6743             :     case AArch64::D25_D26_D27_D28: OpKind = MCK_DDDD; break;
    6744             :     case AArch64::D26_D27_D28_D29: OpKind = MCK_DDDD; break;
    6745             :     case AArch64::D27_D28_D29_D30: OpKind = MCK_DDDD; break;
    6746             :     case AArch64::D28_D29_D30_D31: OpKind = MCK_DDDD; break;
    6747             :     case AArch64::D29_D30_D31_D0: OpKind = MCK_DDDD; break;
    6748             :     case AArch64::D30_D31_D0_D1: OpKind = MCK_DDDD; break;
    6749             :     case AArch64::D31_D0_D1_D2: OpKind = MCK_DDDD; break;
    6750             :     case AArch64::D0_D1_D2: OpKind = MCK_DDD; break;
    6751             :     case AArch64::D1_D2_D3: OpKind = MCK_DDD; break;
    6752             :     case AArch64::D2_D3_D4: OpKind = MCK_DDD; break;
    6753             :     case AArch64::D3_D4_D5: OpKind = MCK_DDD; break;
    6754             :     case AArch64::D4_D5_D6: OpKind = MCK_DDD; break;
    6755             :     case AArch64::D5_D6_D7: OpKind = MCK_DDD; break;
    6756             :     case AArch64::D6_D7_D8: OpKind = MCK_DDD; break;
    6757             :     case AArch64::D7_D8_D9: OpKind = MCK_DDD; break;
    6758             :     case AArch64::D8_D9_D10: OpKind = MCK_DDD; break;
    6759             :     case AArch64::D9_D10_D11: OpKind = MCK_DDD; break;
    6760             :     case AArch64::D10_D11_D12: OpKind = MCK_DDD; break;
    6761             :     case AArch64::D11_D12_D13: OpKind = MCK_DDD; break;
    6762             :     case AArch64::D12_D13_D14: OpKind = MCK_DDD; break;
    6763             :     case AArch64::D13_D14_D15: OpKind = MCK_DDD; break;
    6764             :     case AArch64::D14_D15_D16: OpKind = MCK_DDD; break;
    6765             :     case AArch64::D15_D16_D17: OpKind = MCK_DDD; break;
    6766             :     case AArch64::D16_D17_D18: OpKind = MCK_DDD; break;
    6767             :     case AArch64::D17_D18_D19: OpKind = MCK_DDD; break;
    6768             :     case AArch64::D18_D19_D20: OpKind = MCK_DDD; break;
    6769             :     case AArch64::D19_D20_D21: OpKind = MCK_DDD; break;
    6770             :     case AArch64::D20_D21_D22: OpKind = MCK_DDD; break;
    6771             :     case AArch64::D21_D22_D23: OpKind = MCK_DDD; break;
    6772             :     case AArch64::D22_D23_D24: OpKind = MCK_DDD; break;
    6773             :     case AArch64::D23_D24_D25: OpKind = MCK_DDD; break;
    6774             :     case AArch64::D24_D25_D26: OpKind = MCK_DDD; break;
    6775             :     case AArch64::D25_D26_D27: OpKind = MCK_DDD; break;
    6776             :     case AArch64::D26_D27_D28: OpKind = MCK_DDD; break;
    6777             :     case AArch64::D27_D28_D29: OpKind = MCK_DDD; break;
    6778             :     case AArch64::D28_D29_D30: OpKind = MCK_DDD; break;
    6779             :     case AArch64::D29_D30_D31: OpKind = MCK_DDD; break;
    6780             :     case AArch64::D30_D31_D0: OpKind = MCK_DDD; break;
    6781             :     case AArch64::D31_D0_D1: OpKind = MCK_DDD; break;
    6782             :     case AArch64::Q0_Q1: OpKind = MCK_Reg25; break;
    6783             :     case AArch64::Q1_Q2: OpKind = MCK_Reg25; break;
    6784             :     case AArch64::Q2_Q3: OpKind = MCK_Reg25; break;
    6785             :     case AArch64::Q3_Q4: OpKind = MCK_Reg25; break;
    6786             :     case AArch64::Q4_Q5: OpKind = MCK_Reg25; break;
    6787             :     case AArch64::Q5_Q6: OpKind = MCK_Reg25; break;
    6788             :     case AArch64::Q6_Q7: OpKind = MCK_Reg25; break;
    6789             :     case AArch64::Q7_Q8: OpKind = MCK_Reg25; break;
    6790             :     case AArch64::Q8_Q9: OpKind = MCK_Reg25; break;
    6791             :     case AArch64::Q9_Q10: OpKind = MCK_Reg25; break;
    6792             :     case AArch64::Q10_Q11: OpKind = MCK_Reg25; break;
    6793             :     case AArch64::Q11_Q12: OpKind = MCK_Reg25; break;
    6794             :     case AArch64::Q12_Q13: OpKind = MCK_Reg25; break;
    6795             :     case AArch64::Q13_Q14: OpKind = MCK_Reg25; break;
    6796             :     case AArch64::Q14_Q15: OpKind = MCK_Reg25; break;
    6797             :     case AArch64::Q15_Q16: OpKind = MCK_Reg26; break;
    6798             :     case AArch64::Q16_Q17: OpKind = MCK_QQ; break;
    6799             :     case AArch64::Q17_Q18: OpKind = MCK_QQ; break;
    6800             :     case AArch64::Q18_Q19: OpKind = MCK_QQ; break;
    6801             :     case AArch64::Q19_Q20: OpKind = MCK_QQ; break;
    6802             :     case AArch64::Q20_Q21: OpKind = MCK_QQ; break;
    6803             :     case AArch64::Q21_Q22: OpKind = MCK_QQ; break;
    6804             :     case AArch64::Q22_Q23: OpKind = MCK_QQ; break;
    6805             :     case AArch64::Q23_Q24: OpKind = MCK_QQ; break;
    6806             :     case AArch64::Q24_Q25: OpKind = MCK_QQ; break;
    6807             :     case AArch64::Q25_Q26: OpKind = MCK_QQ; break;
    6808             :     case AArch64::Q26_Q27: OpKind = MCK_QQ; break;
    6809             :     case AArch64::Q27_Q28: OpKind = MCK_QQ; break;
    6810             :     case AArch64::Q28_Q29: OpKind = MCK_QQ; break;
    6811             :     case AArch64::Q29_Q30: OpKind = MCK_QQ; break;
    6812             :     case AArch64::Q30_Q31: OpKind = MCK_QQ; break;
    6813             :     case AArch64::Q31_Q0: OpKind = MCK_Reg28; break;
    6814             :     case AArch64::Q0_Q1_Q2_Q3: OpKind = MCK_Reg29; break;
    6815             :     case AArch64::Q1_Q2_Q3_Q4: OpKind = MCK_Reg29; break;
    6816             :     case AArch64::Q2_Q3_Q4_Q5: OpKind = MCK_Reg29; break;
    6817             :     case AArch64::Q3_Q4_Q5_Q6: OpKind = MCK_Reg29; break;
    6818             :     case AArch64::Q4_Q5_Q6_Q7: OpKind = MCK_Reg29; break;
    6819             :     case AArch64::Q5_Q6_Q7_Q8: OpKind = MCK_Reg29; break;
    6820             :     case AArch64::Q6_Q7_Q8_Q9: OpKind = MCK_Reg29; break;
    6821             :     case AArch64::Q7_Q8_Q9_Q10: OpKind = MCK_Reg29; break;
    6822             :     case AArch64::Q8_Q9_Q10_Q11: OpKind = MCK_Reg29; break;
    6823             :     case AArch64::Q9_Q10_Q11_Q12: OpKind = MCK_Reg29; break;
    6824             :     case AArch64::Q10_Q11_Q12_Q13: OpKind = MCK_Reg29; break;
    6825             :     case AArch64::Q11_Q12_Q13_Q14: OpKind = MCK_Reg29; break;
    6826             :     case AArch64::Q12_Q13_Q14_Q15: OpKind = MCK_Reg29; break;
    6827             :     case AArch64::Q13_Q14_Q15_Q16: OpKind = MCK_Reg30; break;
    6828             :     case AArch64::Q14_Q15_Q16_Q17: OpKind = MCK_Reg31; break;
    6829             :     case AArch64::Q15_Q16_Q17_Q18: OpKind = MCK_Reg32; break;
    6830             :     case AArch64::Q16_Q17_Q18_Q19: OpKind = MCK_QQQQ; break;
    6831             :     case AArch64::Q17_Q18_Q19_Q20: OpKind = MCK_QQQQ; break;
    6832             :     case AArch64::Q18_Q19_Q20_Q21: OpKind = MCK_QQQQ; break;
    6833             :     case AArch64::Q19_Q20_Q21_Q22: OpKind = MCK_QQQQ; break;
    6834             :     case AArch64::Q20_Q21_Q22_Q23: OpKind = MCK_QQQQ; break;
    6835             :     case AArch64::Q21_Q22_Q23_Q24: OpKind = MCK_QQQQ; break;
    6836             :     case AArch64::Q22_Q23_Q24_Q25: OpKind = MCK_QQQQ; break;
    6837             :     case AArch64::Q23_Q24_Q25_Q26: OpKind = MCK_QQQQ; break;
    6838             :     case AArch64::Q24_Q25_Q26_Q27: OpKind = MCK_QQQQ; break;
    6839             :     case AArch64::Q25_Q26_Q27_Q28: OpKind = MCK_QQQQ; break;
    6840             :     case AArch64::Q26_Q27_Q28_Q29: OpKind = MCK_QQQQ; break;
    6841             :     case AArch64::Q27_Q28_Q29_Q30: OpKind = MCK_QQQQ; break;
    6842             :     case AArch64::Q28_Q29_Q30_Q31: OpKind = MCK_QQQQ; break;
    6843             :     case AArch64::Q29_Q30_Q31_Q0: OpKind = MCK_Reg37; break;
    6844             :     case AArch64::Q30_Q31_Q0_Q1: OpKind = MCK_Reg38; break;
    6845             :     case AArch64::Q31_Q0_Q1_Q2: OpKind = MCK_Reg39; break;
    6846             :     case AArch64::Q0_Q1_Q2: OpKind = MCK_Reg40; break;
    6847             :     case AArch64::Q1_Q2_Q3: OpKind = MCK_Reg40; break;
    6848             :     case AArch64::Q2_Q3_Q4: OpKind = MCK_Reg40; break;
    6849             :     case AArch64::Q3_Q4_Q5: OpKind = MCK_Reg40; break;
    6850             :     case AArch64::Q4_Q5_Q6: OpKind = MCK_Reg40; break;
    6851             :     case AArch64::Q5_Q6_Q7: OpKind = MCK_Reg40; break;
    6852             :     case AArch64::Q6_Q7_Q8: OpKind = MCK_Reg40; break;
    6853             :     case AArch64::Q7_Q8_Q9: OpKind = MCK_Reg40; break;
    6854             :     case AArch64::Q8_Q9_Q10: OpKind = MCK_Reg40; break;
    6855             :     case AArch64::Q9_Q10_Q11: OpKind = MCK_Reg40; break;
    6856             :     case AArch64::Q10_Q11_Q12: OpKind = MCK_Reg40; break;
    6857             :     case AArch64::Q11_Q12_Q13: OpKind = MCK_Reg40; break;
    6858             :     case AArch64::Q12_Q13_Q14: OpKind = MCK_Reg40; break;
    6859             :     case AArch64::Q13_Q14_Q15: OpKind = MCK_Reg40; break;
    6860             :     case AArch64::Q14_Q15_Q16: OpKind = MCK_Reg41; break;
    6861             :     case AArch64::Q15_Q16_Q17: OpKind = MCK_Reg42; break;
    6862             :     case AArch64::Q16_Q17_Q18: OpKind = MCK_QQQ; break;
    6863             :     case AArch64::Q17_Q18_Q19: OpKind = MCK_QQQ; break;
    6864             :     case AArch64::Q18_Q19_Q20: OpKind = MCK_QQQ; break;
    6865             :     case AArch64::Q19_Q20_Q21: OpKind = MCK_QQQ; break;
    6866             :     case AArch64::Q20_Q21_Q22: OpKind = MCK_QQQ; break;
    6867             :     case AArch64::Q21_Q22_Q23: OpKind = MCK_QQQ; break;
    6868             :     case AArch64::Q22_Q23_Q24: OpKind = MCK_QQQ; break;
    6869             :     case AArch64::Q23_Q24_Q25: OpKind = MCK_QQQ; break;
    6870             :     case AArch64::Q24_Q25_Q26: OpKind = MCK_QQQ; break;
    6871             :     case AArch64::Q25_Q26_Q27: OpKind = MCK_QQQ; break;
    6872             :     case AArch64::Q26_Q27_Q28: OpKind = MCK_QQQ; break;
    6873             :     case AArch64::Q27_Q28_Q29: OpKind = MCK_QQQ; break;
    6874             :     case AArch64::Q28_Q29_Q30: OpKind = MCK_QQQ; break;
    6875             :     case AArch64::Q29_Q30_Q31: OpKind = MCK_QQQ; break;
    6876             :     case AArch64::Q30_Q31_Q0: OpKind = MCK_Reg45; break;
    6877             :     case AArch64::Q31_Q0_Q1: OpKind = MCK_Reg46; break;
    6878             :     case AArch64::W0_W1: OpKind = MCK_Reg47; break;
    6879             :     case AArch64::W1_W2: OpKind = MCK_Reg47; break;
    6880             :     case AArch64::W2_W3: OpKind = MCK_Reg47; break;
    6881             :     case AArch64::W3_W4: OpKind = MCK_Reg47; break;
    6882             :     case AArch64::W4_W5: OpKind = MCK_Reg47; break;
    6883             :     case AArch64::W5_W6: OpKind = MCK_Reg47; break;
    6884             :     case AArch64::W6_W7: OpKind = MCK_Reg47; break;
    6885             :     case AArch64::W7_W8: OpKind = MCK_Reg47; break;
    6886             :     case AArch64::W8_W9: OpKind = MCK_Reg47; break;
    6887             :     case AArch64::W9_W10: OpKind = MCK_Reg47; break;
    6888             :     case AArch64::W10_W11: OpKind = MCK_Reg47; break;
    6889             :     case AArch64::W11_W12: OpKind = MCK_Reg47; break;
    6890             :     case AArch64::W12_W13: OpKind = MCK_Reg47; break;
    6891             :     case AArch64::W13_W14: OpKind = MCK_Reg47; break;
    6892             :     case AArch64::W14_W15: OpKind = MCK_Reg47; break;
    6893             :     case AArch64::W15_W16: OpKind = MCK_Reg47; break;
    6894             :     case AArch64::W16_W17: OpKind = MCK_Reg47; break;
    6895             :     case AArch64::W17_W18: OpKind = MCK_Reg47; break;
    6896             :     case AArch64::W18_W19: OpKind = MCK_Reg47; break;
    6897             :     case AArch64::W19_W20: OpKind = MCK_Reg47; break;
    6898             :     case AArch64::W20_W21: OpKind = MCK_Reg47; break;
    6899             :     case AArch64::W21_W22: OpKind = MCK_Reg47; break;
    6900             :     case AArch64::W22_W23: OpKind = MCK_Reg47; break;
    6901             :     case AArch64::W23_W24: OpKind = MCK_Reg47; break;
    6902             :     case AArch64::W24_W25: OpKind = MCK_Reg47; break;
    6903             :     case AArch64::W25_W26: OpKind = MCK_Reg47; break;
    6904             :     case AArch64::W26_W27: OpKind = MCK_Reg47; break;
    6905             :     case AArch64::W27_W28: OpKind = MCK_Reg47; break;
    6906             :     case AArch64::W28_W29: OpKind = MCK_Reg47; break;
    6907             :     case AArch64::W29_W30: OpKind = MCK_Reg47; break;
    6908             :     case AArch64::W30_WZR: OpKind = MCK_Reg48; break;
    6909             :     case AArch64::WZR_W0: OpKind = MCK_Reg50; break;
    6910             :     case AArch64::X0_X1: OpKind = MCK_Reg51; break;
    6911             :     case AArch64::X1_X2: OpKind = MCK_Reg51; break;
    6912             :     case AArch64::X2_X3: OpKind = MCK_Reg51; break;
    6913             :     case AArch64::X3_X4: OpKind = MCK_Reg51; break;
    6914             :     case AArch64::X4_X5: OpKind = MCK_Reg51; break;
    6915             :     case AArch64::X5_X6: OpKind = MCK_Reg51; break;
    6916             :     case AArch64::X6_X7: OpKind = MCK_Reg51; break;
    6917             :     case AArch64::X7_X8: OpKind = MCK_Reg51; break;
    6918             :     case AArch64::X8_X9: OpKind = MCK_Reg51; break;
    6919             :     case AArch64::X9_X10: OpKind = MCK_Reg51; break;
    6920             :     case AArch64::X10_X11: OpKind = MCK_Reg51; break;
    6921             :     case AArch64::X11_X12: OpKind = MCK_Reg51; break;
    6922             :     case AArch64::X12_X13: OpKind = MCK_Reg51; break;
    6923             :     case AArch64::X13_X14: OpKind = MCK_Reg51; break;
    6924             :     case AArch64::X14_X15: OpKind = MCK_Reg51; break;
    6925             :     case AArch64::X15_X16: OpKind = MCK_Reg51; break;
    6926             :     case AArch64::X16_X17: OpKind = MCK_Reg51; break;
    6927             :     case AArch64::X17_X18: OpKind = MCK_Reg51; break;
    6928             :     case AArch64::X18_X19: OpKind = MCK_Reg52; break;
    6929             :     case AArch64::X19_X20: OpKind = MCK_Reg53; break;
    6930             :     case AArch64::X20_X21: OpKind = MCK_Reg53; break;
    6931             :     case AArch64::X21_X22: OpKind = MCK_Reg53; break;
    6932             :     case AArch64::X22_X23: OpKind = MCK_Reg53; break;
    6933             :     case AArch64::X23_X24: OpKind = MCK_Reg53; break;
    6934             :     case AArch64::X24_X25: OpKind = MCK_Reg53; break;
    6935             :     case AArch64::X25_X26: OpKind = MCK_Reg53; break;
    6936             :     case AArch64::X26_X27: OpKind = MCK_Reg53; break;
    6937             :     case AArch64::X27_X28: OpKind = MCK_Reg53; break;
    6938             :     case AArch64::X28_FP: OpKind = MCK_Reg53; break;
    6939             :     case AArch64::FP_LR: OpKind = MCK_Reg53; break;
    6940             :     case AArch64::LR_XZR: OpKind = MCK_Reg54; break;
    6941             :     case AArch64::XZR_X0: OpKind = MCK_Reg57; break;
    6942             :     }
    6943      176627 :     return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
    6944             :                                       getDiagKindFromRegisterClass(Kind);
    6945             :   }
    6946             : 
    6947             :   if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
    6948             :     return getDiagKindFromRegisterClass(Kind);
    6949             : 
    6950             :   return MCTargetAsmParser::Match_InvalidOperand;
    6951             : }
    6952             : 
    6953             : #ifndef NDEBUG
    6954             : const char *getMatchClassName(MatchClassKind Kind) {
    6955             :   switch (Kind) {
    6956             :   case InvalidMatchClass: return "InvalidMatchClass";
    6957             :   case OptionalMatchClass: return "OptionalMatchClass";
    6958             :   case MCK__DOT_16B: return "MCK__DOT_16B";
    6959             :   case MCK__DOT_1D: return "MCK__DOT_1D";
    6960             :   case MCK__DOT_1Q: return "MCK__DOT_1Q";
    6961             :   case MCK__DOT_2D: return "MCK__DOT_2D";
    6962             :   case MCK__DOT_2H: return "MCK__DOT_2H";
    6963             :   case MCK__DOT_2S: return "MCK__DOT_2S";
    6964             :   case MCK__DOT_4B: return "MCK__DOT_4B";
    6965             :   case MCK__DOT_4H: return "MCK__DOT_4H";
    6966             :   case MCK__DOT_4S: return "MCK__DOT_4S";
    6967             :   case MCK__DOT_8B: return "MCK__DOT_8B";
    6968             :   case MCK__DOT_8H: return "MCK__DOT_8H";
    6969             :   case MCK__DOT_B: return "MCK__DOT_B";
    6970             :   case MCK__DOT_D: return "MCK__DOT_D";
    6971             :   case MCK__DOT_H: return "MCK__DOT_H";
    6972             :   case MCK__DOT_Q: return "MCK__DOT_Q";
    6973             :   case MCK__DOT_S: return "MCK__DOT_S";
    6974             :   case MCK__EXCLAIM_: return "MCK__EXCLAIM_";
    6975             :   case MCK__35_0: return "MCK__35_0";
    6976             :   case MCK__35_1: return "MCK__35_1";
    6977             :   case MCK__35_12: return "MCK__35_12";
    6978             :   case MCK__35_16: return "MCK__35_16";
    6979             :   case MCK__35_2: return "MCK__35_2";
    6980             :   case MCK__35_24: return "MCK__35_24";
    6981             :   case MCK__35_3: return "MCK__35_3";
    6982             :   case MCK__35_32: return "MCK__35_32";
    6983             :   case MCK__35_4: return "MCK__35_4";
    6984             :   case MCK__35_48: return "MCK__35_48";
    6985             :   case MCK__35_6: return "MCK__35_6";
    6986             :   case MCK__35_64: return "MCK__35_64";
    6987             :   case MCK__35_8: return "MCK__35_8";
    6988             :   case MCK__DOT_: return "MCK__DOT_";
    6989             :   case MCK__DOT_0: return "MCK__DOT_0";
    6990             :   case MCK__DOT_16b: return "MCK__DOT_16b";
    6991             :   case MCK__DOT_1d: return "MCK__DOT_1d";
    6992             :   case MCK__DOT_1q: return "MCK__DOT_1q";
    6993             :   case MCK__DOT_2d: return "MCK__DOT_2d";
    6994             :   case MCK__DOT_2h: return "MCK__DOT_2h";
    6995             :   case MCK__DOT_2s: return "MCK__DOT_2s";
    6996             :   case MCK__DOT_4b: return "MCK__DOT_4b";
    6997             :   case MCK__DOT_4h: return "MCK__DOT_4h";
    6998             :   case MCK__DOT_4s: return "MCK__DOT_4s";
    6999             :   case MCK__DOT_8b: return "MCK__DOT_8b";
    7000             :   case MCK__DOT_8h: return "MCK__DOT_8h";
    7001             :   case MCK__DOT_b: return "MCK__DOT_b";
    7002             :   case MCK__DOT_d: return "MCK__DOT_d";
    7003             :   case MCK__DOT_h: return "MCK__DOT_h";
    7004             :   case MCK__DOT_q: return "MCK__DOT_q";
    7005             :   case MCK__DOT_s: return "MCK__DOT_s";
    7006             :   case MCK__47_: return "MCK__47_";
    7007             :   case MCK__91_: return "MCK__91_";
    7008             :   case MCK__93_: return "MCK__93_";
    7009             :   case MCK_m: return "MCK_m";
    7010             :   case MCK_CCR: return "MCK_CCR";
    7011             :   case MCK_GPR32sponly: return "MCK_GPR32sponly";
    7012             :   case MCK_GPR64sponly: return "MCK_GPR64sponly";
    7013             :   case MCK_PPR_3b: return "MCK_PPR_3b";
    7014             :   case MCK_Reg29: return "MCK_Reg29";
    7015             :   case MCK_Reg30: return "MCK_Reg30";
    7016             :   case MCK_Reg39: return "MCK_Reg39";
    7017             :   case MCK_Reg40: return "MCK_Reg40";
    7018             :   case MCK_Reg25: return "MCK_Reg25";
    7019             :   case MCK_Reg31: return "MCK_Reg31";
    7020             :   case MCK_Reg36: return "MCK_Reg36";
    7021             :   case MCK_Reg38: return "MCK_Reg38";
    7022             :   case MCK_Reg41: return "MCK_Reg41";
    7023             :   case MCK_Reg46: return "MCK_Reg46";
    7024             :   case MCK_Reg20: return "MCK_Reg20";
    7025             :   case MCK_Reg26: return "MCK_Reg26";
    7026             :   case MCK_Reg28: return "MCK_Reg28";
    7027             :   case MCK_Reg32: return "MCK_Reg32";
    7028             :   case MCK_Reg34: return "MCK_Reg34";
    7029             :   case MCK_Reg35: return "MCK_Reg35";
    7030             :   case MCK_Reg37: return "MCK_Reg37";
    7031             :   case MCK_Reg42: return "MCK_Reg42";
    7032             :   case MCK_Reg44: return "MCK_Reg44";
    7033             :   case MCK_Reg45: return "MCK_Reg45";
    7034             :   case MCK_FPR128_lo: return "MCK_FPR128_lo";
    7035             :   case MCK_PPR: return "MCK_PPR";
    7036             :   case MCK_Reg51: return "MCK_Reg51";
    7037             :   case MCK_Reg52: return "MCK_Reg52";
    7038             :   case MCK_Reg57: return "MCK_Reg57";
    7039             :   case MCK_tcGPR64: return "MCK_tcGPR64";
    7040             :   case MCK_Reg47: return "MCK_Reg47";
    7041             :   case MCK_Reg53: return "MCK_Reg53";
    7042             :   case MCK_Reg48: return "MCK_Reg48";
    7043             :   case MCK_Reg50: return "MCK_Reg50";
    7044             :   case MCK_Reg54: return "MCK_Reg54";
    7045             :   case MCK_Reg56: return "MCK_Reg56";
    7046             :   case MCK_GPR32common: return "MCK_GPR32common";
    7047             :   case MCK_GPR64common: return "MCK_GPR64common";
    7048             :   case MCK_DD: return "MCK_DD";
    7049             :   case MCK_DDD: return "MCK_DDD";
    7050             :   case MCK_DDDD: return "MCK_DDDD";
    7051             :   case MCK_FPR128: return "MCK_FPR128";
    7052             :   case MCK_FPR16: return "MCK_FPR16";
    7053             :   case MCK_FPR32: return "MCK_FPR32";
    7054             :   case MCK_FPR64: return "MCK_FPR64";
    7055             :   case MCK_FPR8: return "MCK_FPR8";
    7056             :   case MCK_GPR32: return "MCK_GPR32";
    7057             :   case MCK_GPR32sp: return "MCK_GPR32sp";
    7058             :   case MCK_GPR64: return "MCK_GPR64";
    7059             :   case MCK_GPR64sp: return "MCK_GPR64sp";
    7060             :   case MCK_QQ: return "MCK_QQ";
    7061             :   case MCK_QQQ: return "MCK_QQQ";
    7062             :   case MCK_QQQQ: return "MCK_QQQQ";
    7063             :   case MCK_WSeqPairsClass: return "MCK_WSeqPairsClass";
    7064             :   case MCK_XSeqPairsClass: return "MCK_XSeqPairsClass";
    7065             :   case MCK_ZPR: return "MCK_ZPR";
    7066             :   case MCK_GPR32all: return "MCK_GPR32all";
    7067             :   case MCK_GPR64all: return "MCK_GPR64all";
    7068             :   case MCK_AddSubImmNeg: return "MCK_AddSubImmNeg";
    7069             :   case MCK_AddSubImm: return "MCK_AddSubImm";
    7070             :   case MCK_AdrLabel: return "MCK_AdrLabel";
    7071             :   case MCK_AdrpLabel: return "MCK_AdrpLabel";
    7072             :   case MCK_Barrier: return "MCK_Barrier";
    7073             :   case MCK_BranchTarget14: return "MCK_BranchTarget14";
    7074             :   case MCK_BranchTarget26: return "MCK_BranchTarget26";
    7075             :   case MCK_CondCode: return "MCK_CondCode";
    7076             :   case MCK_Extend64: return "MCK_Extend64";
    7077             :   case MCK_ExtendLSL64: return "MCK_ExtendLSL64";
    7078             :   case MCK_Extend: return "MCK_Extend";
    7079             :   case MCK_FPImm: return "MCK_FPImm";
    7080             :   case MCK_GPR32as64: return "MCK_GPR32as64";
    7081             :   case MCK_GPR64sp0: return "MCK_GPR64sp0";
    7082             :   case MCK_Imm0_127: return "MCK_Imm0_127";
    7083             :   case MCK_Imm0_15: return "MCK_Imm0_15";
    7084             :   case MCK_Imm0_1: return "MCK_Imm0_1";
    7085             :   case MCK_Imm0_255: return "MCK_Imm0_255";
    7086             :   case MCK_Imm0_31: return "MCK_Imm0_31";
    7087             :   case MCK_Imm0_63: return "MCK_Imm0_63";
    7088             :   case MCK_Imm0_65535: return "MCK_Imm0_65535";
    7089             :   case MCK_Imm0_7: return "MCK_Imm0_7";
    7090             :   case MCK_Imm1_16: return "MCK_Imm1_16";
    7091             :   case MCK_Imm1_32: return "MCK_Imm1_32";
    7092             :   case MCK_Imm1_64: return "MCK_Imm1_64";
    7093             :   case MCK_Imm1_8: return "MCK_Imm1_8";
    7094             :   case MCK_Imm: return "MCK_Imm";
    7095             :   case MCK_LogicalImm32Not: return "MCK_LogicalImm32Not";
    7096             :   case MCK_LogicalImm32: return "MCK_LogicalImm32";
    7097             :   case MCK_LogicalImm64Not: return "MCK_LogicalImm64Not";
    7098             :   case MCK_LogicalImm64: return "MCK_LogicalImm64";
    7099             :   case MCK_MRSSystemRegister: return "MCK_MRSSystemRegister";
    7100             :   case MCK_MSRSystemRegister: return "MCK_MSRSystemRegister";
    7101             :   case MCK_MemWExtend128: return "MCK_MemWExtend128";
    7102             :   case MCK_MemWExtend16: return "MCK_MemWExtend16";
    7103             :   case MCK_MemWExtend32: return "MCK_MemWExtend32";
    7104             :   case MCK_MemWExtend64: return "MCK_MemWExtend64";
    7105             :   case MCK_MemWExtend8: return "MCK_MemWExtend8";
    7106             :   case MCK_MemXExtend128: return "MCK_MemXExtend128";
    7107             :   case MCK_MemXExtend16: return "MCK_MemXExtend16";
    7108             :   case MCK_MemXExtend32: return "MCK_MemXExtend32";
    7109             :   case MCK_MemXExtend64: return "MCK_MemXExtend64";
    7110             :   case MCK_MemXExtend8: return "MCK_MemXExtend8";
    7111             :   case MCK_MovKSymbolG0: return "MCK_MovKSymbolG0";
    7112             :   case MCK_MovKSymbolG1: return "MCK_MovKSymbolG1";
    7113             :   case MCK_MovKSymbolG2: return "MCK_MovKSymbolG2";
    7114             :   case MCK_MovKSymbolG3: return "MCK_MovKSymbolG3";
    7115             :   case MCK_MovZSymbolG0: return "MCK_MovZSymbolG0";
    7116             :   case MCK_MovZSymbolG1: return "MCK_MovZSymbolG1";
    7117             :   case MCK_MovZSymbolG2: return "MCK_MovZSymbolG2";
    7118             :   case MCK_MovZSymbolG3: return "MCK_MovZSymbolG3";
    7119             :   case MCK_PCRelLabel19: return "MCK_PCRelLabel19";
    7120             :   case MCK_SVEPredicateHReg: return "MCK_SVEPredicateHReg";
    7121             :   case MCK_SVEPredicateSReg: return "MCK_SVEPredicateSReg";
    7122             :   case MCK_SVEPredicate3bHReg: return "MCK_SVEPredicate3bHReg";
    7123             :   case MCK_SVEPredicate3bSReg: return "MCK_SVEPredicate3bSReg";
    7124             :   case MCK_SVEPredicate3bDReg: return "MCK_SVEPredicate3bDReg";
    7125             :   case MCK_SVEPredicate3bBReg: return "MCK_SVEPredicate3bBReg";
    7126             :   case MCK_SVEPredicate3bAnyReg: return "MCK_SVEPredicate3bAnyReg";
    7127             :   case MCK_SVEPredicateDReg: return "MCK_SVEPredicateDReg";
    7128             :   case MCK_SVEPredicateBReg: return "MCK_SVEPredicateBReg";
    7129             :   case MCK_SVEPredicateAnyReg: return "MCK_SVEPredicateAnyReg";
    7130             :   case MCK_PSBHint: return "MCK_PSBHint";
    7131             :   case MCK_Prefetch: return "MCK_Prefetch";
    7132             :   case MCK_SIMDImmType10: return "MCK_SIMDImmType10";
    7133             :   case MCK_SImm10s8: return "MCK_SImm10s8";
    7134             :   case MCK_SImm6: return "MCK_SImm6";
    7135             :   case MCK_SImm7s16: return "MCK_SImm7s16";
    7136             :   case MCK_SImm7s4: return "MCK_SImm7s4";
    7137             :   case MCK_SImm7s8: return "MCK_SImm7s8";
    7138             :   case MCK_SImm9OffsetFB128: return "MCK_SImm9OffsetFB128";
    7139             :   case MCK_SImm9OffsetFB16: return "MCK_SImm9OffsetFB16";
    7140             :   case MCK_SImm9OffsetFB32: return "MCK_SImm9OffsetFB32";
    7141             :   case MCK_SImm9OffsetFB64: return "MCK_SImm9OffsetFB64";
    7142             :   case MCK_SImm9OffsetFB8: return "MCK_SImm9OffsetFB8";
    7143             :   case MCK_SImm9: return "MCK_SImm9";
    7144             :   case MCK_SVEPattern: return "MCK_SVEPattern";
    7145             :   case MCK_LogicalVecHalfWordShifter: return "MCK_LogicalVecHalfWordShifter";
    7146             :   case MCK_ArithmeticShifter32: return "MCK_ArithmeticShifter32";
    7147             :   case MCK_ArithmeticShifter64: return "MCK_ArithmeticShifter64";
    7148             :   case MCK_LogicalShifter32: return "MCK_LogicalShifter32";
    7149             :   case MCK_LogicalShifter64: return "MCK_LogicalShifter64";
    7150             :   case MCK_LogicalVecShifter: return "MCK_LogicalVecShifter";
    7151             :   case MCK_MovImm32Shifter: return "MCK_MovImm32Shifter";
    7152             :   case MCK_MovImm64Shifter: return "MCK_MovImm64Shifter";
    7153             :   case MCK_MoveVecShifter: return "MCK_MoveVecShifter";
    7154             :   case MCK_Shifter: return "MCK_Shifter";
    7155             :   case MCK_SysCR: return "MCK_SysCR";
    7156             :   case MCK_SystemPStateFieldWithImm0_15: return "MCK_SystemPStateFieldWithImm0_15";
    7157             :   case MCK_SystemPStateFieldWithImm0_1: return "MCK_SystemPStateFieldWithImm0_1";
    7158             :   case MCK_TBZImm0_31: return "MCK_TBZImm0_31";
    7159             :   case MCK_Imm32_63: return "MCK_Imm32_63";
    7160             :   case MCK_UImm12Offset16: return "MCK_UImm12Offset16";
    7161             :   case MCK_UImm12Offset1: return "MCK_UImm12Offset1";
    7162             :   case MCK_UImm12Offset2: return "MCK_UImm12Offset2";
    7163             :   case MCK_UImm12Offset4: return "MCK_UImm12Offset4";
    7164             :   case MCK_UImm12Offset8: return "MCK_UImm12Offset8";
    7165             :   case MCK_VecListFour128: return "MCK_VecListFour128";
    7166             :   case MCK_TypedVectorList4_16b: return "MCK_TypedVectorList4_16b";
    7167             :   case MCK_TypedVectorList4_1d: return "MCK_TypedVectorList4_1d";
    7168             :   case MCK_TypedVectorList4_2d: return "MCK_TypedVectorList4_2d";
    7169             :   case MCK_TypedVectorList4_2s: return "MCK_TypedVectorList4_2s";
    7170             :   case MCK_TypedVectorList4_4h: return "MCK_TypedVectorList4_4h";
    7171             :   case MCK_TypedVectorList4_4s: return "MCK_TypedVectorList4_4s";
    7172             :   case MCK_VecListFour64: return "MCK_VecListFour64";
    7173             :   case MCK_TypedVectorList4_8b: return "MCK_TypedVectorList4_8b";
    7174             :   case MCK_TypedVectorList4_8h: return "MCK_TypedVectorList4_8h";
    7175             :   case MCK_TypedVectorList4_0b: return "MCK_TypedVectorList4_0b";
    7176             :   case MCK_TypedVectorList4_0d: return "MCK_TypedVectorList4_0d";
    7177             :   case MCK_TypedVectorList4_0h: return "MCK_TypedVectorList4_0h";
    7178             :   case MCK_TypedVectorList4_0s: return "MCK_TypedVectorList4_0s";
    7179             :   case MCK_VecListOne128: return "MCK_VecListOne128";
    7180             :   case MCK_TypedVectorList1_16b: return "MCK_TypedVectorList1_16b";
    7181             :   case MCK_TypedVectorList1_1d: return "MCK_TypedVectorList1_1d";
    7182             :   case MCK_TypedVectorList1_2d: return "MCK_TypedVectorList1_2d";
    7183             :   case MCK_TypedVectorList1_2s: return "MCK_TypedVectorList1_2s";
    7184             :   case MCK_TypedVectorList1_4h: return "MCK_TypedVectorList1_4h";
    7185             :   case MCK_TypedVectorList1_4s: return "MCK_TypedVectorList1_4s";
    7186             :   case MCK_VecListOne64: return "MCK_VecListOne64";
    7187             :   case MCK_TypedVectorList1_8b: return "MCK_TypedVectorList1_8b";
    7188             :   case MCK_TypedVectorList1_8h: return "MCK_TypedVectorList1_8h";
    7189             :   case MCK_TypedVectorList1_0b: return "MCK_TypedVectorList1_0b";
    7190             :   case MCK_TypedVectorList1_0d: return "MCK_TypedVectorList1_0d";
    7191             :   case MCK_TypedVectorList1_0h: return "MCK_TypedVectorList1_0h";
    7192             :   case MCK_TypedVectorList1_0s: return "MCK_TypedVectorList1_0s";
    7193             :   case MCK_VecListThree128: return "MCK_VecListThree128";
    7194             :   case MCK_TypedVectorList3_16b: return "MCK_TypedVectorList3_16b";
    7195             :   case MCK_TypedVectorList3_1d: return "MCK_TypedVectorList3_1d";
    7196             :   case MCK_TypedVectorList3_2d: return "MCK_TypedVectorList3_2d";
    7197             :   case MCK_TypedVectorList3_2s: return "MCK_TypedVectorList3_2s";
    7198             :   case MCK_TypedVectorList3_4h: return "MCK_TypedVectorList3_4h";
    7199             :   case MCK_TypedVectorList3_4s: return "MCK_TypedVectorList3_4s";
    7200             :   case MCK_VecListThree64: return "MCK_VecListThree64";
    7201             :   case MCK_TypedVectorList3_8b: return "MCK_TypedVectorList3_8b";
    7202             :   case MCK_TypedVectorList3_8h: return "MCK_TypedVectorList3_8h";
    7203             :   case MCK_TypedVectorList3_0b: return "MCK_TypedVectorList3_0b";
    7204             :   case MCK_TypedVectorList3_0d: return "MCK_TypedVectorList3_0d";
    7205             :   case MCK_TypedVectorList3_0h: return "MCK_TypedVectorList3_0h";
    7206             :   case MCK_TypedVectorList3_0s: return "MCK_TypedVectorList3_0s";
    7207             :   case MCK_VecListTwo128: return "MCK_VecListTwo128";
    7208             :   case MCK_TypedVectorList2_16b: return "MCK_TypedVectorList2_16b";
    7209             :   case MCK_TypedVectorList2_1d: return "MCK_TypedVectorList2_1d";
    7210             :   case MCK_TypedVectorList2_2d: return "MCK_TypedVectorList2_2d";
    7211             :   case MCK_TypedVectorList2_2s: return "MCK_TypedVectorList2_2s";
    7212             :   case MCK_TypedVectorList2_4h: return "MCK_TypedVectorList2_4h";
    7213             :   case MCK_TypedVectorList2_4s: return "MCK_TypedVectorList2_4s";
    7214             :   case MCK_VecListTwo64: return "MCK_VecListTwo64";
    7215             :   case MCK_TypedVectorList2_8b: return "MCK_TypedVectorList2_8b";
    7216             :   case MCK_TypedVectorList2_8h: return "MCK_TypedVectorList2_8h";
    7217             :   case MCK_TypedVectorList2_0b: return "MCK_TypedVectorList2_0b";
    7218             :   case MCK_TypedVectorList2_0d: return "MCK_TypedVectorList2_0d";
    7219             :   case MCK_TypedVectorList2_0h: return "MCK_TypedVectorList2_0h";
    7220             :   case MCK_TypedVectorList2_0s: return "MCK_TypedVectorList2_0s";
    7221             :   case MCK_VectorIndex1: return "MCK_VectorIndex1";
    7222             :   case MCK_VectorIndexB: return "MCK_VectorIndexB";
    7223             :   case MCK_VectorIndexD: return "MCK_VectorIndexD";
    7224             :   case MCK_VectorIndexH: return "MCK_VectorIndexH";
    7225             :   case MCK_VectorIndexS: return "MCK_VectorIndexS";
    7226             :   case MCK_VectorReg128: return "MCK_VectorReg128";
    7227             :   case MCK_VectorReg64: return "MCK_VectorReg64";
    7228             :   case MCK_VectorRegLo: return "MCK_VectorRegLo";
    7229             :   case MCK_WSeqPair: return "MCK_WSeqPair";
    7230             :   case MCK_XSeqPair: return "MCK_XSeqPair";
    7231             :   case MCK_SVEVectorQReg: return "MCK_SVEVectorQReg";
    7232             :   case MCK_SVEVectorHReg: return "MCK_SVEVectorHReg";
    7233             :   case MCK_SVEVectorSReg: return "MCK_SVEVectorSReg";
    7234             :   case MCK_SVEVectorDReg: return "MCK_SVEVectorDReg";
    7235             :   case MCK_SVEVectorBReg: return "MCK_SVEVectorBReg";
    7236             :   case MCK_SVEVectorAnyReg: return "MCK_SVEVectorAnyReg";
    7237             :   case MCK_ComplexRotationEven: return "MCK_ComplexRotationEven";
    7238             :   case MCK_ComplexRotationOdd: return "MCK_ComplexRotationOdd";
    7239             :   case MCK_SVELogicalImm8: return "MCK_SVELogicalImm8";
    7240             :   case MCK_SVELogicalImm16: return "MCK_SVELogicalImm16";
    7241             :   case MCK_SVELogicalImm32: return "MCK_SVELogicalImm32";
    7242             :   case MCK_SVELogicalImm8Not: return "MCK_SVELogicalImm8Not";
    7243             :   case MCK_SVELogicalImm16Not: return "MCK_SVELogicalImm16Not";
    7244             :   case MCK_SVELogicalImm32Not: return "MCK_SVELogicalImm32Not";
    7245             :   case MCK_MOVZ32_lsl0MovAlias: return "MCK_MOVZ32_lsl0MovAlias";
    7246             :   case MCK_MOVZ32_lsl16MovAlias: return "MCK_MOVZ32_lsl16MovAlias";
    7247             :   case MCK_MOVZ64_lsl0MovAlias: return "MCK_MOVZ64_lsl0MovAlias";
    7248             :   case MCK_MOVZ64_lsl16MovAlias: return "MCK_MOVZ64_lsl16MovAlias";
    7249             :   case MCK_MOVZ64_lsl32MovAlias: return "MCK_MOVZ64_lsl32MovAlias";
    7250             :   case MCK_MOVZ64_lsl48MovAlias: return "MCK_MOVZ64_lsl48MovAlias";
    7251             :   case MCK_MOVN32_lsl0MovAlias: return "MCK_MOVN32_lsl0MovAlias";
    7252             :   case MCK_MOVN32_lsl16MovAlias: return "MCK_MOVN32_lsl16MovAlias";
    7253             :   case MCK_MOVN64_lsl0MovAlias: return "MCK_MOVN64_lsl0MovAlias";
    7254             :   case MCK_MOVN64_lsl16MovAlias: return "MCK_MOVN64_lsl16MovAlias";
    7255             :   case MCK_MOVN64_lsl32MovAlias: return "MCK_MOVN64_lsl32MovAlias";
    7256             :   case MCK_MOVN64_lsl48MovAlias: return "MCK_MOVN64_lsl48MovAlias";
    7257             :   case NumMatchClassKinds: return "NumMatchClassKinds";
    7258             :   }
    7259             :   llvm_unreachable("unhandled MatchClassKind!");
    7260             : }
    7261             : 
    7262             : #endif // NDEBUG
    7263         522 : uint64_t AArch64AsmParser::
    7264             : ComputeAvailableFeatures(const FeatureBitset& FB) const {
    7265             :   uint64_t Features = 0;
    7266         522 :   if ((FB[AArch64::HasV8_1aOps]))
    7267             :     Features |= Feature_HasV8_1a;
    7268         522 :   if ((FB[AArch64::HasV8_2aOps]))
    7269          28 :     Features |= Feature_HasV8_2a;
    7270         522 :   if ((FB[AArch64::HasV8_3aOps]))
    7271           9 :     Features |= Feature_HasV8_3a;
    7272         522 :   if ((FB[AArch64::FeatureFPARMv8]))
    7273         517 :     Features |= Feature_HasFPARMv8;
    7274         522 :   if ((FB[AArch64::FeatureNEON]))
    7275         512 :     Features |= Feature_HasNEON;
    7276         522 :   if ((FB[AArch64::FeatureCrypto]))
    7277          31 :     Features |= Feature_HasCrypto;
    7278         522 :   if ((FB[AArch64::FeatureDotProd]))
    7279          12 :     Features |= Feature_HasDotProd;
    7280         522 :   if ((FB[AArch64::FeatureCRC]))
    7281          41 :     Features |= Feature_HasCRC;
    7282         522 :   if ((FB[AArch64::FeatureLSE]))
    7283          36 :     Features |= Feature_HasLSE;
    7284         522 :   if ((FB[AArch64::FeatureRAS]))
    7285          29 :     Features |= Feature_HasRAS;
    7286         522 :   if ((FB[AArch64::FeatureRDM]))
    7287          36 :     Features |= Feature_HasRDM;
    7288         522 :   if ((FB[AArch64::FeatureFullFP16]))
    7289          36 :     Features |= Feature_HasFullFP16;
    7290         522 :   if ((FB[AArch64::FeatureSPE]))
    7291           1 :     Features |= Feature_HasSPE;
    7292         522 :   if ((FB[AArch64::FeatureFuseAES]))
    7293         522 :     Features |= Feature_HasFuseAES;
    7294         522 :   if ((FB[AArch64::FeatureSVE]))
    7295          50 :     Features |= Feature_HasSVE;
    7296         522 :   if ((FB[AArch64::FeatureRCPC]))
    7297          20 :     Features |= Feature_HasRCPC;
    7298         522 :   if ((!FB[AArch64::FeatureNoNegativeImmediates]))
    7299         520 :     Features |= Feature_UseNegativeImmediates;
    7300         522 :   return Features;
    7301             : }
    7302             : 
    7303       13323 : static bool checkAsmTiedOperandConstraints(unsigned Kind,
    7304             :                                const OperandVector &Operands,
    7305             :                                uint64_t &ErrorInfo) {
    7306             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    7307       13323 :   const uint8_t *Converter = ConversionTable[Kind];
    7308       92265 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    7309       39491 :     switch (*p) {
    7310        2408 :     case CVT_Tied: {
    7311        2408 :       unsigned OpIdx = *(p+1);
    7312             :       assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
    7313             :                               std::begin(TiedAsmOperandTable)) &&
    7314             :              "Tied operand not found");
    7315        2408 :       unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
    7316        2408 :       unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
    7317        2408 :       if (OpndNum1 != OpndNum2) {
    7318         140 :         auto &SrcOp1 = Operands[OpndNum1];
    7319         140 :         auto &SrcOp2 = Operands[OpndNum2];
    7320         420 :         if (SrcOp1->isReg() && SrcOp2->isReg() &&
    7321         280 :             SrcOp1->getReg() != SrcOp2->getReg()) {
    7322          20 :           ErrorInfo = OpndNum2;
    7323          20 :           return false;
    7324             :         }
    7325             :       }
    7326             :       break;
    7327             :     }
    7328             :     default:
    7329             :       break;
    7330             :     }
    7331             :   }
    7332             :   return true;
    7333             : }
    7334             : 
    7335             : static const char *const MnemonicTable =
    7336             :     "\003abs\003adc\004adcs\003add\005addhn\006addhn2\004addp\005addpl\004ad"
    7337             :     "ds\004addv\005addvl\003adr\004adrp\004aesd\004aese\006aesimc\005aesmc\003"
    7338             :     "and\004ands\003asr\004asrv\005autda\005autdb\006autdza\006autdzb\005aut"
    7339             :     "ia\tautia1716\007autiasp\006autiaz\005autib\tautib1716\007autibsp\006au"
    7340             :     "tibz\006autiza\006autizb\001b\003bfm\003bic\004bics\003bif\003bit\002bl"
    7341             :     "\003blr\005blraa\006blraaz\005blrab\006blrabz\002br\004braa\005braaz\004"
    7342             :     "brab\005brabz\003brk\003bsl\003cas\004casa\005casab\005casah\005casal\006"
    7343             :     "casalb\006casalh\004casb\004cash\004casl\005caslb\005caslh\004casp\005c"
    7344             :     "aspa\006caspal\005caspl\004cbnz\003cbz\004ccmn\004ccmp\004cinc\004cinv\005"
    7345             :     "clrex\003cls\003clz\004cmeq\004cmge\004cmgt\004cmhi\004cmhs\004cmle\004"
    7346             :     "cmlo\004cmls\004cmlt\003cmn\003cmp\005cmtst\004cneg\003cnt\006crc32b\007"
    7347             :     "crc32cb\007crc32ch\007crc32cw\007crc32cx\006crc32h\006crc32w\006crc32x\004"
    7348             :     "csdb\004csel\004cset\005csetm\005csinc\005csinv\005csneg\005dcps1\005dc"
    7349             :     "ps2\005dcps3\003dmb\004drps\003dsb\003dup\003eon\003eor\004eret\006eret"
    7350             :     "aa\006eretab\003esb\003ext\004extr\004fabd\004fabs\005facge\005facgt\005"
    7351             :     "facle\005faclt\004fadd\005faddp\005fcadd\005fccmp\006fccmpe\005fcmeq\005"
    7352             :     "fcmge\005fcmgt\005fcmla\005fcmle\005fcmlt\004fcmp\005fcmpe\005fcsel\004"
    7353             :     "fcvt\006fcvtas\006fcvtau\005fcvtl\006fcvtl2\006fcvtms\006fcvtmu\005fcvt"
    7354             :     "n\006fcvtn2\006fcvtns\006fcvtnu\006fcvtps\006fcvtpu\006fcvtxn\007fcvtxn"
    7355             :     "2\006fcvtzs\006fcvtzu\004fdiv\007fjcvtzs\005fmadd\004fmax\006fmaxnm\007"
    7356             :     "fmaxnmp\007fmaxnmv\005fmaxp\005fmaxv\004fmin\006fminnm\007fminnmp\007fm"
    7357             :     "innmv\005fminp\005fminv\004fmla\004fmls\004fmov\005fmsub\004fmul\005fmu"
    7358             :     "lx\004fneg\006fnmadd\006fnmsub\005fnmul\006frecpe\006frecps\006frecpx\006"
    7359             :     "frinta\006frinti\006frintm\006frintn\006frintp\006frintx\006frintz\007f"
    7360             :     "rsqrte\007frsqrts\005fsqrt\004fsub\004hint\003hlt\003hvc\003ins\003isb\003"
    7361             :     "ld1\004ld1r\003ld2\004ld2r\003ld3\004ld3r\003ld4\004ld4r\005ldadd\006ld"
    7362             :     "adda\007ldaddab\007ldaddah\007ldaddal\010ldaddalb\010ldaddalh\006ldaddb"
    7363             :     "\006ldaddh\006ldaddl\007ldaddlb\007ldaddlh\005ldapr\006ldaprb\006ldaprh"
    7364             :     "\004ldar\005ldarb\005ldarh\005ldaxp\005ldaxr\006ldaxrb\006ldaxrh\005ldc"
    7365             :     "lr\006ldclra\007ldclrab\007ldclrah\007ldclral\010ldclralb\010ldclralh\006"
    7366             :     "ldclrb\006ldclrh\006ldclrl\007ldclrlb\007ldclrlh\005ldeor\006ldeora\007"
    7367             :     "ldeorab\007ldeorah\007ldeoral\010ldeoralb\010ldeoralh\006ldeorb\006ldeo"
    7368             :     "rh\006ldeorl\007ldeorlb\007ldeorlh\005ldlar\006ldlarb\006ldlarh\004ldnp"
    7369             :     "\003ldp\005ldpsw\003ldr\005ldraa\005ldrab\004ldrb\004ldrh\005ldrsb\005l"
    7370             :     "drsh\005ldrsw\005ldset\006ldseta\007ldsetab\007ldsetah\007ldsetal\010ld"
    7371             :     "setalb\010ldsetalh\006ldsetb\006ldseth\006ldsetl\007ldsetlb\007ldsetlh\006"
    7372             :     "ldsmax\007ldsmaxa\010ldsmaxab\010ldsmaxah\010ldsmaxal\tldsmaxalb\tldsma"
    7373             :     "xalh\007ldsmaxb\007ldsmaxh\007ldsmaxl\010ldsmaxlb\010ldsmaxlh\006ldsmin"
    7374             :     "\007ldsmina\010ldsminab\010ldsminah\010ldsminal\tldsminalb\tldsminalh\007"
    7375             :     "ldsminb\007ldsminh\007ldsminl\010ldsminlb\010ldsminlh\004ldtr\005ldtrb\005"
    7376             :     "ldtrh\006ldtrsb\006ldtrsh\006ldtrsw\006ldumax\007ldumaxa\010ldumaxab\010"
    7377             :     "ldumaxah\010ldumaxal\tldumaxalb\tldumaxalh\007ldumaxb\007ldumaxh\007ldu"
    7378             :     "maxl\010ldumaxlb\010ldumaxlh\006ldumin\007ldumina\010lduminab\010ldumin"
    7379             :     "ah\010lduminal\tlduminalb\tlduminalh\007lduminb\007lduminh\007lduminl\010"
    7380             :     "lduminlb\010lduminlh\004ldur\005ldurb\005ldurh\006ldursb\006ldursh\006l"
    7381             :     "dursw\004ldxp\004ldxr\005ldxrb\005ldxrh\003lsl\004lslv\003lsr\004lsrv\004"
    7382             :     "madd\003mla\003mls\004mneg\003mov\004movi\004movk\004movn\004movz\003mr"
    7383             :     "s\003msr\004msub\003mul\003mvn\004mvni\003neg\004negs\003ngc\004ngcs\003"
    7384             :     "nop\003not\003orn\003orr\005pacda\005pacdb\006pacdza\006pacdzb\005pacga"
    7385             :     "\005pacia\tpacia1716\007paciasp\006paciaz\005pacib\tpacib1716\007pacibs"
    7386             :     "p\006pacibz\006paciza\006pacizb\004pmul\005pmull\006pmull2\004prfm\005p"
    7387             :     "rfum\003psb\005ptrue\006ptrues\006raddhn\007raddhn2\004rbit\004rdvl\003"
    7388             :     "ret\005retaa\005retab\003rev\005rev16\005rev32\005rev64\003ror\004rorv\005"
    7389             :     "rshrn\006rshrn2\006rsubhn\007rsubhn2\004saba\005sabal\006sabal2\004sabd"
    7390             :     "\005sabdl\006sabdl2\006sadalp\005saddl\006saddl2\006saddlp\006saddlv\005"
    7391             :     "saddw\006saddw2\003sbc\004sbcs\004sbfm\005scvtf\004sdiv\004sdot\003sev\004"
    7392             :     "sevl\005sha1c\005sha1h\005sha1m\005sha1p\007sha1su0\007sha1su1\007sha25"
    7393             :     "6h\010sha256h2\tsha256su0\tsha256su1\005shadd\003shl\004shll\005shll2\004"
    7394             :     "shrn\005shrn2\005shsub\003sli\006smaddl\004smax\005smaxp\005smaxv\003sm"
    7395             :     "c\004smin\005sminp\005sminv\005smlal\006smlal2\005smlsl\006smlsl2\006sm"
    7396             :     "negl\004smov\006smsubl\005smulh\005smull\006smull2\005sqabs\005sqadd\007"
    7397             :     "sqdmlal\010sqdmlal2\007sqdmlsl\010sqdmlsl2\007sqdmulh\007sqdmull\010sqd"
    7398             :     "mull2\005sqneg\010sqrdmlah\010sqrdmlsh\010sqrdmulh\006sqrshl\007sqrshrn"
    7399             :     "\010sqrshrn2\010sqrshrun\tsqrshrun2\005sqshl\006sqshlu\006sqshrn\007sqs"
    7400             :     "hrn2\007sqshrun\010sqshrun2\005sqsub\005sqxtn\006sqxtn2\006sqxtun\007sq"
    7401             :     "xtun2\006srhadd\003sri\005srshl\005srshr\005srsra\004sshl\005sshll\006s"
    7402             :     "shll2\004sshr\004ssra\005ssubl\006ssubl2\005ssubw\006ssubw2\003st1\003s"
    7403             :     "t2\003st3\003st4\005stadd\006staddb\006staddh\006staddl\007staddlb\007s"
    7404             :     "taddlh\005stclr\006stclrb\006stclrh\006stclrl\007stclrlb\007stclrlh\005"
    7405             :     "steor\006steorb\006steorh\006steorl\007steorlb\007steorlh\005stllr\006s"
    7406             :     "tllrb\006stllrh\004stlr\005stlrb\005stlrh\005stlxp\005stlxr\006stlxrb\006"
    7407             :     "stlxrh\004stnp\003stp\003str\004strb\004strh\005stset\006stsetb\006stse"
    7408             :     "th\006stsetl\007stsetlb\007stsetlh\006stsmax\007stsmaxb\007stsmaxh\007s"
    7409             :     "tsmaxl\010stsmaxlb\010stsmaxlh\006stsmin\007stsminb\007stsminh\007stsmi"
    7410             :     "nl\010stsminlb\010stsminlh\004sttr\005sttrb\005sttrh\006stumax\007stuma"
    7411             :     "xb\007stumaxh\007stumaxl\010stumaxlb\010stumaxlh\006stumin\007stuminb\007"
    7412             :     "stuminh\007stuminl\010stuminlb\010stuminlh\004stur\005sturb\005sturh\004"
    7413             :     "stxp\004stxr\005stxrb\005stxrh\003sub\005subhn\006subhn2\004subs\006suq"
    7414             :     "add\003svc\003swp\004swpa\005swpab\005swpah\005swpal\006swpalb\006swpal"
    7415             :     "h\004swpb\004swph\004swpl\005swplb\005swplh\004sxtb\004sxth\004sxtl\005"
    7416             :     "sxtl2\004sxtw\003sys\004sysl\003tbl\004tbnz\003tbx\003tbz\004trn1\004tr"
    7417             :     "n2\003tst\004uaba\005uabal\006uabal2\004uabd\005uabdl\006uabdl2\006uada"
    7418             :     "lp\005uaddl\006uaddl2\006uaddlp\006uaddlv\005uaddw\006uaddw2\004ubfm\005"
    7419             :     "ucvtf\004udiv\004udot\005uhadd\005uhsub\006umaddl\004umax\005umaxp\005u"
    7420             :     "maxv\004umin\005uminp\005uminv\005umlal\006umlal2\005umlsl\006umlsl2\006"
    7421             :     "umnegl\004umov\006umsubl\005umulh\005umull\006umull2\005uqadd\006uqrshl"
    7422             :     "\007uqrshrn\010uqrshrn2\005uqshl\006uqshrn\007uqshrn2\005uqsub\005uqxtn"
    7423             :     "\006uqxtn2\006urecpe\006urhadd\005urshl\005urshr\007ursqrte\005ursra\004"
    7424             :     "ushl\005ushll\006ushll2\004ushr\006usqadd\004usra\005usubl\006usubl2\005"
    7425             :     "usubw\006usubw2\004uxtb\004uxth\004uxtl\005uxtl2\004uxtw\004uzp1\004uzp"
    7426             :     "2\003wfe\003wfi\005xpacd\005xpaci\007xpaclri\003xtn\004xtn2\005yield\004"
    7427             :     "zip1\004zip2";
    7428             : 
    7429             : namespace {
    7430             :   struct MatchEntry {
    7431             :     uint16_t Mnemonic;
    7432             :     uint16_t Opcode;
    7433             :     uint16_t ConvertFn;
    7434             :     uint32_t RequiredFeatures;
    7435             :     uint16_t Classes[8];
    7436             :     StringRef getMnemonic() const {
    7437      552640 :       return StringRef(MnemonicTable + Mnemonic + 1,
    7438      552640 :                        MnemonicTable[Mnemonic]);
    7439             :     }
    7440             :   };
    7441             : 
    7442             :   // Predicate for searching for an opcode.
    7443             :   struct LessOpcode {
    7444             :     bool operator()(const MatchEntry &LHS, StringRef RHS) {
    7445      634702 :       return LHS.getMnemonic() < RHS;
    7446             :     }
    7447             :     bool operator()(StringRef LHS, const MatchEntry &RHS) {
    7448      438782 :       return LHS < RHS.getMnemonic();
    7449             :     }
    7450             :     bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
    7451             :       return LHS.getMnemonic() < RHS.getMnemonic();
    7452             :     }
    7453             :   };
    7454             : } // end anonymous namespace.
    7455             : 
    7456             : static const MatchEntry MatchTable0[] = {
    7457             :   { 0 /* abs */, AArch64::ABSv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    7458             :   { 0 /* abs */, AArch64::ABSv16i8, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7459             :   { 0 /* abs */, AArch64::ABSv2i64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7460             :   { 0 /* abs */, AArch64::ABSv4i32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7461             :   { 0 /* abs */, AArch64::ABSv8i16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7462             :   { 0 /* abs */, AArch64::ABSv2i32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7463             :   { 0 /* abs */, AArch64::ABSv4i16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7464             :   { 0 /* abs */, AArch64::ABSv8i8, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7465             :   { 4 /* adc */, AArch64::ADCWr, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7466             :   { 4 /* adc */, AArch64::ADCXr, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7467             :   { 8 /* adcs */, AArch64::ADCSWr, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7468             :   { 8 /* adcs */, AArch64::ADCSXr, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7469             :   { 13 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, 0, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
    7470             :   { 13 /* add */, AArch64::ADDXrx64, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24, 0, { MCK_GPR64sponly, MCK_GPR64sp, MCK_GPR64 }, },
    7471             :   { 13 /* add */, AArch64::ADDv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7472             :   { 13 /* add */, AArch64::ADDWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7473             :   { 13 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, 0, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
    7474             :   { 13 /* add */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, Feature_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
    7475             :   { 13 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, 0, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
    7476             :   { 13 /* add */, AArch64::ADDXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7477             :   { 13 /* add */, AArch64::ADDXrx64, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24, 0, { MCK_GPR64sp, MCK_GPR64sponly, MCK_GPR64 }, },
    7478             :   { 13 /* add */, AArch64::SUBXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, Feature_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImmNeg }, },
    7479             :   { 13 /* add */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, 0, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImm }, },
    7480             :   { 13 /* add */, AArch64::ADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, Feature_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
    7481             :   { 13 /* add */, AArch64::ADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, Feature_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
    7482             :   { 13 /* add */, AArch64::ADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, Feature_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
    7483             :   { 13 /* add */, AArch64::ADD_ZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2, Feature_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEVectorBReg }, },
    7484             :   { 13 /* add */, AArch64::ADDWrs, Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
    7485             :   { 13 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, 0, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
    7486             :   { 13 /* add */, AArch64::ADDXrs, Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
    7487             :   { 13 /* add */, AArch64::ADDXrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend641_3, 0, { MCK_GPR64sp, MCK_GPR64sp, MCK_GPR32, MCK_Extend64 }, },
    7488             :   { 13 /* add */, AArch64::ADDXrx64, Convert__Reg1_0__Reg1_1__Reg1_2__ExtendLSL641_3, 0, { MCK_GPR64sp, MCK_GPR64sp, MCK_GPR64, MCK_ExtendLSL64 }, },
    7489             :   { 13 /* add */, AArch64::ADDv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7490             :   { 13 /* add */, AArch64::ADDv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7491             :   { 13 /* add */, AArch64::ADDv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7492             :   { 13 /* add */, AArch64::ADDv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7493             :   { 13 /* add */, AArch64::ADDv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7494             :   { 13 /* add */, AArch64::ADDv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7495             :   { 13 /* add */, AArch64::ADDv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7496             :   { 13 /* add */, AArch64::ADD_ZPmZ_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5, Feature_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
    7497             :   { 13 /* add */, AArch64::ADD_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5, Feature_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
    7498             :   { 13 /* add */, AArch64::ADD_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5, Feature_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
    7499             :   { 13 /* add */, AArch64::ADD_ZPmZ_B, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorBReg1_5, Feature_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorBReg, MCK_SVEVectorBReg }, },
    7500             :   { 17 /* addhn */, AArch64::ADDHNv2i64_v2i32, Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7501             :   { 17 /* addhn */, AArch64::ADDHNv4i32_v4i16, Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7502             :   { 17 /* addhn */, AArch64::ADDHNv8i16_v8i8, Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7503             :   { 23 /* addhn2 */, AArch64::ADDHNv8i16_v16i8, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7504             :   { 23 /* addhn2 */, AArch64::ADDHNv2i64_v4i32, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7505             :   { 23 /* addhn2 */, AArch64::ADDHNv4i32_v8i16, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7506             :   { 30 /* addp */, AArch64::ADDPv2i64p, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_2d }, },
    7507             :   { 30 /* addp */, AArch64::ADDPv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7508             :   { 30 /* addp */, AArch64::ADDPv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7509             :   { 30 /* addp */, AArch64::ADDPv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7510             :   { 30 /* addp */, AArch64::ADDPv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7511             :   { 30 /* addp */, AArch64::ADDPv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7512             :   { 30 /* addp */, AArch64::ADDPv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7513             :   { 30 /* addp */, AArch64::ADDPv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7514             :   { 35 /* addpl */, AArch64::ADDPL_XXI, Convert__Reg1_0__Reg1_1__SImm61_2, Feature_HasSVE, { MCK_GPR64sp, MCK_GPR64sp, MCK_SImm6 }, },
    7515             :   { 41 /* adds */, AArch64::ADDSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, 0, { MCK_GPR32, MCK_GPR32sponly, MCK_GPR32 }, },
    7516             :   { 41 /* adds */, AArch64::ADDSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7517             :   { 41 /* adds */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, Feature_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
    7518             :   { 41 /* adds */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, 0, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
    7519             :   { 41 /* adds */, AArch64::ADDSXrx64, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24, 0, { MCK_GPR64, MCK_GPR64sponly, MCK_GPR64 }, },
    7520             :   { 41 /* adds */, AArch64::ADDSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7521             :   { 41 /* adds */, AArch64::SUBSXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, Feature_UseNegativeImmediates, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImmNeg }, },
    7522             :   { 41 /* adds */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, 0, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImm }, },
    7523             :   { 41 /* adds */, AArch64::ADDSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
    7524             :   { 41 /* adds */, AArch64::ADDSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, 0, { MCK_GPR32, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
    7525             :   { 41 /* adds */, AArch64::ADDSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
    7526             :   { 41 /* adds */, AArch64::ADDSXrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, 0, { MCK_GPR64, MCK_GPR64sp, MCK_GPR32, MCK_Extend }, },
    7527             :   { 41 /* adds */, AArch64::ADDSXrx64, Convert__Reg1_0__Reg1_1__Reg1_2__ExtendLSL641_3, 0, { MCK_GPR64, MCK_GPR64sp, MCK_GPR64, MCK_ExtendLSL64 }, },
    7528             :   { 46 /* addv */, AArch64::ADDVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
    7529             :   { 46 /* addv */, AArch64::ADDVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_4h }, },
    7530             :   { 46 /* addv */, AArch64::ADDVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
    7531             :   { 46 /* addv */, AArch64::ADDVv16i8v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR8, MCK_VectorReg128, MCK__DOT_16b }, },
    7532             :   { 46 /* addv */, AArch64::ADDVv8i8v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_FPR8, MCK_VectorReg64, MCK__DOT_8b }, },
    7533             :   { 51 /* addvl */, AArch64::ADDVL_XXI, Convert__Reg1_0__Reg1_1__SImm61_2, Feature_HasSVE, { MCK_GPR64sp, MCK_GPR64sp, MCK_SImm6 }, },
    7534             :   { 57 /* adr */, AArch64::ADR, Convert__Reg1_0__AdrLabel1_1, 0, { MCK_GPR64, MCK_AdrLabel }, },
    7535             :   { 61 /* adrp */, AArch64::ADRP, Convert__Reg1_0__AdrpLabel1_1, 0, { MCK_GPR64, MCK_AdrpLabel }, },
    7536             :   { 66 /* aesd */, AArch64::AESDrr, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2, Feature_HasCrypto, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7537             :   { 71 /* aese */, AArch64::AESErr, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2, Feature_HasCrypto, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7538             :   { 76 /* aesimc */, AArch64::AESIMCrr, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasCrypto, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7539             :   { 83 /* aesmc */, AArch64::AESMCrr, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasCrypto, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7540             :   { 89 /* and */, AArch64::ANDWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7541             :   { 89 /* and */, AArch64::ANDWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, 0, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32 }, },
    7542             :   { 89 /* and */, AArch64::ANDXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7543             :   { 89 /* and */, AArch64::ANDXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, 0, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64 }, },
    7544             :   { 89 /* and */, AArch64::AND_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2, Feature_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
    7545             :   { 89 /* and */, AArch64::AND_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2, Feature_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
    7546             :   { 89 /* and */, AArch64::AND_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, Feature_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
    7547             :   { 89 /* and */, AArch64::AND_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2, Feature_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
    7548             :   { 89 /* and */, AArch64::ANDWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
    7549             :   { 89 /* and */, AArch64::ANDXrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_LogicalShifter64 }, },
    7550             :   { 89 /* and */, AArch64::ANDv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7551             :   { 89 /* and */, AArch64::ANDv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7552             :   { 93 /* ands */, AArch64::ANDSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7553             :   { 93 /* ands */, AArch64::ANDSWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, 0, { MCK_GPR32, MCK_GPR32, MCK_LogicalImm32 }, },
    7554             :   { 93 /* ands */, AArch64::ANDSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7555             :   { 93 /* ands */, AArch64::ANDSXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, 0, { MCK_GPR64, MCK_GPR64, MCK_LogicalImm64 }, },
    7556             :   { 93 /* ands */, AArch64::ANDSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
    7557             :   { 93 /* ands */, AArch64::ANDSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_LogicalShifter64 }, },
    7558             :   { 98 /* asr */, AArch64::ASRVWr, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7559             :   { 98 /* asr */, AArch64::SBFMWri, Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31, 0, { MCK_GPR32, MCK_GPR32, MCK_Imm0_31 }, },
    7560             :   { 98 /* asr */, AArch64::ASRVXr, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7561             :   { 98 /* asr */, AArch64::SBFMXri, Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63, 0, { MCK_GPR64, MCK_GPR64, MCK_Imm0_63 }, },
    7562             :   { 102 /* asrv */, AArch64::ASRVWr, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7563             :   { 102 /* asrv */, AArch64::ASRVXr, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7564             :   { 107 /* autda */, AArch64::AUTDA, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a, { MCK_GPR64, MCK_GPR64sp }, },
    7565             :   { 113 /* autdb */, AArch64::AUTDB, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a, { MCK_GPR64, MCK_GPR64sp }, },
    7566             :   { 119 /* autdza */, AArch64::AUTDZA, Convert__Reg1_0, Feature_HasV8_3a, { MCK_GPR64 }, },
    7567             :   { 126 /* autdzb */, AArch64::AUTDZB, Convert__Reg1_0, Feature_HasV8_3a, { MCK_GPR64 }, },
    7568             :   { 133 /* autia */, AArch64::AUTIA, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a, { MCK_GPR64, MCK_GPR64sp }, },
    7569             :   { 139 /* autia1716 */, AArch64::AUTIA1716, Convert_NoOperands, Feature_HasV8_3a, {  }, },
    7570             :   { 149 /* autiasp */, AArch64::AUTIASP, Convert_NoOperands, Feature_HasV8_3a, {  }, },
    7571             :   { 157 /* autiaz */, AArch64::AUTIAZ, Convert_NoOperands, Feature_HasV8_3a, {  }, },
    7572             :   { 164 /* autib */, AArch64::AUTIB, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a, { MCK_GPR64, MCK_GPR64sp }, },
    7573             :   { 170 /* autib1716 */, AArch64::AUTIB1716, Convert_NoOperands, Feature_HasV8_3a, {  }, },
    7574             :   { 180 /* autibsp */, AArch64::AUTIBSP, Convert_NoOperands, Feature_HasV8_3a, {  }, },
    7575             :   { 188 /* autibz */, AArch64::AUTIBZ, Convert_NoOperands, Feature_HasV8_3a, {  }, },
    7576             :   { 195 /* autiza */, AArch64::AUTIZA, Convert__Reg1_0, Feature_HasV8_3a, { MCK_GPR64 }, },
    7577             :   { 202 /* autizb */, AArch64::AUTIZB, Convert__Reg1_0, Feature_HasV8_3a, { MCK_GPR64 }, },
    7578             :   { 209 /* b */, AArch64::B, Convert__BranchTarget261_0, 0, { MCK_BranchTarget26 }, },
    7579             :   { 209 /* b */, AArch64::Bcc, Convert__CondCode1_1__PCRelLabel191_2, 0, { MCK__DOT_, MCK_CondCode, MCK_PCRelLabel19 }, },
    7580             :   { 211 /* bfm */, AArch64::BFMWri, Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_311_2__Imm0_311_3, 0, { MCK_GPR32, MCK_GPR32, MCK_Imm0_31, MCK_Imm0_31 }, },
    7581             :   { 211 /* bfm */, AArch64::BFMXri, Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2__Imm0_631_3, 0, { MCK_GPR64, MCK_GPR64, MCK_Imm0_63, MCK_Imm0_63 }, },
    7582             :   { 215 /* bic */, AArch64::BICv2i32, Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__imm_95_0, 0, { MCK__DOT_2s, MCK_VectorReg64, MCK_Imm0_255 }, },
    7583             :   { 215 /* bic */, AArch64::BICv4i16, Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__imm_95_0, 0, { MCK__DOT_4h, MCK_VectorReg64, MCK_Imm0_255 }, },
    7584             :   { 215 /* bic */, AArch64::BICv4i32, Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__imm_95_0, 0, { MCK__DOT_4s, MCK_VectorReg128, MCK_Imm0_255 }, },
    7585             :   { 215 /* bic */, AArch64::BICv8i16, Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__imm_95_0, 0, { MCK__DOT_8h, MCK_VectorReg128, MCK_Imm0_255 }, },
    7586             :   { 215 /* bic */, AArch64::BICWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7587             :   { 215 /* bic */, AArch64::ANDWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, Feature_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32Not }, },
    7588             :   { 215 /* bic */, AArch64::BICXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7589             :   { 215 /* bic */, AArch64::ANDXri, Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2, Feature_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64Not }, },
    7590             :   { 215 /* bic */, AArch64::BICv4i32, Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__imm_95_0, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_Imm0_255 }, },
    7591             :   { 215 /* bic */, AArch64::BICv8i16, Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__imm_95_0, 0, { MCK_VectorReg128, MCK__DOT_8h, MCK_Imm0_255 }, },
    7592             :   { 215 /* bic */, AArch64::BICv2i32, Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__imm_95_0, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_Imm0_255 }, },
    7593             :   { 215 /* bic */, AArch64::BICv4i16, Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__imm_95_0, 0, { MCK_VectorReg64, MCK__DOT_4h, MCK_Imm0_255 }, },
    7594             :   { 215 /* bic */, AArch64::AND_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2, Feature_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16Not }, },
    7595             :   { 215 /* bic */, AArch64::AND_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2, Feature_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32Not }, },
    7596             :   { 215 /* bic */, AArch64::AND_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2, Feature_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64Not }, },
    7597             :   { 215 /* bic */, AArch64::AND_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2, Feature_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8Not }, },
    7598             :   { 215 /* bic */, AArch64::BICWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
    7599             :   { 215 /* bic */, AArch64::BICXrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_LogicalShifter64 }, },
    7600             :   { 215 /* bic */, AArch64::BICv4i32, Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_Imm0_255, MCK_LogicalVecShifter }, },
    7601             :   { 215 /* bic */, AArch64::BICv8i16, Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_Imm0_255, MCK_LogicalVecHalfWordShifter }, },
    7602             :   { 215 /* bic */, AArch64::BICv2i32, Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_Imm0_255, MCK_LogicalVecShifter }, },
    7603             :   { 215 /* bic */, AArch64::BICv4i16, Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_Imm0_255, MCK_LogicalVecHalfWordShifter }, },
    7604             :   { 215 /* bic */, AArch64::BICv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7605             :   { 215 /* bic */, AArch64::BICv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7606             :   { 219 /* bics */, AArch64::BICSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7607             :   { 219 /* bics */, AArch64::ANDSWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, Feature_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32, MCK_LogicalImm32Not }, },
    7608             :   { 219 /* bics */, AArch64::BICSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7609             :   { 219 /* bics */, AArch64::ANDSXri, Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2, Feature_UseNegativeImmediates, { MCK_GPR64, MCK_GPR64, MCK_LogicalImm64Not }, },
    7610             :   { 219 /* bics */, AArch64::BICSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
    7611             :   { 219 /* bics */, AArch64::BICSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_LogicalShifter64 }, },
    7612             :   { 224 /* bif */, AArch64::BIFv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7613             :   { 224 /* bif */, AArch64::BIFv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7614             :   { 228 /* bit */, AArch64::BITv16i8, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7615             :   { 228 /* bit */, AArch64::BITv8i8, Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7616             :   { 232 /* bl */, AArch64::BL, Convert__BranchTarget261_0, 0, { MCK_BranchTarget26 }, },
    7617             :   { 235 /* blr */, AArch64::BLR, Convert__Reg1_0, 0, { MCK_GPR64 }, },
    7618             :   { 239 /* blraa */, AArch64::BLRAA, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a, { MCK_GPR64, MCK_GPR64sp }, },
    7619             :   { 245 /* blraaz */, AArch64::BLRAAZ, Convert__Reg1_0, Feature_HasV8_3a, { MCK_GPR64 }, },
    7620             :   { 252 /* blrab */, AArch64::BLRAB, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a, { MCK_GPR64, MCK_GPR64sp }, },
    7621             :   { 258 /* blrabz */, AArch64::BLRABZ, Convert__Reg1_0, Feature_HasV8_3a, { MCK_GPR64 }, },
    7622             :   { 265 /* br */, AArch64::BR, Convert__Reg1_0, 0, { MCK_GPR64 }, },
    7623             :   { 268 /* braa */, AArch64::BRAA, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a, { MCK_GPR64, MCK_GPR64sp }, },
    7624             :   { 273 /* braaz */, AArch64::BRAAZ, Convert__Reg1_0, Feature_HasV8_3a, { MCK_GPR64 }, },
    7625             :   { 279 /* brab */, AArch64::BRAB, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a, { MCK_GPR64, MCK_GPR64sp }, },
    7626             :   { 284 /* brabz */, AArch64::BRABZ, Convert__Reg1_0, Feature_HasV8_3a, { MCK_GPR64 }, },
    7627             :   { 290 /* brk */, AArch64::BRK, Convert__Imm0_655351_0, 0, { MCK_Imm0_65535 }, },
    7628             :   { 294 /* bsl */, AArch64::BSLv16i8, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7629             :   { 294 /* bsl */, AArch64::BSLv8i8, Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7630             :   { 298 /* cas */, AArch64::CASW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7631             :   { 298 /* cas */, AArch64::CASX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7632             :   { 302 /* casa */, AArch64::CASAW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7633             :   { 302 /* casa */, AArch64::CASAX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7634             :   { 307 /* casab */, AArch64::CASAB, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7635             :   { 313 /* casah */, AArch64::CASAH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7636             :   { 319 /* casal */, AArch64::CASALW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7637             :   { 319 /* casal */, AArch64::CASALX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7638             :   { 325 /* casalb */, AArch64::CASALB, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7639             :   { 332 /* casalh */, AArch64::CASALH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7640             :   { 339 /* casb */, AArch64::CASB, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7641             :   { 344 /* cash */, AArch64::CASH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7642             :   { 349 /* casl */, AArch64::CASLW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7643             :   { 349 /* casl */, AArch64::CASLX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7644             :   { 354 /* caslb */, AArch64::CASLB, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7645             :   { 360 /* caslh */, AArch64::CASLH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3, Feature_HasLSE, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7646             :   { 366 /* casp */, AArch64::CASPW, Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3, Feature_HasLSE, { MCK_WSeqPair, MCK_WSeqPair, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7647             :   { 366 /* casp */, AArch64::CASPX, Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3, Feature_HasLSE, { MCK_XSeqPair, MCK_XSeqPair, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7648             :   { 371 /* caspa */, AArch64::CASPAW, Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3, Feature_HasLSE, { MCK_WSeqPair, MCK_WSeqPair, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7649             :   { 371 /* caspa */, AArch64::CASPAX, Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3, Feature_HasLSE, { MCK_XSeqPair, MCK_XSeqPair, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7650             :   { 377 /* caspal */, AArch64::CASPALW, Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3, Feature_HasLSE, { MCK_WSeqPair, MCK_WSeqPair, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7651             :   { 377 /* caspal */, AArch64::CASPALX, Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3, Feature_HasLSE, { MCK_XSeqPair, MCK_XSeqPair, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7652             :   { 384 /* caspl */, AArch64::CASPLW, Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3, Feature_HasLSE, { MCK_WSeqPair, MCK_WSeqPair, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7653             :   { 384 /* caspl */, AArch64::CASPLX, Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3, Feature_HasLSE, { MCK_XSeqPair, MCK_XSeqPair, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
    7654             :   { 390 /* cbnz */, AArch64::CBNZW, Convert__Reg1_0__PCRelLabel191_1, 0, { MCK_GPR32, MCK_PCRelLabel19 }, },
    7655             :   { 390 /* cbnz */, AArch64::CBNZX, Convert__Reg1_0__PCRelLabel191_1, 0, { MCK_GPR64, MCK_PCRelLabel19 }, },
    7656             :   { 395 /* cbz */, AArch64::CBZW, Convert__Reg1_0__PCRelLabel191_1, 0, { MCK_GPR32, MCK_PCRelLabel19 }, },
    7657             :   { 395 /* cbz */, AArch64::CBZX, Convert__Reg1_0__PCRelLabel191_1, 0, { MCK_GPR64, MCK_PCRelLabel19 }, },
    7658             :   { 399 /* ccmn */, AArch64::CCMNWr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, 0, { MCK_GPR32, MCK_GPR32, MCK_Imm0_15, MCK_CondCode }, },
    7659             :   { 399 /* ccmn */, AArch64::CCMNWi, Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3, 0, { MCK_GPR32, MCK_Imm0_31, MCK_Imm0_15, MCK_CondCode }, },
    7660             :   { 399 /* ccmn */, AArch64::CCMNXr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, 0, { MCK_GPR64, MCK_GPR64, MCK_Imm0_15, MCK_CondCode }, },
    7661             :   { 399 /* ccmn */, AArch64::CCMNXi, Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3, 0, { MCK_GPR64, MCK_Imm0_31, MCK_Imm0_15, MCK_CondCode }, },
    7662             :   { 404 /* ccmp */, AArch64::CCMPWr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, 0, { MCK_GPR32, MCK_GPR32, MCK_Imm0_15, MCK_CondCode }, },
    7663             :   { 404 /* ccmp */, AArch64::CCMPWi, Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3, 0, { MCK_GPR32, MCK_Imm0_31, MCK_Imm0_15, MCK_CondCode }, },
    7664             :   { 404 /* ccmp */, AArch64::CCMPXr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, 0, { MCK_GPR64, MCK_GPR64, MCK_Imm0_15, MCK_CondCode }, },
    7665             :   { 404 /* ccmp */, AArch64::CCMPXi, Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3, 0, { MCK_GPR64, MCK_Imm0_31, MCK_Imm0_15, MCK_CondCode }, },
    7666             :   { 409 /* cinc */, AArch64::CSINCWr, Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2, 0, { MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
    7667             :   { 409 /* cinc */, AArch64::CSINCXr, Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2, 0, { MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
    7668             :   { 414 /* cinv */, AArch64::CSINVWr, Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2, 0, { MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
    7669             :   { 414 /* cinv */, AArch64::CSINVXr, Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2, 0, { MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
    7670             :   { 419 /* clrex */, AArch64::CLREX, Convert__imm_95_15, 0, {  }, },
    7671             :   { 419 /* clrex */, AArch64::CLREX, Convert__Imm0_151_0, 0, { MCK_Imm0_15 }, },
    7672             :   { 425 /* cls */, AArch64::CLSWr, Convert__Reg1_0__Reg1_1, 0, { MCK_GPR32, MCK_GPR32 }, },
    7673             :   { 425 /* cls */, AArch64::CLSXr, Convert__Reg1_0__Reg1_1, 0, { MCK_GPR64, MCK_GPR64 }, },
    7674             :   { 425 /* cls */, AArch64::CLSv16i8, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7675             :   { 425 /* cls */, AArch64::CLSv4i32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7676             :   { 425 /* cls */, AArch64::CLSv8i16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7677             :   { 425 /* cls */, AArch64::CLSv2i32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7678             :   { 425 /* cls */, AArch64::CLSv4i16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7679             :   { 425 /* cls */, AArch64::CLSv8i8, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7680             :   { 429 /* clz */, AArch64::CLZWr, Convert__Reg1_0__Reg1_1, 0, { MCK_GPR32, MCK_GPR32 }, },
    7681             :   { 429 /* clz */, AArch64::CLZXr, Convert__Reg1_0__Reg1_1, 0, { MCK_GPR64, MCK_GPR64 }, },
    7682             :   { 429 /* clz */, AArch64::CLZv16i8, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7683             :   { 429 /* clz */, AArch64::CLZv4i32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7684             :   { 429 /* clz */, AArch64::CLZv8i16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7685             :   { 429 /* clz */, AArch64::CLZv2i32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7686             :   { 429 /* clz */, AArch64::CLZv4i16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7687             :   { 429 /* clz */, AArch64::CLZv8i8, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7688             :   { 433 /* cmeq */, AArch64::CMEQv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    7689             :   { 433 /* cmeq */, AArch64::CMEQv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7690             :   { 433 /* cmeq */, AArch64::CMEQv16i8rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK__35_0 }, },
    7691             :   { 433 /* cmeq */, AArch64::CMEQv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    7692             :   { 433 /* cmeq */, AArch64::CMEQv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    7693             :   { 433 /* cmeq */, AArch64::CMEQv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    7694             :   { 433 /* cmeq */, AArch64::CMEQv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    7695             :   { 433 /* cmeq */, AArch64::CMEQv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    7696             :   { 433 /* cmeq */, AArch64::CMEQv8i8rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK__35_0 }, },
    7697             :   { 433 /* cmeq */, AArch64::CMEQv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7698             :   { 433 /* cmeq */, AArch64::CMEQv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7699             :   { 433 /* cmeq */, AArch64::CMEQv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7700             :   { 433 /* cmeq */, AArch64::CMEQv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7701             :   { 433 /* cmeq */, AArch64::CMEQv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7702             :   { 433 /* cmeq */, AArch64::CMEQv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7703             :   { 433 /* cmeq */, AArch64::CMEQv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7704             :   { 438 /* cmge */, AArch64::CMGEv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    7705             :   { 438 /* cmge */, AArch64::CMGEv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7706             :   { 438 /* cmge */, AArch64::CMGEv16i8rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK__35_0 }, },
    7707             :   { 438 /* cmge */, AArch64::CMGEv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    7708             :   { 438 /* cmge */, AArch64::CMGEv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    7709             :   { 438 /* cmge */, AArch64::CMGEv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    7710             :   { 438 /* cmge */, AArch64::CMGEv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    7711             :   { 438 /* cmge */, AArch64::CMGEv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    7712             :   { 438 /* cmge */, AArch64::CMGEv8i8rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK__35_0 }, },
    7713             :   { 438 /* cmge */, AArch64::CMGEv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7714             :   { 438 /* cmge */, AArch64::CMGEv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7715             :   { 438 /* cmge */, AArch64::CMGEv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7716             :   { 438 /* cmge */, AArch64::CMGEv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7717             :   { 438 /* cmge */, AArch64::CMGEv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7718             :   { 438 /* cmge */, AArch64::CMGEv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7719             :   { 438 /* cmge */, AArch64::CMGEv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7720             :   { 443 /* cmgt */, AArch64::CMGTv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    7721             :   { 443 /* cmgt */, AArch64::CMGTv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7722             :   { 443 /* cmgt */, AArch64::CMGTv16i8rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK__35_0 }, },
    7723             :   { 443 /* cmgt */, AArch64::CMGTv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    7724             :   { 443 /* cmgt */, AArch64::CMGTv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    7725             :   { 443 /* cmgt */, AArch64::CMGTv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    7726             :   { 443 /* cmgt */, AArch64::CMGTv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    7727             :   { 443 /* cmgt */, AArch64::CMGTv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    7728             :   { 443 /* cmgt */, AArch64::CMGTv8i8rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK__35_0 }, },
    7729             :   { 443 /* cmgt */, AArch64::CMGTv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7730             :   { 443 /* cmgt */, AArch64::CMGTv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7731             :   { 443 /* cmgt */, AArch64::CMGTv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7732             :   { 443 /* cmgt */, AArch64::CMGTv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7733             :   { 443 /* cmgt */, AArch64::CMGTv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7734             :   { 443 /* cmgt */, AArch64::CMGTv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7735             :   { 443 /* cmgt */, AArch64::CMGTv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7736             :   { 448 /* cmhi */, AArch64::CMHIv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7737             :   { 448 /* cmhi */, AArch64::CMHIv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7738             :   { 448 /* cmhi */, AArch64::CMHIv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7739             :   { 448 /* cmhi */, AArch64::CMHIv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7740             :   { 448 /* cmhi */, AArch64::CMHIv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7741             :   { 448 /* cmhi */, AArch64::CMHIv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7742             :   { 448 /* cmhi */, AArch64::CMHIv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7743             :   { 448 /* cmhi */, AArch64::CMHIv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7744             :   { 453 /* cmhs */, AArch64::CMHSv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7745             :   { 453 /* cmhs */, AArch64::CMHSv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7746             :   { 453 /* cmhs */, AArch64::CMHSv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7747             :   { 453 /* cmhs */, AArch64::CMHSv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7748             :   { 453 /* cmhs */, AArch64::CMHSv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7749             :   { 453 /* cmhs */, AArch64::CMHSv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7750             :   { 453 /* cmhs */, AArch64::CMHSv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7751             :   { 453 /* cmhs */, AArch64::CMHSv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7752             :   { 458 /* cmle */, AArch64::CMLEv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    7753             :   { 458 /* cmle */, AArch64::CMGEv1i64, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7754             :   { 458 /* cmle */, AArch64::CMLEv16i8rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK__35_0 }, },
    7755             :   { 458 /* cmle */, AArch64::CMLEv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    7756             :   { 458 /* cmle */, AArch64::CMLEv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    7757             :   { 458 /* cmle */, AArch64::CMLEv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    7758             :   { 458 /* cmle */, AArch64::CMLEv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    7759             :   { 458 /* cmle */, AArch64::CMLEv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    7760             :   { 458 /* cmle */, AArch64::CMLEv8i8rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK__35_0 }, },
    7761             :   { 458 /* cmle */, AArch64::CMGEv16i8, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7762             :   { 458 /* cmle */, AArch64::CMGEv2i64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7763             :   { 458 /* cmle */, AArch64::CMGEv4i32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7764             :   { 458 /* cmle */, AArch64::CMGEv8i16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7765             :   { 458 /* cmle */, AArch64::CMGEv2i32, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7766             :   { 458 /* cmle */, AArch64::CMGEv4i16, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7767             :   { 458 /* cmle */, AArch64::CMGEv8i8, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7768             :   { 463 /* cmlo */, AArch64::CMHIv1i64, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7769             :   { 463 /* cmlo */, AArch64::CMHIv16i8, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7770             :   { 463 /* cmlo */, AArch64::CMHIv2i64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7771             :   { 463 /* cmlo */, AArch64::CMHIv4i32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7772             :   { 463 /* cmlo */, AArch64::CMHIv8i16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7773             :   { 463 /* cmlo */, AArch64::CMHIv2i32, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7774             :   { 463 /* cmlo */, AArch64::CMHIv4i16, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7775             :   { 463 /* cmlo */, AArch64::CMHIv8i8, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7776             :   { 468 /* cmls */, AArch64::CMHSv1i64, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7777             :   { 468 /* cmls */, AArch64::CMHSv16i8, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7778             :   { 468 /* cmls */, AArch64::CMHSv2i64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7779             :   { 468 /* cmls */, AArch64::CMHSv4i32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7780             :   { 468 /* cmls */, AArch64::CMHSv8i16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7781             :   { 468 /* cmls */, AArch64::CMHSv2i32, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7782             :   { 468 /* cmls */, AArch64::CMHSv4i16, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7783             :   { 468 /* cmls */, AArch64::CMHSv8i8, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7784             :   { 473 /* cmlt */, AArch64::CMLTv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    7785             :   { 473 /* cmlt */, AArch64::CMGTv1i64, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7786             :   { 473 /* cmlt */, AArch64::CMLTv16i8rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK__35_0 }, },
    7787             :   { 473 /* cmlt */, AArch64::CMLTv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    7788             :   { 473 /* cmlt */, AArch64::CMLTv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    7789             :   { 473 /* cmlt */, AArch64::CMLTv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    7790             :   { 473 /* cmlt */, AArch64::CMLTv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    7791             :   { 473 /* cmlt */, AArch64::CMLTv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    7792             :   { 473 /* cmlt */, AArch64::CMLTv8i8rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK__35_0 }, },
    7793             :   { 473 /* cmlt */, AArch64::CMGTv16i8, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7794             :   { 473 /* cmlt */, AArch64::CMGTv2i64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7795             :   { 473 /* cmlt */, AArch64::CMGTv4i32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7796             :   { 473 /* cmlt */, AArch64::CMGTv8i16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7797             :   { 473 /* cmlt */, AArch64::CMGTv2i32, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7798             :   { 473 /* cmlt */, AArch64::CMGTv4i16, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7799             :   { 473 /* cmlt */, AArch64::CMGTv8i8, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7800             :   { 478 /* cmn */, AArch64::ADDSWrx, Convert__regWZR__Reg1_0__Reg1_1__imm_95_16, 0, { MCK_GPR32sponly, MCK_GPR32 }, },
    7801             :   { 478 /* cmn */, AArch64::ADDSXrx64, Convert__regXZR__Reg1_0__Reg1_1__imm_95_24, 0, { MCK_GPR64sponly, MCK_GPR64 }, },
    7802             :   { 478 /* cmn */, AArch64::ADDSWrs, Convert__regWZR__Reg1_0__Reg1_1__imm_95_0, 0, { MCK_GPR32, MCK_GPR32 }, },
    7803             :   { 478 /* cmn */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, Feature_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
    7804             :   { 478 /* cmn */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, 0, { MCK_GPR32sp, MCK_AddSubImm }, },
    7805             :   { 478 /* cmn */, AArch64::ADDSXrs, Convert__regXZR__Reg1_0__Reg1_1__imm_95_0, 0, { MCK_GPR64, MCK_GPR64 }, },
    7806             :   { 478 /* cmn */, AArch64::SUBSXri, Convert__regXZR__Reg1_0__AddSubImmNeg2_1, Feature_UseNegativeImmediates, { MCK_GPR64sp, MCK_AddSubImmNeg }, },
    7807             :   { 478 /* cmn */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImm2_1, 0, { MCK_GPR64sp, MCK_AddSubImm }, },
    7808             :   { 478 /* cmn */, AArch64::ADDSWrs, Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2, 0, { MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
    7809             :   { 478 /* cmn */, AArch64::ADDSWrx, Convert__regWZR__Reg1_0__Reg1_1__Extend1_2, 0, { MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
    7810             :   { 478 /* cmn */, AArch64::ADDSXrs, Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2, 0, { MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
    7811             :   { 478 /* cmn */, AArch64::ADDSXrx, Convert__regXZR__Reg1_0__Reg1_1__Extend1_2, 0, { MCK_GPR64sp, MCK_GPR32, MCK_Extend }, },
    7812             :   { 478 /* cmn */, AArch64::ADDSXrx64, Convert__regXZR__Reg1_0__Reg1_1__ExtendLSL641_2, 0, { MCK_GPR64sp, MCK_GPR64, MCK_ExtendLSL64 }, },
    7813             :   { 482 /* cmp */, AArch64::SUBSWrx, Convert__regWZR__Reg1_0__Reg1_1__imm_95_16, 0, { MCK_GPR32sponly, MCK_GPR32 }, },
    7814             :   { 482 /* cmp */, AArch64::SUBSXrx64, Convert__regXZR__Reg1_0__Reg1_1__imm_95_24, 0, { MCK_GPR64sponly, MCK_GPR64 }, },
    7815             :   { 482 /* cmp */, AArch64::SUBSWrs, Convert__regWZR__Reg1_0__Reg1_1__imm_95_0, 0, { MCK_GPR32, MCK_GPR32 }, },
    7816             :   { 482 /* cmp */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, Feature_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
    7817             :   { 482 /* cmp */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, 0, { MCK_GPR32sp, MCK_AddSubImm }, },
    7818             :   { 482 /* cmp */, AArch64::SUBSXrs, Convert__regXZR__Reg1_0__Reg1_1__imm_95_0, 0, { MCK_GPR64, MCK_GPR64 }, },
    7819             :   { 482 /* cmp */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImmNeg2_1, Feature_UseNegativeImmediates, { MCK_GPR64sp, MCK_AddSubImmNeg }, },
    7820             :   { 482 /* cmp */, AArch64::SUBSXri, Convert__regXZR__Reg1_0__AddSubImm2_1, 0, { MCK_GPR64sp, MCK_AddSubImm }, },
    7821             :   { 482 /* cmp */, AArch64::SUBSWrs, Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2, 0, { MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
    7822             :   { 482 /* cmp */, AArch64::SUBSWrx, Convert__regWZR__Reg1_0__Reg1_1__Extend1_2, 0, { MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
    7823             :   { 482 /* cmp */, AArch64::SUBSXrs, Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2, 0, { MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
    7824             :   { 482 /* cmp */, AArch64::SUBSXrx, Convert__regXZR__Reg1_0__Reg1_1__Extend1_2, 0, { MCK_GPR64sp, MCK_GPR32, MCK_Extend }, },
    7825             :   { 482 /* cmp */, AArch64::SUBSXrx64, Convert__regXZR__Reg1_0__Reg1_1__ExtendLSL641_2, 0, { MCK_GPR64sp, MCK_GPR64, MCK_ExtendLSL64 }, },
    7826             :   { 486 /* cmtst */, AArch64::CMTSTv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7827             :   { 486 /* cmtst */, AArch64::CMTSTv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7828             :   { 486 /* cmtst */, AArch64::CMTSTv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7829             :   { 486 /* cmtst */, AArch64::CMTSTv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7830             :   { 486 /* cmtst */, AArch64::CMTSTv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7831             :   { 486 /* cmtst */, AArch64::CMTSTv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7832             :   { 486 /* cmtst */, AArch64::CMTSTv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7833             :   { 486 /* cmtst */, AArch64::CMTSTv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7834             :   { 492 /* cneg */, AArch64::CSNEGWr, Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2, 0, { MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
    7835             :   { 492 /* cneg */, AArch64::CSNEGXr, Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2, 0, { MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
    7836             :   { 497 /* cnt */, AArch64::CNTv16i8, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7837             :   { 497 /* cnt */, AArch64::CNTv8i8, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7838             :   { 501 /* crc32b */, AArch64::CRC32Brr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasCRC, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7839             :   { 508 /* crc32cb */, AArch64::CRC32CBrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasCRC, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7840             :   { 516 /* crc32ch */, AArch64::CRC32CHrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasCRC, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7841             :   { 524 /* crc32cw */, AArch64::CRC32CWrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasCRC, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7842             :   { 532 /* crc32cx */, AArch64::CRC32CXrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasCRC, { MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
    7843             :   { 540 /* crc32h */, AArch64::CRC32Hrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasCRC, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7844             :   { 547 /* crc32w */, AArch64::CRC32Wrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasCRC, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7845             :   { 554 /* crc32x */, AArch64::CRC32Xrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasCRC, { MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
    7846             :   { 561 /* csdb */, AArch64::HINT, Convert__imm_95_20, 0, {  }, },
    7847             :   { 566 /* csel */, AArch64::CSELWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
    7848             :   { 566 /* csel */, AArch64::CSELXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
    7849             :   { 571 /* cset */, AArch64::CSINCWr, Convert__Reg1_0__regWZR__regWZR__CondCode1_1, 0, { MCK_GPR32, MCK_CondCode }, },
    7850             :   { 571 /* cset */, AArch64::CSINCXr, Convert__Reg1_0__regXZR__regXZR__CondCode1_1, 0, { MCK_GPR64, MCK_CondCode }, },
    7851             :   { 576 /* csetm */, AArch64::CSINVWr, Convert__Reg1_0__regWZR__regWZR__CondCode1_1, 0, { MCK_GPR32, MCK_CondCode }, },
    7852             :   { 576 /* csetm */, AArch64::CSINVXr, Convert__Reg1_0__regXZR__regXZR__CondCode1_1, 0, { MCK_GPR64, MCK_CondCode }, },
    7853             :   { 582 /* csinc */, AArch64::CSINCWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
    7854             :   { 582 /* csinc */, AArch64::CSINCXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
    7855             :   { 588 /* csinv */, AArch64::CSINVWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
    7856             :   { 588 /* csinv */, AArch64::CSINVXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
    7857             :   { 594 /* csneg */, AArch64::CSNEGWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
    7858             :   { 594 /* csneg */, AArch64::CSNEGXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
    7859             :   { 600 /* dcps1 */, AArch64::DCPS1, Convert__imm_95_0, 0, {  }, },
    7860             :   { 600 /* dcps1 */, AArch64::DCPS1, Convert__Imm0_655351_0, 0, { MCK_Imm0_65535 }, },
    7861             :   { 606 /* dcps2 */, AArch64::DCPS2, Convert__imm_95_0, 0, {  }, },
    7862             :   { 606 /* dcps2 */, AArch64::DCPS2, Convert__Imm0_655351_0, 0, { MCK_Imm0_65535 }, },
    7863             :   { 612 /* dcps3 */, AArch64::DCPS3, Convert__imm_95_0, 0, {  }, },
    7864             :   { 612 /* dcps3 */, AArch64::DCPS3, Convert__Imm0_655351_0, 0, { MCK_Imm0_65535 }, },
    7865             :   { 618 /* dmb */, AArch64::DMB, Convert__Barrier1_0, 0, { MCK_Barrier }, },
    7866             :   { 622 /* drps */, AArch64::DRPS, Convert_NoOperands, 0, {  }, },
    7867             :   { 627 /* dsb */, AArch64::DSB, Convert__Barrier1_0, 0, { MCK_Barrier }, },
    7868             :   { 631 /* dup */, AArch64::DUP_ZR_H, Convert__SVEVectorHReg1_0__Reg1_1, Feature_HasSVE, { MCK_SVEVectorHReg, MCK_GPR32sp }, },
    7869             :   { 631 /* dup */, AArch64::DUP_ZR_S, Convert__SVEVectorSReg1_0__Reg1_1, Feature_HasSVE, { MCK_SVEVectorSReg, MCK_GPR32sp }, },
    7870             :   { 631 /* dup */, AArch64::DUP_ZR_D, Convert__SVEVectorDReg1_0__Reg1_1, Feature_HasSVE, { MCK_SVEVectorDReg, MCK_GPR64sp }, },
    7871             :   { 631 /* dup */, AArch64::DUP_ZR_B, Convert__SVEVectorBReg1_0__Reg1_1, Feature_HasSVE, { MCK_SVEVectorBReg, MCK_GPR32sp }, },
    7872             :   { 631 /* dup */, AArch64::DUPv16i8gpr, Convert__VectorReg1281_0__Reg1_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_GPR32 }, },
    7873             :   { 631 /* dup */, AArch64::DUPv2i64gpr, Convert__VectorReg1281_0__Reg1_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_GPR64 }, },
    7874             :   { 631 /* dup */, AArch64::DUPv4i32gpr, Convert__VectorReg1281_0__Reg1_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_GPR32 }, },
    7875             :   { 631 /* dup */, AArch64::DUPv8i16gpr, Convert__VectorReg1281_0__Reg1_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_GPR32 }, },
    7876             :   { 631 /* dup */, AArch64::DUPv2i32gpr, Convert__VectorReg641_0__Reg1_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_GPR32 }, },
    7877             :   { 631 /* dup */, AArch64::DUPv4i16gpr, Convert__VectorReg641_0__Reg1_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_GPR32 }, },
    7878             :   { 631 /* dup */, AArch64::DUPv8i8gpr, Convert__VectorReg641_0__Reg1_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_GPR32 }, },
    7879             :   { 631 /* dup */, AArch64::CPYi16, Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_3, Feature_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_h, MCK_VectorIndexH }, },
    7880             :   { 631 /* dup */, AArch64::CPYi32, Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_3, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_s, MCK_VectorIndexS }, },
    7881             :   { 631 /* dup */, AArch64::CPYi64, Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_3, Feature_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_d, MCK_VectorIndexD }, },
    7882             :   { 631 /* dup */, AArch64::CPYi8, Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_3, Feature_HasNEON, { MCK_FPR8, MCK_VectorReg128, MCK__DOT_b, MCK_VectorIndexB }, },
    7883             :   { 631 /* dup */, AArch64::DUPv16i8lane, Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexB1_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_b, MCK_VectorIndexB }, },
    7884             :   { 631 /* dup */, AArch64::DUPv2i64lane, Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexD1_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_d, MCK_VectorIndexD }, },
    7885             :   { 631 /* dup */, AArch64::DUPv4i32lane, Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexS1_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_s, MCK_VectorIndexS }, },
    7886             :   { 631 /* dup */, AArch64::DUPv8i16lane, Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexH1_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_h, MCK_VectorIndexH }, },
    7887             :   { 631 /* dup */, AArch64::DUPv2i32lane, Convert__VectorReg641_0__VectorReg1281_2__VectorIndexS1_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg128, MCK__DOT_s, MCK_VectorIndexS }, },
    7888             :   { 631 /* dup */, AArch64::DUPv4i16lane, Convert__VectorReg641_0__VectorReg1281_2__VectorIndexH1_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg128, MCK__DOT_h, MCK_VectorIndexH }, },
    7889             :   { 631 /* dup */, AArch64::DUPv8i8lane, Convert__VectorReg641_0__VectorReg1281_2__VectorIndexB1_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg128, MCK__DOT_b, MCK_VectorIndexB }, },
    7890             :   { 635 /* eon */, AArch64::EONWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7891             :   { 635 /* eon */, AArch64::EORWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, Feature_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32Not }, },
    7892             :   { 635 /* eon */, AArch64::EONXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7893             :   { 635 /* eon */, AArch64::EORXri, Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2, Feature_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64Not }, },
    7894             :   { 635 /* eon */, AArch64::EONWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
    7895             :   { 635 /* eon */, AArch64::EONXrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_LogicalShifter64 }, },
    7896             :   { 639 /* eor */, AArch64::EORWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
    7897             :   { 639 /* eor */, AArch64::EORWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, 0, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32 }, },
    7898             :   { 639 /* eor */, AArch64::EORXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
    7899             :   { 639 /* eor */, AArch64::EORXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, 0, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64 }, },
    7900             :   { 639 /* eor */, AArch64::EORWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
    7901             :   { 639 /* eor */, AArch64::EORXrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_LogicalShifter64 }, },
    7902             :   { 639 /* eor */, AArch64::EORv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
    7903             :   { 639 /* eor */, AArch64::EORv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b }, },
    7904             :   { 643 /* eret */, AArch64::ERET, Convert_NoOperands, 0, {  }, },
    7905             :   { 648 /* eretaa */, AArch64::ERETAA, Convert_NoOperands, Feature_HasV8_3a, {  }, },
    7906             :   { 655 /* eretab */, AArch64::ERETAB, Convert_NoOperands, Feature_HasV8_3a, {  }, },
    7907             :   { 662 /* esb */, AArch64::HINT, Convert__imm_95_16, Feature_HasRAS, {  }, },
    7908             :   { 666 /* ext */, AArch64::EXTv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__Imm1_6, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_Imm }, },
    7909             :   { 666 /* ext */, AArch64::EXTv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__Imm1_6, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_VectorReg64, MCK__DOT_8b, MCK_Imm }, },
    7910             :   { 670 /* extr */, AArch64::EXTRWrri, Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_311_3, 0, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_Imm0_31 }, },
    7911             :   { 670 /* extr */, AArch64::EXTRXrri, Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_631_3, 0, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_Imm0_63 }, },
    7912             :   { 675 /* fabd */, AArch64::FABD16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    7913             :   { 675 /* fabd */, AArch64::FABD32, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    7914             :   { 675 /* fabd */, AArch64::FABD64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7915             :   { 675 /* fabd */, AArch64::FABDv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7916             :   { 675 /* fabd */, AArch64::FABDv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7917             :   { 675 /* fabd */, AArch64::FABDv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7918             :   { 675 /* fabd */, AArch64::FABDv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7919             :   { 675 /* fabd */, AArch64::FABDv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7920             :   { 680 /* fabs */, AArch64::FABSHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    7921             :   { 680 /* fabs */, AArch64::FABSSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32 }, },
    7922             :   { 680 /* fabs */, AArch64::FABSDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64 }, },
    7923             :   { 680 /* fabs */, AArch64::FABSv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7924             :   { 680 /* fabs */, AArch64::FABSv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7925             :   { 680 /* fabs */, AArch64::FABSv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7926             :   { 680 /* fabs */, AArch64::FABSv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7927             :   { 680 /* fabs */, AArch64::FABSv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7928             :   { 685 /* facge */, AArch64::FACGE16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    7929             :   { 685 /* facge */, AArch64::FACGE32, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    7930             :   { 685 /* facge */, AArch64::FACGE64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7931             :   { 685 /* facge */, AArch64::FACGEv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7932             :   { 685 /* facge */, AArch64::FACGEv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7933             :   { 685 /* facge */, AArch64::FACGEv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7934             :   { 685 /* facge */, AArch64::FACGEv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7935             :   { 685 /* facge */, AArch64::FACGEv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7936             :   { 691 /* facgt */, AArch64::FACGT16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    7937             :   { 691 /* facgt */, AArch64::FACGT32, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    7938             :   { 691 /* facgt */, AArch64::FACGT64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7939             :   { 691 /* facgt */, AArch64::FACGTv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7940             :   { 691 /* facgt */, AArch64::FACGTv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7941             :   { 691 /* facgt */, AArch64::FACGTv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7942             :   { 691 /* facgt */, AArch64::FACGTv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7943             :   { 691 /* facgt */, AArch64::FACGTv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7944             :   { 697 /* facle */, AArch64::FACGE32, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    7945             :   { 697 /* facle */, AArch64::FACGE64, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7946             :   { 697 /* facle */, AArch64::FACGEv2f64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7947             :   { 697 /* facle */, AArch64::FACGEv4f32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7948             :   { 697 /* facle */, AArch64::FACGEv8f16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7949             :   { 697 /* facle */, AArch64::FACGEv2f32, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7950             :   { 697 /* facle */, AArch64::FACGEv4f16, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7951             :   { 703 /* faclt */, AArch64::FACGT32, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    7952             :   { 703 /* faclt */, AArch64::FACGT64, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7953             :   { 703 /* faclt */, AArch64::FACGTv2f64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7954             :   { 703 /* faclt */, AArch64::FACGTv4f32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7955             :   { 703 /* faclt */, AArch64::FACGTv8f16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7956             :   { 703 /* faclt */, AArch64::FACGTv2f32, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7957             :   { 703 /* faclt */, AArch64::FACGTv4f16, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7958             :   { 709 /* fadd */, AArch64::FADDHrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    7959             :   { 709 /* fadd */, AArch64::FADDSrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    7960             :   { 709 /* fadd */, AArch64::FADDDrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7961             :   { 709 /* fadd */, AArch64::FADDv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7962             :   { 709 /* fadd */, AArch64::FADDv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7963             :   { 709 /* fadd */, AArch64::FADDv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7964             :   { 709 /* fadd */, AArch64::FADDv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7965             :   { 709 /* fadd */, AArch64::FADDv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7966             :   { 714 /* faddp */, AArch64::FADDPv2i16p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_2h }, },
    7967             :   { 714 /* faddp */, AArch64::FADDPv2i32p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg64, MCK__DOT_2s }, },
    7968             :   { 714 /* faddp */, AArch64::FADDPv2i64p, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_2d }, },
    7969             :   { 714 /* faddp */, AArch64::FADDPv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    7970             :   { 714 /* faddp */, AArch64::FADDPv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    7971             :   { 714 /* faddp */, AArch64::FADDPv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    7972             :   { 714 /* faddp */, AArch64::FADDPv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    7973             :   { 714 /* faddp */, AArch64::FADDPv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    7974             :   { 720 /* fcadd */, AArch64::FCADDv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6, Feature_HasV8_3a|Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_ComplexRotationOdd }, },
    7975             :   { 720 /* fcadd */, AArch64::FCADDv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6, Feature_HasV8_3a|Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_ComplexRotationOdd }, },
    7976             :   { 720 /* fcadd */, AArch64::FCADDv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6, Feature_HasV8_3a|Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_ComplexRotationOdd }, },
    7977             :   { 720 /* fcadd */, AArch64::FCADDv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__ComplexRotationOdd1_6, Feature_HasV8_3a|Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_ComplexRotationOdd }, },
    7978             :   { 720 /* fcadd */, AArch64::FCADDv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__ComplexRotationOdd1_6, Feature_HasV8_3a|Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_ComplexRotationOdd }, },
    7979             :   { 726 /* fccmp */, AArch64::FCCMPHrr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_Imm0_15, MCK_CondCode }, },
    7980             :   { 726 /* fccmp */, AArch64::FCCMPSrr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_Imm0_15, MCK_CondCode }, },
    7981             :   { 726 /* fccmp */, AArch64::FCCMPDrr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_Imm0_15, MCK_CondCode }, },
    7982             :   { 732 /* fccmpe */, AArch64::FCCMPEHrr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_Imm0_15, MCK_CondCode }, },
    7983             :   { 732 /* fccmpe */, AArch64::FCCMPESrr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_Imm0_15, MCK_CondCode }, },
    7984             :   { 732 /* fccmpe */, AArch64::FCCMPEDrr, Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_Imm0_15, MCK_CondCode }, },
    7985             :   { 739 /* fcmeq */, AArch64::FCMEQv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0 }, },
    7986             :   { 739 /* fcmeq */, AArch64::FCMEQ16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    7987             :   { 739 /* fcmeq */, AArch64::FCMEQv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0 }, },
    7988             :   { 739 /* fcmeq */, AArch64::FCMEQ32, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    7989             :   { 739 /* fcmeq */, AArch64::FCMEQv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    7990             :   { 739 /* fcmeq */, AArch64::FCMEQ64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    7991             :   { 739 /* fcmeq */, AArch64::FCMEQv2i64rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_2d, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    7992             :   { 739 /* fcmeq */, AArch64::FCMEQv2i32rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON, { MCK__DOT_2s, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    7993             :   { 739 /* fcmeq */, AArch64::FCMEQv4i16rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_4h, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    7994             :   { 739 /* fcmeq */, AArch64::FCMEQv4i32rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    7995             :   { 739 /* fcmeq */, AArch64::FCMEQv8i16rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    7996             :   { 739 /* fcmeq */, AArch64::FCMEQv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0, MCK__DOT_0 }, },
    7997             :   { 739 /* fcmeq */, AArch64::FCMEQv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0, MCK__DOT_0 }, },
    7998             :   { 739 /* fcmeq */, AArch64::FCMEQv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0, MCK__DOT_0 }, },
    7999             :   { 739 /* fcmeq */, AArch64::FCMEQv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    8000             :   { 739 /* fcmeq */, AArch64::FCMEQv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    8001             :   { 739 /* fcmeq */, AArch64::FCMEQv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    8002             :   { 739 /* fcmeq */, AArch64::FCMEQv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    8003             :   { 739 /* fcmeq */, AArch64::FCMEQv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    8004             :   { 739 /* fcmeq */, AArch64::FCMEQv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0, MCK__DOT_0 }, },
    8005             :   { 739 /* fcmeq */, AArch64::FCMEQv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8006             :   { 739 /* fcmeq */, AArch64::FCMEQv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0, MCK__DOT_0 }, },
    8007             :   { 739 /* fcmeq */, AArch64::FCMEQv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8008             :   { 739 /* fcmeq */, AArch64::FCMEQv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0, MCK__DOT_0 }, },
    8009             :   { 739 /* fcmeq */, AArch64::FCMEQv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8010             :   { 739 /* fcmeq */, AArch64::FCMEQv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0, MCK__DOT_0 }, },
    8011             :   { 739 /* fcmeq */, AArch64::FCMEQv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8012             :   { 739 /* fcmeq */, AArch64::FCMEQv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0, MCK__DOT_0 }, },
    8013             :   { 739 /* fcmeq */, AArch64::FCMEQv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8014             :   { 745 /* fcmge */, AArch64::FCMGEv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0 }, },
    8015             :   { 745 /* fcmge */, AArch64::FCMGE16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    8016             :   { 745 /* fcmge */, AArch64::FCMGEv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0 }, },
    8017             :   { 745 /* fcmge */, AArch64::FCMGE32, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8018             :   { 745 /* fcmge */, AArch64::FCMGEv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    8019             :   { 745 /* fcmge */, AArch64::FCMGE64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8020             :   { 745 /* fcmge */, AArch64::FCMGEv2i64rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_2d, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8021             :   { 745 /* fcmge */, AArch64::FCMGEv2i32rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON, { MCK__DOT_2s, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    8022             :   { 745 /* fcmge */, AArch64::FCMGEv4i16rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_4h, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    8023             :   { 745 /* fcmge */, AArch64::FCMGEv4i32rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8024             :   { 745 /* fcmge */, AArch64::FCMGEv8i16rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8025             :   { 745 /* fcmge */, AArch64::FCMGEv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0, MCK__DOT_0 }, },
    8026             :   { 745 /* fcmge */, AArch64::FCMGEv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0, MCK__DOT_0 }, },
    8027             :   { 745 /* fcmge */, AArch64::FCMGEv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0, MCK__DOT_0 }, },
    8028             :   { 745 /* fcmge */, AArch64::FCMGEv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    8029             :   { 745 /* fcmge */, AArch64::FCMGEv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    8030             :   { 745 /* fcmge */, AArch64::FCMGEv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    8031             :   { 745 /* fcmge */, AArch64::FCMGEv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    8032             :   { 745 /* fcmge */, AArch64::FCMGEv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    8033             :   { 745 /* fcmge */, AArch64::FCMGEv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0, MCK__DOT_0 }, },
    8034             :   { 745 /* fcmge */, AArch64::FCMGEv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8035             :   { 745 /* fcmge */, AArch64::FCMGEv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0, MCK__DOT_0 }, },
    8036             :   { 745 /* fcmge */, AArch64::FCMGEv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8037             :   { 745 /* fcmge */, AArch64::FCMGEv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0, MCK__DOT_0 }, },
    8038             :   { 745 /* fcmge */, AArch64::FCMGEv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8039             :   { 745 /* fcmge */, AArch64::FCMGEv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0, MCK__DOT_0 }, },
    8040             :   { 745 /* fcmge */, AArch64::FCMGEv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8041             :   { 745 /* fcmge */, AArch64::FCMGEv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0, MCK__DOT_0 }, },
    8042             :   { 745 /* fcmge */, AArch64::FCMGEv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8043             :   { 751 /* fcmgt */, AArch64::FCMGTv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0 }, },
    8044             :   { 751 /* fcmgt */, AArch64::FCMGT16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    8045             :   { 751 /* fcmgt */, AArch64::FCMGTv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0 }, },
    8046             :   { 751 /* fcmgt */, AArch64::FCMGT32, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8047             :   { 751 /* fcmgt */, AArch64::FCMGTv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    8048             :   { 751 /* fcmgt */, AArch64::FCMGT64, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8049             :   { 751 /* fcmgt */, AArch64::FCMGTv2i64rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_2d, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8050             :   { 751 /* fcmgt */, AArch64::FCMGTv2i32rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON, { MCK__DOT_2s, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    8051             :   { 751 /* fcmgt */, AArch64::FCMGTv4i16rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_4h, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    8052             :   { 751 /* fcmgt */, AArch64::FCMGTv4i32rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8053             :   { 751 /* fcmgt */, AArch64::FCMGTv8i16rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8054             :   { 751 /* fcmgt */, AArch64::FCMGTv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0, MCK__DOT_0 }, },
    8055             :   { 751 /* fcmgt */, AArch64::FCMGTv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0, MCK__DOT_0 }, },
    8056             :   { 751 /* fcmgt */, AArch64::FCMGTv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0, MCK__DOT_0 }, },
    8057             :   { 751 /* fcmgt */, AArch64::FCMGTv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    8058             :   { 751 /* fcmgt */, AArch64::FCMGTv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    8059             :   { 751 /* fcmgt */, AArch64::FCMGTv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    8060             :   { 751 /* fcmgt */, AArch64::FCMGTv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    8061             :   { 751 /* fcmgt */, AArch64::FCMGTv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    8062             :   { 751 /* fcmgt */, AArch64::FCMGTv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0, MCK__DOT_0 }, },
    8063             :   { 751 /* fcmgt */, AArch64::FCMGTv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8064             :   { 751 /* fcmgt */, AArch64::FCMGTv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0, MCK__DOT_0 }, },
    8065             :   { 751 /* fcmgt */, AArch64::FCMGTv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8066             :   { 751 /* fcmgt */, AArch64::FCMGTv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0, MCK__DOT_0 }, },
    8067             :   { 751 /* fcmgt */, AArch64::FCMGTv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8068             :   { 751 /* fcmgt */, AArch64::FCMGTv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0, MCK__DOT_0 }, },
    8069             :   { 751 /* fcmgt */, AArch64::FCMGTv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8070             :   { 751 /* fcmgt */, AArch64::FCMGTv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0, MCK__DOT_0 }, },
    8071             :   { 751 /* fcmgt */, AArch64::FCMGTv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8072             :   { 757 /* fcmla */, AArch64::FCMLAv2f64, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6, Feature_HasV8_3a|Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_ComplexRotationEven }, },
    8073             :   { 757 /* fcmla */, AArch64::FCMLAv4f32, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6, Feature_HasV8_3a|Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_ComplexRotationEven }, },
    8074             :   { 757 /* fcmla */, AArch64::FCMLAv8f16, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6, Feature_HasV8_3a|Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_ComplexRotationEven }, },
    8075             :   { 757 /* fcmla */, AArch64::FCMLAv2f32, Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4__ComplexRotationEven1_6, Feature_HasV8_3a|Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_ComplexRotationEven }, },
    8076             :   { 757 /* fcmla */, AArch64::FCMLAv4f16, Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4__ComplexRotationEven1_6, Feature_HasV8_3a|Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_ComplexRotationEven }, },
    8077             :   { 757 /* fcmla */, AArch64::FCMLAv4f32_indexed, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7, Feature_HasV8_3a|Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_s, MCK_VectorIndexD, MCK_ComplexRotationEven }, },
    8078             :   { 757 /* fcmla */, AArch64::FCMLAv8f16_indexed, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6__ComplexRotationEven1_7, Feature_HasV8_3a|Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_h, MCK_VectorIndexS, MCK_ComplexRotationEven }, },
    8079             :   { 757 /* fcmla */, AArch64::FCMLAv4f16_indexed, Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7, Feature_HasV8_3a|Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg128, MCK__DOT_h, MCK_VectorIndexD, MCK_ComplexRotationEven }, },
    8080             :   { 763 /* fcmle */, AArch64::FCMLEv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0 }, },
    8081             :   { 763 /* fcmle */, AArch64::FCMLEv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0 }, },
    8082             :   { 763 /* fcmle */, AArch64::FCMGE32, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8083             :   { 763 /* fcmle */, AArch64::FCMLEv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    8084             :   { 763 /* fcmle */, AArch64::FCMGE64, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8085             :   { 763 /* fcmle */, AArch64::FCMLEv2i64rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_2d, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8086             :   { 763 /* fcmle */, AArch64::FCMLEv2i32rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON, { MCK__DOT_2s, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    8087             :   { 763 /* fcmle */, AArch64::FCMLEv4i16rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_4h, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    8088             :   { 763 /* fcmle */, AArch64::FCMLEv4i32rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8089             :   { 763 /* fcmle */, AArch64::FCMLEv8i16rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8090             :   { 763 /* fcmle */, AArch64::FCMLEv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0, MCK__DOT_0 }, },
    8091             :   { 763 /* fcmle */, AArch64::FCMLEv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0, MCK__DOT_0 }, },
    8092             :   { 763 /* fcmle */, AArch64::FCMLEv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0, MCK__DOT_0 }, },
    8093             :   { 763 /* fcmle */, AArch64::FCMLEv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    8094             :   { 763 /* fcmle */, AArch64::FCMLEv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    8095             :   { 763 /* fcmle */, AArch64::FCMLEv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    8096             :   { 763 /* fcmle */, AArch64::FCMLEv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    8097             :   { 763 /* fcmle */, AArch64::FCMLEv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    8098             :   { 763 /* fcmle */, AArch64::FCMLEv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0, MCK__DOT_0 }, },
    8099             :   { 763 /* fcmle */, AArch64::FCMGEv2f64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8100             :   { 763 /* fcmle */, AArch64::FCMLEv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0, MCK__DOT_0 }, },
    8101             :   { 763 /* fcmle */, AArch64::FCMGEv4f32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8102             :   { 763 /* fcmle */, AArch64::FCMLEv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0, MCK__DOT_0 }, },
    8103             :   { 763 /* fcmle */, AArch64::FCMGEv8f16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8104             :   { 763 /* fcmle */, AArch64::FCMLEv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0, MCK__DOT_0 }, },
    8105             :   { 763 /* fcmle */, AArch64::FCMGEv2f32, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8106             :   { 763 /* fcmle */, AArch64::FCMLEv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0, MCK__DOT_0 }, },
    8107             :   { 763 /* fcmle */, AArch64::FCMGEv4f16, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8108             :   { 769 /* fcmlt */, AArch64::FCMLTv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0 }, },
    8109             :   { 769 /* fcmlt */, AArch64::FCMLTv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0 }, },
    8110             :   { 769 /* fcmlt */, AArch64::FCMGT32, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8111             :   { 769 /* fcmlt */, AArch64::FCMLTv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0 }, },
    8112             :   { 769 /* fcmlt */, AArch64::FCMGT64, Convert__Reg1_0__Reg1_2__Reg1_1, 0, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8113             :   { 769 /* fcmlt */, AArch64::FCMLTv2i64rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_2d, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8114             :   { 769 /* fcmlt */, AArch64::FCMLTv2i32rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON, { MCK__DOT_2s, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    8115             :   { 769 /* fcmlt */, AArch64::FCMLTv4i16rz, Convert__VectorReg641_1__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_4h, MCK_VectorReg64, MCK_VectorReg64, MCK__35_0 }, },
    8116             :   { 769 /* fcmlt */, AArch64::FCMLTv4i32rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8117             :   { 769 /* fcmlt */, AArch64::FCMLTv8i16rz, Convert__VectorReg1281_1__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK__35_0 }, },
    8118             :   { 769 /* fcmlt */, AArch64::FCMLTv1i16rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK__35_0, MCK__DOT_0 }, },
    8119             :   { 769 /* fcmlt */, AArch64::FCMLTv1i32rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK__35_0, MCK__DOT_0 }, },
    8120             :   { 769 /* fcmlt */, AArch64::FCMLTv1i64rz, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK__35_0, MCK__DOT_0 }, },
    8121             :   { 769 /* fcmlt */, AArch64::FCMLTv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0 }, },
    8122             :   { 769 /* fcmlt */, AArch64::FCMLTv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0 }, },
    8123             :   { 769 /* fcmlt */, AArch64::FCMLTv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0 }, },
    8124             :   { 769 /* fcmlt */, AArch64::FCMLTv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0 }, },
    8125             :   { 769 /* fcmlt */, AArch64::FCMLTv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0 }, },
    8126             :   { 769 /* fcmlt */, AArch64::FCMLTv2i64rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK__35_0, MCK__DOT_0 }, },
    8127             :   { 769 /* fcmlt */, AArch64::FCMGTv2f64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8128             :   { 769 /* fcmlt */, AArch64::FCMLTv4i32rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK__35_0, MCK__DOT_0 }, },
    8129             :   { 769 /* fcmlt */, AArch64::FCMGTv4f32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, 0, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8130             :   { 769 /* fcmlt */, AArch64::FCMLTv8i16rz, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK__35_0, MCK__DOT_0 }, },
    8131             :   { 769 /* fcmlt */, AArch64::FCMGTv8f16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8132             :   { 769 /* fcmlt */, AArch64::FCMLTv2i32rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK__35_0, MCK__DOT_0 }, },
    8133             :   { 769 /* fcmlt */, AArch64::FCMGTv2f32, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, 0, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8134             :   { 769 /* fcmlt */, AArch64::FCMLTv4i16rz, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK__35_0, MCK__DOT_0 }, },
    8135             :   { 769 /* fcmlt */, AArch64::FCMGTv4f16, Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8136             :   { 775 /* fcmp */, AArch64::FCMPHrr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8137             :   { 775 /* fcmp */, AArch64::FCMPSrr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32 }, },
    8138             :   { 775 /* fcmp */, AArch64::FCMPDrr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64 }, },
    8139             :   { 775 /* fcmp */, AArch64::FCMPHri, Convert__Reg1_0, Feature_HasFullFP16, { MCK_FPR16, MCK__35_0, MCK__DOT_0 }, },
    8140             :   { 775 /* fcmp */, AArch64::FCMPSri, Convert__Reg1_0, Feature_HasFPARMv8, { MCK_FPR32, MCK__35_0, MCK__DOT_0 }, },
    8141             :   { 775 /* fcmp */, AArch64::FCMPDri, Convert__Reg1_0, Feature_HasFPARMv8, { MCK_FPR64, MCK__35_0, MCK__DOT_0 }, },
    8142             :   { 780 /* fcmpe */, AArch64::FCMPEHrr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8143             :   { 780 /* fcmpe */, AArch64::FCMPESrr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32 }, },
    8144             :   { 780 /* fcmpe */, AArch64::FCMPEDrr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64 }, },
    8145             :   { 780 /* fcmpe */, AArch64::FCMPEHri, Convert__Reg1_0, Feature_HasFullFP16, { MCK_FPR16, MCK__35_0, MCK__DOT_0 }, },
    8146             :   { 780 /* fcmpe */, AArch64::FCMPESri, Convert__Reg1_0, Feature_HasFPARMv8, { MCK_FPR32, MCK__35_0, MCK__DOT_0 }, },
    8147             :   { 780 /* fcmpe */, AArch64::FCMPEDri, Convert__Reg1_0, Feature_HasFPARMv8, { MCK_FPR64, MCK__35_0, MCK__DOT_0 }, },
    8148             :   { 786 /* fcsel */, AArch64::FCSELHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_CondCode }, },
    8149             :   { 786 /* fcsel */, AArch64::FCSELSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_CondCode }, },
    8150             :   { 786 /* fcsel */, AArch64::FCSELDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_CondCode }, },
    8151             :   { 792 /* fcvt */, AArch64::FCVTHSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR16, MCK_FPR32 }, },
    8152             :   { 792 /* fcvt */, AArch64::FCVTHDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR16, MCK_FPR64 }, },
    8153             :   { 792 /* fcvt */, AArch64::FCVTSHr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR16 }, },
    8154             :   { 792 /* fcvt */, AArch64::FCVTSDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR64 }, },
    8155             :   { 792 /* fcvt */, AArch64::FCVTDHr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR16 }, },
    8156             :   { 792 /* fcvt */, AArch64::FCVTDSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR32 }, },
    8157             :   { 797 /* fcvtas */, AArch64::FCVTASv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8158             :   { 797 /* fcvtas */, AArch64::FCVTASv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8159             :   { 797 /* fcvtas */, AArch64::FCVTASv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8160             :   { 797 /* fcvtas */, AArch64::FCVTASUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8161             :   { 797 /* fcvtas */, AArch64::FCVTASUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8162             :   { 797 /* fcvtas */, AArch64::FCVTASUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8163             :   { 797 /* fcvtas */, AArch64::FCVTASUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8164             :   { 797 /* fcvtas */, AArch64::FCVTASUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8165             :   { 797 /* fcvtas */, AArch64::FCVTASUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8166             :   { 797 /* fcvtas */, AArch64::FCVTASv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8167             :   { 797 /* fcvtas */, AArch64::FCVTASv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8168             :   { 797 /* fcvtas */, AArch64::FCVTASv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8169             :   { 797 /* fcvtas */, AArch64::FCVTASv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8170             :   { 797 /* fcvtas */, AArch64::FCVTASv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8171             :   { 804 /* fcvtau */, AArch64::FCVTAUv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8172             :   { 804 /* fcvtau */, AArch64::FCVTAUv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8173             :   { 804 /* fcvtau */, AArch64::FCVTAUv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8174             :   { 804 /* fcvtau */, AArch64::FCVTAUUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8175             :   { 804 /* fcvtau */, AArch64::FCVTAUUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8176             :   { 804 /* fcvtau */, AArch64::FCVTAUUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8177             :   { 804 /* fcvtau */, AArch64::FCVTAUUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8178             :   { 804 /* fcvtau */, AArch64::FCVTAUUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8179             :   { 804 /* fcvtau */, AArch64::FCVTAUUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8180             :   { 804 /* fcvtau */, AArch64::FCVTAUv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8181             :   { 804 /* fcvtau */, AArch64::FCVTAUv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8182             :   { 804 /* fcvtau */, AArch64::FCVTAUv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8183             :   { 804 /* fcvtau */, AArch64::FCVTAUv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8184             :   { 804 /* fcvtau */, AArch64::FCVTAUv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8185             :   { 811 /* fcvtl */, AArch64::FCVTLv2i32, Convert__VectorReg1281_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg64, MCK__DOT_2s }, },
    8186             :   { 811 /* fcvtl */, AArch64::FCVTLv4i16, Convert__VectorReg1281_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg64, MCK__DOT_4h }, },
    8187             :   { 817 /* fcvtl2 */, AArch64::FCVTLv4i32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_4s }, },
    8188             :   { 817 /* fcvtl2 */, AArch64::FCVTLv8i16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_8h }, },
    8189             :   { 824 /* fcvtms */, AArch64::FCVTMSv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8190             :   { 824 /* fcvtms */, AArch64::FCVTMSv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8191             :   { 824 /* fcvtms */, AArch64::FCVTMSv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8192             :   { 824 /* fcvtms */, AArch64::FCVTMSUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8193             :   { 824 /* fcvtms */, AArch64::FCVTMSUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8194             :   { 824 /* fcvtms */, AArch64::FCVTMSUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8195             :   { 824 /* fcvtms */, AArch64::FCVTMSUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8196             :   { 824 /* fcvtms */, AArch64::FCVTMSUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8197             :   { 824 /* fcvtms */, AArch64::FCVTMSUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8198             :   { 824 /* fcvtms */, AArch64::FCVTMSv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8199             :   { 824 /* fcvtms */, AArch64::FCVTMSv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8200             :   { 824 /* fcvtms */, AArch64::FCVTMSv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8201             :   { 824 /* fcvtms */, AArch64::FCVTMSv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8202             :   { 824 /* fcvtms */, AArch64::FCVTMSv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8203             :   { 831 /* fcvtmu */, AArch64::FCVTMUv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8204             :   { 831 /* fcvtmu */, AArch64::FCVTMUv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8205             :   { 831 /* fcvtmu */, AArch64::FCVTMUv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8206             :   { 831 /* fcvtmu */, AArch64::FCVTMUUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8207             :   { 831 /* fcvtmu */, AArch64::FCVTMUUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8208             :   { 831 /* fcvtmu */, AArch64::FCVTMUUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8209             :   { 831 /* fcvtmu */, AArch64::FCVTMUUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8210             :   { 831 /* fcvtmu */, AArch64::FCVTMUUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8211             :   { 831 /* fcvtmu */, AArch64::FCVTMUUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8212             :   { 831 /* fcvtmu */, AArch64::FCVTMUv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8213             :   { 831 /* fcvtmu */, AArch64::FCVTMUv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8214             :   { 831 /* fcvtmu */, AArch64::FCVTMUv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8215             :   { 831 /* fcvtmu */, AArch64::FCVTMUv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8216             :   { 831 /* fcvtmu */, AArch64::FCVTMUv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8217             :   { 838 /* fcvtn */, AArch64::FCVTNv2i32, Convert__VectorReg641_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg128, MCK__DOT_2d }, },
    8218             :   { 838 /* fcvtn */, AArch64::FCVTNv4i16, Convert__VectorReg641_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg128, MCK__DOT_4s }, },
    8219             :   { 844 /* fcvtn2 */, AArch64::FCVTNv4i32, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d }, },
    8220             :   { 844 /* fcvtn2 */, AArch64::FCVTNv8i16, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s }, },
    8221             :   { 851 /* fcvtns */, AArch64::FCVTNSv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8222             :   { 851 /* fcvtns */, AArch64::FCVTNSv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8223             :   { 851 /* fcvtns */, AArch64::FCVTNSv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8224             :   { 851 /* fcvtns */, AArch64::FCVTNSUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8225             :   { 851 /* fcvtns */, AArch64::FCVTNSUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8226             :   { 851 /* fcvtns */, AArch64::FCVTNSUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8227             :   { 851 /* fcvtns */, AArch64::FCVTNSUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8228             :   { 851 /* fcvtns */, AArch64::FCVTNSUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8229             :   { 851 /* fcvtns */, AArch64::FCVTNSUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8230             :   { 851 /* fcvtns */, AArch64::FCVTNSv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8231             :   { 851 /* fcvtns */, AArch64::FCVTNSv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8232             :   { 851 /* fcvtns */, AArch64::FCVTNSv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8233             :   { 851 /* fcvtns */, AArch64::FCVTNSv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8234             :   { 851 /* fcvtns */, AArch64::FCVTNSv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8235             :   { 858 /* fcvtnu */, AArch64::FCVTNUv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8236             :   { 858 /* fcvtnu */, AArch64::FCVTNUv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8237             :   { 858 /* fcvtnu */, AArch64::FCVTNUv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8238             :   { 858 /* fcvtnu */, AArch64::FCVTNUUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8239             :   { 858 /* fcvtnu */, AArch64::FCVTNUUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8240             :   { 858 /* fcvtnu */, AArch64::FCVTNUUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8241             :   { 858 /* fcvtnu */, AArch64::FCVTNUUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8242             :   { 858 /* fcvtnu */, AArch64::FCVTNUUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8243             :   { 858 /* fcvtnu */, AArch64::FCVTNUUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8244             :   { 858 /* fcvtnu */, AArch64::FCVTNUv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8245             :   { 858 /* fcvtnu */, AArch64::FCVTNUv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8246             :   { 858 /* fcvtnu */, AArch64::FCVTNUv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8247             :   { 858 /* fcvtnu */, AArch64::FCVTNUv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8248             :   { 858 /* fcvtnu */, AArch64::FCVTNUv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8249             :   { 865 /* fcvtps */, AArch64::FCVTPSv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8250             :   { 865 /* fcvtps */, AArch64::FCVTPSv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8251             :   { 865 /* fcvtps */, AArch64::FCVTPSv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8252             :   { 865 /* fcvtps */, AArch64::FCVTPSUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8253             :   { 865 /* fcvtps */, AArch64::FCVTPSUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8254             :   { 865 /* fcvtps */, AArch64::FCVTPSUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8255             :   { 865 /* fcvtps */, AArch64::FCVTPSUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8256             :   { 865 /* fcvtps */, AArch64::FCVTPSUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8257             :   { 865 /* fcvtps */, AArch64::FCVTPSUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8258             :   { 865 /* fcvtps */, AArch64::FCVTPSv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8259             :   { 865 /* fcvtps */, AArch64::FCVTPSv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8260             :   { 865 /* fcvtps */, AArch64::FCVTPSv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8261             :   { 865 /* fcvtps */, AArch64::FCVTPSv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8262             :   { 865 /* fcvtps */, AArch64::FCVTPSv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8263             :   { 872 /* fcvtpu */, AArch64::FCVTPUv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8264             :   { 872 /* fcvtpu */, AArch64::FCVTPUv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8265             :   { 872 /* fcvtpu */, AArch64::FCVTPUv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8266             :   { 872 /* fcvtpu */, AArch64::FCVTPUUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8267             :   { 872 /* fcvtpu */, AArch64::FCVTPUUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8268             :   { 872 /* fcvtpu */, AArch64::FCVTPUUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8269             :   { 872 /* fcvtpu */, AArch64::FCVTPUUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8270             :   { 872 /* fcvtpu */, AArch64::FCVTPUUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8271             :   { 872 /* fcvtpu */, AArch64::FCVTPUUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8272             :   { 872 /* fcvtpu */, AArch64::FCVTPUv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8273             :   { 872 /* fcvtpu */, AArch64::FCVTPUv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8274             :   { 872 /* fcvtpu */, AArch64::FCVTPUv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8275             :   { 872 /* fcvtpu */, AArch64::FCVTPUv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8276             :   { 872 /* fcvtpu */, AArch64::FCVTPUv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8277             :   { 879 /* fcvtxn */, AArch64::FCVTXNv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR64 }, },
    8278             :   { 879 /* fcvtxn */, AArch64::FCVTXNv2f32, Convert__VectorReg641_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg128, MCK__DOT_2d }, },
    8279             :   { 886 /* fcvtxn2 */, AArch64::FCVTXNv4f32, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d }, },
    8280             :   { 894 /* fcvtzs */, AArch64::FCVTZSv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8281             :   { 894 /* fcvtzs */, AArch64::FCVTZSv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8282             :   { 894 /* fcvtzs */, AArch64::FCVTZSv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8283             :   { 894 /* fcvtzs */, AArch64::FCVTZSUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8284             :   { 894 /* fcvtzs */, AArch64::FCVTZSUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8285             :   { 894 /* fcvtzs */, AArch64::FCVTZSUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8286             :   { 894 /* fcvtzs */, AArch64::FCVTZSUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8287             :   { 894 /* fcvtzs */, AArch64::FCVTZSUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8288             :   { 894 /* fcvtzs */, AArch64::FCVTZSUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8289             :   { 894 /* fcvtzs */, AArch64::FCVTZSh, Convert__Reg1_0__Reg1_1__Imm1_161_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_Imm1_16 }, },
    8290             :   { 894 /* fcvtzs */, AArch64::FCVTZSs, Convert__Reg1_0__Reg1_1__Imm1_321_2, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
    8291             :   { 894 /* fcvtzs */, AArch64::FCVTZSd, Convert__Reg1_0__Reg1_1__Imm1_641_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_Imm1_64 }, },
    8292             :   { 894 /* fcvtzs */, AArch64::FCVTZSSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16, MCK_Imm1_32 }, },
    8293             :   { 894 /* fcvtzs */, AArch64::FCVTZSSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32, MCK_Imm1_32 }, },
    8294             :   { 894 /* fcvtzs */, AArch64::FCVTZSSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64, MCK_Imm1_32 }, },
    8295             :   { 894 /* fcvtzs */, AArch64::FCVTZSSXHri, Convert__Reg1_0__Reg1_1__Imm1_641_2, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16, MCK_Imm1_64 }, },
    8296             :   { 894 /* fcvtzs */, AArch64::FCVTZSSXSri, Convert__Reg1_0__Reg1_1__Imm1_641_2, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32, MCK_Imm1_64 }, },
    8297             :   { 894 /* fcvtzs */, AArch64::FCVTZSSXDri, Convert__Reg1_0__Reg1_1__Imm1_641_2, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64, MCK_Imm1_64 }, },
    8298             :   { 894 /* fcvtzs */, AArch64::FCVTZSv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8299             :   { 894 /* fcvtzs */, AArch64::FCVTZSv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8300             :   { 894 /* fcvtzs */, AArch64::FCVTZSv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8301             :   { 894 /* fcvtzs */, AArch64::FCVTZSv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8302             :   { 894 /* fcvtzs */, AArch64::FCVTZSv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8303             :   { 894 /* fcvtzs */, AArch64::FCVTZSv2i64_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm1_641_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_64 }, },
    8304             :   { 894 /* fcvtzs */, AArch64::FCVTZSv4i32_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm1_321_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_32 }, },
    8305             :   { 894 /* fcvtzs */, AArch64::FCVTZSv8i16_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm1_161_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_16 }, },
    8306             :   { 894 /* fcvtzs */, AArch64::FCVTZSv2i32_shift, Convert__VectorReg641_0__VectorReg641_2__Imm1_321_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_Imm1_32 }, },
    8307             :   { 894 /* fcvtzs */, AArch64::FCVTZSv4i16_shift, Convert__VectorReg641_0__VectorReg641_2__Imm1_161_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_Imm1_16 }, },
    8308             :   { 901 /* fcvtzu */, AArch64::FCVTZUv1f16, Convert__Reg1_0__Reg1_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16 }, },
    8309             :   { 901 /* fcvtzu */, AArch64::FCVTZUv1i32, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR32, MCK_FPR32 }, },
    8310             :   { 901 /* fcvtzu */, AArch64::FCVTZUv1i64, Convert__Reg1_0__Reg1_1, Feature_HasNEON, { MCK_FPR64, MCK_FPR64 }, },
    8311             :   { 901 /* fcvtzu */, AArch64::FCVTZUUWHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16 }, },
    8312             :   { 901 /* fcvtzu */, AArch64::FCVTZUUWSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32 }, },
    8313             :   { 901 /* fcvtzu */, AArch64::FCVTZUUWDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8314             :   { 901 /* fcvtzu */, AArch64::FCVTZUUXHr, Convert__Reg1_0__Reg1_1, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16 }, },
    8315             :   { 901 /* fcvtzu */, AArch64::FCVTZUUXSr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32 }, },
    8316             :   { 901 /* fcvtzu */, AArch64::FCVTZUUXDr, Convert__Reg1_0__Reg1_1, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64 }, },
    8317             :   { 901 /* fcvtzu */, AArch64::FCVTZUh, Convert__Reg1_0__Reg1_1__Imm1_161_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_Imm1_16 }, },
    8318             :   { 901 /* fcvtzu */, AArch64::FCVTZUs, Convert__Reg1_0__Reg1_1__Imm1_321_2, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
    8319             :   { 901 /* fcvtzu */, AArch64::FCVTZUd, Convert__Reg1_0__Reg1_1__Imm1_641_2, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_Imm1_64 }, },
    8320             :   { 901 /* fcvtzu */, AArch64::FCVTZUSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, Feature_HasFullFP16, { MCK_GPR32, MCK_FPR16, MCK_Imm1_32 }, },
    8321             :   { 901 /* fcvtzu */, AArch64::FCVTZUSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR32, MCK_Imm1_32 }, },
    8322             :   { 901 /* fcvtzu */, AArch64::FCVTZUSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64, MCK_Imm1_32 }, },
    8323             :   { 901 /* fcvtzu */, AArch64::FCVTZUSXHri, Convert__Reg1_0__Reg1_1__Imm1_641_2, Feature_HasFullFP16, { MCK_GPR64, MCK_FPR16, MCK_Imm1_64 }, },
    8324             :   { 901 /* fcvtzu */, AArch64::FCVTZUSXSri, Convert__Reg1_0__Reg1_1__Imm1_641_2, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR32, MCK_Imm1_64 }, },
    8325             :   { 901 /* fcvtzu */, AArch64::FCVTZUSXDri, Convert__Reg1_0__Reg1_1__Imm1_641_2, Feature_HasFPARMv8, { MCK_GPR64, MCK_FPR64, MCK_Imm1_64 }, },
    8326             :   { 901 /* fcvtzu */, AArch64::FCVTZUv2f64, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8327             :   { 901 /* fcvtzu */, AArch64::FCVTZUv4f32, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8328             :   { 901 /* fcvtzu */, AArch64::FCVTZUv8f16, Convert__VectorReg1281_0__VectorReg1281_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8329             :   { 901 /* fcvtzu */, AArch64::FCVTZUv2f32, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8330             :   { 901 /* fcvtzu */, AArch64::FCVTZUv4f16, Convert__VectorReg641_0__VectorReg641_2, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8331             :   { 901 /* fcvtzu */, AArch64::FCVTZUv2i64_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm1_641_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_64 }, },
    8332             :   { 901 /* fcvtzu */, AArch64::FCVTZUv4i32_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm1_321_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_32 }, },
    8333             :   { 901 /* fcvtzu */, AArch64::FCVTZUv8i16_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm1_161_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_16 }, },
    8334             :   { 901 /* fcvtzu */, AArch64::FCVTZUv2i32_shift, Convert__VectorReg641_0__VectorReg641_2__Imm1_321_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_Imm1_32 }, },
    8335             :   { 901 /* fcvtzu */, AArch64::FCVTZUv4i16_shift, Convert__VectorReg641_0__VectorReg641_2__Imm1_161_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_Imm1_16 }, },
    8336             :   { 908 /* fdiv */, AArch64::FDIVHrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    8337             :   { 908 /* fdiv */, AArch64::FDIVSrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8338             :   { 908 /* fdiv */, AArch64::FDIVDrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8339             :   { 908 /* fdiv */, AArch64::FDIVv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8340             :   { 908 /* fdiv */, AArch64::FDIVv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8341             :   { 908 /* fdiv */, AArch64::FDIVv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8342             :   { 908 /* fdiv */, AArch64::FDIVv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8343             :   { 908 /* fdiv */, AArch64::FDIVv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8344             :   { 913 /* fjcvtzs */, AArch64::FJCVTZS, Convert__Reg1_0__Reg1_1, Feature_HasV8_3a|Feature_HasFPARMv8, { MCK_GPR32, MCK_FPR64 }, },
    8345             :   { 921 /* fmadd */, AArch64::FMADDHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    8346             :   { 921 /* fmadd */, AArch64::FMADDSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8347             :   { 921 /* fmadd */, AArch64::FMADDDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8348             :   { 927 /* fmax */, AArch64::FMAXHrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    8349             :   { 927 /* fmax */, AArch64::FMAXSrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8350             :   { 927 /* fmax */, AArch64::FMAXDrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8351             :   { 927 /* fmax */, AArch64::FMAXv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8352             :   { 927 /* fmax */, AArch64::FMAXv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8353             :   { 927 /* fmax */, AArch64::FMAXv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8354             :   { 927 /* fmax */, AArch64::FMAXv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8355             :   { 927 /* fmax */, AArch64::FMAXv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8356             :   { 932 /* fmaxnm */, AArch64::FMAXNMHrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    8357             :   { 932 /* fmaxnm */, AArch64::FMAXNMSrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8358             :   { 932 /* fmaxnm */, AArch64::FMAXNMDrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8359             :   { 932 /* fmaxnm */, AArch64::FMAXNMv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8360             :   { 932 /* fmaxnm */, AArch64::FMAXNMv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8361             :   { 932 /* fmaxnm */, AArch64::FMAXNMv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8362             :   { 932 /* fmaxnm */, AArch64::FMAXNMv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8363             :   { 932 /* fmaxnm */, AArch64::FMAXNMv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8364             :   { 939 /* fmaxnmp */, AArch64::FMAXNMPv2i16p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_2h }, },
    8365             :   { 939 /* fmaxnmp */, AArch64::FMAXNMPv2i32p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg64, MCK__DOT_2s }, },
    8366             :   { 939 /* fmaxnmp */, AArch64::FMAXNMPv2i64p, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_2d }, },
    8367             :   { 939 /* fmaxnmp */, AArch64::FMAXNMPv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8368             :   { 939 /* fmaxnmp */, AArch64::FMAXNMPv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8369             :   { 939 /* fmaxnmp */, AArch64::FMAXNMPv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8370             :   { 939 /* fmaxnmp */, AArch64::FMAXNMPv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8371             :   { 939 /* fmaxnmp */, AArch64::FMAXNMPv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8372             :   { 947 /* fmaxnmv */, AArch64::FMAXNMVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
    8373             :   { 947 /* fmaxnmv */, AArch64::FMAXNMVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_4h }, },
    8374             :   { 947 /* fmaxnmv */, AArch64::FMAXNMVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
    8375             :   { 955 /* fmaxp */, AArch64::FMAXPv2i16p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_2h }, },
    8376             :   { 955 /* fmaxp */, AArch64::FMAXPv2i32p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg64, MCK__DOT_2s }, },
    8377             :   { 955 /* fmaxp */, AArch64::FMAXPv2i64p, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_2d }, },
    8378             :   { 955 /* fmaxp */, AArch64::FMAXPv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8379             :   { 955 /* fmaxp */, AArch64::FMAXPv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8380             :   { 955 /* fmaxp */, AArch64::FMAXPv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8381             :   { 955 /* fmaxp */, AArch64::FMAXPv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8382             :   { 955 /* fmaxp */, AArch64::FMAXPv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8383             :   { 961 /* fmaxv */, AArch64::FMAXVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
    8384             :   { 961 /* fmaxv */, AArch64::FMAXVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_4h }, },
    8385             :   { 961 /* fmaxv */, AArch64::FMAXVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
    8386             :   { 967 /* fmin */, AArch64::FMINHrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    8387             :   { 967 /* fmin */, AArch64::FMINSrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8388             :   { 967 /* fmin */, AArch64::FMINDrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8389             :   { 967 /* fmin */, AArch64::FMINv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8390             :   { 967 /* fmin */, AArch64::FMINv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8391             :   { 967 /* fmin */, AArch64::FMINv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8392             :   { 967 /* fmin */, AArch64::FMINv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8393             :   { 967 /* fmin */, AArch64::FMINv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8394             :   { 972 /* fminnm */, AArch64::FMINNMHrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
    8395             :   { 972 /* fminnm */, AArch64::FMINNMSrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
    8396             :   { 972 /* fminnm */, AArch64::FMINNMDrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
    8397             :   { 972 /* fminnm */, AArch64::FMINNMv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8398             :   { 972 /* fminnm */, AArch64::FMINNMv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8399             :   { 972 /* fminnm */, AArch64::FMINNMv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8400             :   { 972 /* fminnm */, AArch64::FMINNMv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8401             :   { 972 /* fminnm */, AArch64::FMINNMv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8402             :   { 979 /* fminnmp */, AArch64::FMINNMPv2i16p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_2h }, },
    8403             :   { 979 /* fminnmp */, AArch64::FMINNMPv2i32p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg64, MCK__DOT_2s }, },
    8404             :   { 979 /* fminnmp */, AArch64::FMINNMPv2i64p, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_2d }, },
    8405             :   { 979 /* fminnmp */, AArch64::FMINNMPv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8406             :   { 979 /* fminnmp */, AArch64::FMINNMPv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8407             :   { 979 /* fminnmp */, AArch64::FMINNMPv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8408             :   { 979 /* fminnmp */, AArch64::FMINNMPv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8409             :   { 979 /* fminnmp */, AArch64::FMINNMPv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8410             :   { 987 /* fminnmv */, AArch64::FMINNMVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
    8411             :   { 987 /* fminnmv */, AArch64::FMINNMVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_4h }, },
    8412             :   { 987 /* fminnmv */, AArch64::FMINNMVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
    8413             :   { 995 /* fminp */, AArch64::FMINPv2i16p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_2h }, },
    8414             :   { 995 /* fminp */, AArch64::FMINPv2i32p, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg64, MCK__DOT_2s }, },
    8415             :   { 995 /* fminp */, AArch64::FMINPv2i64p, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_2d }, },
    8416             :   { 995 /* fminp */, AArch64::FMINPv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
    8417             :   { 995 /* fminp */, AArch64::FMINPv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
    8418             :   { 995 /* fminp */, AArch64::FMINPv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
    8419             :   { 995 /* fminp */, AArch64::FMINPv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON, { MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s, MCK_VectorReg64, MCK__DOT_2s }, },
    8420             :   { 995 /* fminp */, AArch64::FMINPv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h, MCK_VectorReg64, MCK__DOT_4h }, },
    8421             :   { 1001 /* fminv */, AArch64::FMINVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
    8422             :   { 1001 /* fminv */, AArch64::FMINVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_VectorReg64, MCK__DOT_4h }, },
    8423             :   { 1001 /* fminv */, AArch64::FMINVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
    8424             :   { 1007 /* fmla */, AArch64::FMLAv1i16_indexed, Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorRegLo1_2__VectorIndexH1_4, Feature_HasNEON|Feature_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_VectorRegLo, MCK__DOT_h, MCK_VectorIndexH }, },
    8425             :   { 1007 /* fmla */, AArch64::FMLAv1i32_indexed, Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2__VectorIndexS1_4, Feature_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_VectorReg128, MCK__DOT_s, MCK_VectorIndexS }, },
    8426             :   { 1007 /* fmla */, AArch64::FMLAv1i64_indexed, Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2__VectorIndexD1_4, Feature_HasNEON, { MCK_FPR64, MCK_FPR64, MCK_VectorReg128, MCK__DOT_d, MCK_VectorIndexD }, },
    8427             :   { 1007 /* fmla */, AArch64::FMLAv2f64, Convert_