LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenAsmMatcher.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1209 1996 60.6 %
Date: 2018-05-20 00:06:23 Functions: 12 13 92.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Assembly Matcher Source Fragment                                           *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_ASSEMBLER_HEADER
      11             : #undef GET_ASSEMBLER_HEADER
      12             :   // This should be included into the middle of the declaration of
      13             :   // your subclasses implementation of MCTargetAsmParser.
      14             :   uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
      15             :   void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
      16             :                        const OperandVector &Operands);
      17             :   void convertToMapAndConstraints(unsigned Kind,
      18             :                            const OperandVector &Operands) override;
      19             :   unsigned MatchInstructionImpl(const OperandVector &Operands,
      20             :                                 MCInst &Inst,
      21             :                                 uint64_t &ErrorInfo,
      22             :                                 bool matchingInlineAsm,
      23             :                                 unsigned VariantID = 0);
      24             :   OperandMatchResultTy MatchOperandParserImpl(
      25             :     OperandVector &Operands,
      26             :     StringRef Mnemonic,
      27             :     bool ParseForAllFeatures = false);
      28             :   OperandMatchResultTy tryCustomParseOperand(
      29             :     OperandVector &Operands,
      30             :     unsigned MCK);
      31             : 
      32             : #endif // GET_ASSEMBLER_HEADER_INFO
      33             : 
      34             : 
      35             : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
      36             : #undef GET_OPERAND_DIAGNOSTIC_TYPES
      37             : 
      38             :   Match_AddSubRegExtendLarge,
      39             :   Match_AddSubRegExtendSmall,
      40             :   Match_AddSubRegShift32,
      41             :   Match_AddSubRegShift64,
      42             :   Match_AddSubSecondSource,
      43             :   Match_InvalidComplexRotationEven,
      44             :   Match_InvalidComplexRotationOdd,
      45             :   Match_InvalidCondCode,
      46             :   Match_InvalidFPImm,
      47             :   Match_InvalidGPR64NoXZRshifted16,
      48             :   Match_InvalidGPR64NoXZRshifted32,
      49             :   Match_InvalidGPR64NoXZRshifted64,
      50             :   Match_InvalidGPR64NoXZRshifted8,
      51             :   Match_InvalidGPR64shifted16,
      52             :   Match_InvalidGPR64shifted32,
      53             :   Match_InvalidGPR64shifted64,
      54             :   Match_InvalidGPR64shifted8,
      55             :   Match_InvalidImm0_1,
      56             :   Match_InvalidImm0_127,
      57             :   Match_InvalidImm0_15,
      58             :   Match_InvalidImm0_255,
      59             :   Match_InvalidImm0_31,
      60             :   Match_InvalidImm0_63,
      61             :   Match_InvalidImm0_65535,
      62             :   Match_InvalidImm0_7,
      63             :   Match_InvalidImm1_16,
      64             :   Match_InvalidImm1_32,
      65             :   Match_InvalidImm1_64,
      66             :   Match_InvalidImm1_8,
      67             :   Match_InvalidIndex1,
      68             :   Match_InvalidIndexB,
      69             :   Match_InvalidIndexD,
      70             :   Match_InvalidIndexH,
      71             :   Match_InvalidIndexS,
      72             :   Match_InvalidLabel,
      73             :   Match_InvalidMemoryIndexed1,
      74             :   Match_InvalidMemoryIndexed16,
      75             :   Match_InvalidMemoryIndexed16SImm4,
      76             :   Match_InvalidMemoryIndexed16SImm7,
      77             :   Match_InvalidMemoryIndexed1SImm4,
      78             :   Match_InvalidMemoryIndexed1SImm6,
      79             :   Match_InvalidMemoryIndexed1UImm6,
      80             :   Match_InvalidMemoryIndexed2,
      81             :   Match_InvalidMemoryIndexed2SImm4,
      82             :   Match_InvalidMemoryIndexed2UImm5,
      83             :   Match_InvalidMemoryIndexed2UImm6,
      84             :   Match_InvalidMemoryIndexed3SImm4,
      85             :   Match_InvalidMemoryIndexed4,
      86             :   Match_InvalidMemoryIndexed4SImm4,
      87             :   Match_InvalidMemoryIndexed4SImm7,
      88             :   Match_InvalidMemoryIndexed4UImm5,
      89             :   Match_InvalidMemoryIndexed4UImm6,
      90             :   Match_InvalidMemoryIndexed8,
      91             :   Match_InvalidMemoryIndexed8SImm10,
      92             :   Match_InvalidMemoryIndexed8SImm7,
      93             :   Match_InvalidMemoryIndexed8UImm5,
      94             :   Match_InvalidMemoryIndexed8UImm6,
      95             :   Match_InvalidMemoryIndexedSImm5,
      96             :   Match_InvalidMemoryIndexedSImm6,
      97             :   Match_InvalidMemoryIndexedSImm9,
      98             :   Match_InvalidMemoryWExtend128,
      99             :   Match_InvalidMemoryWExtend16,
     100             :   Match_InvalidMemoryWExtend32,
     101             :   Match_InvalidMemoryWExtend64,
     102             :   Match_InvalidMemoryWExtend8,
     103             :   Match_InvalidMemoryXExtend128,
     104             :   Match_InvalidMemoryXExtend16,
     105             :   Match_InvalidMemoryXExtend32,
     106             :   Match_InvalidMemoryXExtend64,
     107             :   Match_InvalidMemoryXExtend8,
     108             :   Match_InvalidMovImm32Shift,
     109             :   Match_InvalidMovImm64Shift,
     110             :   Match_InvalidSVEPattern,
     111             :   Match_InvalidSVEPredicate3bAnyReg,
     112             :   Match_InvalidSVEPredicate3bBReg,
     113             :   Match_InvalidSVEPredicate3bDReg,
     114             :   Match_InvalidSVEPredicate3bHReg,
     115             :   Match_InvalidSVEPredicate3bSReg,
     116             :   Match_InvalidSVEPredicateAnyReg,
     117             :   Match_InvalidSVEPredicateBReg,
     118             :   Match_InvalidSVEPredicateDReg,
     119             :   Match_InvalidSVEPredicateHReg,
     120             :   Match_InvalidSVEPredicateSReg,
     121             :   Match_InvalidZPR0,
     122             :   Match_InvalidZPR128,
     123             :   Match_InvalidZPR16,
     124             :   Match_InvalidZPR32,
     125             :   Match_InvalidZPR32SXTW16,
     126             :   Match_InvalidZPR32SXTW32,
     127             :   Match_InvalidZPR32SXTW64,
     128             :   Match_InvalidZPR32SXTW8,
     129             :   Match_InvalidZPR32UXTW16,
     130             :   Match_InvalidZPR32UXTW32,
     131             :   Match_InvalidZPR32UXTW64,
     132             :   Match_InvalidZPR32UXTW8,
     133             :   Match_InvalidZPR64,
     134             :   Match_InvalidZPR64LSL16,
     135             :   Match_InvalidZPR64LSL32,
     136             :   Match_InvalidZPR64LSL64,
     137             :   Match_InvalidZPR64LSL8,
     138             :   Match_InvalidZPR64SXTW16,
     139             :   Match_InvalidZPR64SXTW32,
     140             :   Match_InvalidZPR64SXTW64,
     141             :   Match_InvalidZPR64SXTW8,
     142             :   Match_InvalidZPR64UXTW16,
     143             :   Match_InvalidZPR64UXTW32,
     144             :   Match_InvalidZPR64UXTW64,
     145             :   Match_InvalidZPR64UXTW8,
     146             :   Match_InvalidZPR8,
     147             :   Match_LogicalSecondSource,
     148             :   Match_MRS,
     149             :   Match_MSR,
     150             :   END_OPERAND_DIAGNOSTIC_TYPES
     151             : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
     152             : 
     153             : 
     154             : #ifdef GET_REGISTER_MATCHER
     155             : #undef GET_REGISTER_MATCHER
     156             : 
     157             : // Flags for subtarget features that participate in instruction matching.
     158             : enum SubtargetFeatureFlag : uint32_t {
     159             :   Feature_HasV8_1a = (1ULL << 13),
     160             :   Feature_HasV8_2a = (1ULL << 14),
     161             :   Feature_HasV8_3a = (1ULL << 15),
     162             :   Feature_HasFPARMv8 = (1ULL << 3),
     163             :   Feature_HasNEON = (1ULL << 7),
     164             :   Feature_HasCrypto = (1ULL << 1),
     165             :   Feature_HasDotProd = (1ULL << 2),
     166             :   Feature_HasCRC = (1ULL << 0),
     167             :   Feature_HasLSE = (1ULL << 6),
     168             :   Feature_HasRAS = (1ULL << 8),
     169             :   Feature_HasRDM = (1ULL << 10),
     170             :   Feature_HasFullFP16 = (1ULL << 4),
     171             :   Feature_HasSPE = (1ULL << 11),
     172             :   Feature_HasFuseAES = (1ULL << 5),
     173             :   Feature_HasSVE = (1ULL << 12),
     174             :   Feature_HasRCPC = (1ULL << 9),
     175             :   Feature_UseNegativeImmediates = (1ULL << 16),
     176             :   Feature_None = 0
     177             : };
     178             : 
     179      126762 : static unsigned MatchRegisterName(StringRef Name) {
     180      126762 :   switch (Name.size()) {
     181             :   default: break;
     182       91194 :   case 2:        // 91 strings to match.
     183       91194 :     switch (Name[0]) {
     184             :     default: break;
     185        4243 :     case 'b':    // 10 strings to match.
     186        4243 :       switch (Name[1]) {
     187             :       default: break;
     188             :       case '0':  // 1 string to match.
     189             :         return 9;        // "b0"
     190             :       case '1':  // 1 string to match.
     191             :         return 10;       // "b1"
     192             :       case '2':  // 1 string to match.
     193             :         return 11;       // "b2"
     194             :       case '3':  // 1 string to match.
     195             :         return 12;       // "b3"
     196             :       case '4':  // 1 string to match.
     197             :         return 13;       // "b4"
     198             :       case '5':  // 1 string to match.
     199             :         return 14;       // "b5"
     200             :       case '6':  // 1 string to match.
     201             :         return 15;       // "b6"
     202             :       case '7':  // 1 string to match.
     203             :         return 16;       // "b7"
     204             :       case '8':  // 1 string to match.
     205             :         return 17;       // "b8"
     206             :       case '9':  // 1 string to match.
     207             :         return 18;       // "b9"
     208             :       }
     209             :       break;
     210        1787 :     case 'd':    // 10 strings to match.
     211        1787 :       switch (Name[1]) {
     212             :       default: break;
     213             :       case '0':  // 1 string to match.
     214             :         return 41;       // "d0"
     215             :       case '1':  // 1 string to match.
     216             :         return 42;       // "d1"
     217             :       case '2':  // 1 string to match.
     218             :         return 43;       // "d2"
     219             :       case '3':  // 1 string to match.
     220             :         return 44;       // "d3"
     221             :       case '4':  // 1 string to match.
     222             :         return 45;       // "d4"
     223             :       case '5':  // 1 string to match.
     224             :         return 46;       // "d5"
     225             :       case '6':  // 1 string to match.
     226             :         return 47;       // "d6"
     227             :       case '7':  // 1 string to match.
     228             :         return 48;       // "d7"
     229             :       case '8':  // 1 string to match.
     230             :         return 49;       // "d8"
     231             :       case '9':  // 1 string to match.
     232             :         return 50;       // "d9"
     233             :       }
     234             :       break;
     235        4439 :     case 'h':    // 10 strings to match.
     236        4439 :       switch (Name[1]) {
     237             :       default: break;
     238             :       case '0':  // 1 string to match.
     239             :         return 73;       // "h0"
     240             :       case '1':  // 1 string to match.
     241             :         return 74;       // "h1"
     242             :       case '2':  // 1 string to match.
     243             :         return 75;       // "h2"
     244             :       case '3':  // 1 string to match.
     245             :         return 76;       // "h3"
     246             :       case '4':  // 1 string to match.
     247             :         return 77;       // "h4"
     248             :       case '5':  // 1 string to match.
     249             :         return 78;       // "h5"
     250             :       case '6':  // 1 string to match.
     251             :         return 79;       // "h6"
     252             :       case '7':  // 1 string to match.
     253             :         return 80;       // "h7"
     254             :       case '8':  // 1 string to match.
     255             :         return 81;       // "h8"
     256             :       case '9':  // 1 string to match.
     257             :         return 82;       // "h9"
     258             :       }
     259             :       break;
     260           0 :     case 'p':    // 10 strings to match.
     261           0 :       switch (Name[1]) {
     262             :       default: break;
     263             :       case '0':  // 1 string to match.
     264             :         return 105;      // "p0"
     265             :       case '1':  // 1 string to match.
     266             :         return 106;      // "p1"
     267             :       case '2':  // 1 string to match.
     268             :         return 107;      // "p2"
     269             :       case '3':  // 1 string to match.
     270             :         return 108;      // "p3"
     271             :       case '4':  // 1 string to match.
     272             :         return 109;      // "p4"
     273             :       case '5':  // 1 string to match.
     274             :         return 110;      // "p5"
     275             :       case '6':  // 1 string to match.
     276             :         return 111;      // "p6"
     277             :       case '7':  // 1 string to match.
     278             :         return 112;      // "p7"
     279             :       case '8':  // 1 string to match.
     280             :         return 113;      // "p8"
     281             :       case '9':  // 1 string to match.
     282             :         return 114;      // "p9"
     283             :       }
     284             :       break;
     285         561 :     case 'q':    // 10 strings to match.
     286         561 :       switch (Name[1]) {
     287             :       default: break;
     288             :       case '0':  // 1 string to match.
     289             :         return 121;      // "q0"
     290             :       case '1':  // 1 string to match.
     291             :         return 122;      // "q1"
     292             :       case '2':  // 1 string to match.
     293             :         return 123;      // "q2"
     294             :       case '3':  // 1 string to match.
     295             :         return 124;      // "q3"
     296             :       case '4':  // 1 string to match.
     297             :         return 125;      // "q4"
     298             :       case '5':  // 1 string to match.
     299             :         return 126;      // "q5"
     300             :       case '6':  // 1 string to match.
     301             :         return 127;      // "q6"
     302             :       case '7':  // 1 string to match.
     303             :         return 128;      // "q7"
     304             :       case '8':  // 1 string to match.
     305             :         return 129;      // "q8"
     306             :       case '9':  // 1 string to match.
     307             :         return 130;      // "q9"
     308             :       }
     309             :       break;
     310       13573 :     case 's':    // 11 strings to match.
     311       13573 :       switch (Name[1]) {
     312             :       default: break;
     313             :       case '0':  // 1 string to match.
     314             :         return 153;      // "s0"
     315             :       case '1':  // 1 string to match.
     316             :         return 154;      // "s1"
     317             :       case '2':  // 1 string to match.
     318             :         return 155;      // "s2"
     319             :       case '3':  // 1 string to match.
     320             :         return 156;      // "s3"
     321             :       case '4':  // 1 string to match.
     322             :         return 157;      // "s4"
     323             :       case '5':  // 1 string to match.
     324             :         return 158;      // "s5"
     325             :       case '6':  // 1 string to match.
     326             :         return 159;      // "s6"
     327             :       case '7':  // 1 string to match.
     328             :         return 160;      // "s7"
     329             :       case '8':  // 1 string to match.
     330             :         return 161;      // "s8"
     331             :       case '9':  // 1 string to match.
     332             :         return 162;      // "s9"
     333             :       case 'p':  // 1 string to match.
     334             :         return 5;        // "sp"
     335             :       }
     336             :       break;
     337       16748 :     case 'w':    // 10 strings to match.
     338       16748 :       switch (Name[1]) {
     339             :       default: break;
     340             :       case '0':  // 1 string to match.
     341             :         return 185;      // "w0"
     342             :       case '1':  // 1 string to match.
     343             :         return 186;      // "w1"
     344             :       case '2':  // 1 string to match.
     345             :         return 187;      // "w2"
     346             :       case '3':  // 1 string to match.
     347             :         return 188;      // "w3"
     348             :       case '4':  // 1 string to match.
     349             :         return 189;      // "w4"
     350             :       case '5':  // 1 string to match.
     351             :         return 190;      // "w5"
     352             :       case '6':  // 1 string to match.
     353             :         return 191;      // "w6"
     354             :       case '7':  // 1 string to match.
     355             :         return 192;      // "w7"
     356             :       case '8':  // 1 string to match.
     357             :         return 193;      // "w8"
     358             :       case '9':  // 1 string to match.
     359             :         return 194;      // "w9"
     360             :       }
     361             :       break;
     362       49676 :     case 'x':    // 10 strings to match.
     363       49676 :       switch (Name[1]) {
     364             :       default: break;
     365             :       case '0':  // 1 string to match.
     366             :         return 216;      // "x0"
     367             :       case '1':  // 1 string to match.
     368             :         return 217;      // "x1"
     369             :       case '2':  // 1 string to match.
     370             :         return 218;      // "x2"
     371             :       case '3':  // 1 string to match.
     372             :         return 219;      // "x3"
     373             :       case '4':  // 1 string to match.
     374             :         return 220;      // "x4"
     375             :       case '5':  // 1 string to match.
     376             :         return 221;      // "x5"
     377             :       case '6':  // 1 string to match.
     378             :         return 222;      // "x6"
     379             :       case '7':  // 1 string to match.
     380             :         return 223;      // "x7"
     381             :       case '8':  // 1 string to match.
     382             :         return 224;      // "x8"
     383             :       case '9':  // 1 string to match.
     384             :         return 225;      // "x9"
     385             :       }
     386             :       break;
     387           0 :     case 'z':    // 10 strings to match.
     388           0 :       switch (Name[1]) {
     389             :       default: break;
     390             :       case '0':  // 1 string to match.
     391             :         return 245;      // "z0"
     392             :       case '1':  // 1 string to match.
     393             :         return 246;      // "z1"
     394             :       case '2':  // 1 string to match.
     395             :         return 247;      // "z2"
     396             :       case '3':  // 1 string to match.
     397             :         return 248;      // "z3"
     398             :       case '4':  // 1 string to match.
     399             :         return 249;      // "z4"
     400             :       case '5':  // 1 string to match.
     401             :         return 250;      // "z5"
     402             :       case '6':  // 1 string to match.
     403             :         return 251;      // "z6"
     404             :       case '7':  // 1 string to match.
     405             :         return 252;      // "z7"
     406             :       case '8':  // 1 string to match.
     407             :         return 253;      // "z8"
     408             :       case '9':  // 1 string to match.
     409             :         return 254;      // "z9"
     410             :       }
     411             :       break;
     412             :     }
     413             :     break;
     414       32300 :   case 3:        // 184 strings to match.
     415       32300 :     switch (Name[0]) {
     416             :     default: break;
     417         286 :     case 'b':    // 22 strings to match.
     418         286 :       switch (Name[1]) {
     419             :       default: break;
     420         226 :       case '1':  // 10 strings to match.
     421         226 :         switch (Name[2]) {
     422             :         default: break;
     423             :         case '0':        // 1 string to match.
     424             :           return 19;     // "b10"
     425             :         case '1':        // 1 string to match.
     426             :           return 20;     // "b11"
     427             :         case '2':        // 1 string to match.
     428             :           return 21;     // "b12"
     429             :         case '3':        // 1 string to match.
     430             :           return 22;     // "b13"
     431             :         case '4':        // 1 string to match.
     432             :           return 23;     // "b14"
     433             :         case '5':        // 1 string to match.
     434             :           return 24;     // "b15"
     435             :         case '6':        // 1 string to match.
     436             :           return 25;     // "b16"
     437             :         case '7':        // 1 string to match.
     438             :           return 26;     // "b17"
     439             :         case '8':        // 1 string to match.
     440             :           return 27;     // "b18"
     441             :         case '9':        // 1 string to match.
     442             :           return 28;     // "b19"
     443             :         }
     444             :         break;
     445          22 :       case '2':  // 10 strings to match.
     446          22 :         switch (Name[2]) {
     447             :         default: break;
     448             :         case '0':        // 1 string to match.
     449             :           return 29;     // "b20"
     450             :         case '1':        // 1 string to match.
     451             :           return 30;     // "b21"
     452             :         case '2':        // 1 string to match.
     453             :           return 31;     // "b22"
     454             :         case '3':        // 1 string to match.
     455             :           return 32;     // "b23"
     456             :         case '4':        // 1 string to match.
     457             :           return 33;     // "b24"
     458             :         case '5':        // 1 string to match.
     459             :           return 34;     // "b25"
     460             :         case '6':        // 1 string to match.
     461             :           return 35;     // "b26"
     462             :         case '7':        // 1 string to match.
     463             :           return 36;     // "b27"
     464             :         case '8':        // 1 string to match.
     465             :           return 37;     // "b28"
     466             :         case '9':        // 1 string to match.
     467             :           return 38;     // "b29"
     468             :         }
     469             :         break;
     470          10 :       case '3':  // 2 strings to match.
     471          10 :         switch (Name[2]) {
     472             :         default: break;
     473             :         case '0':        // 1 string to match.
     474             :           return 39;     // "b30"
     475          10 :         case '1':        // 1 string to match.
     476          10 :           return 40;     // "b31"
     477             :         }
     478             :         break;
     479             :       }
     480             :       break;
     481        1272 :     case 'd':    // 22 strings to match.
     482        1272 :       switch (Name[1]) {
     483             :       default: break;
     484         412 :       case '1':  // 10 strings to match.
     485         412 :         switch (Name[2]) {
     486             :         default: break;
     487             :         case '0':        // 1 string to match.
     488             :           return 51;     // "d10"
     489             :         case '1':        // 1 string to match.
     490             :           return 52;     // "d11"
     491             :         case '2':        // 1 string to match.
     492             :           return 53;     // "d12"
     493             :         case '3':        // 1 string to match.
     494             :           return 54;     // "d13"
     495             :         case '4':        // 1 string to match.
     496             :           return 55;     // "d14"
     497             :         case '5':        // 1 string to match.
     498             :           return 56;     // "d15"
     499             :         case '6':        // 1 string to match.
     500             :           return 57;     // "d16"
     501             :         case '7':        // 1 string to match.
     502             :           return 58;     // "d17"
     503             :         case '8':        // 1 string to match.
     504             :           return 59;     // "d18"
     505             :         case '9':        // 1 string to match.
     506             :           return 60;     // "d19"
     507             :         }
     508             :         break;
     509         760 :       case '2':  // 10 strings to match.
     510         760 :         switch (Name[2]) {
     511             :         default: break;
     512             :         case '0':        // 1 string to match.
     513             :           return 61;     // "d20"
     514             :         case '1':        // 1 string to match.
     515             :           return 62;     // "d21"
     516             :         case '2':        // 1 string to match.
     517             :           return 63;     // "d22"
     518             :         case '3':        // 1 string to match.
     519             :           return 64;     // "d23"
     520             :         case '4':        // 1 string to match.
     521             :           return 65;     // "d24"
     522             :         case '5':        // 1 string to match.
     523             :           return 66;     // "d25"
     524             :         case '6':        // 1 string to match.
     525             :           return 67;     // "d26"
     526             :         case '7':        // 1 string to match.
     527             :           return 68;     // "d27"
     528             :         case '8':        // 1 string to match.
     529             :           return 69;     // "d28"
     530             :         case '9':        // 1 string to match.
     531             :           return 70;     // "d29"
     532             :         }
     533             :         break;
     534         100 :       case '3':  // 2 strings to match.
     535         100 :         switch (Name[2]) {
     536             :         default: break;
     537             :         case '0':        // 1 string to match.
     538             :           return 71;     // "d30"
     539          80 :         case '1':        // 1 string to match.
     540          80 :           return 72;     // "d31"
     541             :         }
     542             :         break;
     543             :       }
     544             :       break;
     545             :     case 'f':    // 1 string to match.
     546          46 :       if (memcmp(Name.data()+1, "fr", 2) != 0)
     547             :         break;
     548             :       return 1;  // "ffr"
     549        1076 :     case 'h':    // 22 strings to match.
     550        1076 :       switch (Name[1]) {
     551             :       default: break;
     552         906 :       case '1':  // 10 strings to match.
     553         906 :         switch (Name[2]) {
     554             :         default: break;
     555             :         case '0':        // 1 string to match.
     556             :           return 83;     // "h10"
     557             :         case '1':        // 1 string to match.
     558             :           return 84;     // "h11"
     559             :         case '2':        // 1 string to match.
     560             :           return 85;     // "h12"
     561             :         case '3':        // 1 string to match.
     562             :           return 86;     // "h13"
     563             :         case '4':        // 1 string to match.
     564             :           return 87;     // "h14"
     565             :         case '5':        // 1 string to match.
     566             :           return 88;     // "h15"
     567             :         case '6':        // 1 string to match.
     568             :           return 89;     // "h16"
     569             :         case '7':        // 1 string to match.
     570             :           return 90;     // "h17"
     571             :         case '8':        // 1 string to match.
     572             :           return 91;     // "h18"
     573             :         case '9':        // 1 string to match.
     574             :           return 92;     // "h19"
     575             :         }
     576             :         break;
     577         150 :       case '2':  // 10 strings to match.
     578         150 :         switch (Name[2]) {
     579             :         default: break;
     580             :         case '0':        // 1 string to match.
     581             :           return 93;     // "h20"
     582             :         case '1':        // 1 string to match.
     583             :           return 94;     // "h21"
     584             :         case '2':        // 1 string to match.
     585             :           return 95;     // "h22"
     586             :         case '3':        // 1 string to match.
     587             :           return 96;     // "h23"
     588             :         case '4':        // 1 string to match.
     589             :           return 97;     // "h24"
     590             :         case '5':        // 1 string to match.
     591             :           return 98;     // "h25"
     592             :         case '6':        // 1 string to match.
     593             :           return 99;     // "h26"
     594             :         case '7':        // 1 string to match.
     595             :           return 100;    // "h27"
     596             :         case '8':        // 1 string to match.
     597             :           return 101;    // "h28"
     598             :         case '9':        // 1 string to match.
     599             :           return 102;    // "h29"
     600             :         }
     601             :         break;
     602          20 :       case '3':  // 2 strings to match.
     603          20 :         switch (Name[2]) {
     604             :         default: break;
     605             :         case '0':        // 1 string to match.
     606             :           return 103;    // "h30"
     607          10 :         case '1':        // 1 string to match.
     608          10 :           return 104;    // "h31"
     609             :         }
     610             :         break;
     611             :       }
     612             :       break;
     613          34 :     case 'p':    // 6 strings to match.
     614          34 :       if (Name[1] != '1')
     615             :         break;
     616          34 :       switch (Name[2]) {
     617             :       default: break;
     618             :       case '0':  // 1 string to match.
     619             :         return 115;      // "p10"
     620             :       case '1':  // 1 string to match.
     621             :         return 116;      // "p11"
     622             :       case '2':  // 1 string to match.
     623             :         return 117;      // "p12"
     624             :       case '3':  // 1 string to match.
     625             :         return 118;      // "p13"
     626             :       case '4':  // 1 string to match.
     627             :         return 119;      // "p14"
     628             :       case '5':  // 1 string to match.
     629             :         return 120;      // "p15"
     630             :       }
     631             :       break;
     632         744 :     case 'q':    // 22 strings to match.
     633         744 :       switch (Name[1]) {
     634             :       default: break;
     635         174 :       case '1':  // 10 strings to match.
     636         174 :         switch (Name[2]) {
     637             :         default: break;
     638             :         case '0':        // 1 string to match.
     639             :           return 131;    // "q10"
     640             :         case '1':        // 1 string to match.
     641             :           return 132;    // "q11"
     642             :         case '2':        // 1 string to match.
     643             :           return 133;    // "q12"
     644             :         case '3':        // 1 string to match.
     645             :           return 134;    // "q13"
     646             :         case '4':        // 1 string to match.
     647             :           return 135;    // "q14"
     648             :         case '5':        // 1 string to match.
     649             :           return 136;    // "q15"
     650             :         case '6':        // 1 string to match.
     651             :           return 137;    // "q16"
     652             :         case '7':        // 1 string to match.
     653             :           return 138;    // "q17"
     654             :         case '8':        // 1 string to match.
     655             :           return 139;    // "q18"
     656             :         case '9':        // 1 string to match.
     657             :           return 140;    // "q19"
     658             :         }
     659             :         break;
     660         562 :       case '2':  // 10 strings to match.
     661         562 :         switch (Name[2]) {
     662             :         default: break;
     663             :         case '0':        // 1 string to match.
     664             :           return 141;    // "q20"
     665             :         case '1':        // 1 string to match.
     666             :           return 142;    // "q21"
     667             :         case '2':        // 1 string to match.
     668             :           return 143;    // "q22"
     669             :         case '3':        // 1 string to match.
     670             :           return 144;    // "q23"
     671             :         case '4':        // 1 string to match.
     672             :           return 145;    // "q24"
     673             :         case '5':        // 1 string to match.
     674             :           return 146;    // "q25"
     675             :         case '6':        // 1 string to match.
     676             :           return 147;    // "q26"
     677             :         case '7':        // 1 string to match.
     678             :           return 148;    // "q27"
     679             :         case '8':        // 1 string to match.
     680             :           return 149;    // "q28"
     681             :         case '9':        // 1 string to match.
     682             :           return 150;    // "q29"
     683             :         }
     684             :         break;
     685           8 :       case '3':  // 2 strings to match.
     686           8 :         switch (Name[2]) {
     687             :         default: break;
     688             :         case '0':        // 1 string to match.
     689             :           return 151;    // "q30"
     690           0 :         case '1':        // 1 string to match.
     691           0 :           return 152;    // "q31"
     692             :         }
     693             :         break;
     694             :       }
     695             :       break;
     696        1150 :     case 's':    // 22 strings to match.
     697        1150 :       switch (Name[1]) {
     698             :       default: break;
     699         514 :       case '1':  // 10 strings to match.
     700         514 :         switch (Name[2]) {
     701             :         default: break;
     702             :         case '0':        // 1 string to match.
     703             :           return 163;    // "s10"
     704             :         case '1':        // 1 string to match.
     705             :           return 164;    // "s11"
     706             :         case '2':        // 1 string to match.
     707             :           return 165;    // "s12"
     708             :         case '3':        // 1 string to match.
     709             :           return 166;    // "s13"
     710             :         case '4':        // 1 string to match.
     711             :           return 167;    // "s14"
     712             :         case '5':        // 1 string to match.
     713             :           return 168;    // "s15"
     714             :         case '6':        // 1 string to match.
     715             :           return 169;    // "s16"
     716             :         case '7':        // 1 string to match.
     717             :           return 170;    // "s17"
     718             :         case '8':        // 1 string to match.
     719             :           return 171;    // "s18"
     720             :         case '9':        // 1 string to match.
     721             :           return 172;    // "s19"
     722             :         }
     723             :         break;
     724         528 :       case '2':  // 10 strings to match.
     725         528 :         switch (Name[2]) {
     726             :         default: break;
     727             :         case '0':        // 1 string to match.
     728             :           return 173;    // "s20"
     729             :         case '1':        // 1 string to match.
     730             :           return 174;    // "s21"
     731             :         case '2':        // 1 string to match.
     732             :           return 175;    // "s22"
     733             :         case '3':        // 1 string to match.
     734             :           return 176;    // "s23"
     735             :         case '4':        // 1 string to match.
     736             :           return 177;    // "s24"
     737             :         case '5':        // 1 string to match.
     738             :           return 178;    // "s25"
     739             :         case '6':        // 1 string to match.
     740             :           return 179;    // "s26"
     741             :         case '7':        // 1 string to match.
     742             :           return 180;    // "s27"
     743             :         case '8':        // 1 string to match.
     744             :           return 181;    // "s28"
     745             :         case '9':        // 1 string to match.
     746             :           return 182;    // "s29"
     747             :         }
     748             :         break;
     749         100 :       case '3':  // 2 strings to match.
     750         100 :         switch (Name[2]) {
     751             :         default: break;
     752             :         case '0':        // 1 string to match.
     753             :           return 183;    // "s30"
     754          72 :         case '1':        // 1 string to match.
     755          72 :           return 184;    // "s31"
     756             :         }
     757             :         break;
     758             :       }
     759             :       break;
     760        6053 :     case 'w':    // 23 strings to match.
     761        6053 :       switch (Name[1]) {
     762             :       default: break;
     763        2339 :       case '1':  // 10 strings to match.
     764        2339 :         switch (Name[2]) {
     765             :         default: break;
     766             :         case '0':        // 1 string to match.
     767             :           return 195;    // "w10"
     768             :         case '1':        // 1 string to match.
     769             :           return 196;    // "w11"
     770             :         case '2':        // 1 string to match.
     771             :           return 197;    // "w12"
     772             :         case '3':        // 1 string to match.
     773             :           return 198;    // "w13"
     774             :         case '4':        // 1 string to match.
     775             :           return 199;    // "w14"
     776             :         case '5':        // 1 string to match.
     777             :           return 200;    // "w15"
     778             :         case '6':        // 1 string to match.
     779             :           return 201;    // "w16"
     780             :         case '7':        // 1 string to match.
     781             :           return 202;    // "w17"
     782             :         case '8':        // 1 string to match.
     783             :           return 203;    // "w18"
     784             :         case '9':        // 1 string to match.
     785             :           return 204;    // "w19"
     786             :         }
     787             :         break;
     788        2094 :       case '2':  // 10 strings to match.
     789        2094 :         switch (Name[2]) {
     790             :         default: break;
     791             :         case '0':        // 1 string to match.
     792             :           return 205;    // "w20"
     793             :         case '1':        // 1 string to match.
     794             :           return 206;    // "w21"
     795             :         case '2':        // 1 string to match.
     796             :           return 207;    // "w22"
     797             :         case '3':        // 1 string to match.
     798             :           return 208;    // "w23"
     799             :         case '4':        // 1 string to match.
     800             :           return 209;    // "w24"
     801             :         case '5':        // 1 string to match.
     802             :           return 210;    // "w25"
     803             :         case '6':        // 1 string to match.
     804             :           return 211;    // "w26"
     805             :         case '7':        // 1 string to match.
     806             :           return 212;    // "w27"
     807             :         case '8':        // 1 string to match.
     808             :           return 213;    // "w28"
     809             :         case '9':        // 1 string to match.
     810             :           return 214;    // "w29"
     811             :         }
     812             :         break;
     813         176 :       case '3':  // 1 string to match.
     814         176 :         if (Name[2] != '0')
     815             :           break;
     816             :         return 215;      // "w30"
     817         638 :       case 's':  // 1 string to match.
     818         638 :         if (Name[2] != 'p')
     819             :           break;
     820             :         return 6;        // "wsp"
     821         806 :       case 'z':  // 1 string to match.
     822         806 :         if (Name[2] != 'r')
     823             :           break;
     824             :         return 7;        // "wzr"
     825             :       }
     826             :       break;
     827       18299 :     case 'x':    // 22 strings to match.
     828       18299 :       switch (Name[1]) {
     829             :       default: break;
     830       12727 :       case '1':  // 10 strings to match.
     831       12727 :         switch (Name[2]) {
     832             :         default: break;
     833             :         case '0':        // 1 string to match.
     834             :           return 226;    // "x10"
     835             :         case '1':        // 1 string to match.
     836             :           return 227;    // "x11"
     837             :         case '2':        // 1 string to match.
     838             :           return 228;    // "x12"
     839             :         case '3':        // 1 string to match.
     840             :           return 229;    // "x13"
     841             :         case '4':        // 1 string to match.
     842             :           return 230;    // "x14"
     843             :         case '5':        // 1 string to match.
     844             :           return 231;    // "x15"
     845             :         case '6':        // 1 string to match.
     846             :           return 232;    // "x16"
     847             :         case '7':        // 1 string to match.
     848             :           return 233;    // "x17"
     849             :         case '8':        // 1 string to match.
     850             :           return 234;    // "x18"
     851             :         case '9':        // 1 string to match.
     852             :           return 235;    // "x19"
     853             :         }
     854             :         break;
     855        4223 :       case '2':  // 10 strings to match.
     856        4223 :         switch (Name[2]) {
     857             :         default: break;
     858             :         case '0':        // 1 string to match.
     859             :           return 236;    // "x20"
     860             :         case '1':        // 1 string to match.
     861             :           return 237;    // "x21"
     862             :         case '2':        // 1 string to match.
     863             :           return 238;    // "x22"
     864             :         case '3':        // 1 string to match.
     865             :           return 239;    // "x23"
     866             :         case '4':        // 1 string to match.
     867             :           return 240;    // "x24"
     868             :         case '5':        // 1 string to match.
     869             :           return 241;    // "x25"
     870             :         case '6':        // 1 string to match.
     871             :           return 242;    // "x26"
     872             :         case '7':        // 1 string to match.
     873             :           return 243;    // "x27"
     874             :         case '8':        // 1 string to match.
     875             :           return 244;    // "x28"
     876             :         case '9':        // 1 string to match.
     877             :           return 2;      // "x29"
     878             :         }
     879             :         break;
     880         492 :       case '3':  // 1 string to match.
     881         492 :         if (Name[2] != '0')
     882             :           break;
     883             :         return 3;        // "x30"
     884         819 :       case 'z':  // 1 string to match.
     885         819 :         if (Name[2] != 'r')
     886             :           break;
     887             :         return 8;        // "xzr"
     888             :       }
     889             :       break;
     890          70 :     case 'z':    // 22 strings to match.
     891          70 :       switch (Name[1]) {
     892             :       default: break;
     893           0 :       case '1':  // 10 strings to match.
     894           0 :         switch (Name[2]) {
     895             :         default: break;
     896             :         case '0':        // 1 string to match.
     897             :           return 255;    // "z10"
     898             :         case '1':        // 1 string to match.
     899             :           return 256;    // "z11"
     900             :         case '2':        // 1 string to match.
     901             :           return 257;    // "z12"
     902             :         case '3':        // 1 string to match.
     903             :           return 258;    // "z13"
     904             :         case '4':        // 1 string to match.
     905             :           return 259;    // "z14"
     906             :         case '5':        // 1 string to match.
     907             :           return 260;    // "z15"
     908             :         case '6':        // 1 string to match.
     909             :           return 261;    // "z16"
     910             :         case '7':        // 1 string to match.
     911             :           return 262;    // "z17"
     912             :         case '8':        // 1 string to match.
     913             :           return 263;    // "z18"
     914             :         case '9':        // 1 string to match.
     915             :           return 264;    // "z19"
     916             :         }
     917             :         break;
     918           0 :       case '2':  // 10 strings to match.
     919           0 :         switch (Name[2]) {
     920             :         default: break;
     921             :         case '0':        // 1 string to match.
     922             :           return 265;    // "z20"
     923             :         case '1':        // 1 string to match.
     924             :           return 266;    // "z21"
     925             :         case '2':        // 1 string to match.
     926             :           return 267;    // "z22"
     927             :         case '3':        // 1 string to match.
     928             :           return 268;    // "z23"
     929             :         case '4':        // 1 string to match.
     930             :           return 269;    // "z24"
     931             :         case '5':        // 1 string to match.
     932             :           return 270;    // "z25"
     933             :         case '6':        // 1 string to match.
     934             :           return 271;    // "z26"
     935             :         case '7':        // 1 string to match.
     936             :           return 272;    // "z27"
     937             :         case '8':        // 1 string to match.
     938             :           return 273;    // "z28"
     939             :         case '9':        // 1 string to match.
     940             :           return 274;    // "z29"
     941             :         }
     942             :         break;
     943          52 :       case '3':  // 2 strings to match.
     944          52 :         switch (Name[2]) {
     945             :         default: break;
     946             :         case '0':        // 1 string to match.
     947             :           return 275;    // "z30"
     948           0 :         case '1':        // 1 string to match.
     949           0 :           return 276;    // "z31"
     950             :         }
     951             :         break;
     952             :       }
     953             :       break;
     954             :     }
     955             :     break;
     956             :   case 4:        // 1 string to match.
     957        2051 :     if (memcmp(Name.data()+0, "nzcv", 4) != 0)
     958             :       break;
     959             :     return 4;    // "nzcv"
     960         822 :   case 5:        // 10 strings to match.
     961         822 :     if (Name[0] != 'z')
     962             :       break;
     963         676 :     switch (Name[1]) {
     964             :     default: break;
     965             :     case '0':    // 1 string to match.
     966           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     967             :         break;
     968             :       return 277;        // "z0_hi"
     969             :     case '1':    // 1 string to match.
     970           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     971             :         break;
     972             :       return 278;        // "z1_hi"
     973             :     case '2':    // 1 string to match.
     974         384 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     975             :         break;
     976             :       return 279;        // "z2_hi"
     977             :     case '3':    // 1 string to match.
     978         292 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     979             :         break;
     980             :       return 280;        // "z3_hi"
     981             :     case '4':    // 1 string to match.
     982           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     983             :         break;
     984             :       return 281;        // "z4_hi"
     985             :     case '5':    // 1 string to match.
     986           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     987             :         break;
     988             :       return 282;        // "z5_hi"
     989             :     case '6':    // 1 string to match.
     990           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     991             :         break;
     992             :       return 283;        // "z6_hi"
     993             :     case '7':    // 1 string to match.
     994           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     995             :         break;
     996             :       return 284;        // "z7_hi"
     997             :     case '8':    // 1 string to match.
     998           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
     999             :         break;
    1000             :       return 285;        // "z8_hi"
    1001             :     case '9':    // 1 string to match.
    1002           0 :       if (memcmp(Name.data()+2, "_hi", 3) != 0)
    1003             :         break;
    1004             :       return 286;        // "z9_hi"
    1005             :     }
    1006             :     break;
    1007          60 :   case 6:        // 22 strings to match.
    1008          60 :     if (Name[0] != 'z')
    1009             :       break;
    1010           0 :     switch (Name[1]) {
    1011             :     default: break;
    1012           0 :     case '1':    // 10 strings to match.
    1013           0 :       switch (Name[2]) {
    1014             :       default: break;
    1015             :       case '0':  // 1 string to match.
    1016           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1017             :           break;
    1018             :         return 287;      // "z10_hi"
    1019             :       case '1':  // 1 string to match.
    1020           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1021             :           break;
    1022             :         return 288;      // "z11_hi"
    1023             :       case '2':  // 1 string to match.
    1024           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1025             :           break;
    1026             :         return 289;      // "z12_hi"
    1027             :       case '3':  // 1 string to match.
    1028           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1029             :           break;
    1030             :         return 290;      // "z13_hi"
    1031             :       case '4':  // 1 string to match.
    1032           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1033             :           break;
    1034             :         return 291;      // "z14_hi"
    1035             :       case '5':  // 1 string to match.
    1036           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1037             :           break;
    1038             :         return 292;      // "z15_hi"
    1039             :       case '6':  // 1 string to match.
    1040           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1041             :           break;
    1042             :         return 293;      // "z16_hi"
    1043             :       case '7':  // 1 string to match.
    1044           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1045             :           break;
    1046             :         return 294;      // "z17_hi"
    1047             :       case '8':  // 1 string to match.
    1048           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1049             :           break;
    1050             :         return 295;      // "z18_hi"
    1051             :       case '9':  // 1 string to match.
    1052           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1053             :           break;
    1054             :         return 296;      // "z19_hi"
    1055             :       }
    1056             :       break;
    1057           0 :     case '2':    // 10 strings to match.
    1058           0 :       switch (Name[2]) {
    1059             :       default: break;
    1060             :       case '0':  // 1 string to match.
    1061           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1062             :           break;
    1063             :         return 297;      // "z20_hi"
    1064             :       case '1':  // 1 string to match.
    1065           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1066             :           break;
    1067             :         return 298;      // "z21_hi"
    1068             :       case '2':  // 1 string to match.
    1069           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1070             :           break;
    1071             :         return 299;      // "z22_hi"
    1072             :       case '3':  // 1 string to match.
    1073           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1074             :           break;
    1075             :         return 300;      // "z23_hi"
    1076             :       case '4':  // 1 string to match.
    1077           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1078             :           break;
    1079             :         return 301;      // "z24_hi"
    1080             :       case '5':  // 1 string to match.
    1081           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1082             :           break;
    1083             :         return 302;      // "z25_hi"
    1084             :       case '6':  // 1 string to match.
    1085           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1086             :           break;
    1087             :         return 303;      // "z26_hi"
    1088             :       case '7':  // 1 string to match.
    1089           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1090             :           break;
    1091             :         return 304;      // "z27_hi"
    1092             :       case '8':  // 1 string to match.
    1093           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1094             :           break;
    1095             :         return 305;      // "z28_hi"
    1096             :       case '9':  // 1 string to match.
    1097           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1098             :           break;
    1099             :         return 306;      // "z29_hi"
    1100             :       }
    1101             :       break;
    1102           0 :     case '3':    // 2 strings to match.
    1103           0 :       switch (Name[2]) {
    1104             :       default: break;
    1105             :       case '0':  // 1 string to match.
    1106           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1107             :           break;
    1108             :         return 307;      // "z30_hi"
    1109             :       case '1':  // 1 string to match.
    1110           0 :         if (memcmp(Name.data()+3, "_hi", 3) != 0)
    1111             :           break;
    1112             :         return 308;      // "z31_hi"
    1113             :       }
    1114             :       break;
    1115             :     }
    1116             :     break;
    1117             :   }
    1118             :   return 0;
    1119             : }
    1120             : 
    1121             : #endif // GET_REGISTER_MATCHER
    1122             : 
    1123             : 
    1124             : #ifdef GET_SUBTARGET_FEATURE_NAME
    1125             : #undef GET_SUBTARGET_FEATURE_NAME
    1126             : 
    1127             : // User-level names for subtarget features that participate in
    1128             : // instruction matching.
    1129        1783 : static const char *getSubtargetFeatureName(uint64_t Val) {
    1130        1783 :   switch(Val) {
    1131             :   case Feature_HasV8_1a: return "armv8.1a";
    1132           0 :   case Feature_HasV8_2a: return "armv8.2a";
    1133          80 :   case Feature_HasV8_3a: return "armv8.3a";
    1134           3 :   case Feature_HasFPARMv8: return "fp-armv8";
    1135         199 :   case Feature_HasNEON: return "neon";
    1136          17 :   case Feature_HasCrypto: return "crypto";
    1137          10 :   case Feature_HasDotProd: return "dotprod";
    1138          19 :   case Feature_HasCRC: return "crc";
    1139           4 :   case Feature_HasLSE: return "lse";
    1140           1 :   case Feature_HasRAS: return "ras";
    1141           0 :   case Feature_HasRDM: return "rdm";
    1142         335 :   case Feature_HasFullFP16: return "fullfp16";
    1143           1 :   case Feature_HasSPE: return "spe";
    1144           0 :   case Feature_HasFuseAES: return "fuse-aes";
    1145        1080 :   case Feature_HasSVE: return "sve";
    1146           6 :   case Feature_HasRCPC: return "rcpc";
    1147          28 :   case Feature_UseNegativeImmediates: return "NegativeImmediates";
    1148           0 :   default: return "(unknown)";
    1149             :   }
    1150             : }
    1151             : 
    1152             : #endif // GET_SUBTARGET_FEATURE_NAME
    1153             : 
    1154             : 
    1155             : #ifdef GET_MATCHER_IMPLEMENTATION
    1156             : #undef GET_MATCHER_IMPLEMENTATION
    1157             : 
    1158             : enum {
    1159             :   Tie0_1_1,
    1160             :   Tie0_1_2,
    1161             :   Tie0_1_5,
    1162             :   Tie0_2_2,
    1163             :   Tie0_3_3,
    1164             :   Tie0_4_4,
    1165             :   Tie0_5_5,
    1166             :   Tie1_1_1,
    1167             :   Tie1_2_2,
    1168             : };
    1169             : 
    1170             : const char TiedAsmOperandTable[][3] = {
    1171             :   /* Tie0_1_1 */ { 0, 1, 1 },
    1172             :   /* Tie0_1_2 */ { 0, 1, 2 },
    1173             :   /* Tie0_1_5 */ { 0, 1, 5 },
    1174             :   /* Tie0_2_2 */ { 0, 2, 2 },
    1175             :   /* Tie0_3_3 */ { 0, 3, 3 },
    1176             :   /* Tie0_4_4 */ { 0, 4, 4 },
    1177             :   /* Tie0_5_5 */ { 0, 5, 5 },
    1178             :   /* Tie1_1_1 */ { 1, 1, 1 },
    1179             :   /* Tie1_2_2 */ { 1, 2, 2 },
    1180             : };
    1181             : 
    1182             : namespace {
    1183             : enum OperatorConversionKind {
    1184             :   CVT_Done,
    1185             :   CVT_Reg,
    1186             :   CVT_Tied,
    1187             :   CVT_95_Reg,
    1188             :   CVT_95_addVectorReg128Operands,
    1189             :   CVT_95_addVectorReg64Operands,
    1190             :   CVT_imm_95_16,
    1191             :   CVT_imm_95_24,
    1192             :   CVT_imm_95_0,
    1193             :   CVT_95_addAddSubImmNegOperands,
    1194             :   CVT_95_addAddSubImmOperands,
    1195             :   CVT_95_addRegOperands,
    1196             :   CVT_95_addShifterOperands,
    1197             :   CVT_95_addExtendOperands,
    1198             :   CVT_95_addExtend64Operands,
    1199             :   CVT_95_addImmOperands,
    1200             :   CVT_95_addAdrLabelOperands,
    1201             :   CVT_95_addAdrpLabelOperands,
    1202             :   CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_,
    1203             :   CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_,
    1204             :   CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_,
    1205             :   CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_,
    1206             :   CVT_imm_95_31,
    1207             :   CVT_imm_95_63,
    1208             :   CVT_95_addBranchTarget26Operands,
    1209             :   CVT_95_addCondCodeOperands,
    1210             :   CVT_95_addPCRelLabel19Operands,
    1211             :   CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_,
    1212             :   CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_,
    1213             :   CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_,
    1214             :   CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_,
    1215             :   CVT_imm_95_15,
    1216             :   CVT_regWZR,
    1217             :   CVT_regXZR,
    1218             :   CVT_imm_95_20,
    1219             :   CVT_95_addBarrierOperands,
    1220             :   CVT_95_addVectorIndexOperands,
    1221             :   CVT_95_addComplexRotationOddOperands,
    1222             :   CVT_95_addComplexRotationEvenOperands,
    1223             :   CVT_95_addVectorRegLoOperands,
    1224             :   CVT_95_addFPImmOperands,
    1225             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_,
    1226             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_,
    1227             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_,
    1228             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_,
    1229             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_,
    1230             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_,
    1231             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_,
    1232             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_,
    1233             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_,
    1234             :   CVT_95_addImmScaledOperands_LT_1_GT_,
    1235             :   CVT_95_addImmScaledOperands_LT_8_GT_,
    1236             :   CVT_95_addImmScaledOperands_LT_2_GT_,
    1237             :   CVT_95_addImmScaledOperands_LT_16_GT_,
    1238             :   CVT_95_addImmScaledOperands_LT_4_GT_,
    1239             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_,
    1240             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_,
    1241             :   CVT_95_addImmScaledOperands_LT_3_GT_,
    1242             :   CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_,
    1243             :   CVT_95_addUImm12OffsetOperands_LT_4_GT_,
    1244             :   CVT_95_addUImm12OffsetOperands_LT_8_GT_,
    1245             :   CVT_95_addUImm12OffsetOperands_LT_1_GT_,
    1246             :   CVT_95_addUImm12OffsetOperands_LT_2_GT_,
    1247             :   CVT_95_addUImm12OffsetOperands_LT_16_GT_,
    1248             :   CVT_95_addMemExtendOperands,
    1249             :   CVT_95_addMemExtend8Operands,
    1250             :   CVT_95_addMOVZMovAliasOperands_LT_0_GT_,
    1251             :   CVT_95_addMOVZMovAliasOperands_LT_16_GT_,
    1252             :   CVT_95_addMOVNMovAliasOperands_LT_0_GT_,
    1253             :   CVT_95_addMOVNMovAliasOperands_LT_16_GT_,
    1254             :   CVT_95_addMOVZMovAliasOperands_LT_32_GT_,
    1255             :   CVT_imm_95_32,
    1256             :   CVT_95_addMOVZMovAliasOperands_LT_48_GT_,
    1257             :   CVT_imm_95_48,
    1258             :   CVT_95_addMOVNMovAliasOperands_LT_32_GT_,
    1259             :   CVT_95_addMOVNMovAliasOperands_LT_48_GT_,
    1260             :   CVT_95_addSIMDImmType10Operands,
    1261             :   CVT_95_addMRSSystemRegisterOperands,
    1262             :   CVT_95_addMSRSystemRegisterOperands,
    1263             :   CVT_95_addSystemPStateFieldWithImm0_95_15Operands,
    1264             :   CVT_95_addSystemPStateFieldWithImm0_95_1Operands,
    1265             :   CVT_95_addPrefetchOperands,
    1266             :   CVT_95_addPSBHintOperands,
    1267             :   CVT_regLR,
    1268             :   CVT_imm_95_4,
    1269             :   CVT_imm_95_5,
    1270             :   CVT_imm_95_7,
    1271             :   CVT_95_addSysCROperands,
    1272             :   CVT_95_addBranchTarget14Operands,
    1273             :   CVT_95_addGPR32as64Operands,
    1274             :   CVT_imm_95_2,
    1275             :   CVT_imm_95_3,
    1276             :   CVT_imm_95_1,
    1277             :   CVT_NUM_CONVERTERS
    1278             : };
    1279             : 
    1280             : enum InstructionConversionKind {
    1281             :   Convert__Reg1_0__Reg1_1,
    1282             :   Convert__VectorReg1281_1__VectorReg1281_2,
    1283             :   Convert__VectorReg641_1__VectorReg641_2,
    1284             :   Convert__VectorReg1281_0__VectorReg1281_2,
    1285             :   Convert__VectorReg641_0__VectorReg641_2,
    1286             :   Convert__Reg1_0__Reg1_1__Reg1_2,
    1287             :   Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16,
    1288             :   Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24,
    1289             :   Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
    1290             :   Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2,
    1291             :   Convert__Reg1_0__Reg1_1__AddSubImm2_2,
    1292             :   Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2,
    1293             :   Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2,
    1294             :   Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2,
    1295             :   Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2,
    1296             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3,
    1297             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3,
    1298             :   Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3,
    1299             :   Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3,
    1300             :   Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3,
    1301             :   Convert__Reg1_0__Reg1_1__Reg1_2__Extend641_3,
    1302             :   Convert__Reg1_0__Reg1_1__Reg1_2__ExtendLSL641_3,
    1303             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4,
    1304             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4,
    1305             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5,
    1306             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5,
    1307             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5,
    1308             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorBReg1_5,
    1309             :   Convert__VectorReg641_1__VectorReg1281_2__VectorReg1281_3,
    1310             :   Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4,
    1311             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3,
    1312             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4,
    1313             :   Convert__FPRAsmOperandFPR641_1__VectorReg1281_2,
    1314             :   Convert__FPRAsmOperandFPR641_0__VectorReg1281_1,
    1315             :   Convert__Reg1_0__Reg1_1__SImm61_2,
    1316             :   Convert__Reg1_1__VectorReg1281_2,
    1317             :   Convert__Reg1_1__VectorReg641_2,
    1318             :   Convert__Reg1_0__VectorReg1281_1,
    1319             :   Convert__Reg1_0__VectorReg641_1,
    1320             :   Convert__Reg1_0__AdrLabel1_1,
    1321             :   Convert__Reg1_0__AdrpLabel1_1,
    1322             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2,
    1323             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2,
    1324             :   Convert__Reg1_0__Reg1_1__LogicalImm321_2,
    1325             :   Convert__Reg1_0__Reg1_1__LogicalImm641_2,
    1326             :   Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2,
    1327             :   Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2,
    1328             :   Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2,
    1329             :   Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2,
    1330             :   Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3,
    1331             :   Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3,
    1332             :   Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31,
    1333             :   Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63,
    1334             :   Convert__Reg1_0,
    1335             :   Convert_NoOperands,
    1336             :   Convert__BranchTarget261_0,
    1337             :   Convert__CondCode1_1__PCRelLabel191_2,
    1338             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_311_2__Imm0_311_3,
    1339             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2__Imm0_631_3,
    1340             :   Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__imm_95_0,
    1341             :   Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__imm_95_0,
    1342             :   Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2,
    1343             :   Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2,
    1344             :   Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__imm_95_0,
    1345             :   Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__imm_95_0,
    1346             :   Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2,
    1347             :   Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2,
    1348             :   Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2,
    1349             :   Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2,
    1350             :   Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3,
    1351             :   Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1352             :   Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3,
    1353             :   Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1354             :   Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3,
    1355             :   Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1356             :   Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3,
    1357             :   Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    1358             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3,
    1359             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4,
    1360             :   Convert__Imm0_655351_0,
    1361             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3,
    1362             :   Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3,
    1363             :   Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3,
    1364             :   Convert__Reg1_0__PCRelLabel191_1,
    1365             :   Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3,
    1366             :   Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3,
    1367             :   Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2,
    1368             :   Convert__imm_95_15,
    1369             :   Convert__Imm0_151_0,
    1370             :   Convert__Reg1_0__Reg1_2__Reg1_1,
    1371             :   Convert__VectorReg1281_1__VectorReg1281_3__VectorReg1281_2,
    1372             :   Convert__VectorReg641_1__VectorReg641_3__VectorReg641_2,
    1373             :   Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2,
    1374             :   Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2,
    1375             :   Convert__regWZR__Reg1_0__Reg1_1__imm_95_16,
    1376             :   Convert__regXZR__Reg1_0__Reg1_1__imm_95_24,
    1377             :   Convert__regWZR__Reg1_0__Reg1_1__imm_95_0,
    1378             :   Convert__regWZR__Reg1_0__AddSubImmNeg2_1,
    1379             :   Convert__regWZR__Reg1_0__AddSubImm2_1,
    1380             :   Convert__regXZR__Reg1_0__Reg1_1__imm_95_0,
    1381             :   Convert__regXZR__Reg1_0__AddSubImmNeg2_1,
    1382             :   Convert__regXZR__Reg1_0__AddSubImm2_1,
    1383             :   Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2,
    1384             :   Convert__regWZR__Reg1_0__Reg1_1__Extend1_2,
    1385             :   Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2,
    1386             :   Convert__regXZR__Reg1_0__Reg1_1__Extend1_2,
    1387             :   Convert__regXZR__Reg1_0__Reg1_1__ExtendLSL641_2,
    1388             :   Convert__imm_95_20,
    1389             :   Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3,
    1390             :   Convert__Reg1_0__regWZR__regWZR__CondCode1_1,
    1391             :   Convert__Reg1_0__regXZR__regXZR__CondCode1_1,
    1392             :   Convert__imm_95_0,
    1393             :   Convert__Barrier1_0,
    1394             :   Convert__SVEVectorHReg1_0__Reg1_1,
    1395             :   Convert__SVEVectorSReg1_0__Reg1_1,
    1396             :   Convert__SVEVectorDReg1_0__Reg1_1,
    1397             :   Convert__SVEVectorBReg1_0__Reg1_1,
    1398             :   Convert__VectorReg1281_1__Reg1_2,
    1399             :   Convert__VectorReg641_1__Reg1_2,
    1400             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_2,
    1401             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_2,
    1402             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_2,
    1403             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_2,
    1404             :   Convert__VectorReg1281_0__Reg1_2,
    1405             :   Convert__VectorReg641_0__Reg1_2,
    1406             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexB1_3,
    1407             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexD1_3,
    1408             :   Convert__VectorReg641_1__VectorReg1281_2__VectorIndexS1_3,
    1409             :   Convert__VectorReg641_1__VectorReg1281_2__VectorIndexH1_3,
    1410             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexS1_3,
    1411             :   Convert__VectorReg641_1__VectorReg1281_2__VectorIndexB1_3,
    1412             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexH1_3,
    1413             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_3,
    1414             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_3,
    1415             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_3,
    1416             :   Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_3,
    1417             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexB1_4,
    1418             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexD1_4,
    1419             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexS1_4,
    1420             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexH1_4,
    1421             :   Convert__VectorReg641_0__VectorReg1281_2__VectorIndexS1_4,
    1422             :   Convert__VectorReg641_0__VectorReg1281_2__VectorIndexH1_4,
    1423             :   Convert__VectorReg641_0__VectorReg1281_2__VectorIndexB1_4,
    1424             :   Convert__imm_95_16,
    1425             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__Imm1_4,
    1426             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__Imm1_4,
    1427             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__Imm1_6,
    1428             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__Imm1_6,
    1429             :   Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_311_3,
    1430             :   Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_631_3,
    1431             :   Convert__FPRAsmOperandFPR161_1__VectorReg641_2,
    1432             :   Convert__FPRAsmOperandFPR321_1__VectorReg641_2,
    1433             :   Convert__FPRAsmOperandFPR161_0__VectorReg641_1,
    1434             :   Convert__FPRAsmOperandFPR321_0__VectorReg641_1,
    1435             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__ComplexRotationOdd1_4,
    1436             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__ComplexRotationOdd1_4,
    1437             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6,
    1438             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__ComplexRotationOdd1_6,
    1439             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__ComplexRotationEven1_4,
    1440             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3__ComplexRotationEven1_4,
    1441             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexD1_4__ComplexRotationEven1_5,
    1442             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4__ComplexRotationEven1_5,
    1443             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4__ComplexRotationEven1_5,
    1444             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6,
    1445             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4__ComplexRotationEven1_6,
    1446             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7,
    1447             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6__ComplexRotationEven1_7,
    1448             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7,
    1449             :   Convert__VectorReg1281_0__VectorReg641_2,
    1450             :   Convert__VectorReg641_0__VectorReg1281_2,
    1451             :   Convert__Reg1_0__Reg1_1__Imm1_161_2,
    1452             :   Convert__Reg1_0__Reg1_1__Imm1_321_2,
    1453             :   Convert__Reg1_0__Reg1_1__Imm1_641_2,
    1454             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm1_641_3,
    1455             :   Convert__VectorReg641_1__VectorReg641_2__Imm1_321_3,
    1456             :   Convert__VectorReg641_1__VectorReg641_2__Imm1_161_3,
    1457             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm1_321_3,
    1458             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm1_161_3,
    1459             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm1_641_4,
    1460             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm1_321_4,
    1461             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm1_161_4,
    1462             :   Convert__VectorReg641_0__VectorReg641_2__Imm1_321_4,
    1463             :   Convert__VectorReg641_0__VectorReg641_2__Imm1_161_4,
    1464             :   Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
    1465             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4,
    1466             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4,
    1467             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4,
    1468             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4,
    1469             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__VectorIndexH1_4,
    1470             :   Convert__FPRAsmOperandFPR641_1__Tie0_2_2__FPRAsmOperandFPR641_2__VectorReg1281_3__VectorIndexD1_4,
    1471             :   Convert__FPRAsmOperandFPR161_1__Tie0_2_2__FPRAsmOperandFPR161_2__VectorRegLo1_3__VectorIndexH1_4,
    1472             :   Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__VectorIndexS1_4,
    1473             :   Convert__FPRAsmOperandFPR161_0__Tie0_1_1__FPRAsmOperandFPR161_1__VectorRegLo1_2__VectorIndexH1_4,
    1474             :   Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__VectorIndexS1_4,
    1475             :   Convert__FPRAsmOperandFPR641_0__Tie0_1_1__FPRAsmOperandFPR641_1__VectorReg1281_2__VectorIndexD1_4,
    1476             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6,
    1477             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6,
    1478             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorRegLo1_4__VectorIndexH1_6,
    1479             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6,
    1480             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6,
    1481             :   Convert__Reg1_0__FPImm1_1,
    1482             :   Convert__VectorReg1281_1__FPImm1_2,
    1483             :   Convert__VectorReg641_1__FPImm1_2,
    1484             :   Convert__Reg1_0__regWZR,
    1485             :   Convert__Reg1_0__regXZR,
    1486             :   Convert__VectorReg1281_0__FPImm1_2,
    1487             :   Convert__VectorReg641_0__FPImm1_2,
    1488             :   Convert__Reg1_1__VectorReg1281_2__VectorIndex11_3,
    1489             :   Convert__VectorReg1281_1__Reg1_3__VectorIndex11_2,
    1490             :   Convert__Reg1_0__VectorReg1281_1__VectorIndex11_3,
    1491             :   Convert__VectorReg1281_0__Reg1_3__VectorIndex11_2,
    1492             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4,
    1493             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4,
    1494             :   Convert__VectorReg641_1__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4,
    1495             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4,
    1496             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorRegLo1_3__VectorIndexH1_4,
    1497             :   Convert__FPRAsmOperandFPR641_1__FPRAsmOperandFPR641_2__VectorReg1281_3__VectorIndexD1_4,
    1498             :   Convert__FPRAsmOperandFPR161_1__FPRAsmOperandFPR161_2__VectorRegLo1_3__VectorIndexH1_4,
    1499             :   Convert__FPRAsmOperandFPR321_1__FPRAsmOperandFPR321_2__VectorReg1281_3__VectorIndexS1_4,
    1500             :   Convert__FPRAsmOperandFPR161_0__FPRAsmOperandFPR161_1__VectorRegLo1_2__VectorIndexH1_4,
    1501             :   Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__VectorReg1281_2__VectorIndexS1_4,
    1502             :   Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__VectorReg1281_2__VectorIndexD1_4,
    1503             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6,
    1504             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6,
    1505             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorRegLo1_4__VectorIndexH1_6,
    1506             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6,
    1507             :   Convert__VectorReg641_0__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6,
    1508             :   Convert__Imm0_1271_0,
    1509             :   Convert__SVEVectorHReg1_0__Reg1_1__Reg1_2,
    1510             :   Convert__SVEVectorHReg1_0__Reg1_1__SImm51_2,
    1511             :   Convert__SVEVectorHReg1_0__SImm51_1__Reg1_2,
    1512             :   Convert__SVEVectorHReg1_0__SImm51_1__SImm51_2,
    1513             :   Convert__SVEVectorSReg1_0__Reg1_1__Reg1_2,
    1514             :   Convert__SVEVectorSReg1_0__Reg1_1__SImm51_2,
    1515             :   Convert__SVEVectorSReg1_0__SImm51_1__Reg1_2,
    1516             :   Convert__SVEVectorSReg1_0__SImm51_1__SImm51_2,
    1517             :   Convert__SVEVectorDReg1_0__Reg1_1__Reg1_2,
    1518             :   Convert__SVEVectorDReg1_0__Reg1_1__SImm51_2,
    1519             :   Convert__SVEVectorDReg1_0__SImm51_1__Reg1_2,
    1520             :   Convert__SVEVectorDReg1_0__SImm51_1__SImm51_2,
    1521             :   Convert__SVEVectorBReg1_0__Reg1_1__Reg1_2,
    1522             :   Convert__SVEVectorBReg1_0__Reg1_1__SImm51_2,
    1523             :   Convert__SVEVectorBReg1_0__SImm51_1__Reg1_2,
    1524             :   Convert__SVEVectorBReg1_0__SImm51_1__SImm51_2,
    1525             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_3,
    1526             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_3,
    1527             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_3,
    1528             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_3,
    1529             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexB1_2__Reg1_3,
    1530             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexD1_2__Reg1_3,
    1531             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexH1_2__Reg1_3,
    1532             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexS1_2__Reg1_3,
    1533             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexB1_2__VectorReg1281_3__VectorIndexB1_4,
    1534             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexD1_2__VectorReg1281_3__VectorIndexD1_4,
    1535             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexH1_2__VectorReg1281_3__VectorIndexH1_4,
    1536             :   Convert__VectorReg1281_1__Tie0_2_2__VectorIndexS1_2__VectorReg1281_3__VectorIndexS1_4,
    1537             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexB1_2__VectorReg1281_3__VectorIndexB1_5,
    1538             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexD1_2__VectorReg1281_3__VectorIndexD1_5,
    1539             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexH1_2__VectorReg1281_3__VectorIndexH1_5,
    1540             :   Convert__VectorReg1281_0__Tie0_1_1__VectorIndexS1_2__VectorReg1281_3__VectorIndexS1_5,
    1541             :   Convert__TypedVectorList4_1681_0__Reg1_2,
    1542             :   Convert__TypedVectorList4_1641_0__Reg1_2,
    1543             :   Convert__TypedVectorList4_2641_0__Reg1_2,
    1544             :   Convert__TypedVectorList4_2321_0__Reg1_2,
    1545             :   Convert__TypedVectorList4_4161_0__Reg1_2,
    1546             :   Convert__TypedVectorList4_4321_0__Reg1_2,
    1547             :   Convert__TypedVectorList4_881_0__Reg1_2,
    1548             :   Convert__TypedVectorList4_8161_0__Reg1_2,
    1549             :   Convert__TypedVectorList1_1681_0__Reg1_2,
    1550             :   Convert__TypedVectorList1_1641_0__Reg1_2,
    1551             :   Convert__TypedVectorList1_2641_0__Reg1_2,
    1552             :   Convert__TypedVectorList1_2321_0__Reg1_2,
    1553             :   Convert__TypedVectorList1_4161_0__Reg1_2,
    1554             :   Convert__TypedVectorList1_4321_0__Reg1_2,
    1555             :   Convert__TypedVectorList1_881_0__Reg1_2,
    1556             :   Convert__TypedVectorList1_8161_0__Reg1_2,
    1557             :   Convert__TypedVectorList3_1681_0__Reg1_2,
    1558             :   Convert__TypedVectorList3_1641_0__Reg1_2,
    1559             :   Convert__TypedVectorList3_2641_0__Reg1_2,
    1560             :   Convert__TypedVectorList3_2321_0__Reg1_2,
    1561             :   Convert__TypedVectorList3_4161_0__Reg1_2,
    1562             :   Convert__TypedVectorList3_4321_0__Reg1_2,
    1563             :   Convert__TypedVectorList3_881_0__Reg1_2,
    1564             :   Convert__TypedVectorList3_8161_0__Reg1_2,
    1565             :   Convert__TypedVectorList2_1681_0__Reg1_2,
    1566             :   Convert__TypedVectorList2_1641_0__Reg1_2,
    1567             :   Convert__TypedVectorList2_2641_0__Reg1_2,
    1568             :   Convert__TypedVectorList2_2321_0__Reg1_2,
    1569             :   Convert__TypedVectorList2_4161_0__Reg1_2,
    1570             :   Convert__TypedVectorList2_4321_0__Reg1_2,
    1571             :   Convert__TypedVectorList2_881_0__Reg1_2,
    1572             :   Convert__TypedVectorList2_8161_0__Reg1_2,
    1573             :   Convert__VecListFour1281_1__Reg1_3,
    1574             :   Convert__VecListOne1281_1__Reg1_3,
    1575             :   Convert__VecListThree1281_1__Reg1_3,
    1576             :   Convert__VecListTwo1281_1__Reg1_3,
    1577             :   Convert__VecListFour641_1__Reg1_3,
    1578             :   Convert__VecListOne641_1__Reg1_3,
    1579             :   Convert__VecListThree641_1__Reg1_3,
    1580             :   Convert__VecListTwo641_1__Reg1_3,
    1581             :   Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR,
    1582             :   Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4,
    1583             :   Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR,
    1584             :   Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4,
    1585             :   Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR,
    1586             :   Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4,
    1587             :   Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR,
    1588             :   Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4,
    1589             :   Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR,
    1590             :   Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4,
    1591             :   Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR,
    1592             :   Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4,
    1593             :   Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR,
    1594             :   Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4,
    1595             :   Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR,
    1596             :   Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4,
    1597             :   Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR,
    1598             :   Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4,
    1599             :   Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR,
    1600             :   Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4,
    1601             :   Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR,
    1602             :   Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4,
    1603             :   Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR,
    1604             :   Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4,
    1605             :   Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR,
    1606             :   Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4,
    1607             :   Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR,
    1608             :   Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4,
    1609             :   Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR,
    1610             :   Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4,
    1611             :   Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR,
    1612             :   Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4,
    1613             :   Convert__TypedVectorList1_081_0__Tie0_1_1__VectorIndexB1_1__Reg1_3,
    1614             :   Convert__TypedVectorList1_0641_0__Tie0_1_1__VectorIndexD1_1__Reg1_3,
    1615             :   Convert__TypedVectorList1_0161_0__Tie0_1_1__VectorIndexH1_1__Reg1_3,
    1616             :   Convert__TypedVectorList1_0321_0__Tie0_1_1__VectorIndexS1_1__Reg1_3,
    1617             :   Convert__Reg1_2__TypedVectorList3_1681_0__Tie0_3_3__regXZR,
    1618             :   Convert__Reg1_2__TypedVectorList3_1681_0__Tie0_3_3__Reg1_4,
    1619             :   Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR,
    1620             :   Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4,
    1621             :   Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__regXZR,
    1622             :   Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__Reg1_4,
    1623             :   Convert__Reg1_2__TypedVectorList3_2321_0__Tie0_3_3__regXZR,
    1624             :   Convert__Reg1_2__TypedVectorList3_2321_0__Tie0_3_3__Reg1_4,
    1625             :   Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__regXZR,
    1626             :   Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__Reg1_4,
    1627             :   Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__regXZR,
    1628             :   Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__Reg1_4,
    1629             :   Convert__Reg1_2__TypedVectorList3_881_0__Tie0_3_3__regXZR,
    1630             :   Convert__Reg1_2__TypedVectorList3_881_0__Tie0_3_3__Reg1_4,
    1631             :   Convert__Reg1_2__TypedVectorList3_8161_0__Tie0_3_3__regXZR,
    1632             :   Convert__Reg1_2__TypedVectorList3_8161_0__Tie0_3_3__Reg1_4,
    1633             :   Convert__Reg1_2__TypedVectorList2_1681_0__Tie0_3_3__regXZR,
    1634             :   Convert__Reg1_2__TypedVectorList2_1681_0__Tie0_3_3__Reg1_4,
    1635             :   Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR,
    1636             :   Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4,
    1637             :   Convert__Reg1_2__TypedVectorList2_2641_0__Tie0_3_3__regXZR,
    1638             :   Convert__Reg1_2__TypedVectorList2_2641_0__Tie0_3_3__Reg1_4,
    1639             :   Convert__Reg1_2__TypedVectorList2_2321_0__Tie0_3_3__regXZR,
    1640             :   Convert__Reg1_2__TypedVectorList2_2321_0__Tie0_3_3__Reg1_4,
    1641             :   Convert__Reg1_2__TypedVectorList2_4161_0__Tie0_3_3__regXZR,
    1642             :   Convert__Reg1_2__TypedVectorList2_4161_0__Tie0_3_3__Reg1_4,
    1643             :   Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__regXZR,
    1644             :   Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__Reg1_4,
    1645             :   Convert__Reg1_2__TypedVectorList2_881_0__Tie0_3_3__regXZR,
    1646             :   Convert__Reg1_2__TypedVectorList2_881_0__Tie0_3_3__Reg1_4,
    1647             :   Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__regXZR,
    1648             :   Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__Reg1_4,
    1649             :   Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR,
    1650             :   Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5,
    1651             :   Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__regXZR,
    1652             :   Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__Reg1_5,
    1653             :   Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR,
    1654             :   Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5,
    1655             :   Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR,
    1656             :   Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5,
    1657             :   Convert__Reg1_3__VecListFour641_1__Tie0_4_4__regXZR,
    1658             :   Convert__Reg1_3__VecListFour641_1__Tie0_4_4__Reg1_5,
    1659             :   Convert__Reg1_3__VecListOne641_1__Tie0_4_4__regXZR,
    1660             :   Convert__Reg1_3__VecListOne641_1__Tie0_4_4__Reg1_5,
    1661             :   Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR,
    1662             :   Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5,
    1663             :   Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__regXZR,
    1664             :   Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__Reg1_5,
    1665             :   Convert__VecListOne1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4,
    1666             :   Convert__VecListOne1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4,
    1667             :   Convert__VecListOne1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4,
    1668             :   Convert__VecListOne1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4,
    1669             :   Convert__Reg1_3__TypedVectorList1_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR,
    1670             :   Convert__Reg1_3__TypedVectorList1_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1671             :   Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR,
    1672             :   Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1673             :   Convert__Reg1_3__TypedVectorList1_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR,
    1674             :   Convert__Reg1_3__TypedVectorList1_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1675             :   Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR,
    1676             :   Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1677             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR,
    1678             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1679             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR,
    1680             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1681             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR,
    1682             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1683             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR,
    1684             :   Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1685             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1686             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1687             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0,
    1688             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1689             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0,
    1690             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1691             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1692             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1693             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1694             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0,
    1695             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1696             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0,
    1697             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1698             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1699             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW328Only1_6,
    1700             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW328Only1_6,
    1701             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6,
    1702             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1703             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL6481_6,
    1704             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW648Only1_6,
    1705             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW648Only1_6,
    1706             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Imm0_311_6,
    1707             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1708             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1709             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1710             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1711             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW328Only1_6,
    1712             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW328Only1_6,
    1713             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6,
    1714             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1715             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL6481_6,
    1716             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW648Only1_6,
    1717             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW648Only1_6,
    1718             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Imm0_311_6,
    1719             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
    1720             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
    1721             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
    1722             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
    1723             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
    1724             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
    1725             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
    1726             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
    1727             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
    1728             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64641_6,
    1729             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6,
    1730             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6,
    1731             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6,
    1732             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6,
    1733             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6,
    1734             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
    1735             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64641_6,
    1736             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6,
    1737             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6,
    1738             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6,
    1739             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6,
    1740             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6,
    1741             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1742             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1743             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6,
    1744             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW3281_6,
    1745             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6,
    1746             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW3281_6,
    1747             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6,
    1748             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1749             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64161_6,
    1750             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64161_6,
    1751             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64161_6,
    1752             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s21_6,
    1753             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1754             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1755             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6,
    1756             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW3281_6,
    1757             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6,
    1758             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW3281_6,
    1759             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6,
    1760             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1761             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64161_6,
    1762             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64161_6,
    1763             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64161_6,
    1764             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s21_6,
    1765             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
    1766             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
    1767             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
    1768             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
    1769             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
    1770             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
    1771             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
    1772             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
    1773             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s81_6,
    1774             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s81_6,
    1775             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
    1776             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
    1777             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
    1778             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
    1779             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
    1780             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
    1781             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
    1782             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
    1783             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
    1784             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
    1785             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
    1786             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
    1787             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
    1788             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
    1789             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
    1790             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
    1791             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6,
    1792             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6,
    1793             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6,
    1794             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6,
    1795             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
    1796             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64321_6,
    1797             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64321_6,
    1798             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64321_6,
    1799             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6,
    1800             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
    1801             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64321_6,
    1802             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64321_6,
    1803             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64321_6,
    1804             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6,
    1805             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32321_6,
    1806             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32321_6,
    1807             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6,
    1808             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32321_6,
    1809             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32321_6,
    1810             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6,
    1811             :   Convert__TypedVectorList2_081_0__Tie0_1_1__VectorIndexB1_1__Reg1_3,
    1812             :   Convert__TypedVectorList2_0641_0__Tie0_1_1__VectorIndexD1_1__Reg1_3,
    1813             :   Convert__TypedVectorList2_0161_0__Tie0_1_1__VectorIndexH1_1__Reg1_3,
    1814             :   Convert__TypedVectorList2_0321_0__Tie0_1_1__VectorIndexS1_1__Reg1_3,
    1815             :   Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4,
    1816             :   Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4,
    1817             :   Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4,
    1818             :   Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4,
    1819             :   Convert__Reg1_3__TypedVectorList2_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR,
    1820             :   Convert__Reg1_3__TypedVectorList2_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1821             :   Convert__Reg1_3__TypedVectorList2_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR,
    1822             :   Convert__Reg1_3__TypedVectorList2_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1823             :   Convert__Reg1_3__TypedVectorList2_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR,
    1824             :   Convert__Reg1_3__TypedVectorList2_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1825             :   Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR,
    1826             :   Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1827             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR,
    1828             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1829             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR,
    1830             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1831             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR,
    1832             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1833             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR,
    1834             :   Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1835             :   Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1836             :   Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1837             :   Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6,
    1838             :   Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1839             :   Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
    1840             :   Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6,
    1841             :   Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1842             :   Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1843             :   Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6,
    1844             :   Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1845             :   Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
    1846             :   Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6,
    1847             :   Convert__TypedVectorList3_081_0__Tie0_1_1__VectorIndexB1_1__Reg1_3,
    1848             :   Convert__TypedVectorList3_0641_0__Tie0_1_1__VectorIndexD1_1__Reg1_3,
    1849             :   Convert__TypedVectorList3_0161_0__Tie0_1_1__VectorIndexH1_1__Reg1_3,
    1850             :   Convert__TypedVectorList3_0321_0__Tie0_1_1__VectorIndexS1_1__Reg1_3,
    1851             :   Convert__VecListThree1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4,
    1852             :   Convert__VecListThree1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4,
    1853             :   Convert__VecListThree1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4,
    1854             :   Convert__VecListThree1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4,
    1855             :   Convert__Reg1_3__TypedVectorList3_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR,
    1856             :   Convert__Reg1_3__TypedVectorList3_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1857             :   Convert__Reg1_3__TypedVectorList3_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR,
    1858             :   Convert__Reg1_3__TypedVectorList3_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1859             :   Convert__Reg1_3__TypedVectorList3_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR,
    1860             :   Convert__Reg1_3__TypedVectorList3_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1861             :   Convert__Reg1_3__TypedVectorList3_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR,
    1862             :   Convert__Reg1_3__TypedVectorList3_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1863             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR,
    1864             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1865             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR,
    1866             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1867             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR,
    1868             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1869             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR,
    1870             :   Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1871             :   Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1872             :   Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1873             :   Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6,
    1874             :   Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1875             :   Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
    1876             :   Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6,
    1877             :   Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1878             :   Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1879             :   Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6,
    1880             :   Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1881             :   Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
    1882             :   Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6,
    1883             :   Convert__TypedVectorList4_081_0__Tie0_1_1__VectorIndexB1_1__Reg1_3,
    1884             :   Convert__TypedVectorList4_0641_0__Tie0_1_1__VectorIndexD1_1__Reg1_3,
    1885             :   Convert__TypedVectorList4_0161_0__Tie0_1_1__VectorIndexH1_1__Reg1_3,
    1886             :   Convert__TypedVectorList4_0321_0__Tie0_1_1__VectorIndexS1_1__Reg1_3,
    1887             :   Convert__VecListFour1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4,
    1888             :   Convert__VecListFour1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4,
    1889             :   Convert__VecListFour1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4,
    1890             :   Convert__VecListFour1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4,
    1891             :   Convert__Reg1_3__TypedVectorList4_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR,
    1892             :   Convert__Reg1_3__TypedVectorList4_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    1893             :   Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR,
    1894             :   Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    1895             :   Convert__Reg1_3__TypedVectorList4_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR,
    1896             :   Convert__Reg1_3__TypedVectorList4_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    1897             :   Convert__Reg1_3__TypedVectorList4_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR,
    1898             :   Convert__Reg1_3__TypedVectorList4_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    1899             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR,
    1900             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    1901             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR,
    1902             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    1903             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR,
    1904             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    1905             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR,
    1906             :   Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    1907             :   Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1908             :   Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
    1909             :   Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6,
    1910             :   Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1911             :   Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
    1912             :   Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6,
    1913             :   Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1914             :   Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
    1915             :   Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6,
    1916             :   Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
    1917             :   Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
    1918             :   Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6,
    1919             :   Convert__Reg1_1__Reg1_0__Reg1_3,
    1920             :   Convert__Reg1_0__GPR64sp01_2,
    1921             :   Convert__Reg1_0__Reg1_1__GPR64sp01_3,
    1922             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
    1923             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
    1924             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
    1925             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
    1926             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
    1927             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
    1928             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
    1929             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
    1930             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
    1931             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
    1932             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
    1933             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
    1934             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
    1935             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
    1936             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
    1937             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
    1938             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted641_6,
    1939             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted641_6,
    1940             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
    1941             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
    1942             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
    1943             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
    1944             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
    1945             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
    1946             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6,
    1947             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6,
    1948             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6,
    1949             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6,
    1950             :   Convert__Reg1_0__Reg1_1__Reg1_3__imm_95_0,
    1951             :   Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__imm_95_0,
    1952             :   Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Reg1_3__imm_95_0,
    1953             :   Convert__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Reg1_3__imm_95_0,
    1954             :   Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4,
    1955             :   Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s81_4,
    1956             :   Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4,
    1957             :   Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Reg1_3__SImm7s81_4,
    1958             :   Convert__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Reg1_3__SImm7s161_4,
    1959             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5,
    1960             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_5,
    1961             :   Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_5,
    1962             :   Convert__Reg1_3__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Tie0_4_4__SImm7s81_5,
    1963             :   Convert__Reg1_3__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Tie0_4_4__SImm7s161_5,
    1964             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4,
    1965             :   Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_4,
    1966             :   Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_4,
    1967             :   Convert__Reg1_3__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Tie0_4_4__SImm7s81_4,
    1968             :   Convert__Reg1_3__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Tie0_4_4__SImm7s161_4,
    1969             :   Convert__FPRAsmOperandFPR321_0__PCRelLabel191_1,
    1970             :   Convert__FPRAsmOperandFPR641_0__PCRelLabel191_1,
    1971             :   Convert__FPRAsmOperandFPR1281_0__PCRelLabel191_1,
    1972             :   Convert__Reg1_0__Reg1_2__imm_95_0,
    1973             :   Convert__SVEPredicateAnyReg1_0__Reg1_2__imm_95_0,
    1974             :   Convert__SVEVectorAnyReg1_0__Reg1_2__imm_95_0,
    1975             :   Convert__FPRAsmOperandFPR81_0__Reg1_2__imm_95_0,
    1976             :   Convert__FPRAsmOperandFPR161_0__Reg1_2__imm_95_0,
    1977             :   Convert__FPRAsmOperandFPR321_0__Reg1_2__imm_95_0,
    1978             :   Convert__FPRAsmOperandFPR641_0__Reg1_2__imm_95_0,
    1979             :   Convert__FPRAsmOperandFPR1281_0__Reg1_2__imm_95_0,
    1980             :   Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_4,
    1981             :   Convert__Reg1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    1982             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB321_3,
    1983             :   Convert__Reg1_0__Reg1_2__UImm12Offset41_3,
    1984             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB641_3,
    1985             :   Convert__Reg1_0__Reg1_2__UImm12Offset81_3,
    1986             :   Convert__Reg1_2__FPRAsmOperandFPR81_0__Tie0_3_3__SImm91_4,
    1987             :   Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    1988             :   Convert__FPRAsmOperandFPR81_0__Reg1_2__SImm9OffsetFB81_3,
    1989             :   Convert__FPRAsmOperandFPR81_0__Reg1_2__UImm12Offset11_3,
    1990             :   Convert__Reg1_2__FPRAsmOperandFPR161_0__Tie0_3_3__SImm91_4,
    1991             :   Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    1992             :   Convert__FPRAsmOperandFPR161_0__Reg1_2__SImm9OffsetFB161_3,
    1993             :   Convert__FPRAsmOperandFPR161_0__Reg1_2__UImm12Offset21_3,
    1994             :   Convert__Reg1_2__FPRAsmOperandFPR321_0__Tie0_3_3__SImm91_4,
    1995             :   Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    1996             :   Convert__FPRAsmOperandFPR321_0__Reg1_2__SImm9OffsetFB321_3,
    1997             :   Convert__FPRAsmOperandFPR321_0__Reg1_2__UImm12Offset41_3,
    1998             :   Convert__Reg1_2__FPRAsmOperandFPR641_0__Tie0_3_3__SImm91_4,
    1999             :   Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    2000             :   Convert__FPRAsmOperandFPR641_0__Reg1_2__SImm9OffsetFB641_3,
    2001             :   Convert__FPRAsmOperandFPR641_0__Reg1_2__UImm12Offset81_3,
    2002             :   Convert__Reg1_2__FPRAsmOperandFPR1281_0__Tie0_3_3__SImm91_4,
    2003             :   Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    2004             :   Convert__FPRAsmOperandFPR1281_0__Reg1_2__SImm9OffsetFB1281_3,
    2005             :   Convert__FPRAsmOperandFPR1281_0__Reg1_2__UImm12Offset161_3,
    2006             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend322_4,
    2007             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend322_4,
    2008             :   Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_3,
    2009             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend642_4,
    2010             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend642_4,
    2011             :   Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__MemWExtend82_4,
    2012             :   Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__MemXExtend82_4,
    2013             :   Convert__Reg1_2__FPRAsmOperandFPR81_0__Tie0_3_3__SImm91_3,
    2014             :   Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__MemWExtend162_4,
    2015             :   Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__MemXExtend162_4,
    2016             :   Convert__Reg1_2__FPRAsmOperandFPR161_0__Tie0_3_3__SImm91_3,
    2017             :   Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__MemWExtend322_4,
    2018             :   Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__MemXExtend322_4,
    2019             :   Convert__Reg1_2__FPRAsmOperandFPR321_0__Tie0_3_3__SImm91_3,
    2020             :   Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__MemWExtend642_4,
    2021             :   Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__MemXExtend642_4,
    2022             :   Convert__Reg1_2__FPRAsmOperandFPR641_0__Tie0_3_3__SImm91_3,
    2023             :   Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__MemWExtend1282_4,
    2024             :   Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__MemXExtend1282_4,
    2025             :   Convert__Reg1_2__FPRAsmOperandFPR1281_0__Tie0_3_3__SImm91_3,
    2026             :   Convert__SVEPredicateAnyReg1_0__Reg1_2__SImm91_3,
    2027             :   Convert__SVEVectorAnyReg1_0__Reg1_2__SImm91_3,
    2028             :   Convert__Reg1_0__Reg1_2__SImm10s81_3,
    2029             :   Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm10s81_3,
    2030             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB81_3,
    2031             :   Convert__Reg1_0__Reg1_2__UImm12Offset11_3,
    2032             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend82_4,
    2033             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend82_4,
    2034             :   Convert__Reg1_0__Reg1_2__SImm9OffsetFB161_3,
    2035             :   Convert__Reg1_0__Reg1_2__UImm12Offset21_3,
    2036             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend162_4,
    2037             :   Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend162_4,
    2038             :   Convert__Reg1_0__Reg1_2__SImm91_3,
    2039             :   Convert__FPRAsmOperandFPR81_0__Reg1_2__SImm91_3,
    2040             :   Convert__FPRAsmOperandFPR161_0__Reg1_2__SImm91_3,
    2041             :   Convert__FPRAsmOperandFPR321_0__Reg1_2__SImm91_3,
    2042             :   Convert__FPRAsmOperandFPR641_0__Reg1_2__SImm91_3,
    2043             :   Convert__FPRAsmOperandFPR1281_0__Reg1_2__SImm91_3,
    2044             :   Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__Imm0_151_2,
    2045             :   Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__Imm0_311_2,
    2046             :   Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__Imm0_631_2,
    2047             :   Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__Imm0_71_2,
    2048             :   Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__Imm1_161_2,
    2049             :   Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__Imm1_321_2,
    2050             :   Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__Imm1_641_2,
    2051             :   Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__Imm1_81_2,
    2052             :   Convert__Reg1_0__Reg1_1__Reg1_2__regWZR,
    2053             :   Convert__Reg1_0__Reg1_1__Reg1_2__regXZR,
    2054             :   Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0,
    2055             :   Convert__Reg1_0__regWZR__Reg1_1__imm_95_0,
    2056             :   Convert__Reg1_0__MOVZ32_lsl0MovAlias1_1__imm_95_0,
    2057             :   Convert__Reg1_0__MOVZ32_lsl16MovAlias1_1__imm_95_16,
    2058             :   Convert__Reg1_0__MOVN32_lsl0MovAlias1_1__imm_95_0,
    2059             :   Convert__Reg1_0__MOVN32_lsl16MovAlias1_1__imm_95_16,
    2060             :   Convert__Reg1_0__regWZR__LogicalImm321_1,
    2061             :   Convert__Reg1_0__regXZR__Reg1_1__imm_95_0,
    2062             :   Convert__Reg1_0__MOVZ64_lsl0MovAlias1_1__imm_95_0,
    2063             :   Convert__Reg1_0__MOVZ64_lsl16MovAlias1_1__imm_95_16,
    2064             :   Convert__Reg1_0__MOVZ64_lsl32MovAlias1_1__imm_95_32,
    2065             :   Convert__Reg1_0__MOVZ64_lsl48MovAlias1_1__imm_95_48,
    2066             :   Convert__Reg1_0__MOVN64_lsl0MovAlias1_1__imm_95_0,
    2067             :   Convert__Reg1_0__MOVN64_lsl16MovAlias1_1__imm_95_16,
    2068             :   Convert__Reg1_0__MOVN64_lsl32MovAlias1_1__imm_95_32,
    2069             :   Convert__Reg1_0__MOVN64_lsl48MovAlias1_1__imm_95_48,
    2070             :   Convert__Reg1_0__regXZR__LogicalImm641_1,
    2071             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_2,
    2072             :   Convert__VectorReg641_1__VectorReg641_2__VectorReg641_2,
    2073             :   Convert__Reg1_1__VectorReg1281_2__VectorIndexD1_3,
    2074             :   Convert__Reg1_1__VectorReg1281_2__VectorIndexS1_3,
    2075             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_2,
    2076             :   Convert__VectorReg641_0__VectorReg641_2__VectorReg641_2,
    2077             :   Convert__Reg1_0__SIMDImmType101_1,
    2078             :   Convert__VectorReg1281_1__Imm0_2551_2,
    2079             :   Convert__VectorReg1281_1__SIMDImmType101_2,
    2080             :   Convert__VectorReg641_1__Imm0_2551_2__imm_95_0,
    2081             :   Convert__VectorReg1281_1__Imm0_2551_2__imm_95_0,
    2082             :   Convert__VectorReg641_1__Imm0_2551_2,
    2083             :   Convert__VectorReg1281_0__Imm0_2551_2,
    2084             :   Convert__VectorReg1281_0__SIMDImmType101_2,
    2085             :   Convert__VectorReg1281_0__Imm0_2551_2__imm_95_0,
    2086             :   Convert__VectorReg641_0__Imm0_2551_2__imm_95_0,
    2087             :   Convert__VectorReg641_0__Imm0_2551_2,
    2088             :   Convert__VectorReg641_1__Imm0_2551_2__LogicalVecShifter1_3,
    2089             :   Convert__VectorReg641_1__Imm0_2551_2__MoveVecShifter1_3,
    2090             :   Convert__VectorReg641_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    2091             :   Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecShifter1_3,
    2092             :   Convert__VectorReg1281_1__Imm0_2551_2__MoveVecShifter1_3,
    2093             :   Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    2094             :   Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecShifter1_3,
    2095             :   Convert__VectorReg1281_0__Imm0_2551_2__MoveVecShifter1_3,
    2096             :   Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    2097             :   Convert__VectorReg641_0__Imm0_2551_2__LogicalVecShifter1_3,
    2098             :   Convert__VectorReg641_0__Imm0_2551_2__MoveVecShifter1_3,
    2099             :   Convert__VectorReg641_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
    2100             :   Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0,
    2101             :   Convert__Reg1_0__Tie0_1_1__MovKSymbolG01_1__imm_95_0,
    2102             :   Convert__Reg1_0__Tie0_1_1__MovKSymbolG11_1__imm_95_16,
    2103             :   Convert__Reg1_0__Tie0_1_1__MovKSymbolG21_1__imm_95_32,
    2104             :   Convert__Reg1_0__Tie0_1_1__MovKSymbolG31_1__imm_95_48,
    2105             :   Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm32Shifter1_2,
    2106             :   Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm64Shifter1_2,
    2107             :   Convert__Reg1_0__Imm0_655351_1__imm_95_0,
    2108             :   Convert__Reg1_0__MovZSymbolG01_1__imm_95_0,
    2109             :   Convert__Reg1_0__MovZSymbolG11_1__imm_95_16,
    2110             :   Convert__Reg1_0__MovZSymbolG21_1__imm_95_32,
    2111             :   Convert__Reg1_0__MovZSymbolG31_1__imm_95_48,
    2112             :   Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2,
    2113             :   Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2,
    2114             :   Convert__Reg1_0__MRSSystemRegister1_1,
    2115             :   Convert__MSRSystemRegister1_0__Reg1_1,
    2116             :   Convert__SystemPStateFieldWithImm0_151_0__Imm0_151_1,
    2117             :   Convert__SystemPStateFieldWithImm0_11_0__Imm0_11_1,
    2118             :   Convert__Reg1_0__regWZR__Reg1_1__LogicalShifter321_2,
    2119             :   Convert__Reg1_0__regXZR__Reg1_1__LogicalShifter641_2,
    2120             :   Convert__Reg1_0__regWZR__Reg1_1__ArithmeticShifter321_2,
    2121             :   Convert__Reg1_0__regXZR__Reg1_1__ArithmeticShifter641_2,
    2122             :   Convert__Reg1_0__regWZR__Reg1_1,
    2123             :   Convert__Reg1_0__regXZR__Reg1_1,
    2124             :   Convert__VectorReg1281_1__VectorReg641_2__VectorReg641_3,
    2125             :   Convert__VectorReg1281_0__VectorReg641_2__VectorReg641_4,
    2126             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2127             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0,
    2128             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0,
    2129             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2130             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4,
    2131             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4,
    2132             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4,
    2133             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4,
    2134             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4,
    2135             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4,
    2136             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4,
    2137             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm6s11_4,
    2138             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
    2139             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32641_4,
    2140             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32641_4,
    2141             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4,
    2142             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4,
    2143             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4,
    2144             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s81_4,
    2145             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4,
    2146             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2147             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4,
    2148             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4,
    2149             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4,
    2150             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4,
    2151             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4,
    2152             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4,
    2153             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4,
    2154             :   Convert__Prefetch1_0__PCRelLabel191_1,
    2155             :   Convert__Prefetch1_0__Reg1_2__imm_95_0,
    2156             :   Convert__Prefetch1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
    2157             :   Convert__Prefetch1_0__Reg1_2__UImm12Offset81_3,
    2158             :   Convert__Prefetch1_0__Reg1_2__Reg1_3__MemWExtend642_4,
    2159             :   Convert__Prefetch1_0__Reg1_2__Reg1_3__MemXExtend642_4,
    2160             :   Convert__Prefetch1_0__Reg1_2__SImm91_3,
    2161             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
    2162             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4,
    2163             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4,
    2164             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4,
    2165             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4,
    2166             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4,
    2167             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4,
    2168             :   Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4,
    2169             :   Convert__PSBHint1_0,
    2170             :   Convert__SVEPredicateHReg1_0__imm_95_31,
    2171             :   Convert__SVEPredicateSReg1_0__imm_95_31,
    2172             :   Convert__SVEPredicateDReg1_0__imm_95_31,
    2173             :   Convert__SVEPredicateBReg1_0__imm_95_31,
    2174             :   Convert__SVEPredicateHReg1_0__SVEPattern1_1,
    2175             :   Convert__SVEPredicateSReg1_0__SVEPattern1_1,
    2176             :   Convert__SVEPredicateDReg1_0__SVEPattern1_1,
    2177             :   Convert__SVEPredicateBReg1_0__SVEPattern1_1,
    2178             :   Convert__Reg1_0__SImm61_1,
    2179             :   Convert__regLR,
    2180             :   Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_311_2,
    2181             :   Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_631_2,
    2182             :   Convert__VectorReg641_1__VectorReg1281_2__Imm1_321_3,
    2183             :   Convert__VectorReg641_1__VectorReg1281_2__Imm1_161_3,
    2184             :   Convert__VectorReg641_1__VectorReg1281_2__Imm1_81_3,
    2185             :   Convert__VectorReg641_0__VectorReg1281_2__Imm1_321_4,
    2186             :   Convert__VectorReg641_0__VectorReg1281_2__Imm1_161_4,
    2187             :   Convert__VectorReg641_0__VectorReg1281_2__Imm1_81_4,
    2188             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_81_3,
    2189             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3,
    2190             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_161_3,
    2191             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4,
    2192             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4,
    2193             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4,
    2194             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg641_3,
    2195             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg641_4,
    2196             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2,
    2197             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2,
    2198             :   Convert__VectorReg1281_1__VectorReg1281_2__VectorReg641_3,
    2199             :   Convert__VectorReg1281_0__VectorReg1281_2__VectorReg641_4,
    2200             :   Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3,
    2201             :   Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3,
    2202             :   Convert__imm_95_0__Tie0_1_1__imm_95_0__imm_95_0,
    2203             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_1__VectorReg1281_2__VectorIndexS1_3,
    2204             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_1__VectorReg1281_2__VectorIndexS1_3,
    2205             :   Convert__imm_95_4,
    2206             :   Convert__imm_95_5,
    2207             :   Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3,
    2208             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2,
    2209             :   Convert__Reg1_0__Reg1_1__Imm0_631_2,
    2210             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm0_71_3,
    2211             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm0_631_3,
    2212             :   Convert__VectorReg641_1__VectorReg641_2__Imm0_311_3,
    2213             :   Convert__VectorReg641_1__VectorReg641_2__Imm0_151_3,
    2214             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm0_311_3,
    2215             :   Convert__VectorReg641_1__VectorReg641_2__Imm0_71_3,
    2216             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm0_151_3,
    2217             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm0_71_4,
    2218             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm0_631_4,
    2219             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm0_311_4,
    2220             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm0_151_4,
    2221             :   Convert__VectorReg641_0__VectorReg641_2__Imm0_311_4,
    2222             :   Convert__VectorReg641_0__VectorReg641_2__Imm0_151_4,
    2223             :   Convert__VectorReg641_0__VectorReg641_2__Imm0_71_4,
    2224             :   Convert__VectorReg1281_1__VectorReg641_2,
    2225             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2,
    2226             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_71_3,
    2227             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_631_3,
    2228             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_311_3,
    2229             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_151_3,
    2230             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_311_3,
    2231             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_71_3,
    2232             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_151_3,
    2233             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_71_4,
    2234             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_631_4,
    2235             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_311_4,
    2236             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_151_4,
    2237             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_311_4,
    2238             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_151_4,
    2239             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_71_4,
    2240             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4,
    2241             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4,
    2242             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6,
    2243             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6,
    2244             :   Convert__Reg1_1__VectorReg1281_2__VectorIndexB1_3,
    2245             :   Convert__Reg1_1__VectorReg1281_2__VectorIndexH1_3,
    2246             :   Convert__VectorReg1281_1__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4,
    2247             :   Convert__VectorReg1281_1__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4,
    2248             :   Convert__VectorReg1281_0__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6,
    2249             :   Convert__VectorReg1281_0__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6,
    2250             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
    2251             :   Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR161_2__VectorRegLo1_3__VectorIndexH1_4,
    2252             :   Convert__FPRAsmOperandFPR641_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__VectorIndexS1_4,
    2253             :   Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR161_1__VectorRegLo1_2__VectorIndexH1_4,
    2254             :   Convert__FPRAsmOperandFPR641_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__VectorIndexS1_4,
    2255             :   Convert__FPRAsmOperandFPR321_1__FPRAsmOperandFPR161_2__VectorRegLo1_3__VectorIndexH1_4,
    2256             :   Convert__FPRAsmOperandFPR641_1__FPRAsmOperandFPR321_2__VectorReg1281_3__VectorIndexS1_4,
    2257             :   Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR161_1__VectorRegLo1_2__VectorIndexH1_4,
    2258             :   Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR321_1__VectorReg1281_2__VectorIndexS1_4,
    2259             :   Convert__Reg1_0__Reg1_1__Imm1_81_2,
    2260             :   Convert__Reg1_0__Reg1_1__Imm0_151_2,
    2261             :   Convert__Reg1_0__Reg1_1__Imm0_311_2,
    2262             :   Convert__Reg1_0__Reg1_1__Imm0_71_2,
    2263             :   Convert__VectorReg641_1__VectorReg1281_2,
    2264             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm1_641_2,
    2265             :   Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_641_3,
    2266             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_321_3,
    2267             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_161_3,
    2268             :   Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_81_3,
    2269             :   Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_641_4,
    2270             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_321_4,
    2271             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_161_4,
    2272             :   Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_81_4,
    2273             :   Convert__VectorReg1281_1__VectorReg1281_2__Imm1_81_3,
    2274             :   Convert__VectorReg641_1__VectorReg641_2__Imm1_81_3,
    2275             :   Convert__VectorReg1281_0__VectorReg1281_2__Imm1_81_4,
    2276             :   Convert__VectorReg641_0__VectorReg641_2__Imm1_81_4,
    2277             :   Convert__VectorReg1281_1__VectorReg641_2__Imm0_311_3,
    2278             :   Convert__VectorReg1281_1__VectorReg641_2__Imm0_151_3,
    2279             :   Convert__VectorReg1281_1__VectorReg641_2__Imm0_71_3,
    2280             :   Convert__VectorReg1281_0__VectorReg641_2__Imm0_311_4,
    2281             :   Convert__VectorReg1281_0__VectorReg641_2__Imm0_151_4,
    2282             :   Convert__VectorReg1281_0__VectorReg641_2__Imm0_71_4,
    2283             :   Convert__TypedVectorList1_081_0__VectorIndexB1_1__Reg1_3,
    2284             :   Convert__TypedVectorList1_0641_0__VectorIndexD1_1__Reg1_3,
    2285             :   Convert__TypedVectorList1_0161_0__VectorIndexH1_1__Reg1_3,
    2286             :   Convert__TypedVectorList1_0321_0__VectorIndexS1_1__Reg1_3,
    2287             :   Convert__VecListOne1281_1__VectorIndexB1_2__Reg1_4,
    2288             :   Convert__VecListOne1281_1__VectorIndexD1_2__Reg1_4,
    2289             :   Convert__VecListOne1281_1__VectorIndexH1_2__Reg1_4,
    2290             :   Convert__VecListOne1281_1__VectorIndexS1_2__Reg1_4,
    2291             :   Convert__Reg1_3__TypedVectorList1_081_0__VectorIndexB1_1__Tie0_4_4__regXZR,
    2292             :   Convert__Reg1_3__TypedVectorList1_081_0__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    2293             :   Convert__Reg1_3__TypedVectorList1_0641_0__VectorIndexD1_1__Tie0_4_4__regXZR,
    2294             :   Convert__Reg1_3__TypedVectorList1_0641_0__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    2295             :   Convert__Reg1_3__TypedVectorList1_0161_0__VectorIndexH1_1__Tie0_4_4__regXZR,
    2296             :   Convert__Reg1_3__TypedVectorList1_0161_0__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    2297             :   Convert__Reg1_3__TypedVectorList1_0321_0__VectorIndexS1_1__Tie0_4_4__regXZR,
    2298             :   Convert__Reg1_3__TypedVectorList1_0321_0__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    2299             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexB1_2__Tie0_5_5__regXZR,
    2300             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    2301             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexD1_2__Tie0_5_5__regXZR,
    2302             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    2303             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexH1_2__Tie0_5_5__regXZR,
    2304             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    2305             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexS1_2__Tie0_5_5__regXZR,
    2306             :   Convert__Reg1_4__VecListOne1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    2307             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2308             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2309             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0,
    2310             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2311             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0,
    2312             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2313             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2314             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2315             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2316             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0,
    2317             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2318             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0,
    2319             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2320             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2321             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4,
    2322             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4,
    2323             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4,
    2324             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2325             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4,
    2326             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4,
    2327             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4,
    2328             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4,
    2329             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2330             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2331             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2332             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2333             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4,
    2334             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4,
    2335             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4,
    2336             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2337             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4,
    2338             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4,
    2339             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4,
    2340             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4,
    2341             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
    2342             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
    2343             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
    2344             :   Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
    2345             :   Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
    2346             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
    2347             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
    2348             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
    2349             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
    2350             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4,
    2351             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4,
    2352             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW6481_4,
    2353             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4,
    2354             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW6481_4,
    2355             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4,
    2356             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
    2357             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4,
    2358             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4,
    2359             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW6481_4,
    2360             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4,
    2361             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW6481_4,
    2362             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4,
    2363             :   Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2364             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2365             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4,
    2366             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW3281_4,
    2367             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4,
    2368             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW3281_4,
    2369             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4,
    2370             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2371             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4,
    2372             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4,
    2373             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4,
    2374             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4,
    2375             :   Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2376             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2377             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4,
    2378             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW3281_4,
    2379             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4,
    2380             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW3281_4,
    2381             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4,
    2382             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2383             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4,
    2384             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4,
    2385             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4,
    2386             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4,
    2387             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
    2388             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4,
    2389             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4,
    2390             :   Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4,
    2391             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
    2392             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4,
    2393             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4,
    2394             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4,
    2395             :   Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4,
    2396             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
    2397             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4,
    2398             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4,
    2399             :   Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4,
    2400             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
    2401             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4,
    2402             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4,
    2403             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4,
    2404             :   Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4,
    2405             :   Convert__TypedVectorList2_081_0__VectorIndexB1_1__Reg1_3,
    2406             :   Convert__TypedVectorList2_0641_0__VectorIndexD1_1__Reg1_3,
    2407             :   Convert__TypedVectorList2_0161_0__VectorIndexH1_1__Reg1_3,
    2408             :   Convert__TypedVectorList2_0321_0__VectorIndexS1_1__Reg1_3,
    2409             :   Convert__VecListTwo1281_1__VectorIndexB1_2__Reg1_4,
    2410             :   Convert__VecListTwo1281_1__VectorIndexD1_2__Reg1_4,
    2411             :   Convert__VecListTwo1281_1__VectorIndexH1_2__Reg1_4,
    2412             :   Convert__VecListTwo1281_1__VectorIndexS1_2__Reg1_4,
    2413             :   Convert__Reg1_3__TypedVectorList2_081_0__VectorIndexB1_1__Tie0_4_4__regXZR,
    2414             :   Convert__Reg1_3__TypedVectorList2_081_0__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    2415             :   Convert__Reg1_3__TypedVectorList2_0641_0__VectorIndexD1_1__Tie0_4_4__regXZR,
    2416             :   Convert__Reg1_3__TypedVectorList2_0641_0__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    2417             :   Convert__Reg1_3__TypedVectorList2_0161_0__VectorIndexH1_1__Tie0_4_4__regXZR,
    2418             :   Convert__Reg1_3__TypedVectorList2_0161_0__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    2419             :   Convert__Reg1_3__TypedVectorList2_0321_0__VectorIndexS1_1__Tie0_4_4__regXZR,
    2420             :   Convert__Reg1_3__TypedVectorList2_0321_0__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    2421             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexB1_2__Tie0_5_5__regXZR,
    2422             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    2423             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexD1_2__Tie0_5_5__regXZR,
    2424             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    2425             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexH1_2__Tie0_5_5__regXZR,
    2426             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    2427             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexS1_2__Tie0_5_5__regXZR,
    2428             :   Convert__Reg1_4__VecListTwo1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    2429             :   Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2430             :   Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2431             :   Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4,
    2432             :   Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2433             :   Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
    2434             :   Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4,
    2435             :   Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2436             :   Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2437             :   Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4,
    2438             :   Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2439             :   Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
    2440             :   Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4,
    2441             :   Convert__TypedVectorList3_081_0__VectorIndexB1_1__Reg1_3,
    2442             :   Convert__TypedVectorList3_0641_0__VectorIndexD1_1__Reg1_3,
    2443             :   Convert__TypedVectorList3_0161_0__VectorIndexH1_1__Reg1_3,
    2444             :   Convert__TypedVectorList3_0321_0__VectorIndexS1_1__Reg1_3,
    2445             :   Convert__VecListThree1281_1__VectorIndexB1_2__Reg1_4,
    2446             :   Convert__VecListThree1281_1__VectorIndexD1_2__Reg1_4,
    2447             :   Convert__VecListThree1281_1__VectorIndexH1_2__Reg1_4,
    2448             :   Convert__VecListThree1281_1__VectorIndexS1_2__Reg1_4,
    2449             :   Convert__Reg1_3__TypedVectorList3_081_0__VectorIndexB1_1__Tie0_4_4__regXZR,
    2450             :   Convert__Reg1_3__TypedVectorList3_081_0__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    2451             :   Convert__Reg1_3__TypedVectorList3_0641_0__VectorIndexD1_1__Tie0_4_4__regXZR,
    2452             :   Convert__Reg1_3__TypedVectorList3_0641_0__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    2453             :   Convert__Reg1_3__TypedVectorList3_0161_0__VectorIndexH1_1__Tie0_4_4__regXZR,
    2454             :   Convert__Reg1_3__TypedVectorList3_0161_0__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    2455             :   Convert__Reg1_3__TypedVectorList3_0321_0__VectorIndexS1_1__Tie0_4_4__regXZR,
    2456             :   Convert__Reg1_3__TypedVectorList3_0321_0__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    2457             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexB1_2__Tie0_5_5__regXZR,
    2458             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    2459             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexD1_2__Tie0_5_5__regXZR,
    2460             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    2461             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexH1_2__Tie0_5_5__regXZR,
    2462             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    2463             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexS1_2__Tie0_5_5__regXZR,
    2464             :   Convert__Reg1_4__VecListThree1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    2465             :   Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2466             :   Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2467             :   Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4,
    2468             :   Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2469             :   Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
    2470             :   Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4,
    2471             :   Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2472             :   Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2473             :   Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4,
    2474             :   Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2475             :   Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
    2476             :   Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4,
    2477             :   Convert__TypedVectorList4_081_0__VectorIndexB1_1__Reg1_3,
    2478             :   Convert__TypedVectorList4_0641_0__VectorIndexD1_1__Reg1_3,
    2479             :   Convert__TypedVectorList4_0161_0__VectorIndexH1_1__Reg1_3,
    2480             :   Convert__TypedVectorList4_0321_0__VectorIndexS1_1__Reg1_3,
    2481             :   Convert__VecListFour1281_1__VectorIndexB1_2__Reg1_4,
    2482             :   Convert__VecListFour1281_1__VectorIndexD1_2__Reg1_4,
    2483             :   Convert__VecListFour1281_1__VectorIndexH1_2__Reg1_4,
    2484             :   Convert__VecListFour1281_1__VectorIndexS1_2__Reg1_4,
    2485             :   Convert__Reg1_3__TypedVectorList4_081_0__VectorIndexB1_1__Tie0_4_4__regXZR,
    2486             :   Convert__Reg1_3__TypedVectorList4_081_0__VectorIndexB1_1__Tie0_4_4__Reg1_5,
    2487             :   Convert__Reg1_3__TypedVectorList4_0641_0__VectorIndexD1_1__Tie0_4_4__regXZR,
    2488             :   Convert__Reg1_3__TypedVectorList4_0641_0__VectorIndexD1_1__Tie0_4_4__Reg1_5,
    2489             :   Convert__Reg1_3__TypedVectorList4_0161_0__VectorIndexH1_1__Tie0_4_4__regXZR,
    2490             :   Convert__Reg1_3__TypedVectorList4_0161_0__VectorIndexH1_1__Tie0_4_4__Reg1_5,
    2491             :   Convert__Reg1_3__TypedVectorList4_0321_0__VectorIndexS1_1__Tie0_4_4__regXZR,
    2492             :   Convert__Reg1_3__TypedVectorList4_0321_0__VectorIndexS1_1__Tie0_4_4__Reg1_5,
    2493             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexB1_2__Tie0_5_5__regXZR,
    2494             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6,
    2495             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexD1_2__Tie0_5_5__regXZR,
    2496             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6,
    2497             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexH1_2__Tie0_5_5__regXZR,
    2498             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6,
    2499             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexS1_2__Tie0_5_5__regXZR,
    2500             :   Convert__Reg1_4__VecListFour1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6,
    2501             :   Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2502             :   Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
    2503             :   Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4,
    2504             :   Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2505             :   Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
    2506             :   Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4,
    2507             :   Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2508             :   Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
    2509             :   Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4,
    2510             :   Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
    2511             :   Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
    2512             :   Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4,
    2513             :   Convert__regWZR__Reg1_0__Reg1_2,
    2514             :   Convert__regXZR__Reg1_0__Reg1_2,
    2515             :   Convert__Reg1_0__Reg1_1__Reg1_2__GPR64sp01_4,
    2516             :   Convert__Reg1_0__Tie0_1_1__Reg1_1,
    2517             :   Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7,
    2518             :   Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15,
    2519             :   Convert__VectorReg1281_1__VectorReg641_2__imm_95_0,
    2520             :   Convert__VectorReg1281_0__VectorReg641_2__imm_95_0,
    2521             :   Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0,
    2522             :   Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0,
    2523             :   Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_31,
    2524             :   Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__regXZR,
    2525             :   Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__Reg1_4,
    2526             :   Convert__Reg1_0__Imm0_71_1__SysCR1_2__SysCR1_3__Imm0_71_4,
    2527             :   Convert__VectorReg1281_1__VecListFour1281_2__VectorReg1281_3,
    2528             :   Convert__VectorReg1281_1__VecListOne1281_2__VectorReg1281_3,
    2529             :   Convert__VectorReg1281_1__VecListThree1281_2__VectorReg1281_3,
    2530             :   Convert__VectorReg1281_1__VecListTwo1281_2__VectorReg1281_3,
    2531             :   Convert__VectorReg641_1__VecListFour1281_2__VectorReg641_3,
    2532             :   Convert__VectorReg641_1__VecListOne1281_2__VectorReg641_3,
    2533             :   Convert__VectorReg641_1__VecListThree1281_2__VectorReg641_3,
    2534             :   Convert__VectorReg641_1__VecListTwo1281_2__VectorReg641_3,
    2535             :   Convert__VectorReg1281_0__TypedVectorList4_1681_2__VectorReg1281_3,
    2536             :   Convert__VectorReg1281_0__TypedVectorList1_1681_2__VectorReg1281_3,
    2537             :   Convert__VectorReg1281_0__TypedVectorList3_1681_2__VectorReg1281_3,
    2538             :   Convert__VectorReg1281_0__TypedVectorList2_1681_2__VectorReg1281_3,
    2539             :   Convert__VectorReg641_0__TypedVectorList4_1681_2__VectorReg641_3,
    2540             :   Convert__VectorReg641_0__TypedVectorList1_1681_2__VectorReg641_3,
    2541             :   Convert__VectorReg641_0__TypedVectorList3_1681_2__VectorReg641_3,
    2542             :   Convert__VectorReg641_0__TypedVectorList2_1681_2__VectorReg641_3,
    2543             :   Convert__Reg1_0__Imm0_311_1__BranchTarget141_2,
    2544             :   Convert__Reg1_0__Imm32_631_1__BranchTarget141_2,
    2545             :   Convert__GPR32as641_0__TBZImm0_311_1__BranchTarget141_2,
    2546             :   Convert__VectorReg1281_1__Tie0_2_2__VecListFour1281_2__VectorReg1281_3,
    2547             :   Convert__VectorReg1281_1__Tie0_2_2__VecListOne1281_2__VectorReg1281_3,
    2548             :   Convert__VectorReg1281_1__Tie0_2_2__VecListThree1281_2__VectorReg1281_3,
    2549             :   Convert__VectorReg1281_1__Tie0_2_2__VecListTwo1281_2__VectorReg1281_3,
    2550             :   Convert__VectorReg641_1__Tie0_2_2__VecListFour1281_2__VectorReg641_3,
    2551             :   Convert__VectorReg641_1__Tie0_2_2__VecListOne1281_2__VectorReg641_3,
    2552             :   Convert__VectorReg641_1__Tie0_2_2__VecListThree1281_2__VectorReg641_3,
    2553             :   Convert__VectorReg641_1__Tie0_2_2__VecListTwo1281_2__VectorReg641_3,
    2554             :   Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg1281_3,
    2555             :   Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg1281_3,
    2556             :   Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList3_1681_2__VectorReg1281_3,
    2557             :   Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList2_1681_2__VectorReg1281_3,
    2558             :   Convert__VectorReg641_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg641_3,
    2559             :   Convert__VectorReg641_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg641_3,
    2560             :   Convert__VectorReg641_0__Tie0_1_1__TypedVectorList3_1681_2__VectorReg641_3,
    2561             :   Convert__VectorReg641_0__Tie0_1_1__TypedVectorList2_1681_2__VectorReg641_3,
    2562             :   Convert__regWZR__Reg1_0__LogicalImm321_1,
    2563             :   Convert__regXZR__Reg1_0__LogicalImm641_1,
    2564             :   Convert__regWZR__Reg1_0__Reg1_1__LogicalShifter321_2,
    2565             :   Convert__regXZR__Reg1_0__Reg1_1__LogicalShifter641_2,
    2566             :   Convert__imm_95_2,
    2567             :   Convert__imm_95_3,
    2568             :   Convert__imm_95_1,
    2569             :   Convert__SVEPredicateHReg1_0__SVEPredicateHReg1_1__SVEPredicateHReg1_2,
    2570             :   Convert__SVEPredicateSReg1_0__SVEPredicateSReg1_1__SVEPredicateSReg1_2,
    2571             :   Convert__SVEPredicateDReg1_0__SVEPredicateDReg1_1__SVEPredicateDReg1_2,
    2572             :   Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1__SVEPredicateBReg1_2,
    2573             :   CVT_NUM_SIGNATURES
    2574             : };
    2575             : 
    2576             : } // end anonymous namespace
    2577             : 
    2578             : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
    2579             :   // Convert__Reg1_0__Reg1_1
    2580             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
    2581             :   // Convert__VectorReg1281_1__VectorReg1281_2
    2582             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2583             :   // Convert__VectorReg641_1__VectorReg641_2
    2584             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2585             :   // Convert__VectorReg1281_0__VectorReg1281_2
    2586             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2587             :   // Convert__VectorReg641_0__VectorReg641_2
    2588             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2589             :   // Convert__Reg1_0__Reg1_1__Reg1_2
    2590             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    2591             :   // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16
    2592             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_16, 0, CVT_Done },
    2593             :   // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24
    2594             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_24, 0, CVT_Done },
    2595             :   // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
    2596             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    2597             :   // Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2
    2598             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addAddSubImmNegOperands, 3, CVT_Done },
    2599             :   // Convert__Reg1_0__Reg1_1__AddSubImm2_2
    2600             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addAddSubImmOperands, 3, CVT_Done },
    2601             :   // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2
    2602             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    2603             :   // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2
    2604             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    2605             :   // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2
    2606             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    2607             :   // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2
    2608             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    2609             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3
    2610             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    2611             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3
    2612             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    2613             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3
    2614             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2615             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3
    2616             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtendOperands, 4, CVT_Done },
    2617             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3
    2618             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2619             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Extend641_3
    2620             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtend64Operands, 4, CVT_Done },
    2621             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ExtendLSL641_3
    2622             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtend64Operands, 4, CVT_Done },
    2623             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4
    2624             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
    2625             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4
    2626             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    2627             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5
    2628             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
    2629             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5
    2630             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
    2631             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5
    2632             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
    2633             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorBReg1_5
    2634             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
    2635             :   // Convert__VectorReg641_1__VectorReg1281_2__VectorReg1281_3
    2636             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    2637             :   // Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4
    2638             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
    2639             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3
    2640             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    2641             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4
    2642             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
    2643             :   // Convert__FPRAsmOperandFPR641_1__VectorReg1281_2
    2644             :   { CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2645             :   // Convert__FPRAsmOperandFPR641_0__VectorReg1281_1
    2646             :   { CVT_95_addRegOperands, 1, CVT_95_addVectorReg128Operands, 2, CVT_Done },
    2647             :   // Convert__Reg1_0__Reg1_1__SImm61_2
    2648             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    2649             :   // Convert__Reg1_1__VectorReg1281_2
    2650             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2651             :   // Convert__Reg1_1__VectorReg641_2
    2652             :   { CVT_95_Reg, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2653             :   // Convert__Reg1_0__VectorReg1281_1
    2654             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_Done },
    2655             :   // Convert__Reg1_0__VectorReg641_1
    2656             :   { CVT_95_Reg, 1, CVT_95_addVectorReg64Operands, 2, CVT_Done },
    2657             :   // Convert__Reg1_0__AdrLabel1_1
    2658             :   { CVT_95_Reg, 1, CVT_95_addAdrLabelOperands, 2, CVT_Done },
    2659             :   // Convert__Reg1_0__AdrpLabel1_1
    2660             :   { CVT_95_Reg, 1, CVT_95_addAdrpLabelOperands, 2, CVT_Done },
    2661             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2
    2662             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2663             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2
    2664             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2665             :   // Convert__Reg1_0__Reg1_1__LogicalImm321_2
    2666             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 3, CVT_Done },
    2667             :   // Convert__Reg1_0__Reg1_1__LogicalImm641_2
    2668             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 3, CVT_Done },
    2669             :   // Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2
    2670             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_, 3, CVT_Done },
    2671             :   // Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2
    2672             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 3, CVT_Done },
    2673             :   // Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2
    2674             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 3, CVT_Done },
    2675             :   // Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2
    2676             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_, 3, CVT_Done },
    2677             :   // Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3
    2678             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2679             :   // Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3
    2680             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2681             :   // Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31
    2682             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_imm_95_31, 0, CVT_Done },
    2683             :   // Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63
    2684             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_imm_95_63, 0, CVT_Done },
    2685             :   // Convert__Reg1_0
    2686             :   { CVT_95_Reg, 1, CVT_Done },
    2687             :   // Convert_NoOperands
    2688             :   { CVT_Done },
    2689             :   // Convert__BranchTarget261_0
    2690             :   { CVT_95_addBranchTarget26Operands, 1, CVT_Done },
    2691             :   // Convert__CondCode1_1__PCRelLabel191_2
    2692             :   { CVT_95_addCondCodeOperands, 2, CVT_95_addPCRelLabel19Operands, 3, CVT_Done },
    2693             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_311_2__Imm0_311_3
    2694             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2695             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2__Imm0_631_3
    2696             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2697             :   // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__imm_95_0
    2698             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    2699             :   // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__imm_95_0
    2700             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    2701             :   // Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2
    2702             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_, 3, CVT_Done },
    2703             :   // Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2
    2704             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_, 3, CVT_Done },
    2705             :   // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__imm_95_0
    2706             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    2707             :   // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__imm_95_0
    2708             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    2709             :   // Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2
    2710             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_, 3, CVT_Done },
    2711             :   // Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2
    2712             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_, 3, CVT_Done },
    2713             :   // Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2
    2714             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_, 3, CVT_Done },
    2715             :   // Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2
    2716             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_, 3, CVT_Done },
    2717             :   // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3
    2718             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2719             :   // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    2720             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2721             :   // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3
    2722             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2723             :   // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    2724             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2725             :   // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3
    2726             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2727             :   // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    2728             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2729             :   // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3
    2730             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2731             :   // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    2732             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    2733             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3
    2734             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    2735             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4
    2736             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    2737             :   // Convert__Imm0_655351_0
    2738             :   { CVT_95_addImmOperands, 1, CVT_Done },
    2739             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3
    2740             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Done },
    2741             :   // Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3
    2742             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2743             :   // Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3
    2744             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_Done },
    2745             :   // Convert__Reg1_0__PCRelLabel191_1
    2746             :   { CVT_95_Reg, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
    2747             :   // Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3
    2748             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
    2749             :   // Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3
    2750             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
    2751             :   // Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2
    2752             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 3, CVT_Done },
    2753             :   // Convert__imm_95_15
    2754             :   { CVT_imm_95_15, 0, CVT_Done },
    2755             :   // Convert__Imm0_151_0
    2756             :   { CVT_95_addImmOperands, 1, CVT_Done },
    2757             :   // Convert__Reg1_0__Reg1_2__Reg1_1
    2758             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
    2759             :   // Convert__VectorReg1281_1__VectorReg1281_3__VectorReg1281_2
    2760             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2761             :   // Convert__VectorReg641_1__VectorReg641_3__VectorReg641_2
    2762             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 4, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2763             :   // Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2
    2764             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2765             :   // Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2
    2766             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 5, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2767             :   // Convert__regWZR__Reg1_0__Reg1_1__imm_95_16
    2768             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_16, 0, CVT_Done },
    2769             :   // Convert__regXZR__Reg1_0__Reg1_1__imm_95_24
    2770             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_24, 0, CVT_Done },
    2771             :   // Convert__regWZR__Reg1_0__Reg1_1__imm_95_0
    2772             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
    2773             :   // Convert__regWZR__Reg1_0__AddSubImmNeg2_1
    2774             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addAddSubImmNegOperands, 2, CVT_Done },
    2775             :   // Convert__regWZR__Reg1_0__AddSubImm2_1
    2776             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addAddSubImmOperands, 2, CVT_Done },
    2777             :   // Convert__regXZR__Reg1_0__Reg1_1__imm_95_0
    2778             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
    2779             :   // Convert__regXZR__Reg1_0__AddSubImmNeg2_1
    2780             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addAddSubImmNegOperands, 2, CVT_Done },
    2781             :   // Convert__regXZR__Reg1_0__AddSubImm2_1
    2782             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addAddSubImmOperands, 2, CVT_Done },
    2783             :   // Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2
    2784             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    2785             :   // Convert__regWZR__Reg1_0__Reg1_1__Extend1_2
    2786             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtendOperands, 3, CVT_Done },
    2787             :   // Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2
    2788             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    2789             :   // Convert__regXZR__Reg1_0__Reg1_1__Extend1_2
    2790             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtendOperands, 3, CVT_Done },
    2791             :   // Convert__regXZR__Reg1_0__Reg1_1__ExtendLSL641_2
    2792             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtend64Operands, 3, CVT_Done },
    2793             :   // Convert__imm_95_20
    2794             :   { CVT_imm_95_20, 0, CVT_Done },
    2795             :   // Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3
    2796             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
    2797             :   // Convert__Reg1_0__regWZR__regWZR__CondCode1_1
    2798             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_regWZR, 0, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2799             :   // Convert__Reg1_0__regXZR__regXZR__CondCode1_1
    2800             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_regXZR, 0, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2801             :   // Convert__imm_95_0
    2802             :   { CVT_imm_95_0, 0, CVT_Done },
    2803             :   // Convert__Barrier1_0
    2804             :   { CVT_95_addBarrierOperands, 1, CVT_Done },
    2805             :   // Convert__SVEVectorHReg1_0__Reg1_1
    2806             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2807             :   // Convert__SVEVectorSReg1_0__Reg1_1
    2808             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2809             :   // Convert__SVEVectorDReg1_0__Reg1_1
    2810             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2811             :   // Convert__SVEVectorBReg1_0__Reg1_1
    2812             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2813             :   // Convert__VectorReg1281_1__Reg1_2
    2814             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_Reg, 3, CVT_Done },
    2815             :   // Convert__VectorReg641_1__Reg1_2
    2816             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_Reg, 3, CVT_Done },
    2817             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_2
    2818             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
    2819             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_2
    2820             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
    2821             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_2
    2822             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
    2823             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_2
    2824             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
    2825             :   // Convert__VectorReg1281_0__Reg1_2
    2826             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_Reg, 3, CVT_Done },
    2827             :   // Convert__VectorReg641_0__Reg1_2
    2828             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_Reg, 3, CVT_Done },
    2829             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexB1_3
    2830             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2831             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexD1_3
    2832             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2833             :   // Convert__VectorReg641_1__VectorReg1281_2__VectorIndexS1_3
    2834             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2835             :   // Convert__VectorReg641_1__VectorReg1281_2__VectorIndexH1_3
    2836             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2837             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexS1_3
    2838             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2839             :   // Convert__VectorReg641_1__VectorReg1281_2__VectorIndexB1_3
    2840             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2841             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorIndexH1_3
    2842             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2843             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexH1_3
    2844             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2845             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexS1_3
    2846             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2847             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexD1_3
    2848             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2849             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndexB1_3
    2850             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2851             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexB1_4
    2852             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2853             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexD1_4
    2854             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2855             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexS1_4
    2856             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2857             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorIndexH1_4
    2858             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2859             :   // Convert__VectorReg641_0__VectorReg1281_2__VectorIndexS1_4
    2860             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2861             :   // Convert__VectorReg641_0__VectorReg1281_2__VectorIndexH1_4
    2862             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2863             :   // Convert__VectorReg641_0__VectorReg1281_2__VectorIndexB1_4
    2864             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2865             :   // Convert__imm_95_16
    2866             :   { CVT_imm_95_16, 0, CVT_Done },
    2867             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__Imm1_4
    2868             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    2869             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__Imm1_4
    2870             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    2871             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__Imm1_6
    2872             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addImmOperands, 7, CVT_Done },
    2873             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__Imm1_6
    2874             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addImmOperands, 7, CVT_Done },
    2875             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_311_3
    2876             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2877             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_631_3
    2878             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2879             :   // Convert__FPRAsmOperandFPR161_1__VectorReg641_2
    2880             :   { CVT_95_addRegOperands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2881             :   // Convert__FPRAsmOperandFPR321_1__VectorReg641_2
    2882             :   { CVT_95_addRegOperands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2883             :   // Convert__FPRAsmOperandFPR161_0__VectorReg641_1
    2884             :   { CVT_95_addRegOperands, 1, CVT_95_addVectorReg64Operands, 2, CVT_Done },
    2885             :   // Convert__FPRAsmOperandFPR321_0__VectorReg641_1
    2886             :   { CVT_95_addRegOperands, 1, CVT_95_addVectorReg64Operands, 2, CVT_Done },
    2887             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__ComplexRotationOdd1_4
    2888             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
    2889             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__ComplexRotationOdd1_4
    2890             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
    2891             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6
    2892             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
    2893             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__ComplexRotationOdd1_6
    2894             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
    2895             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__ComplexRotationEven1_4
    2896             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
    2897             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3__ComplexRotationEven1_4
    2898             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
    2899             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexD1_4__ComplexRotationEven1_5
    2900             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
    2901             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4__ComplexRotationEven1_5
    2902             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
    2903             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4__ComplexRotationEven1_5
    2904             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
    2905             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6
    2906             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
    2907             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4__ComplexRotationEven1_6
    2908             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
    2909             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7
    2910             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
    2911             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6__ComplexRotationEven1_7
    2912             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
    2913             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexD1_6__ComplexRotationEven1_7
    2914             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
    2915             :   // Convert__VectorReg1281_0__VectorReg641_2
    2916             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    2917             :   // Convert__VectorReg641_0__VectorReg1281_2
    2918             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    2919             :   // Convert__Reg1_0__Reg1_1__Imm1_161_2
    2920             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    2921             :   // Convert__Reg1_0__Reg1_1__Imm1_321_2
    2922             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    2923             :   // Convert__Reg1_0__Reg1_1__Imm1_641_2
    2924             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    2925             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_641_3
    2926             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2927             :   // Convert__VectorReg641_1__VectorReg641_2__Imm1_321_3
    2928             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2929             :   // Convert__VectorReg641_1__VectorReg641_2__Imm1_161_3
    2930             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2931             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_321_3
    2932             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2933             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_161_3
    2934             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2935             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_641_4
    2936             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    2937             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_321_4
    2938             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    2939             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_161_4
    2940             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    2941             :   // Convert__VectorReg641_0__VectorReg641_2__Imm1_321_4
    2942             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    2943             :   // Convert__VectorReg641_0__VectorReg641_2__Imm1_161_4
    2944             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    2945             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
    2946             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
    2947             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4
    2948             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2949             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4
    2950             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2951             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4
    2952             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2953             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4
    2954             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2955             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__VectorIndexH1_4
    2956             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2957             :   // Convert__FPRAsmOperandFPR641_1__Tie0_2_2__FPRAsmOperandFPR641_2__VectorReg1281_3__VectorIndexD1_4
    2958             :   { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2959             :   // Convert__FPRAsmOperandFPR161_1__Tie0_2_2__FPRAsmOperandFPR161_2__VectorRegLo1_3__VectorIndexH1_4
    2960             :   { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2961             :   // Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__VectorIndexS1_4
    2962             :   { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2963             :   // Convert__FPRAsmOperandFPR161_0__Tie0_1_1__FPRAsmOperandFPR161_1__VectorRegLo1_2__VectorIndexH1_4
    2964             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2965             :   // Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__VectorIndexS1_4
    2966             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2967             :   // Convert__FPRAsmOperandFPR641_0__Tie0_1_1__FPRAsmOperandFPR641_1__VectorReg1281_2__VectorIndexD1_4
    2968             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    2969             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6
    2970             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    2971             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6
    2972             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    2973             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorRegLo1_4__VectorIndexH1_6
    2974             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    2975             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6
    2976             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    2977             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6
    2978             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    2979             :   // Convert__Reg1_0__FPImm1_1
    2980             :   { CVT_95_Reg, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
    2981             :   // Convert__VectorReg1281_1__FPImm1_2
    2982             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addFPImmOperands, 3, CVT_Done },
    2983             :   // Convert__VectorReg641_1__FPImm1_2
    2984             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addFPImmOperands, 3, CVT_Done },
    2985             :   // Convert__Reg1_0__regWZR
    2986             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_Done },
    2987             :   // Convert__Reg1_0__regXZR
    2988             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_Done },
    2989             :   // Convert__VectorReg1281_0__FPImm1_2
    2990             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addFPImmOperands, 3, CVT_Done },
    2991             :   // Convert__VectorReg641_0__FPImm1_2
    2992             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addFPImmOperands, 3, CVT_Done },
    2993             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndex11_3
    2994             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2995             :   // Convert__VectorReg1281_1__Reg1_3__VectorIndex11_2
    2996             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_Reg, 4, CVT_95_addVectorIndexOperands, 3, CVT_Done },
    2997             :   // Convert__Reg1_0__VectorReg1281_1__VectorIndex11_3
    2998             :   { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    2999             :   // Convert__VectorReg1281_0__Reg1_3__VectorIndex11_2
    3000             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_Reg, 4, CVT_95_addVectorIndexOperands, 3, CVT_Done },
    3001             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__VectorIndexD1_4
    3002             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3003             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4
    3004             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3005             :   // Convert__VectorReg641_1__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4
    3006             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3007             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__VectorIndexS1_4
    3008             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3009             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorRegLo1_3__VectorIndexH1_4
    3010             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3011             :   // Convert__FPRAsmOperandFPR641_1__FPRAsmOperandFPR641_2__VectorReg1281_3__VectorIndexD1_4
    3012             :   { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3013             :   // Convert__FPRAsmOperandFPR161_1__FPRAsmOperandFPR161_2__VectorRegLo1_3__VectorIndexH1_4
    3014             :   { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3015             :   // Convert__FPRAsmOperandFPR321_1__FPRAsmOperandFPR321_2__VectorReg1281_3__VectorIndexS1_4
    3016             :   { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3017             :   // Convert__FPRAsmOperandFPR161_0__FPRAsmOperandFPR161_1__VectorRegLo1_2__VectorIndexH1_4
    3018             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3019             :   // Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__VectorReg1281_2__VectorIndexS1_4
    3020             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3021             :   // Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__VectorReg1281_2__VectorIndexD1_4
    3022             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3023             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorIndexD1_6
    3024             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    3025             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorIndexS1_6
    3026             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    3027             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorRegLo1_4__VectorIndexH1_6
    3028             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    3029             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6
    3030             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    3031             :   // Convert__VectorReg641_0__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6
    3032             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    3033             :   // Convert__Imm0_1271_0
    3034             :   { CVT_95_addImmOperands, 1, CVT_Done },
    3035             :   // Convert__SVEVectorHReg1_0__Reg1_1__Reg1_2
    3036             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    3037             :   // Convert__SVEVectorHReg1_0__Reg1_1__SImm51_2
    3038             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    3039             :   // Convert__SVEVectorHReg1_0__SImm51_1__Reg1_2
    3040             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    3041             :   // Convert__SVEVectorHReg1_0__SImm51_1__SImm51_2
    3042             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    3043             :   // Convert__SVEVectorSReg1_0__Reg1_1__Reg1_2
    3044             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    3045             :   // Convert__SVEVectorSReg1_0__Reg1_1__SImm51_2
    3046             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    3047             :   // Convert__SVEVectorSReg1_0__SImm51_1__Reg1_2
    3048             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    3049             :   // Convert__SVEVectorSReg1_0__SImm51_1__SImm51_2
    3050             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    3051             :   // Convert__SVEVectorDReg1_0__Reg1_1__Reg1_2
    3052             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    3053             :   // Convert__SVEVectorDReg1_0__Reg1_1__SImm51_2
    3054             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    3055             :   // Convert__SVEVectorDReg1_0__SImm51_1__Reg1_2
    3056             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    3057             :   // Convert__SVEVectorDReg1_0__SImm51_1__SImm51_2
    3058             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    3059             :   // Convert__SVEVectorBReg1_0__Reg1_1__Reg1_2
    3060             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    3061             :   // Convert__SVEVectorBReg1_0__Reg1_1__SImm51_2
    3062             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    3063             :   // Convert__SVEVectorBReg1_0__SImm51_1__Reg1_2
    3064             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    3065             :   // Convert__SVEVectorBReg1_0__SImm51_1__SImm51_2
    3066             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    3067             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_3
    3068             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
    3069             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_3
    3070             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
    3071             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_3
    3072             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
    3073             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_3
    3074             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
    3075             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexB1_2__Reg1_3
    3076             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
    3077             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexD1_2__Reg1_3
    3078             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
    3079             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexH1_2__Reg1_3
    3080             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
    3081             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexS1_2__Reg1_3
    3082             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
    3083             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexB1_2__VectorReg1281_3__VectorIndexB1_4
    3084             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3085             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexD1_2__VectorReg1281_3__VectorIndexD1_4
    3086             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3087             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexH1_2__VectorReg1281_3__VectorIndexH1_4
    3088             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3089             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorIndexS1_2__VectorReg1281_3__VectorIndexS1_4
    3090             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    3091             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexB1_2__VectorReg1281_3__VectorIndexB1_5
    3092             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 6, CVT_Done },
    3093             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexD1_2__VectorReg1281_3__VectorIndexD1_5
    3094             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 6, CVT_Done },
    3095             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexH1_2__VectorReg1281_3__VectorIndexH1_5
    3096             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 6, CVT_Done },
    3097             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorIndexS1_2__VectorReg1281_3__VectorIndexS1_5
    3098             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 6, CVT_Done },
    3099             :   // Convert__TypedVectorList4_1681_0__Reg1_2
    3100             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3101             :   // Convert__TypedVectorList4_1641_0__Reg1_2
    3102             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3103             :   // Convert__TypedVectorList4_2641_0__Reg1_2
    3104             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3105             :   // Convert__TypedVectorList4_2321_0__Reg1_2
    3106             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3107             :   // Convert__TypedVectorList4_4161_0__Reg1_2
    3108             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3109             :   // Convert__TypedVectorList4_4321_0__Reg1_2
    3110             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3111             :   // Convert__TypedVectorList4_881_0__Reg1_2
    3112             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3113             :   // Convert__TypedVectorList4_8161_0__Reg1_2
    3114             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3115             :   // Convert__TypedVectorList1_1681_0__Reg1_2
    3116             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3117             :   // Convert__TypedVectorList1_1641_0__Reg1_2
    3118             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3119             :   // Convert__TypedVectorList1_2641_0__Reg1_2
    3120             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3121             :   // Convert__TypedVectorList1_2321_0__Reg1_2
    3122             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3123             :   // Convert__TypedVectorList1_4161_0__Reg1_2
    3124             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3125             :   // Convert__TypedVectorList1_4321_0__Reg1_2
    3126             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3127             :   // Convert__TypedVectorList1_881_0__Reg1_2
    3128             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3129             :   // Convert__TypedVectorList1_8161_0__Reg1_2
    3130             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3131             :   // Convert__TypedVectorList3_1681_0__Reg1_2
    3132             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3133             :   // Convert__TypedVectorList3_1641_0__Reg1_2
    3134             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3135             :   // Convert__TypedVectorList3_2641_0__Reg1_2
    3136             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3137             :   // Convert__TypedVectorList3_2321_0__Reg1_2
    3138             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3139             :   // Convert__TypedVectorList3_4161_0__Reg1_2
    3140             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3141             :   // Convert__TypedVectorList3_4321_0__Reg1_2
    3142             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3143             :   // Convert__TypedVectorList3_881_0__Reg1_2
    3144             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3145             :   // Convert__TypedVectorList3_8161_0__Reg1_2
    3146             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3147             :   // Convert__TypedVectorList2_1681_0__Reg1_2
    3148             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3149             :   // Convert__TypedVectorList2_1641_0__Reg1_2
    3150             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3151             :   // Convert__TypedVectorList2_2641_0__Reg1_2
    3152             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3153             :   // Convert__TypedVectorList2_2321_0__Reg1_2
    3154             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3155             :   // Convert__TypedVectorList2_4161_0__Reg1_2
    3156             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3157             :   // Convert__TypedVectorList2_4321_0__Reg1_2
    3158             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3159             :   // Convert__TypedVectorList2_881_0__Reg1_2
    3160             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3161             :   // Convert__TypedVectorList2_8161_0__Reg1_2
    3162             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
    3163             :   // Convert__VecListFour1281_1__Reg1_3
    3164             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    3165             :   // Convert__VecListOne1281_1__Reg1_3
    3166             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    3167             :   // Convert__VecListThree1281_1__Reg1_3
    3168             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    3169             :   // Convert__VecListTwo1281_1__Reg1_3
    3170             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    3171             :   // Convert__VecListFour641_1__Reg1_3
    3172             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    3173             :   // Convert__VecListOne641_1__Reg1_3
    3174             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    3175             :   // Convert__VecListThree641_1__Reg1_3
    3176             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    3177             :   // Convert__VecListTwo641_1__Reg1_3
    3178             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 2, CVT_95_Reg, 4, CVT_Done },
    3179             :   // Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR
    3180             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3181             :   // Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4
    3182             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3183             :   // Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR
    3184             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3185             :   // Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4
    3186             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3187             :   // Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR
    3188             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3189             :   // Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4
    3190             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3191             :   // Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR
    3192             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3193             :   // Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4
    3194             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3195             :   // Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR
    3196             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3197             :   // Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4
    3198             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3199             :   // Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR
    3200             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3201             :   // Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4
    3202             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3203             :   // Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR
    3204             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3205             :   // Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4
    3206             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3207             :   // Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR
    3208             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3209             :   // Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4
    3210             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3211             :   // Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR
    3212             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3213             :   // Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4
    3214             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3215             :   // Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR
    3216             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3217             :   // Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4
    3218             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3219             :   // Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR
    3220             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3221             :   // Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4
    3222             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3223             :   // Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR
    3224             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3225             :   // Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4
    3226             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3227             :   // Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR
    3228             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3229             :   // Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4
    3230             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3231             :   // Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR
    3232             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3233             :   // Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4
    3234             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3235             :   // Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR
    3236             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3237             :   // Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4
    3238             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3239             :   // Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR
    3240             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3241             :   // Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4
    3242             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3243             :   // Convert__TypedVectorList1_081_0__Tie0_1_1__VectorIndexB1_1__Reg1_3
    3244             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3245             :   // Convert__TypedVectorList1_0641_0__Tie0_1_1__VectorIndexD1_1__Reg1_3
    3246             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3247             :   // Convert__TypedVectorList1_0161_0__Tie0_1_1__VectorIndexH1_1__Reg1_3
    3248             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3249             :   // Convert__TypedVectorList1_0321_0__Tie0_1_1__VectorIndexS1_1__Reg1_3
    3250             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3251             :   // Convert__Reg1_2__TypedVectorList3_1681_0__Tie0_3_3__regXZR
    3252             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3253             :   // Convert__Reg1_2__TypedVectorList3_1681_0__Tie0_3_3__Reg1_4
    3254             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3255             :   // Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR
    3256             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3257             :   // Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4
    3258             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3259             :   // Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__regXZR
    3260             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3261             :   // Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__Reg1_4
    3262             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3263             :   // Convert__Reg1_2__TypedVectorList3_2321_0__Tie0_3_3__regXZR
    3264             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3265             :   // Convert__Reg1_2__TypedVectorList3_2321_0__Tie0_3_3__Reg1_4
    3266             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3267             :   // Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__regXZR
    3268             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3269             :   // Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__Reg1_4
    3270             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3271             :   // Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__regXZR
    3272             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3273             :   // Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__Reg1_4
    3274             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3275             :   // Convert__Reg1_2__TypedVectorList3_881_0__Tie0_3_3__regXZR
    3276             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3277             :   // Convert__Reg1_2__TypedVectorList3_881_0__Tie0_3_3__Reg1_4
    3278             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3279             :   // Convert__Reg1_2__TypedVectorList3_8161_0__Tie0_3_3__regXZR
    3280             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3281             :   // Convert__Reg1_2__TypedVectorList3_8161_0__Tie0_3_3__Reg1_4
    3282             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3283             :   // Convert__Reg1_2__TypedVectorList2_1681_0__Tie0_3_3__regXZR
    3284             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3285             :   // Convert__Reg1_2__TypedVectorList2_1681_0__Tie0_3_3__Reg1_4
    3286             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3287             :   // Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR
    3288             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3289             :   // Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4
    3290             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3291             :   // Convert__Reg1_2__TypedVectorList2_2641_0__Tie0_3_3__regXZR
    3292             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3293             :   // Convert__Reg1_2__TypedVectorList2_2641_0__Tie0_3_3__Reg1_4
    3294             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3295             :   // Convert__Reg1_2__TypedVectorList2_2321_0__Tie0_3_3__regXZR
    3296             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3297             :   // Convert__Reg1_2__TypedVectorList2_2321_0__Tie0_3_3__Reg1_4
    3298             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3299             :   // Convert__Reg1_2__TypedVectorList2_4161_0__Tie0_3_3__regXZR
    3300             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3301             :   // Convert__Reg1_2__TypedVectorList2_4161_0__Tie0_3_3__Reg1_4
    3302             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3303             :   // Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__regXZR
    3304             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3305             :   // Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__Reg1_4
    3306             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3307             :   // Convert__Reg1_2__TypedVectorList2_881_0__Tie0_3_3__regXZR
    3308             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3309             :   // Convert__Reg1_2__TypedVectorList2_881_0__Tie0_3_3__Reg1_4
    3310             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3311             :   // Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__regXZR
    3312             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
    3313             :   // Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__Reg1_4
    3314             :   { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
    3315             :   // Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR
    3316             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3317             :   // Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5
    3318             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3319             :   // Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__regXZR
    3320             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3321             :   // Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__Reg1_5
    3322             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3323             :   // Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR
    3324             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3325             :   // Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5
    3326             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3327             :   // Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR
    3328             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3329             :   // Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5
    3330             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3331             :   // Convert__Reg1_3__VecListFour641_1__Tie0_4_4__regXZR
    3332             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3333             :   // Convert__Reg1_3__VecListFour641_1__Tie0_4_4__Reg1_5
    3334             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3335             :   // Convert__Reg1_3__VecListOne641_1__Tie0_4_4__regXZR
    3336             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3337             :   // Convert__Reg1_3__VecListOne641_1__Tie0_4_4__Reg1_5
    3338             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3339             :   // Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR
    3340             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3341             :   // Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5
    3342             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3343             :   // Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__regXZR
    3344             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3345             :   // Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__Reg1_5
    3346             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3347             :   // Convert__VecListOne1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4
    3348             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3349             :   // Convert__VecListOne1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4
    3350             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3351             :   // Convert__VecListOne1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4
    3352             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3353             :   // Convert__VecListOne1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4
    3354             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3355             :   // Convert__Reg1_3__TypedVectorList1_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR
    3356             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3357             :   // Convert__Reg1_3__TypedVectorList1_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5
    3358             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3359             :   // Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR
    3360             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3361             :   // Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5
    3362             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3363             :   // Convert__Reg1_3__TypedVectorList1_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR
    3364             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3365             :   // Convert__Reg1_3__TypedVectorList1_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5
    3366             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3367             :   // Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR
    3368             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3369             :   // Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5
    3370             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3371             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR
    3372             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3373             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6
    3374             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3375             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR
    3376             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3377             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6
    3378             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3379             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR
    3380             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3381             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6
    3382             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3383             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR
    3384             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3385             :   // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6
    3386             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3387             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3388             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3389             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3390             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3391             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0
    3392             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
    3393             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3394             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3395             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0
    3396             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
    3397             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3398             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3399             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3400             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3401             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3402             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3403             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3404             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3405             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0
    3406             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
    3407             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3408             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3409             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0
    3410             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
    3411             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3412             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3413             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3414             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3415             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW328Only1_6
    3416             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3417             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW328Only1_6
    3418             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3419             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6
    3420             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
    3421             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3422             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3423             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL6481_6
    3424             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3425             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW648Only1_6
    3426             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3427             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW648Only1_6
    3428             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3429             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Imm0_311_6
    3430             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
    3431             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3432             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3433             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3434             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3435             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3436             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3437             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3438             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3439             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW328Only1_6
    3440             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3441             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW328Only1_6
    3442             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3443             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6
    3444             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
    3445             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3446             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3447             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL6481_6
    3448             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3449             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW648Only1_6
    3450             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3451             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW648Only1_6
    3452             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3453             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Imm0_311_6
    3454             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
    3455             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
    3456             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3457             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
    3458             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3459             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
    3460             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3461             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
    3462             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3463             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
    3464             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3465             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
    3466             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3467             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
    3468             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3469             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
    3470             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3471             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
    3472             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3473             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64641_6
    3474             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3475             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6
    3476             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3477             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6
    3478             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3479             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6
    3480             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3481             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6
    3482             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3483             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6
    3484             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_8_GT_, 7, CVT_Done },
    3485             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
    3486             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3487             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64641_6
    3488             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3489             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6
    3490             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3491             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6
    3492             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3493             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6
    3494             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3495             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6
    3496             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3497             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6
    3498             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_8_GT_, 7, CVT_Done },
    3499             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3500             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3501             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3502             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3503             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6
    3504             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3505             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW3281_6
    3506             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3507             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6
    3508             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3509             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW3281_6
    3510             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3511             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6
    3512             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3513             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3514             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3515             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64161_6
    3516             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3517             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64161_6
    3518             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3519             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64161_6
    3520             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3521             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s21_6
    3522             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3523             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3524             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3525             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3526             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3527             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6
    3528             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3529             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW3281_6
    3530             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3531             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6
    3532             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3533             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW3281_6
    3534             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3535             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6
    3536             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3537             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3538             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3539             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64161_6
    3540             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3541             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64161_6
    3542             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3543             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64161_6
    3544             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3545             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s21_6
    3546             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3547             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
    3548             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3549             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
    3550             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3551             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
    3552             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3553             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
    3554             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3555             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
    3556             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3557             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
    3558             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3559             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
    3560             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3561             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
    3562             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
    3563             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s81_6
    3564             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_8_GT_, 7, CVT_Done },
    3565             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s81_6
    3566             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_8_GT_, 7, CVT_Done },
    3567             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
    3568             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3569             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
    3570             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3571             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
    3572             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3573             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
    3574             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3575             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
    3576             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3577             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
    3578             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3579             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
    3580             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
    3581             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
    3582             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
    3583             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
    3584             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
    3585             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
    3586             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
    3587             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
    3588             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
    3589             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
    3590             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
    3591             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
    3592             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3593             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
    3594             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
    3595             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
    3596             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3597             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
    3598             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
    3599             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6
    3600             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3601             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6
    3602             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3603             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6
    3604             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3605             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6
    3606             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3607             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
    3608             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3609             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64321_6
    3610             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3611             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64321_6
    3612             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3613             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64321_6
    3614             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3615             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6
    3616             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3617             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
    3618             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3619             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64321_6
    3620             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3621             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64321_6
    3622             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3623             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64321_6
    3624             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3625             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6
    3626             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3627             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32321_6
    3628             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3629             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32321_6
    3630             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3631             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6
    3632             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3633             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32321_6
    3634             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3635             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32321_6
    3636             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3637             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6
    3638             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3639             :   // Convert__TypedVectorList2_081_0__Tie0_1_1__VectorIndexB1_1__Reg1_3
    3640             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3641             :   // Convert__TypedVectorList2_0641_0__Tie0_1_1__VectorIndexD1_1__Reg1_3
    3642             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3643             :   // Convert__TypedVectorList2_0161_0__Tie0_1_1__VectorIndexH1_1__Reg1_3
    3644             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3645             :   // Convert__TypedVectorList2_0321_0__Tie0_1_1__VectorIndexS1_1__Reg1_3
    3646             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3647             :   // Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4
    3648             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3649             :   // Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4
    3650             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3651             :   // Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4
    3652             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3653             :   // Convert__VecListTwo1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4
    3654             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3655             :   // Convert__Reg1_3__TypedVectorList2_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR
    3656             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3657             :   // Convert__Reg1_3__TypedVectorList2_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5
    3658             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3659             :   // Convert__Reg1_3__TypedVectorList2_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR
    3660             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3661             :   // Convert__Reg1_3__TypedVectorList2_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5
    3662             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3663             :   // Convert__Reg1_3__TypedVectorList2_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR
    3664             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3665             :   // Convert__Reg1_3__TypedVectorList2_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5
    3666             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3667             :   // Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR
    3668             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3669             :   // Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5
    3670             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3671             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR
    3672             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3673             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6
    3674             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3675             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR
    3676             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3677             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6
    3678             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3679             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR
    3680             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3681             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6
    3682             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3683             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR
    3684             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3685             :   // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6
    3686             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3687             :   // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3688             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3689             :   // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3690             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3691             :   // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6
    3692             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3693             :   // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3694             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3695             :   // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
    3696             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3697             :   // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6
    3698             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3699             :   // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3700             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3701             :   // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3702             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3703             :   // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6
    3704             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3705             :   // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3706             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3707             :   // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
    3708             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3709             :   // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6
    3710             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
    3711             :   // Convert__TypedVectorList3_081_0__Tie0_1_1__VectorIndexB1_1__Reg1_3
    3712             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3713             :   // Convert__TypedVectorList3_0641_0__Tie0_1_1__VectorIndexD1_1__Reg1_3
    3714             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3715             :   // Convert__TypedVectorList3_0161_0__Tie0_1_1__VectorIndexH1_1__Reg1_3
    3716             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3717             :   // Convert__TypedVectorList3_0321_0__Tie0_1_1__VectorIndexS1_1__Reg1_3
    3718             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3719             :   // Convert__VecListThree1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4
    3720             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3721             :   // Convert__VecListThree1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4
    3722             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3723             :   // Convert__VecListThree1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4
    3724             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3725             :   // Convert__VecListThree1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4
    3726             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3727             :   // Convert__Reg1_3__TypedVectorList3_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR
    3728             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3729             :   // Convert__Reg1_3__TypedVectorList3_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5
    3730             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3731             :   // Convert__Reg1_3__TypedVectorList3_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR
    3732             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3733             :   // Convert__Reg1_3__TypedVectorList3_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5
    3734             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3735             :   // Convert__Reg1_3__TypedVectorList3_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR
    3736             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3737             :   // Convert__Reg1_3__TypedVectorList3_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5
    3738             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3739             :   // Convert__Reg1_3__TypedVectorList3_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR
    3740             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3741             :   // Convert__Reg1_3__TypedVectorList3_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5
    3742             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3743             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR
    3744             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3745             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6
    3746             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3747             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR
    3748             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3749             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6
    3750             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3751             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR
    3752             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3753             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6
    3754             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3755             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR
    3756             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3757             :   // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6
    3758             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3759             :   // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3760             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3761             :   // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3762             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3763             :   // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6
    3764             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_3_GT_, 7, CVT_Done },
    3765             :   // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3766             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3767             :   // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
    3768             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3769             :   // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6
    3770             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_3_GT_, 7, CVT_Done },
    3771             :   // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3772             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3773             :   // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3774             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3775             :   // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6
    3776             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_3_GT_, 7, CVT_Done },
    3777             :   // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3778             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3779             :   // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
    3780             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3781             :   // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6
    3782             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_3_GT_, 7, CVT_Done },
    3783             :   // Convert__TypedVectorList4_081_0__Tie0_1_1__VectorIndexB1_1__Reg1_3
    3784             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3785             :   // Convert__TypedVectorList4_0641_0__Tie0_1_1__VectorIndexD1_1__Reg1_3
    3786             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3787             :   // Convert__TypedVectorList4_0161_0__Tie0_1_1__VectorIndexH1_1__Reg1_3
    3788             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3789             :   // Convert__TypedVectorList4_0321_0__Tie0_1_1__VectorIndexS1_1__Reg1_3
    3790             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    3791             :   // Convert__VecListFour1281_1__Tie0_2_2__VectorIndexB1_2__Reg1_4
    3792             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3793             :   // Convert__VecListFour1281_1__Tie0_2_2__VectorIndexD1_2__Reg1_4
    3794             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3795             :   // Convert__VecListFour1281_1__Tie0_2_2__VectorIndexH1_2__Reg1_4
    3796             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3797             :   // Convert__VecListFour1281_1__Tie0_2_2__VectorIndexS1_2__Reg1_4
    3798             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    3799             :   // Convert__Reg1_3__TypedVectorList4_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__regXZR
    3800             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3801             :   // Convert__Reg1_3__TypedVectorList4_081_0__Tie1_1_1__VectorIndexB1_1__Tie0_4_4__Reg1_5
    3802             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3803             :   // Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__regXZR
    3804             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3805             :   // Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__VectorIndexD1_1__Tie0_4_4__Reg1_5
    3806             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3807             :   // Convert__Reg1_3__TypedVectorList4_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__regXZR
    3808             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3809             :   // Convert__Reg1_3__TypedVectorList4_0161_0__Tie1_1_1__VectorIndexH1_1__Tie0_4_4__Reg1_5
    3810             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3811             :   // Convert__Reg1_3__TypedVectorList4_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__regXZR
    3812             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    3813             :   // Convert__Reg1_3__TypedVectorList4_0321_0__Tie1_1_1__VectorIndexS1_1__Tie0_4_4__Reg1_5
    3814             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    3815             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__regXZR
    3816             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3817             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexB1_2__Tie0_5_5__Reg1_6
    3818             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3819             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__regXZR
    3820             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3821             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexD1_2__Tie0_5_5__Reg1_6
    3822             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3823             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__regXZR
    3824             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3825             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexH1_2__Tie0_5_5__Reg1_6
    3826             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3827             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__regXZR
    3828             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    3829             :   // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__VectorIndexS1_2__Tie0_5_5__Reg1_6
    3830             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    3831             :   // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3832             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3833             :   // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
    3834             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3835             :   // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6
    3836             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3837             :   // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3838             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3839             :   // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
    3840             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3841             :   // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6
    3842             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3843             :   // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3844             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3845             :   // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
    3846             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3847             :   // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6
    3848             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3849             :   // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
    3850             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
    3851             :   // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
    3852             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3853             :   // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6
    3854             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
    3855             :   // Convert__Reg1_1__Reg1_0__Reg1_3
    3856             :   { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_Done },
    3857             :   // Convert__Reg1_0__GPR64sp01_2
    3858             :   { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_Done },
    3859             :   // Convert__Reg1_0__Reg1_1__GPR64sp01_3
    3860             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands, 4, CVT_Done },
    3861             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
    3862             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
    3863             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
    3864             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
    3865             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
    3866             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
    3867             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
    3868             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
    3869             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
    3870             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
    3871             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
    3872             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
    3873             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
    3874             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
    3875             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
    3876             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
    3877             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
    3878             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3879             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
    3880             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3881             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
    3882             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3883             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
    3884             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3885             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
    3886             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3887             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
    3888             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3889             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
    3890             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3891             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
    3892             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3893             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted641_6
    3894             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3895             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted641_6
    3896             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3897             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
    3898             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3899             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
    3900             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3901             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
    3902             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3903             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
    3904             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3905             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
    3906             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3907             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
    3908             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3909             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6
    3910             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3911             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6
    3912             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3913             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6
    3914             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3915             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6
    3916             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
    3917             :   // Convert__Reg1_0__Reg1_1__Reg1_3__imm_95_0
    3918             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    3919             :   // Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__imm_95_0
    3920             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    3921             :   // Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Reg1_3__imm_95_0
    3922             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    3923             :   // Convert__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Reg1_3__imm_95_0
    3924             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    3925             :   // Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4
    3926             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    3927             :   // Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s81_4
    3928             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
    3929             :   // Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4
    3930             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    3931             :   // Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Reg1_3__SImm7s81_4
    3932             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
    3933             :   // Convert__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Reg1_3__SImm7s161_4
    3934             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_16_GT_, 5, CVT_Done },
    3935             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5
    3936             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_4_GT_, 6, CVT_Done },
    3937             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_5
    3938             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_8_GT_, 6, CVT_Done },
    3939             :   // Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_5
    3940             :   { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_4_GT_, 6, CVT_Done },
    3941             :   // Convert__Reg1_3__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Tie0_4_4__SImm7s81_5
    3942             :   { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_8_GT_, 6, CVT_Done },
    3943             :   // Convert__Reg1_3__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Tie0_4_4__SImm7s161_5
    3944             :   { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_16_GT_, 6, CVT_Done },
    3945             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4
    3946             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    3947             :   // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_4
    3948             :   { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
    3949             :   // Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_4
    3950             :   { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    3951             :   // Convert__Reg1_3__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Tie0_4_4__SImm7s81_4
    3952             :   { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
    3953             :   // Convert__Reg1_3__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Tie0_4_4__SImm7s161_4
    3954             :   { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_16_GT_, 5, CVT_Done },
    3955             :   // Convert__FPRAsmOperandFPR321_0__PCRelLabel191_1
    3956             :   { CVT_95_addRegOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
    3957             :   // Convert__FPRAsmOperandFPR641_0__PCRelLabel191_1
    3958             :   { CVT_95_addRegOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
    3959             :   // Convert__FPRAsmOperandFPR1281_0__PCRelLabel191_1
    3960             :   { CVT_95_addRegOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
    3961             :   // Convert__Reg1_0__Reg1_2__imm_95_0
    3962             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3963             :   // Convert__SVEPredicateAnyReg1_0__Reg1_2__imm_95_0
    3964             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3965             :   // Convert__SVEVectorAnyReg1_0__Reg1_2__imm_95_0
    3966             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3967             :   // Convert__FPRAsmOperandFPR81_0__Reg1_2__imm_95_0
    3968             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3969             :   // Convert__FPRAsmOperandFPR161_0__Reg1_2__imm_95_0
    3970             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3971             :   // Convert__FPRAsmOperandFPR321_0__Reg1_2__imm_95_0
    3972             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3973             :   // Convert__FPRAsmOperandFPR641_0__Reg1_2__imm_95_0
    3974             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3975             :   // Convert__FPRAsmOperandFPR1281_0__Reg1_2__imm_95_0
    3976             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    3977             :   // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_4
    3978             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
    3979             :   // Convert__Reg1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    3980             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    3981             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB321_3
    3982             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3983             :   // Convert__Reg1_0__Reg1_2__UImm12Offset41_3
    3984             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_4_GT_, 4, CVT_Done },
    3985             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB641_3
    3986             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3987             :   // Convert__Reg1_0__Reg1_2__UImm12Offset81_3
    3988             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_8_GT_, 4, CVT_Done },
    3989             :   // Convert__Reg1_2__FPRAsmOperandFPR81_0__Tie0_3_3__SImm91_4
    3990             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
    3991             :   // Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    3992             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    3993             :   // Convert__FPRAsmOperandFPR81_0__Reg1_2__SImm9OffsetFB81_3
    3994             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    3995             :   // Convert__FPRAsmOperandFPR81_0__Reg1_2__UImm12Offset11_3
    3996             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_1_GT_, 4, CVT_Done },
    3997             :   // Convert__Reg1_2__FPRAsmOperandFPR161_0__Tie0_3_3__SImm91_4
    3998             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
    3999             :   // Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    4000             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    4001             :   // Convert__FPRAsmOperandFPR161_0__Reg1_2__SImm9OffsetFB161_3
    4002             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4003             :   // Convert__FPRAsmOperandFPR161_0__Reg1_2__UImm12Offset21_3
    4004             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_2_GT_, 4, CVT_Done },
    4005             :   // Convert__Reg1_2__FPRAsmOperandFPR321_0__Tie0_3_3__SImm91_4
    4006             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
    4007             :   // Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    4008             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    4009             :   // Convert__FPRAsmOperandFPR321_0__Reg1_2__SImm9OffsetFB321_3
    4010             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4011             :   // Convert__FPRAsmOperandFPR321_0__Reg1_2__UImm12Offset41_3
    4012             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_4_GT_, 4, CVT_Done },
    4013             :   // Convert__Reg1_2__FPRAsmOperandFPR641_0__Tie0_3_3__SImm91_4
    4014             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
    4015             :   // Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    4016             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    4017             :   // Convert__FPRAsmOperandFPR641_0__Reg1_2__SImm9OffsetFB641_3
    4018             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4019             :   // Convert__FPRAsmOperandFPR641_0__Reg1_2__UImm12Offset81_3
    4020             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_8_GT_, 4, CVT_Done },
    4021             :   // Convert__Reg1_2__FPRAsmOperandFPR1281_0__Tie0_3_3__SImm91_4
    4022             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
    4023             :   // Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    4024             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    4025             :   // Convert__FPRAsmOperandFPR1281_0__Reg1_2__SImm9OffsetFB1281_3
    4026             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4027             :   // Convert__FPRAsmOperandFPR1281_0__Reg1_2__UImm12Offset161_3
    4028             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_16_GT_, 4, CVT_Done },
    4029             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend322_4
    4030             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4031             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend322_4
    4032             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4033             :   // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_3
    4034             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
    4035             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend642_4
    4036             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4037             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend642_4
    4038             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4039             :   // Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__MemWExtend82_4
    4040             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
    4041             :   // Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__MemXExtend82_4
    4042             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
    4043             :   // Convert__Reg1_2__FPRAsmOperandFPR81_0__Tie0_3_3__SImm91_3
    4044             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
    4045             :   // Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__MemWExtend162_4
    4046             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4047             :   // Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__MemXExtend162_4
    4048             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4049             :   // Convert__Reg1_2__FPRAsmOperandFPR161_0__Tie0_3_3__SImm91_3
    4050             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
    4051             :   // Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__MemWExtend322_4
    4052             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4053             :   // Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__MemXExtend322_4
    4054             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4055             :   // Convert__Reg1_2__FPRAsmOperandFPR321_0__Tie0_3_3__SImm91_3
    4056             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
    4057             :   // Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__MemWExtend642_4
    4058             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4059             :   // Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__MemXExtend642_4
    4060             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4061             :   // Convert__Reg1_2__FPRAsmOperandFPR641_0__Tie0_3_3__SImm91_3
    4062             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
    4063             :   // Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__MemWExtend1282_4
    4064             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4065             :   // Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__MemXExtend1282_4
    4066             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4067             :   // Convert__Reg1_2__FPRAsmOperandFPR1281_0__Tie0_3_3__SImm91_3
    4068             :   { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
    4069             :   // Convert__SVEPredicateAnyReg1_0__Reg1_2__SImm91_3
    4070             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4071             :   // Convert__SVEVectorAnyReg1_0__Reg1_2__SImm91_3
    4072             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4073             :   // Convert__Reg1_0__Reg1_2__SImm10s81_3
    4074             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmScaledOperands_LT_8_GT_, 4, CVT_Done },
    4075             :   // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm10s81_3
    4076             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmScaledOperands_LT_8_GT_, 4, CVT_Done },
    4077             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB81_3
    4078             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4079             :   // Convert__Reg1_0__Reg1_2__UImm12Offset11_3
    4080             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_1_GT_, 4, CVT_Done },
    4081             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend82_4
    4082             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
    4083             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend82_4
    4084             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
    4085             :   // Convert__Reg1_0__Reg1_2__SImm9OffsetFB161_3
    4086             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4087             :   // Convert__Reg1_0__Reg1_2__UImm12Offset21_3
    4088             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_2_GT_, 4, CVT_Done },
    4089             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend162_4
    4090             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4091             :   // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend162_4
    4092             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4093             :   // Convert__Reg1_0__Reg1_2__SImm91_3
    4094             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4095             :   // Convert__FPRAsmOperandFPR81_0__Reg1_2__SImm91_3
    4096             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4097             :   // Convert__FPRAsmOperandFPR161_0__Reg1_2__SImm91_3
    4098             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4099             :   // Convert__FPRAsmOperandFPR321_0__Reg1_2__SImm91_3
    4100             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4101             :   // Convert__FPRAsmOperandFPR641_0__Reg1_2__SImm91_3
    4102             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4103             :   // Convert__FPRAsmOperandFPR1281_0__Reg1_2__SImm91_3
    4104             :   { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4105             :   // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__Imm0_151_2
    4106             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4107             :   // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__Imm0_311_2
    4108             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4109             :   // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__Imm0_631_2
    4110             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4111             :   // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__Imm0_71_2
    4112             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4113             :   // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__Imm1_161_2
    4114             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4115             :   // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__Imm1_321_2
    4116             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4117             :   // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__Imm1_641_2
    4118             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4119             :   // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__Imm1_81_2
    4120             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4121             :   // Convert__Reg1_0__Reg1_1__Reg1_2__regWZR
    4122             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_regWZR, 0, CVT_Done },
    4123             :   // Convert__Reg1_0__Reg1_1__Reg1_2__regXZR
    4124             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_regXZR, 0, CVT_Done },
    4125             :   // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0
    4126             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    4127             :   // Convert__Reg1_0__regWZR__Reg1_1__imm_95_0
    4128             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
    4129             :   // Convert__Reg1_0__MOVZ32_lsl0MovAlias1_1__imm_95_0
    4130             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
    4131             :   // Convert__Reg1_0__MOVZ32_lsl16MovAlias1_1__imm_95_16
    4132             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
    4133             :   // Convert__Reg1_0__MOVN32_lsl0MovAlias1_1__imm_95_0
    4134             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
    4135             :   // Convert__Reg1_0__MOVN32_lsl16MovAlias1_1__imm_95_16
    4136             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
    4137             :   // Convert__Reg1_0__regWZR__LogicalImm321_1
    4138             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 2, CVT_Done },
    4139             :   // Convert__Reg1_0__regXZR__Reg1_1__imm_95_0
    4140             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
    4141             :   // Convert__Reg1_0__MOVZ64_lsl0MovAlias1_1__imm_95_0
    4142             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
    4143             :   // Convert__Reg1_0__MOVZ64_lsl16MovAlias1_1__imm_95_16
    4144             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
    4145             :   // Convert__Reg1_0__MOVZ64_lsl32MovAlias1_1__imm_95_32
    4146             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_32_GT_, 2, CVT_imm_95_32, 0, CVT_Done },
    4147             :   // Convert__Reg1_0__MOVZ64_lsl48MovAlias1_1__imm_95_48
    4148             :   { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_48_GT_, 2, CVT_imm_95_48, 0, CVT_Done },
    4149             :   // Convert__Reg1_0__MOVN64_lsl0MovAlias1_1__imm_95_0
    4150             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
    4151             :   // Convert__Reg1_0__MOVN64_lsl16MovAlias1_1__imm_95_16
    4152             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
    4153             :   // Convert__Reg1_0__MOVN64_lsl32MovAlias1_1__imm_95_32
    4154             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_32_GT_, 2, CVT_imm_95_32, 0, CVT_Done },
    4155             :   // Convert__Reg1_0__MOVN64_lsl48MovAlias1_1__imm_95_48
    4156             :   { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_48_GT_, 2, CVT_imm_95_48, 0, CVT_Done },
    4157             :   // Convert__Reg1_0__regXZR__LogicalImm641_1
    4158             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 2, CVT_Done },
    4159             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_2
    4160             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    4161             :   // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_2
    4162             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    4163             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndexD1_3
    4164             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    4165             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndexS1_3
    4166             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    4167             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_2
    4168             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    4169             :   // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_2
    4170             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    4171             :   // Convert__Reg1_0__SIMDImmType101_1
    4172             :   { CVT_95_Reg, 1, CVT_95_addSIMDImmType10Operands, 2, CVT_Done },
    4173             :   // Convert__VectorReg1281_1__Imm0_2551_2
    4174             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4175             :   // Convert__VectorReg1281_1__SIMDImmType101_2
    4176             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addSIMDImmType10Operands, 3, CVT_Done },
    4177             :   // Convert__VectorReg641_1__Imm0_2551_2__imm_95_0
    4178             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    4179             :   // Convert__VectorReg1281_1__Imm0_2551_2__imm_95_0
    4180             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    4181             :   // Convert__VectorReg641_1__Imm0_2551_2
    4182             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4183             :   // Convert__VectorReg1281_0__Imm0_2551_2
    4184             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_Done },
    4185             :   // Convert__VectorReg1281_0__SIMDImmType101_2
    4186             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addSIMDImmType10Operands, 3, CVT_Done },
    4187             :   // Convert__VectorReg1281_0__Imm0_2551_2__imm_95_0
    4188             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    4189             :   // Convert__VectorReg641_0__Imm0_2551_2__imm_95_0
    4190             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    4191             :   // Convert__VectorReg641_0__Imm0_2551_2
    4192             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_Done },
    4193             :   // Convert__VectorReg641_1__Imm0_2551_2__LogicalVecShifter1_3
    4194             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4195             :   // Convert__VectorReg641_1__Imm0_2551_2__MoveVecShifter1_3
    4196             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4197             :   // Convert__VectorReg641_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    4198             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4199             :   // Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecShifter1_3
    4200             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4201             :   // Convert__VectorReg1281_1__Imm0_2551_2__MoveVecShifter1_3
    4202             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4203             :   // Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    4204             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4205             :   // Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecShifter1_3
    4206             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4207             :   // Convert__VectorReg1281_0__Imm0_2551_2__MoveVecShifter1_3
    4208             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4209             :   // Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    4210             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4211             :   // Convert__VectorReg641_0__Imm0_2551_2__LogicalVecShifter1_3
    4212             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4213             :   // Convert__VectorReg641_0__Imm0_2551_2__MoveVecShifter1_3
    4214             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4215             :   // Convert__VectorReg641_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3
    4216             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
    4217             :   // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0
    4218             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    4219             :   // Convert__Reg1_0__Tie0_1_1__MovKSymbolG01_1__imm_95_0
    4220             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    4221             :   // Convert__Reg1_0__Tie0_1_1__MovKSymbolG11_1__imm_95_16
    4222             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_16, 0, CVT_Done },
    4223             :   // Convert__Reg1_0__Tie0_1_1__MovKSymbolG21_1__imm_95_32
    4224             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_32, 0, CVT_Done },
    4225             :   // Convert__Reg1_0__Tie0_1_1__MovKSymbolG31_1__imm_95_48
    4226             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_48, 0, CVT_Done },
    4227             :   // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm32Shifter1_2
    4228             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    4229             :   // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm64Shifter1_2
    4230             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    4231             :   // Convert__Reg1_0__Imm0_655351_1__imm_95_0
    4232             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    4233             :   // Convert__Reg1_0__MovZSymbolG01_1__imm_95_0
    4234             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    4235             :   // Convert__Reg1_0__MovZSymbolG11_1__imm_95_16
    4236             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_16, 0, CVT_Done },
    4237             :   // Convert__Reg1_0__MovZSymbolG21_1__imm_95_32
    4238             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_32, 0, CVT_Done },
    4239             :   // Convert__Reg1_0__MovZSymbolG31_1__imm_95_48
    4240             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_48, 0, CVT_Done },
    4241             :   // Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2
    4242             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    4243             :   // Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2
    4244             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    4245             :   // Convert__Reg1_0__MRSSystemRegister1_1
    4246             :   { CVT_95_Reg, 1, CVT_95_addMRSSystemRegisterOperands, 2, CVT_Done },
    4247             :   // Convert__MSRSystemRegister1_0__Reg1_1
    4248             :   { CVT_95_addMSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
    4249             :   // Convert__SystemPStateFieldWithImm0_151_0__Imm0_151_1
    4250             :   { CVT_95_addSystemPStateFieldWithImm0_95_15Operands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    4251             :   // Convert__SystemPStateFieldWithImm0_11_0__Imm0_11_1
    4252             :   { CVT_95_addSystemPStateFieldWithImm0_95_1Operands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    4253             :   // Convert__Reg1_0__regWZR__Reg1_1__LogicalShifter321_2
    4254             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    4255             :   // Convert__Reg1_0__regXZR__Reg1_1__LogicalShifter641_2
    4256             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    4257             :   // Convert__Reg1_0__regWZR__Reg1_1__ArithmeticShifter321_2
    4258             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    4259             :   // Convert__Reg1_0__regXZR__Reg1_1__ArithmeticShifter641_2
    4260             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    4261             :   // Convert__Reg1_0__regWZR__Reg1_1
    4262             :   { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_Done },
    4263             :   // Convert__Reg1_0__regXZR__Reg1_1
    4264             :   { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_Done },
    4265             :   // Convert__VectorReg1281_1__VectorReg641_2__VectorReg641_3
    4266             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    4267             :   // Convert__VectorReg1281_0__VectorReg641_2__VectorReg641_4
    4268             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    4269             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4270             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4271             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0
    4272             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
    4273             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0
    4274             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
    4275             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4276             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4277             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4
    4278             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4279             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4
    4280             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4281             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4
    4282             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4283             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4
    4284             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4285             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4
    4286             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4287             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4
    4288             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    4289             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4
    4290             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    4291             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm6s11_4
    4292             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4293             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
    4294             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4295             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32641_4
    4296             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4297             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32641_4
    4298             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4299             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4
    4300             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4301             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4
    4302             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4303             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4
    4304             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4305             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s81_4
    4306             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
    4307             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4
    4308             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
    4309             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4310             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4311             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4
    4312             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4313             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4
    4314             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4315             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4
    4316             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4317             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4
    4318             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4319             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4
    4320             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4321             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4
    4322             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4323             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4
    4324             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4325             :   // Convert__Prefetch1_0__PCRelLabel191_1
    4326             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
    4327             :   // Convert__Prefetch1_0__Reg1_2__imm_95_0
    4328             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
    4329             :   // Convert__Prefetch1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
    4330             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    4331             :   // Convert__Prefetch1_0__Reg1_2__UImm12Offset81_3
    4332             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_8_GT_, 4, CVT_Done },
    4333             :   // Convert__Prefetch1_0__Reg1_2__Reg1_3__MemWExtend642_4
    4334             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4335             :   // Convert__Prefetch1_0__Reg1_2__Reg1_3__MemXExtend642_4
    4336             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
    4337             :   // Convert__Prefetch1_0__Reg1_2__SImm91_3
    4338             :   { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4339             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
    4340             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4341             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4
    4342             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4343             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4
    4344             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4345             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4
    4346             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4347             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4
    4348             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4349             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4
    4350             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4351             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4
    4352             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    4353             :   // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4
    4354             :   { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    4355             :   // Convert__PSBHint1_0
    4356             :   { CVT_95_addPSBHintOperands, 1, CVT_Done },
    4357             :   // Convert__SVEPredicateHReg1_0__imm_95_31
    4358             :   { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    4359             :   // Convert__SVEPredicateSReg1_0__imm_95_31
    4360             :   { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    4361             :   // Convert__SVEPredicateDReg1_0__imm_95_31
    4362             :   { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    4363             :   // Convert__SVEPredicateBReg1_0__imm_95_31
    4364             :   { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    4365             :   // Convert__SVEPredicateHReg1_0__SVEPattern1_1
    4366             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    4367             :   // Convert__SVEPredicateSReg1_0__SVEPattern1_1
    4368             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    4369             :   // Convert__SVEPredicateDReg1_0__SVEPattern1_1
    4370             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    4371             :   // Convert__SVEPredicateBReg1_0__SVEPattern1_1
    4372             :   { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    4373             :   // Convert__Reg1_0__SImm61_1
    4374             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
    4375             :   // Convert__regLR
    4376             :   { CVT_regLR, 0, CVT_Done },
    4377             :   // Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_311_2
    4378             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4379             :   // Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_631_2
    4380             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4381             :   // Convert__VectorReg641_1__VectorReg1281_2__Imm1_321_3
    4382             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4383             :   // Convert__VectorReg641_1__VectorReg1281_2__Imm1_161_3
    4384             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4385             :   // Convert__VectorReg641_1__VectorReg1281_2__Imm1_81_3
    4386             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4387             :   // Convert__VectorReg641_0__VectorReg1281_2__Imm1_321_4
    4388             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4389             :   // Convert__VectorReg641_0__VectorReg1281_2__Imm1_161_4
    4390             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4391             :   // Convert__VectorReg641_0__VectorReg1281_2__Imm1_81_4
    4392             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4393             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_81_3
    4394             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4395             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3
    4396             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4397             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_161_3
    4398             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4399             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4
    4400             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4401             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4
    4402             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4403             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4
    4404             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4405             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg641_3
    4406             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    4407             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg641_4
    4408             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    4409             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2
    4410             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    4411             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2
    4412             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    4413             :   // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg641_3
    4414             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    4415             :   // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg641_4
    4416             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
    4417             :   // Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3
    4418             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4419             :   // Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3
    4420             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4421             :   // Convert__imm_95_0__Tie0_1_1__imm_95_0__imm_95_0
    4422             :   { CVT_imm_95_0, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    4423             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_1__VectorReg1281_2__VectorIndexS1_3
    4424             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    4425             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_1__VectorReg1281_2__VectorIndexS1_3
    4426             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    4427             :   // Convert__imm_95_4
    4428             :   { CVT_imm_95_4, 0, CVT_Done },
    4429             :   // Convert__imm_95_5
    4430             :   { CVT_imm_95_5, 0, CVT_Done },
    4431             :   // Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3
    4432             :   { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    4433             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2
    4434             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    4435             :   // Convert__Reg1_0__Reg1_1__Imm0_631_2
    4436             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4437             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_71_3
    4438             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4439             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_631_3
    4440             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4441             :   // Convert__VectorReg641_1__VectorReg641_2__Imm0_311_3
    4442             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4443             :   // Convert__VectorReg641_1__VectorReg641_2__Imm0_151_3
    4444             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4445             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_311_3
    4446             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4447             :   // Convert__VectorReg641_1__VectorReg641_2__Imm0_71_3
    4448             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4449             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_151_3
    4450             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4451             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_71_4
    4452             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4453             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_631_4
    4454             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4455             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_311_4
    4456             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4457             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_151_4
    4458             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4459             :   // Convert__VectorReg641_0__VectorReg641_2__Imm0_311_4
    4460             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4461             :   // Convert__VectorReg641_0__VectorReg641_2__Imm0_151_4
    4462             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4463             :   // Convert__VectorReg641_0__VectorReg641_2__Imm0_71_4
    4464             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4465             :   // Convert__VectorReg1281_1__VectorReg641_2
    4466             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
    4467             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2
    4468             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4469             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_71_3
    4470             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4471             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_631_3
    4472             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4473             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_311_3
    4474             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4475             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_151_3
    4476             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4477             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_311_3
    4478             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4479             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_71_3
    4480             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4481             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_151_3
    4482             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4483             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_71_4
    4484             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4485             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_631_4
    4486             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4487             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_311_4
    4488             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4489             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_151_4
    4490             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4491             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_311_4
    4492             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4493             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_151_4
    4494             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4495             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_71_4
    4496             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4497             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4
    4498             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4499             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4
    4500             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4501             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6
    4502             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    4503             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6
    4504             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    4505             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndexB1_3
    4506             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    4507             :   // Convert__Reg1_1__VectorReg1281_2__VectorIndexH1_3
    4508             :   { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
    4509             :   // Convert__VectorReg1281_1__VectorReg641_2__VectorReg1281_3__VectorIndexS1_4
    4510             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4511             :   // Convert__VectorReg1281_1__VectorReg641_2__VectorRegLo1_3__VectorIndexH1_4
    4512             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4513             :   // Convert__VectorReg1281_0__VectorReg641_2__VectorReg1281_4__VectorIndexS1_6
    4514             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    4515             :   // Convert__VectorReg1281_0__VectorReg641_2__VectorRegLo1_4__VectorIndexH1_6
    4516             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
    4517             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
    4518             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    4519             :   // Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR161_2__VectorRegLo1_3__VectorIndexH1_4
    4520             :   { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4521             :   // Convert__FPRAsmOperandFPR641_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__VectorIndexS1_4
    4522             :   { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4523             :   // Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR161_1__VectorRegLo1_2__VectorIndexH1_4
    4524             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4525             :   // Convert__FPRAsmOperandFPR641_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__VectorIndexS1_4
    4526             :   { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4527             :   // Convert__FPRAsmOperandFPR321_1__FPRAsmOperandFPR161_2__VectorRegLo1_3__VectorIndexH1_4
    4528             :   { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4529             :   // Convert__FPRAsmOperandFPR641_1__FPRAsmOperandFPR321_2__VectorReg1281_3__VectorIndexS1_4
    4530             :   { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4531             :   // Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR161_1__VectorRegLo1_2__VectorIndexH1_4
    4532             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4533             :   // Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR321_1__VectorReg1281_2__VectorIndexS1_4
    4534             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
    4535             :   // Convert__Reg1_0__Reg1_1__Imm1_81_2
    4536             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4537             :   // Convert__Reg1_0__Reg1_1__Imm0_151_2
    4538             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4539             :   // Convert__Reg1_0__Reg1_1__Imm0_311_2
    4540             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4541             :   // Convert__Reg1_0__Reg1_1__Imm0_71_2
    4542             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4543             :   // Convert__VectorReg641_1__VectorReg1281_2
    4544             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
    4545             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm1_641_2
    4546             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
    4547             :   // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_641_3
    4548             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4549             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_321_3
    4550             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4551             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_161_3
    4552             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4553             :   // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_81_3
    4554             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4555             :   // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_641_4
    4556             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4557             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_321_4
    4558             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4559             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_161_4
    4560             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4561             :   // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_81_4
    4562             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4563             :   // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_81_3
    4564             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4565             :   // Convert__VectorReg641_1__VectorReg641_2__Imm1_81_3
    4566             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4567             :   // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_81_4
    4568             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4569             :   // Convert__VectorReg641_0__VectorReg641_2__Imm1_81_4
    4570             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4571             :   // Convert__VectorReg1281_1__VectorReg641_2__Imm0_311_3
    4572             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4573             :   // Convert__VectorReg1281_1__VectorReg641_2__Imm0_151_3
    4574             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4575             :   // Convert__VectorReg1281_1__VectorReg641_2__Imm0_71_3
    4576             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    4577             :   // Convert__VectorReg1281_0__VectorReg641_2__Imm0_311_4
    4578             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4579             :   // Convert__VectorReg1281_0__VectorReg641_2__Imm0_151_4
    4580             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4581             :   // Convert__VectorReg1281_0__VectorReg641_2__Imm0_71_4
    4582             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
    4583             :   // Convert__TypedVectorList1_081_0__VectorIndexB1_1__Reg1_3
    4584             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4585             :   // Convert__TypedVectorList1_0641_0__VectorIndexD1_1__Reg1_3
    4586             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4587             :   // Convert__TypedVectorList1_0161_0__VectorIndexH1_1__Reg1_3
    4588             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4589             :   // Convert__TypedVectorList1_0321_0__VectorIndexS1_1__Reg1_3
    4590             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4591             :   // Convert__VecListOne1281_1__VectorIndexB1_2__Reg1_4
    4592             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4593             :   // Convert__VecListOne1281_1__VectorIndexD1_2__Reg1_4
    4594             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4595             :   // Convert__VecListOne1281_1__VectorIndexH1_2__Reg1_4
    4596             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4597             :   // Convert__VecListOne1281_1__VectorIndexS1_2__Reg1_4
    4598             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4599             :   // Convert__Reg1_3__TypedVectorList1_081_0__VectorIndexB1_1__Tie0_4_4__regXZR
    4600             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4601             :   // Convert__Reg1_3__TypedVectorList1_081_0__VectorIndexB1_1__Tie0_4_4__Reg1_5
    4602             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4603             :   // Convert__Reg1_3__TypedVectorList1_0641_0__VectorIndexD1_1__Tie0_4_4__regXZR
    4604             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4605             :   // Convert__Reg1_3__TypedVectorList1_0641_0__VectorIndexD1_1__Tie0_4_4__Reg1_5
    4606             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4607             :   // Convert__Reg1_3__TypedVectorList1_0161_0__VectorIndexH1_1__Tie0_4_4__regXZR
    4608             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4609             :   // Convert__Reg1_3__TypedVectorList1_0161_0__VectorIndexH1_1__Tie0_4_4__Reg1_5
    4610             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4611             :   // Convert__Reg1_3__TypedVectorList1_0321_0__VectorIndexS1_1__Tie0_4_4__regXZR
    4612             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4613             :   // Convert__Reg1_3__TypedVectorList1_0321_0__VectorIndexS1_1__Tie0_4_4__Reg1_5
    4614             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4615             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexB1_2__Tie0_5_5__regXZR
    4616             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4617             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6
    4618             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4619             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexD1_2__Tie0_5_5__regXZR
    4620             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4621             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6
    4622             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4623             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexH1_2__Tie0_5_5__regXZR
    4624             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4625             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6
    4626             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4627             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexS1_2__Tie0_5_5__regXZR
    4628             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4629             :   // Convert__Reg1_4__VecListOne1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6
    4630             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4631             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4632             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4633             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4634             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4635             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0
    4636             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
    4637             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4638             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4639             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0
    4640             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
    4641             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4642             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4643             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4644             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4645             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4646             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4647             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4648             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4649             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0
    4650             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
    4651             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4652             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4653             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0
    4654             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
    4655             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4656             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4657             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4658             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4659             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4
    4660             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4661             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4
    4662             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4663             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4
    4664             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    4665             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4666             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4667             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4
    4668             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4669             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4
    4670             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4671             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4
    4672             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4673             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4
    4674             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    4675             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4676             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4677             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4678             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4679             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4680             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4681             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4682             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4683             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4
    4684             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4685             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4
    4686             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4687             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4
    4688             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    4689             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4690             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4691             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4
    4692             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4693             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4
    4694             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4695             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4
    4696             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4697             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4
    4698             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    4699             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
    4700             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4701             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
    4702             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4703             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
    4704             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4705             :   // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
    4706             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4707             :   // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
    4708             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4709             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
    4710             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4711             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
    4712             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4713             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
    4714             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
    4715             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
    4716             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4717             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4
    4718             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4719             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4
    4720             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4721             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW6481_4
    4722             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4723             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4
    4724             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4725             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW6481_4
    4726             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4727             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4
    4728             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
    4729             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
    4730             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4731             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4
    4732             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4733             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4
    4734             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4735             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW6481_4
    4736             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4737             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4
    4738             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4739             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW6481_4
    4740             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4741             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4
    4742             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
    4743             :   // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4744             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4745             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4746             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4747             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4
    4748             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4749             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW3281_4
    4750             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4751             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4
    4752             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4753             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW3281_4
    4754             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4755             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4
    4756             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4757             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4758             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4759             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4
    4760             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4761             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4
    4762             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4763             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4
    4764             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4765             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4
    4766             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4767             :   // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4768             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4769             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4770             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4771             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4
    4772             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4773             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW3281_4
    4774             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4775             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4
    4776             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4777             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW3281_4
    4778             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4779             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4
    4780             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4781             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4782             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4783             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4
    4784             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4785             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4
    4786             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4787             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4
    4788             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4789             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4
    4790             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4791             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
    4792             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4793             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4
    4794             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4795             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4
    4796             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4797             :   // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4
    4798             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    4799             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
    4800             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4801             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4
    4802             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4803             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4
    4804             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4805             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4
    4806             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4807             :   // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4
    4808             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    4809             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
    4810             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4811             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4
    4812             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4813             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4
    4814             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4815             :   // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4
    4816             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    4817             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
    4818             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4819             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4
    4820             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4821             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4
    4822             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4823             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4
    4824             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4825             :   // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4
    4826             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    4827             :   // Convert__TypedVectorList2_081_0__VectorIndexB1_1__Reg1_3
    4828             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4829             :   // Convert__TypedVectorList2_0641_0__VectorIndexD1_1__Reg1_3
    4830             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4831             :   // Convert__TypedVectorList2_0161_0__VectorIndexH1_1__Reg1_3
    4832             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4833             :   // Convert__TypedVectorList2_0321_0__VectorIndexS1_1__Reg1_3
    4834             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4835             :   // Convert__VecListTwo1281_1__VectorIndexB1_2__Reg1_4
    4836             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4837             :   // Convert__VecListTwo1281_1__VectorIndexD1_2__Reg1_4
    4838             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4839             :   // Convert__VecListTwo1281_1__VectorIndexH1_2__Reg1_4
    4840             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4841             :   // Convert__VecListTwo1281_1__VectorIndexS1_2__Reg1_4
    4842             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4843             :   // Convert__Reg1_3__TypedVectorList2_081_0__VectorIndexB1_1__Tie0_4_4__regXZR
    4844             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4845             :   // Convert__Reg1_3__TypedVectorList2_081_0__VectorIndexB1_1__Tie0_4_4__Reg1_5
    4846             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4847             :   // Convert__Reg1_3__TypedVectorList2_0641_0__VectorIndexD1_1__Tie0_4_4__regXZR
    4848             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4849             :   // Convert__Reg1_3__TypedVectorList2_0641_0__VectorIndexD1_1__Tie0_4_4__Reg1_5
    4850             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4851             :   // Convert__Reg1_3__TypedVectorList2_0161_0__VectorIndexH1_1__Tie0_4_4__regXZR
    4852             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4853             :   // Convert__Reg1_3__TypedVectorList2_0161_0__VectorIndexH1_1__Tie0_4_4__Reg1_5
    4854             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4855             :   // Convert__Reg1_3__TypedVectorList2_0321_0__VectorIndexS1_1__Tie0_4_4__regXZR
    4856             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4857             :   // Convert__Reg1_3__TypedVectorList2_0321_0__VectorIndexS1_1__Tie0_4_4__Reg1_5
    4858             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4859             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexB1_2__Tie0_5_5__regXZR
    4860             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4861             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6
    4862             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4863             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexD1_2__Tie0_5_5__regXZR
    4864             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4865             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6
    4866             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4867             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexH1_2__Tie0_5_5__regXZR
    4868             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4869             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6
    4870             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4871             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexS1_2__Tie0_5_5__regXZR
    4872             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4873             :   // Convert__Reg1_4__VecListTwo1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6
    4874             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4875             :   // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4876             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4877             :   // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4878             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4879             :   // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4
    4880             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4881             :   // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4882             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4883             :   // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
    4884             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4885             :   // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4
    4886             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4887             :   // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4888             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4889             :   // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4890             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4891             :   // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4
    4892             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4893             :   // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4894             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4895             :   // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
    4896             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4897             :   // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4
    4898             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
    4899             :   // Convert__TypedVectorList3_081_0__VectorIndexB1_1__Reg1_3
    4900             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4901             :   // Convert__TypedVectorList3_0641_0__VectorIndexD1_1__Reg1_3
    4902             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4903             :   // Convert__TypedVectorList3_0161_0__VectorIndexH1_1__Reg1_3
    4904             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4905             :   // Convert__TypedVectorList3_0321_0__VectorIndexS1_1__Reg1_3
    4906             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4907             :   // Convert__VecListThree1281_1__VectorIndexB1_2__Reg1_4
    4908             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4909             :   // Convert__VecListThree1281_1__VectorIndexD1_2__Reg1_4
    4910             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4911             :   // Convert__VecListThree1281_1__VectorIndexH1_2__Reg1_4
    4912             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4913             :   // Convert__VecListThree1281_1__VectorIndexS1_2__Reg1_4
    4914             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4915             :   // Convert__Reg1_3__TypedVectorList3_081_0__VectorIndexB1_1__Tie0_4_4__regXZR
    4916             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4917             :   // Convert__Reg1_3__TypedVectorList3_081_0__VectorIndexB1_1__Tie0_4_4__Reg1_5
    4918             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4919             :   // Convert__Reg1_3__TypedVectorList3_0641_0__VectorIndexD1_1__Tie0_4_4__regXZR
    4920             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4921             :   // Convert__Reg1_3__TypedVectorList3_0641_0__VectorIndexD1_1__Tie0_4_4__Reg1_5
    4922             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4923             :   // Convert__Reg1_3__TypedVectorList3_0161_0__VectorIndexH1_1__Tie0_4_4__regXZR
    4924             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4925             :   // Convert__Reg1_3__TypedVectorList3_0161_0__VectorIndexH1_1__Tie0_4_4__Reg1_5
    4926             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4927             :   // Convert__Reg1_3__TypedVectorList3_0321_0__VectorIndexS1_1__Tie0_4_4__regXZR
    4928             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4929             :   // Convert__Reg1_3__TypedVectorList3_0321_0__VectorIndexS1_1__Tie0_4_4__Reg1_5
    4930             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4931             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexB1_2__Tie0_5_5__regXZR
    4932             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4933             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6
    4934             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4935             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexD1_2__Tie0_5_5__regXZR
    4936             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4937             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6
    4938             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4939             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexH1_2__Tie0_5_5__regXZR
    4940             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4941             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6
    4942             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4943             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexS1_2__Tie0_5_5__regXZR
    4944             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    4945             :   // Convert__Reg1_4__VecListThree1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6
    4946             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    4947             :   // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4948             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4949             :   // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    4950             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4951             :   // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4
    4952             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_3_GT_, 5, CVT_Done },
    4953             :   // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4954             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4955             :   // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
    4956             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4957             :   // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4
    4958             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_3_GT_, 5, CVT_Done },
    4959             :   // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4960             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4961             :   // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    4962             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4963             :   // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4
    4964             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_3_GT_, 5, CVT_Done },
    4965             :   // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    4966             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    4967             :   // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
    4968             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    4969             :   // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4
    4970             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_3_GT_, 5, CVT_Done },
    4971             :   // Convert__TypedVectorList4_081_0__VectorIndexB1_1__Reg1_3
    4972             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4973             :   // Convert__TypedVectorList4_0641_0__VectorIndexD1_1__Reg1_3
    4974             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4975             :   // Convert__TypedVectorList4_0161_0__VectorIndexH1_1__Reg1_3
    4976             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4977             :   // Convert__TypedVectorList4_0321_0__VectorIndexS1_1__Reg1_3
    4978             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
    4979             :   // Convert__VecListFour1281_1__VectorIndexB1_2__Reg1_4
    4980             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4981             :   // Convert__VecListFour1281_1__VectorIndexD1_2__Reg1_4
    4982             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4983             :   // Convert__VecListFour1281_1__VectorIndexH1_2__Reg1_4
    4984             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4985             :   // Convert__VecListFour1281_1__VectorIndexS1_2__Reg1_4
    4986             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
    4987             :   // Convert__Reg1_3__TypedVectorList4_081_0__VectorIndexB1_1__Tie0_4_4__regXZR
    4988             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4989             :   // Convert__Reg1_3__TypedVectorList4_081_0__VectorIndexB1_1__Tie0_4_4__Reg1_5
    4990             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4991             :   // Convert__Reg1_3__TypedVectorList4_0641_0__VectorIndexD1_1__Tie0_4_4__regXZR
    4992             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4993             :   // Convert__Reg1_3__TypedVectorList4_0641_0__VectorIndexD1_1__Tie0_4_4__Reg1_5
    4994             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4995             :   // Convert__Reg1_3__TypedVectorList4_0161_0__VectorIndexH1_1__Tie0_4_4__regXZR
    4996             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    4997             :   // Convert__Reg1_3__TypedVectorList4_0161_0__VectorIndexH1_1__Tie0_4_4__Reg1_5
    4998             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    4999             :   // Convert__Reg1_3__TypedVectorList4_0321_0__VectorIndexS1_1__Tie0_4_4__regXZR
    5000             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
    5001             :   // Convert__Reg1_3__TypedVectorList4_0321_0__VectorIndexS1_1__Tie0_4_4__Reg1_5
    5002             :   { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
    5003             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexB1_2__Tie0_5_5__regXZR
    5004             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    5005             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexB1_2__Tie0_5_5__Reg1_6
    5006             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    5007             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexD1_2__Tie0_5_5__regXZR
    5008             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    5009             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexD1_2__Tie0_5_5__Reg1_6
    5010             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    5011             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexH1_2__Tie0_5_5__regXZR
    5012             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    5013             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexH1_2__Tie0_5_5__Reg1_6
    5014             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    5015             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexS1_2__Tie0_5_5__regXZR
    5016             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
    5017             :   // Convert__Reg1_4__VecListFour1281_1__VectorIndexS1_2__Tie0_5_5__Reg1_6
    5018             :   { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
    5019             :   // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    5020             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    5021             :   // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
    5022             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    5023             :   // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4
    5024             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    5025             :   // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    5026             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    5027             :   // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
    5028             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    5029             :   // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4
    5030             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    5031             :   // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    5032             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    5033             :   // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
    5034             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    5035             :   // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4
    5036             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    5037             :   // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
    5038             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
    5039             :   // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
    5040             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
    5041             :   // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4
    5042             :   { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
    5043             :   // Convert__regWZR__Reg1_0__Reg1_2
    5044             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
    5045             :   // Convert__regXZR__Reg1_0__Reg1_2
    5046             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
    5047             :   // Convert__Reg1_0__Reg1_1__Reg1_2__GPR64sp01_4
    5048             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 5, CVT_Done },
    5049             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1
    5050             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
    5051             :   // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7
    5052             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_7, 0, CVT_Done },
    5053             :   // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15
    5054             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_15, 0, CVT_Done },
    5055             :   // Convert__VectorReg1281_1__VectorReg641_2__imm_95_0
    5056             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    5057             :   // Convert__VectorReg1281_0__VectorReg641_2__imm_95_0
    5058             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    5059             :   // Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0
    5060             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    5061             :   // Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0
    5062             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_imm_95_0, 0, CVT_Done },
    5063             :   // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_31
    5064             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done },
    5065             :   // Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__regXZR
    5066             :   { CVT_95_addImmOperands, 1, CVT_95_addSysCROperands, 2, CVT_95_addSysCROperands, 3, CVT_95_addImmOperands, 4, CVT_regXZR, 0, CVT_Done },
    5067             :   // Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__Reg1_4
    5068             :   { CVT_95_addImmOperands, 1, CVT_95_addSysCROperands, 2, CVT_95_addSysCROperands, 3, CVT_95_addImmOperands, 4, CVT_95_Reg, 5, CVT_Done },
    5069             :   // Convert__Reg1_0__Imm0_71_1__SysCR1_2__SysCR1_3__Imm0_71_4
    5070             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addSysCROperands, 3, CVT_95_addSysCROperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
    5071             :   // Convert__VectorReg1281_1__VecListFour1281_2__VectorReg1281_3
    5072             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5073             :   // Convert__VectorReg1281_1__VecListOne1281_2__VectorReg1281_3
    5074             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5075             :   // Convert__VectorReg1281_1__VecListThree1281_2__VectorReg1281_3
    5076             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5077             :   // Convert__VectorReg1281_1__VecListTwo1281_2__VectorReg1281_3
    5078             :   { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5079             :   // Convert__VectorReg641_1__VecListFour1281_2__VectorReg641_3
    5080             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5081             :   // Convert__VectorReg641_1__VecListOne1281_2__VectorReg641_3
    5082             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5083             :   // Convert__VectorReg641_1__VecListThree1281_2__VectorReg641_3
    5084             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5085             :   // Convert__VectorReg641_1__VecListTwo1281_2__VectorReg641_3
    5086             :   { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5087             :   // Convert__VectorReg1281_0__TypedVectorList4_1681_2__VectorReg1281_3
    5088             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5089             :   // Convert__VectorReg1281_0__TypedVectorList1_1681_2__VectorReg1281_3
    5090             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5091             :   // Convert__VectorReg1281_0__TypedVectorList3_1681_2__VectorReg1281_3
    5092             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5093             :   // Convert__VectorReg1281_0__TypedVectorList2_1681_2__VectorReg1281_3
    5094             :   { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5095             :   // Convert__VectorReg641_0__TypedVectorList4_1681_2__VectorReg641_3
    5096             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5097             :   // Convert__VectorReg641_0__TypedVectorList1_1681_2__VectorReg641_3
    5098             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5099             :   // Convert__VectorReg641_0__TypedVectorList3_1681_2__VectorReg641_3
    5100             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5101             :   // Convert__VectorReg641_0__TypedVectorList2_1681_2__VectorReg641_3
    5102             :   { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5103             :   // Convert__Reg1_0__Imm0_311_1__BranchTarget141_2
    5104             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
    5105             :   // Convert__Reg1_0__Imm32_631_1__BranchTarget141_2
    5106             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
    5107             :   // Convert__GPR32as641_0__TBZImm0_311_1__BranchTarget141_2
    5108             :   { CVT_95_addGPR32as64Operands, 1, CVT_95_addImmOperands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
    5109             :   // Convert__VectorReg1281_1__Tie0_2_2__VecListFour1281_2__VectorReg1281_3
    5110             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5111             :   // Convert__VectorReg1281_1__Tie0_2_2__VecListOne1281_2__VectorReg1281_3
    5112             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5113             :   // Convert__VectorReg1281_1__Tie0_2_2__VecListThree1281_2__VectorReg1281_3
    5114             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5115             :   // Convert__VectorReg1281_1__Tie0_2_2__VecListTwo1281_2__VectorReg1281_3
    5116             :   { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5117             :   // Convert__VectorReg641_1__Tie0_2_2__VecListFour1281_2__VectorReg641_3
    5118             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5119             :   // Convert__VectorReg641_1__Tie0_2_2__VecListOne1281_2__VectorReg641_3
    5120             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5121             :   // Convert__VectorReg641_1__Tie0_2_2__VecListThree1281_2__VectorReg641_3
    5122             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5123             :   // Convert__VectorReg641_1__Tie0_2_2__VecListTwo1281_2__VectorReg641_3
    5124             :   { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5125             :   // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg1281_3
    5126             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5127             :   // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg1281_3
    5128             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5129             :   // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList3_1681_2__VectorReg1281_3
    5130             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5131             :   // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList2_1681_2__VectorReg1281_3
    5132             :   { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
    5133             :   // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg641_3
    5134             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5135             :   // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg641_3
    5136             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5137             :   // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList3_1681_2__VectorReg641_3
    5138             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5139             :   // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList2_1681_2__VectorReg641_3
    5140             :   { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
    5141             :   // Convert__regWZR__Reg1_0__LogicalImm321_1
    5142             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 2, CVT_Done },
    5143             :   // Convert__regXZR__Reg1_0__LogicalImm641_1
    5144             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 2, CVT_Done },
    5145             :   // Convert__regWZR__Reg1_0__Reg1_1__LogicalShifter321_2
    5146             :   { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    5147             :   // Convert__regXZR__Reg1_0__Reg1_1__LogicalShifter641_2
    5148             :   { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
    5149             :   // Convert__imm_95_2
    5150             :   { CVT_imm_95_2, 0, CVT_Done },
    5151             :   // Convert__imm_95_3
    5152             :   { CVT_imm_95_3, 0, CVT_Done },
    5153             :   // Convert__imm_95_1
    5154             :   { CVT_imm_95_1, 0, CVT_Done },
    5155             :   // Convert__SVEPredicateHReg1_0__SVEPredicateHReg1_1__SVEPredicateHReg1_2
    5156             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    5157             :   // Convert__SVEPredicateSReg1_0__SVEPredicateSReg1_1__SVEPredicateSReg1_2
    5158             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    5159             :   // Convert__SVEPredicateDReg1_0__SVEPredicateDReg1_1__SVEPredicateDReg1_2
    5160             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    5161             :   // Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1__SVEPredicateBReg1_2
    5162             :   { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
    5163             : };
    5164             : 
    5165       15974 : void AArch64AsmParser::
    5166             : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
    5167             :                 const OperandVector &Operands) {
    5168             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    5169       15974 :   const uint8_t *Converter = ConversionTable[Kind];
    5170             :   unsigned OpIdx;
    5171             :   Inst.setOpcode(Opcode);
    5172      115740 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    5173       49883 :     OpIdx = *(p + 1);
    5174       49883 :     switch (*p) {
    5175           0 :     default: llvm_unreachable("invalid conversion entry!");
    5176           0 :     case CVT_Reg:
    5177           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    5178             :       break;
    5179        2420 :     case CVT_Tied: {
    5180             :       assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
    5181             :                           std::begin(TiedAsmOperandTable)) &&
    5182             :              "Tied operand not found");
    5183        2420 :       unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
    5184             :       Inst.addOperand(Inst.getOperand(TiedResOpnd));
    5185             :       break;
    5186             :     }
    5187       19559 :     case CVT_95_Reg:
    5188       39118 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    5189             :       break;
    5190        3658 :     case CVT_95_addVectorReg128Operands:
    5191        7316 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorReg128Operands(Inst, 1);
    5192             :       break;
    5193        2407 :     case CVT_95_addVectorReg64Operands:
    5194        4814 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorReg64Operands(Inst, 1);
    5195             :       break;
    5196             :     case CVT_imm_95_16:
    5197         164 :       Inst.addOperand(MCOperand::createImm(16));
    5198             :       break;
    5199             :     case CVT_imm_95_24:
    5200           8 :       Inst.addOperand(MCOperand::createImm(24));
    5201             :       break;
    5202             :     case CVT_imm_95_0:
    5203        2888 :       Inst.addOperand(MCOperand::createImm(0));
    5204             :       break;
    5205          20 :     case CVT_95_addAddSubImmNegOperands:
    5206          40 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addAddSubImmNegOperands(Inst, 2);
    5207             :       break;
    5208         462 :     case CVT_95_addAddSubImmOperands:
    5209         924 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addAddSubImmOperands(Inst, 2);
    5210             :       break;
    5211        5925 :     case CVT_95_addRegOperands:
    5212       11850 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    5213             :       break;
    5214         396 :     case CVT_95_addShifterOperands:
    5215         792 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addShifterOperands(Inst, 1);
    5216             :       break;
    5217         155 :     case CVT_95_addExtendOperands:
    5218         310 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addExtendOperands(Inst, 1);
    5219             :       break;
    5220          54 :     case CVT_95_addExtend64Operands:
    5221         108 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addExtend64Operands(Inst, 1);
    5222             :       break;
    5223        2461 :     case CVT_95_addImmOperands:
    5224        2461 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    5225             :       break;
    5226          27 :     case CVT_95_addAdrLabelOperands:
    5227          27 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
    5228             :       break;
    5229         172 :     case CVT_95_addAdrpLabelOperands:
    5230         344 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addAdrpLabelOperands(Inst, 1);
    5231             :       break;
    5232          45 :     case CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_:
    5233          90 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int32_t>(Inst, 1);
    5234             :       break;
    5235          51 :     case CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_:
    5236         102 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int64_t>(Inst, 1);
    5237             :       break;
    5238           3 :     case CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_:
    5239           6 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int16_t>(Inst, 1);
    5240             :       break;
    5241           3 :     case CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_:
    5242           6 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int8_t>(Inst, 1);
    5243             :       break;
    5244             :     case CVT_imm_95_31:
    5245          70 :       Inst.addOperand(MCOperand::createImm(31));
    5246             :       break;
    5247             :     case CVT_imm_95_63:
    5248           4 :       Inst.addOperand(MCOperand::createImm(63));
    5249             :       break;
    5250          71 :     case CVT_95_addBranchTarget26Operands:
    5251         142 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addBranchTarget26Operands(Inst, 1);
    5252             :       break;
    5253         243 :     case CVT_95_addCondCodeOperands:
    5254         243 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 1);
    5255             :       break;
    5256         179 :     case CVT_95_addPCRelLabel19Operands:
    5257         358 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addPCRelLabel19Operands(Inst, 1);
    5258             :       break;
    5259           7 :     case CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_:
    5260          14 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int32_t>(Inst, 1);
    5261             :       break;
    5262           9 :     case CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_:
    5263          18 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int64_t>(Inst, 1);
    5264             :       break;
    5265           3 :     case CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_:
    5266           6 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int16_t>(Inst, 1);
    5267             :       break;
    5268           3 :     case CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_:
    5269           6 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int8_t>(Inst, 1);
    5270             :       break;
    5271             :     case CVT_imm_95_15:
    5272          22 :       Inst.addOperand(MCOperand::createImm(15));
    5273             :       break;
    5274             :     case CVT_regWZR:
    5275         944 :       Inst.addOperand(MCOperand::createReg(AArch64::WZR));
    5276             :       break;
    5277             :     case CVT_regXZR:
    5278        1602 :       Inst.addOperand(MCOperand::createReg(AArch64::XZR));
    5279             :       break;
    5280             :     case CVT_imm_95_20:
    5281           2 :       Inst.addOperand(MCOperand::createImm(20));
    5282             :       break;
    5283          45 :     case CVT_95_addBarrierOperands:
    5284          45 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addBarrierOperands(Inst, 1);
    5285             :       break;
    5286         730 :     case CVT_95_addVectorIndexOperands:
    5287         730 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorIndexOperands(Inst, 1);
    5288             :       break;
    5289          12 :     case CVT_95_addComplexRotationOddOperands:
    5290          24 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
    5291             :       break;
    5292          30 :     case CVT_95_addComplexRotationEvenOperands:
    5293          30 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
    5294             :       break;
    5295         101 :     case CVT_95_addVectorRegLoOperands:
    5296         202 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorRegLoOperands(Inst, 1);
    5297             :       break;
    5298          31 :     case CVT_95_addFPImmOperands:
    5299          31 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
    5300             :       break;
    5301         253 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_:
    5302         506 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_QReg, 4>(Inst, 1);
    5303             :       break;
    5304         161 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_:
    5305         322 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_DReg, 4>(Inst, 1);
    5306             :       break;
    5307         174 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_:
    5308         348 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_QReg, 1>(Inst, 1);
    5309             :       break;
    5310          97 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_:
    5311         194 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_DReg, 1>(Inst, 1);
    5312             :       break;
    5313         258 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_:
    5314         516 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_QReg, 3>(Inst, 1);
    5315             :       break;
    5316         165 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_:
    5317         330 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_DReg, 3>(Inst, 1);
    5318             :       break;
    5319         251 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_:
    5320         502 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_QReg, 2>(Inst, 1);
    5321             :       break;
    5322         159 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_:
    5323         318 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_DReg, 2>(Inst, 1);
    5324             :       break;
    5325        1446 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_:
    5326        2892 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_ZReg, 1>(Inst, 1);
    5327             :       break;
    5328         345 :     case CVT_95_addImmScaledOperands_LT_1_GT_:
    5329         345 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<1>(Inst, 1);
    5330             :       break;
    5331         100 :     case CVT_95_addImmScaledOperands_LT_8_GT_:
    5332         100 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<8>(Inst, 1);
    5333             :       break;
    5334         105 :     case CVT_95_addImmScaledOperands_LT_2_GT_:
    5335         105 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<2>(Inst, 1);
    5336             :       break;
    5337          52 :     case CVT_95_addImmScaledOperands_LT_16_GT_:
    5338          52 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<16>(Inst, 1);
    5339             :       break;
    5340         156 :     case CVT_95_addImmScaledOperands_LT_4_GT_:
    5341         156 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<4>(Inst, 1);
    5342             :       break;
    5343         120 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_:
    5344         240 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_ZReg, 2>(Inst, 1);
    5345             :       break;
    5346         120 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_:
    5347         240 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_ZReg, 3>(Inst, 1);
    5348             :       break;
    5349          48 :     case CVT_95_addImmScaledOperands_LT_3_GT_:
    5350          48 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<3>(Inst, 1);
    5351             :       break;
    5352         120 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_:
    5353         240 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_ZReg, 4>(Inst, 1);
    5354             :       break;
    5355         126 :     case CVT_95_addUImm12OffsetOperands_LT_4_GT_:
    5356         252 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<4>(Inst, 1);
    5357             :       break;
    5358         227 :     case CVT_95_addUImm12OffsetOperands_LT_8_GT_:
    5359         454 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<8>(Inst, 1);
    5360             :       break;
    5361         114 :     case CVT_95_addUImm12OffsetOperands_LT_1_GT_:
    5362         228 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<1>(Inst, 1);
    5363             :       break;
    5364         117 :     case CVT_95_addUImm12OffsetOperands_LT_2_GT_:
    5365         234 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<2>(Inst, 1);
    5366             :       break;
    5367          53 :     case CVT_95_addUImm12OffsetOperands_LT_16_GT_:
    5368         106 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<16>(Inst, 1);
    5369             :       break;
    5370          58 :     case CVT_95_addMemExtendOperands:
    5371         116 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMemExtendOperands(Inst, 2);
    5372             :       break;
    5373           8 :     case CVT_95_addMemExtend8Operands:
    5374          16 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMemExtend8Operands(Inst, 2);
    5375             :       break;
    5376           8 :     case CVT_95_addMOVZMovAliasOperands_LT_0_GT_:
    5377           8 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<0>(Inst, 1);
    5378             :       break;
    5379           0 :     case CVT_95_addMOVZMovAliasOperands_LT_16_GT_:
    5380           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<16>(Inst, 1);
    5381             :       break;
    5382           5 :     case CVT_95_addMOVNMovAliasOperands_LT_0_GT_:
    5383          10 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<0>(Inst, 1);
    5384             :       break;
    5385           0 :     case CVT_95_addMOVNMovAliasOperands_LT_16_GT_:
    5386           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<16>(Inst, 1);
    5387             :       break;
    5388           1 :     case CVT_95_addMOVZMovAliasOperands_LT_32_GT_:
    5389           2 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<32>(Inst, 1);
    5390             :       break;
    5391             :     case CVT_imm_95_32:
    5392          84 :       Inst.addOperand(MCOperand::createImm(32));
    5393             :       break;
    5394           0 :     case CVT_95_addMOVZMovAliasOperands_LT_48_GT_:
    5395           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<48>(Inst, 1);
    5396             :       break;
    5397             :     case CVT_imm_95_48:
    5398          24 :       Inst.addOperand(MCOperand::createImm(48));
    5399             :       break;
    5400           0 :     case CVT_95_addMOVNMovAliasOperands_LT_32_GT_:
    5401           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<32>(Inst, 1);
    5402             :       break;
    5403           0 :     case CVT_95_addMOVNMovAliasOperands_LT_48_GT_:
    5404           0 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<48>(Inst, 1);
    5405             :       break;
    5406           6 :     case CVT_95_addSIMDImmType10Operands:
    5407          12 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSIMDImmType10Operands(Inst, 1);
    5408             :       break;
    5409        1034 :     case CVT_95_addMRSSystemRegisterOperands:
    5410        2068 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMRSSystemRegisterOperands(Inst, 1);
    5411             :       break;
    5412         750 :     case CVT_95_addMSRSystemRegisterOperands:
    5413        1500 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addMSRSystemRegisterOperands(Inst, 1);
    5414             :       break;
    5415           5 :     case CVT_95_addSystemPStateFieldWithImm0_95_15Operands:
    5416          10 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSystemPStateFieldWithImm0_15Operands(Inst, 1);
    5417             :       break;
    5418           4 :     case CVT_95_addSystemPStateFieldWithImm0_95_1Operands:
    5419           8 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSystemPStateFieldWithImm0_1Operands(Inst, 1);
    5420             :       break;
    5421         512 :     case CVT_95_addPrefetchOperands:
    5422         512 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addPrefetchOperands(Inst, 1);
    5423             :       break;
    5424           1 :     case CVT_95_addPSBHintOperands:
    5425           1 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addPSBHintOperands(Inst, 1);
    5426             :       break;
    5427             :     case CVT_regLR:
    5428         234 :       Inst.addOperand(MCOperand::createReg(AArch64::LR));
    5429             :       break;
    5430             :     case CVT_imm_95_4:
    5431           6 :       Inst.addOperand(MCOperand::createImm(4));
    5432             :       break;
    5433             :     case CVT_imm_95_5:
    5434           6 :       Inst.addOperand(MCOperand::createImm(5));
    5435             :       break;
    5436             :     case CVT_imm_95_7:
    5437          18 :       Inst.addOperand(MCOperand::createImm(7));
    5438             :       break;
    5439         356 :     case CVT_95_addSysCROperands:
    5440         356 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addSysCROperands(Inst, 1);
    5441             :       break;
    5442          29 :     case CVT_95_addBranchTarget14Operands:
    5443          58 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addBranchTarget14Operands(Inst, 1);
    5444             :       break;
    5445          10 :     case CVT_95_addGPR32as64Operands:
    5446          20 :       static_cast<AArch64Operand&>(*Operands[OpIdx]).addGPR32as64Operands(Inst, 1);
    5447             :       break;
    5448             :     case CVT_imm_95_2:
    5449           6 :       Inst.addOperand(MCOperand::createImm(2));
    5450             :       break;
    5451             :     case CVT_imm_95_3:
    5452           6 :       Inst.addOperand(MCOperand::createImm(3));
    5453             :       break;
    5454             :     case CVT_imm_95_1:
    5455           6 :       Inst.addOperand(MCOperand::createImm(1));
    5456             :       break;
    5457             :     }
    5458             :   }
    5459       15974 : }
    5460             : 
    5461           0 : void AArch64AsmParser::
    5462             : convertToMapAndConstraints(unsigned Kind,
    5463             :                            const OperandVector &Operands) {
    5464             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    5465             :   unsigned NumMCOperands = 0;
    5466           0 :   const uint8_t *Converter = ConversionTable[Kind];
    5467           0 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    5468           0 :     switch (*p) {
    5469           0 :     default: llvm_unreachable("invalid conversion entry!");
    5470           0 :     case CVT_Reg:
    5471           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5472           0 :       Operands[*(p + 1)]->setConstraint("r");
    5473           0 :       ++NumMCOperands;
    5474           0 :       break;
    5475           0 :     case CVT_Tied:
    5476           0 :       ++NumMCOperands;
    5477           0 :       break;
    5478           0 :     case CVT_95_Reg:
    5479           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5480           0 :       Operands[*(p + 1)]->setConstraint("r");
    5481           0 :       NumMCOperands += 1;
    5482           0 :       break;
    5483           0 :     case CVT_95_addVectorReg128Operands:
    5484           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5485           0 :       Operands[*(p + 1)]->setConstraint("m");
    5486           0 :       NumMCOperands += 1;
    5487           0 :       break;
    5488           0 :     case CVT_95_addVectorReg64Operands:
    5489           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5490           0 :       Operands[*(p + 1)]->setConstraint("m");
    5491           0 :       NumMCOperands += 1;
    5492           0 :       break;
    5493           0 :     case CVT_imm_95_16:
    5494           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5495           0 :       Operands[*(p + 1)]->setConstraint("");
    5496           0 :       ++NumMCOperands;
    5497           0 :       break;
    5498           0 :     case CVT_imm_95_24:
    5499           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5500           0 :       Operands[*(p + 1)]->setConstraint("");
    5501           0 :       ++NumMCOperands;
    5502           0 :       break;
    5503           0 :     case CVT_imm_95_0:
    5504           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5505           0 :       Operands[*(p + 1)]->setConstraint("");
    5506           0 :       ++NumMCOperands;
    5507           0 :       break;
    5508           0 :     case CVT_95_addAddSubImmNegOperands:
    5509           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5510           0 :       Operands[*(p + 1)]->setConstraint("m");
    5511           0 :       NumMCOperands += 2;
    5512           0 :       break;
    5513           0 :     case CVT_95_addAddSubImmOperands:
    5514           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5515           0 :       Operands[*(p + 1)]->setConstraint("m");
    5516           0 :       NumMCOperands += 2;
    5517           0 :       break;
    5518           0 :     case CVT_95_addRegOperands:
    5519           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5520           0 :       Operands[*(p + 1)]->setConstraint("m");
    5521           0 :       NumMCOperands += 1;
    5522           0 :       break;
    5523           0 :     case CVT_95_addShifterOperands:
    5524           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5525           0 :       Operands[*(p + 1)]->setConstraint("m");
    5526           0 :       NumMCOperands += 1;
    5527           0 :       break;
    5528           0 :     case CVT_95_addExtendOperands:
    5529           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5530           0 :       Operands[*(p + 1)]->setConstraint("m");
    5531           0 :       NumMCOperands += 1;
    5532           0 :       break;
    5533           0 :     case CVT_95_addExtend64Operands:
    5534           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5535           0 :       Operands[*(p + 1)]->setConstraint("m");
    5536           0 :       NumMCOperands += 1;
    5537           0 :       break;
    5538           0 :     case CVT_95_addImmOperands:
    5539           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5540           0 :       Operands[*(p + 1)]->setConstraint("m");
    5541           0 :       NumMCOperands += 1;
    5542           0 :       break;
    5543           0 :     case CVT_95_addAdrLabelOperands:
    5544           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5545           0 :       Operands[*(p + 1)]->setConstraint("m");
    5546           0 :       NumMCOperands += 1;
    5547           0 :       break;
    5548           0 :     case CVT_95_addAdrpLabelOperands:
    5549           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5550           0 :       Operands[*(p + 1)]->setConstraint("m");
    5551           0 :       NumMCOperands += 1;
    5552           0 :       break;
    5553           0 :     case CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_:
    5554           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5555           0 :       Operands[*(p + 1)]->setConstraint("m");
    5556           0 :       NumMCOperands += 1;
    5557           0 :       break;
    5558           0 :     case CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_:
    5559           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5560           0 :       Operands[*(p + 1)]->setConstraint("m");
    5561           0 :       NumMCOperands += 1;
    5562           0 :       break;
    5563           0 :     case CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_:
    5564           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5565           0 :       Operands[*(p + 1)]->setConstraint("m");
    5566           0 :       NumMCOperands += 1;
    5567           0 :       break;
    5568           0 :     case CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_:
    5569           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5570           0 :       Operands[*(p + 1)]->setConstraint("m");
    5571           0 :       NumMCOperands += 1;
    5572           0 :       break;
    5573           0 :     case CVT_imm_95_31:
    5574           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5575           0 :       Operands[*(p + 1)]->setConstraint("");
    5576           0 :       ++NumMCOperands;
    5577           0 :       break;
    5578           0 :     case CVT_imm_95_63:
    5579           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5580           0 :       Operands[*(p + 1)]->setConstraint("");
    5581           0 :       ++NumMCOperands;
    5582           0 :       break;
    5583           0 :     case CVT_95_addBranchTarget26Operands:
    5584           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5585           0 :       Operands[*(p + 1)]->setConstraint("m");
    5586           0 :       NumMCOperands += 1;
    5587           0 :       break;
    5588           0 :     case CVT_95_addCondCodeOperands:
    5589           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5590           0 :       Operands[*(p + 1)]->setConstraint("m");
    5591           0 :       NumMCOperands += 1;
    5592           0 :       break;
    5593           0 :     case CVT_95_addPCRelLabel19Operands:
    5594           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5595           0 :       Operands[*(p + 1)]->setConstraint("m");
    5596           0 :       NumMCOperands += 1;
    5597           0 :       break;
    5598           0 :     case CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_:
    5599           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5600           0 :       Operands[*(p + 1)]->setConstraint("m");
    5601           0 :       NumMCOperands += 1;
    5602           0 :       break;
    5603           0 :     case CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_:
    5604           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5605           0 :       Operands[*(p + 1)]->setConstraint("m");
    5606           0 :       NumMCOperands += 1;
    5607           0 :       break;
    5608           0 :     case CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_:
    5609           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5610           0 :       Operands[*(p + 1)]->setConstraint("m");
    5611           0 :       NumMCOperands += 1;
    5612           0 :       break;
    5613           0 :     case CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_:
    5614           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5615           0 :       Operands[*(p + 1)]->setConstraint("m");
    5616           0 :       NumMCOperands += 1;
    5617           0 :       break;
    5618           0 :     case CVT_imm_95_15:
    5619           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5620           0 :       Operands[*(p + 1)]->setConstraint("");
    5621           0 :       ++NumMCOperands;
    5622           0 :       break;
    5623           0 :     case CVT_regWZR:
    5624           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5625           0 :       Operands[*(p + 1)]->setConstraint("m");
    5626           0 :       ++NumMCOperands;
    5627           0 :       break;
    5628           0 :     case CVT_regXZR:
    5629           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5630           0 :       Operands[*(p + 1)]->setConstraint("m");
    5631           0 :       ++NumMCOperands;
    5632           0 :       break;
    5633           0 :     case CVT_imm_95_20:
    5634           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5635           0 :       Operands[*(p + 1)]->setConstraint("");
    5636           0 :       ++NumMCOperands;
    5637           0 :       break;
    5638           0 :     case CVT_95_addBarrierOperands:
    5639           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5640           0 :       Operands[*(p + 1)]->setConstraint("m");
    5641           0 :       NumMCOperands += 1;
    5642           0 :       break;
    5643           0 :     case CVT_95_addVectorIndexOperands:
    5644           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5645           0 :       Operands[*(p + 1)]->setConstraint("m");
    5646           0 :       NumMCOperands += 1;
    5647           0 :       break;
    5648           0 :     case CVT_95_addComplexRotationOddOperands:
    5649           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5650           0 :       Operands[*(p + 1)]->setConstraint("m");
    5651           0 :       NumMCOperands += 1;
    5652           0 :       break;
    5653           0 :     case CVT_95_addComplexRotationEvenOperands:
    5654           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5655           0 :       Operands[*(p + 1)]->setConstraint("m");
    5656           0 :       NumMCOperands += 1;
    5657           0 :       break;
    5658           0 :     case CVT_95_addVectorRegLoOperands:
    5659           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5660           0 :       Operands[*(p + 1)]->setConstraint("m");
    5661           0 :       NumMCOperands += 1;
    5662           0 :       break;
    5663           0 :     case CVT_95_addFPImmOperands:
    5664           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5665           0 :       Operands[*(p + 1)]->setConstraint("m");
    5666           0 :       NumMCOperands += 1;
    5667           0 :       break;
    5668           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_:
    5669           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5670           0 :       Operands[*(p + 1)]->setConstraint("m");
    5671           0 :       NumMCOperands += 1;
    5672           0 :       break;
    5673           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_:
    5674           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5675           0 :       Operands[*(p + 1)]->setConstraint("m");
    5676           0 :       NumMCOperands += 1;
    5677           0 :       break;
    5678           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_:
    5679           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5680           0 :       Operands[*(p + 1)]->setConstraint("m");
    5681           0 :       NumMCOperands += 1;
    5682           0 :       break;
    5683           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_:
    5684           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5685           0 :       Operands[*(p + 1)]->setConstraint("m");
    5686           0 :       NumMCOperands += 1;
    5687           0 :       break;
    5688           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_:
    5689           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5690           0 :       Operands[*(p + 1)]->setConstraint("m");
    5691           0 :       NumMCOperands += 1;
    5692           0 :       break;
    5693           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_:
    5694           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5695           0 :       Operands[*(p + 1)]->setConstraint("m");
    5696           0 :       NumMCOperands += 1;
    5697           0 :       break;
    5698           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_:
    5699           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5700           0 :       Operands[*(p + 1)]->setConstraint("m");
    5701           0 :       NumMCOperands += 1;
    5702           0 :       break;
    5703           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_:
    5704           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5705           0 :       Operands[*(p + 1)]->setConstraint("m");
    5706           0 :       NumMCOperands += 1;
    5707           0 :       break;
    5708           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_:
    5709           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5710           0 :       Operands[*(p + 1)]->setConstraint("m");
    5711           0 :       NumMCOperands += 1;
    5712           0 :       break;
    5713           0 :     case CVT_95_addImmScaledOperands_LT_1_GT_:
    5714           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5715           0 :       Operands[*(p + 1)]->setConstraint("m");
    5716           0 :       NumMCOperands += 1;
    5717           0 :       break;
    5718           0 :     case CVT_95_addImmScaledOperands_LT_8_GT_:
    5719           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5720           0 :       Operands[*(p + 1)]->setConstraint("m");
    5721           0 :       NumMCOperands += 1;
    5722           0 :       break;
    5723           0 :     case CVT_95_addImmScaledOperands_LT_2_GT_:
    5724           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5725           0 :       Operands[*(p + 1)]->setConstraint("m");
    5726           0 :       NumMCOperands += 1;
    5727           0 :       break;
    5728           0 :     case CVT_95_addImmScaledOperands_LT_16_GT_:
    5729           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5730           0 :       Operands[*(p + 1)]->setConstraint("m");
    5731           0 :       NumMCOperands += 1;
    5732           0 :       break;
    5733           0 :     case CVT_95_addImmScaledOperands_LT_4_GT_:
    5734           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5735           0 :       Operands[*(p + 1)]->setConstraint("m");
    5736           0 :       NumMCOperands += 1;
    5737           0 :       break;
    5738           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_:
    5739           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5740           0 :       Operands[*(p + 1)]->setConstraint("m");
    5741           0 :       NumMCOperands += 1;
    5742           0 :       break;
    5743           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_:
    5744           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5745           0 :       Operands[*(p + 1)]->setConstraint("m");
    5746           0 :       NumMCOperands += 1;
    5747           0 :       break;
    5748           0 :     case CVT_95_addImmScaledOperands_LT_3_GT_:
    5749           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5750           0 :       Operands[*(p + 1)]->setConstraint("m");
    5751           0 :       NumMCOperands += 1;
    5752           0 :       break;
    5753           0 :     case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_:
    5754           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5755           0 :       Operands[*(p + 1)]->setConstraint("m");
    5756           0 :       NumMCOperands += 1;
    5757           0 :       break;
    5758           0 :     case CVT_95_addUImm12OffsetOperands_LT_4_GT_:
    5759           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5760           0 :       Operands[*(p + 1)]->setConstraint("m");
    5761           0 :       NumMCOperands += 1;
    5762           0 :       break;
    5763           0 :     case CVT_95_addUImm12OffsetOperands_LT_8_GT_:
    5764           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5765           0 :       Operands[*(p + 1)]->setConstraint("m");
    5766           0 :       NumMCOperands += 1;
    5767           0 :       break;
    5768           0 :     case CVT_95_addUImm12OffsetOperands_LT_1_GT_:
    5769           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5770           0 :       Operands[*(p + 1)]->setConstraint("m");
    5771           0 :       NumMCOperands += 1;
    5772           0 :       break;
    5773           0 :     case CVT_95_addUImm12OffsetOperands_LT_2_GT_:
    5774           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5775           0 :       Operands[*(p + 1)]->setConstraint("m");
    5776           0 :       NumMCOperands += 1;
    5777           0 :       break;
    5778           0 :     case CVT_95_addUImm12OffsetOperands_LT_16_GT_:
    5779           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5780           0 :       Operands[*(p + 1)]->setConstraint("m");
    5781           0 :       NumMCOperands += 1;
    5782           0 :       break;
    5783           0 :     case CVT_95_addMemExtendOperands:
    5784           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5785           0 :       Operands[*(p + 1)]->setConstraint("m");
    5786           0 :       NumMCOperands += 2;
    5787           0 :       break;
    5788           0 :     case CVT_95_addMemExtend8Operands:
    5789           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5790           0 :       Operands[*(p + 1)]->setConstraint("m");
    5791           0 :       NumMCOperands += 2;
    5792           0 :       break;
    5793           0 :     case CVT_95_addMOVZMovAliasOperands_LT_0_GT_:
    5794           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5795           0 :       Operands[*(p + 1)]->setConstraint("m");
    5796           0 :       NumMCOperands += 1;
    5797           0 :       break;
    5798           0 :     case CVT_95_addMOVZMovAliasOperands_LT_16_GT_:
    5799           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5800           0 :       Operands[*(p + 1)]->setConstraint("m");
    5801           0 :       NumMCOperands += 1;
    5802           0 :       break;
    5803           0 :     case CVT_95_addMOVNMovAliasOperands_LT_0_GT_:
    5804           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5805           0 :       Operands[*(p + 1)]->setConstraint("m");
    5806           0 :       NumMCOperands += 1;
    5807           0 :       break;
    5808           0 :     case CVT_95_addMOVNMovAliasOperands_LT_16_GT_:
    5809           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5810           0 :       Operands[*(p + 1)]->setConstraint("m");
    5811           0 :       NumMCOperands += 1;
    5812           0 :       break;
    5813           0 :     case CVT_95_addMOVZMovAliasOperands_LT_32_GT_:
    5814           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5815           0 :       Operands[*(p + 1)]->setConstraint("m");
    5816           0 :       NumMCOperands += 1;
    5817           0 :       break;
    5818           0 :     case CVT_imm_95_32:
    5819           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5820           0 :       Operands[*(p + 1)]->setConstraint("");
    5821           0 :       ++NumMCOperands;
    5822           0 :       break;
    5823           0 :     case CVT_95_addMOVZMovAliasOperands_LT_48_GT_:
    5824           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5825           0 :       Operands[*(p + 1)]->setConstraint("m");
    5826           0 :       NumMCOperands += 1;
    5827           0 :       break;
    5828           0 :     case CVT_imm_95_48:
    5829           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5830           0 :       Operands[*(p + 1)]->setConstraint("");
    5831           0 :       ++NumMCOperands;
    5832           0 :       break;
    5833           0 :     case CVT_95_addMOVNMovAliasOperands_LT_32_GT_:
    5834           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5835           0 :       Operands[*(p + 1)]->setConstraint("m");
    5836           0 :       NumMCOperands += 1;
    5837           0 :       break;
    5838           0 :     case CVT_95_addMOVNMovAliasOperands_LT_48_GT_:
    5839           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5840           0 :       Operands[*(p + 1)]->setConstraint("m");
    5841           0 :       NumMCOperands += 1;
    5842           0 :       break;
    5843           0 :     case CVT_95_addSIMDImmType10Operands:
    5844           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5845           0 :       Operands[*(p + 1)]->setConstraint("m");
    5846           0 :       NumMCOperands += 1;
    5847           0 :       break;
    5848           0 :     case CVT_95_addMRSSystemRegisterOperands:
    5849           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5850           0 :       Operands[*(p + 1)]->setConstraint("m");
    5851           0 :       NumMCOperands += 1;
    5852           0 :       break;
    5853           0 :     case CVT_95_addMSRSystemRegisterOperands:
    5854           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5855           0 :       Operands[*(p + 1)]->setConstraint("m");
    5856           0 :       NumMCOperands += 1;
    5857           0 :       break;
    5858           0 :     case CVT_95_addSystemPStateFieldWithImm0_95_15Operands:
    5859           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5860           0 :       Operands[*(p + 1)]->setConstraint("m");
    5861           0 :       NumMCOperands += 1;
    5862           0 :       break;
    5863           0 :     case CVT_95_addSystemPStateFieldWithImm0_95_1Operands:
    5864           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5865           0 :       Operands[*(p + 1)]->setConstraint("m");
    5866           0 :       NumMCOperands += 1;
    5867           0 :       break;
    5868           0 :     case CVT_95_addPrefetchOperands:
    5869           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5870           0 :       Operands[*(p + 1)]->setConstraint("m");
    5871           0 :       NumMCOperands += 1;
    5872           0 :       break;
    5873           0 :     case CVT_95_addPSBHintOperands:
    5874           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5875           0 :       Operands[*(p + 1)]->setConstraint("m");
    5876           0 :       NumMCOperands += 1;
    5877           0 :       break;
    5878           0 :     case CVT_regLR:
    5879           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5880           0 :       Operands[*(p + 1)]->setConstraint("m");
    5881           0 :       ++NumMCOperands;
    5882           0 :       break;
    5883           0 :     case CVT_imm_95_4:
    5884           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5885           0 :       Operands[*(p + 1)]->setConstraint("");
    5886           0 :       ++NumMCOperands;
    5887           0 :       break;
    5888           0 :     case CVT_imm_95_5:
    5889           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5890           0 :       Operands[*(p + 1)]->setConstraint("");
    5891           0 :       ++NumMCOperands;
    5892           0 :       break;
    5893           0 :     case CVT_imm_95_7:
    5894           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5895           0 :       Operands[*(p + 1)]->setConstraint("");
    5896           0 :       ++NumMCOperands;
    5897           0 :       break;
    5898           0 :     case CVT_95_addSysCROperands:
    5899           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5900           0 :       Operands[*(p + 1)]->setConstraint("m");
    5901           0 :       NumMCOperands += 1;
    5902           0 :       break;
    5903           0 :     case CVT_95_addBranchTarget14Operands:
    5904           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5905           0 :       Operands[*(p + 1)]->setConstraint("m");
    5906           0 :       NumMCOperands += 1;
    5907           0 :       break;
    5908           0 :     case CVT_95_addGPR32as64Operands:
    5909           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5910           0 :       Operands[*(p + 1)]->setConstraint("m");
    5911           0 :       NumMCOperands += 1;
    5912           0 :       break;
    5913           0 :     case CVT_imm_95_2:
    5914           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5915           0 :       Operands[*(p + 1)]->setConstraint("");
    5916           0 :       ++NumMCOperands;
    5917           0 :       break;
    5918           0 :     case CVT_imm_95_3:
    5919           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5920           0 :       Operands[*(p + 1)]->setConstraint("");
    5921           0 :       ++NumMCOperands;
    5922           0 :       break;
    5923           0 :     case CVT_imm_95_1:
    5924           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    5925           0 :       Operands[*(p + 1)]->setConstraint("");
    5926           0 :       ++NumMCOperands;
    5927           0 :       break;
    5928             :     }
    5929             :   }
    5930           0 : }
    5931             : 
    5932             : namespace {
    5933             : 
    5934             : /// MatchClassKind - The kinds of classes which participate in
    5935             : /// instruction matching.
    5936             : enum MatchClassKind {
    5937             :   InvalidMatchClass = 0,
    5938             :   OptionalMatchClass = 1,
    5939             :   MCK__DOT_16B, // '.16B'
    5940             :   MCK__DOT_1D, // '.1D'
    5941             :   MCK__DOT_1Q, // '.1Q'
    5942             :   MCK__DOT_2D, // '.2D'
    5943             :   MCK__DOT_2H, // '.2H'
    5944             :   MCK__DOT_2S, // '.2S'
    5945             :   MCK__DOT_4B, // '.4B'
    5946             :   MCK__DOT_4H, // '.4H'
    5947             :   MCK__DOT_4S, // '.4S'
    5948             :   MCK__DOT_8B, // '.8B'
    5949             :   MCK__DOT_8H, // '.8H'
    5950             :   MCK__DOT_B, // '.B'
    5951             :   MCK__DOT_D, // '.D'
    5952             :   MCK__DOT_H, // '.H'
    5953             :   MCK__DOT_Q, // '.Q'
    5954             :   MCK__DOT_S, // '.S'
    5955             :   MCK__EXCLAIM_, // '!'
    5956             :   MCK__35_0, // '#0'
    5957             :   MCK__35_1, // '#1'
    5958             :   MCK__35_12, // '#12'
    5959             :   MCK__35_16, // '#16'
    5960             :   MCK__35_2, // '#2'
    5961             :   MCK__35_24, // '#24'
    5962             :   MCK__35_3, // '#3'
    5963             :   MCK__35_32, // '#32'
    5964             :   MCK__35_4, // '#4'
    5965             :   MCK__35_48, // '#48'
    5966             :   MCK__35_6, // '#6'
    5967             :   MCK__35_64, // '#64'
    5968             :   MCK__35_8, // '#8'
    5969             :   MCK__DOT_, // '.'
    5970             :   MCK__DOT_0, // '.0'
    5971             :   MCK__DOT_16b, // '.16b'
    5972             :   MCK__DOT_1d, // '.1d'
    5973             :   MCK__DOT_1q, // '.1q'
    5974             :   MCK__DOT_2d, // '.2d'
    5975             :   MCK__DOT_2h, // '.2h'
    5976             :   MCK__DOT_2s, // '.2s'
    5977             :   MCK__DOT_4b, // '.4b'
    5978             :   MCK__DOT_4h, // '.4h'
    5979             :   MCK__DOT_4s, // '.4s'
    5980             :   MCK__DOT_8b, // '.8b'
    5981             :   MCK__DOT_8h, // '.8h'
    5982             :   MCK__DOT_b, // '.b'
    5983             :   MCK__DOT_d, // '.d'
    5984             :   MCK__DOT_h, // '.h'
    5985             :   MCK__DOT_q, // '.q'
    5986             :   MCK__DOT_s, // '.s'
    5987             :   MCK__47_, // '/'
    5988             :   MCK__91_, // '['
    5989             :   MCK__93_, // ']'
    5990             :   MCK_m, // 'm'
    5991             :   MCK_mul, // 'mul'
    5992             :   MCK_vl, // 'vl'
    5993             :   MCK_z, // 'z'
    5994             :   MCK_LAST_TOKEN = MCK_z,
    5995             :   MCK_CCR, // register class 'CCR'
    5996             :   MCK_GPR32sponly, // register class 'GPR32sponly'
    5997             :   MCK_GPR64sponly, // register class 'GPR64sponly'
    5998             :   MCK_PPR_3b, // register class 'PPR_3b'
    5999             :   MCK_Reg29, // derived register class
    6000             :   MCK_Reg62, // derived register class
    6001             :   MCK_Reg30, // derived register class
    6002             :   MCK_Reg39, // derived register class
    6003             :   MCK_Reg40, // derived register class
    6004             :   MCK_Reg63, // derived register class
    6005             :   MCK_Reg72, // derived register class
    6006             :   MCK_Reg73, // derived register class
    6007             :   MCK_Reg25, // derived register class
    6008             :   MCK_Reg31, // derived register class
    6009             :   MCK_Reg36, // derived register class
    6010             :   MCK_Reg38, // derived register class
    6011             :   MCK_Reg41, // derived register class
    6012             :   MCK_Reg46, // derived register class
    6013             :   MCK_Reg58, // derived register class
    6014             :   MCK_Reg64, // derived register class
    6015             :   MCK_Reg69, // derived register class
    6016             :   MCK_Reg71, // derived register class
    6017             :   MCK_Reg74, // derived register class
    6018             :   MCK_Reg79, // derived register class
    6019             :   MCK_Reg20, // derived register class
    6020             :   MCK_Reg26, // derived register class
    6021             :   MCK_Reg28, // derived register class
    6022             :   MCK_Reg32, // derived register class
    6023             :   MCK_Reg34, // derived register class
    6024             :   MCK_Reg35, // derived register class
    6025             :   MCK_Reg37, // derived register class
    6026             :   MCK_Reg42, // derived register class
    6027             :   MCK_Reg44, // derived register class
    6028             :   MCK_Reg45, // derived register class
    6029             :   MCK_Reg59, // derived register class
    6030             :   MCK_Reg61, // derived register class
    6031             :   MCK_Reg65, // derived register class
    6032             :   MCK_Reg67, // derived register class
    6033             :   MCK_Reg68, // derived register class
    6034             :   MCK_Reg70, // derived register class
    6035             :   MCK_Reg75, // derived register class
    6036             :   MCK_Reg77, // derived register class
    6037             :   MCK_Reg78, // derived register class
    6038             :   MCK_FPR128_lo, // register class 'FPR128_lo'
    6039             :   MCK_PPR, // register class 'PPR'
    6040             :   MCK_Reg51, // derived register class
    6041             :   MCK_Reg52, // derived register class
    6042             :   MCK_Reg57, // derived register class
    6043             :   MCK_tcGPR64, // register class 'tcGPR64'
    6044             :   MCK_Reg47, // derived register class
    6045             :   MCK_Reg53, // derived register class
    6046             :   MCK_Reg48, // derived register class
    6047             :   MCK_Reg50, // derived register class
    6048             :   MCK_Reg54, // derived register class
    6049             :   MCK_Reg56, // derived register class
    6050             :   MCK_GPR32common, // register class 'GPR32common'
    6051             :   MCK_GPR64common, // register class 'GPR64common'
    6052             :   MCK_DD, // register class 'DD'
    6053             :   MCK_DDD, // register class 'DDD'
    6054             :   MCK_DDDD, // register class 'DDDD'
    6055             :   MCK_FPR128, // register class 'FPR128'
    6056             :   MCK_FPR16, // register class 'FPR16'
    6057             :   MCK_FPR32, // register class 'FPR32'
    6058             :   MCK_FPR64, // register class 'FPR64'
    6059             :   MCK_FPR8, // register class 'FPR8'
    6060             :   MCK_GPR32, // register class 'GPR32'
    6061             :   MCK_GPR32sp, // register class 'GPR32sp'
    6062             :   MCK_GPR64, // register class 'GPR64'
    6063             :   MCK_GPR64sp, // register class 'GPR64sp'
    6064             :   MCK_QQ, // register class 'QQ'
    6065             :   MCK_QQQ, // register class 'QQQ'
    6066             :   MCK_QQQQ, // register class 'QQQQ'
    6067             :   MCK_WSeqPairsClass, // register class 'WSeqPairsClass'
    6068             :   MCK_XSeqPairsClass, // register class 'XSeqPairsClass'
    6069             :   MCK_ZPR, // register class 'ZPR'
    6070             :   MCK_ZPR2, // register class 'ZPR2'
    6071             :   MCK_ZPR3, // register class 'ZPR3'
    6072             :   MCK_ZPR4, // register class 'ZPR4'
    6073             :   MCK_GPR32all, // register class 'GPR32all'
    6074             :   MCK_GPR64all, // register class 'GPR64all'
    6075             :   MCK_LAST_REGISTER = MCK_GPR64all,
    6076             :   MCK_AddSubImmNeg, // user defined class 'AddSubImmNegOperand'
    6077             :   MCK_AddSubImm, // user defined class 'AddSubImmOperand'
    6078             :   MCK_AdrLabel, // user defined class 'AdrOperand'
    6079             :   MCK_AdrpLabel, // user defined class 'AdrpOperand'
    6080             :   MCK_Barrier, // user defined class 'BarrierAsmOperand'
    6081             :   MCK_BranchTarget14, // user defined class 'BranchTarget14Operand'
    6082             :   MCK_BranchTarget26, // user defined class 'BranchTarget26Operand'
    6083             :   MCK_CondCode, // user defined class 'CondCode'
    6084             :   MCK_Extend64, // user defined class 'ExtendOperand64'
    6085             :   MCK_ExtendLSL64, // user defined class 'ExtendOperandLSL64'
    6086             :   MCK_Extend, // user defined class 'ExtendOperand'
    6087             :   MCK_FPImm, // user defined class 'FPImmOperand'
    6088             :   MCK_GPR32as64, // user defined class 'GPR32as64Operand'
    6089             :   MCK_GPR64NoXZRshifted16, // user defined class 'GPR64NoXZRshiftedAsmOpnd16'
    6090             :   MCK_GPR64NoXZRshifted32, // user defined class 'GPR64NoXZRshiftedAsmOpnd32'
    6091             :   MCK_GPR64NoXZRshifted64, // user defined class 'GPR64NoXZRshiftedAsmOpnd64'
    6092             :   MCK_GPR64NoXZRshifted8, // user defined class 'GPR64NoXZRshiftedAsmOpnd8'
    6093             :   MCK_GPR64shifted16, // user defined class 'GPR64shiftedAsmOpnd16'
    6094             :   MCK_GPR64shifted32, // user defined class 'GPR64shiftedAsmOpnd32'
    6095             :   MCK_GPR64shifted64, // user defined class 'GPR64shiftedAsmOpnd64'
    6096             :   MCK_GPR64shifted8, // user defined class 'GPR64shiftedAsmOpnd8'
    6097             :   MCK_GPR64sp0, // user defined class 'GPR64spPlus0Operand'
    6098             :   MCK_Imm0_127, // user defined class 'Imm0_127Operand'
    6099             :   MCK_Imm0_15, // user defined class 'Imm0_15Operand'
    6100             :   MCK_Imm0_1, // user defined class 'Imm0_1Operand'
    6101             :   MCK_Imm0_255, // user defined class 'Imm0_255Operand'
    6102             :   MCK_Imm0_31, // user defined class 'Imm0_31Operand'
    6103             :   MCK_Imm0_63, // user defined class 'Imm0_63Operand'
    6104             :   MCK_Imm0_65535, // user defined class 'Imm0_65535Operand'
    6105             :   MCK_Imm0_7, // user defined class 'Imm0_7Operand'
    6106             :   MCK_Imm1_16, // user defined class 'Imm1_16Operand'
    6107             :   MCK_Imm1_32, // user defined class 'Imm1_32Operand'
    6108             :   MCK_Imm1_64, // user defined class 'Imm1_64Operand'
    6109             :   MCK_Imm1_8, // user defined class 'Imm1_8Operand'
    6110             :   MCK_Imm, // user defined class 'ImmAsmOperand'
    6111             :   MCK_LogicalImm32Not, // user defined class 'LogicalImm32NotOperand'
    6112             :   MCK_LogicalImm32, // user defined class 'LogicalImm32Operand'
    6113             :   MCK_LogicalImm64Not, // user defined class 'LogicalImm64NotOperand'
    6114             :   MCK_LogicalImm64, // user defined class 'LogicalImm64Operand'
    6115             :   MCK_MRSSystemRegister, // user defined class 'MRSSystemRegisterOperand'
    6116             :   MCK_MSRSystemRegister, // user defined class 'MSRSystemRegisterOperand'
    6117             :   MCK_MemWExtend128, // user defined class 'MemWExtend128Operand'
    6118             :   MCK_MemWExtend16, // user defined class 'MemWExtend16Operand'
    6119             :   MCK_MemWExtend32, // user defined class 'MemWExtend32Operand'
    6120             :   MCK_MemWExtend64, // user defined class 'MemWExtend64Operand'
    6121             :   MCK_MemWExtend8, // user defined class 'MemWExtend8Operand'
    6122             :   MCK_MemXExtend128, // user defined class 'MemXExtend128Operand'
    6123             :   MCK_MemXExtend16, // user defined class 'MemXExtend16Operand'
    6124             :   MCK_MemXExtend32, // user defined class 'MemXExtend32Operand'
    6125             :   MCK_MemXExtend64, // user defined class 'MemXExtend64Operand'
    6126             :   MCK_MemXExtend8, // user defined class 'MemXExtend8Operand'
    6127             :   MCK_MovKSymbolG0, // user defined class 'MovKSymbolG0AsmOperand'
    6128             :   MCK_MovKSymbolG1, // user defined class 'MovKSymbolG1AsmOperand'
    6129             :   MCK_MovKSymbolG2, // user defined class 'MovKSymbolG2AsmOperand'
    6130             :   MCK_MovKSymbolG3, // user defined class 'MovKSymbolG3AsmOperand'
    6131             :   MCK_MovZSymbolG0, // user defined class 'MovZSymbolG0AsmOperand'
    6132             :   MCK_MovZSymbolG1, // user defined class 'MovZSymbolG1AsmOperand'
    6133             :   MCK_MovZSymbolG2, // user defined class 'MovZSymbolG2AsmOperand'
    6134             :   MCK_MovZSymbolG3, // user defined class 'MovZSymbolG3AsmOperand'
    6135             :   MCK_PCRelLabel19, // user defined class 'PCRelLabel19Operand'
    6136             :   MCK_SVEPredicateHReg, // user defined class 'PPRAsmOp16'
    6137             :   MCK_SVEPredicateSReg, // user defined class 'PPRAsmOp32'
    6138             :   MCK_SVEPredicate3bHReg, // user defined class 'PPRAsmOp3b16'
    6139             :   MCK_SVEPredicate3bSReg, // user defined class 'PPRAsmOp3b32'
    6140             :   MCK_SVEPredicate3bDReg, // user defined class 'PPRAsmOp3b64'
    6141             :   MCK_SVEPredicate3bBReg, // user defined class 'PPRAsmOp3b8'
    6142             :   MCK_SVEPredicate3bAnyReg, // user defined class 'PPRAsmOp3bAny'
    6143             :   MCK_SVEPredicateDReg, // user defined class 'PPRAsmOp64'
    6144             :   MCK_SVEPredicateBReg, // user defined class 'PPRAsmOp8'
    6145             :   MCK_SVEPredicateAnyReg, // user defined class 'PPRAsmOpAny'
    6146             :   MCK_PSBHint, // user defined class 'PSBHintOperand'
    6147             :   MCK_Prefetch, // user defined class 'PrefetchOperand'
    6148             :   MCK_SIMDImmType10, // user defined class 'SIMDImmType10Operand'
    6149             :   MCK_SImm10s8, // user defined class 'SImm10s8Operand'
    6150             :   MCK_SImm4s16, // user defined class 'SImm4s16Operand'
    6151             :   MCK_SImm4s1, // user defined class 'SImm4s1Operand'
    6152             :   MCK_SImm4s2, // user defined class 'SImm4s2Operand'
    6153             :   MCK_SImm4s3, // user defined class 'SImm4s3Operand'
    6154             :   MCK_SImm4s4, // user defined class 'SImm4s4Operand'
    6155             :   MCK_SImm5, // user defined class 'SImm5Operand'
    6156             :   MCK_SImm6, // user defined class 'SImm6Operand'
    6157             :   MCK_SImm6s1, // user defined class 'SImm6s1Operand'
    6158             :   MCK_SImm7s16, // user defined class 'SImm7s16Operand'
    6159             :   MCK_SImm7s4, // user defined class 'SImm7s4Operand'
    6160             :   MCK_SImm7s8, // user defined class 'SImm7s8Operand'
    6161             :   MCK_SImm9OffsetFB128, // user defined class 'SImm9OffsetFB128Operand'
    6162             :   MCK_SImm9OffsetFB16, // user defined class 'SImm9OffsetFB16Operand'
    6163             :   MCK_SImm9OffsetFB32, // user defined class 'SImm9OffsetFB32Operand'
    6164             :   MCK_SImm9OffsetFB64, // user defined class 'SImm9OffsetFB64Operand'
    6165             :   MCK_SImm9OffsetFB8, // user defined class 'SImm9OffsetFB8Operand'
    6166             :   MCK_SImm9, // user defined class 'SImm9Operand'
    6167             :   MCK_SVEPattern, // user defined class 'SVEPatternOperand'
    6168             :   MCK_SVEPrefetch, // user defined class 'SVEPrefetchOperand'
    6169             :   MCK_LogicalVecHalfWordShifter, // user defined class 'LogicalVecHalfWordShifterOperand'
    6170             :   MCK_ArithmeticShifter32, // user defined class 'ArithmeticShifterOperand32'
    6171             :   MCK_ArithmeticShifter64, // user defined class 'ArithmeticShifterOperand64'
    6172             :   MCK_LogicalShifter32, // user defined class 'LogicalShifterOperand32'
    6173             :   MCK_LogicalShifter64, // user defined class 'LogicalShifterOperand64'
    6174             :   MCK_LogicalVecShifter, // user defined class 'LogicalVecShifterOperand'
    6175             :   MCK_MovImm32Shifter, // user defined class 'MovImm32ShifterOperand'
    6176             :   MCK_MovImm64Shifter, // user defined class 'MovImm64ShifterOperand'
    6177             :   MCK_MoveVecShifter, // user defined class 'MoveVecShifterOperand'
    6178             :   MCK_Shifter, // user defined class 'ShifterOperand'
    6179             :   MCK_SysCR, // user defined class 'SysCRAsmOperand'
    6180             :   MCK_SystemPStateFieldWithImm0_15, // user defined class 'SystemPStateFieldWithImm0_15Operand'
    6181             :   MCK_SystemPStateFieldWithImm0_1, // user defined class 'SystemPStateFieldWithImm0_1Operand'
    6182             :   MCK_TBZImm0_31, // user defined class 'TBZImm0_31Operand'
    6183             :   MCK_Imm32_63, // user defined class 'TBZImm32_63Operand'
    6184             :   MCK_UImm12Offset16, // user defined class 'UImm12OffsetScale16Operand'
    6185             :   MCK_UImm12Offset1, // user defined class 'UImm12OffsetScale1Operand'
    6186             :   MCK_UImm12Offset2, // user defined class 'UImm12OffsetScale2Operand'
    6187             :   MCK_UImm12Offset4, // user defined class 'UImm12OffsetScale4Operand'
    6188             :   MCK_UImm12Offset8, // user defined class 'UImm12OffsetScale8Operand'
    6189             :   MCK_UImm5s2, // user defined class 'UImm5s2Operand'
    6190             :   MCK_UImm5s4, // user defined class 'UImm5s4Operand'
    6191             :   MCK_UImm5s8, // user defined class 'UImm5s8Operand'
    6192             :   MCK_UImm6s1, // user defined class 'UImm6s1Operand'
    6193             :   MCK_UImm6s2, // user defined class 'UImm6s2Operand'
    6194             :   MCK_UImm6s4, // user defined class 'UImm6s4Operand'
    6195             :   MCK_UImm6s8, // user defined class 'UImm6s8Operand'
    6196             :   MCK_VecListFour128, // user defined class 'VecListFour_128AsmOperand'
    6197             :   MCK_TypedVectorList4_168, // user defined class 'VecListFour_16bAsmOperand'
    6198             :   MCK_TypedVectorList4_164, // user defined class 'VecListFour_1dAsmOperand'
    6199             :   MCK_TypedVectorList4_264, // user defined class 'VecListFour_2dAsmOperand'
    6200             :   MCK_TypedVectorList4_232, // user defined class 'VecListFour_2sAsmOperand'
    6201             :   MCK_TypedVectorList4_416, // user defined class 'VecListFour_4hAsmOperand'
    6202             :   MCK_TypedVectorList4_432, // user defined class 'VecListFour_4sAsmOperand'
    6203             :   MCK_VecListFour64, // user defined class 'VecListFour_64AsmOperand'
    6204             :   MCK_TypedVectorList4_88, // user defined class 'VecListFour_8bAsmOperand'
    6205             :   MCK_TypedVectorList4_816, // user defined class 'VecListFour_8hAsmOperand'
    6206             :   MCK_TypedVectorList4_08, // user defined class 'VecListFour_bAsmOperand'
    6207             :   MCK_TypedVectorList4_064, // user defined class 'VecListFour_dAsmOperand'
    6208             :   MCK_TypedVectorList4_016, // user defined class 'VecListFour_hAsmOperand'
    6209             :   MCK_TypedVectorList4_032, // user defined class 'VecListFour_sAsmOperand'
    6210             :   MCK_VecListOne128, // user defined class 'VecListOne_128AsmOperand'
    6211             :   MCK_TypedVectorList1_168, // user defined class 'VecListOne_16bAsmOperand'
    6212             :   MCK_TypedVectorList1_164, // user defined class 'VecListOne_1dAsmOperand'
    6213             :   MCK_TypedVectorList1_264, // user defined class 'VecListOne_2dAsmOperand'
    6214             :   MCK_TypedVectorList1_232, // user defined class 'VecListOne_2sAsmOperand'
    6215             :   MCK_TypedVectorList1_416, // user defined class 'VecListOne_4hAsmOperand'
    6216             :   MCK_TypedVectorList1_432, // user defined class 'VecListOne_4sAsmOperand'
    6217             :   MCK_VecListOne64, // user defined class 'VecListOne_64AsmOperand'
    6218             :   MCK_TypedVectorList1_88, // user defined class 'VecListOne_8bAsmOperand'
    6219             :   MCK_TypedVectorList1_816, // user defined class 'VecListOne_8hAsmOperand'
    6220             :   MCK_TypedVectorList1_08, // user defined class 'VecListOne_bAsmOperand'
    6221             :   MCK_TypedVectorList1_064, // user defined class 'VecListOne_dAsmOperand'
    6222             :   MCK_TypedVectorList1_016, // user defined class 'VecListOne_hAsmOperand'
    6223             :   MCK_TypedVectorList1_032, // user defined class 'VecListOne_sAsmOperand'
    6224             :   MCK_VecListThree128, // user defined class 'VecListThree_128AsmOperand'
    6225             :   MCK_TypedVectorList3_168, // user defined class 'VecListThree_16bAsmOperand'
    6226             :   MCK_TypedVectorList3_164, // user defined class 'VecListThree_1dAsmOperand'
    6227             :   MCK_TypedVectorList3_264, // user defined class 'VecListThree_2dAsmOperand'
    6228             :   MCK_TypedVectorList3_232, // user defined class 'VecListThree_2sAsmOperand'
    6229             :   MCK_TypedVectorList3_416, // user defined class 'VecListThree_4hAsmOperand'
    6230             :   MCK_TypedVectorList3_432, // user defined class 'VecListThree_4sAsmOperand'
    6231             :   MCK_VecListThree64, // user defined class 'VecListThree_64AsmOperand'
    6232             :   MCK_TypedVectorList3_88, // user defined class 'VecListThree_8bAsmOperand'
    6233             :   MCK_TypedVectorList3_816, // user defined class 'VecListThree_8hAsmOperand'
    6234             :   MCK_TypedVectorList3_08, // user defined class 'VecListThree_bAsmOperand'
    6235             :   MCK_TypedVectorList3_064, // user defined class 'VecListThree_dAsmOperand'
    6236             :   MCK_TypedVectorList3_016, // user defined class 'VecListThree_hAsmOperand'
    6237             :   MCK_TypedVectorList3_032, // user defined class 'VecListThree_sAsmOperand'
    6238             :   MCK_VecListTwo128, // user defined class 'VecListTwo_128AsmOperand'
    6239             :   MCK_TypedVectorList2_168, // user defined class 'VecListTwo_16bAsmOperand'
    6240             :   MCK_TypedVectorList2_164, // user defined class 'VecListTwo_1dAsmOperand'
    6241             :   MCK_TypedVectorList2_264, // user defined class 'VecListTwo_2dAsmOperand'
    6242             :   MCK_TypedVectorList2_232, // user defined class 'VecListTwo_2sAsmOperand'
    6243             :   MCK_TypedVectorList2_416, // user defined class 'VecListTwo_4hAsmOperand'
    6244             :   MCK_TypedVectorList2_432, // user defined class 'VecListTwo_4sAsmOperand'
    6245             :   MCK_VecListTwo64, // user defined class 'VecListTwo_64AsmOperand'
    6246             :   MCK_TypedVectorList2_88, // user defined class 'VecListTwo_8bAsmOperand'
    6247             :   MCK_TypedVectorList2_816, // user defined class 'VecListTwo_8hAsmOperand'
    6248             :   MCK_TypedVectorList2_08, // user defined class 'VecListTwo_bAsmOperand'
    6249             :   MCK_TypedVectorList2_064, // user defined class 'VecListTwo_dAsmOperand'
    6250             :   MCK_TypedVectorList2_016, // user defined class 'VecListTwo_hAsmOperand'
    6251             :   MCK_TypedVectorList2_032, // user defined class 'VecListTwo_sAsmOperand'
    6252             :   MCK_VectorIndex1, // user defined class 'VectorIndex1Operand'
    6253             :   MCK_VectorIndexB, // user defined class 'VectorIndexBOperand'
    6254             :   MCK_VectorIndexD, // user defined class 'VectorIndexDOperand'
    6255             :   MCK_VectorIndexH, // user defined class 'VectorIndexHOperand'
    6256             :   MCK_VectorIndexS, // user defined class 'VectorIndexSOperand'
    6257             :   MCK_VectorReg128, // user defined class 'VectorReg128AsmOperand'
    6258             :   MCK_VectorReg64, // user defined class 'VectorReg64AsmOperand'
    6259             :   MCK_VectorRegLo, // user defined class 'VectorRegLoAsmOperand'
    6260             :   MCK_WSeqPair, // user defined class 'WSeqPairsAsmOperandClass'
    6261             :   MCK_XSeqPair, // user defined class 'XSeqPairsAsmOperandClass'
    6262             :   MCK_ZPRExtendSXTW3216, // user defined class 'ZPR32AsmOpndExtSXTW16'
    6263             :   MCK_ZPRExtendSXTW3232, // user defined class 'ZPR32AsmOpndExtSXTW32'
    6264             :   MCK_ZPRExtendSXTW3264, // user defined class 'ZPR32AsmOpndExtSXTW64'
    6265             :   MCK_ZPRExtendSXTW328, // user defined class 'ZPR32AsmOpndExtSXTW8'
    6266             :   MCK_ZPRExtendSXTW328Only, // user defined class 'ZPR32AsmOpndExtSXTW8Only'
    6267             :   MCK_ZPRExtendUXTW3216, // user defined class 'ZPR32AsmOpndExtUXTW16'
    6268             :   MCK_ZPRExtendUXTW3232, // user defined class 'ZPR32AsmOpndExtUXTW32'
    6269             :   MCK_ZPRExtendUXTW3264, // user defined class 'ZPR32AsmOpndExtUXTW64'
    6270             :   MCK_ZPRExtendUXTW328, // user defined class 'ZPR32AsmOpndExtUXTW8'
    6271             :   MCK_ZPRExtendUXTW328Only, // user defined class 'ZPR32AsmOpndExtUXTW8Only'
    6272             :   MCK_ZPRExtendLSL6416, // user defined class 'ZPR64AsmOpndExtLSL16'
    6273             :   MCK_ZPRExtendLSL6432, // user defined class 'ZPR64AsmOpndExtLSL32'
    6274             :   MCK_ZPRExtendLSL6464, // user defined class 'ZPR64AsmOpndExtLSL64'
    6275             :   MCK_ZPRExtendLSL648, // user defined class 'ZPR64AsmOpndExtLSL8'
    6276             :   MCK_ZPRExtendSXTW6416, // user defined class 'ZPR64AsmOpndExtSXTW16'
    6277             :   MCK_ZPRExtendSXTW6432, // user defined class 'ZPR64AsmOpndExtSXTW32'
    6278             :   MCK_ZPRExtendSXTW6464, // user defined class 'ZPR64AsmOpndExtSXTW64'
    6279             :   MCK_ZPRExtendSXTW648, // user defined class 'ZPR64AsmOpndExtSXTW8'
    6280             :   MCK_ZPRExtendSXTW648Only, // user defined class 'ZPR64AsmOpndExtSXTW8Only'
    6281             :   MCK_ZPRExtendUXTW6416, // user defined class 'ZPR64AsmOpndExtUXTW16'
    6282             :   MCK_ZPRExtendUXTW6432, // user defined class 'ZPR64AsmOpndExtUXTW32'
    6283             :   MCK_ZPRExtendUXTW6464, // user defined class 'ZPR64AsmOpndExtUXTW64'
    6284             :   MCK_ZPRExtendUXTW648, // user defined class 'ZPR64AsmOpndExtUXTW8'
    6285             :   MCK_ZPRExtendUXTW648Only, // user defined class 'ZPR64AsmOpndExtUXTW8Only'
    6286             :   MCK_SVEVectorQReg, // user defined class 'ZPRAsmOp128'
    6287             :   MCK_SVEVectorHReg, // user defined class 'ZPRAsmOp16'
    6288             :   MCK_SVEVectorSReg, // user defined class 'ZPRAsmOp32'
    6289             :   MCK_SVEVectorDReg, // user defined class 'ZPRAsmOp64'
    6290             :   MCK_SVEVectorBReg, // user defined class 'ZPRAsmOp8'
    6291             :   MCK_SVEVectorAnyReg, // user defined class 'ZPRAsmOpAny'
    6292             :   MCK_ComplexRotationEven, // user defined class 'anonymous_1287'
    6293             :   MCK_ComplexRotationOdd, // user defined class 'anonymous_1288'
    6294             :   MCK_SVELogicalImm8, // user defined class 'anonymous_1338'
    6295             :   MCK_SVELogicalImm16, // user defined class 'anonymous_1339'
    6296             :   MCK_SVELogicalImm32, // user defined class 'anonymous_1340'
    6297             :   MCK_SVELogicalImm8Not, // user defined class 'anonymous_1341'
    6298             :   MCK_SVELogicalImm16Not, // user defined class 'anonymous_1342'
    6299             :   MCK_SVELogicalImm32Not, // user defined class 'anonymous_1343'
    6300             :   MCK_MOVZ32_lsl0MovAlias, // user defined class 'anonymous_1460_asmoperand'
    6301             :   MCK_MOVZ32_lsl16MovAlias, // user defined class 'anonymous_1461_asmoperand'
    6302             :   MCK_MOVZ64_lsl0MovAlias, // user defined class 'anonymous_1462_asmoperand'
    6303             :   MCK_MOVZ64_lsl16MovAlias, // user defined class 'anonymous_1463_asmoperand'
    6304             :   MCK_MOVZ64_lsl32MovAlias, // user defined class 'anonymous_1464_asmoperand'
    6305             :   MCK_MOVZ64_lsl48MovAlias, // user defined class 'anonymous_1465_asmoperand'
    6306             :   MCK_MOVN32_lsl0MovAlias, // user defined class 'anonymous_1466_asmoperand'
    6307             :   MCK_MOVN32_lsl16MovAlias, // user defined class 'anonymous_1467_asmoperand'
    6308             :   MCK_MOVN64_lsl0MovAlias, // user defined class 'anonymous_1468_asmoperand'
    6309             :   MCK_MOVN64_lsl16MovAlias, // user defined class 'anonymous_1469_asmoperand'
    6310             :   MCK_MOVN64_lsl32MovAlias, // user defined class 'anonymous_1470_asmoperand'
    6311             :   MCK_MOVN64_lsl48MovAlias, // user defined class 'anonymous_1471_asmoperand'
    6312             :   MCK_FPRAsmOperandFPR8, // user defined class 'anonymous_938'
    6313             :   MCK_FPRAsmOperandFPR16, // user defined class 'anonymous_939'
    6314             :   MCK_FPRAsmOperandFPR32, // user defined class 'anonymous_940'
    6315             :   MCK_FPRAsmOperandFPR64, // user defined class 'anonymous_941'
    6316             :   MCK_FPRAsmOperandFPR128, // user defined class 'anonymous_942'
    6317             :   MCK_SVEVectorList18, // user defined class 'anonymous_943'
    6318             :   MCK_SVEVectorList116, // user defined class 'anonymous_944'
    6319             :   MCK_SVEVectorList132, // user defined class 'anonymous_945'
    6320             :   MCK_SVEVectorList164, // user defined class 'anonymous_946'
    6321             :   MCK_SVEVectorList28, // user defined class 'anonymous_947'
    6322             :   MCK_SVEVectorList216, // user defined class 'anonymous_948'
    6323             :   MCK_SVEVectorList232, // user defined class 'anonymous_949'
    6324             :   MCK_SVEVectorList264, // user defined class 'anonymous_950'
    6325             :   MCK_SVEVectorList38, // user defined class 'anonymous_951'
    6326             :   MCK_SVEVectorList316, // user defined class 'anonymous_952'
    6327             :   MCK_SVEVectorList332, // user defined class 'anonymous_953'
    6328             :   MCK_SVEVectorList364, // user defined class 'anonymous_954'
    6329             :   MCK_SVEVectorList48, // user defined class 'anonymous_955'
    6330             :   MCK_SVEVectorList416, // user defined class 'anonymous_956'
    6331             :   MCK_SVEVectorList432, // user defined class 'anonymous_957'
    6332             :   MCK_SVEVectorList464, // user defined class 'anonymous_958'
    6333             :   NumMatchClassKinds
    6334             : };
    6335             : 
    6336             : }
    6337             : 
    6338             : static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
    6339             :   return MCTargetAsmParser::Match_InvalidOperand;
    6340             : }
    6341             : 
    6342      132002 : static MatchClassKind matchTokenString(StringRef Name) {
    6343      132002 :   switch (Name.size()) {
    6344             :   default: break;
    6345       86986 :   case 1:        // 7 strings to match.
    6346       86986 :     switch (Name[0]) {
    6347             :     default: break;
    6348             :     case '!':    // 1 string to match.
    6349             :       return MCK__EXCLAIM_;      // "!"
    6350         102 :     case '.':    // 1 string to match.
    6351         102 :       return MCK__DOT_;  // "."
    6352       16890 :     case '/':    // 1 string to match.
    6353       16890 :       return MCK__47_;   // "/"
    6354       42578 :     case '[':    // 1 string to match.
    6355       42578 :       return MCK__91_;   // "["
    6356       10404 :     case ']':    // 1 string to match.
    6357       10404 :       return MCK__93_;   // "]"
    6358         176 :     case 'm':    // 1 string to match.
    6359         176 :       return MCK_m;      // "m"
    6360       16696 :     case 'z':    // 1 string to match.
    6361       16696 :       return MCK_z;      // "z"
    6362             :     }
    6363             :     break;
    6364        7217 :   case 2:        // 19 strings to match.
    6365        7217 :     switch (Name[0]) {
    6366             :     default: break;
    6367         234 :     case '#':    // 7 strings to match.
    6368         234 :       switch (Name[1]) {
    6369             :       default: break;
    6370             :       case '0':  // 1 string to match.
    6371             :         return MCK__35_0;        // "#0"
    6372             :       case '1':  // 1 string to match.
    6373             :         return MCK__35_1;        // "#1"
    6374             :       case '2':  // 1 string to match.
    6375             :         return MCK__35_2;        // "#2"
    6376             :       case '3':  // 1 string to match.
    6377             :         return MCK__35_3;        // "#3"
    6378             :       case '4':  // 1 string to match.
    6379             :         return MCK__35_4;        // "#4"
    6380             :       case '6':  // 1 string to match.
    6381             :         return MCK__35_6;        // "#6"
    6382             :       case '8':  // 1 string to match.
    6383             :         return MCK__35_8;        // "#8"
    6384             :       }
    6385             :       break;
    6386        6163 :     case '.':    // 11 strings to match.
    6387        6163 :       switch (Name[1]) {
    6388             :       default: break;
    6389             :       case '0':  // 1 string to match.
    6390             :         return MCK__DOT_0;       // ".0"
    6391             :       case 'B':  // 1 string to match.
    6392             :         return MCK__DOT_B;       // ".B"
    6393             :       case 'D':  // 1 string to match.
    6394             :         return MCK__DOT_D;       // ".D"
    6395             :       case 'H':  // 1 string to match.
    6396             :         return MCK__DOT_H;       // ".H"
    6397             :       case 'Q':  // 1 string to match.
    6398             :         return MCK__DOT_Q;       // ".Q"
    6399             :       case 'S':  // 1 string to match.
    6400             :         return MCK__DOT_S;       // ".S"
    6401             :       case 'b':  // 1 string to match.
    6402             :         return MCK__DOT_b;       // ".b"
    6403             :       case 'd':  // 1 string to match.
    6404             :         return MCK__DOT_d;       // ".d"
    6405             :       case 'h':  // 1 string to match.
    6406             :         return MCK__DOT_h;       // ".h"
    6407             :       case 'q':  // 1 string to match.
    6408             :         return MCK__DOT_q;       // ".q"
    6409             :       case 's':  // 1 string to match.
    6410             :         return MCK__DOT_s;       // ".s"
    6411             :       }
    6412             :       break;
    6413         820 :     case 'v':    // 1 string to match.
    6414         820 :       if (Name[1] != 'l')
    6415             :         break;
    6416             :       return MCK_vl;     // "vl"
    6417             :     }
    6418             :     break;
    6419       35610 :   case 3:        // 27 strings to match.
    6420       35610 :     switch (Name[0]) {
    6421             :     default: break;
    6422           0 :     case '#':    // 6 strings to match.
    6423           0 :       switch (Name[1]) {
    6424             :       default: break;
    6425           0 :       case '1':  // 2 strings to match.
    6426           0 :         switch (Name[2]) {
    6427             :         default: break;
    6428             :         case '2':        // 1 string to match.
    6429             :           return MCK__35_12;     // "#12"
    6430           0 :         case '6':        // 1 string to match.
    6431           0 :           return MCK__35_16;     // "#16"
    6432             :         }
    6433             :         break;
    6434           0 :       case '2':  // 1 string to match.
    6435           0 :         if (Name[2] != '4')
    6436             :           break;
    6437             :         return MCK__35_24;       // "#24"
    6438           0 :       case '3':  // 1 string to match.
    6439           0 :         if (Name[2] != '2')
    6440             :           break;
    6441             :         return MCK__35_32;       // "#32"
    6442           0 :       case '4':  // 1 string to match.
    6443           0 :         if (Name[2] != '8')
    6444             :           break;
    6445             :         return MCK__35_48;       // "#48"
    6446           0 :       case '6':  // 1 string to match.
    6447           0 :         if (Name[2] != '4')
    6448             :           break;
    6449             :         return MCK__35_64;       // "#64"
    6450             :       }
    6451             :       break;
    6452       34782 :     case '.':    // 20 strings to match.
    6453       34782 :       switch (Name[1]) {
    6454             :       default: break;
    6455        1021 :       case '1':  // 4 strings to match.
    6456        1021 :         switch (Name[2]) {
    6457             :         default: break;
    6458             :         case 'D':        // 1 string to match.
    6459             :           return MCK__DOT_1D;    // ".1D"
    6460           2 :         case 'Q':        // 1 string to match.
    6461           2 :           return MCK__DOT_1Q;    // ".1Q"
    6462        1003 :         case 'd':        // 1 string to match.
    6463        1003 :           return MCK__DOT_1d;    // ".1d"
    6464          14 :         case 'q':        // 1 string to match.
    6465          14 :           return MCK__DOT_1q;    // ".1q"
    6466             :         }
    6467             :         break;
    6468        8925 :       case '2':  // 6 strings to match.
    6469        8925 :         switch (Name[2]) {
    6470             :         default: break;
    6471             :         case 'D':        // 1 string to match.
    6472             :           return MCK__DOT_2D;    // ".2D"
    6473             :         case 'H':        // 1 string to match.
    6474             :           return MCK__DOT_2H;    // ".2H"
    6475             :         case 'S':        // 1 string to match.
    6476             :           return MCK__DOT_2S;    // ".2S"
    6477             :         case 'd':        // 1 string to match.
    6478             :           return MCK__DOT_2d;    // ".2d"
    6479             :         case 'h':        // 1 string to match.
    6480             :           return MCK__DOT_2h;    // ".2h"
    6481             :         case 's':        // 1 string to match.
    6482             :           return MCK__DOT_2s;    // ".2s"
    6483             :         }
    6484             :         break;
    6485       12396 :       case '4':  // 6 strings to match.
    6486       12396 :         switch (Name[2]) {
    6487             :         default: break;
    6488             :         case 'B':        // 1 string to match.
    6489             :           return MCK__DOT_4B;    // ".4B"
    6490           0 :         case 'H':        // 1 string to match.
    6491           0 :           return MCK__DOT_4H;    // ".4H"
    6492          13 :         case 'S':        // 1 string to match.
    6493          13 :           return MCK__DOT_4S;    // ".4S"
    6494          52 :         case 'b':        // 1 string to match.
    6495          52 :           return MCK__DOT_4b;    // ".4b"
    6496        6467 :         case 'h':        // 1 string to match.
    6497        6467 :           return MCK__DOT_4h;    // ".4h"
    6498        5848 :         case 's':        // 1 string to match.
    6499        5848 :           return MCK__DOT_4s;    // ".4s"
    6500             :         }
    6501             :         break;
    6502       12224 :       case '8':  // 4 strings to match.
    6503       12224 :         switch (Name[2]) {
    6504             :         default: break;
    6505             :         case 'B':        // 1 string to match.
    6506             :           return MCK__DOT_8B;    // ".8B"
    6507           4 :         case 'H':        // 1 string to match.
    6508           4 :           return MCK__DOT_8H;    // ".8H"
    6509        4919 :         case 'b':        // 1 string to match.
    6510        4919 :           return MCK__DOT_8b;    // ".8b"
    6511        7280 :         case 'h':        // 1 string to match.
    6512        7280 :           return MCK__DOT_8h;    // ".8h"
    6513             :         }
    6514             :         break;
    6515             :       }
    6516             :       break;
    6517             :     case 'm':    // 1 string to match.
    6518         828 :       if (memcmp(Name.data()+1, "ul", 2) != 0)
    6519             :         break;
    6520             :       return MCK_mul;    // "mul"
    6521             :     }
    6522             :     break;
    6523             :   case 4:        // 2 strings to match.
    6524        2189 :     if (memcmp(Name.data()+0, ".16", 3) != 0)
    6525             :       break;
    6526        2189 :     switch (Name[3]) {
    6527             :     default: break;
    6528             :     case 'B':    // 1 string to match.
    6529             :       return MCK__DOT_16B;       // ".16B"
    6530        2174 :     case 'b':    // 1 string to match.
    6531        2174 :       return MCK__DOT_16b;       // ".16b"
    6532             :     }
    6533             :     break;
    6534             :   }
    6535             :   return InvalidMatchClass;
    6536             : }
    6537             : 
    6538             : /// isSubclass - Compute whether \p A is a subclass of \p B.
    6539      698979 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
    6540      698979 :   if (A == B)
    6541             :     return true;
    6542             : 
    6543      592799 :   switch (A) {
    6544             :   default:
    6545             :     return false;
    6546             : 
    6547          15 :   case MCK__DOT_16B:
    6548          15 :     return B == MCK__DOT_16b;
    6549             : 
    6550           2 :   case MCK__DOT_1D:
    6551           2 :     return B == MCK__DOT_1d;
    6552             : 
    6553           2 :   case MCK__DOT_1Q:
    6554           2 :     return B == MCK__DOT_1q;
    6555             : 
    6556           8 :   case MCK__DOT_2D:
    6557           8 :     return B == MCK__DOT_2d;
    6558             : 
    6559           1 :   case MCK__DOT_2H:
    6560           1 :     return B == MCK__DOT_2h;
    6561             : 
    6562          16 :   case MCK__DOT_2S:
    6563          16 :     return B == MCK__DOT_2s;
    6564             : 
    6565          16 :   case MCK__DOT_4B:
    6566          16 :     return B == MCK__DOT_4b;
    6567             : 
    6568           0 :   case MCK__DOT_4H:
    6569           0 :     return B == MCK__DOT_4h;
    6570             : 
    6571          13 :   case MCK__DOT_4S:
    6572          13 :     return B == MCK__DOT_4s;
    6573             : 
    6574          21 :   case MCK__DOT_8B:
    6575          21 :     return B == MCK__DOT_8b;
    6576             : 
    6577           4 :   case MCK__DOT_8H:
    6578           4 :     return B == MCK__DOT_8h;
    6579             : 
    6580           0 :   case MCK__DOT_B:
    6581           0 :     return B == MCK__DOT_b;
    6582             : 
    6583           0 :   case MCK__DOT_D:
    6584           0 :     return B == MCK__DOT_d;
    6585             : 
    6586           0 :   case MCK__DOT_H:
    6587           0 :     return B == MCK__DOT_h;
    6588             : 
    6589           0 :   case MCK__DOT_Q:
    6590           0 :     return B == MCK__DOT_q;
    6591             : 
    6592           0 :   case MCK__DOT_S:
    6593           0 :     return B == MCK__DOT_s;
    6594             : 
    6595        2830 :   case MCK_GPR32sponly:
    6596        2830 :     switch (B) {
    6597             :     default: return false;
    6598         155 :     case MCK_GPR32sp: return true;
    6599           0 :     case MCK_GPR32all: return true;
    6600             :     }
    6601             : 
    6602        8276 :   case MCK_GPR64sponly:
    6603        8276 :     switch (B) {
    6604             :     default: return false;
    6605        4513 :     case MCK_GPR64sp: return true;
    6606           0 :     case MCK_GPR64all: return true;
    6607             :     }
    6608             : 
    6609        2112 :   case MCK_PPR_3b:
    6610        2112 :     return B == MCK_PPR;
    6611             : 
    6612           0 :   case MCK_Reg29:
    6613             :     switch (B) {
    6614             :     default: return false;
    6615             :     case MCK_Reg30: return true;
    6616             :     case MCK_Reg39: return true;
    6617             :     case MCK_Reg31: return true;
    6618             :     case MCK_Reg36: return true;
    6619             :     case MCK_Reg38: return true;
    6620             :     case MCK_Reg32: return true;
    6621             :     case MCK_Reg34: return true;
    6622             :     case MCK_Reg35: return true;
    6623             :     case MCK_Reg37: return true;
    6624             :     case MCK_QQQQ: return true;
    6625             :     }
    6626             : 
    6627           0 :   case MCK_Reg62:
    6628             :     switch (B) {
    6629             :     default: return false;
    6630             :     case MCK_Reg63: return true;
    6631             :     case MCK_Reg72: return true;
    6632             :     case MCK_Reg64: return true;
    6633             :     case MCK_Reg69: return true;
    6634             :     case MCK_Reg71: return true;
    6635             :     case MCK_Reg65: return true;
    6636             :     case MCK_Reg67: return true;
    6637             :     case MCK_Reg68: return true;
    6638             :     case MCK_Reg70: return true;
    6639             :     case MCK_ZPR4: return true;
    6640             :     }
    6641             : 
    6642           0 :   case MCK_Reg30:
    6643           0 :     switch (B) {
    6644             :     default: return false;
    6645           0 :     case MCK_Reg31: return true;
    6646           0 :     case MCK_Reg36: return true;
    6647           0 :     case MCK_Reg32: return true;
    6648           0 :     case MCK_Reg34: return true;
    6649           0 :     case MCK_Reg35: return true;
    6650           0 :     case MCK_QQQQ: return true;
    6651             :     }
    6652             : 
    6653           0 :   case MCK_Reg39:
    6654           0 :     switch (B) {
    6655             :     default: return false;
    6656           0 :     case MCK_Reg36: return true;
    6657           0 :     case MCK_Reg38: return true;
    6658           0 :     case MCK_Reg34: return true;
    6659           0 :     case MCK_Reg35: return true;
    6660           0 :     case MCK_Reg37: return true;
    6661           0 :     case MCK_QQQQ: return true;
    6662             :     }
    6663             : 
    6664           0 :   case MCK_Reg40:
    6665           0 :     switch (B) {
    6666             :     default: return false;
    6667           0 :     case MCK_Reg41: return true;
    6668           0 :     case MCK_Reg46: return true;
    6669           0 :     case MCK_Reg42: return true;
    6670           0 :     case MCK_Reg44: return true;
    6671           0 :     case MCK_Reg45: return true;
    6672           0 :     case MCK_QQQ: return true;
    6673             :     }
    6674             : 
    6675           0 :   case MCK_Reg63:
    6676           0 :     switch (B) {
    6677             :     default: return false;
    6678           0 :     case MCK_Reg64: return true;
    6679           0 :     case MCK_Reg69: return true;
    6680           0 :     case MCK_Reg65: return true;
    6681           0 :     case MCK_Reg67: return true;
    6682           0 :     case MCK_Reg68: return true;
    6683           0 :     case MCK_ZPR4: return true;
    6684             :     }
    6685             : 
    6686           0 :   case MCK_Reg72:
    6687           0 :     switch (B) {
    6688             :     default: return false;
    6689           0 :     case MCK_Reg69: return true;
    6690           0 :     case MCK_Reg71: return true;
    6691           0 :     case MCK_Reg67: return true;
    6692           0 :     case MCK_Reg68: return true;
    6693           0 :     case MCK_Reg70: return true;
    6694           0 :     case MCK_ZPR4: return true;
    6695             :     }
    6696             : 
    6697           0 :   case MCK_Reg73:
    6698           0 :     switch (B) {
    6699             :     default: return false;
    6700           0 :     case MCK_Reg74: return true;
    6701           0 :     case MCK_Reg79: return true;
    6702           0 :     case MCK_Reg75: return true;
    6703           0 :     case MCK_Reg77: return true;
    6704           0 :     case MCK_Reg78: return true;
    6705           0 :     case MCK_ZPR3: return true;
    6706             :     }
    6707             : 
    6708           0 :   case MCK_Reg25:
    6709           0 :     switch (B) {
    6710             :     default: return false;
    6711           0 :     case MCK_Reg26: return true;
    6712           0 :     case MCK_Reg28: return true;
    6713           0 :     case MCK_QQ: return true;
    6714             :     }
    6715             : 
    6716           0 :   case MCK_Reg31:
    6717           0 :     switch (B) {
    6718             :     default: return false;
    6719           0 :     case MCK_Reg32: return true;
    6720           0 :     case MCK_Reg34: return true;
    6721           0 :     case MCK_QQQQ: return true;
    6722             :     }
    6723             : 
    6724           0 :   case MCK_Reg36:
    6725           0 :     switch (B) {
    6726             :     default: return false;
    6727           0 :     case MCK_Reg34: return true;
    6728           0 :     case MCK_Reg35: return true;
    6729           0 :     case MCK_QQQQ: return true;
    6730             :     }
    6731             : 
    6732           0 :   case MCK_Reg38:
    6733           0 :     switch (B) {
    6734             :     default: return false;
    6735           0 :     case MCK_Reg35: return true;
    6736           0 :     case MCK_Reg37: return true;
    6737           0 :     case MCK_QQQQ: return true;
    6738             :     }
    6739             : 
    6740           0 :   case MCK_Reg41:
    6741           0 :     switch (B) {
    6742             :     default: return false;
    6743           0 :     case MCK_Reg42: return true;
    6744           0 :     case MCK_Reg44: return true;
    6745           0 :     case MCK_QQQ: return true;
    6746             :     }
    6747             : 
    6748           0 :   case MCK_Reg46:
    6749           0 :     switch (B) {
    6750             :     default: return false;
    6751           0 :     case MCK_Reg44: return true;
    6752           0 :     case MCK_Reg45: return true;
    6753           0 :     case MCK_QQQ: return true;
    6754             :     }
    6755             : 
    6756           0 :   case MCK_Reg58:
    6757           0 :     switch (B) {
    6758             :     default: return false;
    6759           0 :     case MCK_Reg59: return true;
    6760           0 :     case MCK_Reg61: return true;
    6761           0 :     case MCK_ZPR2: return true;
    6762             :     }
    6763             : 
    6764           0 :   case MCK_Reg64:
    6765           0 :     switch (B) {
    6766             :     default: return false;
    6767           0 :     case MCK_Reg65: return true;
    6768           0 :     case MCK_Reg67: return true;
    6769           0 :     case MCK_ZPR4: return true;
    6770             :     }
    6771             : 
    6772           0 :   case MCK_Reg69:
    6773           0 :     switch (B) {
    6774             :     default: return false;
    6775           0 :     case MCK_Reg67: return true;
    6776           0 :     case MCK_Reg68: return true;
    6777           0 :     case MCK_ZPR4: return true;
    6778             :     }
    6779             : 
    6780           0 :   case MCK_Reg71:
    6781           0 :     switch (B) {
    6782             :     default: return false;
    6783           0 :     case MCK_Reg68: return true;
    6784           0 :     case MCK_Reg70: return true;
    6785           0 :     case MCK_ZPR4: return true;
    6786             :     }
    6787             : 
    6788           0 :   case MCK_Reg74:
    6789           0 :     switch (B) {
    6790             :     default: return false;
    6791           0 :     case MCK_Reg75: return true;
    6792           0 :     case MCK_Reg77: return true;
    6793           0 :     case MCK_ZPR3: return true;
    6794             :     }
    6795             : 
    6796           0 :   case MCK_Reg79:
    6797           0 :     switch (B) {
    6798             :     default: return false;
    6799           0 :     case MCK_Reg77: return true;
    6800           0 :     case MCK_Reg78: return true;
    6801           0 :     case MCK_ZPR3: return true;
    6802             :     }
    6803             : 
    6804       26515 :   case MCK_Reg20:
    6805       26515 :     return B == MCK_ZPR;
    6806             : 
    6807           0 :   case MCK_Reg26:
    6808           0 :     return B == MCK_QQ;
    6809             : 
    6810           0 :   case MCK_Reg28:
    6811           0 :     return B == MCK_QQ;
    6812             : 
    6813           0 :   case MCK_Reg32:
    6814           0 :     return B == MCK_QQQQ;
    6815             : 
    6816           0 :   case MCK_Reg34:
    6817           0 :     return B == MCK_QQQQ;
    6818             : 
    6819           0 :   case MCK_Reg35:
    6820           0 :     return B == MCK_QQQQ;
    6821             : 
    6822           0 :   case MCK_Reg37:
    6823           0 :     return B == MCK_QQQQ;
    6824             : 
    6825           0 :   case MCK_Reg42:
    6826           0 :     return B == MCK_QQQ;
    6827             : 
    6828           0 :   case MCK_Reg44:
    6829           0 :     return B == MCK_QQQ;
    6830             : 
    6831           0 :   case MCK_Reg45:
    6832           0 :     return B == MCK_QQQ;
    6833             : 
    6834           0 :   case MCK_Reg59:
    6835           0 :     return B == MCK_ZPR2;
    6836             : 
    6837           0 :   case MCK_Reg61:
    6838           0 :     return B == MCK_ZPR2;
    6839             : 
    6840           0 :   case MCK_Reg65:
    6841           0 :     return B == MCK_ZPR4;
    6842             : 
    6843           0 :   case MCK_Reg67:
    6844           0 :     return B == MCK_ZPR4;
    6845             : 
    6846           0 :   case MCK_Reg68:
    6847           0 :     return B == MCK_ZPR4;
    6848             : 
    6849           0 :   case MCK_Reg70:
    6850           0 :     return B == MCK_ZPR4;
    6851             : 
    6852           0 :   case MCK_Reg75:
    6853           0 :     return B == MCK_ZPR3;
    6854             : 
    6855           0 :   case MCK_Reg77:
    6856           0 :     return B == MCK_ZPR3;
    6857             : 
    6858           0 :   case MCK_Reg78:
    6859           0 :     return B == MCK_ZPR3;
    6860             : 
    6861       43578 :   case MCK_FPR128_lo:
    6862       43578 :     return B == MCK_FPR128;
    6863             : 
    6864          27 :   case MCK_Reg51:
    6865             :     switch (B) {
    6866             :     default: return false;
    6867             :     case MCK_Reg52: return true;
    6868             :     case MCK_Reg57: return true;
    6869             :     case MCK_Reg53: return true;
    6870             :     case MCK_Reg54: return true;
    6871             :     case MCK_Reg56: return true;
    6872             :     case MCK_XSeqPairsClass: return true;
    6873             :     }
    6874             : 
    6875           0 :   case MCK_Reg52:
    6876             :     switch (B) {
    6877             :     default: return false;
    6878             :     case MCK_Reg53: return true;
    6879             :     case MCK_Reg54: return true;
    6880             :     case MCK_Reg56: return true;
    6881             :     case MCK_XSeqPairsClass: return true;
    6882             :     }
    6883             : 
    6884           0 :   case MCK_Reg57:
    6885           0 :     switch (B) {
    6886             :     default: return false;
    6887           0 :     case MCK_Reg56: return true;
    6888           0 :     case MCK_XSeqPairsClass: return true;
    6889             :     }
    6890             : 
    6891       58427 :   case MCK_tcGPR64:
    6892             :     switch (B) {
    6893             :     default: return false;
    6894             :     case MCK_GPR64common: return true;
    6895             :     case MCK_GPR64: return true;
    6896             :     case MCK_GPR64sp: return true;
    6897             :     case MCK_GPR64all: return true;
    6898             :     }
    6899             : 
    6900           2 :   case MCK_Reg47:
    6901             :     switch (B) {
    6902             :     default: return false;
    6903             :     case MCK_Reg48: return true;
    6904             :     case MCK_Reg50: return true;
    6905             :     case MCK_WSeqPairsClass: return true;
    6906             :     }
    6907             : 
    6908           0 :   case MCK_Reg53:
    6909             :     switch (B) {
    6910             :     default: return false;
    6911             :     case MCK_Reg54: return true;
    6912             :     case MCK_Reg56: return true;
    6913             :     case MCK_XSeqPairsClass: return true;
    6914             :     }
    6915             : 
    6916           0 :   case MCK_Reg48:
    6917           0 :     return B == MCK_WSeqPairsClass;
    6918             : 
    6919           0 :   case MCK_Reg50:
    6920           0 :     return B == MCK_WSeqPairsClass;
    6921             : 
    6922           0 :   case MCK_Reg54:
    6923           0 :     return B == MCK_XSeqPairsClass;
    6924             : 
    6925           0 :   case MCK_Reg56:
    6926           0 :     return B == MCK_XSeqPairsClass;
    6927             : 
    6928       24100 :   case MCK_GPR32common:
    6929             :     switch (B) {
    6930             :     default: return false;
    6931             :     case MCK_GPR32: return true;
    6932             :     case MCK_GPR32sp: return true;
    6933             :     case MCK_GPR32all: return true;
    6934             :     }
    6935             : 
    6936        7564 :   case MCK_GPR64common:
    6937             :     switch (B) {
    6938             :     default: return false;
    6939             :     case MCK_GPR64: return true;
    6940             :     case MCK_GPR64sp: return true;
    6941             :     case MCK_GPR64all: return true;
    6942             :     }
    6943             : 
    6944       21709 :   case MCK_GPR32:
    6945       21709 :     return B == MCK_GPR32all;
    6946             : 
    6947        3656 :   case MCK_GPR32sp:
    6948        3656 :     return B == MCK_GPR32all;
    6949             : 
    6950       16775 :   case MCK_GPR64:
    6951       16775 :     return B == MCK_GPR64all;
    6952             : 
    6953        7579 :   case MCK_GPR64sp:
    6954        7579 :     return B == MCK_GPR64all;
    6955             : 
    6956           0 :   case MCK_Extend64:
    6957           0 :     return B == MCK_Extend;
    6958             : 
    6959           0 :   case MCK_ExtendLSL64:
    6960           0 :     return B == MCK_Extend;
    6961             : 
    6962           3 :   case MCK_LogicalVecHalfWordShifter:
    6963           3 :     switch (B) {
    6964             :     default: return false;
    6965           0 :     case MCK_LogicalVecShifter: return true;
    6966           0 :     case MCK_Shifter: return true;
    6967             :     }
    6968             : 
    6969           0 :   case MCK_ArithmeticShifter32:
    6970           0 :     return B == MCK_Shifter;
    6971             : 
    6972           0 :   case MCK_ArithmeticShifter64:
    6973           0 :     return B == MCK_Shifter;
    6974             : 
    6975           0 :   case MCK_LogicalShifter32:
    6976           0 :     return B == MCK_Shifter;
    6977             : 
    6978           0 :   case MCK_LogicalShifter64:
    6979           0 :     return B == MCK_Shifter;
    6980             : 
    6981          19 :   case MCK_LogicalVecShifter:
    6982          19 :     return B == MCK_Shifter;
    6983             : 
    6984           0 :   case MCK_MovImm32Shifter:
    6985           0 :     return B == MCK_Shifter;
    6986             : 
    6987           0 :   case MCK_MovImm64Shifter:
    6988           0 :     return B == MCK_Shifter;
    6989             : 
    6990           2 :   case MCK_MoveVecShifter:
    6991           2 :     return B == MCK_Shifter;
    6992             :   }
    6993             : }
    6994             : 
    6995      639774 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
    6996             :   AArch64Operand &Operand = (AArch64Operand&)GOp;
    6997      639774 :   if (Kind == InvalidMatchClass)
    6998             :     return MCTargetAsmParser::Match_InvalidOperand;
    6999             : 
    7000      636729 :   if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
    7001      264004 :     return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
    7002             :              MCTargetAsmParser::Match_Success :
    7003             :              MCTargetAsmParser::Match_InvalidOperand;
    7004             : 
    7005      504727 :   switch (Kind) {
    7006             :   default: break;
    7007             :   // 'AddSubImmNeg' class
    7008         978 :   case MCK_AddSubImmNeg: {
    7009         978 :     DiagnosticPredicate DP(Operand.isAddSubImmNeg());
    7010         978 :     if (DP.isMatch())
    7011             :       return MCTargetAsmParser::Match_Success;
    7012             :     if (DP.isNearMatch())
    7013             :       return AArch64AsmParser::Match_AddSubSecondSource;
    7014             :     break;
    7015             :     }
    7016             :   // 'AddSubImm' class
    7017         958 :   case MCK_AddSubImm: {
    7018         958 :     DiagnosticPredicate DP(Operand.isAddSubImm());
    7019         958 :     if (DP.isMatch())
    7020             :       return MCTargetAsmParser::Match_Success;
    7021             :     if (DP.isNearMatch())
    7022             :       return AArch64AsmParser::Match_AddSubSecondSource;
    7023             :     break;
    7024             :     }
    7025             :   // 'AdrLabel' class
    7026          33 :   case MCK_AdrLabel: {
    7027             :     DiagnosticPredicate DP(Operand.isAdrLabel());
    7028          33 :     if (DP.isMatch())
    7029             :       return MCTargetAsmParser::Match_Success;
    7030             :     if (DP.isNearMatch())
    7031             :       return AArch64AsmParser::Match_InvalidLabel;
    7032             :     break;
    7033             :     }
    7034             :   // 'AdrpLabel' class
    7035         182 :   case MCK_AdrpLabel: {
    7036             :     DiagnosticPredicate DP(Operand.isAdrpLabel());
    7037         182 :     if (DP.isMatch())
    7038             :       return MCTargetAsmParser::Match_Success;
    7039             :     if (DP.isNearMatch())
    7040             :       return AArch64AsmParser::Match_InvalidLabel;
    7041             :     break;
    7042             :     }
    7043             :   // 'Barrier' class
    7044          45 :   case MCK_Barrier: {
    7045             :     DiagnosticPredicate DP(Operand.isBarrier());
    7046          45 :     if (DP.isMatch())
    7047             :       return MCTargetAsmParser::Match_Success;
    7048             :     break;
    7049             :     }
    7050             :   // 'BranchTarget14' class
    7051             :   case MCK_BranchTarget14: {
    7052             :     DiagnosticPredicate DP(Operand.isBranchTarget<14>());
    7053          29 :     if (DP.isMatch())
    7054             :       return MCTargetAsmParser::Match_Success;
    7055             :     if (DP.isNearMatch())
    7056             :       return AArch64AsmParser::Match_InvalidLabel;
    7057             :     break;
    7058             :     }
    7059             :   // 'BranchTarget26' class
    7060             :   case MCK_BranchTarget26: {
    7061             :     DiagnosticPredicate DP(Operand.isBranchTarget<26>());
    7062         179 :     if (DP.isMatch())
    7063             :       return MCTargetAsmParser::Match_Success;
    7064             :     if (DP.isNearMatch())
    7065             :       return AArch64AsmParser::Match_InvalidLabel;
    7066             :     break;
    7067             :     }
    7068             :   // 'CondCode' class
    7069         265 :   case MCK_CondCode: {
    7070             :     DiagnosticPredicate DP(Operand.isCondCode());
    7071         265 :     if (DP.isMatch())
    7072             :       return MCTargetAsmParser::Match_Success;
    7073             :     if (DP.isNearMatch())
    7074             :       return AArch64AsmParser::Match_InvalidCondCode;
    7075             :     break;
    7076             :     }
    7077             :   // 'Extend64' class
    7078          34 :   case MCK_Extend64: {
    7079          34 :     DiagnosticPredicate DP(Operand.isExtend64());
    7080          34 :     if (DP.isMatch())
    7081             :       return MCTargetAsmParser::Match_Success;
    7082             :     if (DP.isNearMatch())
    7083             :       return AArch64AsmParser::Match_AddSubRegExtendSmall;
    7084             :     break;
    7085             :     }
    7086             :   // 'ExtendLSL64' class
    7087          64 :   case MCK_ExtendLSL64: {
    7088          64 :     DiagnosticPredicate DP(Operand.isExtendLSL64());
    7089          64 :     if (DP.isMatch())
    7090             :       return MCTargetAsmParser::Match_Success;
    7091             :     if (DP.isNearMatch())
    7092             :       return AArch64AsmParser::Match_AddSubRegExtendLarge;
    7093             :     break;
    7094             :     }
    7095             :   // 'Extend' class
    7096         191 :   case MCK_Extend: {
    7097         191 :     DiagnosticPredicate DP(Operand.isExtend());
    7098         191 :     if (DP.isMatch())
    7099             :       return MCTargetAsmParser::Match_Success;
    7100             :     if (DP.isNearMatch())
    7101             :       return AArch64AsmParser::Match_AddSubRegExtendLarge;
    7102             :     break;
    7103             :     }
    7104             :   // 'FPImm' class
    7105          52 :   case MCK_FPImm: {
    7106             :     DiagnosticPredicate DP(Operand.isFPImm());
    7107          52 :     if (DP.isMatch())
    7108             :       return MCTargetAsmParser::Match_Success;
    7109             :     if (DP.isNearMatch())
    7110             :       return AArch64AsmParser::Match_InvalidFPImm;
    7111             :     break;
    7112             :     }
    7113             :   // 'GPR32as64' class
    7114          26 :   case MCK_GPR32as64: {
    7115          26 :     DiagnosticPredicate DP(Operand.isGPR32as64());
    7116          26 :     if (DP.isMatch())
    7117             :       return MCTargetAsmParser::Match_Success;
    7118             :     break;
    7119             :     }
    7120             :   // 'GPR64NoXZRshifted16' class
    7121         859 :   case MCK_GPR64NoXZRshifted16: {
    7122         859 :     DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 16>());
    7123         859 :     if (DP.isMatch())
    7124             :       return MCTargetAsmParser::Match_Success;
    7125         734 :     if (DP.isNearMatch())
    7126             :       return AArch64AsmParser::Match_InvalidGPR64NoXZRshifted16;
    7127             :     break;
    7128             :     }
    7129             :   // 'GPR64NoXZRshifted32' class
    7130         768 :   case MCK_GPR64NoXZRshifted32: {
    7131         768 :     DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 32>());
    7132         768 :     if (DP.isMatch())
    7133             :       return MCTargetAsmParser::Match_Success;
    7134         658 :     if (DP.isNearMatch())
    7135             :       return AArch64AsmParser::Match_InvalidGPR64NoXZRshifted32;
    7136             :     break;
    7137             :     }
    7138             :   // 'GPR64NoXZRshifted64' class
    7139         578 :   case MCK_GPR64NoXZRshifted64: {
    7140         578 :     DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 64>());
    7141         578 :     if (DP.isMatch())
    7142             :       return MCTargetAsmParser::Match_Success;
    7143         488 :     if (DP.isNearMatch())
    7144             :       return AArch64AsmParser::Match_InvalidGPR64NoXZRshifted64;
    7145             :     break;
    7146             :     }
    7147             :   // 'GPR64NoXZRshifted8' class
    7148         853 :   case MCK_GPR64NoXZRshifted8: {
    7149         853 :     DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 8>());
    7150         853 :     if (DP.isMatch())
    7151             :       return MCTargetAsmParser::Match_Success;
    7152         703 :     if (DP.isNearMatch())
    7153             :       return AArch64AsmParser::Match_InvalidGPR64NoXZRshifted8;
    7154             :     break;
    7155             :     }
    7156             :   // 'GPR64shifted16' class
    7157         204 :   case MCK_GPR64shifted16: {
    7158         204 :     DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64RegClassID, 16>());
    7159         204 :     if (DP.isMatch())
    7160             :       return MCTargetAsmParser::Match_Success;
    7161         154 :     if (DP.isNearMatch())
    7162             :       return AArch64AsmParser::Match_InvalidGPR64shifted16;
    7163             :     break;
    7164             :     }
    7165             :   // 'GPR64shifted32' class
    7166         158 :   case MCK_GPR64shifted32: {
    7167         158 :     DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64RegClassID, 32>());
    7168         158 :     if (DP.isMatch())
    7169             :       return MCTargetAsmParser::Match_Success;
    7170         128 :     if (DP.isNearMatch())
    7171             :       return AArch64AsmParser::Match_InvalidGPR64shifted32;
    7172             :     break;
    7173             :     }
    7174             :   // 'GPR64shifted64' class
    7175          56 :   case MCK_GPR64shifted64: {
    7176          56 :     DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64RegClassID, 64>());
    7177          56 :     if (DP.isMatch())
    7178             :       return MCTargetAsmParser::Match_Success;
    7179          46 :     if (DP.isNearMatch())
    7180             :       return AArch64AsmParser::Match_InvalidGPR64shifted64;
    7181             :     break;
    7182             :     }
    7183             :   // 'GPR64shifted8' class
    7184         177 :   case MCK_GPR64shifted8: {
    7185         177 :     DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64RegClassID, 8>());
    7186         177 :     if (DP.isMatch())
    7187             :       return MCTargetAsmParser::Match_Success;
    7188         112 :     if (DP.isNearMatch())
    7189             :       return AArch64AsmParser::Match_InvalidGPR64shifted8;
    7190             :     break;
    7191             :     }
    7192             :   // 'GPR64sp0' class
    7193         131 :   case MCK_GPR64sp0: {
    7194         131 :     DiagnosticPredicate DP(Operand.isGPR64<AArch64::GPR64spRegClassID>());
    7195         131 :     if (DP.isMatch())
    7196             :       return MCTargetAsmParser::Match_Success;
    7197             :     break;
    7198             :     }
    7199             :   // 'Imm0_127' class
    7200             :   case MCK_Imm0_127: {
    7201             :     DiagnosticPredicate DP(Operand.isImmInRange<0,127>());
    7202           6 :     if (DP.isMatch())
    7203             :       return MCTargetAsmParser::Match_Success;
    7204             :     if (DP.isNearMatch())
    7205             :       return AArch64AsmParser::Match_InvalidImm0_127;
    7206             :     break;
    7207             :     }
    7208             :   // 'Imm0_15' class
    7209             :   case MCK_Imm0_15: {
    7210             :     DiagnosticPredicate DP(Operand.isImmInRange<0,15>());
    7211         197 :     if (DP.isMatch())
    7212             :       return MCTargetAsmParser::Match_Success;
    7213             :     if (DP.isNearMatch())
    7214             :       return AArch64AsmParser::Match_InvalidImm0_15;
    7215             :     break;
    7216             :     }
    7217             :   // 'Imm0_1' class
    7218             :   case MCK_Imm0_1: {
    7219             :     DiagnosticPredicate DP(Operand.isImmInRange<0,1>());
    7220          12 :     if (DP.isMatch())
    7221             :       return MCTargetAsmParser::Match_Success;
    7222             :     if (DP.isNearMatch())
    7223             :       return AArch64AsmParser::Match_InvalidImm0_1;
    7224             :     break;
    7225             :     }
    7226             :   // 'Imm0_255' class
    7227             :   case MCK_Imm0_255: {
    7228             :     DiagnosticPredicate DP(Operand.isImmInRange<0,255>());
    7229         338 :     if (DP.isMatch())
    7230             :       return MCTargetAsmParser::Match_Success;
    7231             :     if (DP.isNearMatch())
    7232             :       return AArch64AsmParser::Match_InvalidImm0_255;
    7233             :     break;
    7234             :     }
    7235             :   // 'Imm0_31' class
    7236             :   case MCK_Imm0_31: {
    7237             :     DiagnosticPredicate DP(Operand.isImmInRange<0,31>());
    7238         432 :     if (DP.isMatch())
    7239             :       return MCTargetAsmParser::Match_Success;
    7240             :     if (DP.isNearMatch())
    7241             :       return AArch64AsmParser::Match_InvalidImm0_31;
    7242             :     break;
    7243             :     }
    7244             :   // 'Imm0_63' class
    7245             :   case MCK_Imm0_63: {
    7246             :     DiagnosticPredicate DP(Operand.isImmInRange<0,63>());
    7247         199 :     if (DP.isMatch())
    7248             :       return MCTargetAsmParser::Match_Success;
    7249             :     if (DP.isNearMatch())
    7250             :       return AArch64AsmParser::Match_InvalidImm0_63;
    7251             :     break;
    7252             :     }
    7253             :   // 'Imm0_65535' class
    7254             :   case MCK_Imm0_65535: {
    7255             :     DiagnosticPredicate DP(Operand.isImmInRange<0,65535>());
    7256         409 :     if (DP.isMatch())
    7257             :       return MCTargetAsmParser::Match_Success;
    7258             :     if (DP.isNearMatch())
    7259             :       return AArch64AsmParser::Match_InvalidImm0_65535;
    7260             :     break;
    7261             :     }
    7262             :   // 'Imm0_7' class
    7263             :   case MCK_Imm0_7: {
    7264             :     DiagnosticPredicate DP(Operand.isImmInRange<0,7>());
    7265         631 :     if (DP.isMatch())
    7266             :       return MCTargetAsmParser::Match_Success;
    7267             :     if (DP.isNearMatch())
    7268             :       return AArch64AsmParser::Match_InvalidImm0_7;
    7269             :     break;
    7270             :     }
    7271             :   // 'Imm1_16' class
    7272             :   case MCK_Imm1_16: {
    7273             :     DiagnosticPredicate DP(Operand.isImmInRange<1,16>());
    7274         160 :     if (DP.isMatch())
    7275             :       return MCTargetAsmParser::Match_Success;
    7276             :     if (DP.isNearMatch())
    7277             :       return AArch64AsmParser::Match_InvalidImm1_16;
    7278             :     break;
    7279             :     }
    7280             :   // 'Imm1_32' class
    7281             :   case MCK_Imm1_32: {
    7282             :     DiagnosticPredicate DP(Operand.isImmInRange<1,32>());
    7283         238 :     if (DP.isMatch())
    7284             :       return MCTargetAsmParser::Match_Success;
    7285             :     if (DP.isNearMatch())
    7286             :       return AArch64AsmParser::Match_InvalidImm1_32;
    7287             :     break;
    7288             :     }
    7289             :   // 'Imm1_64' class
    7290             :   case MCK_Imm1_64: {
    7291             :     DiagnosticPredicate DP(Operand.isImmInRange<1,64>());
    7292         163 :     if (DP.isMatch())
    7293             :       return MCTargetAsmParser::Match_Success;
    7294             :     if (DP.isNearMatch())
    7295             :       return AArch64AsmParser::Match_InvalidImm1_64;
    7296             :     break;
    7297             :     }
    7298             :   // 'Imm1_8' class
    7299             :   case MCK_Imm1_8: {
    7300             :     DiagnosticPredicate DP(Operand.isImmInRange<1,8>());
    7301         142 :     if (DP.isMatch())
    7302             :       return MCTargetAsmParser::Match_Success;
    7303             :     if (DP.isNearMatch())
    7304             :       return AArch64AsmParser::Match_InvalidImm1_8;
    7305             :     break;
    7306             :     }
    7307             :   // 'Imm' class
    7308           2 :   case MCK_Imm: {
    7309             :     DiagnosticPredicate DP(Operand.isImm());
    7310           2 :     if (DP.isMatch())
    7311             :       return MCTargetAsmParser::Match_Success;
    7312             :     break;
    7313             :     }
    7314             :   // 'LogicalImm32Not' class
    7315          32 :   case MCK_LogicalImm32Not: {
    7316          32 :     DiagnosticPredicate DP(Operand.isLogicalImm<int32_t>());
    7317          32 :     if (DP.isMatch())
    7318             :       return MCTargetAsmParser::Match_Success;
    7319             :     if (DP.isNearMatch())
    7320             :       return AArch64AsmParser::Match_LogicalSecondSource;
    7321             :     break;
    7322             :     }
    7323             :   // 'LogicalImm32' class
    7324         104 :   case MCK_LogicalImm32: {
    7325         104 :     DiagnosticPredicate DP(Operand.isLogicalImm<int32_t>());
    7326         104 :     if (DP.isMatch())
    7327             :       return MCTargetAsmParser::Match_Success;
    7328             :     if (DP.isNearMatch())
    7329             :       return AArch64AsmParser::Match_LogicalSecondSource;
    7330             :     break;
    7331             :     }
    7332             :   // 'LogicalImm64Not' class
    7333          40 :   case MCK_LogicalImm64Not: {
    7334          40 :     DiagnosticPredicate DP(Operand.isLogicalImm<int64_t>());
    7335          40 :     if (DP.isMatch())
    7336             :       return MCTargetAsmParser::Match_Success;
    7337             :     if (DP.isNearMatch())
    7338             :       return AArch64AsmParser::Match_LogicalSecondSource;
    7339             :     break;
    7340             :     }
    7341             :   // 'LogicalImm64' class
    7342          95 :   case MCK_LogicalImm64: {
    7343          95 :     DiagnosticPredicate DP(Operand.isLogicalImm<int64_t>());
    7344          95 :     if (DP.isMatch())
    7345             :       return MCTargetAsmParser::Match_Success;
    7346             :     if (DP.isNearMatch())
    7347             :       return AArch64AsmParser::Match_LogicalSecondSource;
    7348             :     break;
    7349             :     }
    7350             :   // 'MRSSystemRegister' class
    7351             :   case MCK_MRSSystemRegister: {
    7352             :     DiagnosticPredicate DP(Operand.isMRSSystemRegister());
    7353        1124 :     if (DP.isMatch())
    7354             :       return MCTargetAsmParser::Match_Success;
    7355             :     if (DP.isNearMatch())
    7356             :       return AArch64AsmParser::Match_MRS;
    7357             :     break;
    7358             :     }
    7359             :   // 'MSRSystemRegister' class
    7360             :   case MCK_MSRSystemRegister: {
    7361             :     DiagnosticPredicate DP(Operand.isMSRSystemRegister());
    7362        1029 :     if (DP.isMatch())
    7363             :       return MCTargetAsmParser::Match_Success;
    7364             :     if (DP.isNearMatch())
    7365             :       return AArch64AsmParser::Match_MSR;
    7366             :     break;
    7367             :     }
    7368             :   // 'MemWExtend128' class
    7369          13 :   case MCK_MemWExtend128: {
    7370          13 :     DiagnosticPredicate DP(Operand.isMemWExtend<128>());
    7371          13 :     if (DP.isMatch())
    7372             :       return MCTargetAsmParser::Match_Success;
    7373             :     if (DP.isNearMatch())
    7374             :       return AArch64AsmParser::Match_InvalidMemoryWExtend128;
    7375             :     break;
    7376             :     }
    7377             :   // 'MemWExtend16' class
    7378          12 :   case MCK_MemWExtend16: {
    7379          12 :     DiagnosticPredicate DP(Operand.isMemWExtend<16>());
    7380          12 :     if (DP.isMatch())
    7381             :       return MCTargetAsmParser::Match_Success;
    7382             :     if (DP.isNearMatch())
    7383             :       return AArch64AsmParser::Match_InvalidMemoryWExtend16;
    7384             :     break;
    7385             :     }
    7386             :   // 'MemWExtend32' class
    7387          16 :   case MCK_MemWExtend32: {
    7388          16 :     DiagnosticPredicate DP(Operand.isMemWExtend<32>());
    7389          16 :     if (DP.isMatch())
    7390             :       return MCTargetAsmParser::Match_Success;
    7391             :     if (DP.isNearMatch())
    7392             :       return AArch64AsmParser::Match_InvalidMemoryWExtend32;
    7393             :     break;
    7394             :     }
    7395             :   // 'MemWExtend64' class
    7396          15 :   case MCK_MemWExtend64: {
    7397          15 :     DiagnosticPredicate DP(Operand.isMemWExtend<64>());
    7398          15 :     if (DP.isMatch())
    7399             :       return MCTargetAsmParser::Match_Success;
    7400             :     if (DP.isNearMatch())
    7401             :       return AArch64AsmParser::Match_InvalidMemoryWExtend64;
    7402             :     break;
    7403             :     }
    7404             :   // 'MemWExtend8' class
    7405           8 :   case MCK_MemWExtend8: {
    7406           8 :     DiagnosticPredicate DP(Operand.isMemWExtend<8>());
    7407           8 :     if (DP.isMatch())
    7408             :       return MCTargetAsmParser::Match_Success;
    7409             :     if (DP.isNearMatch())
    7410             :       return AArch64AsmParser::Match_InvalidMemoryWExtend8;
    7411             :     break;
    7412             :     }
    7413             :   // 'MemXExtend128' class
    7414           6 :   case MCK_MemXExtend128: {
    7415           6 :     DiagnosticPredicate DP(Operand.isMemXExtend<128>());
    7416           6 :     if (DP.isMatch())
    7417             :       return MCTargetAsmParser::Match_Success;
    7418             :     if (DP.isNearMatch())
    7419             :       return AArch64AsmParser::Match_InvalidMemoryXExtend128;
    7420             :     break;
    7421             :     }
    7422             :   // 'MemXExtend16' class
    7423           6 :   case MCK_MemXExtend16: {
    7424           6 :     DiagnosticPredicate DP(Operand.isMemXExtend<16>());
    7425           6 :     if (DP.isMatch())
    7426             :       return MCTargetAsmParser::Match_Success;
    7427             :     if (DP.isNearMatch())
    7428             :       return AArch64AsmParser::Match_InvalidMemoryXExtend16;
    7429             :     break;
    7430             :     }
    7431             :   // 'MemXExtend32' class
    7432          15 :   case MCK_MemXExtend32: {
    7433          15 :     DiagnosticPredicate DP(Operand.isMemXExtend<32>());
    7434          15 :     if (DP.isMatch())
    7435             :       return MCTargetAsmParser::Match_Success;
    7436             :     if (DP.isNearMatch())
    7437             :       return AArch64AsmParser::Match_InvalidMemoryXExtend32;
    7438             :     break;
    7439             :     }
    7440             :   // 'MemXExtend64' class
    7441          13 :   case MCK_MemXExtend64: {
    7442          13 :     DiagnosticPredicate DP(Operand.isMemXExtend<64>());
    7443          13 :     if (DP.isMatch())
    7444             :       return MCTargetAsmParser::Match_Success;
    7445             :     if (DP.isNearMatch())
    7446             :       return AArch64AsmParser::Match_InvalidMemoryXExtend64;
    7447             :     break;
    7448             :     }
    7449             :   // 'MemXExtend8' class
    7450           6 :   case MCK_MemXExtend8: {
    7451           6 :     DiagnosticPredicate DP(Operand.isMemXExtend<8>());
    7452           6 :     if (DP.isMatch())
    7453             :       return MCTargetAsmParser::Match_Success;
    7454             :     if (DP.isNearMatch())
    7455             :       return AArch64AsmParser::Match_InvalidMemoryXExtend8;
    7456             :     break;
    7457             :     }
    7458             :   // 'MovKSymbolG0' class
    7459             :   case MCK_MovKSymbolG0: {
    7460             :     DiagnosticPredicate DP(Operand.isMovKSymbolG0());
    7461          94 :     if (DP.isMatch())
    7462             :       return MCTargetAsmParser::Match_Success;
    7463             :     break;
    7464             :     }
    7465             :   // 'MovKSymbolG1' class
    7466             :   case MCK_MovKSymbolG1: {
    7467             :     DiagnosticPredicate DP(Operand.isMovKSymbolG1());
    7468          64 :     if (DP.isMatch())
    7469             :       return MCTargetAsmParser::Match_Success;
    7470             :     break;
    7471             :     }
    7472             :   // 'MovKSymbolG2' class
    7473             :   case MCK_MovKSymbolG2: {
    7474             :     DiagnosticPredicate DP(Operand.isMovKSymbolG2());
    7475          21 :     if (DP.isMatch())
    7476             :       return MCTargetAsmParser::Match_Success;
    7477             :     break;
    7478             :     }
    7479             :   // 'MovKSymbolG3' class
    7480             :   case MCK_MovKSymbolG3: {
    7481             :     DiagnosticPredicate DP(Operand.isMovKSymbolG3());
    7482          13 :     if (DP.isMatch())
    7483             :       return MCTargetAsmParser::Match_Success;
    7484             :     break;
    7485             :     }
    7486             :   // 'MovZSymbolG0' class
    7487             :   case MCK_MovZSymbolG0: {
    7488             :     DiagnosticPredicate DP(Operand.isMovZSymbolG0());
    7489         186 :     if (DP.isMatch())
    7490             :       return MCTargetAsmParser::Match_Success;
    7491             :     break;
    7492             :     }
    7493             :   // 'MovZSymbolG1' class
    7494             :   case MCK_MovZSymbolG1: {
    7495             :     DiagnosticPredicate DP(Operand.isMovZSymbolG1());
    7496         147 :     if (DP.isMatch())
    7497             :       return MCTargetAsmParser::Match_Success;
    7498             :     break;
    7499             :     }
    7500             :   // 'MovZSymbolG2' class
    7501             :   case MCK_MovZSymbolG2: {
    7502             :     DiagnosticPredicate DP(Operand.isMovZSymbolG2());
    7503          74 :     if (DP.isMatch())
    7504             :       return MCTargetAsmParser::Match_Success;
    7505             :     break;
    7506             :     }
    7507             :   // 'MovZSymbolG3' class
    7508             :   case MCK_MovZSymbolG3: {
    7509             :     DiagnosticPredicate DP(Operand.isMovZSymbolG3());
    7510          41 :     if (DP.isMatch())
    7511             :       return MCTargetAsmParser::Match_Success;
    7512             :     break;
    7513             :     }
    7514             :   // 'PCRelLabel19' class
    7515             :   case MCK_PCRelLabel19: {
    7516             :     DiagnosticPredicate DP(Operand.isBranchTarget<19>());
    7517         835 :     if (DP.isMatch())
    7518             :       return MCTargetAsmParser::Match_Success;
    7519             :     if (DP.isNearMatch())
    7520             :       return AArch64AsmParser::Match_InvalidLabel;
    7521             :     break;
    7522             :     }
    7523             :   // 'SVEPredicateHReg' class
    7524        1116 :   case MCK_SVEPredicateHReg: {
    7525        1116 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<16, AArch64::PPRRegClassID>());
    7526        1116 :     if (DP.isMatch())
    7527             :       return MCTargetAsmParser::Match_Success;
    7528        1022 :     if (DP.isNearMatch())
    7529             :       return AArch64AsmParser::Match_InvalidSVEPredicateHReg;
    7530             :     break;
    7531             :     }
    7532             :   // 'SVEPredicateSReg' class
    7533        1108 :   case MCK_SVEPredicateSReg: {
    7534        1108 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<32, AArch64::PPRRegClassID>());
    7535        1108 :     if (DP.isMatch())
    7536             :       return MCTargetAsmParser::Match_Success;
    7537         326 :     if (DP.isNearMatch())
    7538             :       return AArch64AsmParser::Match_InvalidSVEPredicateSReg;
    7539             :     break;
    7540             :     }
    7541             :   // 'SVEPredicate3bHReg' class
    7542           0 :   case MCK_SVEPredicate3bHReg: {
    7543           0 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<16, AArch64::PPR_3bRegClassID>());
    7544           0 :     if (DP.isMatch())
    7545             :       return MCTargetAsmParser::Match_Success;
    7546           0 :     if (DP.isNearMatch())
    7547             :       return AArch64AsmParser::Match_InvalidSVEPredicate3bHReg;
    7548             :     break;
    7549             :     }
    7550             :   // 'SVEPredicate3bSReg' class
    7551           0 :   case MCK_SVEPredicate3bSReg: {
    7552           0 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<32, AArch64::PPR_3bRegClassID>());
    7553           0 :     if (DP.isMatch())
    7554             :       return MCTargetAsmParser::Match_Success;
    7555           0 :     if (DP.isNearMatch())
    7556             :       return AArch64AsmParser::Match_InvalidSVEPredicate3bSReg;
    7557             :     break;
    7558             :     }
    7559             :   // 'SVEPredicate3bDReg' class
    7560           0 :   case MCK_SVEPredicate3bDReg: {
    7561           0 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<64, AArch64::PPR_3bRegClassID>());
    7562           0 :     if (DP.isMatch())
    7563             :       return MCTargetAsmParser::Match_Success;
    7564           0 :     if (DP.isNearMatch())
    7565             :       return AArch64AsmParser::Match_InvalidSVEPredicate3bDReg;
    7566             :     break;
    7567             :     }
    7568             :   // 'SVEPredicate3bBReg' class
    7569           0 :   case MCK_SVEPredicate3bBReg: {
    7570           0 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<8, AArch64::PPR_3bRegClassID>());
    7571           0 :     if (DP.isMatch())
    7572             :       return MCTargetAsmParser::Match_Success;
    7573           0 :     if (DP.isNearMatch())
    7574             :       return AArch64AsmParser::Match_InvalidSVEPredicate3bBReg;
    7575             :     break;
    7576             :     }
    7577             :   // 'SVEPredicate3bAnyReg' class
    7578       31138 :   case MCK_SVEPredicate3bAnyReg: {
    7579       31138 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<0, AArch64::PPR_3bRegClassID>());
    7580       31138 :     if (DP.isMatch())
    7581             :       return MCTargetAsmParser::Match_Success;
    7582        1082 :     if (DP.isNearMatch())
    7583             :       return AArch64AsmParser::Match_InvalidSVEPredicate3bAnyReg;
    7584             :     break;
    7585             :     }
    7586             :   // 'SVEPredicateDReg' class
    7587         876 :   case MCK_SVEPredicateDReg: {
    7588         876 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<64, AArch64::PPRRegClassID>());
    7589         876 :     if (DP.isMatch())
    7590             :       return MCTargetAsmParser::Match_Success;
    7591         782 :     if (DP.isNearMatch())
    7592             :       return AArch64AsmParser::Match_InvalidSVEPredicateDReg;
    7593             :     break;
    7594             :     }
    7595             :   // 'SVEPredicateBReg' class
    7596         852 :   case MCK_SVEPredicateBReg: {
    7597         852 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<8, AArch64::PPRRegClassID>());
    7598         852 :     if (DP.isMatch())
    7599             :       return MCTargetAsmParser::Match_Success;
    7600         758 :     if (DP.isNearMatch())
    7601             :       return AArch64AsmParser::Match_InvalidSVEPredicateBReg;
    7602             :     break;
    7603             :     }
    7604             :   // 'SVEPredicateAnyReg' class
    7605        1153 :   case MCK_SVEPredicateAnyReg: {
    7606        1153 :     DiagnosticPredicate DP(Operand.isSVEPredicateVectorRegOfWidth<0, AArch64::PPRRegClassID>());
    7607        1153 :     if (DP.isMatch())
    7608             :       return MCTargetAsmParser::Match_Success;
    7609        1083 :     if (DP.isNearMatch())
    7610             :       return AArch64AsmParser::Match_InvalidSVEPredicateAnyReg;
    7611             :     break;
    7612             :     }
    7613             :   // 'PSBHint' class
    7614           3 :   case MCK_PSBHint: {
    7615             :     DiagnosticPredicate DP(Operand.isPSBHint());
    7616           3 :     if (DP.isMatch())
    7617             :       return MCTargetAsmParser::Match_Success;
    7618             :     break;
    7619             :     }
    7620             :   // 'Prefetch' class
    7621         139 :   case MCK_Prefetch: {
    7622             :     DiagnosticPredicate DP(Operand.isPrefetch());
    7623         139 :     if (DP.isMatch())
    7624             :       return MCTargetAsmParser::Match_Success;
    7625             :     break;
    7626             :     }
    7627             :   // 'SIMDImmType10' class
    7628             :   case MCK_SIMDImmType10: {
    7629             :     DiagnosticPredicate DP(Operand.isSIMDImmType10());
    7630           8 :     if (DP.isMatch())
    7631             :       return MCTargetAsmParser::Match_Success;
    7632             :     break;
    7633             :     }
    7634             :   // 'SImm10s8' class
    7635             :   case MCK_SImm10s8: {
    7636             :     DiagnosticPredicate DP(Operand.isSImmScaled<10, 8>());
    7637          76 :     if (DP.isMatch())
    7638             :       return MCTargetAsmParser::Match_Success;
    7639          32 :     if (DP.isNearMatch())
    7640             :       return AArch64AsmParser::Match_InvalidMemoryIndexed8SImm10;
    7641             :     break;
    7642             :     }
    7643             :   // 'SImm4s16' class
    7644             :   case MCK_SImm4s16: {
    7645             :     DiagnosticPredicate DP(Operand.isSImmScaled<4, 16>());
    7646         156 :     if (DP.isMatch())
    7647             :       return MCTargetAsmParser::Match_Success;
    7648          88 :     if (DP.isNearMatch())
    7649             :       return AArch64AsmParser::Match_InvalidMemoryIndexed16SImm4;
    7650             :     break;
    7651             :     }
    7652             :   // 'SImm4s1' class
    7653             :   case MCK_SImm4s1: {
    7654             :     DiagnosticPredicate DP(Operand.isSImmScaled<4, 1>());
    7655        1398 :     if (DP.isMatch())
    7656             :       return MCTargetAsmParser::Match_Success;
    7657         898 :     if (DP.isNearMatch())
    7658             :       return AArch64AsmParser::Match_InvalidMemoryIndexed1SImm4;
    7659             :     break;
    7660             :     }
    7661             :   // 'SImm4s2' class
    7662             :   case MCK_SImm4s2: {
    7663             :     DiagnosticPredicate DP(Operand.isSImmScaled<4, 2>());
    7664         268 :     if (DP.isMatch())
    7665             :       return MCTargetAsmParser::Match_Success;
    7666         188 :     if (DP.isNearMatch())
    7667             :       return AArch64AsmParser::Match_InvalidMemoryIndexed2SImm4;
    7668             :     break;
    7669             :     }
    7670             :   // 'SImm4s3' class
    7671             :   case MCK_SImm4s3: {
    7672             :     DiagnosticPredicate DP(Operand.isSImmScaled<4, 3>());
    7673         268 :     if (DP.isMatch())
    7674             :       return MCTargetAsmParser::Match_Success;
    7675         188 :     if (DP.isNearMatch())
    7676             :       return AArch64AsmParser::Match_InvalidMemoryIndexed3SImm4;
    7677             :     break;
    7678             :     }
    7679             :   // 'SImm4s4' class
    7680             :   case MCK_SImm4s4: {
    7681             :     DiagnosticPredicate DP(Operand.isSImmScaled<4, 4>());
    7682         268 :     if (DP.isMatch())
    7683             :       return MCTargetAsmParser::Match_Success;
    7684         188 :     if (DP.isNearMatch())
    7685             :       return AArch64AsmParser::Match_InvalidMemoryIndexed4SImm4;
    7686             :     break;
    7687             :     }
    7688             :   // 'SImm5' class
    7689             :   case MCK_SImm5: {
    7690             :     DiagnosticPredicate DP(Operand.isSImm<5>());
    7691         360 :     if (DP.isMatch())
    7692             :       return MCTargetAsmParser::Match_Success;
    7693             :     if (DP.isNearMatch())
    7694             :       return AArch64AsmParser::Match_InvalidMemoryIndexedSImm5;
    7695             :     break;
    7696             :     }
    7697             :   // 'SImm6' class
    7698             :   case MCK_SImm6: {
    7699             :     DiagnosticPredicate DP(Operand.isSImm<6>());
    7700          72 :     if (DP.isMatch())
    7701             :       return MCTargetAsmParser::Match_Success;
    7702             :     if (DP.isNearMatch())
    7703             :       return AArch64AsmParser::Match_InvalidMemoryIndexedSImm6;
    7704             :     break;
    7705             :     }
    7706             :   // 'SImm6s1' class
    7707             :   case MCK_SImm6s1: {
    7708             :     DiagnosticPredicate DP(Operand.isSImmScaled<6, 1>());
    7709         394 :     if (DP.isMatch())
    7710             :       return MCTargetAsmParser::Match_Success;
    7711         354 :     if (DP.isNearMatch())
    7712             :       return AArch64AsmParser::Match_InvalidMemoryIndexed1SImm6;
    7713             :     break;
    7714             :     }
    7715             :   // 'SImm7s16' class
    7716             :   case MCK_SImm7s16: {
    7717             :     DiagnosticPredicate DP(Operand.isSImmScaled<7, 16>());
    7718          78 :     if (DP.isMatch())
    7719             :       return MCTargetAsmParser::Match_Success;
    7720          58 :     if (DP.isNearMatch())
    7721             :       return AArch64AsmParser::Match_InvalidMemoryIndexed16SImm7;
    7722             :     break;
    7723             :     }
    7724             :   // 'SImm7s4' class
    7725             :   case MCK_SImm7s4: {
    7726             :     DiagnosticPredicate DP(Operand.isSImmScaled<7, 4>());
    7727         244 :     if (DP.isMatch())
    7728             :       return MCTargetAsmParser::Match_Success;
    7729         164 :     if (DP.isNearMatch())
    7730             :       return AArch64AsmParser::Match_InvalidMemoryIndexed4SImm7;
    7731             :     break;
    7732             :     }
    7733             :   // 'SImm7s8' class
    7734             :   case MCK_SImm7s8: {
    7735             :     DiagnosticPredicate DP(Operand.isSImmScaled<7, 8>());
    7736         174 :     if (DP.isMatch())
    7737             :       return MCTargetAsmParser::Match_Success;
    7738          90 :     if (DP.isNearMatch())
    7739             :       return AArch64AsmParser::Match_InvalidMemoryIndexed8SImm7;
    7740             :     break;
    7741             :     }
    7742             :   // 'SImm9OffsetFB128' class
    7743          95 :   case MCK_SImm9OffsetFB128: {
    7744          95 :     DiagnosticPredicate DP(Operand.isSImm9OffsetFB<128>());
    7745          95 :     if (DP.isMatch())
    7746             :       return MCTargetAsmParser::Match_Success;
    7747             :     break;
    7748             :     }
    7749             :   // 'SImm9OffsetFB16' class
    7750         219 :   case MCK_SImm9OffsetFB16: {
    7751         219 :     DiagnosticPredicate DP(Operand.isSImm9OffsetFB<16>());
    7752         219 :     if (DP.isMatch())
    7753             :       return MCTargetAsmParser::Match_Success;
    7754             :     break;
    7755             :     }
    7756             :   // 'SImm9OffsetFB32' class
    7757         236 :   case MCK_SImm9OffsetFB32: {
    7758         236 :     DiagnosticPredicate DP(Operand.isSImm9OffsetFB<32>());
    7759         236 :     if (DP.isMatch())
    7760             :       return MCTargetAsmParser::Match_Success;
    7761             :     break;
    7762             :     }
    7763             :   // 'SImm9OffsetFB64' class
    7764         304 :   case MCK_SImm9OffsetFB64: {
    7765         304 :     DiagnosticPredicate DP(Operand.isSImm9OffsetFB<64>());
    7766         304 :     if (DP.isMatch())
    7767             :       return MCTargetAsmParser::Match_Success;
    7768             :     break;
    7769             :     }
    7770             :   // 'SImm9OffsetFB8' class
    7771         204 :   case MCK_SImm9OffsetFB8: {
    7772         204 :     DiagnosticPredicate DP(Operand.isSImm9OffsetFB<8>());
    7773         204 :     if (DP.isMatch())
    7774             :       return MCTargetAsmParser::Match_Success;
    7775             :     break;
    7776             :     }
    7777             :   // 'SImm9' class
    7778             :   case MCK_SImm9: {
    7779             :     DiagnosticPredicate DP(Operand.isSImm<9>());
    7780         667 :     if (DP.isMatch())
    7781             :       return MCTargetAsmParser::Match_Success;
    7782             :     if (DP.isNearMatch())
    7783             :       return AArch64AsmParser::Match_InvalidMemoryIndexedSImm9;
    7784             :     break;
    7785             :     }
    7786             :   // 'SVEPattern' class
    7787             :   case MCK_SVEPattern: {
    7788             :     DiagnosticPredicate DP(Operand.isSVEPattern());
    7789         376 :     if (DP.isMatch())
    7790             :       return MCTargetAsmParser::Match_Success;
    7791             :     if (DP.isNearMatch())
    7792             :       return AArch64AsmParser::Match_InvalidSVEPattern;
    7793             :     break;
    7794             :     }
    7795             :   // 'SVEPrefetch' class
    7796        7167 :   case MCK_SVEPrefetch: {
    7797             :     DiagnosticPredicate DP(Operand.isPrefetch());
    7798        7167 :     if (DP.isMatch())
    7799             :       return MCTargetAsmParser::Match_Success;
    7800             :     break;
    7801             :     }
    7802             :   // 'LogicalVecHalfWordShifter' class
    7803          27 :   case MCK_LogicalVecHalfWordShifter: {
    7804          27 :     DiagnosticPredicate DP(Operand.isLogicalVecHalfWordShifter());
    7805          27 :     if (DP.isMatch())
    7806             :       return MCTargetAsmParser::Match_Success;
    7807             :     break;
    7808             :     }
    7809             :   // 'ArithmeticShifter32' class
    7810             :   case MCK_ArithmeticShifter32: {
    7811             :     DiagnosticPredicate DP(Operand.isArithmeticShifter<32>());
    7812         223 :     if (DP.isMatch())
    7813             :       return MCTargetAsmParser::Match_Success;
    7814             :     if (DP.isNearMatch())
    7815             :       return AArch64AsmParser::Match_AddSubRegShift32;
    7816             :     break;
    7817             :     }
    7818             :   // 'ArithmeticShifter64' class
    7819             :   case MCK_ArithmeticShifter64: {
    7820             :     DiagnosticPredicate DP(Operand.isArithmeticShifter<64>());
    7821         168 :     if (DP.isMatch())
    7822             :       return MCTargetAsmParser::Match_Success;
    7823             :     if (DP.isNearMatch())
    7824             :       return AArch64AsmParser::Match_AddSubRegShift64;
    7825             :     break;
    7826             :     }
    7827             :   // 'LogicalShifter32' class
    7828             :   case MCK_LogicalShifter32: {
    7829             :     DiagnosticPredicate DP(Operand.isLogicalShifter<32>());
    7830          57 :     if (DP.isMatch())
    7831             :       return MCTargetAsmParser::Match_Success;
    7832             :     if (DP.isNearMatch())
    7833             :       return AArch64AsmParser::Match_AddSubRegShift32;
    7834             :     break;
    7835             :     }
    7836             :   // 'LogicalShifter64' class
    7837             :   case MCK_LogicalShifter64: {
    7838             :     DiagnosticPredicate DP(Operand.isLogicalShifter<64>());
    7839          47 :     if (DP.isMatch())
    7840             :       return MCTargetAsmParser::Match_Success;
    7841             :     if (DP.isNearMatch())
    7842             :       return AArch64AsmParser::Match_AddSubRegShift64;
    7843             :     break;
    7844             :     }
    7845             :   // 'LogicalVecShifter' class
    7846          75 :   case MCK_LogicalVecShifter: {
    7847          75 :     DiagnosticPredicate DP(Operand.isLogicalVecShifter());
    7848          75 :     if (DP.isMatch())
    7849             :       return MCTargetAsmParser::Match_Success;
    7850             :     break;
    7851             :     }
    7852             :   // 'MovImm32Shifter' class
    7853             :   case MCK_MovImm32Shifter: {
    7854             :     DiagnosticPredicate DP(Operand.isMovImm32Shifter());
    7855          15 :     if (DP.isMatch())
    7856             :       return MCTargetAsmParser::Match_Success;
    7857             :     if (DP.isNearMatch())
    7858             :       return AArch64AsmParser::Match_InvalidMovImm32Shift;
    7859             :     break;
    7860             :     }
    7861             :   // 'MovImm64Shifter' class
    7862          16 :   case MCK_MovImm64Shifter: {
    7863          16 :     DiagnosticPredicate DP(Operand.isMovImm64Shifter());
    7864          16 :     if (DP.isMatch())
    7865             :       return MCTargetAsmParser::Match_Success;
    7866             :     if (DP.isNearMatch())
    7867             :       return AArch64AsmParser::Match_InvalidMovImm64Shift;
    7868             :     break;
    7869             :     }
    7870             :   // 'MoveVecShifter' class
    7871             :   case MCK_MoveVecShifter: {
    7872             :     DiagnosticPredicate DP(Operand.isMoveVecShifter());
    7873          18 :     if (DP.isMatch())
    7874             :       return MCTargetAsmParser::Match_Success;
    7875             :     break;
    7876             :     }
    7877             :   // 'Shifter' class
    7878             :   case MCK_Shifter: {
    7879             :     DiagnosticPredicate DP(Operand.isShifter());
    7880           0 :     if (DP.isMatch())
    7881             :       return MCTargetAsmParser::Match_Success;
    7882             :     break;
    7883             :     }
    7884             :   // 'SysCR' class
    7885         552 :   case MCK_SysCR: {
    7886             :     DiagnosticPredicate DP(Operand.isSysCR());
    7887         552 :     if (DP.isMatch())
    7888             :       return MCTargetAsmParser::Match_Success;
    7889             :     break;
    7890             :     }
    7891             :   // 'SystemPStateFieldWithImm0_15' class
    7892             :   case MCK_SystemPStateFieldWithImm0_15: {
    7893             :     DiagnosticPredicate DP(Operand.isSystemPStateFieldWithImm0_15());
    7894         279 :     if (DP.isMatch())
    7895             :       return MCTargetAsmParser::Match_Success;
    7896             :     break;
    7897             :     }
    7898             :   // 'SystemPStateFieldWithImm0_1' class
    7899             :   case MCK_SystemPStateFieldWithImm0_1: {
    7900             :     DiagnosticPredicate DP(Operand.isSystemPStateFieldWithImm0_1());
    7901         274 :     if (DP.isMatch())
    7902             :       return MCTargetAsmParser::Match_Success;
    7903             :     break;
    7904             :     }
    7905             :   // 'TBZImm0_31' class
    7906             :   case MCK_TBZImm0_31: {
    7907             :     DiagnosticPredicate DP(Operand.isImmInRange<0,31>());
    7908          18 :     if (DP.isMatch())
    7909             :       return MCTargetAsmParser::Match_Success;
    7910             :     break;
    7911             :     }
    7912             :   // 'Imm32_63' class
    7913             :   case MCK_Imm32_63: {
    7914             :     DiagnosticPredicate DP(Operand.isImmInRange<32,63>());
    7915          25 :     if (DP.isMatch())
    7916             :       return MCTargetAsmParser::Match_Success;
    7917             :     if (DP.isNearMatch())
    7918             :       return AArch64AsmParser::Match_InvalidImm0_63;
    7919             :     break;
    7920             :     }
    7921             :   // 'UImm12Offset16' class
    7922          90 :   case MCK_UImm12Offset16: {
    7923          90 :     DiagnosticPredicate DP(Operand.isUImm12Offset<16>());
    7924          90 :     if (DP.isMatch())
    7925             :       return MCTargetAsmParser::Match_Success;
    7926             :     if (DP.isNearMatch())
    7927             :       return AArch64AsmParser::Match_InvalidMemoryIndexed16;
    7928             :     break;
    7929             :     }
    7930             :   // 'UImm12Offset1' class
    7931         198 :   case MCK_UImm12Offset1: {
    7932         198 :     DiagnosticPredicate DP(Operand.isUImm12Offset<1>());
    7933         198 :     if (DP.isMatch())
    7934             :       return MCTargetAsmParser::Match_Success;
    7935             :     if (DP.isNearMatch())
    7936             :       return AArch64AsmParser::Match_InvalidMemoryIndexed1;
    7937             :     break;
    7938             :     }
    7939             :   // 'UImm12Offset2' class
    7940         205 :   case MCK_UImm12Offset2: {
    7941         205 :     DiagnosticPredicate DP(Operand.isUImm12Offset<2>());
    7942         205 :     if (DP.isMatch())
    7943             :       return MCTargetAsmParser::Match_Success;
    7944             :     if (DP.isNearMatch())
    7945             :       return AArch64AsmParser::Match_InvalidMemoryIndexed2;
    7946             :     break;
    7947             :     }
    7948             :   // 'UImm12Offset4' class
    7949         225 :   case MCK_UImm12Offset4: {
    7950         225 :     DiagnosticPredicate DP(Operand.isUImm12Offset<4>());
    7951         225 :     if (DP.isMatch())
    7952             :       return MCTargetAsmParser::Match_Success;
    7953             :     if (DP.isNearMatch())
    7954             :       return AArch64AsmParser::Match_InvalidMemoryIndexed4;
    7955             :     break;
    7956             :     }
    7957             :   // 'UImm12Offset8' class
    7958         308 :   case MCK_UImm12Offset8: {
    7959         308 :     DiagnosticPredicate DP(Operand.isUImm12Offset<8>());
    7960         308 :     if (DP.isMatch())
    7961             :       return MCTargetAsmParser::Match_Success;
    7962             :     if (DP.isNearMatch())
    7963             :       return AArch64AsmParser::Match_InvalidMemoryIndexed8;
    7964             :     break;
    7965             :     }
    7966             :   // 'UImm5s2' class
    7967             :   case MCK_UImm5s2: {
    7968             :     DiagnosticPredicate DP(Operand.isUImmScaled<5, 2>());
    7969         206 :     if (DP.isMatch())
    7970             :       return MCTargetAsmParser::Match_Success;
    7971         136 :     if (DP.isNearMatch())
    7972             :       return AArch64AsmParser::Match_InvalidMemoryIndexed2UImm5;
    7973             :     break;
    7974             :     }
    7975             :   // 'UImm5s4' class
    7976             :   case MCK_UImm5s4: {
    7977             :     DiagnosticPredicate DP(Operand.isUImmScaled<5, 4>());
    7978         172 :     if (DP.isMatch())
    7979             :       return MCTargetAsmParser::Match_Success;
    7980         112 :     if (DP.isNearMatch())
    7981             :       return AArch64AsmParser::Match_InvalidMemoryIndexed4UImm5;
    7982             :     break;
    7983             :     }
    7984             :   // 'UImm5s8' class
    7985             :   case MCK_UImm5s8: {
    7986             :     DiagnosticPredicate DP(Operand.isUImmScaled<5, 8>());
    7987          79 :     if (DP.isMatch())
    7988             :       return MCTargetAsmParser::Match_Success;
    7989          44 :     if (DP.isNearMatch())
    7990             :       return AArch64AsmParser::Match_InvalidMemoryIndexed8UImm5;
    7991             :     break;
    7992             :     }
    7993             :   // 'UImm6s1' class
    7994             :   case MCK_UImm6s1: {
    7995             :     DiagnosticPredicate DP(Operand.isUImmScaled<6, 1>());
    7996          57 :     if (DP.isMatch())
    7997             :       return MCTargetAsmParser::Match_Success;
    7998          22 :     if (DP.isNearMatch())
    7999             :       return AArch64AsmParser::Match_InvalidMemoryIndexed1UImm6;
    8000             :     break;
    8001             :     }
    8002             :   // 'UImm6s2' class
    8003             :   case MCK_UImm6s2: {
    8004             :     DiagnosticPredicate DP(Operand.isUImmScaled<6, 2>());
    8005          51 :     if (DP.isMatch())
    8006             :       return MCTargetAsmParser::Match_Success;
    8007          26 :     if (DP.isNearMatch())
    8008             :       return AArch64AsmParser::Match_InvalidMemoryIndexed2UImm6;
    8009             :     break;
    8010             :     }
    8011             :   // 'UImm6s4' class
    8012             :   case MCK_UImm6s4: {
    8013             :     DiagnosticPredicate DP(Operand.isUImmScaled<6, 4>());
    8014          37 :     if (DP.isMatch())
    8015             :       return MCTargetAsmParser::Match_Success;
    8016          22 :     if (DP.isNearMatch())
    8017             :       return AArch64AsmParser::Match_InvalidMemoryIndexed4UImm6;
    8018             :     break;
    8019             :     }
    8020             :   // 'UImm6s8' class
    8021             :   case MCK_UImm6s8: {
    8022             :     DiagnosticPredicate DP(Operand.isUImmScaled<6, 8>());
    8023          17 :     if (DP.isMatch())
    8024             :       return MCTargetAsmParser::Match_Success;
    8025          12 :     if (DP.isNearMatch())
    8026             :       return AArch64AsmParser::Match_InvalidMemoryIndexed8UImm6;
    8027             :     break;
    8028             :     }
    8029             :   // 'VecListFour128' class
    8030             :   case MCK_VecListFour128: {
    8031             :     DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 4>());
    8032         348 :     if (DP.isMatch())
    8033             :       return MCTargetAsmParser::Match_Success;
    8034             :     break;
    8035             :     }
    8036             :   // 'TypedVectorList4_168' class
    8037             :   case MCK_TypedVectorList4_168: {
    8038             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 16, 8>());
    8039        2192 :     if (DP.isMatch())
    8040             :       return MCTargetAsmParser::Match_Success;
    8041             :     break;
    8042             :     }
    8043             :   // 'TypedVectorList4_164' class
    8044             :   case MCK_TypedVectorList4_164: {
    8045             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 1, 64>());
    8046        1613 :     if (DP.isMatch())
    8047             :       return MCTargetAsmParser::Match_Success;
    8048             :     break;
    8049             :     }
    8050             :   // 'TypedVectorList4_264' class
    8051             :   case MCK_TypedVectorList4_264: {
    8052             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 2, 64>());
    8053        2066 :     if (DP.isMatch())
    8054             :       return MCTargetAsmParser::Match_Success;
    8055             :     break;
    8056             :     }
    8057             :   // 'TypedVectorList4_232' class
    8058             :   case MCK_TypedVectorList4_232: {
    8059             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 2, 32>());
    8060        2023 :     if (DP.isMatch())
    8061             :       return MCTargetAsmParser::Match_Success;
    8062             :     break;
    8063             :     }
    8064             :   // 'TypedVectorList4_416' class
    8065             :   case MCK_TypedVectorList4_416: {
    8066             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 4, 16>());
    8067        1983 :     if (DP.isMatch())
    8068             :       return MCTargetAsmParser::Match_Success;
    8069             :     break;
    8070             :     }
    8071             :   // 'TypedVectorList4_432' class
    8072             :   case MCK_TypedVectorList4_432: {
    8073             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 4, 32>());
    8074        1933 :     if (DP.isMatch())
    8075             :       return MCTargetAsmParser::Match_Success;
    8076             :     break;
    8077             :     }
    8078             :   // 'VecListFour64' class
    8079             :   case MCK_VecListFour64: {
    8080             :     DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 4>());
    8081         286 :     if (DP.isMatch())
    8082             :       return MCTargetAsmParser::Match_Success;
    8083             :     break;
    8084             :     }
    8085             :   // 'TypedVectorList4_88' class
    8086             :   case MCK_TypedVectorList4_88: {
    8087             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 8, 8>());
    8088        1894 :     if (DP.isMatch())
    8089             :       return MCTargetAsmParser::Match_Success;
    8090             :     break;
    8091             :     }
    8092             :   // 'TypedVectorList4_816' class
    8093             :   case MCK_TypedVectorList4_816: {
    8094             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 8, 16>());
    8095        1848 :     if (DP.isMatch())
    8096             :       return MCTargetAsmParser::Match_Success;
    8097             :     break;
    8098             :     }
    8099             :   // 'TypedVectorList4_08' class
    8100             :   case MCK_TypedVectorList4_08: {
    8101             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 0, 8>());
    8102         212 :     if (DP.isMatch())
    8103             :       return MCTargetAsmParser::Match_Success;
    8104             :     break;
    8105             :     }
    8106             :   // 'TypedVectorList4_064' class
    8107             :   case MCK_TypedVectorList4_064: {
    8108             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 0, 64>());
    8109         194 :     if (DP.isMatch())
    8110             :       return MCTargetAsmParser::Match_Success;
    8111             :     break;
    8112             :     }
    8113             :   // 'TypedVectorList4_016' class
    8114             :   case MCK_TypedVectorList4_016: {
    8115             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 0, 16>());
    8116         180 :     if (DP.isMatch())
    8117             :       return MCTargetAsmParser::Match_Success;
    8118             :     break;
    8119             :     }
    8120             :   // 'TypedVectorList4_032' class
    8121             :   case MCK_TypedVectorList4_032: {
    8122             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 0, 32>());
    8123         162 :     if (DP.isMatch())
    8124             :       return MCTargetAsmParser::Match_Success;
    8125             :     break;
    8126             :     }
    8127             :   // 'VecListOne128' class
    8128             :   case MCK_VecListOne128: {
    8129             :     DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 1>());
    8130         257 :     if (DP.isMatch())
    8131             :       return MCTargetAsmParser::Match_Success;
    8132             :     break;
    8133             :     }
    8134             :   // 'TypedVectorList1_168' class
    8135             :   case MCK_TypedVectorList1_168: {
    8136             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 16, 8>());
    8137        1538 :     if (DP.isMatch())
    8138             :       return MCTargetAsmParser::Match_Success;
    8139             :     break;
    8140             :     }
    8141             :   // 'TypedVectorList1_164' class
    8142             :   case MCK_TypedVectorList1_164: {
    8143             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 1, 64>());
    8144        1465 :     if (DP.isMatch())
    8145             :       return MCTargetAsmParser::Match_Success;
    8146             :     break;
    8147             :     }
    8148             :   // 'TypedVectorList1_264' class
    8149             :   case MCK_TypedVectorList1_264: {
    8150             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 2, 64>());
    8151        1440 :     if (DP.isMatch())
    8152             :       return MCTargetAsmParser::Match_Success;
    8153             :     break;
    8154             :     }
    8155             :   // 'TypedVectorList1_232' class
    8156             :   case MCK_TypedVectorList1_232: {
    8157             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 2, 32>());
    8158        1417 :     if (DP.isMatch())
    8159             :       return MCTargetAsmParser::Match_Success;
    8160             :     break;
    8161             :     }
    8162             :   // 'TypedVectorList1_416' class
    8163             :   case MCK_TypedVectorList1_416: {
    8164             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 4, 16>());
    8165        1395 :     if (DP.isMatch())
    8166             :       return MCTargetAsmParser::Match_Success;
    8167             :     break;
    8168             :     }
    8169             :   // 'TypedVectorList1_432' class
    8170             :   case MCK_TypedVectorList1_432: {
    8171             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 4, 32>());
    8172        1368 :     if (DP.isMatch())
    8173             :       return MCTargetAsmParser::Match_Success;
    8174             :     break;
    8175             :     }
    8176             :   // 'VecListOne64' class
    8177             :   case MCK_VecListOne64: {
    8178             :     DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 1>());
    8179         203 :     if (DP.isMatch())
    8180             :       return MCTargetAsmParser::Match_Success;
    8181             :     break;
    8182             :     }
    8183             :   // 'TypedVectorList1_88' class
    8184             :   case MCK_TypedVectorList1_88: {
    8185             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 8, 8>());
    8186        1347 :     if (DP.isMatch())
    8187             :       return MCTargetAsmParser::Match_Success;
    8188             :     break;
    8189             :     }
    8190             :   // 'TypedVectorList1_816' class
    8191             :   case MCK_TypedVectorList1_816: {
    8192             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 8, 16>());
    8193        1322 :     if (DP.isMatch())
    8194             :       return MCTargetAsmParser::Match_Success;
    8195             :     break;
    8196             :     }
    8197             :   // 'TypedVectorList1_08' class
    8198             :   case MCK_TypedVectorList1_08: {
    8199             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 0, 8>());
    8200         446 :     if (DP.isMatch())
    8201             :       return MCTargetAsmParser::Match_Success;
    8202             :     break;
    8203             :     }
    8204             :   // 'TypedVectorList1_064' class
    8205             :   case MCK_TypedVectorList1_064: {
    8206             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 0, 64>());
    8207         428 :     if (DP.isMatch())
    8208             :       return MCTargetAsmParser::Match_Success;
    8209             :     break;
    8210             :     }
    8211             :   // 'TypedVectorList1_016' class
    8212             :   case MCK_TypedVectorList1_016: {
    8213             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 0, 16>());
    8214         414 :     if (DP.isMatch())
    8215             :       return MCTargetAsmParser::Match_Success;
    8216             :     break;
    8217             :     }
    8218             :   // 'TypedVectorList1_032' class
    8219             :   case MCK_TypedVectorList1_032: {
    8220             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 1, 0, 32>());
    8221         398 :     if (DP.isMatch())
    8222             :       return MCTargetAsmParser::Match_Success;
    8223             :     break;
    8224             :     }
    8225             :   // 'VecListThree128' class
    8226             :   case MCK_VecListThree128: {
    8227             :     DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 3>());
    8228         270 :     if (DP.isMatch())
    8229             :       return MCTargetAsmParser::Match_Success;
    8230             :     break;
    8231             :     }
    8232             :   // 'TypedVectorList3_168' class
    8233             :   case MCK_TypedVectorList3_168: {
    8234             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 16, 8>());
    8235        1886 :     if (DP.isMatch())
    8236             :       return MCTargetAsmParser::Match_Success;
    8237             :     break;
    8238             :     }
    8239             :   // 'TypedVectorList3_164' class
    8240             :   case MCK_TypedVectorList3_164: {
    8241             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 1, 64>());
    8242        1306 :     if (DP.isMatch())
    8243             :       return MCTargetAsmParser::Match_Success;
    8244             :     break;
    8245             :     }
    8246             :   // 'TypedVectorList3_264' class
    8247             :   case MCK_TypedVectorList3_264: {
    8248             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 2, 64>());
    8249        1774 :     if (DP.isMatch())
    8250             :       return MCTargetAsmParser::Match_Success;
    8251             :     break;
    8252             :     }
    8253             :   // 'TypedVectorList3_232' class
    8254             :   case MCK_TypedVectorList3_232: {
    8255             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 2, 32>());
    8256        1729 :     if (DP.isMatch())
    8257             :       return MCTargetAsmParser::Match_Success;
    8258             :     break;
    8259             :     }
    8260             :   // 'TypedVectorList3_416' class
    8261             :   case MCK_TypedVectorList3_416: {
    8262             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 4, 16>());
    8263        1689 :     if (DP.isMatch())
    8264             :       return MCTargetAsmParser::Match_Success;
    8265             :     break;
    8266             :     }
    8267             :   // 'TypedVectorList3_432' class
    8268             :   case MCK_TypedVectorList3_432: {
    8269             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 4, 32>());
    8270        1642 :     if (DP.isMatch())
    8271             :       return MCTargetAsmParser::Match_Success;
    8272             :     break;
    8273             :     }
    8274             :   // 'VecListThree64' class
    8275             :   case MCK_VecListThree64: {
    8276             :     DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 3>());
    8277         204 :     if (DP.isMatch())
    8278             :       return MCTargetAsmParser::Match_Success;
    8279             :     break;
    8280             :     }
    8281             :   // 'TypedVectorList3_88' class
    8282             :   case MCK_TypedVectorList3_88: {
    8283             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 8, 8>());
    8284        1601 :     if (DP.isMatch())
    8285             :       return MCTargetAsmParser::Match_Success;
    8286             :     break;
    8287             :     }
    8288             :   // 'TypedVectorList3_816' class
    8289             :   case MCK_TypedVectorList3_816: {
    8290             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 8, 16>());
    8291        1558 :     if (DP.isMatch())
    8292             :       return MCTargetAsmParser::Match_Success;
    8293             :     break;
    8294             :     }
    8295             :   // 'TypedVectorList3_08' class
    8296             :   case MCK_TypedVectorList3_08: {
    8297             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 0, 8>());
    8298         210 :     if (DP.isMatch())
    8299             :       return MCTargetAsmParser::Match_Success;
    8300             :     break;
    8301             :     }
    8302             :   // 'TypedVectorList3_064' class
    8303             :   case MCK_TypedVectorList3_064: {
    8304             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 0, 64>());
    8305         196 :     if (DP.isMatch())
    8306             :       return MCTargetAsmParser::Match_Success;
    8307             :     break;
    8308             :     }
    8309             :   // 'TypedVectorList3_016' class
    8310             :   case MCK_TypedVectorList3_016: {
    8311             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 0, 16>());
    8312         178 :     if (DP.isMatch())
    8313             :       return MCTargetAsmParser::Match_Success;
    8314             :     break;
    8315             :     }
    8316             :   // 'TypedVectorList3_032' class
    8317             :   case MCK_TypedVectorList3_032: {
    8318             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 3, 0, 32>());
    8319         164 :     if (DP.isMatch())
    8320             :       return MCTargetAsmParser::Match_Success;
    8321             :     break;
    8322             :     }
    8323             :   // 'VecListTwo128' class
    8324             :   case MCK_VecListTwo128: {
    8325             :     DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 2>());
    8326         219 :     if (DP.isMatch())
    8327             :       return MCTargetAsmParser::Match_Success;
    8328             :     break;
    8329             :     }
    8330             :   // 'TypedVectorList2_168' class
    8331             :   case MCK_TypedVectorList2_168: {
    8332             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 16, 8>());
    8333        1731 :     if (DP.isMatch())
    8334             :       return MCTargetAsmParser::Match_Success;
    8335             :     break;
    8336             :     }
    8337             :   // 'TypedVectorList2_164' class
    8338             :   case MCK_TypedVectorList2_164: {
    8339             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 1, 64>());
    8340        1156 :     if (DP.isMatch())
    8341             :       return MCTargetAsmParser::Match_Success;
    8342             :     break;
    8343             :     }
    8344             :   // 'TypedVectorList2_264' class
    8345             :   case MCK_TypedVectorList2_264: {
    8346             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 2, 64>());
    8347        1625 :     if (DP.isMatch())
    8348             :       return MCTargetAsmParser::Match_Success;
    8349             :     break;
    8350             :     }
    8351             :   // 'TypedVectorList2_232' class
    8352             :   case MCK_TypedVectorList2_232: {
    8353             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 2, 32>());
    8354        1582 :     if (DP.isMatch())
    8355             :       return MCTargetAsmParser::Match_Success;
    8356             :     break;
    8357             :     }
    8358             :   // 'TypedVectorList2_416' class
    8359             :   case MCK_TypedVectorList2_416: {
    8360             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 4, 16>());
    8361        1542 :     if (DP.isMatch())
    8362             :       return MCTargetAsmParser::Match_Success;
    8363             :     break;
    8364             :     }
    8365             :   // 'TypedVectorList2_432' class
    8366             :   case MCK_TypedVectorList2_432: {
    8367             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 4, 32>());
    8368        1493 :     if (DP.isMatch())
    8369             :       return MCTargetAsmParser::Match_Success;
    8370             :     break;
    8371             :     }
    8372             :   // 'VecListTwo64' class
    8373             :   case MCK_VecListTwo64: {
    8374             :     DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 2>());
    8375         157 :     if (DP.isMatch())
    8376             :       return MCTargetAsmParser::Match_Success;
    8377             :     break;
    8378             :     }
    8379             :   // 'TypedVectorList2_88' class
    8380             :   case MCK_TypedVectorList2_88: {
    8381             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 8, 8>());
    8382        1454 :     if (DP.isMatch())
    8383             :       return MCTargetAsmParser::Match_Success;
    8384             :     break;
    8385             :     }
    8386             :   // 'TypedVectorList2_816' class
    8387             :   case MCK_TypedVectorList2_816: {
    8388             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 8, 16>());
    8389        1409 :     if (DP.isMatch())
    8390             :       return MCTargetAsmParser::Match_Success;
    8391             :     break;
    8392             :     }
    8393             :   // 'TypedVectorList2_08' class
    8394             :   case MCK_TypedVectorList2_08: {
    8395             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 0, 8>());
    8396         230 :     if (DP.isMatch())
    8397             :       return MCTargetAsmParser::Match_Success;
    8398             :     break;
    8399             :     }
    8400             :   // 'TypedVectorList2_064' class
    8401             :   case MCK_TypedVectorList2_064: {
    8402             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 0, 64>());
    8403         214 :     if (DP.isMatch())
    8404             :       return MCTargetAsmParser::Match_Success;
    8405             :     break;
    8406             :     }
    8407             :   // 'TypedVectorList2_016' class
    8408             :   case MCK_TypedVectorList2_016: {
    8409             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 0, 16>());
    8410         196 :     if (DP.isMatch())
    8411             :       return MCTargetAsmParser::Match_Success;
    8412             :     break;
    8413             :     }
    8414             :   // 'TypedVectorList2_032' class
    8415             :   case MCK_TypedVectorList2_032: {
    8416             :     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 2, 0, 32>());
    8417         180 :     if (DP.isMatch())
    8418             :       return MCTargetAsmParser::Match_Success;
    8419             :     break;
    8420             :     }
    8421             :   // 'VectorIndex1' class
    8422          13 :   case MCK_VectorIndex1: {
    8423             :     DiagnosticPredicate DP(Operand.isVectorIndex1());
    8424          13 :     if (DP.isMatch())
    8425             :       return MCTargetAsmParser::Match_Success;
    8426             :     if (DP.isNearMatch())
    8427             :       return AArch64AsmParser::Match_InvalidIndex1;
    8428             :     break;
    8429             :     }
    8430             :   // 'VectorIndexB' class
    8431         206 :   case MCK_VectorIndexB: {
    8432             :     DiagnosticPredicate DP(Operand.isVectorIndexB());
    8433         206 :     if (DP.isMatch())
    8434             :       return MCTargetAsmParser::Match_Success;
    8435             :     if (DP.isNearMatch())
    8436             :       return AArch64AsmParser::Match_InvalidIndexB;
    8437             :     break;
    8438             :     }
    8439             :   // 'VectorIndexD' class
    8440         283 :   case MCK_VectorIndexD: {
    8441             :     DiagnosticPredicate DP(Operand.isVectorIndexD());
    8442         283 :     if (DP.isMatch())
    8443             :       return MCTargetAsmParser::Match_Success;
    8444             :     if (DP.isNearMatch())
    8445             :       return AArch64AsmParser::Match_InvalidIndexD;
    8446             :     break;
    8447             :     }
    8448             :   // 'VectorIndexH' class
    8449         377 :   case MCK_VectorIndexH: {
    8450             :     DiagnosticPredicate DP(Operand.isVectorIndexH());
    8451         377 :     if (DP.isMatch())
    8452             :       return MCTargetAsmParser::Match_Success;
    8453             :     if (DP.isNearMatch())
    8454             :       return AArch64AsmParser::Match_InvalidIndexH;
    8455             :     break;
    8456             :     }
    8457             :   // 'VectorIndexS' class
    8458         471 :   case MCK_VectorIndexS: {
    8459             :     DiagnosticPredicate DP(Operand.isVectorIndexS());
    8460         471 :     if (DP.isMatch())
    8461             :       return MCTargetAsmParser::Match_Success;
    8462             :     if (DP.isNearMatch())
    8463             :       return AArch64AsmParser::Match_InvalidIndexS;
    8464             :     break;
    8465             :     }
    8466             :   // 'VectorReg128' class
    8467       19563 :   case MCK_VectorReg128: {
    8468             :     DiagnosticPredicate DP(Operand.isNeonVectorReg());
    8469       19563 :     if (DP.isMatch())
    8470             :       return MCTargetAsmParser::Match_Success;
    8471             :     break;
    8472             :     }
    8473             :   // 'VectorReg64' class
    8474       11518 :   case MCK_VectorReg64: {
    8475             :     DiagnosticPredicate DP(Operand.isNeonVectorReg());
    8476       11518 :     if (DP.isMatch())
    8477             :       return MCTargetAsmParser::Match_Success;
    8478             :     break;
    8479             :     }
    8480             :   // 'VectorRegLo' class
    8481         237 :   case MCK_VectorRegLo: {
    8482         237 :     DiagnosticPredicate DP(Operand.isNeonVectorRegLo());
    8483         237 :     if (DP.isMatch())
    8484             :       return MCTargetAsmParser::Match_Success;
    8485             :     break;
    8486             :     }
    8487             :   // 'WSeqPair' class
    8488          77 :   case MCK_WSeqPair: {
    8489          77 :     DiagnosticPredicate DP(Operand.isWSeqPair());
    8490          77 :     if (DP.isMatch())
    8491             :       return MCTargetAsmParser::Match_Success;
    8492             :     break;
    8493             :     }
    8494             :   // 'XSeqPair' class
    8495          54 :   case MCK_XSeqPair: {
    8496          54 :     DiagnosticPredicate DP(Operand.isXSeqPair());
    8497          54 :     if (DP.isMatch())
    8498             :       return MCTargetAsmParser::Match_Success;
    8499             :     break;
    8500             :     }
    8501             :   // 'ZPRExtendSXTW3216' class
    8502         337 :   case MCK_ZPRExtendSXTW3216: {
    8503         337 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 16, false>());
    8504         337 :     if (DP.isMatch())
    8505             :       return MCTargetAsmParser::Match_Success;
    8506         307 :     if (DP.isNearMatch())
    8507             :       return AArch64AsmParser::Match_InvalidZPR32SXTW16;
    8508             :     break;
    8509             :     }
    8510             :   // 'ZPRExtendSXTW3232' class
    8511         269 :   case MCK_ZPRExtendSXTW3232: {
    8512         269 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 32, false>());
    8513         269 :     if (DP.isMatch())
    8514             :       return MCTargetAsmParser::Match_Success;
    8515         249 :     if (DP.isNearMatch())
    8516             :       return AArch64AsmParser::Match_InvalidZPR32SXTW32;
    8517             :     break;
    8518             :     }
    8519             :   // 'ZPRExtendSXTW3264' class
    8520         107 :   case MCK_ZPRExtendSXTW3264: {
    8521         107 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 64, false>());
    8522         107 :     if (DP.isMatch())
    8523             :       return MCTargetAsmParser::Match_Success;
    8524         102 :     if (DP.isNearMatch())
    8525             :       return AArch64AsmParser::Match_InvalidZPR32SXTW64;
    8526             :     break;
    8527             :     }
    8528             :   // 'ZPRExtendSXTW328' class
    8529         352 :   case MCK_ZPRExtendSXTW328: {
    8530         352 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 8, false>());
    8531         352 :     if (DP.isMatch())
    8532             :       return MCTargetAsmParser::Match_Success;
    8533         312 :     if (DP.isNearMatch())
    8534             :       return AArch64AsmParser::Match_InvalidZPR32SXTW8;
    8535             :     break;
    8536             :     }
    8537             :   // 'ZPRExtendSXTW328Only' class
    8538         269 :   case MCK_ZPRExtendSXTW328Only: {
    8539         269 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 8, true>());
    8540         269 :     if (DP.isMatch())
    8541             :       return MCTargetAsmParser::Match_Success;
    8542         244 :     if (DP.isNearMatch())
    8543             :       return AArch64AsmParser::Match_InvalidZPR32SXTW8;
    8544             :     break;
    8545             :     }
    8546             :   // 'ZPRExtendUXTW3216' class
    8547         304 :   case MCK_ZPRExtendUXTW3216: {
    8548         304 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 16, false>());
    8549         304 :     if (DP.isMatch())
    8550             :       return MCTargetAsmParser::Match_Success;
    8551         274 :     if (DP.isNearMatch())
    8552             :       return AArch64AsmParser::Match_InvalidZPR32UXTW16;
    8553             :     break;
    8554             :     }
    8555             :   // 'ZPRExtendUXTW3232' class
    8556         248 :   case MCK_ZPRExtendUXTW3232: {
    8557         248 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 32, false>());
    8558         248 :     if (DP.isMatch())
    8559             :       return MCTargetAsmParser::Match_Success;
    8560         228 :     if (DP.isNearMatch())
    8561             :       return AArch64AsmParser::Match_InvalidZPR32UXTW32;
    8562             :     break;
    8563             :     }
    8564             :   // 'ZPRExtendUXTW3264' class
    8565         104 :   case MCK_ZPRExtendUXTW3264: {
    8566         104 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 64, false>());
    8567         104 :     if (DP.isMatch())
    8568             :       return MCTargetAsmParser::Match_Success;
    8569          99 :     if (DP.isNearMatch())
    8570             :       return AArch64AsmParser::Match_InvalidZPR32UXTW64;
    8571             :     break;
    8572             :     }
    8573             :   // 'ZPRExtendUXTW328' class
    8574         304 :   case MCK_ZPRExtendUXTW328: {
    8575         304 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 8, false>());
    8576         304 :     if (DP.isMatch())
    8577             :       return MCTargetAsmParser::Match_Success;
    8578         264 :     if (DP.isNearMatch())
    8579             :       return AArch64AsmParser::Match_InvalidZPR32UXTW8;
    8580             :     break;
    8581             :     }
    8582             :   // 'ZPRExtendUXTW328Only' class
    8583         254 :   case MCK_ZPRExtendUXTW328Only: {
    8584         254 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 8, true>());
    8585         254 :     if (DP.isMatch())
    8586             :       return MCTargetAsmParser::Match_Success;
    8587         219 :     if (DP.isNearMatch())
    8588             :       return AArch64AsmParser::Match_InvalidZPR32UXTW8;
    8589             :     break;
    8590             :     }
    8591             :   // 'ZPRExtendLSL6416' class
    8592         371 :   case MCK_ZPRExtendLSL6416: {
    8593         371 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::LSL, 16, false>());
    8594         371 :     if (DP.isMatch())
    8595             :       return MCTargetAsmParser::Match_Success;
    8596         341 :     if (DP.isNearMatch())
    8597             :       return AArch64AsmParser::Match_InvalidZPR64LSL16;
    8598             :     break;
    8599             :     }
    8600             :   // 'ZPRExtendLSL6432' class
    8601         399 :   case MCK_ZPRExtendLSL6432: {
    8602         399 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::LSL, 32, false>());
    8603         399 :     if (DP.isMatch())
    8604             :       return MCTargetAsmParser::Match_Success;
    8605         369 :     if (DP.isNearMatch())
    8606             :       return AArch64AsmParser::Match_InvalidZPR64LSL32;
    8607             :     break;
    8608             :     }
    8609             :   // 'ZPRExtendLSL6464' class
    8610         285 :   case MCK_ZPRExtendLSL6464: {
    8611         285 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::LSL, 64, false>());
    8612         285 :     if (DP.isMatch())
    8613             :       return MCTargetAsmParser::Match_Success;
    8614         265 :     if (DP.isNearMatch())
    8615             :       return AArch64AsmParser::Match_InvalidZPR64LSL64;
    8616             :     break;
    8617             :     }
    8618             :   // 'ZPRExtendLSL648' class
    8619        1005 :   case MCK_ZPRExtendLSL648: {
    8620        1005 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::LSL, 8, false>());
    8621        1005 :     if (DP.isMatch())
    8622             :       return MCTargetAsmParser::Match_Success;
    8623         910 :     if (DP.isNearMatch())
    8624             :       return AArch64AsmParser::Match_InvalidZPR64LSL8;
    8625             :     break;
    8626             :     }
    8627             :   // 'ZPRExtendSXTW6416' class
    8628         338 :   case MCK_ZPRExtendSXTW6416: {
    8629         338 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 16, false>());
    8630         338 :     if (DP.isMatch())
    8631             :       return MCTargetAsmParser::Match_Success;
    8632         308 :     if (DP.isNearMatch())
    8633             :       return AArch64AsmParser::Match_InvalidZPR64SXTW16;
    8634             :     break;
    8635             :     }
    8636             :   // 'ZPRExtendSXTW6432' class
    8637         366 :   case MCK_ZPRExtendSXTW6432: {
    8638         366 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 32, false>());
    8639         366 :     if (DP.isMatch())
    8640             :       return MCTargetAsmParser::Match_Success;
    8641         336 :     if (DP.isNearMatch())
    8642             :       return AArch64AsmParser::Match_InvalidZPR64SXTW32;
    8643             :     break;
    8644             :     }
    8645             :   // 'ZPRExtendSXTW6464' class
    8646         264 :   case MCK_ZPRExtendSXTW6464: {
    8647         264 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 64, false>());
    8648         264 :     if (DP.isMatch())
    8649             :       return MCTargetAsmParser::Match_Success;
    8650         244 :     if (DP.isNearMatch())
    8651             :       return AArch64AsmParser::Match_InvalidZPR64SXTW64;
    8652             :     break;
    8653             :     }
    8654             :   // 'ZPRExtendSXTW648' class
    8655         619 :   case MCK_ZPRExtendSXTW648: {
    8656         619 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 8, false>());
    8657         619 :     if (DP.isMatch())
    8658             :       return MCTargetAsmParser::Match_Success;
    8659         554 :     if (DP.isNearMatch())
    8660             :       return AArch64AsmParser::Match_InvalidZPR64SXTW8;
    8661             :     break;
    8662             :     }
    8663             :   // 'ZPRExtendSXTW648Only' class
    8664         290 :   case MCK_ZPRExtendSXTW648Only: {
    8665         290 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::SXTW, 8, true>());
    8666         290 :     if (DP.isMatch())
    8667             :       return MCTargetAsmParser::Match_Success;
    8668         260 :     if (DP.isNearMatch())
    8669             :       return AArch64AsmParser::Match_InvalidZPR64SXTW8;
    8670             :     break;
    8671             :     }
    8672             :   // 'ZPRExtendUXTW6416' class
    8673         305 :   case MCK_ZPRExtendUXTW6416: {
    8674         305 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 16, false>());
    8675         305 :     if (DP.isMatch())
    8676             :       return MCTargetAsmParser::Match_Success;
    8677         275 :     if (DP.isNearMatch())
    8678             :       return AArch64AsmParser::Match_InvalidZPR64UXTW16;
    8679             :     break;
    8680             :     }
    8681             :   // 'ZPRExtendUXTW6432' class
    8682         333 :   case MCK_ZPRExtendUXTW6432: {
    8683         333 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 32, false>());
    8684         333 :     if (DP.isMatch())
    8685             :       return MCTargetAsmParser::Match_Success;
    8686         303 :     if (DP.isNearMatch())
    8687             :       return AArch64AsmParser::Match_InvalidZPR64UXTW32;
    8688             :     break;
    8689             :     }
    8690             :   // 'ZPRExtendUXTW6464' class
    8691         243 :   case MCK_ZPRExtendUXTW6464: {
    8692         243 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 64, false>());
    8693         243 :     if (DP.isMatch())
    8694             :       return MCTargetAsmParser::Match_Success;
    8695         223 :     if (DP.isNearMatch())
    8696             :       return AArch64AsmParser::Match_InvalidZPR64UXTW64;
    8697             :     break;
    8698             :     }
    8699             :   // 'ZPRExtendUXTW648' class
    8700         541 :   case MCK_ZPRExtendUXTW648: {
    8701         541 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 8, false>());
    8702         541 :     if (DP.isMatch())
    8703             :       return MCTargetAsmParser::Match_Success;
    8704         476 :     if (DP.isNearMatch())
    8705             :       return AArch64AsmParser::Match_InvalidZPR64UXTW8;
    8706             :     break;
    8707             :     }
    8708             :   // 'ZPRExtendUXTW648Only' class
    8709         272 :   case MCK_ZPRExtendUXTW648Only: {
    8710         272 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 8, true>());
    8711         272 :     if (DP.isMatch())
    8712             :       return MCTargetAsmParser::Match_Success;
    8713         242 :     if (DP.isNearMatch())
    8714             :       return AArch64AsmParser::Match_InvalidZPR64UXTW8;
    8715             :     break;
    8716             :     }
    8717             :   // 'SVEVectorQReg' class
    8718           0 :   case MCK_SVEVectorQReg: {
    8719           0 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegOfWidth<128, AArch64::ZPRRegClassID>());
    8720           0 :     if (DP.isMatch())
    8721             :       return MCTargetAsmParser::Match_Success;
    8722           0 :     if (DP.isNearMatch())
    8723             :       return AArch64AsmParser::Match_InvalidZPR128;
    8724             :     break;
    8725             :     }
    8726             :   // 'SVEVectorHReg' class
    8727        7390 :   case MCK_SVEVectorHReg: {
    8728        7390 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegOfWidth<16, AArch64::ZPRRegClassID>());
    8729        7390 :     if (DP.isMatch())
    8730             :       return MCTargetAsmParser::Match_Success;
    8731        6250 :     if (DP.isNearMatch())
    8732             :       return AArch64AsmParser::Match_InvalidZPR16;
    8733             :     break;
    8734             :     }
    8735             :   // 'SVEVectorSReg' class
    8736       22987 :   case MCK_SVEVectorSReg: {
    8737       22987 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegOfWidth<32, AArch64::ZPRRegClassID>());
    8738       22987 :     if (DP.isMatch())
    8739             :       return MCTargetAsmParser::Match_Success;
    8740       19093 :     if (DP.isNearMatch())
    8741             :       return AArch64AsmParser::Match_InvalidZPR32;
    8742             :     break;
    8743             :     }
    8744             :   // 'SVEVectorDReg' class
    8745       32185 :   case MCK_SVEVectorDReg: {
    8746       32185 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegOfWidth<64, AArch64::ZPRRegClassID>());
    8747       32185 :     if (DP.isMatch())
    8748             :       return MCTargetAsmParser::Match_Success;
    8749       25931 :     if (DP.isNearMatch())
    8750             :       return AArch64AsmParser::Match_InvalidZPR64;
    8751             :     break;
    8752             :     }
    8753             :   // 'SVEVectorBReg' class
    8754        4200 :   case MCK_SVEVectorBReg: {
    8755        4200 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegOfWidth<8, AArch64::ZPRRegClassID>());
    8756        4200 :     if (DP.isMatch())
    8757             :       return MCTargetAsmParser::Match_Success;
    8758        3309 :     if (DP.isNearMatch())
    8759             :       return AArch64AsmParser::Match_InvalidZPR8;
    8760             :     break;
    8761             :     }
    8762             :   // 'SVEVectorAnyReg' class
    8763        1135 :   case MCK_SVEVectorAnyReg: {
    8764        1135 :     DiagnosticPredicate DP(Operand.isSVEDataVectorRegOfWidth<0, AArch64::ZPRRegClassID>());
    8765        1135 :     if (DP.isMatch())
    8766             :       return MCTargetAsmParser::Match_Success;
    8767        1065 :     if (DP.isNearMatch())
    8768             :       return AArch64AsmParser::Match_InvalidZPR0;
    8769             :     break;
    8770             :     }
    8771             :   // 'ComplexRotationEven' class
    8772             :   case MCK_ComplexRotationEven: {
    8773             :     DiagnosticPredicate DP(Operand.isComplexRotation<90, 0>());
    8774          72 :     if (DP.isMatch())
    8775             :       return MCTargetAsmParser::Match_Success;
    8776             :     if (DP.isNearMatch())
    8777             :       return AArch64AsmParser::Match_InvalidComplexRotationEven;
    8778             :     break;
    8779             :     }
    8780             :   // 'ComplexRotationOdd' class
    8781             :   case MCK_ComplexRotationOdd: {
    8782             :     DiagnosticPredicate DP(Operand.isComplexRotation<180, 90>());
    8783          36 :     if (DP.isMatch())
    8784             :       return MCTargetAsmParser::Match_Success;
    8785             :     if (DP.isNearMatch())
    8786             :       return AArch64AsmParser::Match_InvalidComplexRotationOdd;
    8787             :     break;
    8788             :     }
    8789             :   // 'SVELogicalImm8' class
    8790           9 :   case MCK_SVELogicalImm8: {
    8791           9 :     DiagnosticPredicate DP(Operand.isLogicalImm<int8_t>());
    8792           9 :     if (DP.isMatch())
    8793             :       return MCTargetAsmParser::Match_Success;
    8794             :     if (DP.isNearMatch())
    8795             :       return AArch64AsmParser::Match_LogicalSecondSource;
    8796             :     break;
    8797             :     }
    8798             :   // 'SVELogicalImm16' class
    8799           9 :   case MCK_SVELogicalImm16: {
    8800           9 :     DiagnosticPredicate DP(Operand.isLogicalImm<int16_t>());
    8801           9 :     if (DP.isMatch())
    8802             :       return MCTargetAsmParser::Match_Success;
    8803             :     if (DP.isNearMatch())
    8804             :       return AArch64AsmParser::Match_LogicalSecondSource;
    8805             :     break;
    8806             :     }
    8807             :   // 'SVELogicalImm32' class
    8808           9 :   case MCK_SVELogicalImm32: {
    8809           9 :     DiagnosticPredicate DP(Operand.isLogicalImm<int32_t>());
    8810           9 :     if (DP.isMatch())
    8811             :       return MCTargetAsmParser::Match_Success;
    8812             :     if (DP.isNearMatch())
    8813             :       return AArch64AsmParser::Match_LogicalSecondSource;
    8814             :     break;
    8815             :     }
    8816             :   // 'SVELogicalImm8Not' class
    8817           5 :   case MCK_SVELogicalImm8Not: {
    8818           5 :     DiagnosticPredicate DP(Operand.isLogicalImm<int8_t>());
    8819           5 :     if (DP.isMatch())
    8820             :       return MCTargetAsmParser::Match_Success;
    8821             :     if (DP.isNearMatch())
    8822             :       return AArch64AsmParser::Match_LogicalSecondSource;
    8823             :     break;
    8824             :     }
    8825             :   // 'SVELogicalImm16Not' class
    8826           5 :   case MCK_SVELogicalImm16Not: {
    8827           5 :     DiagnosticPredicate DP(Operand.isLogicalImm<int16_t>());
    8828           5 :     if (DP.isMatch())
    8829             :       return MCTargetAsmParser::Match_Success;
    8830             :     if (DP.isNearMatch())
    8831             :       return AArch64AsmParser::Match_LogicalSecondSource;
    8832             :     break;
    8833             :     }
    8834             :   // 'SVELogicalImm32Not' class
    8835           5 :   case MCK_SVELogicalImm32Not: {
    8836           5 :     DiagnosticPredicate DP(Operand.isLogicalImm<int32_t>());
    8837           5 :     if (DP.isMatch())
    8838             :       return MCTargetAsmParser::Match_Success;
    8839             :     if (DP.isNearMatch())
    8840             :       return AArch64AsmParser::Match_LogicalSecondSource;
    8841             :     break;
    8842             :     }
    8843             :   // 'MOVZ32_lsl0MovAlias' class
    8844             :   case MCK_MOVZ32_lsl0MovAlias: {
    8845             :     DiagnosticPredicate DP(Operand.isMOVZMovAlias<32, 0>());
    8846          13 :     if (DP.isMatch())
    8847             :       return MCTargetAsmParser::Match_Success;
    8848             :     break;
    8849             :     }
    8850             :   // 'MOVZ32_lsl16MovAlias' class
    8851             :   case MCK_MOVZ32_lsl16MovAlias: {
    8852             :     DiagnosticPredicate DP(Operand.isMOVZMovAlias<32, 16>());
    8853          13 :     if (DP.isMatch())
    8854             :       return MCTargetAsmParser::Match_Success;
    8855             :     break;
    8856             :     }
    8857             :   // 'MOVZ64_lsl0MovAlias' class
    8858             :   case MCK_MOVZ64_lsl0MovAlias: {
    8859