LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenGlobalISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 47 160 29.4 %
Date: 2018-05-20 00:06:23 Functions: 5 7 71.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Global Instruction Selector for the AArch64 target                         *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_GLOBALISEL_PREDICATE_BITSET
      10             : const unsigned MAX_SUBTARGET_PREDICATES = 15;
      11             : using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
      12             : #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
      13             : 
      14             : #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
      15             :   mutable MatcherState State;
      16             :   typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
      17             :   typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
      18             :   const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
      19             :   static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
      20             :   static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
      21             :   bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
      22             :   bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
      23             :   bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
      24             :   const int64_t *getMatchTable() const override;
      25             : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
      26             : 
      27             : #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
      28             : , State(1),
      29        5672 : ISelInfo({TypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers})
      30             : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
      31             : 
      32             : #ifdef GET_GLOBALISEL_IMPL
      33             : // Bits for subtarget features that participate in instruction matching.
      34             : enum SubtargetFeatureBits : uint8_t {
      35             :   Feature_HasFPARMv8Bit = 3,
      36             :   Feature_HasNEONBit = 4,
      37             :   Feature_HasCryptoBit = 6,
      38             :   Feature_HasDotProdBit = 0,
      39             :   Feature_HasCRCBit = 1,
      40             :   Feature_HasLSEBit = 14,
      41             :   Feature_HasRDMBit = 5,
      42             :   Feature_HasPerfMonBit = 7,
      43             :   Feature_HasFullFP16Bit = 2,
      44             :   Feature_HasFuseAESBit = 12,
      45             :   Feature_IsLEBit = 8,
      46             :   Feature_IsBEBit = 13,
      47             :   Feature_UseAlternateSExtLoadCVTF32Bit = 11,
      48             :   Feature_NotForCodeSizeBit = 10,
      49             :   Feature_UseSTRQroBit = 9,
      50             : };
      51             : 
      52        1418 : PredicateBitset AArch64InstructionSelector::
      53             : computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
      54        1418 :   PredicateBitset Features;
      55        1418 :   if (Subtarget->hasFPARMv8())
      56             :     Features[Feature_HasFPARMv8Bit] = 1;
      57        1418 :   if (Subtarget->hasNEON())
      58             :     Features[Feature_HasNEONBit] = 1;
      59        1418 :   if (Subtarget->hasCrypto())
      60             :     Features[Feature_HasCryptoBit] = 1;
      61        1418 :   if (Subtarget->hasDotProd())
      62             :     Features[Feature_HasDotProdBit] = 1;
      63        1418 :   if (Subtarget->hasCRC())
      64             :     Features[Feature_HasCRCBit] = 1;
      65        1418 :   if (Subtarget->hasLSE())
      66             :     Features[Feature_HasLSEBit] = 1;
      67        1418 :   if (Subtarget->hasRDM())
      68             :     Features[Feature_HasRDMBit] = 1;
      69        1418 :   if (Subtarget->hasPerfMon())
      70             :     Features[Feature_HasPerfMonBit] = 1;
      71        1418 :   if (Subtarget->hasFullFP16())
      72             :     Features[Feature_HasFullFP16Bit] = 1;
      73        1418 :   if (Subtarget->hasFuseAES())
      74             :     Features[Feature_HasFuseAESBit] = 1;
      75        1418 :   if (Subtarget->isLittleEndian())
      76             :     Features[Feature_IsLEBit] = 1;
      77        1418 :   if (!Subtarget->isLittleEndian())
      78             :     Features[Feature_IsBEBit] = 1;
      79        1418 :   if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
      80             :     Features[Feature_UseAlternateSExtLoadCVTF32Bit] = 1;
      81        1418 :   return Features;
      82             : }
      83             : 
      84         803 : PredicateBitset AArch64InstructionSelector::
      85             : computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
      86         803 :   PredicateBitset Features;
      87         803 :   if (!MF->getFunction().optForSize())
      88             :     Features[Feature_NotForCodeSizeBit] = 1;
      89         803 :   if (!Subtarget->isSTRQroSlow() || MF->getFunction().optForSize())
      90             :     Features[Feature_UseSTRQroBit] = 1;
      91         803 :   return Features;
      92             : }
      93             : 
      94             : // LLT Objects.
      95             : enum {
      96             :   GILLT_s16,
      97             :   GILLT_s32,
      98             :   GILLT_s64,
      99             :   GILLT_s128,
     100             :   GILLT_v2s32,
     101             :   GILLT_v2s64,
     102             :   GILLT_v4s16,
     103             :   GILLT_v4s32,
     104             :   GILLT_v8s8,
     105             :   GILLT_v8s16,
     106             :   GILLT_v16s8,
     107             : };
     108             : const static LLT TypeObjects[] = {
     109             :   LLT::scalar(16),
     110             :   LLT::scalar(32),
     111             :   LLT::scalar(64),
     112             :   LLT::scalar(128),
     113             :   LLT::vector(2, 32),
     114             :   LLT::vector(2, 64),
     115             :   LLT::vector(4, 16),
     116             :   LLT::vector(4, 32),
     117             :   LLT::vector(8, 8),
     118             :   LLT::vector(8, 16),
     119             :   LLT::vector(16, 8),
     120       99237 : };
     121             : 
     122             : // Feature bitsets.
     123             : enum {
     124             :   GIFBS_Invalid,
     125             :   GIFBS_HasCRC,
     126             :   GIFBS_HasCrypto,
     127             :   GIFBS_HasDotProd,
     128             :   GIFBS_HasFPARMv8,
     129             :   GIFBS_HasFullFP16,
     130             :   GIFBS_HasFuseAES,
     131             :   GIFBS_HasLSE,
     132             :   GIFBS_HasNEON,
     133             :   GIFBS_HasRDM,
     134             :   GIFBS_IsBE,
     135             :   GIFBS_IsLE,
     136             :   GIFBS_HasFullFP16_HasNEON,
     137             :   GIFBS_HasNEON_HasRDM,
     138             : };
     139             : const static PredicateBitset FeatureBitsets[] {
     140             :   {}, // GIFBS_Invalid
     141             :   {Feature_HasCRCBit, },
     142             :   {Feature_HasCryptoBit, },
     143             :   {Feature_HasDotProdBit, },
     144             :   {Feature_HasFPARMv8Bit, },
     145             :   {Feature_HasFullFP16Bit, },
     146             :   {Feature_HasFuseAESBit, },
     147             :   {Feature_HasLSEBit, },
     148             :   {Feature_HasNEONBit, },
     149             :   {Feature_HasRDMBit, },
     150             :   {Feature_IsBEBit, },
     151             :   {Feature_IsLEBit, },
     152             :   {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
     153             :   {Feature_HasNEONBit, Feature_HasRDMBit, },
     154       99237 : };
     155             : 
     156             : // ComplexPattern predicates.
     157             : enum {
     158             :   GICP_Invalid,
     159             :   GICP_gi_addsub_shifted_imm32,
     160             :   GICP_gi_addsub_shifted_imm64,
     161             :   GICP_gi_am_indexed128,
     162             :   GICP_gi_am_indexed16,
     163             :   GICP_gi_am_indexed32,
     164             :   GICP_gi_am_indexed64,
     165             :   GICP_gi_am_indexed8,
     166             :   GICP_gi_am_unscaled128,
     167             :   GICP_gi_am_unscaled16,
     168             :   GICP_gi_am_unscaled32,
     169             :   GICP_gi_am_unscaled64,
     170             :   GICP_gi_am_unscaled8,
     171             : };
     172             : // See constructor for table contents
     173             : 
     174             : // PatFrag predicates.
     175             : enum {
     176             :   GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1,
     177             :   GIPFP_I64_Predicate_VectorIndexB,
     178             :   GIPFP_I64_Predicate_VectorIndexD,
     179             :   GIPFP_I64_Predicate_VectorIndexH,
     180             :   GIPFP_I64_Predicate_VectorIndexS,
     181             :   GIPFP_I64_Predicate_i64imm_32bit,
     182             :   GIPFP_I64_Predicate_imm0_1,
     183             :   GIPFP_I64_Predicate_imm0_127,
     184             :   GIPFP_I64_Predicate_imm0_15,
     185             :   GIPFP_I64_Predicate_imm0_255,
     186             :   GIPFP_I64_Predicate_imm0_31,
     187             :   GIPFP_I64_Predicate_imm0_63,
     188             :   GIPFP_I64_Predicate_imm0_65535,
     189             :   GIPFP_I64_Predicate_imm0_7,
     190             :   GIPFP_I64_Predicate_imm32_0_15,
     191             :   GIPFP_I64_Predicate_imm32_0_31,
     192             :   GIPFP_I64_Predicate_maski16_or_more,
     193             :   GIPFP_I64_Predicate_maski8_or_more,
     194             :   GIPFP_I64_Predicate_s64imm_32bit,
     195             :   GIPFP_I64_Predicate_simm4s1,
     196             :   GIPFP_I64_Predicate_simm4s16,
     197             :   GIPFP_I64_Predicate_simm4s2,
     198             :   GIPFP_I64_Predicate_simm4s3,
     199             :   GIPFP_I64_Predicate_simm4s4,
     200             :   GIPFP_I64_Predicate_simm5_32b,
     201             :   GIPFP_I64_Predicate_simm5_64b,
     202             :   GIPFP_I64_Predicate_simm6_32b,
     203             :   GIPFP_I64_Predicate_simm6s1,
     204             :   GIPFP_I64_Predicate_simm9,
     205             :   GIPFP_I64_Predicate_sve_pred_enum,
     206             :   GIPFP_I64_Predicate_sve_prfop,
     207             :   GIPFP_I64_Predicate_tbz_imm0_31_diag,
     208             :   GIPFP_I64_Predicate_tbz_imm0_31_nodiag,
     209             :   GIPFP_I64_Predicate_tbz_imm32_63,
     210             :   GIPFP_I64_Predicate_uimm5s2,
     211             :   GIPFP_I64_Predicate_uimm5s4,
     212             :   GIPFP_I64_Predicate_uimm5s8,
     213             :   GIPFP_I64_Predicate_uimm6s1,
     214             :   GIPFP_I64_Predicate_uimm6s2,
     215             :   GIPFP_I64_Predicate_uimm6s4,
     216             :   GIPFP_I64_Predicate_uimm6s8,
     217             :   GIPFP_I64_Predicate_vecshiftL16,
     218             :   GIPFP_I64_Predicate_vecshiftL32,
     219             :   GIPFP_I64_Predicate_vecshiftL64,
     220             :   GIPFP_I64_Predicate_vecshiftL8,
     221             :   GIPFP_I64_Predicate_vecshiftR16,
     222             :   GIPFP_I64_Predicate_vecshiftR16Narrow,
     223             :   GIPFP_I64_Predicate_vecshiftR32,
     224             :   GIPFP_I64_Predicate_vecshiftR32Narrow,
     225             :   GIPFP_I64_Predicate_vecshiftR64,
     226             :   GIPFP_I64_Predicate_vecshiftR64Narrow,
     227             :   GIPFP_I64_Predicate_vecshiftR8,
     228             : };
     229           5 : bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
     230           5 :   switch (PredicateID) {
     231           0 :   case GIPFP_I64_Predicate_VectorIndex1: {
     232             :     
     233           0 :   return ((uint64_t)Imm) == 1;
     234             : 
     235             :     llvm_unreachable("ImmediateCode should have returned");
     236             :     return false;
     237             :   }
     238           0 :   case GIPFP_I64_Predicate_VectorIndexB: {
     239             :     
     240           0 :   return ((uint64_t)Imm) < 16;
     241             : 
     242             :     llvm_unreachable("ImmediateCode should have returned");
     243             :     return false;
     244             :   }
     245           0 :   case GIPFP_I64_Predicate_VectorIndexD: {
     246             :     
     247           0 :   return ((uint64_t)Imm) < 2;
     248             : 
     249             :     llvm_unreachable("ImmediateCode should have returned");
     250             :     return false;
     251             :   }
     252           0 :   case GIPFP_I64_Predicate_VectorIndexH: {
     253             :     
     254           0 :   return ((uint64_t)Imm) < 8;
     255             : 
     256             :     llvm_unreachable("ImmediateCode should have returned");
     257             :     return false;
     258             :   }
     259           0 :   case GIPFP_I64_Predicate_VectorIndexS: {
     260             :     
     261           0 :   return ((uint64_t)Imm) < 4;
     262             : 
     263             :     llvm_unreachable("ImmediateCode should have returned");
     264             :     return false;
     265             :   }
     266           0 :   case GIPFP_I64_Predicate_i64imm_32bit: {
     267             :     
     268           0 :   return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
     269             : 
     270             :     llvm_unreachable("ImmediateCode should have returned");
     271             :     return false;
     272             :   }
     273           0 :   case GIPFP_I64_Predicate_imm0_1: {
     274             :     
     275           0 :   return ((uint64_t)Imm) < 2;
     276             : 
     277             :     llvm_unreachable("ImmediateCode should have returned");
     278             :     return false;
     279             :   }
     280           1 :   case GIPFP_I64_Predicate_imm0_127: {
     281             :     
     282           1 :   return ((uint32_t)Imm) < 128;
     283             : 
     284             :     llvm_unreachable("ImmediateCode should have returned");
     285             :     return false;
     286             :   }
     287           0 :   case GIPFP_I64_Predicate_imm0_15: {
     288             :     
     289           0 :   return ((uint64_t)Imm) < 16;
     290             : 
     291             :     llvm_unreachable("ImmediateCode should have returned");
     292             :     return false;
     293             :   }
     294           0 :   case GIPFP_I64_Predicate_imm0_255: {
     295             :     
     296           0 :   return ((uint32_t)Imm) < 256;
     297             : 
     298             :     llvm_unreachable("ImmediateCode should have returned");
     299             :     return false;
     300             :   }
     301           0 :   case GIPFP_I64_Predicate_imm0_31: {
     302             :     
     303           0 :   return ((uint64_t)Imm) < 32;
     304             : 
     305             :     llvm_unreachable("ImmediateCode should have returned");
     306             :     return false;
     307             :   }
     308           2 :   case GIPFP_I64_Predicate_imm0_63: {
     309             :     
     310           2 :   return ((uint64_t)Imm) < 64;
     311             : 
     312             :     llvm_unreachable("ImmediateCode should have returned");
     313             :     return false;
     314             :   }
     315           0 :   case GIPFP_I64_Predicate_imm0_65535: {
     316             :     
     317           0 :   return ((uint32_t)Imm) < 65536;
     318             : 
     319             :     llvm_unreachable("ImmediateCode should have returned");
     320             :     return false;
     321             :   }
     322           0 :   case GIPFP_I64_Predicate_imm0_7: {
     323             :     
     324           0 :   return ((uint64_t)Imm) < 8;
     325             : 
     326             :     llvm_unreachable("ImmediateCode should have returned");
     327             :     return false;
     328             :   }
     329           0 :   case GIPFP_I64_Predicate_imm32_0_15: {
     330             :     
     331           0 :   return ((uint32_t)Imm) < 16;
     332             : 
     333             :     llvm_unreachable("ImmediateCode should have returned");
     334             :     return false;
     335             :   }
     336           0 :   case GIPFP_I64_Predicate_imm32_0_31: {
     337             :     
     338           0 :   return ((uint64_t)Imm) < 32;
     339             : 
     340             :     llvm_unreachable("ImmediateCode should have returned");
     341             :     return false;
     342             :   }
     343           0 :   case GIPFP_I64_Predicate_maski16_or_more: {
     344           0 :      return (Imm & 0xffff) == 0xffff; 
     345             :     llvm_unreachable("ImmediateCode should have returned");
     346             :     return false;
     347             :   }
     348           0 :   case GIPFP_I64_Predicate_maski8_or_more: {
     349           0 :      return (Imm & 0xff) == 0xff; 
     350             :     llvm_unreachable("ImmediateCode should have returned");
     351             :     return false;
     352             :   }
     353           1 :   case GIPFP_I64_Predicate_s64imm_32bit: {
     354             :     
     355             :   int64_t Imm64 = static_cast<int64_t>(Imm);
     356           1 :   return Imm64 >= std::numeric_limits<int32_t>::min() &&
     357           1 :          Imm64 <= std::numeric_limits<int32_t>::max();
     358             : 
     359             :     llvm_unreachable("ImmediateCode should have returned");
     360             :     return false;
     361             :   }
     362           0 :   case GIPFP_I64_Predicate_simm4s1: {
     363           0 :      return Imm >=-8  && Imm <= 7; 
     364             :     llvm_unreachable("ImmediateCode should have returned");
     365             :     return false;
     366             :   }
     367           0 :   case GIPFP_I64_Predicate_simm4s16: {
     368           0 :      return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; 
     369             :     llvm_unreachable("ImmediateCode should have returned");
     370             :     return false;
     371             :   }
     372           0 :   case GIPFP_I64_Predicate_simm4s2: {
     373           0 :      return Imm >=-16  && Imm <= 14 && (Imm % 2) == 0x0; 
     374             :     llvm_unreachable("ImmediateCode should have returned");
     375             :     return false;
     376             :   }
     377           0 :   case GIPFP_I64_Predicate_simm4s3: {
     378           0 :      return Imm >=-24  && Imm <= 21 && (Imm % 3) == 0x0; 
     379             :     llvm_unreachable("ImmediateCode should have returned");
     380             :     return false;
     381             :   }
     382           0 :   case GIPFP_I64_Predicate_simm4s4: {
     383           0 :      return Imm >=-32  && Imm <= 28 && (Imm % 4) == 0x0; 
     384             :     llvm_unreachable("ImmediateCode should have returned");
     385             :     return false;
     386             :   }
     387           0 :   case GIPFP_I64_Predicate_simm5_32b: {
     388           0 :      return Imm >= -16 && Imm < 16; 
     389             :     llvm_unreachable("ImmediateCode should have returned");
     390             :     return false;
     391             :   }
     392           0 :   case GIPFP_I64_Predicate_simm5_64b: {
     393           0 :      return Imm >= -16 && Imm < 16; 
     394             :     llvm_unreachable("ImmediateCode should have returned");
     395             :     return false;
     396             :   }
     397           0 :   case GIPFP_I64_Predicate_simm6_32b: {
     398           0 :      return Imm >= -32 && Imm < 32; 
     399             :     llvm_unreachable("ImmediateCode should have returned");
     400             :     return false;
     401             :   }
     402           0 :   case GIPFP_I64_Predicate_simm6s1: {
     403           0 :      return Imm >= -32 && Imm < 32; 
     404             :     llvm_unreachable("ImmediateCode should have returned");
     405             :     return false;
     406             :   }
     407           0 :   case GIPFP_I64_Predicate_simm9: {
     408           0 :      return Imm >= -256 && Imm < 256; 
     409             :     llvm_unreachable("ImmediateCode should have returned");
     410             :     return false;
     411             :   }
     412           0 :   case GIPFP_I64_Predicate_sve_pred_enum: {
     413             :     
     414           0 :   return (((uint32_t)Imm) < 32);
     415             :   
     416             :     llvm_unreachable("ImmediateCode should have returned");
     417             :     return false;
     418             :   }
     419           0 :   case GIPFP_I64_Predicate_sve_prfop: {
     420             :     
     421           0 :     return (((uint32_t)Imm) <= 15);
     422             :   
     423             :     llvm_unreachable("ImmediateCode should have returned");
     424             :     return false;
     425             :   }
     426           0 :   case GIPFP_I64_Predicate_tbz_imm0_31_diag: {
     427             :     
     428           0 :   return (((uint32_t)Imm) < 32);
     429             : 
     430             :     llvm_unreachable("ImmediateCode should have returned");
     431             :     return false;
     432             :   }
     433           0 :   case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: {
     434             :     
     435           0 :   return (((uint32_t)Imm) < 32);
     436             : 
     437             :     llvm_unreachable("ImmediateCode should have returned");
     438             :     return false;
     439             :   }
     440           0 :   case GIPFP_I64_Predicate_tbz_imm32_63: {
     441             :     
     442           0 :   return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
     443             : 
     444             :     llvm_unreachable("ImmediateCode should have returned");
     445             :     return false;
     446             :   }
     447           0 :   case GIPFP_I64_Predicate_uimm5s2: {
     448           0 :      return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 
     449             :     llvm_unreachable("ImmediateCode should have returned");
     450             :     return false;
     451             :   }
     452           0 :   case GIPFP_I64_Predicate_uimm5s4: {
     453           0 :      return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 
     454             :     llvm_unreachable("ImmediateCode should have returned");
     455             :     return false;
     456             :   }
     457           0 :   case GIPFP_I64_Predicate_uimm5s8: {
     458           0 :      return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 
     459             :     llvm_unreachable("ImmediateCode should have returned");
     460             :     return false;
     461             :   }
     462           0 :   case GIPFP_I64_Predicate_uimm6s1: {
     463           0 :      return Imm >= 0 && Imm < 64; 
     464             :     llvm_unreachable("ImmediateCode should have returned");
     465             :     return false;
     466             :   }
     467           0 :   case GIPFP_I64_Predicate_uimm6s2: {
     468           0 :      return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); 
     469             :     llvm_unreachable("ImmediateCode should have returned");
     470             :     return false;
     471             :   }
     472           0 :   case GIPFP_I64_Predicate_uimm6s4: {
     473           0 :      return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); 
     474             :     llvm_unreachable("ImmediateCode should have returned");
     475             :     return false;
     476             :   }
     477           0 :   case GIPFP_I64_Predicate_uimm6s8: {
     478           0 :      return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); 
     479             :     llvm_unreachable("ImmediateCode should have returned");
     480             :     return false;
     481             :   }
     482           0 :   case GIPFP_I64_Predicate_vecshiftL16: {
     483             :     
     484           0 :   return (((uint32_t)Imm) < 16);
     485             : 
     486             :     llvm_unreachable("ImmediateCode should have returned");
     487             :     return false;
     488             :   }
     489           0 :   case GIPFP_I64_Predicate_vecshiftL32: {
     490             :     
     491           0 :   return (((uint32_t)Imm) < 32);
     492             : 
     493             :     llvm_unreachable("ImmediateCode should have returned");
     494             :     return false;
     495             :   }
     496           0 :   case GIPFP_I64_Predicate_vecshiftL64: {
     497             :     
     498           0 :   return (((uint32_t)Imm) < 64);
     499             : 
     500             :     llvm_unreachable("ImmediateCode should have returned");
     501             :     return false;
     502             :   }
     503           0 :   case GIPFP_I64_Predicate_vecshiftL8: {
     504             :     
     505           0 :   return (((uint32_t)Imm) < 8);
     506             : 
     507             :     llvm_unreachable("ImmediateCode should have returned");
     508             :     return false;
     509             :   }
     510           0 :   case GIPFP_I64_Predicate_vecshiftR16: {
     511             :     
     512           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
     513             : 
     514             :     llvm_unreachable("ImmediateCode should have returned");
     515             :     return false;
     516             :   }
     517           0 :   case GIPFP_I64_Predicate_vecshiftR16Narrow: {
     518             :     
     519           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
     520             : 
     521             :     llvm_unreachable("ImmediateCode should have returned");
     522             :     return false;
     523             :   }
     524           0 :   case GIPFP_I64_Predicate_vecshiftR32: {
     525             :     
     526           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
     527             : 
     528             :     llvm_unreachable("ImmediateCode should have returned");
     529             :     return false;
     530             :   }
     531           0 :   case GIPFP_I64_Predicate_vecshiftR32Narrow: {
     532             :     
     533           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
     534             : 
     535             :     llvm_unreachable("ImmediateCode should have returned");
     536             :     return false;
     537             :   }
     538           1 :   case GIPFP_I64_Predicate_vecshiftR64: {
     539             :     
     540           1 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
     541             : 
     542             :     llvm_unreachable("ImmediateCode should have returned");
     543             :     return false;
     544             :   }
     545           0 :   case GIPFP_I64_Predicate_vecshiftR64Narrow: {
     546             :     
     547           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
     548             : 
     549             :     llvm_unreachable("ImmediateCode should have returned");
     550             :     return false;
     551             :   }
     552           0 :   case GIPFP_I64_Predicate_vecshiftR8: {
     553             :     
     554           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
     555             : 
     556             :     llvm_unreachable("ImmediateCode should have returned");
     557             :     return false;
     558             :   }
     559             :   }
     560           0 :   llvm_unreachable("Unknown predicate");
     561             :   return false;
     562             : }
     563             : // PatFrag predicates.
     564             : enum {
     565             :   GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
     566             :   GIPFP_APFloat_Predicate_fpimm16,
     567             :   GIPFP_APFloat_Predicate_fpimm32,
     568             :   GIPFP_APFloat_Predicate_fpimm64,
     569             :   GIPFP_APFloat_Predicate_simdimmtype10,
     570             : };
     571          59 : bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
     572          59 :   switch (PredicateID) {
     573          59 :   case GIPFP_APFloat_Predicate_fpimm0: {
     574             :     
     575          59 :   return Imm.isExactlyValue(+0.0);
     576             : 
     577             :     llvm_unreachable("ImmediateCode should have returned");
     578             :     return false;
     579             :   }
     580           0 :   case GIPFP_APFloat_Predicate_fpimm16: {
     581             :     
     582           0 :       return AArch64_AM::getFP16Imm(Imm) != -1;
     583             :     
     584             :     llvm_unreachable("ImmediateCode should have returned");
     585             :     return false;
     586             :   }
     587           0 :   case GIPFP_APFloat_Predicate_fpimm32: {
     588             :     
     589           0 :       return AArch64_AM::getFP32Imm(Imm) != -1;
     590             :     
     591             :     llvm_unreachable("ImmediateCode should have returned");
     592             :     return false;
     593             :   }
     594           0 :   case GIPFP_APFloat_Predicate_fpimm64: {
     595             :     
     596           0 :       return AArch64_AM::getFP64Imm(Imm) != -1;
     597             :     
     598             :     llvm_unreachable("ImmediateCode should have returned");
     599             :     return false;
     600             :   }
     601           0 :   case GIPFP_APFloat_Predicate_simdimmtype10: {
     602             :     
     603             :       return AArch64_AM::isAdvSIMDModImmType10(
     604           0 :                  Imm.bitcastToAPInt().getZExtValue());
     605             :     
     606             :     llvm_unreachable("ImmediateCode should have returned");
     607             :     return false;
     608             :   }
     609             :   }
     610           0 :   llvm_unreachable("Unknown predicate");
     611             :   return false;
     612             : }
     613             : // PatFrag predicates.
     614             : enum {
     615             :   GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1,
     616             :   GIPFP_APInt_Predicate_logical_imm64,
     617             : };
     618           0 : bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
     619           0 :   switch (PredicateID) {
     620             :   case GIPFP_APInt_Predicate_logical_imm32: {
     621             :     
     622           0 :   return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
     623             : 
     624             :     llvm_unreachable("ImmediateCode should have returned");
     625             :     return false;
     626             :   }
     627             :   case GIPFP_APInt_Predicate_logical_imm64: {
     628             :     
     629           0 :   return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
     630             : 
     631             :     llvm_unreachable("ImmediateCode should have returned");
     632             :     return false;
     633             :   }
     634             :   }
     635           0 :   llvm_unreachable("Unknown predicate");
     636             :   return false;
     637             : }
     638             : 
     639             : AArch64InstructionSelector::ComplexMatcherMemFn
     640             : AArch64InstructionSelector::ComplexPredicateFns[] = {
     641             :   nullptr, // GICP_Invalid
     642             :   &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
     643             :   &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
     644             :   &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
     645             :   &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
     646             :   &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
     647             :   &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
     648             :   &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
     649             :   &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
     650             :   &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
     651             :   &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
     652             :   &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
     653             :   &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
     654             : };
     655             : 
     656             : // Custom renderers.
     657             : enum {
     658             :   GICR_Invalid,
     659             :   GICR_renderTruncImm, 
     660             : };
     661             : AArch64InstructionSelector::CustomRendererFn
     662             : AArch64InstructionSelector::CustomRenderers[] = {
     663             :   nullptr, // GICP_Invalid
     664             :   &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm
     665             : };
     666             : 
     667         803 : bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
     668         803 :   MachineFunction &MF = *I.getParent()->getParent();
     669         803 :   MachineRegisterInfo &MRI = MF.getRegInfo();
     670             :   // FIXME: This should be computed on a per-function basis rather than per-insn.
     671         803 :   AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
     672         803 :   const PredicateBitset AvailableFeatures = getAvailableFeatures();
     673             :   NewMIVector OutMIs;
     674             :   State.MIs.clear();
     675         803 :   State.MIs.push_back(&I);
     676             : 
     677         803 :   if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
     678             :     return true;
     679             :   }
     680             : 
     681         304 :   return false;
     682             : }
     683             : 
     684           0 : const int64_t *AArch64InstructionSelector::getMatchTable() const {
     685             :   constexpr static int64_t MatchTable0[] = {
     686             :     GIM_Try, /*On fail goto*//*Label 0*/ 269,
     687             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
     688             :       GIM_Try, /*On fail goto*//*Label 1*/ 136,
     689             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     690             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     691             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     692             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     693             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
     694             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     695             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
     696             :         // No instruction predicates
     697             :         // MIs[0] Rd
     698             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     699             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     700             :         // MIs[0] Operand 1
     701             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
     702             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
     703             :         // MIs[0] Operand 2
     704             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
     705             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
     706             :         // MIs[1] Operand 0
     707             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
     708             :         // MIs[1] Operand 1
     709             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     710             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
     711             :         // MIs[2] Operand 0
     712             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
     713             :         // MIs[2] Rn
     714             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     715             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
     716             :         // MIs[1] C
     717             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     718             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
     719             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
     720             :         // MIs[3] Operand 0
     721             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
     722             :         // MIs[3] Operand 1
     723             :         // No operand predicates
     724             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     725             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
     726             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
     727             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     728             :         // Rule ID 2005
     729             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     730             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
     731             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     732             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
     733             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     734             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
     735             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     736             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     737             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     738             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
     739             :         GIR_EraseFromParent, /*InsnID*/0,
     740             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     741             :         GIR_Done,
     742             :       // Label 1: @136
     743             :       GIM_Try, /*On fail goto*//*Label 2*/ 267,
     744             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     745             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     746             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     747             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     748             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
     749             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     750             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
     751             :         // No instruction predicates
     752             :         // MIs[0] Rd
     753             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     754             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     755             :         // MIs[0] Operand 1
     756             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
     757             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
     758             :         // MIs[0] Operand 2
     759             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
     760             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
     761             :         // MIs[1] Operand 0
     762             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
     763             :         // MIs[1] Operand 1
     764             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     765             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
     766             :         // MIs[2] Operand 0
     767             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
     768             :         // MIs[2] Rn
     769             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     770             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
     771             :         // MIs[1] C
     772             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     773             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
     774             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
     775             :         // MIs[3] Operand 0
     776             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
     777             :         // MIs[3] Operand 1
     778             :         // No operand predicates
     779             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     780             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
     781             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
     782             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     783             :         // Rule ID 2006
     784             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     785             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
     786             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     787             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
     788             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     789             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
     790             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     791             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     792             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     793             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
     794             :         GIR_EraseFromParent, /*InsnID*/0,
     795             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     796             :         GIR_Done,
     797             :       // Label 2: @267
     798             :       GIM_Reject,
     799             :       GIR_Done,
     800             :     // Label 0: @269
     801             :     GIM_Try, /*On fail goto*//*Label 3*/ 594,
     802             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
     803             :       GIM_Try, /*On fail goto*//*Label 4*/ 327,
     804             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     805             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     806             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     807             :         // MIs[0] Rt
     808             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     809             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     810             :         // MIs[0] Operand 1
     811             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     812             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
     813             :         // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     814             :         // Rule ID 191
     815             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui,
     816             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     817             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     818             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     819             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     820             :         GIR_EraseFromParent, /*InsnID*/0,
     821             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     822             :         GIR_Done,
     823             :       // Label 4: @327
     824             :       GIM_Try, /*On fail goto*//*Label 5*/ 380,
     825             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     826             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     827             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     828             :         // MIs[0] Rt
     829             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     830             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
     831             :         // MIs[0] Operand 1
     832             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     833             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
     834             :         // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     835             :         // Rule ID 192
     836             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui,
     837             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     838             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     839             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     840             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     841             :         GIR_EraseFromParent, /*InsnID*/0,
     842             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     843             :         GIR_Done,
     844             :       // Label 5: @380
     845             :       GIM_Try, /*On fail goto*//*Label 6*/ 433,
     846             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     847             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     848             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     849             :         // MIs[0] Rt
     850             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
     851             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID,
     852             :         // MIs[0] Operand 1
     853             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     854             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
     855             :         // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     856             :         // Rule ID 194
     857             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui,
     858             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     859             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     860             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     861             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     862             :         GIR_EraseFromParent, /*InsnID*/0,
     863             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     864             :         GIR_Done,
     865             :       // Label 6: @433
     866             :       GIM_Try, /*On fail goto*//*Label 7*/ 486,
     867             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     868             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     869             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     870             :         // MIs[0] Rt
     871             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     872             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
     873             :         // MIs[0] Operand 1
     874             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     875             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
     876             :         // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     877             :         // Rule ID 195
     878             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSui,
     879             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     880             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     881             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     882             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     883             :         GIR_EraseFromParent, /*InsnID*/0,
     884             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     885             :         GIR_Done,
     886             :       // Label 7: @486
     887             :       GIM_Try, /*On fail goto*//*Label 8*/ 539,
     888             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     889             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     890             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     891             :         // MIs[0] Rt
     892             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     893             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
     894             :         // MIs[0] Operand 1
     895             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     896             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
     897             :         // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     898             :         // Rule ID 196
     899             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
     900             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     901             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     902             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     903             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     904             :         GIR_EraseFromParent, /*InsnID*/0,
     905             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     906             :         GIR_Done,
     907             :       // Label 8: @539
     908             :       GIM_Try, /*On fail goto*//*Label 9*/ 592,
     909             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     910             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     911             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     912             :         // MIs[0] Rt
     913             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
     914             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
     915             :         // MIs[0] Operand 1
     916             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     917             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
     918             :         // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     919             :         // Rule ID 197
     920             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
     921             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     922             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     923             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     924             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     925             :         GIR_EraseFromParent, /*InsnID*/0,
     926             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     927             :         GIR_Done,
     928             :       // Label 9: @592
     929             :       GIM_Reject,
     930             :       GIR_Done,
     931             :     // Label 3: @594
     932             :     GIM_Try, /*On fail goto*//*Label 10*/ 866,
     933             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXTLOAD,
     934             :       GIM_Try, /*On fail goto*//*Label 11*/ 652,
     935             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     936             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
     937             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     938             :         // MIs[0] Rt
     939             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     940             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
     941             :         // MIs[0] Operand 1
     942             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     943             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
     944             :         // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     945             :         // Rule ID 200
     946             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWui,
     947             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     948             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     949             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     950             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     951             :         GIR_EraseFromParent, /*InsnID*/0,
     952             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     953             :         GIR_Done,
     954             :       // Label 11: @652
     955             :       GIM_Try, /*On fail goto*//*Label 12*/ 705,
     956             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     957             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
     958             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     959             :         // MIs[0] Rt
     960             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     961             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     962             :         // MIs[0] Operand 1
     963             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     964             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
     965             :         // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     966             :         // Rule ID 201
     967             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXui,
     968             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     969             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     970             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     971             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     972             :         GIR_EraseFromParent, /*InsnID*/0,
     973             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     974             :         GIR_Done,
     975             :       // Label 12: @705
     976             :       GIM_Try, /*On fail goto*//*Label 13*/ 758,
     977             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     978             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
     979             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     980             :         // MIs[0] Rt
     981             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     982             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
     983             :         // MIs[0] Operand 1
     984             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     985             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
     986             :         // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     987             :         // Rule ID 202
     988             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWui,
     989             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     990             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     991             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     992             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     993             :         GIR_EraseFromParent, /*InsnID*/0,
     994             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     995             :         GIR_Done,
     996             :       // Label 13: @758
     997             :       GIM_Try, /*On fail goto*//*Label 14*/ 811,
     998             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     999             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    1000             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1001             :         // MIs[0] Rt
    1002             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1003             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1004             :         // MIs[0] Operand 1
    1005             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1006             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
    1007             :         // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
    1008             :         // Rule ID 203
    1009             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXui,
    1010             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1011             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1012             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1013             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1014             :         GIR_EraseFromParent, /*InsnID*/0,
    1015             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1016             :         GIR_Done,
    1017             :       // Label 14: @811
    1018             :       GIM_Try, /*On fail goto*//*Label 15*/ 864,
    1019             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1020             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
    1021             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1022             :         // MIs[0] Rt
    1023             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1024             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1025             :         // MIs[0] Operand 1
    1026             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1027             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
    1028             :         // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
    1029             :         // Rule ID 204
    1030             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWui,
    1031             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1032             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1033             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1034             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1035             :         GIR_EraseFromParent, /*InsnID*/0,
    1036             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1037             :         GIR_Done,
    1038             :       // Label 15: @864
    1039             :       GIM_Reject,
    1040             :       GIR_Done,
    1041             :     // Label 10: @866
    1042             :     GIM_Try, /*On fail goto*//*Label 16*/ 2591,
    1043             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE,
    1044             :       GIM_Try, /*On fail goto*//*Label 17*/ 921,
    1045             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1046             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1047             :         // MIs[0] Rt
    1048             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1049             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1050             :         // MIs[0] Operand 1
    1051             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1052             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1053             :         // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1054             :         // Rule ID 237
    1055             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui,
    1056             :         GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt
    1057             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1058             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1059             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1060             :         GIR_EraseFromParent, /*InsnID*/0,
    1061             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1062             :         GIR_Done,
    1063             :       // Label 17: @921
    1064             :       GIM_Try, /*On fail goto*//*Label 18*/ 971,
    1065             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1066             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1067             :         // MIs[0] Rt
    1068             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1069             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    1070             :         // MIs[0] Operand 1
    1071             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1072             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
    1073             :         // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
    1074             :         // Rule ID 238
    1075             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui,
    1076             :         GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt
    1077             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1078             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1079             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1080             :         GIR_EraseFromParent, /*InsnID*/0,
    1081             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1082             :         GIR_Done,
    1083             :       // Label 18: @971
    1084             :       GIM_Try, /*On fail goto*//*Label 19*/ 1020,
    1085             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1086             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1087             :         // MIs[0] Rt
    1088             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
    1089             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID,
    1090             :         // MIs[0] Operand 1
    1091             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1092             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
    1093             :         // (st FPR16Op:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHui FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
    1094             :         // Rule ID 240
    1095             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui,
    1096             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1097             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1098             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1099             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1100             :         GIR_EraseFromParent, /*InsnID*/0,
    1101             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1102             :         GIR_Done,
    1103             :       // Label 19: @1020
    1104             :       GIM_Try, /*On fail goto*//*Label 20*/ 1069,
    1105             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1106             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1107             :         // MIs[0] Rt
    1108             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1109             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    1110             :         // MIs[0] Operand 1
    1111             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1112             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
    1113             :         // (st FPR32Op:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
    1114             :         // Rule ID 241
    1115             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSui,
    1116             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1117             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1118             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1119             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1120             :         GIR_EraseFromParent, /*InsnID*/0,
    1121             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1122             :         GIR_Done,
    1123             :       // Label 20: @1069
    1124             :       GIM_Try, /*On fail goto*//*Label 21*/ 1118,
    1125             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1126             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1127             :         // MIs[0] Rt
    1128             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1129             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1130             :         // MIs[0] Operand 1
    1131             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1132             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1133             :         // (st FPR64Op:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1134             :         // Rule ID 242
    1135             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1136             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1137             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1138             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1139             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1140             :         GIR_EraseFromParent, /*InsnID*/0,
    1141             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1142             :         GIR_Done,
    1143             :       // Label 21: @1118
    1144             :       GIM_Try, /*On fail goto*//*Label 22*/ 1167,
    1145             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1146             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1147             :         // MIs[0] Rt
    1148             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1149             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1150             :         // MIs[0] Operand 1
    1151             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1152             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1153             :         // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1154             :         // Rule ID 2244
    1155             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1156             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1157             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1158             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1159             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1160             :         GIR_EraseFromParent, /*InsnID*/0,
    1161             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1162             :         GIR_Done,
    1163             :       // Label 22: @1167
    1164             :       GIM_Try, /*On fail goto*//*Label 23*/ 1216,
    1165             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1166             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1167             :         // MIs[0] Rt
    1168             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1169             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1170             :         // MIs[0] Operand 1
    1171             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1172             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1173             :         // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1174             :         // Rule ID 2245
    1175             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1176             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1177             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1178             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1179             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1180             :         GIR_EraseFromParent, /*InsnID*/0,
    1181             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1182             :         GIR_Done,
    1183             :       // Label 23: @1216
    1184             :       GIM_Try, /*On fail goto*//*Label 24*/ 1267,
    1185             :         GIM_CheckFeatures, GIFBS_IsLE,
    1186             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1187             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1188             :         // MIs[0] Rt
    1189             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1190             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1191             :         // MIs[0] Operand 1
    1192             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1193             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1194             :         // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1195             :         // Rule ID 2246
    1196             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1197             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1198             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1199             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1200             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1201             :         GIR_EraseFromParent, /*InsnID*/0,
    1202             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1203             :         GIR_Done,
    1204             :       // Label 24: @1267
    1205             :       GIM_Try, /*On fail goto*//*Label 25*/ 1318,
    1206             :         GIM_CheckFeatures, GIFBS_IsLE,
    1207             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1208             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1209             :         // MIs[0] Rt
    1210             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    1211             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1212             :         // MIs[0] Operand 1
    1213             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1214             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1215             :         // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1216             :         // Rule ID 2247
    1217             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1218             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1219             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1220             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1221             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1222             :         GIR_EraseFromParent, /*InsnID*/0,
    1223             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1224             :         GIR_Done,
    1225             :       // Label 25: @1318
    1226             :       GIM_Try, /*On fail goto*//*Label 26*/ 1369,
    1227             :         GIM_CheckFeatures, GIFBS_IsLE,
    1228             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1229             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1230             :         // MIs[0] Rt
    1231             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    1232             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1233             :         // MIs[0] Operand 1
    1234             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1235             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1236             :         // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1237             :         // Rule ID 2248
    1238             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1239             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1240             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1241             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1242             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1243             :         GIR_EraseFromParent, /*InsnID*/0,
    1244             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1245             :         GIR_Done,
    1246             :       // Label 26: @1369
    1247             :       GIM_Try, /*On fail goto*//*Label 27*/ 1420,
    1248             :         GIM_CheckFeatures, GIFBS_IsLE,
    1249             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1250             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1251             :         // MIs[0] Rt
    1252             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1253             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1254             :         // MIs[0] Operand 1
    1255             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1256             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1257             :         // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1258             :         // Rule ID 2249
    1259             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1260             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1261             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1262             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1263             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1264             :         GIR_EraseFromParent, /*InsnID*/0,
    1265             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1266             :         GIR_Done,
    1267             :       // Label 27: @1420
    1268             :       GIM_Try, /*On fail goto*//*Label 28*/ 1471,
    1269             :         GIM_CheckFeatures, GIFBS_IsLE,
    1270             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1271             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1272             :         // MIs[0] Rt
    1273             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    1274             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1275             :         // MIs[0] Operand 1
    1276             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1277             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1278             :         // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1279             :         // Rule ID 2250
    1280             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1281             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1282             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1283             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1284             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1285             :         GIR_EraseFromParent, /*InsnID*/0,
    1286             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1287             :         GIR_Done,
    1288             :       // Label 28: @1471
    1289             :       GIM_Try, /*On fail goto*//*Label 29*/ 1520,
    1290             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1291             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1292             :         // MIs[0] Rt
    1293             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    1294             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1295             :         // MIs[0] Operand 1
    1296             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1297             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1298             :         // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1299             :         // Rule ID 2251
    1300             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1301             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1302             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1303             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1304             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1305             :         GIR_EraseFromParent, /*InsnID*/0,
    1306             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1307             :         GIR_Done,
    1308             :       // Label 29: @1520
    1309             :       GIM_Try, /*On fail goto*//*Label 30*/ 1571,
    1310             :         GIM_CheckFeatures, GIFBS_IsLE,
    1311             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1312             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1313             :         // MIs[0] Rt
    1314             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1315             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1316             :         // MIs[0] Operand 1
    1317             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1318             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1319             :         // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1320             :         // Rule ID 2252
    1321             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1322             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1323             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1324             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1325             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1326             :         GIR_EraseFromParent, /*InsnID*/0,
    1327             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1328             :         GIR_Done,
    1329             :       // Label 30: @1571
    1330             :       GIM_Try, /*On fail goto*//*Label 31*/ 1622,
    1331             :         GIM_CheckFeatures, GIFBS_IsLE,
    1332             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1333             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1334             :         // MIs[0] Rt
    1335             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    1336             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1337             :         // MIs[0] Operand 1
    1338             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1339             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1340             :         // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1341             :         // Rule ID 2253
    1342             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1343             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1344             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1345             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1346             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1347             :         GIR_EraseFromParent, /*InsnID*/0,
    1348             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1349             :         GIR_Done,
    1350             :       // Label 31: @1622
    1351             :       GIM_Try, /*On fail goto*//*Label 32*/ 1673,
    1352             :         GIM_CheckFeatures, GIFBS_IsLE,
    1353             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1354             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1355             :         // MIs[0] Rt
    1356             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    1357             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1358             :         // MIs[0] Operand 1
    1359             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1360             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1361             :         // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1362             :         // Rule ID 2254
    1363             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1364             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1365             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1366             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1367             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1368             :         GIR_EraseFromParent, /*InsnID*/0,
    1369             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1370             :         GIR_Done,
    1371             :       // Label 32: @1673
    1372             :       GIM_Try, /*On fail goto*//*Label 33*/ 1724,
    1373             :         GIM_CheckFeatures, GIFBS_IsLE,
    1374             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1375             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1376             :         // MIs[0] Rt
    1377             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    1378             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1379             :         // MIs[0] Operand 1
    1380             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1381             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1382             :         // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1383             :         // Rule ID 2255
    1384             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1385             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1386             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1387             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1388             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1389             :         GIR_EraseFromParent, /*InsnID*/0,
    1390             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1391             :         GIR_Done,
    1392             :       // Label 33: @1724
    1393             :       GIM_Try, /*On fail goto*//*Label 34*/ 1775,
    1394             :         GIM_CheckFeatures, GIFBS_IsLE,
    1395             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1396             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1397             :         // MIs[0] Rt
    1398             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1399             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1400             :         // MIs[0] Operand 1
    1401             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1402             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1403             :         // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1404             :         // Rule ID 2256
    1405             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1406             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1407             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1408             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1409             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1410             :         GIR_EraseFromParent, /*InsnID*/0,
    1411             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1412             :         GIR_Done,
    1413             :       // Label 34: @1775
    1414             :       GIM_Try, /*On fail goto*//*Label 35*/ 1826,
    1415             :         GIM_CheckFeatures, GIFBS_IsLE,
    1416             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1417             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1418             :         // MIs[0] Rt
    1419             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    1420             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1421             :         // MIs[0] Operand 1
    1422             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1423             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1424             :         // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1425             :         // Rule ID 2257
    1426             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1427             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1428             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1429             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1430             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1431             :         GIR_EraseFromParent, /*InsnID*/0,
    1432             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1433             :         GIR_Done,
    1434             :       // Label 35: @1826
    1435             :       GIM_Try, /*On fail goto*//*Label 36*/ 1877,
    1436             :         GIM_CheckFeatures, GIFBS_IsLE,
    1437             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1438             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1439             :         // MIs[0] Rt
    1440             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    1441             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1442             :         // MIs[0] Operand 1
    1443             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1444             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1445             :         // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1446             :         // Rule ID 2258
    1447             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1448             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1449             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1450             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1451             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1452             :         GIR_EraseFromParent, /*InsnID*/0,
    1453             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1454             :         GIR_Done,
    1455             :       // Label 36: @1877
    1456             :       GIM_Try, /*On fail goto*//*Label 37*/ 1928,
    1457             :         GIM_CheckFeatures, GIFBS_IsLE,
    1458             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1459             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1460             :         // MIs[0] Rt
    1461             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1462             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1463             :         // MIs[0] Operand 1
    1464             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1465             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    1466             :         // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1467             :         // Rule ID 2270
    1468             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    1469             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1470             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1471             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1472             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1473             :         GIR_EraseFromParent, /*InsnID*/0,
    1474             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1475             :         GIR_Done,
    1476             :       // Label 37: @1928
    1477             :       GIM_Try, /*On fail goto*//*Label 38*/ 1979,
    1478             :         GIM_CheckFeatures, GIFBS_IsLE,
    1479             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1480             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1481             :         // MIs[0] Rt
    1482             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    1483             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1484             :         // MIs[0] Operand 1
    1485             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1486             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    1487             :         // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1488             :         // Rule ID 2271
    1489             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    1490             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1491             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1492             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1493             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1494             :         GIR_EraseFromParent, /*InsnID*/0,
    1495             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1496             :         GIR_Done,
    1497             :       // Label 38: @1979
    1498             :       GIM_Try, /*On fail goto*//*Label 39*/ 2030,
    1499             :         GIM_CheckFeatures, GIFBS_IsLE,
    1500             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1501             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1502             :         // MIs[0] Rt
    1503             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    1504             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1505             :         // MIs[0] Operand 1
    1506             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1507             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    1508             :         // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1509             :         // Rule ID 2272
    1510             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    1511             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1512             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1513             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1514             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1515             :         GIR_EraseFromParent, /*InsnID*/0,
    1516             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1517             :         GIR_Done,
    1518             :       // Label 39: @2030
    1519             :       GIM_Try, /*On fail goto*//*Label 40*/ 2081,
    1520             :         GIM_CheckFeatures, GIFBS_IsLE,
    1521             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1522             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1523             :         // MIs[0] Rt
    1524             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1525             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1526             :         // MIs[0] Operand 1
    1527             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1528             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    1529             :         // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1530             :         // Rule ID 2273
    1531             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    1532             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1533             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1534             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1535             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1536             :         GIR_EraseFromParent, /*InsnID*/0,
    1537             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1538             :         GIR_Done,
    1539             :       // Label 40: @2081
    1540             :       GIM_Try, /*On fail goto*//*Label 41*/ 2132,
    1541             :         GIM_CheckFeatures, GIFBS_IsLE,
    1542             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1543             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1544             :         // MIs[0] Rt
    1545             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    1546             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1547             :         // MIs[0] Operand 1
    1548             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1549             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    1550             :         // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1551             :         // Rule ID 2274
    1552             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    1553             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1554             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1555             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1556             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1557             :         GIR_EraseFromParent, /*InsnID*/0,
    1558             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1559             :         GIR_Done,
    1560             :       // Label 41: @2132
    1561             :       GIM_Try, /*On fail goto*//*Label 42*/ 2181,
    1562             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1563             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1564             :         // MIs[0] Rt
    1565             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    1566             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1567             :         // MIs[0] Operand 1
    1568             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1569             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1570             :         // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1571             :         // Rule ID 2275
    1572             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1573             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1574             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1575             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1576             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1577             :         GIR_EraseFromParent, /*InsnID*/0,
    1578             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1579             :         GIR_Done,
    1580             :       // Label 42: @2181
    1581             :       GIM_Try, /*On fail goto*//*Label 43*/ 2232,
    1582             :         GIM_CheckFeatures, GIFBS_IsLE,
    1583             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1584             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1585             :         // MIs[0] Rt
    1586             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1587             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1588             :         // MIs[0] Operand 1
    1589             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1590             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1591             :         // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1592             :         // Rule ID 2276
    1593             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1594             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1595             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1596             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1597             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1598             :         GIR_EraseFromParent, /*InsnID*/0,
    1599             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1600             :         GIR_Done,
    1601             :       // Label 43: @2232
    1602             :       GIM_Try, /*On fail goto*//*Label 44*/ 2283,
    1603             :         GIM_CheckFeatures, GIFBS_IsLE,
    1604             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1605             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1606             :         // MIs[0] Rt
    1607             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    1608             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1609             :         // MIs[0] Operand 1
    1610             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1611             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1612             :         // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1613             :         // Rule ID 2277
    1614             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1615             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1616             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1617             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1618             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1619             :         GIR_EraseFromParent, /*InsnID*/0,
    1620             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1621             :         GIR_Done,
    1622             :       // Label 44: @2283
    1623             :       GIM_Try, /*On fail goto*//*Label 45*/ 2334,
    1624             :         GIM_CheckFeatures, GIFBS_IsLE,
    1625             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1626             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1627             :         // MIs[0] Rt
    1628             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    1629             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1630             :         // MIs[0] Operand 1
    1631             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1632             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1633             :         // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1634             :         // Rule ID 2278
    1635             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1636             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1637             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1638             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1639             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1640             :         GIR_EraseFromParent, /*InsnID*/0,
    1641             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1642             :         GIR_Done,
    1643             :       // Label 45: @2334
    1644             :       GIM_Try, /*On fail goto*//*Label 46*/ 2385,
    1645             :         GIM_CheckFeatures, GIFBS_IsLE,
    1646             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1647             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1648             :         // MIs[0] Rt
    1649             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    1650             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1651             :         // MIs[0] Operand 1
    1652             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1653             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1654             :         // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1655             :         // Rule ID 2279
    1656             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1657             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1658             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1659             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1660             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1661             :         GIR_EraseFromParent, /*InsnID*/0,
    1662             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1663             :         GIR_Done,
    1664             :       // Label 46: @2385
    1665             :       GIM_Try, /*On fail goto*//*Label 47*/ 2436,
    1666             :         GIM_CheckFeatures, GIFBS_IsLE,
    1667             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1668             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1669             :         // MIs[0] Rt
    1670             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1671             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1672             :         // MIs[0] Operand 1
    1673             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1674             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1675             :         // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1676             :         // Rule ID 2280
    1677             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1678             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1679             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1680             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1681             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1682             :         GIR_EraseFromParent, /*InsnID*/0,
    1683             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1684             :         GIR_Done,
    1685             :       // Label 47: @2436
    1686             :       GIM_Try, /*On fail goto*//*Label 48*/ 2487,
    1687             :         GIM_CheckFeatures, GIFBS_IsLE,
    1688             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1689             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1690             :         // MIs[0] Rt
    1691             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    1692             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1693             :         // MIs[0] Operand 1
    1694             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1695             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1696             :         // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1697             :         // Rule ID 2281
    1698             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1699             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1700             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1701             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1702             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1703             :         GIR_EraseFromParent, /*InsnID*/0,
    1704             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1705             :         GIR_Done,
    1706             :       // Label 48: @2487
    1707             :       GIM_Try, /*On fail goto*//*Label 49*/ 2538,
    1708             :         GIM_CheckFeatures, GIFBS_IsLE,
    1709             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1710             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1711             :         // MIs[0] Rt
    1712             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    1713             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1714             :         // MIs[0] Operand 1
    1715             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1716             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1717             :         // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1718             :         // Rule ID 2282
    1719             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1720             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1721             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1722             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1723             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1724             :         GIR_EraseFromParent, /*InsnID*/0,
    1725             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1726             :         GIR_Done,
    1727             :       // Label 49: @2538
    1728             :       GIM_Try, /*On fail goto*//*Label 50*/ 2589,
    1729             :         GIM_CheckFeatures, GIFBS_IsLE,
    1730             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1731             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1732             :         // MIs[0] Rt
    1733             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    1734             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1735             :         // MIs[0] Operand 1
    1736             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1737             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    1738             :         // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    1739             :         // Rule ID 2283
    1740             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    1741             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1742             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1743             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1744             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1745             :         GIR_EraseFromParent, /*InsnID*/0,
    1746             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1747             :         GIR_Done,
    1748             :       // Label 50: @2589
    1749             :       GIM_Reject,
    1750             :       GIR_Done,
    1751             :     // Label 16: @2591
    1752             :     GIM_Try, /*On fail goto*//*Label 51*/ 2704,
    1753             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXTLOAD,
    1754             :       GIM_Try, /*On fail goto*//*Label 52*/ 2649,
    1755             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1756             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
    1757             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1758             :         // MIs[0] Rt
    1759             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1760             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    1761             :         // MIs[0] Operand 1
    1762             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1763             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
    1764             :         // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
    1765             :         // Rule ID 198
    1766             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui,
    1767             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1768             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1769             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1770             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1771             :         GIR_EraseFromParent, /*InsnID*/0,
    1772             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1773             :         GIR_Done,
    1774             :       // Label 52: @2649
    1775             :       GIM_Try, /*On fail goto*//*Label 53*/ 2702,
    1776             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1777             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    1778             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1779             :         // MIs[0] Rt
    1780             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1781             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    1782             :         // MIs[0] Operand 1
    1783             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1784             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
    1785             :         // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
    1786             :         // Rule ID 199
    1787             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
    1788             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1789             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1790             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1791             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1792             :         GIR_EraseFromParent, /*InsnID*/0,
    1793             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1794             :         GIR_Done,
    1795             :       // Label 53: @2702
    1796             :       GIM_Reject,
    1797             :       GIR_Done,
    1798             :     // Label 51: @2704
    1799             :     GIM_Try, /*On fail goto*//*Label 54*/ 2951,
    1800             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    1801             :       GIM_Try, /*On fail goto*//*Label 55*/ 2829,
    1802             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1803             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1804             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1805             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1806             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1807             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1808             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1809             :         // No instruction predicates
    1810             :         // MIs[0] Rd
    1811             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1812             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1813             :         // MIs[0] Operand 1
    1814             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1815             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
    1816             :         // MIs[0] Operand 2
    1817             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1818             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1819             :         // MIs[1] Operand 0
    1820             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1821             :         // MIs[1] Operand 1
    1822             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1823             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    1824             :         // MIs[2] Operand 0
    1825             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1826             :         // MIs[2] Rn
    1827             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1828             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1829             :         // MIs[1] Operand 2
    1830             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1831             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
    1832             :         // MIs[3] Operand 0
    1833             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1834             :         // MIs[3] Rm
    1835             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    1836             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1837             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1838             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1839             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1840             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
    1841             :         // Rule ID 2000
    1842             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
    1843             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1844             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1845             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    1846             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    1847             :         GIR_EraseFromParent, /*InsnID*/0,
    1848             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1849             :         GIR_Done,
    1850             :       // Label 55: @2829
    1851             :       GIM_Try, /*On fail goto*//*Label 56*/ 2949,
    1852             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1853             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1854             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1855             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1856             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1857             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1858             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1859             :         // No instruction predicates
    1860             :         // MIs[0] Rd
    1861             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1862             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1863             :         // MIs[0] Operand 1
    1864             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1865             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
    1866             :         // MIs[0] Operand 2
    1867             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1868             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1869             :         // MIs[1] Operand 0
    1870             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1871             :         // MIs[1] Operand 1
    1872             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1873             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    1874             :         // MIs[2] Operand 0
    1875             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1876             :         // MIs[2] Rn
    1877             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1878             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1879             :         // MIs[1] Operand 2
    1880             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1881             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
    1882             :         // MIs[3] Operand 0
    1883             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1884             :         // MIs[3] Rm
    1885             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    1886             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1887             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1888             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1889             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1890             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
    1891             :         // Rule ID 2001
    1892             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
    1893             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1894             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1895             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    1896             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    1897             :         GIR_EraseFromParent, /*InsnID*/0,
    1898             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1899             :         GIR_Done,
    1900             :       // Label 56: @2949
    1901             :       GIM_Reject,
    1902             :       GIR_Done,
    1903             :     // Label 54: @2951
    1904             :     GIM_Try, /*On fail goto*//*Label 57*/ 3682,
    1905             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
    1906             :       GIM_Try, /*On fail goto*//*Label 58*/ 3005,
    1907             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1908             :         // No instruction predicates
    1909             :         // MIs[0] Rd
    1910             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1911             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
    1912             :         // MIs[0] imm
    1913             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1914             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
    1915             :         // MIs[0] Rn
    1916             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1917             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
    1918             :         // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
    1919             :         // Rule ID 3764
    1920             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
    1921             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1922             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    1923             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    1924             :         GIR_EraseFromParent, /*InsnID*/0,
    1925             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1926             :         GIR_Done,
    1927             :       // Label 58: @3005
    1928             :       GIM_Try, /*On fail goto*//*Label 59*/ 3054,
    1929             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1930             :         // No instruction predicates
    1931             :         // MIs[0] Rd
    1932             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1933             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
    1934             :         // MIs[0] imm
    1935             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1936             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
    1937             :         // MIs[0] Rn
    1938             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1939             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID,
    1940             :         // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
    1941             :         // Rule ID 3765
    1942             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
    1943             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1944             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    1945             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    1946             :         GIR_EraseFromParent, /*InsnID*/0,
    1947             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1948             :         GIR_Done,
    1949             :       // Label 59: @3054
    1950             :       GIM_Try, /*On fail goto*//*Label 60*/ 3186,
    1951             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1952             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1953             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1954             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1955             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1956             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1957             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1958             :         // No instruction predicates
    1959             :         // MIs[0] Rd
    1960             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1961             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1962             :         // MIs[0] Operand 1
    1963             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1964             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1965             :         // MIs[1] Operand 0
    1966             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1967             :         // MIs[1] Operand 1
    1968             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1969             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    1970             :         // MIs[2] Operand 0
    1971             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1972             :         // MIs[2] Rn
    1973             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1974             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1975             :         // MIs[1] C
    1976             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1977             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    1978             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
    1979             :         // MIs[3] Operand 0
    1980             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1981             :         // MIs[3] Operand 1
    1982             :         // No operand predicates
    1983             :         // MIs[0] Ra
    1984             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1985             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    1986             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1987             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1988             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1989             :         // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    1990             :         // Rule ID 2008
    1991             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    1992             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    1993             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    1994             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    1995             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    1996             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    1997             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1998             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1999             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    2000             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
    2001             :         GIR_EraseFromParent, /*InsnID*/0,
    2002             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2003             :         GIR_Done,
    2004             :       // Label 60: @3186
    2005             :       GIM_Try, /*On fail goto*//*Label 61*/ 3318,
    2006             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2007             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2008             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2009             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2010             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2011             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2012             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2013             :         // No instruction predicates
    2014             :         // MIs[0] Rd
    2015             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2016             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2017             :         // MIs[0] Operand 1
    2018             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2019             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2020             :         // MIs[1] Operand 0
    2021             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2022             :         // MIs[1] Operand 1
    2023             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2024             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2025             :         // MIs[2] Operand 0
    2026             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2027             :         // MIs[2] Rn
    2028             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2029             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2030             :         // MIs[1] C
    2031             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2032             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    2033             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
    2034             :         // MIs[3] Operand 0
    2035             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2036             :         // MIs[3] Operand 1
    2037             :         // No operand predicates
    2038             :         // MIs[0] Ra
    2039             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2040             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    2041             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2042             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2043             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2044             :         // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    2045             :         // Rule ID 2009
    2046             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    2047             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    2048             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    2049             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    2050             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    2051             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    2052             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2053             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2054             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    2055             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
    2056             :         GIR_EraseFromParent, /*InsnID*/0,
    2057             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2058             :         GIR_Done,
    2059             :       // Label 61: @3318
    2060             :       GIM_Try, /*On fail goto*//*Label 62*/ 3367,
    2061             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2062             :         // No instruction predicates
    2063             :         // MIs[0] Rd
    2064             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2065             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
    2066             :         // MIs[0] Rn
    2067             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    2068             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
    2069             :         // MIs[0] imm
    2070             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2071             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
    2072             :         // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
    2073             :         // Rule ID 33
    2074             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
    2075             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2076             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    2077             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    2078             :         GIR_EraseFromParent, /*InsnID*/0,
    2079             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2080             :         GIR_Done,
    2081             :       // Label 62: @3367
    2082             :       GIM_Try, /*On fail goto*//*Label 63*/ 3416,
    2083             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2084             :         // No instruction predicates
    2085             :         // MIs[0] Rd
    2086             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2087             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
    2088             :         // MIs[0] Rn
    2089             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2090             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
    2091             :         // MIs[0] imm
    2092             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2093             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
    2094             :         // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
    2095             :         // Rule ID 34
    2096             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
    2097             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2098             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    2099             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    2100             :         GIR_EraseFromParent, /*InsnID*/0,
    2101             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2102             :         GIR_Done,
    2103             :       // Label 63: @3416
    2104             :       GIM_Try, /*On fail goto*//*Label 64*/ 3548,
    2105             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2106             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2107             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2108             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2109             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2110             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2111             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2112             :         // No instruction predicates
    2113             :         // MIs[0] Rd
    2114             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2115             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2116             :         // MIs[0] Ra
    2117             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2118             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2119             :         // MIs[0] Operand 2
    2120             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2121             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2122             :         // MIs[1] Operand 0
    2123             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2124             :         // MIs[1] Operand 1
    2125             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2126             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    2127             :         // MIs[2] Operand 0
    2128             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2129             :         // MIs[2] Rn
    2130             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2131             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2132             :         // MIs[1] C
    2133             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2134             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    2135             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
    2136             :         // MIs[3] Operand 0
    2137             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2138             :         // MIs[3] Operand 1
    2139             :         // No operand predicates
    2140             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2141             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2142             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2143             :         // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    2144             :         // Rule ID 4146
    2145             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    2146             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    2147             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    2148             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    2149             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    2150             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    2151             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2152             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2153             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    2154             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2155             :         GIR_EraseFromParent, /*InsnID*/0,
    2156             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2157             :         GIR_Done,
    2158             :       // Label 64: @3548
    2159             :       GIM_Try, /*On fail goto*//*Label 65*/ 3680,
    2160             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2161             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2162             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2163             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2164             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2165             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2166             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2167             :         // No instruction predicates
    2168             :         // MIs[0] Rd
    2169             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2170             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2171             :         // MIs[0] Ra
    2172             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2173             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2174             :         // MIs[0] Operand 2
    2175             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2176             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2177             :         // MIs[1] Operand 0
    2178             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2179             :         // MIs[1] Operand 1
    2180             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2181             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2182             :         // MIs[2] Operand 0
    2183             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2184             :         // MIs[2] Rn
    2185             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2186             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2187             :         // MIs[1] C
    2188             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2189             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    2190             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
    2191             :         // MIs[3] Operand 0
    2192             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2193             :         // MIs[3] Operand 1
    2194             :         // No operand predicates
    2195             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2196             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2197             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2198             :         // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    2199             :         // Rule ID 4147
    2200             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    2201             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    2202             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    2203             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    2204             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    2205             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    2206             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2207             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2208             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    2209             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2210             :         GIR_EraseFromParent, /*InsnID*/0,
    2211             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2212             :         GIR_Done,
    2213             :       // Label 65: @3680
    2214             :       GIM_Reject,
    2215             :       GIR_Done,
    2216             :     // Label 57: @3682
    2217             :     GIM_Try, /*On fail goto*//*Label 66*/ 3953,
    2218             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    2219             :       GIM_Try, /*On fail goto*//*Label 67*/ 3819,
    2220             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2221             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2222             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2223             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2224             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2225             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2226             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2227             :         // No instruction predicates
    2228             :         // MIs[0] Rd
    2229             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2230             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2231             :         // MIs[0] Ra
    2232             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2233             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2234             :         // MIs[0] Operand 2
    2235             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2236             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2237             :         // MIs[1] Operand 0
    2238             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2239             :         // MIs[1] Operand 1
    2240             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2241             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    2242             :         // MIs[2] Operand 0
    2243             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2244             :         // MIs[2] Rn
    2245             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2246             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2247             :         // MIs[1] C
    2248             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2249             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    2250             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
    2251             :         // MIs[3] Operand 0
    2252             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2253             :         // MIs[3] Operand 1
    2254             :         // No operand predicates
    2255             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2256             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2257             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2258             :         // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    2259             :         // Rule ID 2011
    2260             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    2261             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    2262             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    2263             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    2264             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    2265             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
    2266             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2267             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2268             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    2269             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2270             :         GIR_EraseFromParent, /*InsnID*/0,
    2271             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2272             :         GIR_Done,
    2273             :       // Label 67: @3819
    2274             :       GIM_Try, /*On fail goto*//*Label 68*/ 3951,
    2275             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2276             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2277             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2278             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2279             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2280             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2281             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2282             :         // No instruction predicates
    2283             :         // MIs[0] Rd
    2284             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2285             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2286             :         // MIs[0] Ra
    2287             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2288             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2289             :         // MIs[0] Operand 2
    2290             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2291             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2292             :         // MIs[1] Operand 0
    2293             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2294             :         // MIs[1] Operand 1
    2295             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2296             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2297             :         // MIs[2] Operand 0
    2298             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2299             :         // MIs[2] Rn
    2300             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2301             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2302             :         // MIs[1] C
    2303             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2304             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    2305             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
    2306             :         // MIs[3] Operand 0
    2307             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2308             :         // MIs[3] Operand 1
    2309             :         // No operand predicates
    2310             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2311             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2312             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2313             :         // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    2314             :         // Rule ID 2012
    2315             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    2316             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    2317             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    2318             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    2319             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    2320             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
    2321             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2322             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2323             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    2324             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2325             :         GIR_EraseFromParent, /*InsnID*/0,
    2326             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2327             :         GIR_Done,
    2328             :       // Label 68: @3951
    2329             :       GIM_Reject,
    2330             :       GIR_Done,
    2331             :     // Label 66: @3953
    2332             :     GIM_Try, /*On fail goto*//*Label 69*/ 4444,
    2333             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
    2334             :       GIM_Try, /*On fail goto*//*Label 70*/ 4079,
    2335             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2336             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2337             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2338             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2339             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2340             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2341             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2342             :         // No instruction predicates
    2343             :         // MIs[0] Rd
    2344             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2345             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2346             :         // MIs[0] Operand 1
    2347             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2348             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2349             :         // MIs[1] Operand 0
    2350             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2351             :         // MIs[1] Operand 1
    2352             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2353             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    2354             :         // MIs[2] Operand 0
    2355             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2356             :         // MIs[2] Rn
    2357             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2358             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2359             :         // MIs[1] Operand 2
    2360             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2361             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
    2362             :         // MIs[3] Operand 0
    2363             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2364             :         // MIs[3] Rm
    2365             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2366             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2367             :         // MIs[0] Ra
    2368             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2369             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    2370             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2371             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2372             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2373             :         // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2374             :         // Rule ID 3776
    2375             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    2376             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2377             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2378             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2379             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
    2380             :         GIR_EraseFromParent, /*InsnID*/0,
    2381             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2382             :         GIR_Done,
    2383             :       // Label 70: @4079
    2384             :       GIM_Try, /*On fail goto*//*Label 71*/ 4200,
    2385             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2386             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2387             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2388             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2389             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2390             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2391             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2392             :         // No instruction predicates
    2393             :         // MIs[0] Rd
    2394             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2395             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2396             :         // MIs[0] Operand 1
    2397             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2398             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2399             :         // MIs[1] Operand 0
    2400             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2401             :         // MIs[1] Operand 1
    2402             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2403             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2404             :         // MIs[2] Operand 0
    2405             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2406             :         // MIs[2] Rn
    2407             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2408             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2409             :         // MIs[1] Operand 2
    2410             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2411             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
    2412             :         // MIs[3] Operand 0
    2413             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2414             :         // MIs[3] Rm
    2415             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2416             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2417             :         // MIs[0] Ra
    2418             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2419             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    2420             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2421             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2422             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2423             :         // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2424             :         // Rule ID 3777
    2425             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    2426             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2427             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2428             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2429             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
    2430             :         GIR_EraseFromParent, /*InsnID*/0,
    2431             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2432             :         GIR_Done,
    2433             :       // Label 71: @4200
    2434             :       GIM_Try, /*On fail goto*//*Label 72*/ 4321,
    2435             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2436             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2437             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2438             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2439             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2440             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2441             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2442             :         // No instruction predicates
    2443             :         // MIs[0] Rd
    2444             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2445             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2446             :         // MIs[0] Ra
    2447             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2448             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2449             :         // MIs[0] Operand 2
    2450             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2451             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2452             :         // MIs[1] Operand 0
    2453             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2454             :         // MIs[1] Operand 1
    2455             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2456             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    2457             :         // MIs[2] Operand 0
    2458             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2459             :         // MIs[2] Rn
    2460             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2461             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2462             :         // MIs[1] Operand 2
    2463             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2464             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
    2465             :         // MIs[3] Operand 0
    2466             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2467             :         // MIs[3] Rm
    2468             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2469             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2470             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2471             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2472             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2473             :         // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2474             :         // Rule ID 65
    2475             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    2476             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2477             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2478             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2479             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2480             :         GIR_EraseFromParent, /*InsnID*/0,
    2481             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2482             :         GIR_Done,
    2483             :       // Label 72: @4321
    2484             :       GIM_Try, /*On fail goto*//*Label 73*/ 4442,
    2485             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2486             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2487             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2488             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2489             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2490             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2491             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2492             :         // No instruction predicates
    2493             :         // MIs[0] Rd
    2494             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2495             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2496             :         // MIs[0] Ra
    2497             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2498             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2499             :         // MIs[0] Operand 2
    2500             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2501             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2502             :         // MIs[1] Operand 0
    2503             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2504             :         // MIs[1] Operand 1
    2505             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2506             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2507             :         // MIs[2] Operand 0
    2508             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2509             :         // MIs[2] Rn
    2510             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2511             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2512             :         // MIs[1] Operand 2
    2513             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2514             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
    2515             :         // MIs[3] Operand 0
    2516             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2517             :         // MIs[3] Rm
    2518             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2519             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2520             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2521             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2522             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2523             :         // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2524             :         // Rule ID 67
    2525             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    2526             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2527             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2528             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2529             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2530             :         GIR_EraseFromParent, /*InsnID*/0,
    2531             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2532             :         GIR_Done,
    2533             :       // Label 73: @4442
    2534             :       GIM_Reject,
    2535             :       GIR_Done,
    2536             :     // Label 69: @4444
    2537             :     GIM_Try, /*On fail goto*//*Label 74*/ 4583,
    2538             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ASHR,
    2539             :       GIM_Try, /*On fail goto*//*Label 75*/ 4515,
    2540             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2541             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2542             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2543             :         // No instruction predicates
    2544             :         // MIs[0] Rd
    2545             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2546             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    2547             :         // MIs[0] Rn
    2548             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    2549             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2550             :         // MIs[0] imm
    2551             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2552             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2553             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
    2554             :         // MIs[1] Operand 0
    2555             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2556             :         // MIs[1] Operand 1
    2557             :         // No operand predicates
    2558             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2559             :         // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
    2560             :         // Rule ID 2026
    2561             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMWri,
    2562             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2563             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    2564             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    2565             :         GIR_AddImm, /*InsnID*/0, /*Imm*/31,
    2566             :         GIR_EraseFromParent, /*InsnID*/0,
    2567             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2568             :         GIR_Done,
    2569             :       // Label 75: @4515
    2570             :       GIM_Try, /*On fail goto*//*Label 76*/ 4581,
    2571             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2572             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2573             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2574             :         // No instruction predicates
    2575             :         // MIs[0] Rd
    2576             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2577             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2578             :         // MIs[0] Rn
    2579             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2580             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2581             :         // MIs[0] imm
    2582             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2583             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2584             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63,
    2585             :         // MIs[1] Operand 0
    2586             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2587             :         // MIs[1] Operand 1
    2588             :         // No operand predicates
    2589             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2590             :         // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] })
    2591             :         // Rule ID 2027
    2592             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri,
    2593             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2594             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    2595             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    2596             :         GIR_AddImm, /*InsnID*/0, /*Imm*/63,
    2597             :         GIR_EraseFromParent, /*InsnID*/0,
    2598             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2599             :         GIR_Done,
    2600             :       // Label 76: @4581
    2601             :       GIM_Reject,
    2602             :       GIR_Done,
    2603             :     // Label 74: @4583
    2604             :     GIM_Try, /*On fail goto*//*Label 77*/ 4832,
    2605             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    2606             :       GIM_Try, /*On fail goto*//*Label 78*/ 4709,
    2607             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2608             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2609             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2610             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2611             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2612             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2613             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2614             :         // No instruction predicates
    2615             :         // MIs[0] Rd
    2616             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2617             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2618             :         // MIs[0] Ra
    2619             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2620             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2621             :         // MIs[0] Operand 2
    2622             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2623             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2624             :         // MIs[1] Operand 0
    2625             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2626             :         // MIs[1] Operand 1
    2627             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2628             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    2629             :         // MIs[2] Operand 0
    2630             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2631             :         // MIs[2] Rn
    2632             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2633             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2634             :         // MIs[1] Operand 2
    2635             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2636             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
    2637             :         // MIs[3] Operand 0
    2638             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2639             :         // MIs[3] Rm
    2640             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2641             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2642             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2643             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2644             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2645             :         // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2646             :         // Rule ID 66
    2647             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
    2648             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2649             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2650             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2651             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2652             :         GIR_EraseFromParent, /*InsnID*/0,
    2653             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2654             :         GIR_Done,
    2655             :       // Label 78: @4709
    2656             :       GIM_Try, /*On fail goto*//*Label 79*/ 4830,
    2657             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2658             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2659             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2660             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2661             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2662             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2663             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2664             :         // No instruction predicates
    2665             :         // MIs[0] Rd
    2666             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2667             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2668             :         // MIs[0] Ra
    2669             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2670             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2671             :         // MIs[0] Operand 2
    2672             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2673             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2674             :         // MIs[1] Operand 0
    2675             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2676             :         // MIs[1] Operand 1
    2677             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2678             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2679             :         // MIs[2] Operand 0
    2680             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2681             :         // MIs[2] Rn
    2682             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2683             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2684             :         // MIs[1] Operand 2
    2685             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2686             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
    2687             :         // MIs[3] Operand 0
    2688             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2689             :         // MIs[3] Rm
    2690             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2691             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2692             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2693             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2694             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2695             :         // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2696             :         // Rule ID 68
    2697             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
    2698             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2699             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2700             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2701             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2702             :         GIR_EraseFromParent, /*InsnID*/0,
    2703             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2704             :         GIR_Done,
    2705             :       // Label 79: @4830
    2706             :       GIM_Reject,
    2707             :       GIR_Done,
    2708             :     // Label 77: @4832
    2709             :     GIM_Try, /*On fail goto*//*Label 80*/ 6901,
    2710             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2711             :       GIM_Try, /*On fail goto*//*Label 81*/ 4942,
    2712             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
    2713             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2714             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2715             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
    2716             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2717             :         // No instruction predicates
    2718             :         // MIs[0] dst
    2719             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    2720             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2721             :         // MIs[0] Operand 1
    2722             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane,
    2723             :         // MIs[0] Vd
    2724             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    2725             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2726             :         // MIs[0] idx
    2727             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2728             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2729             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB,
    2730             :         // MIs[1] Operand 0
    2731             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2732             :         // MIs[1] Operand 1
    2733             :         // No operand predicates
    2734             :         // MIs[0] Vs
    2735             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
    2736             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID,
    2737             :         // MIs[0] idx2
    2738             :         GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
    2739             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    2740             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB,
    2741             :         // MIs[2] Operand 0
    2742             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2743             :         // MIs[2] Operand 1
    2744             :         // No operand predicates
    2745             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2746             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2747             :         // (intrinsic_wo_chain:{ *:[v16i8] } 352:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)
    2748             :         // Rule ID 2688
    2749             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi8lane,
    2750             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2751             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
    2752             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
    2753             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs
    2754             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
    2755             :         GIR_EraseFromParent, /*InsnID*/0,
    2756             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2757             :         GIR_Done,
    2758             :       // Label 81: @4942
    2759             :       GIM_Try, /*On fail goto*//*Label 82*/ 5047,
    2760             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
    2761             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2762             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2763             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
    2764             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2765             :         // No instruction predicates
    2766             :         // MIs[0] dst
    2767             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    2768             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2769             :         // MIs[0] Operand 1
    2770             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane,
    2771             :         // MIs[0] Vd
    2772             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    2773             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2774             :         // MIs[0] idx
    2775             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2776             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2777             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH,
    2778             :         // MIs[1] Operand 0
    2779             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2780             :         // MIs[1] Operand 1
    2781             :         // No operand predicates
    2782             :         // MIs[0] Vs
    2783             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
    2784             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID,
    2785             :         // MIs[0] idx2
    2786             :         GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
    2787             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    2788             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH,
    2789             :         // MIs[2] Operand 0
    2790             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2791             :         // MIs[2] Operand 1
    2792             :         // No operand predicates
    2793             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2794             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2795             :         // (intrinsic_wo_chain:{ *:[v8i16] } 352:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)
    2796             :         // Rule ID 2689
    2797             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi16lane,
    2798             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2799             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
    2800             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
    2801             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs
    2802             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
    2803             :         GIR_EraseFromParent, /*InsnID*/0,
    2804             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2805             :         GIR_Done,
    2806             :       // Label 82: @5047
    2807             :       GIM_Try, /*On fail goto*//*Label 83*/ 5152,
    2808             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
    2809             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2810             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2811             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
    2812             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2813             :         // No instruction predicates
    2814             :         // MIs[0] dst
    2815             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2816             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2817             :         // MIs[0] Operand 1
    2818             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane,
    2819             :         // MIs[0] Vd
    2820             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2821             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2822             :         // MIs[0] idx
    2823             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2824             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2825             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS,
    2826             :         // MIs[1] Operand 0
    2827             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2828             :         // MIs[1] Operand 1
    2829             :         // No operand predicates
    2830             :         // MIs[0] Vs
    2831             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
    2832             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID,
    2833             :         // MIs[0] idx2
    2834             :         GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
    2835             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    2836             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS,
    2837             :         // MIs[2] Operand 0
    2838             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2839             :         // MIs[2] Operand 1
    2840             :         // No operand predicates
    2841             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2842             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2843             :         // (intrinsic_wo_chain:{ *:[v4i32] } 352:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)
    2844             :         // Rule ID 2690
    2845             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi32lane,
    2846             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2847             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
    2848             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
    2849             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs
    2850             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
    2851             :         GIR_EraseFromParent, /*InsnID*/0,
    2852             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2853             :         GIR_Done,
    2854             :       // Label 83: @5152
    2855             :       GIM_Try, /*On fail goto*//*Label 84*/ 5257,
    2856             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
    2857             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2858             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2859             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
    2860             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2861             :         // No instruction predicates
    2862             :         // MIs[0] dst
    2863             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    2864             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2865             :         // MIs[0] Operand 1
    2866             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane,
    2867             :         // MIs[0] Vd
    2868             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    2869             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2870             :         // MIs[0] idx
    2871             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2872             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2873             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD,
    2874             :         // MIs[1] Operand 0
    2875             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2876             :         // MIs[1] Operand 1
    2877             :         // No operand predicates
    2878             :         // MIs[0] Vs
    2879             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
    2880             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID,
    2881             :         // MIs[0] idx2
    2882             :         GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
    2883             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    2884             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD,
    2885             :         // MIs[2] Operand 0
    2886             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2887             :         // MIs[2] Operand 1
    2888             :         // No operand predicates
    2889             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2890             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2891             :         // (intrinsic_wo_chain:{ *:[v2i64] } 352:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)
    2892             :         // Rule ID 2691
    2893             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
    2894             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2895             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
    2896             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
    2897             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs
    2898             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
    2899             :         GIR_EraseFromParent, /*InsnID*/0,
    2900             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2901             :         GIR_Done,
    2902             :       // Label 84: @5257
    2903             :       GIM_Try, /*On fail goto*//*Label 85*/ 5348,
    2904             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2905             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2906             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2907             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2908             :         // No instruction predicates
    2909             :         // MIs[0] dst
    2910             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    2911             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    2912             :         // MIs[0] Operand 1
    2913             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    2914             :         // MIs[0] Rd
    2915             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    2916             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2917             :         // MIs[0] Operand 3
    2918             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    2919             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2920             :         // MIs[1] Operand 0
    2921             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    2922             :         // MIs[1] Operand 1
    2923             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2924             :         // MIs[1] Rn
    2925             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2926             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2927             :         // MIs[1] Rm
    2928             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2929             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    2930             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2931             :         // (intrinsic_wo_chain:{ *:[v4i16] } 285:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 290:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    2932             :         // Rule ID 1163
    2933             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16,
    2934             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2935             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2936             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2937             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2938             :         GIR_EraseFromParent, /*InsnID*/0,
    2939             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2940             :         GIR_Done,
    2941             :       // Label 85: @5348
    2942             :       GIM_Try, /*On fail goto*//*Label 86*/ 5439,
    2943             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2944             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2945             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2946             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2947             :         // No instruction predicates
    2948             :         // MIs[0] dst
    2949             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    2950             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2951             :         // MIs[0] Operand 1
    2952             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    2953             :         // MIs[0] Rd
    2954             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    2955             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2956             :         // MIs[0] Operand 3
    2957             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    2958             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2959             :         // MIs[1] Operand 0
    2960             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    2961             :         // MIs[1] Operand 1
    2962             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2963             :         // MIs[1] Rn
    2964             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    2965             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2966             :         // MIs[1] Rm
    2967             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    2968             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    2969             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2970             :         // (intrinsic_wo_chain:{ *:[v8i16] } 285:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 290:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
    2971             :         // Rule ID 1164
    2972             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16,
    2973             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2974             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2975             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2976             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2977             :         GIR_EraseFromParent, /*InsnID*/0,
    2978             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2979             :         GIR_Done,
    2980             :       // Label 86: @5439
    2981             :       GIM_Try, /*On fail goto*//*Label 87*/ 5530,
    2982             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2983             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2984             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2985             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2986             :         // No instruction predicates
    2987             :         // MIs[0] dst
    2988             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    2989             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    2990             :         // MIs[0] Operand 1
    2991             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    2992             :         // MIs[0] Rd
    2993             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    2994             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2995             :         // MIs[0] Operand 3
    2996             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    2997             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2998             :         // MIs[1] Operand 0
    2999             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    3000             :         // MIs[1] Operand 1
    3001             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3002             :         // MIs[1] Rn
    3003             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    3004             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3005             :         // MIs[1] Rm
    3006             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    3007             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3008             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3009             :         // (intrinsic_wo_chain:{ *:[v2i32] } 285:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 290:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    3010             :         // Rule ID 1165
    3011             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32,
    3012             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3013             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3014             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3015             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3016             :         GIR_EraseFromParent, /*InsnID*/0,
    3017             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3018             :         GIR_Done,
    3019             :       // Label 87: @5530
    3020             :       GIM_Try, /*On fail goto*//*Label 88*/ 5621,
    3021             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    3022             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3023             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3024             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3025             :         // No instruction predicates
    3026             :         // MIs[0] dst
    3027             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3028             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3029             :         // MIs[0] Operand 1
    3030             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3031             :         // MIs[0] Rd
    3032             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3033             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3034             :         // MIs[0] Operand 3
    3035             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    3036             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3037             :         // MIs[1] Operand 0
    3038             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    3039             :         // MIs[1] Operand 1
    3040             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3041             :         // MIs[1] Rn
    3042             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    3043             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3044             :         // MIs[1] Rm
    3045             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    3046             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    3047             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3048             :         // (intrinsic_wo_chain:{ *:[v4i32] } 285:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 290:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
    3049             :         // Rule ID 1166
    3050             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32,
    3051             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3052             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3053             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3054             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3055             :         GIR_EraseFromParent, /*InsnID*/0,
    3056             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3057             :         GIR_Done,
    3058             :       // Label 88: @5621
    3059             :       GIM_Try, /*On fail goto*//*Label 89*/ 5712,
    3060             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    3061             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3062             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3063             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3064             :         // No instruction predicates
    3065             :         // MIs[0] dst
    3066             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    3067             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    3068             :         // MIs[0] Operand 1
    3069             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3070             :         // MIs[0] Rd
    3071             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    3072             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3073             :         // MIs[0] Operand 3
    3074             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    3075             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3076             :         // MIs[1] Operand 0
    3077             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    3078             :         // MIs[1] Operand 1
    3079             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3080             :         // MIs[1] Rn
    3081             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    3082             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3083             :         // MIs[1] Rm
    3084             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    3085             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3086             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3087             :         // (intrinsic_wo_chain:{ *:[v4i16] } 298:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 290:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    3088             :         // Rule ID 1167
    3089             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16,
    3090             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3091             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3092             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3093             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3094             :         GIR_EraseFromParent, /*InsnID*/0,
    3095             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3096             :         GIR_Done,
    3097             :       // Label 89: @5712
    3098             :       GIM_Try, /*On fail goto*//*Label 90*/ 5803,
    3099             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    3100             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3101             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3102             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3103             :         // No instruction predicates
    3104             :         // MIs[0] dst
    3105             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    3106             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3107             :         // MIs[0] Operand 1
    3108             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3109             :         // MIs[0] Rd
    3110             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    3111             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3112             :         // MIs[0] Operand 3
    3113             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    3114             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3115             :         // MIs[1] Operand 0
    3116             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    3117             :         // MIs[1] Operand 1
    3118             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3119             :         // MIs[1] Rn
    3120             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    3121             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3122             :         // MIs[1] Rm
    3123             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    3124             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    3125             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3126             :         // (intrinsic_wo_chain:{ *:[v8i16] } 298:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 290:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
    3127             :         // Rule ID 1168
    3128             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16,
    3129             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3130             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3131             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3132             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3133             :         GIR_EraseFromParent, /*InsnID*/0,
    3134             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3135             :         GIR_Done,
    3136             :       // Label 90: @5803
    3137             :       GIM_Try, /*On fail goto*//*Label 91*/ 5894,
    3138             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    3139             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3140             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3141             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3142             :         // No instruction predicates
    3143             :         // MIs[0] dst
    3144             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    3145             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    3146             :         // MIs[0] Operand 1
    3147             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3148             :         // MIs[0] Rd
    3149             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    3150             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3151             :         // MIs[0] Operand 3
    3152             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    3153             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3154             :         // MIs[1] Operand 0
    3155             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    3156             :         // MIs[1] Operand 1
    3157             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3158             :         // MIs[1] Rn
    3159             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    3160             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3161             :         // MIs[1] Rm
    3162             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    3163             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3164             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3165             :         // (intrinsic_wo_chain:{ *:[v2i32] } 298:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 290:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    3166             :         // Rule ID 1169
    3167             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32,
    3168             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3169             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3170             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3171             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3172             :         GIR_EraseFromParent, /*InsnID*/0,
    3173             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3174             :         GIR_Done,
    3175             :       // Label 91: @5894
    3176             :       GIM_Try, /*On fail goto*//*Label 92*/ 5985,
    3177             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    3178             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3179             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3180             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3181             :         // No instruction predicates
    3182             :         // MIs[0] dst
    3183             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3184             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3185             :         // MIs[0] Operand 1
    3186             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3187             :         // MIs[0] Rd
    3188             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3189             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3190             :         // MIs[0] Operand 3
    3191             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    3192             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3193             :         // MIs[1] Operand 0
    3194             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    3195             :         // MIs[1] Operand 1
    3196             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3197             :         // MIs[1] Rn
    3198             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    3199             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3200             :         // MIs[1] Rm
    3201             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    3202             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    3203             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3204             :         // (intrinsic_wo_chain:{ *:[v4i32] } 298:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 290:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
    3205             :         // Rule ID 1170
    3206             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32,
    3207             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3208             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3209             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3210             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3211             :         GIR_EraseFromParent, /*InsnID*/0,
    3212             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3213             :         GIR_Done,
    3214             :       // Label 92: @5985
    3215             :       GIM_Try, /*On fail goto*//*Label 93*/ 6076,
    3216             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3217             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3218             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3219             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3220             :         // No instruction predicates
    3221             :         // MIs[0] dst
    3222             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3223             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3224             :         // MIs[0] Operand 1
    3225             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3226             :         // MIs[0] Rd
    3227             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3228             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3229             :         // MIs[0] Operand 3
    3230             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    3231             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3232             :         // MIs[1] Operand 0
    3233             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    3234             :         // MIs[1] Operand 1
    3235             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull,
    3236             :         // MIs[1] Rn
    3237             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    3238             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3239             :         // MIs[1] Rm
    3240             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    3241             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3242             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3243             :         // (intrinsic_wo_chain:{ *:[v4i32] } 285:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    3244             :         // Rule ID 1305
    3245             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_v4i32,
    3246             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3247             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3248             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3249             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3250             :         GIR_EraseFromParent, /*InsnID*/0,
    3251             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3252             :         GIR_Done,
    3253             :       // Label 93: @6076
    3254             :       GIM_Try, /*On fail goto*//*Label 94*/ 6167,
    3255             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3256             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3257             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3258             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3259             :         // No instruction predicates
    3260             :         // MIs[0] dst
    3261             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    3262             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3263             :         // MIs[0] Operand 1
    3264             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3265             :         // MIs[0] Rd
    3266             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    3267             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3268             :         // MIs[0] Operand 3
    3269             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    3270             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3271             :         // MIs[1] Operand 0
    3272             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    3273             :         // MIs[1] Operand 1
    3274             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull,
    3275             :         // MIs[1] Rn
    3276             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    3277             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3278             :         // MIs[1] Rm
    3279             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    3280             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3281             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3282             :         // (intrinsic_wo_chain:{ *:[v2i64] } 285:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    3283             :         // Rule ID 1307
    3284             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_v2i64,
    3285             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3286             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3287             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3288             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3289             :         GIR_EraseFromParent, /*InsnID*/0,
    3290             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3291             :         GIR_Done,
    3292             :       // Label 94: @6167
    3293             :       GIM_Try, /*On fail goto*//*Label 95*/ 6258,
    3294             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3295             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3296             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3297             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3298             :         // No instruction predicates
    3299             :         // MIs[0] dst
    3300             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3301             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3302             :         // MIs[0] Operand 1
    3303             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3304             :         // MIs[0] Rd
    3305             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3306             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3307             :         // MIs[0] Operand 3
    3308             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    3309             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3310             :         // MIs[1] Operand 0
    3311             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    3312             :         // MIs[1] Operand 1
    3313             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull,
    3314             :         // MIs[1] Rn
    3315             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    3316             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3317             :         // MIs[1] Rm
    3318             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    3319             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3320             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3321             :         // (intrinsic_wo_chain:{ *:[v4i32] } 298:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    3322             :         // Rule ID 1309
    3323             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_v4i32,
    3324             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3325             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3326             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3327             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3328             :         GIR_EraseFromParent, /*InsnID*/0,
    3329             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3330             :         GIR_Done,
    3331             :       // Label 95: @6258
    3332             :       GIM_Try, /*On fail goto*//*Label 96*/ 6349,
    3333             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3334             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3335             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3336             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3337             :         // No instruction predicates
    3338             :         // MIs[0] dst
    3339             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    3340             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3341             :         // MIs[0] Operand 1
    3342             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3343             :         // MIs[0] Rd
    3344             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    3345             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3346             :         // MIs[0] Operand 3
    3347             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    3348             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3349             :         // MIs[1] Operand 0
    3350             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    3351             :         // MIs[1] Operand 1
    3352             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull,
    3353             :         // MIs[1] Rn
    3354             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    3355             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3356             :         // MIs[1] Rm
    3357             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    3358             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3359             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3360             :         // (intrinsic_wo_chain:{ *:[v2i64] } 298:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    3361             :         // Rule ID 1311
    3362             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_v2i64,
    3363             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3364             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3365             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3366             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3367             :         GIR_EraseFromParent, /*InsnID*/0,
    3368             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3369             :         GIR_Done,
    3370             :       // Label 96: @6349
    3371             :       GIM_Try, /*On fail goto*//*Label 97*/ 6440,
    3372             :         GIM_CheckFeatures, GIFBS_HasRDM,
    3373             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3374             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3375             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3376             :         // No instruction predicates
    3377             :         // MIs[0] dst
    3378             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3379             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    3380             :         // MIs[0] Operand 1
    3381             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3382             :         // MIs[0] Rd
    3383             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3384             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3385             :         // MIs[0] Operand 3
    3386             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3387             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3388             :         // MIs[1] Operand 0
    3389             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3390             :         // MIs[1] Operand 1
    3391             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3392             :         // MIs[1] Rn
    3393             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3394             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3395             :         // MIs[1] Rm
    3396             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3397             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID,
    3398             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3399             :         // (intrinsic_wo_chain:{ *:[i32] } 285:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 290:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
    3400             :         // Rule ID 2487
    3401             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv1i32,
    3402             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3403             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3404             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3405             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3406             :         GIR_EraseFromParent, /*InsnID*/0,
    3407             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3408             :         GIR_Done,
    3409             :       // Label 97: @6440
    3410             :       GIM_Try, /*On fail goto*//*Label 98*/ 6531,
    3411             :         GIM_CheckFeatures, GIFBS_HasRDM,
    3412             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3413             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3414             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3415             :         // No instruction predicates
    3416             :         // MIs[0] dst
    3417             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3418             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    3419             :         // MIs[0] Operand 1
    3420             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3421             :         // MIs[0] Rd
    3422             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3423             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3424             :         // MIs[0] Operand 3
    3425             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3426             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3427             :         // MIs[1] Operand 0
    3428             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3429             :         // MIs[1] Operand 1
    3430             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3431             :         // MIs[1] Rn
    3432             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3433             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3434             :         // MIs[1] Rm
    3435             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3436             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID,
    3437             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3438             :         // (intrinsic_wo_chain:{ *:[i32] } 298:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 290:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
    3439             :         // Rule ID 2488
    3440             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv1i32,
    3441             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3442             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3443             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3444             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3445             :         GIR_EraseFromParent, /*InsnID*/0,
    3446             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3447             :         GIR_Done,
    3448             :       // Label 98: @6531
    3449             :       GIM_Try, /*On fail goto*//*Label 99*/ 6620,
    3450             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3451             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3452             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3453             :         // No instruction predicates
    3454             :         // MIs[0] dst
    3455             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3456             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    3457             :         // MIs[0] Operand 1
    3458             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3459             :         // MIs[0] Rd
    3460             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3461             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3462             :         // MIs[0] Operand 3
    3463             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    3464             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3465             :         // MIs[1] Operand 0
    3466             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3467             :         // MIs[1] Operand 1
    3468             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar,
    3469             :         // MIs[1] Rn
    3470             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3471             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3472             :         // MIs[1] Rm
    3473             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3474             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID,
    3475             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3476             :         // (intrinsic_wo_chain:{ *:[i64] } 285:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 288:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQDMLALi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
    3477             :         // Rule ID 2489
    3478             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALi32,
    3479             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3480             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3481             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3482             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3483             :         GIR_EraseFromParent, /*InsnID*/0,
    3484             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3485             :         GIR_Done,
    3486             :       // Label 99: @6620
    3487             :       GIM_Try, /*On fail goto*//*Label 100*/ 6709,
    3488             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3489             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3490             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3491             :         // No instruction predicates
    3492             :         // MIs[0] dst
    3493             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3494             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    3495             :         // MIs[0] Operand 1
    3496             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3497             :         // MIs[0] Rd
    3498             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3499             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3500             :         // MIs[0] Operand 3
    3501             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    3502             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3503             :         // MIs[1] Operand 0
    3504             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3505             :         // MIs[1] Operand 1
    3506             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar,
    3507             :         // MIs[1] Rn
    3508             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3509             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3510             :         // MIs[1] Rm
    3511             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3512             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID,
    3513             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3514             :         // (intrinsic_wo_chain:{ *:[i64] } 298:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 288:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQDMLSLi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
    3515             :         // Rule ID 2490
    3516             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLi32,
    3517             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3518             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3519             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3520             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3521             :         GIR_EraseFromParent, /*InsnID*/0,
    3522             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3523             :         GIR_Done,
    3524             :       // Label 100: @6709
    3525             :       GIM_Try, /*On fail goto*//*Label 101*/ 6804,
    3526             :         GIM_CheckFeatures, GIFBS_HasFuseAES,
    3527             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3528             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3529             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3530             :         // No instruction predicates
    3531             :         // MIs[0] Rd
    3532             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    3533             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3534             :         // MIs[0] Operand 1
    3535             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc,
    3536             :         // MIs[0] Operand 2
    3537             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    3538             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3539             :         // MIs[1] Operand 0
    3540             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    3541             :         // MIs[1] Operand 1
    3542             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aese,
    3543             :         // MIs[1] src1
    3544             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    3545             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3546             :         // MIs[1] src2
    3547             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    3548             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    3549             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3550             :         // (intrinsic_wo_chain:{ *:[v16i8] } 190:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 188:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))  =>  (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
    3551             :         // Rule ID 3066
    3552             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
    3553             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESErr,
    3554             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3555             :         GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
    3556             :         GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
    3557             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3558             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrrTied,
    3559             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3560             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3561             :         GIR_EraseFromParent, /*InsnID*/0,
    3562             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3563             :         GIR_Done,
    3564             :       // Label 101: @6804
    3565             :       GIM_Try, /*On fail goto*//*Label 102*/ 6899,
    3566             :         GIM_CheckFeatures, GIFBS_HasFuseAES,
    3567             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3568             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3569             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3570             :         // No instruction predicates
    3571             :         // MIs[0] Rd
    3572             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    3573             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3574             :         // MIs[0] Operand 1
    3575             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc,
    3576             :         // MIs[0] Operand 2
    3577             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    3578             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3579             :         // MIs[1] Operand 0
    3580             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    3581             :         // MIs[1] Operand 1
    3582             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aesd,
    3583             :         // MIs[1] src1
    3584             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    3585             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3586             :         // MIs[1] src2
    3587             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    3588             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    3589             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3590             :         // (intrinsic_wo_chain:{ *:[v16i8] } 189:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 187:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))  =>  (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
    3591             :         // Rule ID 3067
    3592             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
    3593             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESDrr,
    3594             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3595             :         GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
    3596             :         GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
    3597             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3598             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrrTied,
    3599             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3600             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3601             :         GIR_EraseFromParent, /*InsnID*/0,
    3602             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3603             :         GIR_Done,
    3604             :       // Label 102: @6899
    3605             :       GIM_Reject,
    3606             :       GIR_Done,
    3607             :     // Label 80: @6901
    3608             :     GIM_Try, /*On fail goto*//*Label 103*/ 7228,
    3609             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
    3610             :       GIM_Try, /*On fail goto*//*Label 104*/ 6986,
    3611             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3612             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3613             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3614             :         // No instruction predicates
    3615             :         // MIs[0] Rd
    3616             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3617             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3618             :         // MIs[0] Operand 1
    3619             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3620             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
    3621             :         // MIs[1] Operand 0
    3622             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3623             :         // MIs[1] Operand 1
    3624             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3625             :         GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
    3626             :         // MIs[1] Rn
    3627             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3628             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
    3629             :         // MIs[0] Rm
    3630             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3631             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
    3632             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3633             :         // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm)  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
    3634             :         // Rule ID 1996
    3635             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
    3636             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3637             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3638             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
    3639             :         GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
    3640             :         GIR_EraseFromParent, /*InsnID*/0,
    3641             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3642             :         GIR_Done,
    3643             :       // Label 104: @6986
    3644             :       GIM_Try, /*On fail goto*//*Label 105*/ 7066,
    3645             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3646             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3647             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3648             :         // No instruction predicates
    3649             :         // MIs[0] Rd
    3650             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3651             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3652             :         // MIs[0] Operand 1
    3653             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3654             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
    3655             :         // MIs[1] Operand 0
    3656             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3657             :         // MIs[1] Operand 1
    3658             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    3659             :         GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
    3660             :         // MIs[1] Rn
    3661             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    3662             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    3663             :         // MIs[0] Rm
    3664             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3665             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    3666             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3667             :         // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm)  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
    3668             :         // Rule ID 1997
    3669             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
    3670             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3671             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3672             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
    3673             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3674             :         GIR_EraseFromParent, /*InsnID*/0,
    3675             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3676             :         GIR_Done,
    3677             :       // Label 105: @7066
    3678             :       GIM_Try, /*On fail goto*//*Label 106*/ 7146,
    3679             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3680             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3681             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3682             :         // No instruction predicates
    3683             :         // MIs[0] Rd
    3684             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3685             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3686             :         // MIs[0] Rm
    3687             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3688             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    3689             :         // MIs[0] Operand 2
    3690             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3691             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
    3692             :         // MIs[1] Operand 0
    3693             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3694             :         // MIs[1] Operand 1
    3695             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3696             :         GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
    3697             :         // MIs[1] Rn
    3698             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3699             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
    3700             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3701             :         // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
    3702             :         // Rule ID 4144
    3703             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
    3704             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3705             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3706             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
    3707             :         GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
    3708             :         GIR_EraseFromParent, /*InsnID*/0,
    3709             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3710             :         GIR_Done,
    3711             :       // Label 106: @7146
    3712             :       GIM_Try, /*On fail goto*//*Label 107*/ 7226,
    3713             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3714             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3715             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3716             :         // No instruction predicates
    3717             :         // MIs[0] Rd
    3718             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3719             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3720             :         // MIs[0] Rm
    3721             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3722             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    3723             :         // MIs[0] Operand 2
    3724             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3725             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
    3726             :         // MIs[1] Operand 0
    3727             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3728             :         // MIs[1] Operand 1
    3729             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    3730             :         GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
    3731             :         // MIs[1] Rn
    3732             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    3733             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    3734             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3735             :         // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
    3736             :         // Rule ID 4145
    3737             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
    3738             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3739             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3740             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
    3741             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3742             :         GIR_EraseFromParent, /*InsnID*/0,
    3743             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3744             :         GIR_Done,
    3745             :       // Label 107: @7226
    3746             :       GIM_Reject,
    3747             :       GIR_Done,
    3748             :     // Label 103: @7228
    3749             :     GIM_Try, /*On fail goto*//*Label 108*/ 7395,
    3750             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    3751             :       GIM_Try, /*On fail goto*//*Label 109*/ 7313,
    3752             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3753             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3754             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3755             :         // No instruction predicates
    3756             :         // MIs[0] Rd
    3757             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3758             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3759             :         // MIs[0] Operand 1
    3760             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3761             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
    3762             :         // MIs[0] Operand 2
    3763             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3764             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    3765             :         // MIs[1] Operand 0
    3766             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3767             :         // MIs[1] Rn
    3768             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3769             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    3770             :         // MIs[1] Rm
    3771             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3772             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
    3773             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3774             :         // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
    3775             :         // Rule ID 1994
    3776             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
    3777             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3778             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    3779             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
    3780             :         GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
    3781             :         GIR_EraseFromParent, /*InsnID*/0,
    3782             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3783             :         GIR_Done,
    3784             :       // Label 109: @7313
    3785             :       GIM_Try, /*On fail goto*//*Label 110*/ 7393,
    3786             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3787             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3788             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3789             :         // No instruction predicates
    3790             :         // MIs[0] Rd
    3791             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3792             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3793             :         // MIs[0] Operand 1
    3794             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3795             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
    3796             :         // MIs[0] Operand 2
    3797             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3798             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    3799             :         // MIs[1] Operand 0
    3800             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3801             :         // MIs[1] Rn
    3802             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    3803             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    3804             :         // MIs[1] Rm
    3805             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    3806             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    3807             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3808             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
    3809             :         // Rule ID 1995
    3810             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
    3811             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3812             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    3813             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
    3814             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3815             :         GIR_EraseFromParent, /*InsnID*/0,
    3816             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3817             :         GIR_Done,
    3818             :       // Label 110: @7393
    3819             :       GIM_Reject,
    3820             :       GIR_Done,
    3821             :     // Label 108: @7395
    3822             :     GIM_Try, /*On fail goto*//*Label 111*/ 7608,
    3823             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
    3824             :       GIM_Try, /*On fail goto*//*Label 112*/ 7503,
    3825             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3826             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3827             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3828             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    3829             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    3830             :         // No instruction predicates
    3831             :         // MIs[0] Rd
    3832             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3833             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3834             :         // MIs[0] Operand 1
    3835             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3836             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
    3837             :         // MIs[1] Operand 0
    3838             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3839             :         // MIs[1] Rn
    3840             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3841             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    3842             :         // MIs[0] C
    3843             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3844             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    3845             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
    3846             :         // MIs[2] Operand 0
    3847             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    3848             :         // MIs[2] Operand 1
    3849             :         // No operand predicates
    3850             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3851             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    3852             :         // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
    3853             :         // Rule ID 2002
    3854             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    3855             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    3856             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3857             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C
    3858             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3859             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    3860             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3861             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    3862             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3863             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3864             :         GIR_EraseFromParent, /*InsnID*/0,
    3865             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3866             :         GIR_Done,
    3867             :       // Label 112: @7503
    3868             :       GIM_Try, /*On fail goto*//*Label 113*/ 7606,
    3869             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3870             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3871             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3872             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    3873             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    3874             :         // No instruction predicates
    3875             :         // MIs[0] Rd
    3876             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3877             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3878             :         // MIs[0] Operand 1
    3879             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3880             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    3881             :         // MIs[1] Operand 0
    3882             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3883             :         // MIs[1] Rn
    3884             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3885             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    3886             :         // MIs[0] C
    3887             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3888             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    3889             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
    3890             :         // MIs[2] Operand 0
    3891             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    3892             :         // MIs[2] Operand 1
    3893             :         // No operand predicates
    3894             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3895             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    3896             :         // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
    3897             :         // Rule ID 2003
    3898             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    3899             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    3900             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3901             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C
    3902             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3903             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    3904             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3905             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    3906             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3907             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3908             :         GIR_EraseFromParent, /*InsnID*/0,
    3909             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3910             :         GIR_Done,
    3911             :       // Label 113: @7606
    3912             :       GIM_Reject,
    3913             :       GIR_Done,
    3914             :     // Label 111: @7608
    3915             :     GIM_Try, /*On fail goto*//*Label 114*/ 8899,
    3916             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
    3917             :       GIM_Try, /*On fail goto*//*Label 115*/ 7720,
    3918             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3919             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3920             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3921             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3922             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    3923             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    3924             :         // No instruction predicates
    3925             :         // MIs[0] dst
    3926             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    3927             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3928             :         // MIs[0] Operand 1
    3929             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    3930             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    3931             :         // MIs[1] Operand 0
    3932             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    3933             :         // MIs[1] Operand 1
    3934             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
    3935             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    3936             :         // MIs[2] Operand 0
    3937             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v8s8,
    3938             :         // MIs[2] Operand 1
    3939             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    3940             :         // MIs[2] Rn
    3941             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
    3942             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3943             :         // MIs[2] Rm
    3944             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
    3945             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3946             :         // MIs[0] Rd
    3947             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    3948             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3949             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3950             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    3951             :         // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 266:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    3952             :         // Rule ID 3898
    3953             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
    3954             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3955             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3956             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    3957             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    3958             :         GIR_EraseFromParent, /*InsnID*/0,
    3959             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3960             :         GIR_Done,
    3961             :       // Label 115: @7720
    3962             :       GIM_Try, /*On fail goto*//*Label 116*/ 7827,
    3963             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3964             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3965             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3966             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3967             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    3968             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    3969             :         // No instruction predicates
    3970             :         // MIs[0] dst
    3971             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3972             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3973             :         // MIs[0] Operand 1
    3974             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    3975             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    3976             :         // MIs[1] Operand 0
    3977             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    3978             :         // MIs[1] Operand 1
    3979             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
    3980             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    3981             :         // MIs[2] Operand 0
    3982             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v4s16,
    3983             :         // MIs[2] Operand 1
    3984             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    3985             :         // MIs[2] Rn
    3986             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
    3987             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3988             :         // MIs[2] Rm
    3989             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
    3990             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3991             :         // MIs[0] Rd
    3992             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3993             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3994             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3995             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    3996             :         // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 266:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    3997             :         // Rule ID 3900
    3998             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
    3999             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4000             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4001             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4002             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4003             :         GIR_EraseFromParent, /*InsnID*/0,
    4004             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4005             :         GIR_Done,
    4006             :       // Label 116: @7827
    4007             :       GIM_Try, /*On fail goto*//*Label 117*/ 7934,
    4008             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4009             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4010             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4011             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4012             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4013             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4014             :         // No instruction predicates
    4015             :         // MIs[0] dst
    4016             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4017             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4018             :         // MIs[0] Operand 1
    4019             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    4020             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4021             :         // MIs[1] Operand 0
    4022             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    4023             :         // MIs[1] Operand 1
    4024             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    4025             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4026             :         // MIs[2] Operand 0
    4027             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v2s32,
    4028             :         // MIs[2] Operand 1
    4029             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4030             :         // MIs[2] Rn
    4031             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
    4032             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4033             :         // MIs[2] Rm
    4034             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
    4035             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4036             :         // MIs[0] Rd
    4037             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    4038             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4039             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4040             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4041             :         // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 266:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    4042             :         // Rule ID 3902
    4043             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
    4044             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4045             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4046             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4047             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4048             :         GIR_EraseFromParent, /*InsnID*/0,
    4049             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4050             :         GIR_Done,
    4051             :       // Label 117: @7934
    4052             :       GIM_Try, /*On fail goto*//*Label 118*/ 8041,
    4053             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4054             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4055             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4056             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4057             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4058             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4059             :         // No instruction predicates
    4060             :         // MIs[0] dst
    4061             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    4062             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4063             :         // MIs[0] Operand 1
    4064             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    4065             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4066             :         // MIs[1] Operand 0
    4067             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    4068             :         // MIs[1] Operand 1
    4069             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
    4070             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4071             :         // MIs[2] Operand 0
    4072             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v8s8,
    4073             :         // MIs[2] Operand 1
    4074             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4075             :         // MIs[2] Rn
    4076             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
    4077             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4078             :         // MIs[2] Rm
    4079             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
    4080             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4081             :         // MIs[0] Rd
    4082             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    4083             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4084             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4085             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4086             :         // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 324:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    4087             :         // Rule ID 3916
    4088             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
    4089             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4090             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4091             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4092             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4093             :         GIR_EraseFromParent, /*InsnID*/0,
    4094             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4095             :         GIR_Done,
    4096             :       // Label 118: @8041
    4097             :       GIM_Try, /*On fail goto*//*Label 119*/ 8148,
    4098             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4099             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4100             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4101             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4102             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4103             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4104             :         // No instruction predicates
    4105             :         // MIs[0] dst
    4106             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    4107             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4108             :         // MIs[0] Operand 1
    4109             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    4110             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4111             :         // MIs[1] Operand 0
    4112             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    4113             :         // MIs[1] Operand 1
    4114             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
    4115             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4116             :         // MIs[2] Operand 0
    4117             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v4s16,
    4118             :         // MIs[2] Operand 1
    4119             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4120             :         // MIs[2] Rn
    4121             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
    4122             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4123             :         // MIs[2] Rm
    4124             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
    4125             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4126             :         // MIs[0] Rd
    4127             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    4128             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4129             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4130             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4131             :         // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 324:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    4132             :         // Rule ID 3918
    4133             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
    4134             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4135             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4136             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4137             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4138             :         GIR_EraseFromParent, /*InsnID*/0,
    4139             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4140             :         GIR_Done,
    4141             :       // Label 119: @8148
    4142             :       GIM_Try, /*On fail goto*//*Label 120*/ 8255,
    4143             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4144             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4145             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4146             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4147             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4148             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4149             :         // No instruction predicates
    4150             :         // MIs[0] dst
    4151             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4152             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4153             :         // MIs[0] Operand 1
    4154             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    4155             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4156             :         // MIs[1] Operand 0
    4157             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    4158             :         // MIs[1] Operand 1
    4159             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    4160             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4161             :         // MIs[2] Operand 0
    4162             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v2s32,
    4163             :         // MIs[2] Operand 1
    4164             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4165             :         // MIs[2] Rn
    4166             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
    4167             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4168             :         // MIs[2] Rm
    4169             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
    4170             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4171             :         // MIs[0] Rd
    4172             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    4173             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4174             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4175             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4176             :         // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 324:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    4177             :         // Rule ID 3920
    4178             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
    4179             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4180             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4181             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4182             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4183             :         GIR_EraseFromParent, /*InsnID*/0,
    4184             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4185             :         GIR_Done,
    4186             :       // Label 120: @8255
    4187             :       GIM_Try, /*On fail goto*//*Label 121*/ 8362,
    4188             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4189             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4190             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4191             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4192             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4193             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4194             :         // No instruction predicates
    4195             :         // MIs[0] dst
    4196             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    4197             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4198             :         // MIs[0] Rd
    4199             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    4200             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4201             :         // MIs[0] Operand 2
    4202             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    4203             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4204             :         // MIs[1] Operand 0
    4205             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    4206             :         // MIs[1] Operand 1
    4207             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
    4208             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4209             :         // MIs[2] Operand 0
    4210             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v8s8,
    4211             :         // MIs[2] Operand 1
    4212             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4213             :         // MIs[2] Rn
    4214             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
    4215             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4216             :         // MIs[2] Rm
    4217             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
    4218             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4219             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4220             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4221             :         // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 266:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    4222             :         // Rule ID 1263
    4223             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
    4224             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4225             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4226             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4227             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4228             :         GIR_EraseFromParent, /*InsnID*/0,
    4229             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4230             :         GIR_Done,
    4231             :       // Label 121: @8362
    4232             :       GIM_Try, /*On fail goto*//*Label 122*/ 8469,
    4233             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4234             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4235             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4236             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4237             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4238             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4239             :         // No instruction predicates
    4240             :         // MIs[0] dst
    4241             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    4242             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4243             :         // MIs[0] Rd
    4244             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    4245             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4246             :         // MIs[0] Operand 2
    4247             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    4248             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4249             :         // MIs[1] Operand 0
    4250             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    4251             :         // MIs[1] Operand 1
    4252             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
    4253             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4254             :         // MIs[2] Operand 0
    4255             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v4s16,
    4256             :         // MIs[2] Operand 1
    4257             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4258             :         // MIs[2] Rn
    4259             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
    4260             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4261             :         // MIs[2] Rm
    4262             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
    4263             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4264             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4265             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4266             :         // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 266:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    4267             :         // Rule ID 1265
    4268             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
    4269             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4270             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4271             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4272             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4273             :         GIR_EraseFromParent, /*InsnID*/0,
    4274             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4275             :         GIR_Done,
    4276             :       // Label 122: @8469
    4277             :       GIM_Try, /*On fail goto*//*Label 123*/ 8576,
    4278             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4279             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4280             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4281             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4282             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4283             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4284             :         // No instruction predicates
    4285             :         // MIs[0] dst
    4286             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4287             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4288             :         // MIs[0] Rd
    4289             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    4290             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4291             :         // MIs[0] Operand 2
    4292             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    4293             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4294             :         // MIs[1] Operand 0
    4295             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    4296             :         // MIs[1] Operand 1
    4297             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    4298             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4299             :         // MIs[2] Operand 0
    4300             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v2s32,
    4301             :         // MIs[2] Operand 1
    4302             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4303             :         // MIs[2] Rn
    4304             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
    4305             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4306             :         // MIs[2] Rm
    4307             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
    4308             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4309             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4310             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4311             :         // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 266:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    4312             :         // Rule ID 1267
    4313             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
    4314             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4315             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4316             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4317             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4318             :         GIR_EraseFromParent, /*InsnID*/0,
    4319             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4320             :         GIR_Done,
    4321             :       // Label 123: @8576
    4322             :       GIM_Try, /*On fail goto*//*Label 124*/ 8683,
    4323             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4324             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4325             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4326             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4327             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4328             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4329             :         // No instruction predicates
    4330             :         // MIs[0] dst
    4331             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    4332             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4333             :         // MIs[0] Rd
    4334             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    4335             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4336             :         // MIs[0] Operand 2
    4337             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    4338             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4339             :         // MIs[1] Operand 0
    4340             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    4341             :         // MIs[1] Operand 1
    4342             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
    4343             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4344             :         // MIs[2] Operand 0
    4345             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v8s8,
    4346             :         // MIs[2] Operand 1
    4347             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4348             :         // MIs[2] Rn
    4349             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
    4350             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4351             :         // MIs[2] Rm
    4352             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
    4353             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4354             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4355             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4356             :         // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 324:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    4357             :         // Rule ID 1329
    4358             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
    4359             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4360             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4361             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4362             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4363             :         GIR_EraseFromParent, /*InsnID*/0,
    4364             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4365             :         GIR_Done,
    4366             :       // Label 124: @8683
    4367             :       GIM_Try, /*On fail goto*//*Label 125*/ 8790,
    4368             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4369             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4370             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4371             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4372             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4373             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4374             :         // No instruction predicates
    4375             :         // MIs[0] dst
    4376             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    4377             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4378             :         // MIs[0] Rd
    4379             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    4380             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4381             :         // MIs[0] Operand 2
    4382             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    4383             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4384             :         // MIs[1] Operand 0
    4385             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    4386             :         // MIs[1] Operand 1
    4387             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
    4388             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4389             :         // MIs[2] Operand 0
    4390             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v4s16,
    4391             :         // MIs[2] Operand 1
    4392             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4393             :         // MIs[2] Rn
    4394             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
    4395             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4396             :         // MIs[2] Rm
    4397             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
    4398             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4399             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4400             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4401             :         // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 324:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    4402             :         // Rule ID 1331
    4403             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
    4404             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4405             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4406             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4407             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4408             :         GIR_EraseFromParent, /*InsnID*/0,
    4409             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4410             :         GIR_Done,
    4411             :       // Label 125: @8790
    4412             :       GIM_Try, /*On fail goto*//*Label 126*/ 8897,
    4413             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4414             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4415             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4416             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4417             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4418             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4419             :         // No instruction predicates
    4420             :         // MIs[0] dst
    4421             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4422             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4423             :         // MIs[0] Rd
    4424             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    4425             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4426             :         // MIs[0] Operand 2
    4427             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    4428             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4429             :         // MIs[1] Operand 0
    4430             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    4431             :         // MIs[1] Operand 1
    4432             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    4433             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4434             :         // MIs[2] Operand 0
    4435             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v2s32,
    4436             :         // MIs[2] Operand 1
    4437             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4438             :         // MIs[2] Rn
    4439             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
    4440             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4441             :         // MIs[2] Rm
    4442             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
    4443             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4444             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4445             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4446             :         // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 324:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    4447             :         // Rule ID 1333
    4448             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
    4449             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4450             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4451             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4452             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4453             :         GIR_EraseFromParent, /*InsnID*/0,
    4454             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4455             :         GIR_Done,
    4456             :       // Label 126: @8897
    4457             :       GIM_Reject,
    4458             :       GIR_Done,
    4459             :     // Label 114: @8899
    4460             :     GIM_Try, /*On fail goto*//*Label 127*/ 9090,
    4461             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
    4462             :       GIM_Try, /*On fail goto*//*Label 128*/ 8996,
    4463             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4464             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4465             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4466             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    4467             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    4468             :         // No instruction predicates
    4469             :         // MIs[0] Rd
    4470             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4471             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4472             :         // MIs[0] Operand 1
    4473             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    4474             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
    4475             :         // MIs[1] Operand 0
    4476             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    4477             :         // MIs[1] Rn
    4478             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    4479             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    4480             :         // MIs[0] Operand 2
    4481             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    4482             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    4483             :         // MIs[2] Operand 0
    4484             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    4485             :         // MIs[2] Rm
    4486             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    4487             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    4488             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4489             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4490             :         // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
    4491             :         // Rule ID 1998
    4492             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    4493             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4494             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    4495             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
    4496             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    4497             :         GIR_EraseFromParent, /*InsnID*/0,
    4498             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4499             :         GIR_Done,
    4500             :       // Label 128: @8996
    4501             :       GIM_Try, /*On fail goto*//*Label 129*/ 9088,
    4502             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4503             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4504             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4505             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    4506             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    4507             :         // No instruction predicates
    4508             :         // MIs[0] Rd
    4509             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4510             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4511             :         // MIs[0] Operand 1
    4512             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    4513             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4514             :         // MIs[1] Operand 0
    4515             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    4516             :         // MIs[1] Rn
    4517             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    4518             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    4519             :         // MIs[0] Operand 2
    4520             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    4521             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    4522             :         // MIs[2] Operand 0
    4523             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    4524             :         // MIs[2] Rm
    4525             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    4526             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    4527             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4528             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4529             :         // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
    4530             :         // Rule ID 1999
    4531             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    4532             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4533             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    4534             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
    4535             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    4536             :         GIR_EraseFromParent, /*InsnID*/0,
    4537             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4538             :         GIR_Done,
    4539             :       // Label 129: @9088
    4540             :       GIM_Reject,
    4541             :       GIR_Done,
    4542             :     // Label 127: @9090
    4543             :     GIM_Try, /*On fail goto*//*Label 130*/ 9415,
    4544             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
    4545             :       GIM_Try, /*On fail goto*//*Label 131*/ 9148,
    4546             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4547             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    4548             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4549             :         // MIs[0] Rt
    4550             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4551             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4552             :         // MIs[0] Operand 1
    4553             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4554             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    4555             :         // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4556             :         // Rule ID 206
    4557             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi,
    4558             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4559             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4560             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4561             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4562             :         GIR_EraseFromParent, /*InsnID*/0,
    4563             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4564             :         GIR_Done,
    4565             :       // Label 131: @9148
    4566             :       GIM_Try, /*On fail goto*//*Label 132*/ 9201,
    4567             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4568             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    4569             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4570             :         // MIs[0] Rt
    4571             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4572             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    4573             :         // MIs[0] Operand 1
    4574             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4575             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4576             :         // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4577             :         // Rule ID 207
    4578             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi,
    4579             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4580             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4581             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4582             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4583             :         GIR_EraseFromParent, /*InsnID*/0,
    4584             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4585             :         GIR_Done,
    4586             :       // Label 132: @9201
    4587             :       GIM_Try, /*On fail goto*//*Label 133*/ 9254,
    4588             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4589             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    4590             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4591             :         // MIs[0] Rt
    4592             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
    4593             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID,
    4594             :         // MIs[0] Operand 1
    4595             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4596             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    4597             :         // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4598             :         // Rule ID 209
    4599             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHi,
    4600             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4601             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4602             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4603             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4604             :         GIR_EraseFromParent, /*InsnID*/0,
    4605             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4606             :         GIR_Done,
    4607             :       // Label 133: @9254
    4608             :       GIM_Try, /*On fail goto*//*Label 134*/ 9307,
    4609             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4610             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    4611             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4612             :         // MIs[0] Rt
    4613             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4614             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    4615             :         // MIs[0] Operand 1
    4616             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4617             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4618             :         // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4619             :         // Rule ID 210
    4620             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSi,
    4621             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4622             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4623             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4624             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4625             :         GIR_EraseFromParent, /*InsnID*/0,
    4626             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4627             :         GIR_Done,
    4628             :       // Label 134: @9307
    4629             :       GIM_Try, /*On fail goto*//*Label 135*/ 9360,
    4630             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4631             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    4632             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4633             :         // MIs[0] Rt
    4634             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4635             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4636             :         // MIs[0] Operand 1
    4637             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4638             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    4639             :         // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4640             :         // Rule ID 211
    4641             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    4642             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4643             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4644             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4645             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4646             :         GIR_EraseFromParent, /*InsnID*/0,
    4647             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4648             :         GIR_Done,
    4649             :       // Label 135: @9360
    4650             :       GIM_Try, /*On fail goto*//*Label 136*/ 9413,
    4651             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4652             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    4653             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4654             :         // MIs[0] Rt
    4655             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    4656             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4657             :         // MIs[0] Operand 1
    4658             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4659             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    4660             :         // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4661             :         // Rule ID 212
    4662             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    4663             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4664             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4665             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4666             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4667             :         GIR_EraseFromParent, /*InsnID*/0,
    4668             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4669             :         GIR_Done,
    4670             :       // Label 136: @9413
    4671             :       GIM_Reject,
    4672             :       GIR_Done,
    4673             :     // Label 130: @9415
    4674             :     GIM_Try, /*On fail goto*//*Label 137*/ 9687,
    4675             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXTLOAD,
    4676             :       GIM_Try, /*On fail goto*//*Label 138*/ 9473,
    4677             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4678             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
    4679             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4680             :         // MIs[0] Rt
    4681             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4682             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    4683             :         // MIs[0] Operand 1
    4684             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4685             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    4686             :         // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4687             :         // Rule ID 215
    4688             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHWi,
    4689             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4690             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4691             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4692             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4693             :         GIR_EraseFromParent, /*InsnID*/0,
    4694             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4695             :         GIR_Done,
    4696             :       // Label 138: @9473
    4697             :       GIM_Try, /*On fail goto*//*Label 139*/ 9526,
    4698             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4699             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
    4700             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4701             :         // MIs[0] Rt
    4702             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4703             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4704             :         // MIs[0] Operand 1
    4705             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4706             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    4707             :         // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4708             :         // Rule ID 216
    4709             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHXi,
    4710             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4711             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4712             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4713             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4714             :         GIR_EraseFromParent, /*InsnID*/0,
    4715             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4716             :         GIR_Done,
    4717             :       // Label 139: @9526
    4718             :       GIM_Try, /*On fail goto*//*Label 140*/ 9579,
    4719             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4720             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    4721             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4722             :         // MIs[0] Rt
    4723             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4724             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    4725             :         // MIs[0] Operand 1
    4726             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4727             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    4728             :         // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4729             :         // Rule ID 217
    4730             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBWi,
    4731             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4732             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4733             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4734             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4735             :         GIR_EraseFromParent, /*InsnID*/0,
    4736             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4737             :         GIR_Done,
    4738             :       // Label 140: @9579
    4739             :       GIM_Try, /*On fail goto*//*Label 141*/ 9632,
    4740             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4741             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    4742             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4743             :         // MIs[0] Rt
    4744             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4745             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4746             :         // MIs[0] Operand 1
    4747             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4748             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    4749             :         // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4750             :         // Rule ID 218
    4751             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBXi,
    4752             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4753             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4754             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4755             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4756             :         GIR_EraseFromParent, /*InsnID*/0,
    4757             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4758             :         GIR_Done,
    4759             :       // Label 141: @9632
    4760             :       GIM_Try, /*On fail goto*//*Label 142*/ 9685,
    4761             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4762             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
    4763             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4764             :         // MIs[0] Rt
    4765             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4766             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4767             :         // MIs[0] Operand 1
    4768             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4769             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4770             :         // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4771             :         // Rule ID 219
    4772             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSWi,
    4773             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4774             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4775             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4776             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4777             :         GIR_EraseFromParent, /*InsnID*/0,
    4778             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4779             :         GIR_Done,
    4780             :       // Label 142: @9685
    4781             :       GIM_Reject,
    4782             :       GIR_Done,
    4783             :     // Label 137: @9687
    4784             :     GIM_Try, /*On fail goto*//*Label 143*/ 9990,
    4785             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE,
    4786             :       GIM_Try, /*On fail goto*//*Label 144*/ 9742,
    4787             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4788             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4789             :         // MIs[0] Rt
    4790             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4791             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4792             :         // MIs[0] Operand 1
    4793             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4794             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    4795             :         // (st GPR64z:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURXi GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4796             :         // Rule ID 245
    4797             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi,
    4798             :         GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt
    4799             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4800             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4801             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4802             :         GIR_EraseFromParent, /*InsnID*/0,
    4803             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4804             :         GIR_Done,
    4805             :       // Label 144: @9742
    4806             :       GIM_Try, /*On fail goto*//*Label 145*/ 9792,
    4807             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4808             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4809             :         // MIs[0] Rt
    4810             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4811             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    4812             :         // MIs[0] Operand 1
    4813             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4814             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4815             :         // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURWi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4816             :         // Rule ID 246
    4817             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi,
    4818             :         GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt
    4819             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4820             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4821             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4822             :         GIR_EraseFromParent, /*InsnID*/0,
    4823             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4824             :         GIR_Done,
    4825             :       // Label 145: @9792
    4826             :       GIM_Try, /*On fail goto*//*Label 146*/ 9841,
    4827             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4828             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4829             :         // MIs[0] Rt
    4830             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
    4831             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID,
    4832             :         // MIs[0] Operand 1
    4833             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4834             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    4835             :         // (st FPR16Op:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURHi FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4836             :         // Rule ID 248
    4837             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHi,
    4838             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4839             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4840             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4841             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4842             :         GIR_EraseFromParent, /*InsnID*/0,
    4843             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4844             :         GIR_Done,
    4845             :       // Label 146: @9841
    4846             :       GIM_Try, /*On fail goto*//*Label 147*/ 9890,
    4847             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4848             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4849             :         // MIs[0] Rt
    4850             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4851             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    4852             :         // MIs[0] Operand 1
    4853             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4854             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4855             :         // (st FPR32Op:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4856             :         // Rule ID 249
    4857             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURSi,
    4858             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4859             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4860             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4861             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4862             :         GIR_EraseFromParent, /*InsnID*/0,
    4863             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4864             :         GIR_Done,
    4865             :       // Label 147: @9890
    4866             :       GIM_Try, /*On fail goto*//*Label 148*/ 9939,
    4867             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4868             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4869             :         // MIs[0] Rt
    4870             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4871             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4872             :         // MIs[0] Operand 1
    4873             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4874             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    4875             :         // (st FPR64Op:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4876             :         // Rule ID 250
    4877             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    4878             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4879             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4880             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4881             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4882             :         GIR_EraseFromParent, /*InsnID*/0,
    4883             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4884             :         GIR_Done,
    4885             :       // Label 148: @9939
    4886             :       GIM_Try, /*On fail goto*//*Label 149*/ 9988,
    4887             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4888             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4889             :         // MIs[0] Rt
    4890             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    4891             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4892             :         // MIs[0] Operand 1
    4893             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4894             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    4895             :         // (st FPR128Op:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128Op:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4896             :         // Rule ID 251
    4897             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    4898             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4899             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4900             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4901             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4902             :         GIR_EraseFromParent, /*InsnID*/0,
    4903             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4904             :         GIR_Done,
    4905             :       // Label 149: @9988
    4906             :       GIM_Reject,
    4907             :       GIR_Done,
    4908             :     // Label 143: @9990
    4909             :     GIM_Try, /*On fail goto*//*Label 150*/ 10103,
    4910             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXTLOAD,
    4911             :       GIM_Try, /*On fail goto*//*Label 151*/ 10048,
    4912             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4913             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
    4914             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4915             :         // MIs[0] Rt
    4916             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4917             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    4918             :         // MIs[0] Operand 1
    4919             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4920             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    4921             :         // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4922             :         // Rule ID 213
    4923             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
    4924             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4925             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4926             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4927             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4928             :         GIR_EraseFromParent, /*InsnID*/0,
    4929             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4930             :         GIR_Done,
    4931             :       // Label 151: @10048
    4932             :       GIM_Try, /*On fail goto*//*Label 152*/ 10101,
    4933             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4934             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    4935             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4936             :         // MIs[0] Rt
    4937             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4938             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    4939             :         // MIs[0] Operand 1
    4940             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4941             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    4942             :         // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4943             :         // Rule ID 214
    4944             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    4945             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4946             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4947             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4948             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4949             :         GIR_EraseFromParent, /*InsnID*/0,
    4950             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4951             :         GIR_Done,
    4952             :       // Label 152: @10101
    4953             :       GIM_Reject,
    4954             :       GIR_Done,
    4955             :     // Label 150: @10103
    4956             :     GIM_Try, /*On fail goto*//*Label 153*/ 12037,
    4957             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
    4958             :       GIM_Try, /*On fail goto*//*Label 154*/ 10163,
    4959             :         GIM_CheckFeatures, GIFBS_IsLE,
    4960             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4961             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    4962             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4963             :         // MIs[0] Rt
    4964             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    4965             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4966             :         // MIs[0] Operand 1
    4967             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4968             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4969             :         // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4970             :         // Rule ID 2139
    4971             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4972             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4973             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4974             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4975             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4976             :         GIR_EraseFromParent, /*InsnID*/0,
    4977             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4978             :         GIR_Done,
    4979             :       // Label 154: @10163
    4980             :       GIM_Try, /*On fail goto*//*Label 155*/ 10218,
    4981             :         GIM_CheckFeatures, GIFBS_IsLE,
    4982             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4983             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    4984             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4985             :         // MIs[0] Rt
    4986             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    4987             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4988             :         // MIs[0] Operand 1
    4989             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4990             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4991             :         // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4992             :         // Rule ID 2140
    4993             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4994             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4995             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4996             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4997             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4998             :         GIR_EraseFromParent, /*InsnID*/0,
    4999             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5000             :         GIR_Done,
    5001             :       // Label 155: @10218
    5002             :       GIM_Try, /*On fail goto*//*Label 156*/ 10273,
    5003             :         GIM_CheckFeatures, GIFBS_IsLE,
    5004             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5005             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5006             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5007             :         // MIs[0] Rt
    5008             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5009             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5010             :         // MIs[0] Operand 1
    5011             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5012             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    5013             :         // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    5014             :         // Rule ID 2141
    5015             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    5016             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5017             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5018             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5019             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5020             :         GIR_EraseFromParent, /*InsnID*/0,
    5021             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5022             :         GIR_Done,
    5023             :       // Label 156: @10273
    5024             :       GIM_Try, /*On fail goto*//*Label 157*/ 10328,
    5025             :         GIM_CheckFeatures, GIFBS_IsLE,
    5026             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5027             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5028             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5029             :         // MIs[0] Rt
    5030             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5031             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5032             :         // MIs[0] Operand 1
    5033             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5034             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    5035             :         // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    5036             :         // Rule ID 2142
    5037             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    5038             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5039             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5040             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5041             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5042             :         GIR_EraseFromParent, /*InsnID*/0,
    5043             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5044             :         GIR_Done,
    5045             :       // Label 157: @10328
    5046             :       GIM_Try, /*On fail goto*//*Label 158*/ 10383,
    5047             :         GIM_CheckFeatures, GIFBS_IsLE,
    5048             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5049             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5050             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5051             :         // MIs[0] Rt
    5052             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5053             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5054             :         // MIs[0] Operand 1
    5055             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5056             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    5057             :         // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    5058             :         // Rule ID 2143
    5059             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    5060             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5061             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5062             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5063             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5064             :         GIR_EraseFromParent, /*InsnID*/0,
    5065             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5066             :         GIR_Done,
    5067             :       // Label 158: @10383
    5068             :       GIM_Try, /*On fail goto*//*Label 159*/ 10436,
    5069             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5070             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5071             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5072             :         // MIs[0] Rt
    5073             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5074             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5075             :         // MIs[0] Operand 1
    5076             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5077             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    5078             :         // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    5079             :         // Rule ID 2144
    5080             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    5081             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5082             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5083             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5084             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5085             :         GIR_EraseFromParent, /*InsnID*/0,
    5086             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5087             :         GIR_Done,
    5088             :       // Label 159: @10436
    5089             :       GIM_Try, /*On fail goto*//*Label 160*/ 10489,
    5090             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5091             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5092             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5093             :         // MIs[0] Rt
    5094             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5095             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5096             :         // MIs[0] Operand 1
    5097             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5098             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    5099             :         // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    5100             :         // Rule ID 2145
    5101             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    5102             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5103             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5104             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5105             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5106             :         GIR_EraseFromParent, /*InsnID*/0,
    5107             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5108             :         GIR_Done,
    5109             :       // Label 160: @10489
    5110             :       GIM_Try, /*On fail goto*//*Label 161*/ 10544,
    5111             :         GIM_CheckFeatures, GIFBS_IsLE,
    5112             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5113             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5114             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5115             :         // MIs[0] Rt
    5116             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5117             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5118             :         // MIs[0] Operand 1
    5119             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5120             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5121             :         // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5122             :         // Rule ID 2146
    5123             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5124             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5125             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5126             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5127             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5128             :         GIR_EraseFromParent, /*InsnID*/0,
    5129             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5130             :         GIR_Done,
    5131             :       // Label 161: @10544
    5132             :       GIM_Try, /*On fail goto*//*Label 162*/ 10599,
    5133             :         GIM_CheckFeatures, GIFBS_IsLE,
    5134             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5135             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5136             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5137             :         // MIs[0] Rt
    5138             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5139             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5140             :         // MIs[0] Operand 1
    5141             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5142             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5143             :         // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5144             :         // Rule ID 2147
    5145             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5146             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5147             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5148             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5149             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5150             :         GIR_EraseFromParent, /*InsnID*/0,
    5151             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5152             :         GIR_Done,
    5153             :       // Label 162: @10599
    5154             :       GIM_Try, /*On fail goto*//*Label 163*/ 10654,
    5155             :         GIM_CheckFeatures, GIFBS_IsLE,
    5156             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5157             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5158             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5159             :         // MIs[0] Rt
    5160             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5161             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5162             :         // MIs[0] Operand 1
    5163             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5164             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5165             :         // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5166             :         // Rule ID 2148
    5167             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5168             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5169             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5170             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5171             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5172             :         GIR_EraseFromParent, /*InsnID*/0,
    5173             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5174             :         GIR_Done,
    5175             :       // Label 163: @10654
    5176             :       GIM_Try, /*On fail goto*//*Label 164*/ 10709,
    5177             :         GIM_CheckFeatures, GIFBS_IsLE,
    5178             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5179             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5180             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5181             :         // MIs[0] Rt
    5182             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5183             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5184             :         // MIs[0] Operand 1
    5185             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5186             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5187             :         // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5188             :         // Rule ID 2149
    5189             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5190             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5191             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5192             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5193             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5194             :         GIR_EraseFromParent, /*InsnID*/0,
    5195             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5196             :         GIR_Done,
    5197             :       // Label 164: @10709
    5198             :       GIM_Try, /*On fail goto*//*Label 165*/ 10764,
    5199             :         GIM_CheckFeatures, GIFBS_IsLE,
    5200             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5201             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5202             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5203             :         // MIs[0] Rt
    5204             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5205             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5206             :         // MIs[0] Operand 1
    5207             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5208             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5209             :         // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5210             :         // Rule ID 2150
    5211             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5212             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5213             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5214             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5215             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5216             :         GIR_EraseFromParent, /*InsnID*/0,
    5217             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5218             :         GIR_Done,
    5219             :       // Label 165: @10764
    5220             :       GIM_Try, /*On fail goto*//*Label 166*/ 10819,
    5221             :         GIM_CheckFeatures, GIFBS_IsLE,
    5222             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5223             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5224             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5225             :         // MIs[0] Rt
    5226             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5227             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5228             :         // MIs[0] Operand 1
    5229             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5230             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5231             :         // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5232             :         // Rule ID 2151
    5233             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5234             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5235             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5236             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5237             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5238             :         GIR_EraseFromParent, /*InsnID*/0,
    5239             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5240             :         GIR_Done,
    5241             :       // Label 166: @10819
    5242             :       GIM_Try, /*On fail goto*//*Label 167*/ 10874,
    5243             :         GIM_CheckFeatures, GIFBS_IsLE,
    5244             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5245             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5246             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5247             :         // MIs[0] Rt
    5248             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5249             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5250             :         // MIs[0] Operand 1
    5251             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5252             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5253             :         // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5254             :         // Rule ID 2152
    5255             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5256             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5257             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5258             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5259             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5260             :         GIR_EraseFromParent, /*InsnID*/0,
    5261             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5262             :         GIR_Done,
    5263             :       // Label 167: @10874
    5264             :       GIM_Try, /*On fail goto*//*Label 168*/ 10927,
    5265             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5266             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5267             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5268             :         // MIs[0] Rt
    5269             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    5270             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5271             :         // MIs[0] Operand 1
    5272             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5273             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5274             :         // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5275             :         // Rule ID 2153
    5276             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5277             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5278             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5279             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5280             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5281             :         GIR_EraseFromParent, /*InsnID*/0,
    5282             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5283             :         GIR_Done,
    5284             :       // Label 168: @10927
    5285             :       GIM_Try, /*On fail goto*//*Label 169*/ 10982,
    5286             :         GIM_CheckFeatures, GIFBS_IsLE,
    5287             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5288             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5289             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5290             :         // MIs[0] Rt
    5291             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5292             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5293             :         // MIs[0] Operand 1
    5294             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5295             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5296             :         // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5297             :         // Rule ID 2166
    5298             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5299             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5300             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5301             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5302             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5303             :         GIR_EraseFromParent, /*InsnID*/0,
    5304             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5305             :         GIR_Done,
    5306             :       // Label 169: @10982
    5307             :       GIM_Try, /*On fail goto*//*Label 170*/ 11037,
    5308             :         GIM_CheckFeatures, GIFBS_IsLE,
    5309             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5310             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5311             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5312             :         // MIs[0] Rt
    5313             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5314             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5315             :         // MIs[0] Operand 1
    5316             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5317             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5318             :         // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5319             :         // Rule ID 2167
    5320             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5321             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5322             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5323             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5324             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5325             :         GIR_EraseFromParent, /*InsnID*/0,
    5326             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5327             :         GIR_Done,
    5328             :       // Label 170: @11037
    5329             :       GIM_Try, /*On fail goto*//*Label 171*/ 11092,
    5330             :         GIM_CheckFeatures, GIFBS_IsLE,
    5331             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5332             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5333             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5334             :         // MIs[0] Rt
    5335             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5336             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5337             :         // MIs[0] Operand 1
    5338             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5339             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5340             :         // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5341             :         // Rule ID 2168
    5342             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5343             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5344             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5345             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5346             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5347             :         GIR_EraseFromParent, /*InsnID*/0,
    5348             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5349             :         GIR_Done,
    5350             :       // Label 171: @11092
    5351             :       GIM_Try, /*On fail goto*//*Label 172*/ 11147,
    5352             :         GIM_CheckFeatures, GIFBS_IsLE,
    5353             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5354             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5355             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5356             :         // MIs[0] Rt
    5357             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5358             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5359             :         // MIs[0] Operand 1
    5360             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5361             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5362             :         // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5363             :         // Rule ID 2169
    5364             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5365             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5366             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5367             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5368             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5369             :         GIR_EraseFromParent, /*InsnID*/0,
    5370             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5371             :         GIR_Done,
    5372             :       // Label 172: @11147
    5373             :       GIM_Try, /*On fail goto*//*Label 173*/ 11202,
    5374             :         GIM_CheckFeatures, GIFBS_IsLE,
    5375             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5376             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5377             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5378             :         // MIs[0] Rt
    5379             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5380             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5381             :         // MIs[0] Operand 1
    5382             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5383             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5384             :         // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5385             :         // Rule ID 2170
    5386             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5387             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5388             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5389             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5390             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5391             :         GIR_EraseFromParent, /*InsnID*/0,
    5392             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5393             :         GIR_Done,
    5394             :       // Label 173: @11202
    5395             :       GIM_Try, /*On fail goto*//*Label 174*/ 11255,
    5396             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5397             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5398             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5399             :         // MIs[0] Rt
    5400             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5401             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5402             :         // MIs[0] Operand 1
    5403             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5404             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5405             :         // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5406             :         // Rule ID 2171
    5407             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5408             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5409             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5410             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5411             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5412             :         GIR_EraseFromParent, /*InsnID*/0,
    5413             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5414             :         GIR_Done,
    5415             :       // Label 174: @11255
    5416             :       GIM_Try, /*On fail goto*//*Label 175*/ 11308,
    5417             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5418             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5419             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5420             :         // MIs[0] Rt
    5421             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5422             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5423             :         // MIs[0] Operand 1
    5424             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5425             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5426             :         // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5427             :         // Rule ID 2172
    5428             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5429             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5430             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5431             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5432             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5433             :         GIR_EraseFromParent, /*InsnID*/0,
    5434             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5435             :         GIR_Done,
    5436             :       // Label 175: @11308
    5437             :       GIM_Try, /*On fail goto*//*Label 176*/ 11363,
    5438             :         GIM_CheckFeatures, GIFBS_IsLE,
    5439             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5440             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5441             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5442             :         // MIs[0] Rt
    5443             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5444             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5445             :         // MIs[0] Operand 1
    5446             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5447             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5448             :         // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5449             :         // Rule ID 2173
    5450             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5451             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5452             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5453             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5454             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5455             :         GIR_EraseFromParent, /*InsnID*/0,
    5456             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5457             :         GIR_Done,
    5458             :       // Label 176: @11363
    5459             :       GIM_Try, /*On fail goto*//*Label 177*/ 11418,
    5460             :         GIM_CheckFeatures, GIFBS_IsLE,
    5461             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5462             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5463             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5464             :         // MIs[0] Rt
    5465             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5466             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5467             :         // MIs[0] Operand 1
    5468             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5469             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5470             :         // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5471             :         // Rule ID 2174
    5472             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5473             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5474             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5475             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5476             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5477             :         GIR_EraseFromParent, /*InsnID*/0,
    5478             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5479             :         GIR_Done,
    5480             :       // Label 177: @11418
    5481             :       GIM_Try, /*On fail goto*//*Label 178*/ 11473,
    5482             :         GIM_CheckFeatures, GIFBS_IsLE,
    5483             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5484             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5485             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5486             :         // MIs[0] Rt
    5487             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5488             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5489             :         // MIs[0] Operand 1
    5490             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5491             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5492             :         // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5493             :         // Rule ID 2175
    5494             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5495             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5496             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5497             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5498             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5499             :         GIR_EraseFromParent, /*InsnID*/0,
    5500             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5501             :         GIR_Done,
    5502             :       // Label 178: @11473
    5503             :       GIM_Try, /*On fail goto*//*Label 179*/ 11528,
    5504             :         GIM_CheckFeatures, GIFBS_IsLE,
    5505             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5506             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5507             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5508             :         // MIs[0] Rt
    5509             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5510             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5511             :         // MIs[0] Operand 1
    5512             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5513             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5514             :         // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5515             :         // Rule ID 2176
    5516             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5517             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5518             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5519             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5520             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5521             :         GIR_EraseFromParent, /*InsnID*/0,
    5522             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5523             :         GIR_Done,
    5524             :       // Label 179: @11528
    5525             :       GIM_Try, /*On fail goto*//*Label 180*/ 11583,
    5526             :         GIM_CheckFeatures, GIFBS_IsLE,
    5527             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5528             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5529             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5530             :         // MIs[0] Rt
    5531             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5532             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5533             :         // MIs[0] Operand 1
    5534             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5535             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5536             :         // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5537             :         // Rule ID 2177
    5538             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5539             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5540             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5541             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5542             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5543             :         GIR_EraseFromParent, /*InsnID*/0,
    5544             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5545             :         GIR_Done,
    5546             :       // Label 180: @11583
    5547             :       GIM_Try, /*On fail goto*//*Label 181*/ 11638,
    5548             :         GIM_CheckFeatures, GIFBS_IsLE,
    5549             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5550             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5551             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5552             :         // MIs[0] Rt
    5553             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5554             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5555             :         // MIs[0] Operand 1
    5556             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5557             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5558             :         // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5559             :         // Rule ID 2178
    5560             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5561             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5562             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5563             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5564             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5565             :         GIR_EraseFromParent, /*InsnID*/0,
    5566             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5567             :         GIR_Done,
    5568             :       // Label 181: @11638
    5569             :       GIM_Try, /*On fail goto*//*Label 182*/ 11693,
    5570             :         GIM_CheckFeatures, GIFBS_IsLE,
    5571             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5572             :         GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5573             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5574             :         // MIs[0] Rt
    5575             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5576             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5577             :         // MIs[0] Operand 1
    5578             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5579             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5580             :         // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5581             :         // Rule ID 2179
    5582             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5583             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5584             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5585             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5586             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5587             :         GIR_EraseFromParent, /*InsnID*/0,
    5588             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5589             :         GIR_Done,
    5590             :       // Label 182: @11693
    5591             :       GIM_Try, /*On fail goto*//*Label 183*/ 11750,
    5592             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5593             :         GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5594             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
    5595             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5596             :         // MIs[0] Rt
    5597             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5598             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5599             :         // MIs[0] Operand 1
    5600             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5601             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
    5602             :         // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
    5603             :         // Rule ID 2158
    5604             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui,
    5605             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5606             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5607             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5608             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5609             :         GIR_EraseFromParent, /*InsnID*/0,
    5610             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5611             :         GIR_Done,
    5612             :       // Label 183: @11750
    5613             :       GIM_Try, /*On fail goto*//*Label 184*/ 11807,
    5614             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5615             :         GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5616             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    5617             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5618             :         // MIs[0] Rt
    5619             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5620             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5621             :         // MIs[0] Operand 1
    5622             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5623             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
    5624             :         // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
    5625             :         // Rule ID 2159
    5626             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
    5627             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5628             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5629             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5630             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5631             :         GIR_EraseFromParent, /*InsnID*/0,
    5632             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5633             :         GIR_Done,
    5634             :       // Label 184: @11807
    5635             :       GIM_Try, /*On fail goto*//*Label 185*/ 11864,
    5636             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5637             :         GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5638             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    5639             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5640             :         // MIs[0] Rt
    5641             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5642             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5643             :         // MIs[0] Operand 1
    5644             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5645             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
    5646             :         // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
    5647             :         // Rule ID 2160
    5648             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
    5649             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5650             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5651             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5652             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5653             :         GIR_EraseFromParent, /*InsnID*/0,
    5654             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5655             :         GIR_Done,
    5656             :       // Label 185: @11864
    5657             :       GIM_Try, /*On fail goto*//*Label 186*/ 11921,
    5658             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5659             :         GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5660             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
    5661             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5662             :         // MIs[0] Rt
    5663             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5664             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5665             :         // MIs[0] Operand 1
    5666             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5667             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    5668             :         // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5669             :         // Rule ID 2180
    5670             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
    5671             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5672             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5673             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5674             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5675             :         GIR_EraseFromParent, /*InsnID*/0,
    5676             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5677             :         GIR_Done,
    5678             :       // Label 186: @11921
    5679             :       GIM_Try, /*On fail goto*//*Label 187*/ 11978,
    5680             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5681             :         GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5682             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    5683             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5684             :         // MIs[0] Rt
    5685             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5686             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5687             :         // MIs[0] Operand 1
    5688             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5689             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    5690             :         // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5691             :         // Rule ID 2181
    5692             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    5693             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5694             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5695             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5696             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5697             :         GIR_EraseFromParent, /*InsnID*/0,
    5698             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5699             :         GIR_Done,
    5700             :       // Label 187: @11978
    5701             :       GIM_Try, /*On fail goto*//*Label 188*/ 12035,
    5702             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5703             :         GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
    5704             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    5705             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5706             :         // MIs[0] Rt
    5707             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5708             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5709             :         // MIs[0] Operand 1
    5710             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5711             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    5712             :         // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5713             :         // Rule ID 2182
    5714             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    5715             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5716             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5717             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5718             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5719             :         GIR_EraseFromParent, /*InsnID*/0,
    5720             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5721             :         GIR_Done,
    5722             :       // Label 188: @12035
    5723             :       GIM_Reject,
    5724             :       GIR_Done,
    5725             :     // Label 153: @12037
    5726             :     GIM_Try, /*On fail goto*//*Label 189*/ 12142,
    5727             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE,
    5728             :       GIM_Try, /*On fail goto*//*Label 190*/ 12091,
    5729             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5730             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5731             :         // MIs[0] Rt
    5732             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5733             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5734             :         // MIs[0] Operand 1
    5735             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5736             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5737             :         // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5738             :         // Rule ID 2268
    5739             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5740             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5741             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5742             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5743             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5744             :         GIR_EraseFromParent, /*InsnID*/0,
    5745             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5746             :         GIR_Done,
    5747             :       // Label 190: @12091
    5748             :       GIM_Try, /*On fail goto*//*Label 191*/ 12140,
    5749             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5750             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5751             :         // MIs[0] Rt
    5752             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5753             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5754             :         // MIs[0] Operand 1
    5755             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5756             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5757             :         // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5758             :         // Rule ID 2269
    5759             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5760             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5761             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5762             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5763             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5764             :         GIR_EraseFromParent, /*InsnID*/0,
    5765             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5766             :         GIR_Done,
    5767             :       // Label 191: @12140
    5768             :       GIM_Reject,
    5769             :       GIR_Done,
    5770             :     // Label 189: @12142
    5771             :     GIM_Try, /*On fail goto*//*Label 192*/ 12361,
    5772             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXTLOAD,
    5773             :       GIM_Try, /*On fail goto*//*Label 193*/ 12200,
    5774             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5775             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    5776             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5777             :         // MIs[0] Rt
    5778             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5779             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5780             :         // MIs[0] Operand 1
    5781             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5782             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
    5783             :         // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
    5784             :         // Rule ID 2156
    5785             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
    5786             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5787             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5788             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5789             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5790             :         GIR_EraseFromParent, /*InsnID*/0,
    5791             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5792             :         GIR_Done,
    5793             :       // Label 193: @12200
    5794             :       GIM_Try, /*On fail goto*//*Label 194*/ 12253,
    5795             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5796             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
    5797             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5798             :         // MIs[0] Rt
    5799             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5800             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5801             :         // MIs[0] Operand 1
    5802             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5803             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    5804             :         // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5805             :         // Rule ID 2187
    5806             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
    5807             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5808             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5809             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5810             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5811             :         GIR_EraseFromParent, /*InsnID*/0,
    5812             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5813             :         GIR_Done,
    5814             :       // Label 194: @12253
    5815             :       GIM_Try, /*On fail goto*//*Label 195*/ 12306,
    5816             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5817             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    5818             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5819             :         // MIs[0] Rt
    5820             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5821             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5822             :         // MIs[0] Operand 1
    5823             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5824             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    5825             :         // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5826             :         // Rule ID 2188
    5827             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    5828             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5829             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5830             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5831             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5832             :         GIR_EraseFromParent, /*InsnID*/0,
    5833             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5834             :         GIR_Done,
    5835             :       // Label 195: @12306
    5836             :       GIM_Try, /*On fail goto*//*Label 196*/ 12359,
    5837             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5838             :         GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
    5839             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5840             :         // MIs[0] Rt
    5841             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5842             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    5843             :         // MIs[0] Operand 1
    5844             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5845             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    5846             :         // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5847             :         // Rule ID 2189
    5848             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    5849             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5850             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5851             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5852             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5853             :         GIR_EraseFromParent, /*InsnID*/0,
    5854             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5855             :         GIR_Done,
    5856             :       // Label 196: @12359
    5857             :       GIM_Reject,
    5858             :       GIR_Done,
    5859             :     // Label 192: @12361
    5860             :     GIM_Try, /*On fail goto*//*Label 197*/ 16327,
    5861             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5862             :       GIM_Try, /*On fail goto*//*Label 198*/ 12447,
    5863             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5864             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5865             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5866             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5867             :         // No instruction predicates
    5868             :         // MIs[0] dst
    5869             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5870             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5871             :         // MIs[0] Operand 1
    5872             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5873             :         // MIs[0] Rd
    5874             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    5875             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    5876             :         // MIs[0] Rn
    5877             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    5878             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    5879             :         // MIs[0] imm
    5880             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5881             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5882             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL8,
    5883             :         // MIs[1] Operand 0
    5884             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5885             :         // MIs[1] Operand 1
    5886             :         // No operand predicates
    5887             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5888             :         // (intrinsic_wo_chain:{ *:[v8i8] } 359:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm)  =>  (SLIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
    5889             :         // Rule ID 1615
    5890             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i8_shift,
    5891             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5892             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5893             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5894             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5895             :         GIR_EraseFromParent, /*InsnID*/0,
    5896             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5897             :         GIR_Done,
    5898             :       // Label 198: @12447
    5899             :       GIM_Try, /*On fail goto*//*Label 199*/ 12528,
    5900             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5901             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5902             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5903             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5904             :         // No instruction predicates
    5905             :         // MIs[0] dst
    5906             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5907             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5908             :         // MIs[0] Operand 1
    5909             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5910             :         // MIs[0] Rd
    5911             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    5912             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    5913             :         // MIs[0] Rn
    5914             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    5915             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    5916             :         // MIs[0] imm
    5917             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5918             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5919             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL8,
    5920             :         // MIs[1] Operand 0
    5921             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5922             :         // MIs[1] Operand 1
    5923             :         // No operand predicates
    5924             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5925             :         // (intrinsic_wo_chain:{ *:[v16i8] } 359:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm)  =>  (SLIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
    5926             :         // Rule ID 1616
    5927             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv16i8_shift,
    5928             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5929             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5930             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5931             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5932             :         GIR_EraseFromParent, /*InsnID*/0,
    5933             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5934             :         GIR_Done,
    5935             :       // Label 199: @12528
    5936             :       GIM_Try, /*On fail goto*//*Label 200*/ 12609,
    5937             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5938             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5939             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5940             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5941             :         // No instruction predicates
    5942             :         // MIs[0] dst
    5943             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5944             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5945             :         // MIs[0] Operand 1
    5946             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5947             :         // MIs[0] Rd
    5948             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    5949             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    5950             :         // MIs[0] Rn
    5951             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    5952             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    5953             :         // MIs[0] imm
    5954             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5955             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5956             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL16,
    5957             :         // MIs[1] Operand 0
    5958             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5959             :         // MIs[1] Operand 1
    5960             :         // No operand predicates
    5961             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5962             :         // (intrinsic_wo_chain:{ *:[v4i16] } 359:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm)  =>  (SLIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    5963             :         // Rule ID 1617
    5964             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i16_shift,
    5965             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5966             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5967             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5968             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5969             :         GIR_EraseFromParent, /*InsnID*/0,
    5970             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5971             :         GIR_Done,
    5972             :       // Label 200: @12609
    5973             :       GIM_Try, /*On fail goto*//*Label 201*/ 12690,
    5974             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5975             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5976             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5977             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5978             :         // No instruction predicates
    5979             :         // MIs[0] dst
    5980             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5981             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5982             :         // MIs[0] Operand 1
    5983             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5984             :         // MIs[0] Rd
    5985             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    5986             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    5987             :         // MIs[0] Rn
    5988             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    5989             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    5990             :         // MIs[0] imm
    5991             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5992             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5993             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL16,
    5994             :         // MIs[1] Operand 0
    5995             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5996             :         // MIs[1] Operand 1
    5997             :         // No operand predicates
    5998             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5999             :         // (intrinsic_wo_chain:{ *:[v8i16] } 359:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm)  =>  (SLIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6000             :         // Rule ID 1618
    6001             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i16_shift,
    6002             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6003             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6004             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6005             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6006             :         GIR_EraseFromParent, /*InsnID*/0,
    6007             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6008             :         GIR_Done,
    6009             :       // Label 201: @12690
    6010             :       GIM_Try, /*On fail goto*//*Label 202*/ 12771,
    6011             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6012             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6013             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6014             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6015             :         // No instruction predicates
    6016             :         // MIs[0] dst
    6017             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6018             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6019             :         // MIs[0] Operand 1
    6020             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    6021             :         // MIs[0] Rd
    6022             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6023             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6024             :         // MIs[0] Rn
    6025             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6026             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6027             :         // MIs[0] imm
    6028             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6029             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6030             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL32,
    6031             :         // MIs[1] Operand 0
    6032             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6033             :         // MIs[1] Operand 1
    6034             :         // No operand predicates
    6035             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6036             :         // (intrinsic_wo_chain:{ *:[v2i32] } 359:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SLIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6037             :         // Rule ID 1619
    6038             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i32_shift,
    6039             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6040             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6041             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6042             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6043             :         GIR_EraseFromParent, /*InsnID*/0,
    6044             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6045             :         GIR_Done,
    6046             :       // Label 202: @12771
    6047             :       GIM_Try, /*On fail goto*//*Label 203*/ 12852,
    6048             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6049             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6050             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6051             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6052             :         // No instruction predicates
    6053             :         // MIs[0] dst
    6054             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6055             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6056             :         // MIs[0] Operand 1
    6057             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    6058             :         // MIs[0] Rd
    6059             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6060             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6061             :         // MIs[0] Rn
    6062             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6063             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6064             :         // MIs[0] imm
    6065             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6066             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6067             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL32,
    6068             :         // MIs[1] Operand 0
    6069             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6070             :         // MIs[1] Operand 1
    6071             :         // No operand predicates
    6072             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6073             :         // (intrinsic_wo_chain:{ *:[v4i32] } 359:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SLIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6074             :         // Rule ID 1620
    6075             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i32_shift,
    6076             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6077             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6078             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6079             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6080             :         GIR_EraseFromParent, /*InsnID*/0,
    6081             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6082             :         GIR_Done,
    6083             :       // Label 203: @12852
    6084             :       GIM_Try, /*On fail goto*//*Label 204*/ 12933,
    6085             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6086             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6087             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6088             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6089             :         // No instruction predicates
    6090             :         // MIs[0] dst
    6091             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    6092             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6093             :         // MIs[0] Operand 1
    6094             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    6095             :         // MIs[0] Rd
    6096             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6097             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6098             :         // MIs[0] Rn
    6099             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    6100             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6101             :         // MIs[0] imm
    6102             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6103             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6104             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL64,
    6105             :         // MIs[1] Operand 0
    6106             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6107             :         // MIs[1] Operand 1
    6108             :         // No operand predicates
    6109             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6110             :         // (intrinsic_wo_chain:{ *:[v2i64] } 359:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SLIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6111             :         // Rule ID 1621
    6112             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i64_shift,
    6113             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6114             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6115             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6116             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6117             :         GIR_EraseFromParent, /*InsnID*/0,
    6118             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6119             :         GIR_Done,
    6120             :       // Label 204: @12933
    6121             :       GIM_Try, /*On fail goto*//*Label 205*/ 13014,
    6122             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6123             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6124             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6125             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6126             :         // No instruction predicates
    6127             :         // MIs[0] dst
    6128             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6129             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6130             :         // MIs[0] Operand 1
    6131             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6132             :         // MIs[0] Rd
    6133             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    6134             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6135             :         // MIs[0] Rn
    6136             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    6137             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6138             :         // MIs[0] imm
    6139             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6140             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6141             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8,
    6142             :         // MIs[1] Operand 0
    6143             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6144             :         // MIs[1] Operand 1
    6145             :         // No operand predicates
    6146             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6147             :         // (intrinsic_wo_chain:{ *:[v8i8] } 360:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SRIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
    6148             :         // Rule ID 1648
    6149             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i8_shift,
    6150             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6151             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6152             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6153             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6154             :         GIR_EraseFromParent, /*InsnID*/0,
    6155             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6156             :         GIR_Done,
    6157             :       // Label 205: @13014
    6158             :       GIM_Try, /*On fail goto*//*Label 206*/ 13095,
    6159             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6160             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6161             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6162             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6163             :         // No instruction predicates
    6164             :         // MIs[0] dst
    6165             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    6166             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6167             :         // MIs[0] Operand 1
    6168             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6169             :         // MIs[0] Rd
    6170             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    6171             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6172             :         // MIs[0] Rn
    6173             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    6174             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6175             :         // MIs[0] imm
    6176             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6177             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6178             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8,
    6179             :         // MIs[1] Operand 0
    6180             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6181             :         // MIs[1] Operand 1
    6182             :         // No operand predicates
    6183             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6184             :         // (intrinsic_wo_chain:{ *:[v16i8] } 360:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SRIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
    6185             :         // Rule ID 1649
    6186             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv16i8_shift,
    6187             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6188             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6189             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6190             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6191             :         GIR_EraseFromParent, /*InsnID*/0,
    6192             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6193             :         GIR_Done,
    6194             :       // Label 206: @13095
    6195             :       GIM_Try, /*On fail goto*//*Label 207*/ 13176,
    6196             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6197             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6198             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6199             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6200             :         // No instruction predicates
    6201             :         // MIs[0] dst
    6202             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6203             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6204             :         // MIs[0] Operand 1
    6205             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6206             :         // MIs[0] Rd
    6207             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    6208             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6209             :         // MIs[0] Rn
    6210             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    6211             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6212             :         // MIs[0] imm
    6213             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6214             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6215             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16,
    6216             :         // MIs[1] Operand 0
    6217             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6218             :         // MIs[1] Operand 1
    6219             :         // No operand predicates
    6220             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6221             :         // (intrinsic_wo_chain:{ *:[v4i16] } 360:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SRIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6222             :         // Rule ID 1650
    6223             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i16_shift,
    6224             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6225             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6226             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6227             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6228             :         GIR_EraseFromParent, /*InsnID*/0,
    6229             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6230             :         GIR_Done,
    6231             :       // Label 207: @13176
    6232             :       GIM_Try, /*On fail goto*//*Label 208*/ 13257,
    6233             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6234             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6235             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6236             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6237             :         // No instruction predicates
    6238             :         // MIs[0] dst
    6239             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    6240             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6241             :         // MIs[0] Operand 1
    6242             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6243             :         // MIs[0] Rd
    6244             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6245             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6246             :         // MIs[0] Rn
    6247             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    6248             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6249             :         // MIs[0] imm
    6250             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6251             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6252             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16,
    6253             :         // MIs[1] Operand 0
    6254             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6255             :         // MIs[1] Operand 1
    6256             :         // No operand predicates
    6257             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6258             :         // (intrinsic_wo_chain:{ *:[v8i16] } 360:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SRIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6259             :         // Rule ID 1651
    6260             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i16_shift,
    6261             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6262             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6263             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6264             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6265             :         GIR_EraseFromParent, /*InsnID*/0,
    6266             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6267             :         GIR_Done,
    6268             :       // Label 208: @13257
    6269             :       GIM_Try, /*On fail goto*//*Label 209*/ 13338,
    6270             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6271             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6272             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6273             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6274             :         // No instruction predicates
    6275             :         // MIs[0] dst
    6276             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6277             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6278             :         // MIs[0] Operand 1
    6279             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6280             :         // MIs[0] Rd
    6281             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6282             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6283             :         // MIs[0] Rn
    6284             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6285             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6286             :         // MIs[0] imm
    6287             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6288             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6289             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6290             :         // MIs[1] Operand 0
    6291             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6292             :         // MIs[1] Operand 1
    6293             :         // No operand predicates
    6294             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6295             :         // (intrinsic_wo_chain:{ *:[v2i32] } 360:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SRIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6296             :         // Rule ID 1652
    6297             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i32_shift,
    6298             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6299             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6300             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6301             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6302             :         GIR_EraseFromParent, /*InsnID*/0,
    6303             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6304             :         GIR_Done,
    6305             :       // Label 209: @13338
    6306             :       GIM_Try, /*On fail goto*//*Label 210*/ 13419,
    6307             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6308             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6309             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6310             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6311             :         // No instruction predicates
    6312             :         // MIs[0] dst
    6313             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6314             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6315             :         // MIs[0] Operand 1
    6316             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6317             :         // MIs[0] Rd
    6318             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6319             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6320             :         // MIs[0] Rn
    6321             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6322             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6323             :         // MIs[0] imm
    6324             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6325             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6326             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6327             :         // MIs[1] Operand 0
    6328             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6329             :         // MIs[1] Operand 1
    6330             :         // No operand predicates
    6331             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6332             :         // (intrinsic_wo_chain:{ *:[v4i32] } 360:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SRIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6333             :         // Rule ID 1653
    6334             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i32_shift,
    6335             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6336             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6337             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6338             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6339             :         GIR_EraseFromParent, /*InsnID*/0,
    6340             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6341             :         GIR_Done,
    6342             :       // Label 210: @13419
    6343             :       GIM_Try, /*On fail goto*//*Label 211*/ 13500,
    6344             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6345             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6346             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6347             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6348             :         // No instruction predicates
    6349             :         // MIs[0] dst
    6350             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    6351             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6352             :         // MIs[0] Operand 1
    6353             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6354             :         // MIs[0] Rd
    6355             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6356             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6357             :         // MIs[0] Rn
    6358             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    6359             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6360             :         // MIs[0] imm
    6361             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6362             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6363             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    6364             :         // MIs[1] Operand 0
    6365             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6366             :         // MIs[1] Operand 1
    6367             :         // No operand predicates
    6368             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6369             :         // (intrinsic_wo_chain:{ *:[v2i64] } 360:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6370             :         // Rule ID 1654
    6371             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i64_shift,
    6372             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6373             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6374             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6375             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6376             :         GIR_EraseFromParent, /*InsnID*/0,
    6377             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6378             :         GIR_Done,
    6379             :       // Label 211: @13500
    6380             :       GIM_Try, /*On fail goto*//*Label 212*/ 13579,
    6381             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6382             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6383             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6384             :         // No instruction predicates
    6385             :         // MIs[0] dst
    6386             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    6387             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6388             :         // MIs[0] Operand 1
    6389             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    6390             :         // MIs[0] Rd
    6391             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6392             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6393             :         // MIs[0] Rn
    6394             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    6395             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6396             :         // MIs[0] imm
    6397             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6398             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6399             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL64,
    6400             :         // MIs[1] Operand 0
    6401             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6402             :         // MIs[1] Operand 1
    6403             :         // No operand predicates
    6404             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6405             :         // (intrinsic_wo_chain:{ *:[v1i64] } 359:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SLId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)
    6406             :         // Rule ID 2942
    6407             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLId,
    6408             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6409             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6410             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6411             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6412             :         GIR_EraseFromParent, /*InsnID*/0,
    6413             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6414             :         GIR_Done,
    6415             :       // Label 212: @13579
    6416             :       GIM_Try, /*On fail goto*//*Label 213*/ 13658,
    6417             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6418             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6419             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6420             :         // No instruction predicates
    6421             :         // MIs[0] dst
    6422             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    6423             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6424             :         // MIs[0] Operand 1
    6425             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6426             :         // MIs[0] Rd
    6427             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6428             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6429             :         // MIs[0] Rn
    6430             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    6431             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6432             :         // MIs[0] imm
    6433             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6434             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6435             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    6436             :         // MIs[1] Operand 0
    6437             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6438             :         // MIs[1] Operand 1
    6439             :         // No operand predicates
    6440             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6441             :         // (intrinsic_wo_chain:{ *:[v1i64] } 360:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    6442             :         // Rule ID 2943
    6443             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRId,
    6444             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6445             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6446             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6447             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6448             :         GIR_EraseFromParent, /*InsnID*/0,
    6449             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6450             :         GIR_Done,
    6451             :       // Label 213: @13658
    6452             :       GIM_Try, /*On fail goto*//*Label 214*/ 13727,
    6453             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6454             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6455             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6456             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6457             :         // No instruction predicates
    6458             :         // MIs[0] Rd
    6459             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6460             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6461             :         // MIs[0] Operand 1
    6462             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn,
    6463             :         // MIs[0] Rn
    6464             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6465             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6466             :         // MIs[0] imm
    6467             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6468             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6469             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6470             :         // MIs[1] Operand 0
    6471             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6472             :         // MIs[1] Operand 1
    6473             :         // No operand predicates
    6474             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6475             :         // (intrinsic_wo_chain:{ *:[i32] } 292:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6476             :         // Rule ID 1567
    6477             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNs,
    6478             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6479             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6480             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6481             :         GIR_EraseFromParent, /*InsnID*/0,
    6482             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6483             :         GIR_Done,
    6484             :       // Label 214: @13727
    6485             :       GIM_Try, /*On fail goto*//*Label 215*/ 13796,
    6486             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6487             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6488             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6489             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6490             :         // No instruction predicates
    6491             :         // MIs[0] Rd
    6492             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6493             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6494             :         // MIs[0] Operand 1
    6495             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun,
    6496             :         // MIs[0] Rn
    6497             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6498             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6499             :         // MIs[0] imm
    6500             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6501             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6502             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6503             :         // MIs[1] Operand 0
    6504             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6505             :         // MIs[1] Operand 1
    6506             :         // No operand predicates
    6507             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6508             :         // (intrinsic_wo_chain:{ *:[i32] } 293:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6509             :         // Rule ID 1568
    6510             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNs,
    6511             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6512             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6513             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6514             :         GIR_EraseFromParent, /*InsnID*/0,
    6515             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6516             :         GIR_Done,
    6517             :       // Label 215: @13796
    6518             :       GIM_Try, /*On fail goto*//*Label 216*/ 13865,
    6519             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6520             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6521             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6522             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6523             :         // No instruction predicates
    6524             :         // MIs[0] Rd
    6525             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6526             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6527             :         // MIs[0] Operand 1
    6528             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn,
    6529             :         // MIs[0] Rn
    6530             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6531             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6532             :         // MIs[0] imm
    6533             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6534             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6535             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6536             :         // MIs[1] Operand 0
    6537             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6538             :         // MIs[1] Operand 1
    6539             :         // No operand predicates
    6540             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6541             :         // (intrinsic_wo_chain:{ *:[i32] } 296:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6542             :         // Rule ID 1573
    6543             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNs,
    6544             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6545             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6546             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6547             :         GIR_EraseFromParent, /*InsnID*/0,
    6548             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6549             :         GIR_Done,
    6550             :       // Label 216: @13865
    6551             :       GIM_Try, /*On fail goto*//*Label 217*/ 13934,
    6552             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6553             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6554             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6555             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6556             :         // No instruction predicates
    6557             :         // MIs[0] Rd
    6558             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6559             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6560             :         // MIs[0] Operand 1
    6561             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun,
    6562             :         // MIs[0] Rn
    6563             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6564             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6565             :         // MIs[0] imm
    6566             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6567             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6568             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6569             :         // MIs[1] Operand 0
    6570             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6571             :         // MIs[1] Operand 1
    6572             :         // No operand predicates
    6573             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6574             :         // (intrinsic_wo_chain:{ *:[i32] } 297:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6575             :         // Rule ID 1574
    6576             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNs,
    6577             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6578             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6579             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6580             :         GIR_EraseFromParent, /*InsnID*/0,
    6581             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6582             :         GIR_Done,
    6583             :       // Label 217: @13934
    6584             :       GIM_Try, /*On fail goto*//*Label 218*/ 14003,
    6585             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6586             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6587             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6588             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6589             :         // No instruction predicates
    6590             :         // MIs[0] Rd
    6591             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6592             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6593             :         // MIs[0] Operand 1
    6594             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn,
    6595             :         // MIs[0] Rn
    6596             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6597             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6598             :         // MIs[0] imm
    6599             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6600             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6601             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6602             :         // MIs[1] Operand 0
    6603             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6604             :         // MIs[1] Operand 1
    6605             :         // No operand predicates
    6606             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6607             :         // (intrinsic_wo_chain:{ *:[i32] } 340:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6608             :         // Rule ID 1579
    6609             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNs,
    6610             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6611             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6612             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6613             :         GIR_EraseFromParent, /*InsnID*/0,
    6614             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6615             :         GIR_Done,
    6616             :       // Label 218: @14003
    6617             :       GIM_Try, /*On fail goto*//*Label 219*/ 14072,
    6618             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6619             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6620             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6621             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6622             :         // No instruction predicates
    6623             :         // MIs[0] Rd
    6624             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6625             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6626             :         // MIs[0] Operand 1
    6627             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn,
    6628             :         // MIs[0] Rn
    6629             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6630             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6631             :         // MIs[0] imm
    6632             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6633             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6634             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6635             :         // MIs[1] Operand 0
    6636             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6637             :         // MIs[1] Operand 1
    6638             :         // No operand predicates
    6639             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6640             :         // (intrinsic_wo_chain:{ *:[i32] } 342:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6641             :         // Rule ID 1582
    6642             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNs,
    6643             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6644             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6645             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6646             :         GIR_EraseFromParent, /*InsnID*/0,
    6647             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6648             :         GIR_Done,
    6649             :       // Label 219: @14072
    6650             :       GIM_Try, /*On fail goto*//*Label 220*/ 14141,
    6651             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6652             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6653             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6654             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6655             :         // No instruction predicates
    6656             :         // MIs[0] Rd
    6657             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6658             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6659             :         // MIs[0] Operand 1
    6660             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn,
    6661             :         // MIs[0] Rn
    6662             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6663             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6664             :         // MIs[0] imm
    6665             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6666             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6667             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6668             :         // MIs[1] Operand 0
    6669             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6670             :         // MIs[1] Operand 1
    6671             :         // No operand predicates
    6672             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6673             :         // (intrinsic_wo_chain:{ *:[v8i8] } 264:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (RSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6674             :         // Rule ID 1602
    6675             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i8_shift,
    6676             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6677             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6678             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6679             :         GIR_EraseFromParent, /*InsnID*/0,
    6680             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6681             :         GIR_Done,
    6682             :       // Label 220: @14141
    6683             :       GIM_Try, /*On fail goto*//*Label 221*/ 14210,
    6684             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6685             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6686             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6687             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6688             :         // No instruction predicates
    6689             :         // MIs[0] Rd
    6690             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6691             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6692             :         // MIs[0] Operand 1
    6693             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn,
    6694             :         // MIs[0] Rn
    6695             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6696             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6697             :         // MIs[0] imm
    6698             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6699             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6700             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6701             :         // MIs[1] Operand 0
    6702             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6703             :         // MIs[1] Operand 1
    6704             :         // No operand predicates
    6705             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6706             :         // (intrinsic_wo_chain:{ *:[v4i16] } 264:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (RSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6707             :         // Rule ID 1603
    6708             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i16_shift,
    6709             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6710             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6711             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6712             :         GIR_EraseFromParent, /*InsnID*/0,
    6713             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6714             :         GIR_Done,
    6715             :       // Label 221: @14210
    6716             :       GIM_Try, /*On fail goto*//*Label 222*/ 14279,
    6717             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6718             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6719             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6720             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6721             :         // No instruction predicates
    6722             :         // MIs[0] Rd
    6723             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6724             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6725             :         // MIs[0] Operand 1
    6726             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn,
    6727             :         // MIs[0] Rn
    6728             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6729             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6730             :         // MIs[0] imm
    6731             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6732             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6733             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    6734             :         // MIs[1] Operand 0
    6735             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6736             :         // MIs[1] Operand 1
    6737             :         // No operand predicates
    6738             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6739             :         // (intrinsic_wo_chain:{ *:[v2i32] } 264:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (RSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6740             :         // Rule ID 1604
    6741             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv2i32_shift,
    6742             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6743             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6744             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6745             :         GIR_EraseFromParent, /*InsnID*/0,
    6746             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6747             :         GIR_Done,
    6748             :       // Label 222: @14279
    6749             :       GIM_Try, /*On fail goto*//*Label 223*/ 14348,
    6750             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6751             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6752             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6753             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6754             :         // No instruction predicates
    6755             :         // MIs[0] Rd
    6756             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6757             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6758             :         // MIs[0] Operand 1
    6759             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn,
    6760             :         // MIs[0] Rn
    6761             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6762             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6763             :         // MIs[0] imm
    6764             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6765             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6766             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6767             :         // MIs[1] Operand 0
    6768             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6769             :         // MIs[1] Operand 1
    6770             :         // No operand predicates
    6771             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6772             :         // (intrinsic_wo_chain:{ *:[v8i8] } 292:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (SQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6773             :         // Rule ID 1622
    6774             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i8_shift,
    6775             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6776             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6777             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6778             :         GIR_EraseFromParent, /*InsnID*/0,
    6779             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6780             :         GIR_Done,
    6781             :       // Label 223: @14348
    6782             :       GIM_Try, /*On fail goto*//*Label 224*/ 14417,
    6783             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6784             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6785             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6786             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6787             :         // No instruction predicates
    6788             :         // MIs[0] Rd
    6789             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6790             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6791             :         // MIs[0] Operand 1
    6792             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn,
    6793             :         // MIs[0] Rn
    6794             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6795             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6796             :         // MIs[0] imm
    6797             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6798             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6799             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6800             :         // MIs[1] Operand 0
    6801             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6802             :         // MIs[1] Operand 1
    6803             :         // No operand predicates
    6804             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6805             :         // (intrinsic_wo_chain:{ *:[v4i16] } 292:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (SQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6806             :         // Rule ID 1623
    6807             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i16_shift,
    6808             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6809             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6810             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6811             :         GIR_EraseFromParent, /*InsnID*/0,
    6812             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6813             :         GIR_Done,
    6814             :       // Label 224: @14417
    6815             :       GIM_Try, /*On fail goto*//*Label 225*/ 14486,
    6816             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6817             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6818             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6819             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6820             :         // No instruction predicates
    6821             :         // MIs[0] Rd
    6822             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6823             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6824             :         // MIs[0] Operand 1
    6825             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn,
    6826             :         // MIs[0] Rn
    6827             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6828             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6829             :         // MIs[0] imm
    6830             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6831             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6832             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    6833             :         // MIs[1] Operand 0
    6834             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6835             :         // MIs[1] Operand 1
    6836             :         // No operand predicates
    6837             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6838             :         // (intrinsic_wo_chain:{ *:[v2i32] } 292:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (SQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6839             :         // Rule ID 1624
    6840             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv2i32_shift,
    6841             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6842             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6843             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6844             :         GIR_EraseFromParent, /*InsnID*/0,
    6845             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6846             :         GIR_Done,
    6847             :       // Label 225: @14486
    6848             :       GIM_Try, /*On fail goto*//*Label 226*/ 14555,
    6849             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6850             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6851             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6852             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6853             :         // No instruction predicates
    6854             :         // MIs[0] Rd
    6855             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6856             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6857             :         // MIs[0] Operand 1
    6858             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun,
    6859             :         // MIs[0] Rn
    6860             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6861             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6862             :         // MIs[0] imm
    6863             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6864             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6865             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6866             :         // MIs[1] Operand 0
    6867             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6868             :         // MIs[1] Operand 1
    6869             :         // No operand predicates
    6870             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6871             :         // (intrinsic_wo_chain:{ *:[v8i8] } 293:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (SQRSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6872             :         // Rule ID 1625
    6873             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i8_shift,
    6874             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6875             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6876             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6877             :         GIR_EraseFromParent, /*InsnID*/0,
    6878             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6879             :         GIR_Done,
    6880             :       // Label 226: @14555
    6881             :       GIM_Try, /*On fail goto*//*Label 227*/ 14624,
    6882             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6883             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6884             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6885             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6886             :         // No instruction predicates
    6887             :         // MIs[0] Rd
    6888             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6889             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6890             :         // MIs[0] Operand 1
    6891             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun,
    6892             :         // MIs[0] Rn
    6893             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6894             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6895             :         // MIs[0] imm
    6896             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6897             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6898             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6899             :         // MIs[1] Operand 0
    6900             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6901             :         // MIs[1] Operand 1
    6902             :         // No operand predicates
    6903             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6904             :         // (intrinsic_wo_chain:{ *:[v4i16] } 293:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (SQRSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6905             :         // Rule ID 1626
    6906             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i16_shift,
    6907             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6908             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6909             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6910             :         GIR_EraseFromParent, /*InsnID*/0,
    6911             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6912             :         GIR_Done,
    6913             :       // Label 227: @14624
    6914             :       GIM_Try, /*On fail goto*//*Label 228*/ 14693,
    6915             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6916             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6917             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6918             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6919             :         // No instruction predicates
    6920             :         // MIs[0] Rd
    6921             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6922             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6923             :         // MIs[0] Operand 1
    6924             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun,
    6925             :         // MIs[0] Rn
    6926             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6927             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6928             :         // MIs[0] imm
    6929             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6930             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6931             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    6932             :         // MIs[1] Operand 0
    6933             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6934             :         // MIs[1] Operand 1
    6935             :         // No operand predicates
    6936             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6937             :         // (intrinsic_wo_chain:{ *:[v2i32] } 293:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (SQRSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6938             :         // Rule ID 1627
    6939             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv2i32_shift,
    6940             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6941             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6942             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6943             :         GIR_EraseFromParent, /*InsnID*/0,
    6944             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6945             :         GIR_Done,
    6946             :       // Label 228: @14693
    6947             :       GIM_Try, /*On fail goto*//*Label 229*/ 14762,
    6948             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6949             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6950             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6951             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6952             :         // No instruction predicates
    6953             :         // MIs[0] Rd
    6954             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6955             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6956             :         // MIs[0] Operand 1
    6957             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn,
    6958             :         // MIs[0] Rn
    6959             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6960             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6961             :         // MIs[0] imm
    6962             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6963             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6964             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6965             :         // MIs[1] Operand 0
    6966             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6967             :         // MIs[1] Operand 1
    6968             :         // No operand predicates
    6969             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6970             :         // (intrinsic_wo_chain:{ *:[v8i8] } 296:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (SQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6971             :         // Rule ID 1642
    6972             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i8_shift,
    6973             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6974             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6975             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6976             :         GIR_EraseFromParent, /*InsnID*/0,
    6977             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6978             :         GIR_Done,
    6979             :       // Label 229: @14762
    6980             :       GIM_Try, /*On fail goto*//*Label 230*/ 14831,
    6981             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6982             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6983             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6984             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6985             :         // No instruction predicates
    6986             :         // MIs[0] Rd
    6987             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6988             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6989             :         // MIs[0] Operand 1
    6990             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn,
    6991             :         // MIs[0] Rn
    6992             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6993             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6994             :         // MIs[0] imm
    6995             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6996             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6997             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6998             :         // MIs[1] Operand 0
    6999             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7000             :         // MIs[1] Operand 1
    7001             :         // No operand predicates
    7002             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7003             :         // (intrinsic_wo_chain:{ *:[v4i16] } 296:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (SQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7004             :         // Rule ID 1643
    7005             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i16_shift,
    7006             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7007             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7008             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7009             :         GIR_EraseFromParent, /*InsnID*/0,
    7010             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7011             :         GIR_Done,
    7012             :       // Label 230: @14831
    7013             :       GIM_Try, /*On fail goto*//*Label 231*/ 14900,
    7014             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7015             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7016             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7017             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7018             :         // No instruction predicates
    7019             :         // MIs[0] Rd
    7020             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7021             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7022             :         // MIs[0] Operand 1
    7023             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn,
    7024             :         // MIs[0] Rn
    7025             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7026             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7027             :         // MIs[0] imm
    7028             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7029             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7030             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    7031             :         // MIs[1] Operand 0
    7032             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7033             :         // MIs[1] Operand 1
    7034             :         // No operand predicates
    7035             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7036             :         // (intrinsic_wo_chain:{ *:[v2i32] } 296:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (SQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    7037             :         // Rule ID 1644
    7038             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv2i32_shift,
    7039             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7040             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7041             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7042             :         GIR_EraseFromParent, /*InsnID*/0,
    7043             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7044             :         GIR_Done,
    7045             :       // Label 231: @14900
    7046             :       GIM_Try, /*On fail goto*//*Label 232*/ 14969,
    7047             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7048             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7049             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7050             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7051             :         // No instruction predicates
    7052             :         // MIs[0] Rd
    7053             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7054             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7055             :         // MIs[0] Operand 1
    7056             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun,
    7057             :         // MIs[0] Rn
    7058             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7059             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7060             :         // MIs[0] imm
    7061             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7062             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7063             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    7064             :         // MIs[1] Operand 0
    7065             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7066             :         // MIs[1] Operand 1
    7067             :         // No operand predicates
    7068             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7069             :         // (intrinsic_wo_chain:{ *:[v8i8] } 297:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (SQSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7070             :         // Rule ID 1645
    7071             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i8_shift,
    7072             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7073             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7074             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7075             :         GIR_EraseFromParent, /*InsnID*/0,
    7076             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7077             :         GIR_Done,
    7078             :       // Label 232: @14969
    7079             :       GIM_Try, /*On fail goto*//*Label 233*/ 15038,
    7080             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7081             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7082             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7083             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7084             :         // No instruction predicates
    7085             :         // MIs[0] Rd
    7086             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7087             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7088             :         // MIs[0] Operand 1
    7089             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun,
    7090             :         // MIs[0] Rn
    7091             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7092             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7093             :         // MIs[0] imm
    7094             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7095             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7096             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    7097             :         // MIs[1] Operand 0
    7098             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7099             :         // MIs[1] Operand 1
    7100             :         // No operand predicates
    7101             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7102             :         // (intrinsic_wo_chain:{ *:[v4i16] } 297:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (SQSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7103             :         // Rule ID 1646
    7104             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i16_shift,
    7105             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7106             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7107             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7108             :         GIR_EraseFromParent, /*InsnID*/0,
    7109             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7110             :         GIR_Done,
    7111             :       // Label 233: @15038
    7112             :       GIM_Try, /*On fail goto*//*Label 234*/ 15107,
    7113             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7114             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7115             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7116             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7117             :         // No instruction predicates
    7118             :         // MIs[0] Rd
    7119             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7120             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7121             :         // MIs[0] Operand 1
    7122             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun,
    7123             :         // MIs[0] Rn
    7124             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7125             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7126             :         // MIs[0] imm
    7127             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7128             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7129             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    7130             :         // MIs[1] Operand 0
    7131             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7132             :         // MIs[1] Operand 1
    7133             :         // No operand predicates
    7134             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7135             :         // (intrinsic_wo_chain:{ *:[v2i32] } 297:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (SQSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    7136             :         // Rule ID 1647
    7137             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv2i32_shift,
    7138             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7139             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7140             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7141             :         GIR_EraseFromParent, /*InsnID*/0,
    7142             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7143             :         GIR_Done,
    7144             :       // Label 234: @15107
    7145             :       GIM_Try, /*On fail goto*//*Label 235*/ 15176,
    7146             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7147             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7148             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7149             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7150             :         // No instruction predicates
    7151             :         // MIs[0] Rd
    7152             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7153             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7154             :         // MIs[0] Operand 1
    7155             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn,
    7156             :         // MIs[0] Rn
    7157             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7158             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7159             :         // MIs[0] imm
    7160             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7161             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7162             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    7163             :         // MIs[1] Operand 0
    7164             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7165             :         // MIs[1] Operand 1
    7166             :         // No operand predicates
    7167             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7168             :         // (intrinsic_wo_chain:{ *:[v8i8] } 340:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (UQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7169             :         // Rule ID 1694
    7170             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i8_shift,
    7171             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7172             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7173             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7174             :         GIR_EraseFromParent, /*InsnID*/0,
    7175             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7176             :         GIR_Done,
    7177             :       // Label 235: @15176
    7178             :       GIM_Try, /*On fail goto*//*Label 236*/ 15245,
    7179             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7180             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7181             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7182             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7183             :         // No instruction predicates
    7184             :         // MIs[0] Rd
    7185             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7186             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7187             :         // MIs[0] Operand 1
    7188             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn,
    7189             :         // MIs[0] Rn
    7190             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7191             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7192             :         // MIs[0] imm
    7193             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7194             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7195             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    7196             :         // MIs[1] Operand 0
    7197             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7198             :         // MIs[1] Operand 1
    7199             :         // No operand predicates
    7200             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7201             :         // (intrinsic_wo_chain:{ *:[v4i16] } 340:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (UQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7202             :         // Rule ID 1695
    7203             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i16_shift,
    7204             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7205             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7206             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7207             :         GIR_EraseFromParent, /*InsnID*/0,
    7208             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7209             :         GIR_Done,
    7210             :       // Label 236: @15245
    7211             :       GIM_Try, /*On fail goto*//*Label 237*/ 15314,
    7212             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7213             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7214             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7215             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7216             :         // No instruction predicates
    7217             :         // MIs[0] Rd
    7218             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7219             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7220             :         // MIs[0] Operand 1
    7221             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn,
    7222             :         // MIs[0] Rn
    7223             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7224             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7225             :         // MIs[0] imm
    7226             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7227             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7228             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    7229             :         // MIs[1] Operand 0
    7230             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7231             :         // MIs[1] Operand 1
    7232             :         // No operand predicates
    7233             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7234             :         // (intrinsic_wo_chain:{ *:[v2i32] } 340:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (UQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    7235             :         // Rule ID 1696
    7236             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv2i32_shift,
    7237             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7238             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7239             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7240             :         GIR_EraseFromParent, /*InsnID*/0,
    7241             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7242             :         GIR_Done,
    7243             :       // Label 237: @15314
    7244             :       GIM_Try, /*On fail goto*//*Label 238*/ 15383,
    7245             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7246             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7247             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7248             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7249             :         // No instruction predicates
    7250             :         // MIs[0] Rd
    7251             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7252             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7253             :         // MIs[0] Operand 1
    7254             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn,
    7255             :         // MIs[0] Rn
    7256             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7257             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7258             :         // MIs[0] imm
    7259             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7260             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7261             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    7262             :         // MIs[1] Operand 0
    7263             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7264             :         // MIs[1] Operand 1
    7265             :         // No operand predicates
    7266             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7267             :         // (intrinsic_wo_chain:{ *:[v8i8] } 342:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (UQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7268             :         // Rule ID 1704
    7269             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i8_shift,
    7270             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7271             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7272             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7273             :         GIR_EraseFromParent, /*InsnID*/0,
    7274             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7275             :         GIR_Done,
    7276             :       // Label 238: @15383
    7277             :       GIM_Try, /*On fail goto*//*Label 239*/ 15452,
    7278             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7279             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7280             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7281             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7282             :         // No instruction predicates
    7283             :         // MIs[0] Rd
    7284             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7285             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7286             :         // MIs[0] Operand 1
    7287             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn,
    7288             :         // MIs[0] Rn
    7289             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7290             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7291             :         // MIs[0] imm
    7292             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7293             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7294             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    7295             :         // MIs[1] Operand 0
    7296             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7297             :         // MIs[1] Operand 1
    7298             :         // No operand predicates
    7299             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7300             :         // (intrinsic_wo_chain:{ *:[v4i16] } 342:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (UQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7301             :         // Rule ID 1705
    7302             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i16_shift,
    7303             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7304             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7305             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7306             :         GIR_EraseFromParent, /*InsnID*/0,
    7307             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7308             :         GIR_Done,
    7309             :       // Label 239: @15452
    7310             :       GIM_Try, /*On fail goto*//*Label 240*/ 15521,
    7311             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7312             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7313             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7314             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7315             :         // No instruction predicates
    7316             :         // MIs[0] Rd
    7317             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7318             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7319             :         // MIs[0] Operand 1
    7320             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn,
    7321             :         // MIs[0] Rn
    7322             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7323             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7324             :         // MIs[0] imm
    7325             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7326             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7327             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    7328             :         // MIs[1] Operand 0
    7329             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7330             :         // MIs[1] Operand 1
    7331             :         // No operand predicates
    7332             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7333             :         // (intrinsic_wo_chain:{ *:[v2i32] } 342:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (UQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    7334             :         // Rule ID 1706
    7335             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv2i32_shift,
    7336             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7337             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7338             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7339             :         GIR_EraseFromParent, /*InsnID*/0,
    7340             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7341             :         GIR_Done,
    7342             :       // Label 240: @15521
    7343             :       GIM_Try, /*On fail goto*//*Label 241*/ 15588,
    7344             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7345             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7346             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7347             :         // No instruction predicates
    7348             :         // MIs[0] Rd
    7349             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7350             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    7351             :         // MIs[0] Operand 1
    7352             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7353             :         // MIs[0] Rn
    7354             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7355             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    7356             :         // MIs[0] imm
    7357             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7358             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7359             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    7360             :         // MIs[1] Operand 0
    7361             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7362             :         // MIs[1] Operand 1
    7363             :         // No operand predicates
    7364             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7365             :         // (intrinsic_wo_chain:{ *:[i32] } 353:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
    7366             :         // Rule ID 2930
    7367             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSs,
    7368             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7369             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7370             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7371             :         GIR_EraseFromParent, /*InsnID*/0,
    7372             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7373             :         GIR_Done,
    7374             :       // Label 241: @15588
    7375             :       GIM_Try, /*On fail goto*//*Label 242*/ 15655,
    7376             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7377             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7378             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7379             :         // No instruction predicates
    7380             :         // MIs[0] Rd
    7381             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7382             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    7383             :         // MIs[0] Operand 1
    7384             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7385             :         // MIs[0] Rn
    7386             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7387             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    7388             :         // MIs[0] imm
    7389             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7390             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7391             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    7392             :         // MIs[1] Operand 0
    7393             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7394             :         // MIs[1] Operand 1
    7395             :         // No operand predicates
    7396             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7397             :         // (intrinsic_wo_chain:{ *:[i32] } 354:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
    7398             :         // Rule ID 2931
    7399             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUs,
    7400             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7401             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7402             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7403             :         GIR_EraseFromParent, /*InsnID*/0,
    7404             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7405             :         GIR_Done,
    7406             :       // Label 242: @15655
    7407             :       GIM_Try, /*On fail goto*//*Label 243*/ 15722,
    7408             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7409             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7410             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7411             :         // No instruction predicates
    7412             :         // MIs[0] Rd
    7413             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7414             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7415             :         // MIs[0] Operand 1
    7416             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7417             :         // MIs[0] Rn
    7418             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7419             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7420             :         // MIs[0] imm
    7421             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7422             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7423             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7424             :         // MIs[1] Operand 0
    7425             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7426             :         // MIs[1] Operand 1
    7427             :         // No operand predicates
    7428             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7429             :         // (intrinsic_wo_chain:{ *:[i64] } 353:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7430             :         // Rule ID 2932
    7431             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd,
    7432             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7433             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7434             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7435             :         GIR_EraseFromParent, /*InsnID*/0,
    7436             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7437             :         GIR_Done,
    7438             :       // Label 243: @15722
    7439             :       GIM_Try, /*On fail goto*//*Label 244*/ 15789,
    7440             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7441             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7442             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7443             :         // No instruction predicates
    7444             :         // MIs[0] Rd
    7445             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7446             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7447             :         // MIs[0] Operand 1
    7448             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7449             :         // MIs[0] Rn
    7450             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7451             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7452             :         // MIs[0] imm
    7453             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7454             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7455             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7456             :         // MIs[1] Operand 0
    7457             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7458             :         // MIs[1] Operand 1
    7459             :         // No operand predicates
    7460             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7461             :         // (intrinsic_wo_chain:{ *:[i64] } 354:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7462             :         // Rule ID 2933
    7463             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd,
    7464             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7465             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7466             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7467             :         GIR_EraseFromParent, /*InsnID*/0,
    7468             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7469             :         GIR_Done,
    7470             :       // Label 244: @15789
    7471             :       GIM_Try, /*On fail goto*//*Label 245*/ 15856,
    7472             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7473             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7474             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7475             :         // No instruction predicates
    7476             :         // MIs[0] Rd
    7477             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7478             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7479             :         // MIs[0] Operand 1
    7480             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7481             :         // MIs[0] Rn
    7482             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7483             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7484             :         // MIs[0] imm
    7485             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7486             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7487             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7488             :         // MIs[1] Operand 0
    7489             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7490             :         // MIs[1] Operand 1
    7491             :         // No operand predicates
    7492             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7493             :         // (intrinsic_wo_chain:{ *:[v1i64] } 353:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7494             :         // Rule ID 2934
    7495             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd,
    7496             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7497             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7498             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7499             :         GIR_EraseFromParent, /*InsnID*/0,
    7500             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7501             :         GIR_Done,
    7502             :       // Label 245: @15856
    7503             :       GIM_Try, /*On fail goto*//*Label 246*/ 15923,
    7504             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7505             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7506             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7507             :         // No instruction predicates
    7508             :         // MIs[0] Rd
    7509             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7510             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7511             :         // MIs[0] Operand 1
    7512             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7513             :         // MIs[0] Rn
    7514             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7515             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7516             :         // MIs[0] imm
    7517             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7518             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7519             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7520             :         // MIs[1] Operand 0
    7521             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7522             :         // MIs[1] Operand 1
    7523             :         // No operand predicates
    7524             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7525             :         // (intrinsic_wo_chain:{ *:[v1i64] } 354:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7526             :         // Rule ID 2935
    7527             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd,
    7528             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7529             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7530             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7531             :         GIR_EraseFromParent, /*InsnID*/0,
    7532             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7533             :         GIR_Done,
    7534             :       // Label 246: @15923
    7535             :       GIM_Try, /*On fail goto*//*Label 247*/ 15990,
    7536             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7537             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7538             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7539             :         // No instruction predicates
    7540             :         // MIs[0] Rd
    7541             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7542             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    7543             :         // MIs[0] Operand 1
    7544             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    7545             :         // MIs[0] Rn
    7546             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7547             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    7548             :         // MIs[0] imm
    7549             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7550             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7551             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    7552             :         // MIs[1] Operand 0
    7553             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7554             :         // MIs[1] Operand 1
    7555             :         // No operand predicates
    7556             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7557             :         // (intrinsic_wo_chain:{ *:[f32] } 356:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
    7558             :         // Rule ID 2936
    7559             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFs,
    7560             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7561             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7562             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7563             :         GIR_EraseFromParent, /*InsnID*/0,
    7564             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7565             :         GIR_Done,
    7566             :       // Label 247: @15990
    7567             :       GIM_Try, /*On fail goto*//*Label 248*/ 16057,
    7568             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7569             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7570             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7571             :         // No instruction predicates
    7572             :         // MIs[0] Rd
    7573             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7574             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    7575             :         // MIs[0] Operand 1
    7576             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    7577             :         // MIs[0] Rn
    7578             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7579             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    7580             :         // MIs[0] imm
    7581             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7582             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7583             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    7584             :         // MIs[1] Operand 0
    7585             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7586             :         // MIs[1] Operand 1
    7587             :         // No operand predicates
    7588             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7589             :         // (intrinsic_wo_chain:{ *:[f32] } 357:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
    7590             :         // Rule ID 2937
    7591             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFs,
    7592             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7593             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7594             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7595             :         GIR_EraseFromParent, /*InsnID*/0,
    7596             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7597             :         GIR_Done,
    7598             :       // Label 248: @16057
    7599             :       GIM_Try, /*On fail goto*//*Label 249*/ 16124,
    7600             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7601             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7602             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7603             :         // No instruction predicates
    7604             :         // MIs[0] Rd
    7605             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7606             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7607             :         // MIs[0] Operand 1
    7608             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    7609             :         // MIs[0] Rn
    7610             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7611             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7612             :         // MIs[0] imm
    7613             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7614             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7615             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7616             :         // MIs[1] Operand 0
    7617             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7618             :         // MIs[1] Operand 1
    7619             :         // No operand predicates
    7620             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7621             :         // (intrinsic_wo_chain:{ *:[f64] } 356:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7622             :         // Rule ID 2938
    7623             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd,
    7624             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7625             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7626             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7627             :         GIR_EraseFromParent, /*InsnID*/0,
    7628             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7629             :         GIR_Done,
    7630             :       // Label 249: @16124
    7631             :       GIM_Try, /*On fail goto*//*Label 250*/ 16191,
    7632             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7633             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7634             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7635             :         // No instruction predicates
    7636             :         // MIs[0] Rd
    7637             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7638             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7639             :         // MIs[0] Operand 1
    7640             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    7641             :         // MIs[0] Rn
    7642             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7643             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7644             :         // MIs[0] imm
    7645             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7646             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7647             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7648             :         // MIs[1] Operand 0
    7649             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7650             :         // MIs[1] Operand 1
    7651             :         // No operand predicates
    7652             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7653             :         // (intrinsic_wo_chain:{ *:[f64] } 357:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7654             :         // Rule ID 2939
    7655             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd,
    7656             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7657             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7658             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7659             :         GIR_EraseFromParent, /*InsnID*/0,
    7660             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7661             :         GIR_Done,
    7662             :       // Label 250: @16191
    7663             :       GIM_Try, /*On fail goto*//*Label 251*/ 16258,
    7664             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7665             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7666             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7667             :         // No instruction predicates
    7668             :         // MIs[0] Rd
    7669             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7670             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7671             :         // MIs[0] Operand 1
    7672             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    7673             :         // MIs[0] Rn
    7674             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7675             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7676             :         // MIs[0] imm
    7677             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7678             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7679             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7680             :         // MIs[1] Operand 0
    7681             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7682             :         // MIs[1] Operand 1
    7683             :         // No operand predicates
    7684             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7685             :         // (intrinsic_wo_chain:{ *:[v1f64] } 356:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7686             :         // Rule ID 2940
    7687             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd,
    7688             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7689             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7690             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7691             :         GIR_EraseFromParent, /*InsnID*/0,
    7692             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7693             :         GIR_Done,
    7694             :       // Label 251: @16258
    7695             :       GIM_Try, /*On fail goto*//*Label 252*/ 16325,
    7696             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7697             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7698             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7699             :         // No instruction predicates
    7700             :         // MIs[0] Rd
    7701             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7702             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7703             :         // MIs[0] Operand 1
    7704             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    7705             :         // MIs[0] Rn
    7706             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7707             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7708             :         // MIs[0] imm
    7709             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7710             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7711             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7712             :         // MIs[1] Operand 0
    7713             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7714             :         // MIs[1] Operand 1
    7715             :         // No operand predicates
    7716             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7717             :         // (intrinsic_wo_chain:{ *:[v1f64] } 357:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7718             :         // Rule ID 2941
    7719             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd,
    7720             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7721             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7722             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7723             :         GIR_EraseFromParent, /*InsnID*/0,
    7724             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7725             :         GIR_Done,
    7726             :       // Label 252: @16325
    7727             :       GIM_Reject,
    7728             :       GIR_Done,
    7729             :     // Label 197: @16327
    7730             :     GIM_Try, /*On fail goto*//*Label 253*/ 16432,
    7731             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    7732             :       GIM_Try, /*On fail goto*//*Label 254*/ 16381,
    7733             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    7734             :         // No instruction predicates
    7735             :         // MIs[0] Rd
    7736             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7737             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    7738             :         // MIs[0] Rn
    7739             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7740             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
    7741             :         // MIs[0] imm
    7742             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7743             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
    7744             :         // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
    7745             :         // Rule ID 1972
    7746             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
    7747             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7748             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    7749             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    7750             :         GIR_EraseFromParent, /*InsnID*/0,
    7751             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7752             :         GIR_Done,
    7753             :       // Label 254: @16381
    7754             :       GIM_Try, /*On fail goto*//*Label 255*/ 16430,
    7755             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    7756             :         // No instruction predicates
    7757             :         // MIs[0] Rd
    7758             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7759             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    7760             :         // MIs[0] Rn
    7761             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    7762             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
    7763             :         // MIs[0] imm
    7764             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7765             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
    7766             :         // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
    7767             :         // Rule ID 1973
    7768             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
    7769             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7770             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    7771             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    7772             :         GIR_EraseFromParent, /*InsnID*/0,
    7773             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7774             :         GIR_Done,
    7775             :       // Label 255: @16430
    7776             :       GIM_Reject,
    7777             :       GIR_Done,
    7778             :     // Label 253: @16432
    7779             :     GIM_Try, /*On fail goto*//*Label 256*/ 16631,
    7780             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS,
    7781             :       GIM_Try, /*On fail goto*//*Label 257*/ 16485,
    7782             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    7783             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    7784             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7785             :         // No instruction predicates
    7786             :         // MIs[0] Operand 0
    7787             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_hint,
    7788             :         // MIs[0] imm
    7789             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7790             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7791             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_127,
    7792             :         // MIs[1] Operand 0
    7793             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7794             :         // MIs[1] Operand 1
    7795             :         // No operand predicates
    7796             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7797             :         // (intrinsic_void 203:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_127>>:$imm)  =>  (HINT (imm:{ *:[i32] }):$imm)
    7798             :         // Rule ID 10
    7799             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HINT,
    7800             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7801             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    7802             :         GIR_EraseFromParent, /*InsnID*/0,
    7803             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7804             :         GIR_Done,
    7805             :       // Label 257: @16485
    7806             :       GIM_Try, /*On fail goto*//*Label 258*/ 16533,
    7807             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    7808             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    7809             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7810             :         // No instruction predicates
    7811             :         // MIs[0] Operand 0
    7812             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dmb,
    7813             :         // MIs[0] CRm
    7814             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7815             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7816             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15,
    7817             :         // MIs[1] Operand 0
    7818             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7819             :         // MIs[1] Operand 1
    7820             :         // No operand predicates
    7821             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7822             :         // (intrinsic_void 201:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (DMB (imm:{ *:[i32] }):$CRm)
    7823             :         // Rule ID 11
    7824             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB,
    7825             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
    7826             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    7827             :         GIR_EraseFromParent, /*InsnID*/0,
    7828             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7829             :         GIR_Done,
    7830             :       // Label 258: @16533
    7831             :       GIM_Try, /*On fail goto*//*Label 259*/ 16581,
    7832             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    7833             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    7834             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7835             :         // No instruction predicates
    7836             :         // MIs[0] Operand 0
    7837             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dsb,
    7838             :         // MIs[0] CRm
    7839             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7840             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7841             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15,
    7842             :         // MIs[1] Operand 0
    7843             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7844             :         // MIs[1] Operand 1
    7845             :         // No operand predicates
    7846             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7847             :         // (intrinsic_void 202:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (DSB (imm:{ *:[i32] }):$CRm)
    7848             :         // Rule ID 12
    7849             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DSB,
    7850             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
    7851             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    7852             :         GIR_EraseFromParent, /*InsnID*/0,
    7853             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7854             :         GIR_Done,
    7855             :       // Label 259: @16581
    7856             :       GIM_Try, /*On fail goto*//*Label 260*/ 16629,
    7857             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    7858             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    7859             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7860             :         // No instruction predicates
    7861             :         // MIs[0] Operand 0
    7862             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_isb,
    7863             :         // MIs[0] CRm
    7864             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7865             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7866             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15,
    7867             :         // MIs[1] Operand 0
    7868             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7869             :         // MIs[1] Operand 1
    7870             :         // No operand predicates
    7871             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7872             :         // (intrinsic_void 204:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (ISB (imm:{ *:[i32] }):$CRm)
    7873             :         // Rule ID 13
    7874             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ISB,
    7875             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
    7876             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    7877             :         GIR_EraseFromParent, /*InsnID*/0,
    7878             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7879             :         GIR_Done,
    7880             :       // Label 260: @16629
    7881             :       GIM_Reject,
    7882             :       GIR_Done,
    7883             :     // Label 256: @16631
    7884             :     GIM_Try, /*On fail goto*//*Label 261*/ 17958,
    7885             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7886             :       GIM_Try, /*On fail goto*//*Label 262*/ 16702,
    7887             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    7888             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7889             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7890             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7891             :         // No instruction predicates
    7892             :         // MIs[0] Rd
    7893             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7894             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7895             :         // MIs[0] Operand 1
    7896             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7897             :         // MIs[0] Rn
    7898             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7899             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7900             :         // MIs[0] imm
    7901             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7902             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7903             :         // MIs[1] Operand 0
    7904             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7905             :         // MIs[1] Operand 1
    7906             :         // No operand predicates
    7907             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7908             :         // (intrinsic_wo_chain:{ *:[v4i16] } 353:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7909             :         // Rule ID 1587
    7910             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i16_shift,
    7911             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7912             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7913             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7914             :         GIR_EraseFromParent, /*InsnID*/0,
    7915             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7916             :         GIR_Done,
    7917             :       // Label 262: @16702
    7918             :       GIM_Try, /*On fail goto*//*Label 263*/ 16768,
    7919             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    7920             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7921             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7922             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7923             :         // No instruction predicates
    7924             :         // MIs[0] Rd
    7925             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7926             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    7927             :         // MIs[0] Operand 1
    7928             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7929             :         // MIs[0] Rn
    7930             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7931             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7932             :         // MIs[0] imm
    7933             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7934             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7935             :         // MIs[1] Operand 0
    7936             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7937             :         // MIs[1] Operand 1
    7938             :         // No operand predicates
    7939             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7940             :         // (intrinsic_wo_chain:{ *:[v8i16] } 353:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7941             :         // Rule ID 1588
    7942             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv8i16_shift,
    7943             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7944             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7945             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7946             :         GIR_EraseFromParent, /*InsnID*/0,
    7947             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7948             :         GIR_Done,
    7949             :       // Label 263: @16768
    7950             :       GIM_Try, /*On fail goto*//*Label 264*/ 16834,
    7951             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7952             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7953             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7954             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7955             :         // No instruction predicates
    7956             :         // MIs[0] Rd
    7957             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7958             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7959             :         // MIs[0] Operand 1
    7960             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7961             :         // MIs[0] Rn
    7962             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7963             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7964             :         // MIs[0] imm
    7965             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7966             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7967             :         // MIs[1] Operand 0
    7968             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7969             :         // MIs[1] Operand 1
    7970             :         // No operand predicates
    7971             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7972             :         // (intrinsic_wo_chain:{ *:[v2i32] } 353:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7973             :         // Rule ID 1589
    7974             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i32_shift,
    7975             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7976             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7977             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7978             :         GIR_EraseFromParent, /*InsnID*/0,
    7979             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7980             :         GIR_Done,
    7981             :       // Label 264: @16834
    7982             :       GIM_Try, /*On fail goto*//*Label 265*/ 16900,
    7983             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7984             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7985             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7986             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7987             :         // No instruction predicates
    7988             :         // MIs[0] Rd
    7989             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7990             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    7991             :         // MIs[0] Operand 1
    7992             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7993             :         // MIs[0] Rn
    7994             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7995             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7996             :         // MIs[0] imm
    7997             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7998             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7999             :         // MIs[1] Operand 0
    8000             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8001             :         // MIs[1] Operand 1
    8002             :         // No operand predicates
    8003             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8004             :         // (intrinsic_wo_chain:{ *:[v4i32] } 353:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8005             :         // Rule ID 1590
    8006             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i32_shift,
    8007             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8008             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8009             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8010             :         GIR_EraseFromParent, /*InsnID*/0,
    8011             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8012             :         GIR_Done,
    8013             :       // Label 265: @16900
    8014             :       GIM_Try, /*On fail goto*//*Label 266*/ 16966,
    8015             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8016             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8017             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8018             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8019             :         // No instruction predicates
    8020             :         // MIs[0] Rd
    8021             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8022             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8023             :         // MIs[0] Operand 1
    8024             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    8025             :         // MIs[0] Rn
    8026             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8027             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8028             :         // MIs[0] imm
    8029             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8030             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8031             :         // MIs[1] Operand 0
    8032             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8033             :         // MIs[1] Operand 1
    8034             :         // No operand predicates
    8035             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8036             :         // (intrinsic_wo_chain:{ *:[v2i64] } 353:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)
    8037             :         // Rule ID 1591
    8038             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i64_shift,
    8039             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8040             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8041             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8042             :         GIR_EraseFromParent, /*InsnID*/0,
    8043             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8044             :         GIR_Done,
    8045             :       // Label 266: @16966
    8046             :       GIM_Try, /*On fail goto*//*Label 267*/ 17032,
    8047             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8048             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8049             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8050             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8051             :         // No instruction predicates
    8052             :         // MIs[0] Rd
    8053             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8054             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8055             :         // MIs[0] Operand 1
    8056             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    8057             :         // MIs[0] Rn
    8058             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8059             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8060             :         // MIs[0] imm
    8061             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8062             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8063             :         // MIs[1] Operand 0
    8064             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8065             :         // MIs[1] Operand 1
    8066             :         // No operand predicates
    8067             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8068             :         // (intrinsic_wo_chain:{ *:[v4i16] } 354:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8069             :         // Rule ID 1592
    8070             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i16_shift,
    8071             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8072             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8073             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8074             :         GIR_EraseFromParent, /*InsnID*/0,
    8075             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8076             :         GIR_Done,
    8077             :       // Label 267: @17032
    8078             :       GIM_Try, /*On fail goto*//*Label 268*/ 17098,
    8079             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8080             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8081             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8082             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8083             :         // No instruction predicates
    8084             :         // MIs[0] Rd
    8085             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8086             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8087             :         // MIs[0] Operand 1
    8088             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    8089             :         // MIs[0] Rn
    8090             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8091             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8092             :         // MIs[0] imm
    8093             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8094             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8095             :         // MIs[1] Operand 0
    8096             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8097             :         // MIs[1] Operand 1
    8098             :         // No operand predicates
    8099             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8100             :         // (intrinsic_wo_chain:{ *:[v8i16] } 354:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8101             :         // Rule ID 1593
    8102             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv8i16_shift,
    8103             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8104             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8105             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8106             :         GIR_EraseFromParent, /*InsnID*/0,
    8107             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8108             :         GIR_Done,
    8109             :       // Label 268: @17098
    8110             :       GIM_Try, /*On fail goto*//*Label 269*/ 17164,
    8111             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8112             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8113             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8114             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8115             :         // No instruction predicates
    8116             :         // MIs[0] Rd
    8117             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8118             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8119             :         // MIs[0] Operand 1
    8120             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    8121             :         // MIs[0] Rn
    8122             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8123             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8124             :         // MIs[0] imm
    8125             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8126             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8127             :         // MIs[1] Operand 0
    8128             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8129             :         // MIs[1] Operand 1
    8130             :         // No operand predicates
    8131             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8132             :         // (intrinsic_wo_chain:{ *:[v2i32] } 354:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8133             :         // Rule ID 1594
    8134             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i32_shift,
    8135             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8136             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8137             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8138             :         GIR_EraseFromParent, /*InsnID*/0,
    8139             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8140             :         GIR_Done,
    8141             :       // Label 269: @17164
    8142             :       GIM_Try, /*On fail goto*//*Label 270*/ 17230,
    8143             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8144             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8145             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8146             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8147             :         // No instruction predicates
    8148             :         // MIs[0] Rd
    8149             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8150             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8151             :         // MIs[0] Operand 1
    8152             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    8153             :         // MIs[0] Rn
    8154             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8155             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8156             :         // MIs[0] imm
    8157             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8158             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8159             :         // MIs[1] Operand 0
    8160             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8161             :         // MIs[1] Operand 1
    8162             :         // No operand predicates
    8163             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8164             :         // (intrinsic_wo_chain:{ *:[v4i32] } 354:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8165             :         // Rule ID 1595
    8166             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i32_shift,
    8167             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8168             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8169             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8170             :         GIR_EraseFromParent, /*InsnID*/0,
    8171             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8172             :         GIR_Done,
    8173             :       // Label 270: @17230
    8174             :       GIM_Try, /*On fail goto*//*Label 271*/ 17296,
    8175             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8176             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8177             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8178             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8179             :         // No instruction predicates
    8180             :         // MIs[0] Rd
    8181             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8182             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8183             :         // MIs[0] Operand 1
    8184             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    8185             :         // MIs[0] Rn
    8186             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8187             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8188             :         // MIs[0] imm
    8189             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8190             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8191             :         // MIs[1] Operand 0
    8192             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8193             :         // MIs[1] Operand 1
    8194             :         // No operand predicates
    8195             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8196             :         // (intrinsic_wo_chain:{ *:[v2i64] } 354:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)
    8197             :         // Rule ID 1596
    8198             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i64_shift,
    8199             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8200             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8201             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8202             :         GIR_EraseFromParent, /*InsnID*/0,
    8203             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8204             :         GIR_Done,
    8205             :       // Label 271: @17296
    8206             :       GIM_Try, /*On fail goto*//*Label 272*/ 17362,
    8207             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8208             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8209             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8210             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8211             :         // No instruction predicates
    8212             :         // MIs[0] Rd
    8213             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8214             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8215             :         // MIs[0] Operand 1
    8216             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8217             :         // MIs[0] Rn
    8218             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8219             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8220             :         // MIs[0] imm
    8221             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8222             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8223             :         // MIs[1] Operand 0
    8224             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8225             :         // MIs[1] Operand 1
    8226             :         // No operand predicates
    8227             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8228             :         // (intrinsic_wo_chain:{ *:[v4f16] } 356:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8229             :         // Rule ID 1597
    8230             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i16_shift,
    8231             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8232             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8233             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8234             :         GIR_EraseFromParent, /*InsnID*/0,
    8235             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8236             :         GIR_Done,
    8237             :       // Label 272: @17362
    8238             :       GIM_Try, /*On fail goto*//*Label 273*/ 17428,
    8239             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8240             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8241             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8242             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8243             :         // No instruction predicates
    8244             :         // MIs[0] Rd
    8245             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8246             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8247             :         // MIs[0] Operand 1
    8248             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8249             :         // MIs[0] Rn
    8250             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8251             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8252             :         // MIs[0] imm
    8253             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8254             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8255             :         // MIs[1] Operand 0
    8256             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8257             :         // MIs[1] Operand 1
    8258             :         // No operand predicates
    8259             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8260             :         // (intrinsic_wo_chain:{ *:[v8f16] } 356:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8261             :         // Rule ID 1598
    8262             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv8i16_shift,
    8263             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8264             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8265             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8266             :         GIR_EraseFromParent, /*InsnID*/0,
    8267             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8268             :         GIR_Done,
    8269             :       // Label 273: @17428
    8270             :       GIM_Try, /*On fail goto*//*Label 274*/ 17494,
    8271             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8272             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8273             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8274             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8275             :         // No instruction predicates
    8276             :         // MIs[0] Rd
    8277             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8278             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8279             :         // MIs[0] Operand 1
    8280             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8281             :         // MIs[0] Rn
    8282             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8283             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8284             :         // MIs[0] imm
    8285             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8286             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8287             :         // MIs[1] Operand 0
    8288             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8289             :         // MIs[1] Operand 1
    8290             :         // No operand predicates
    8291             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8292             :         // (intrinsic_wo_chain:{ *:[v2f32] } 356:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8293             :         // Rule ID 1599
    8294             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i32_shift,
    8295             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8296             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8297             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8298             :         GIR_EraseFromParent, /*InsnID*/0,
    8299             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8300             :         GIR_Done,
    8301             :       // Label 274: @17494
    8302             :       GIM_Try, /*On fail goto*//*Label 275*/ 17560,
    8303             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8304             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8305             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8306             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8307             :         // No instruction predicates
    8308             :         // MIs[0] Rd
    8309             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8310             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8311             :         // MIs[0] Operand 1
    8312             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8313             :         // MIs[0] Rn
    8314             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8315             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8316             :         // MIs[0] imm
    8317             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8318             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8319             :         // MIs[1] Operand 0
    8320             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8321             :         // MIs[1] Operand 1
    8322             :         // No operand predicates
    8323             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8324             :         // (intrinsic_wo_chain:{ *:[v4f32] } 356:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8325             :         // Rule ID 1600
    8326             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i32_shift,
    8327             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8328             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8329             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8330             :         GIR_EraseFromParent, /*InsnID*/0,
    8331             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8332             :         GIR_Done,
    8333             :       // Label 275: @17560
    8334             :       GIM_Try, /*On fail goto*//*Label 276*/ 17626,
    8335             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8336             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8337             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8338             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8339             :         // No instruction predicates
    8340             :         // MIs[0] Rd
    8341             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8342             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8343             :         // MIs[0] Operand 1
    8344             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8345             :         // MIs[0] Rn
    8346             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8347             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8348             :         // MIs[0] imm
    8349             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8350             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8351             :         // MIs[1] Operand 0
    8352             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8353             :         // MIs[1] Operand 1
    8354             :         // No operand predicates
    8355             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8356             :         // (intrinsic_wo_chain:{ *:[v2f64] } 356:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    8357             :         // Rule ID 1601
    8358             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i64_shift,
    8359             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8360             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8361             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8362             :         GIR_EraseFromParent, /*InsnID*/0,
    8363             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8364             :         GIR_Done,
    8365             :       // Label 276: @17626
    8366             :       GIM_Try, /*On fail goto*//*Label 277*/ 17692,
    8367             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8368             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8369             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8370             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8371             :         // No instruction predicates
    8372             :         // MIs[0] Rd
    8373             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8374             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8375             :         // MIs[0] Operand 1
    8376             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8377             :         // MIs[0] Rn
    8378             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8379             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8380             :         // MIs[0] imm
    8381             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8382             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8383             :         // MIs[1] Operand 0
    8384             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8385             :         // MIs[1] Operand 1
    8386             :         // No operand predicates
    8387             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8388             :         // (intrinsic_wo_chain:{ *:[v4f16] } 357:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8389             :         // Rule ID 1689
    8390             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i16_shift,
    8391             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8392             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8393             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8394             :         GIR_EraseFromParent, /*InsnID*/0,
    8395             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8396             :         GIR_Done,
    8397             :       // Label 277: @17692
    8398             :       GIM_Try, /*On fail goto*//*Label 278*/ 17758,
    8399             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8400             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8401             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8402             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8403             :         // No instruction predicates
    8404             :         // MIs[0] Rd
    8405             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8406             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8407             :         // MIs[0] Operand 1
    8408             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8409             :         // MIs[0] Rn
    8410             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8411             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8412             :         // MIs[0] imm
    8413             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8414             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8415             :         // MIs[1] Operand 0
    8416             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8417             :         // MIs[1] Operand 1
    8418             :         // No operand predicates
    8419             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8420             :         // (intrinsic_wo_chain:{ *:[v8f16] } 357:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8421             :         // Rule ID 1690
    8422             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv8i16_shift,
    8423             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8424             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8425             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8426             :         GIR_EraseFromParent, /*InsnID*/0,
    8427             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8428             :         GIR_Done,
    8429             :       // Label 278: @17758
    8430             :       GIM_Try, /*On fail goto*//*Label 279*/ 17824,
    8431             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8432             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8433             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8434             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8435             :         // No instruction predicates
    8436             :         // MIs[0] Rd
    8437             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8438             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8439             :         // MIs[0] Operand 1
    8440             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8441             :         // MIs[0] Rn
    8442             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8443             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8444             :         // MIs[0] imm
    8445             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8446             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8447             :         // MIs[1] Operand 0
    8448             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8449             :         // MIs[1] Operand 1
    8450             :         // No operand predicates
    8451             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8452             :         // (intrinsic_wo_chain:{ *:[v2f32] } 357:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8453             :         // Rule ID 1691
    8454             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i32_shift,
    8455             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8456             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8457             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8458             :         GIR_EraseFromParent, /*InsnID*/0,
    8459             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8460             :         GIR_Done,
    8461             :       // Label 279: @17824
    8462             :       GIM_Try, /*On fail goto*//*Label 280*/ 17890,
    8463             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8464             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8465             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8466             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8467             :         // No instruction predicates
    8468             :         // MIs[0] Rd
    8469             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8470             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8471             :         // MIs[0] Operand 1
    8472             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8473             :         // MIs[0] Rn
    8474             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8475             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8476             :         // MIs[0] imm
    8477             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8478             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8479             :         // MIs[1] Operand 0
    8480             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8481             :         // MIs[1] Operand 1
    8482             :         // No operand predicates
    8483             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8484             :         // (intrinsic_wo_chain:{ *:[v4f32] } 357:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8485             :         // Rule ID 1692
    8486             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i32_shift,
    8487             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8488             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8489             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8490             :         GIR_EraseFromParent, /*InsnID*/0,
    8491             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8492             :         GIR_Done,
    8493             :       // Label 280: @17890
    8494             :       GIM_Try, /*On fail goto*//*Label 281*/ 17956,
    8495             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8496             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8497             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8498             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8499             :         // No instruction predicates
    8500             :         // MIs[0] Rd
    8501             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8502             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8503             :         // MIs[0] Operand 1
    8504             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8505             :         // MIs[0] Rn
    8506             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8507             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8508             :         // MIs[0] imm
    8509             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8510             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8511             :         // MIs[1] Operand 0
    8512             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8513             :         // MIs[1] Operand 1
    8514             :         // No operand predicates
    8515             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8516             :         // (intrinsic_wo_chain:{ *:[v2f64] } 357:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    8517             :         // Rule ID 1693
    8518             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i64_shift,
    8519             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8520             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8521             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8522             :         GIR_EraseFromParent, /*InsnID*/0,
    8523             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8524             :         GIR_Done,
    8525             :       // Label 281: @17956
    8526             :       GIM_Reject,
    8527             :       GIR_Done,
    8528             :     // Label 261: @17958
    8529             :     GIM_Try, /*On fail goto*//*Label 282*/ 22897,
    8530             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
    8531             :       GIM_Try, /*On fail goto*//*Label 283*/ 18050,
    8532             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8533             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8534             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8535             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8536             :         // No instruction predicates
    8537             :         // MIs[0] dst
    8538             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8539             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8540             :         // MIs[0] Operand 1
    8541             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
    8542             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8543             :         // MIs[1] Operand 0
    8544             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s8,
    8545             :         // MIs[1] Operand 1
    8546             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8547             :         // MIs[1] Rn
    8548             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    8549             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8550             :         // MIs[1] Rm
    8551             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    8552             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8553             :         // MIs[0] Rd
    8554             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8555             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8556             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8557             :         // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 266:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    8558             :         // Rule ID 3844
    8559             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
    8560             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8561             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8562             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8563             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8564             :         GIR_EraseFromParent, /*InsnID*/0,
    8565             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8566             :         GIR_Done,
    8567             :       // Label 283: @18050
    8568             :       GIM_Try, /*On fail goto*//*Label 284*/ 18137,
    8569             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8570             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8571             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8572             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8573             :         // No instruction predicates
    8574             :         // MIs[0] dst
    8575             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    8576             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8577             :         // MIs[0] Operand 1
    8578             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
    8579             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8580             :         // MIs[1] Operand 0
    8581             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    8582             :         // MIs[1] Operand 1
    8583             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8584             :         // MIs[1] Rn
    8585             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    8586             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8587             :         // MIs[1] Rm
    8588             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    8589             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8590             :         // MIs[0] Rd
    8591             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    8592             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8593             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8594             :         // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 266:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
    8595             :         // Rule ID 3845
    8596             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
    8597             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8598             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8599             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8600             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8601             :         GIR_EraseFromParent, /*InsnID*/0,
    8602             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8603             :         GIR_Done,
    8604             :       // Label 284: @18137
    8605             :       GIM_Try, /*On fail goto*//*Label 285*/ 18224,
    8606             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8607             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8608             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8609             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8610             :         // No instruction predicates
    8611             :         // MIs[0] dst
    8612             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8613             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8614             :         // MIs[0] Operand 1
    8615             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    8616             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8617             :         // MIs[1] Operand 0
    8618             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    8619             :         // MIs[1] Operand 1
    8620             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8621             :         // MIs[1] Rn
    8622             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    8623             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8624             :         // MIs[1] Rm
    8625             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    8626             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8627             :         // MIs[0] Rd
    8628             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8629             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8630             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8631             :         // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 266:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    8632             :         // Rule ID 3846
    8633             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
    8634             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8635             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8636             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8637             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8638             :         GIR_EraseFromParent, /*InsnID*/0,
    8639             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8640             :         GIR_Done,
    8641             :       // Label 285: @18224
    8642             :       GIM_Try, /*On fail goto*//*Label 286*/ 18311,
    8643             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8644             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8645             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8646             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8647             :         // No instruction predicates
    8648             :         // MIs[0] dst
    8649             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8650             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8651             :         // MIs[0] Operand 1
    8652             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    8653             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8654             :         // MIs[1] Operand 0
    8655             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    8656             :         // MIs[1] Operand 1
    8657             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8658             :         // MIs[1] Rn
    8659             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    8660             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8661             :         // MIs[1] Rm
    8662             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    8663             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8664             :         // MIs[0] Rd
    8665             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8666             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8667             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8668             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 266:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
    8669             :         // Rule ID 3847
    8670             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
    8671             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8672             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8673             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8674             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8675             :         GIR_EraseFromParent, /*InsnID*/0,
    8676             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8677             :         GIR_Done,
    8678             :       // Label 286: @18311
    8679             :       GIM_Try, /*On fail goto*//*Label 287*/ 18398,
    8680             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8681             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8682             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8683             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8684             :         // No instruction predicates
    8685             :         // MIs[0] dst
    8686             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8687             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8688             :         // MIs[0] Operand 1
    8689             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    8690             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8691             :         // MIs[1] Operand 0
    8692             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    8693             :         // MIs[1] Operand 1
    8694             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8695             :         // MIs[1] Rn
    8696             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    8697             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8698             :         // MIs[1] Rm
    8699             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    8700             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8701             :         // MIs[0] Rd
    8702             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8703             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8704             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8705             :         // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 266:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    8706             :         // Rule ID 3848
    8707             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
    8708             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8709             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8710             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8711             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8712             :         GIR_EraseFromParent, /*InsnID*/0,
    8713             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8714             :         GIR_Done,
    8715             :       // Label 287: @18398
    8716             :       GIM_Try, /*On fail goto*//*Label 288*/ 18485,
    8717             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8718             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8719             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8720             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8721             :         // No instruction predicates
    8722             :         // MIs[0] dst
    8723             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8724             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8725             :         // MIs[0] Operand 1
    8726             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    8727             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8728             :         // MIs[1] Operand 0
    8729             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    8730             :         // MIs[1] Operand 1
    8731             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8732             :         // MIs[1] Rn
    8733             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    8734             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8735             :         // MIs[1] Rm
    8736             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    8737             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8738             :         // MIs[0] Rd
    8739             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8740             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8741             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8742             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 266:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
    8743             :         // Rule ID 3849
    8744             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
    8745             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8746             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8747             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8748             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8749             :         GIR_EraseFromParent, /*InsnID*/0,
    8750             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8751             :         GIR_Done,
    8752             :       // Label 288: @18485
    8753             :       GIM_Try, /*On fail goto*//*Label 289*/ 18572,
    8754             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8755             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8756             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8757             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8758             :         // No instruction predicates
    8759             :         // MIs[0] dst
    8760             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8761             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8762             :         // MIs[0] Operand 1
    8763             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
    8764             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8765             :         // MIs[1] Operand 0
    8766             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s8,
    8767             :         // MIs[1] Operand 1
    8768             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8769             :         // MIs[1] Rn
    8770             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    8771             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8772             :         // MIs[1] Rm
    8773             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    8774             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8775             :         // MIs[0] Rd
    8776             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8777             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8778             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8779             :         // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 324:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    8780             :         // Rule ID 3850
    8781             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
    8782             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8783             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8784             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8785             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8786             :         GIR_EraseFromParent, /*InsnID*/0,
    8787             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8788             :         GIR_Done,
    8789             :       // Label 289: @18572
    8790             :       GIM_Try, /*On fail goto*//*Label 290*/ 18659,
    8791             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8792             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8793             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8794             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8795             :         // No instruction predicates
    8796             :         // MIs[0] dst
    8797             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    8798             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8799             :         // MIs[0] Operand 1
    8800             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
    8801             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8802             :         // MIs[1] Operand 0
    8803             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    8804             :         // MIs[1] Operand 1
    8805             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8806             :         // MIs[1] Rn
    8807             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    8808             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8809             :         // MIs[1] Rm
    8810             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    8811             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8812             :         // MIs[0] Rd
    8813             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    8814             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8815             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8816             :         // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 324:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
    8817             :         // Rule ID 3851
    8818             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
    8819             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8820             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8821             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8822             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8823             :         GIR_EraseFromParent, /*InsnID*/0,
    8824             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8825             :         GIR_Done,
    8826             :       // Label 290: @18659
    8827             :       GIM_Try, /*On fail goto*//*Label 291*/ 18746,
    8828             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8829             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8830             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8831             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8832             :         // No instruction predicates
    8833             :         // MIs[0] dst
    8834             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8835             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8836             :         // MIs[0] Operand 1
    8837             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    8838             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8839             :         // MIs[1] Operand 0
    8840             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    8841             :         // MIs[1] Operand 1
    8842             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8843             :         // MIs[1] Rn
    8844             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    8845             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8846             :         // MIs[1] Rm
    8847             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    8848             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8849             :         // MIs[0] Rd
    8850             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8851             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8852             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8853             :         // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 324:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    8854             :         // Rule ID 3852
    8855             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
    8856             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8857             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8858             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8859             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8860             :         GIR_EraseFromParent, /*InsnID*/0,
    8861             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8862             :         GIR_Done,
    8863             :       // Label 291: @18746
    8864             :       GIM_Try, /*On fail goto*//*Label 292*/ 18833,
    8865             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8866             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8867             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8868             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8869             :         // No instruction predicates
    8870             :         // MIs[0] dst
    8871             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8872             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8873             :         // MIs[0] Operand 1
    8874             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    8875             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8876             :         // MIs[1] Operand 0
    8877             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    8878             :         // MIs[1] Operand 1
    8879             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8880             :         // MIs[1] Rn
    8881             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    8882             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8883             :         // MIs[1] Rm
    8884             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    8885             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8886             :         // MIs[0] Rd
    8887             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8888             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8889             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8890             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 324:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
    8891             :         // Rule ID 3853
    8892             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
    8893             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8894             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8895             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8896             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8897             :         GIR_EraseFromParent, /*InsnID*/0,
    8898             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8899             :         GIR_Done,
    8900             :       // Label 292: @18833
    8901             :       GIM_Try, /*On fail goto*//*Label 293*/ 18920,
    8902             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8903             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8904             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8905             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8906             :         // No instruction predicates
    8907             :         // MIs[0] dst
    8908             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8909             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8910             :         // MIs[0] Operand 1
    8911             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    8912             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8913             :         // MIs[1] Operand 0
    8914             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    8915             :         // MIs[1] Operand 1
    8916             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8917             :         // MIs[1] Rn
    8918             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    8919             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8920             :         // MIs[1] Rm
    8921             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    8922             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8923             :         // MIs[0] Rd
    8924             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8925             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8926             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8927             :         // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 324:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    8928             :         // Rule ID 3854
    8929             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
    8930             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8931             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8932             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8933             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8934             :         GIR_EraseFromParent, /*InsnID*/0,
    8935             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8936             :         GIR_Done,
    8937             :       // Label 293: @18920
    8938             :       GIM_Try, /*On fail goto*//*Label 294*/ 19007,
    8939             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8940             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8941             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8942             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8943             :         // No instruction predicates
    8944             :         // MIs[0] dst
    8945             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8946             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8947             :         // MIs[0] Operand 1
    8948             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    8949             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8950             :         // MIs[1] Operand 0
    8951             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    8952             :         // MIs[1] Operand 1
    8953             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8954             :         // MIs[1] Rn
    8955             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    8956             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8957             :         // MIs[1] Rm
    8958             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    8959             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8960             :         // MIs[0] Rd
    8961             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8962             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8963             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8964             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 324:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
    8965             :         // Rule ID 3855
    8966             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
    8967             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8968             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8969             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8970             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8971             :         GIR_EraseFromParent, /*InsnID*/0,
    8972             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8973             :         GIR_Done,
    8974             :       // Label 294: @19007
    8975             :       GIM_Try, /*On fail goto*//*Label 295*/ 19094,
    8976             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8977             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8978             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8979             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8980             :         // No instruction predicates
    8981             :         // MIs[0] dst
    8982             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8983             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8984             :         // MIs[0] Operand 1
    8985             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    8986             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8987             :         // MIs[1] Operand 0
    8988             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    8989             :         // MIs[1] Operand 1
    8990             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
    8991             :         // MIs[1] Rn
    8992             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    8993             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8994             :         // MIs[1] Rm
    8995             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    8996             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8997             :         // MIs[0] Rd
    8998             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8999             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9000             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9001             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 283:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    9002             :         // Rule ID 3910
    9003             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
    9004             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9005             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9006             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9007             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    9008             :         GIR_EraseFromParent, /*InsnID*/0,
    9009             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9010             :         GIR_Done,
    9011             :       // Label 295: @19094
    9012             :       GIM_Try, /*On fail goto*//*Label 296*/ 19181,
    9013             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9014             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9015             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9016             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    9017             :         // No instruction predicates
    9018             :         // MIs[0] dst
    9019             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9020             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9021             :         // MIs[0] Operand 1
    9022             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    9023             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9024             :         // MIs[1] Operand 0
    9025             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    9026             :         // MIs[1] Operand 1
    9027             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
    9028             :         // MIs[1] Rn
    9029             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    9030             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9031             :         // MIs[1] Rm
    9032             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    9033             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    9034             :         // MIs[0] Rd
    9035             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9036             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9037             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9038             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 283:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    9039             :         // Rule ID 3912
    9040             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
    9041             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9042             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9043             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9044             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    9045             :         GIR_EraseFromParent, /*InsnID*/0,
    9046             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9047             :         GIR_Done,
    9048             :       // Label 296: @19181
    9049             :       GIM_Try, /*On fail goto*//*Label 297*/ 19268,
    9050             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9051             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9052             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9053             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    9054             :         // No instruction predicates
    9055             :         // MIs[0] dst
    9056             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    9057             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9058             :         // MIs[0] Operand 1
    9059             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    9060             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9061             :         // MIs[1] Operand 0
    9062             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    9063             :         // MIs[1] Operand 1
    9064             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
    9065             :         // MIs[1] Rn
    9066             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    9067             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9068             :         // MIs[1] Rm
    9069             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    9070             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    9071             :         // MIs[0] Rd
    9072             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    9073             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9074             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9075             :         // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 283:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    9076             :         // Rule ID 3914
    9077             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
    9078             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9079             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9080             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9081             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    9082             :         GIR_EraseFromParent, /*InsnID*/0,
    9083             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9084             :         GIR_Done,
    9085             :       // Label 297: @19268
    9086             :       GIM_Try, /*On fail goto*//*Label 298*/ 19355,
    9087             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9088             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9089             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9090             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    9091             :         // No instruction predicates
    9092             :         // MIs[0] dst
    9093             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9094             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9095             :         // MIs[0] Operand 1
    9096             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    9097             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9098             :         // MIs[1] Operand 0
    9099             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    9100             :         // MIs[1] Operand 1
    9101             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
    9102             :         // MIs[1] Rn
    9103             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    9104             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9105             :         // MIs[1] Rm
    9106             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    9107             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    9108             :         // MIs[0] Rd
    9109             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9110             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9111             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9112             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 337:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    9113             :         // Rule ID 3928
    9114             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
    9115             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9116             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9117             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9118             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    9119             :         GIR_EraseFromParent, /*InsnID*/0,
    9120             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9121             :         GIR_Done,
    9122             :       // Label 298: @19355
    9123             :       GIM_Try, /*On fail goto*//*Label 299*/ 19442,
    9124             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9125             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9126             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9127             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    9128             :         // No instruction predicates
    9129             :         // MIs[0] dst
    9130             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9131             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9132             :         // MIs[0] Operand 1
    9133             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    9134             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9135             :         // MIs[1] Operand 0
    9136             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    9137             :         // MIs[1] Operand 1
    9138             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
    9139             :         // MIs[1] Rn
    9140             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    9141             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9142             :         // MIs[1] Rm
    9143             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    9144             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    9145             :         // MIs[0] Rd
    9146             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9147             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9148             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9149             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 337:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    9150             :         // Rule ID 3930
    9151             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
    9152             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9153             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9154             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9155             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    9156             :         GIR_EraseFromParent, /*InsnID*/0,
    9157             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9158             :         GIR_Done,
    9159             :       // Label 299: @19442
    9160             :       GIM_Try, /*On fail goto*//*Label 300*/ 19529,
    9161             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9162             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9163             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9164             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    9165             :         // No instruction predicates
    9166             :         // MIs[0] dst
    9167             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    9168             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9169             :         // MIs[0] Operand 1
    9170             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    9171             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9172             :         // MIs[1] Operand 0
    9173             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    9174             :         // MIs[1] Operand 1
    9175             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
    9176             :         // MIs[1] Rn
    9177             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    9178             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9179             :         // MIs[1] Rm
    9180             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    9181             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    9182             :         // MIs[0] Rd
    9183             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    9184             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9185             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9186             :         // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 337:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    9187             :         // Rule ID 3932
    9188             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
    9189             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9190             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9191             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9192             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    9193             :         GIR_EraseFromParent, /*InsnID*/0,
    9194             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9195             :         GIR_Done,
    9196             :       // Label 300: @19529
    9197             :       GIM_Try, /*On fail goto*//*Label 301*/ 19604,
    9198             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9199             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9200             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9201             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9202             :         // No instruction predicates
    9203             :         // MIs[0] dst
    9204             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9205             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9206             :         // MIs[0] Operand 1
    9207             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    9208             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9209             :         // MIs[1] Operand 0
    9210             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    9211             :         // MIs[1] Operand 1
    9212             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9213             :         // MIs[1] Rn
    9214             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    9215             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9216             :         // MIs[0] Rd
    9217             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9218             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9219             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9220             :         // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 267:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
    9221             :         // Rule ID 3826
    9222             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
    9223             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9224             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9225             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9226             :         GIR_EraseFromParent, /*InsnID*/0,
    9227             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9228             :         GIR_Done,
    9229             :       // Label 301: @19604
    9230             :       GIM_Try, /*On fail goto*//*Label 302*/ 19679,
    9231             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9232             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9233             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9234             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9235             :         // No instruction predicates
    9236             :         // MIs[0] dst
    9237             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9238             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9239             :         // MIs[0] Operand 1
    9240             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    9241             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9242             :         // MIs[1] Operand 0
    9243             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    9244             :         // MIs[1] Operand 1
    9245             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9246             :         // MIs[1] Rn
    9247             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    9248             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9249             :         // MIs[0] Rd
    9250             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9251             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9252             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9253             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 267:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
    9254             :         // Rule ID 3827
    9255             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
    9256             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9257             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9258             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9259             :         GIR_EraseFromParent, /*InsnID*/0,
    9260             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9261             :         GIR_Done,
    9262             :       // Label 302: @19679
    9263             :       GIM_Try, /*On fail goto*//*Label 303*/ 19754,
    9264             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9265             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9266             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9267             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9268             :         // No instruction predicates
    9269             :         // MIs[0] dst
    9270             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9271             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9272             :         // MIs[0] Operand 1
    9273             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    9274             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9275             :         // MIs[1] Operand 0
    9276             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    9277             :         // MIs[1] Operand 1
    9278             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9279             :         // MIs[1] Rn
    9280             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    9281             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9282             :         // MIs[0] Rd
    9283             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9284             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9285             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9286             :         // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 267:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
    9287             :         // Rule ID 3828
    9288             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
    9289             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9290             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9291             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9292             :         GIR_EraseFromParent, /*InsnID*/0,
    9293             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9294             :         GIR_Done,
    9295             :       // Label 303: @19754
    9296             :       GIM_Try, /*On fail goto*//*Label 304*/ 19829,
    9297             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9298             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9299             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9300             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9301             :         // No instruction predicates
    9302             :         // MIs[0] dst
    9303             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9304             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9305             :         // MIs[0] Operand 1
    9306             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    9307             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9308             :         // MIs[1] Operand 0
    9309             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    9310             :         // MIs[1] Operand 1
    9311             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9312             :         // MIs[1] Rn
    9313             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    9314             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9315             :         // MIs[0] Rd
    9316             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9317             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9318             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9319             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 267:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
    9320             :         // Rule ID 3829
    9321             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
    9322             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9323             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9324             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9325             :         GIR_EraseFromParent, /*InsnID*/0,
    9326             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9327             :         GIR_Done,
    9328             :       // Label 304: @19829
    9329             :       GIM_Try, /*On fail goto*//*Label 305*/ 19904,
    9330             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9331             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9332             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9333             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9334             :         // No instruction predicates
    9335             :         // MIs[0] dst
    9336             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    9337             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9338             :         // MIs[0] Operand 1
    9339             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    9340             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9341             :         // MIs[1] Operand 0
    9342             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    9343             :         // MIs[1] Operand 1
    9344             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9345             :         // MIs[1] Rn
    9346             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    9347             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9348             :         // MIs[0] Rd
    9349             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    9350             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9351             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9352             :         // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 267:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
    9353             :         // Rule ID 3830
    9354             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
    9355             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9356             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9357             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9358             :         GIR_EraseFromParent, /*InsnID*/0,
    9359             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9360             :         GIR_Done,
    9361             :       // Label 305: @19904
    9362             :       GIM_Try, /*On fail goto*//*Label 306*/ 19979,
    9363             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9364             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9365             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9366             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9367             :         // No instruction predicates
    9368             :         // MIs[0] dst
    9369             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    9370             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9371             :         // MIs[0] Operand 1
    9372             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    9373             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9374             :         // MIs[1] Operand 0
    9375             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    9376             :         // MIs[1] Operand 1
    9377             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9378             :         // MIs[1] Rn
    9379             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    9380             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9381             :         // MIs[0] Rd
    9382             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    9383             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9384             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9385             :         // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 267:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
    9386             :         // Rule ID 3831
    9387             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
    9388             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9389             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9390             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9391             :         GIR_EraseFromParent, /*InsnID*/0,
    9392             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9393             :         GIR_Done,
    9394             :       // Label 306: @19979
    9395             :       GIM_Try, /*On fail goto*//*Label 307*/ 20054,
    9396             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9397             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9398             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9399             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9400             :         // No instruction predicates
    9401             :         // MIs[0] dst
    9402             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9403             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9404             :         // MIs[0] Operand 1
    9405             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    9406             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9407             :         // MIs[1] Operand 0
    9408             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    9409             :         // MIs[1] Operand 1
    9410             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
    9411             :         // MIs[1] Rn
    9412             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    9413             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9414             :         // MIs[0] Rd
    9415             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9416             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9417             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9418             :         // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 325:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
    9419             :         // Rule ID 3832
    9420             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
    9421             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9422             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9423             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9424             :         GIR_EraseFromParent, /*InsnID*/0,
    9425             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9426             :         GIR_Done,
    9427             :       // Label 307: @20054
    9428             :       GIM_Try, /*On fail goto*//*Label 308*/ 20129,
    9429             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9430             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9431             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9432             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9433             :         // No instruction predicates
    9434             :         // MIs[0] dst
    9435             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9436             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9437             :         // MIs[0] Operand 1
    9438             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    9439             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9440             :         // MIs[1] Operand 0
    9441             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    9442             :         // MIs[1] Operand 1
    9443             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
    9444             :         // MIs[1] Rn
    9445             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    9446             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9447             :         // MIs[0] Rd
    9448             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9449             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9450             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9451             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 325:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
    9452             :         // Rule ID 3833
    9453             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
    9454             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9455             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9456             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9457             :         GIR_EraseFromParent, /*InsnID*/0,
    9458             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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