LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenGlobalISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 46 125 36.8 %
Date: 2018-02-25 19:55:18 Functions: 5 6 83.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Global Instruction Selector for the AArch64 target                         *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_GLOBALISEL_PREDICATE_BITSET
      10             : const unsigned MAX_SUBTARGET_PREDICATES = 14;
      11             : using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
      12             : #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
      13             : 
      14             : #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
      15             :   mutable MatcherState State;
      16             :   typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
      17             :   typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
      18             :   const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
      19             :   static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
      20             :   static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
      21             : bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
      22             : bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
      23             : bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
      24             : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
      25             : 
      26             : #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
      27             : , State(1),
      28        5296 : ISelInfo({TypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers})
      29             : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
      30             : 
      31             : #ifdef GET_GLOBALISEL_IMPL
      32             : // Bits for subtarget features that participate in instruction matching.
      33             : enum SubtargetFeatureBits : uint8_t {
      34             :   Feature_HasFPARMv8Bit = 2,
      35             :   Feature_HasNEONBit = 3,
      36             :   Feature_HasCryptoBit = 5,
      37             :   Feature_HasCRCBit = 0,
      38             :   Feature_HasLSEBit = 13,
      39             :   Feature_HasRDMBit = 4,
      40             :   Feature_HasPerfMonBit = 6,
      41             :   Feature_HasFullFP16Bit = 1,
      42             :   Feature_HasFuseAESBit = 11,
      43             :   Feature_IsLEBit = 7,
      44             :   Feature_IsBEBit = 12,
      45             :   Feature_UseAlternateSExtLoadCVTF32Bit = 10,
      46             :   Feature_NotForCodeSizeBit = 9,
      47             :   Feature_UseSTRQroBit = 8,
      48             : };
      49             : 
      50        1324 : PredicateBitset AArch64InstructionSelector::
      51             : computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
      52        1324 :   PredicateBitset Features;
      53        1324 :   if (Subtarget->hasFPARMv8())
      54             :     Features[Feature_HasFPARMv8Bit] = 1;
      55        1324 :   if (Subtarget->hasNEON())
      56             :     Features[Feature_HasNEONBit] = 1;
      57        1324 :   if (Subtarget->hasCrypto())
      58             :     Features[Feature_HasCryptoBit] = 1;
      59        1324 :   if (Subtarget->hasCRC())
      60             :     Features[Feature_HasCRCBit] = 1;
      61        1324 :   if (Subtarget->hasLSE())
      62             :     Features[Feature_HasLSEBit] = 1;
      63        1324 :   if (Subtarget->hasRDM())
      64             :     Features[Feature_HasRDMBit] = 1;
      65        1324 :   if (Subtarget->hasPerfMon())
      66             :     Features[Feature_HasPerfMonBit] = 1;
      67        1324 :   if (Subtarget->hasFullFP16())
      68             :     Features[Feature_HasFullFP16Bit] = 1;
      69        1324 :   if (Subtarget->hasFuseAES())
      70             :     Features[Feature_HasFuseAESBit] = 1;
      71        1324 :   if (Subtarget->isLittleEndian())
      72             :     Features[Feature_IsLEBit] = 1;
      73        1324 :   if (!Subtarget->isLittleEndian())
      74             :     Features[Feature_IsBEBit] = 1;
      75        1324 :   if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
      76             :     Features[Feature_UseAlternateSExtLoadCVTF32Bit] = 1;
      77        1324 :   return Features;
      78             : }
      79             : 
      80         612 : PredicateBitset AArch64InstructionSelector::
      81             : computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
      82         612 :   PredicateBitset Features;
      83         612 :   if (!MF->getFunction().optForSize())
      84             :     Features[Feature_NotForCodeSizeBit] = 1;
      85         612 :   if (!Subtarget->isSTRQroSlow() || MF->getFunction().optForSize())
      86             :     Features[Feature_UseSTRQroBit] = 1;
      87         612 :   return Features;
      88             : }
      89             : 
      90             : // LLT Objects.
      91             : enum {
      92             :   GILLT_s1,
      93             :   GILLT_s8,
      94             :   GILLT_s16,
      95             :   GILLT_s32,
      96             :   GILLT_s64,
      97             :   GILLT_s128,
      98             :   GILLT_v2s32,
      99             :   GILLT_v2s64,
     100             :   GILLT_v4s16,
     101             :   GILLT_v4s32,
     102             :   GILLT_v8s8,
     103             :   GILLT_v8s16,
     104             :   GILLT_v16s8,
     105             : };
     106             : const static LLT TypeObjects[] = {
     107             :   LLT::scalar(1),
     108             :   LLT::scalar(8),
     109             :   LLT::scalar(16),
     110             :   LLT::scalar(32),
     111             :   LLT::scalar(64),
     112             :   LLT::scalar(128),
     113             :   LLT::vector(2, 32),
     114             :   LLT::vector(2, 64),
     115             :   LLT::vector(4, 16),
     116             :   LLT::vector(4, 32),
     117             :   LLT::vector(8, 8),
     118             :   LLT::vector(8, 16),
     119             :   LLT::vector(16, 8),
     120       81774 : };
     121             : 
     122             : // Feature bitsets.
     123             : enum {
     124             :   GIFBS_Invalid,
     125             :   GIFBS_HasCRC,
     126             :   GIFBS_HasCrypto,
     127             :   GIFBS_HasFPARMv8,
     128             :   GIFBS_HasFullFP16,
     129             :   GIFBS_HasFuseAES,
     130             :   GIFBS_HasLSE,
     131             :   GIFBS_HasNEON,
     132             :   GIFBS_HasRDM,
     133             :   GIFBS_IsBE,
     134             :   GIFBS_IsLE,
     135             :   GIFBS_HasFullFP16_HasNEON,
     136             :   GIFBS_HasNEON_HasRDM,
     137             : };
     138             : const static PredicateBitset FeatureBitsets[] {
     139             :   {}, // GIFBS_Invalid
     140             :   {Feature_HasCRCBit, },
     141             :   {Feature_HasCryptoBit, },
     142             :   {Feature_HasFPARMv8Bit, },
     143             :   {Feature_HasFullFP16Bit, },
     144             :   {Feature_HasFuseAESBit, },
     145             :   {Feature_HasLSEBit, },
     146             :   {Feature_HasNEONBit, },
     147             :   {Feature_HasRDMBit, },
     148             :   {Feature_IsBEBit, },
     149             :   {Feature_IsLEBit, },
     150             :   {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
     151             :   {Feature_HasNEONBit, Feature_HasRDMBit, },
     152       81774 : };
     153             : 
     154             : // ComplexPattern predicates.
     155             : enum {
     156             :   GICP_Invalid,
     157             :   GICP_gi_addsub_shifted_imm32,
     158             :   GICP_gi_addsub_shifted_imm64,
     159             :   GICP_gi_am_indexed128,
     160             :   GICP_gi_am_indexed16,
     161             :   GICP_gi_am_indexed32,
     162             :   GICP_gi_am_indexed64,
     163             :   GICP_gi_am_indexed8,
     164             :   GICP_gi_am_unscaled128,
     165             :   GICP_gi_am_unscaled16,
     166             :   GICP_gi_am_unscaled32,
     167             :   GICP_gi_am_unscaled64,
     168             :   GICP_gi_am_unscaled8,
     169             : };
     170             : // See constructor for table contents
     171             : 
     172             : // PatFrag predicates.
     173             : enum {
     174             :   GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1,
     175             :   GIPFP_I64_Predicate_VectorIndexB,
     176             :   GIPFP_I64_Predicate_VectorIndexD,
     177             :   GIPFP_I64_Predicate_VectorIndexH,
     178             :   GIPFP_I64_Predicate_VectorIndexS,
     179             :   GIPFP_I64_Predicate_i64imm_32bit,
     180             :   GIPFP_I64_Predicate_imm0_1,
     181             :   GIPFP_I64_Predicate_imm0_127,
     182             :   GIPFP_I64_Predicate_imm0_15,
     183             :   GIPFP_I64_Predicate_imm0_255,
     184             :   GIPFP_I64_Predicate_imm0_31,
     185             :   GIPFP_I64_Predicate_imm0_63,
     186             :   GIPFP_I64_Predicate_imm0_65535,
     187             :   GIPFP_I64_Predicate_imm0_7,
     188             :   GIPFP_I64_Predicate_imm32_0_15,
     189             :   GIPFP_I64_Predicate_imm32_0_31,
     190             :   GIPFP_I64_Predicate_maski16_or_more,
     191             :   GIPFP_I64_Predicate_maski8_or_more,
     192             :   GIPFP_I64_Predicate_s64imm_32bit,
     193             :   GIPFP_I64_Predicate_simm6_32b,
     194             :   GIPFP_I64_Predicate_simm9,
     195             :   GIPFP_I64_Predicate_sve_pred_enum,
     196             :   GIPFP_I64_Predicate_tbz_imm0_31_diag,
     197             :   GIPFP_I64_Predicate_tbz_imm0_31_nodiag,
     198             :   GIPFP_I64_Predicate_tbz_imm32_63,
     199             :   GIPFP_I64_Predicate_vecshiftL16,
     200             :   GIPFP_I64_Predicate_vecshiftL32,
     201             :   GIPFP_I64_Predicate_vecshiftL64,
     202             :   GIPFP_I64_Predicate_vecshiftL8,
     203             :   GIPFP_I64_Predicate_vecshiftR16,
     204             :   GIPFP_I64_Predicate_vecshiftR16Narrow,
     205             :   GIPFP_I64_Predicate_vecshiftR32,
     206             :   GIPFP_I64_Predicate_vecshiftR32Narrow,
     207             :   GIPFP_I64_Predicate_vecshiftR64,
     208             :   GIPFP_I64_Predicate_vecshiftR64Narrow,
     209             :   GIPFP_I64_Predicate_vecshiftR8,
     210             : };
     211           5 : bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
     212           5 :   switch (PredicateID) {
     213           0 :   case GIPFP_I64_Predicate_VectorIndex1: {
     214             :     
     215           0 :   return ((uint64_t)Imm) == 1;
     216             : 
     217             :     llvm_unreachable("ImmediateCode should have returned");
     218             :     return false;
     219             :   }
     220           0 :   case GIPFP_I64_Predicate_VectorIndexB: {
     221             :     
     222           0 :   return ((uint64_t)Imm) < 16;
     223             : 
     224             :     llvm_unreachable("ImmediateCode should have returned");
     225             :     return false;
     226             :   }
     227           0 :   case GIPFP_I64_Predicate_VectorIndexD: {
     228             :     
     229           0 :   return ((uint64_t)Imm) < 2;
     230             : 
     231             :     llvm_unreachable("ImmediateCode should have returned");
     232             :     return false;
     233             :   }
     234           0 :   case GIPFP_I64_Predicate_VectorIndexH: {
     235             :     
     236           0 :   return ((uint64_t)Imm) < 8;
     237             : 
     238             :     llvm_unreachable("ImmediateCode should have returned");
     239             :     return false;
     240             :   }
     241           0 :   case GIPFP_I64_Predicate_VectorIndexS: {
     242             :     
     243           0 :   return ((uint64_t)Imm) < 4;
     244             : 
     245             :     llvm_unreachable("ImmediateCode should have returned");
     246             :     return false;
     247             :   }
     248           0 :   case GIPFP_I64_Predicate_i64imm_32bit: {
     249             :     
     250           0 :   return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
     251             : 
     252             :     llvm_unreachable("ImmediateCode should have returned");
     253             :     return false;
     254             :   }
     255           0 :   case GIPFP_I64_Predicate_imm0_1: {
     256             :     
     257           0 :   return ((uint64_t)Imm) < 2;
     258             : 
     259             :     llvm_unreachable("ImmediateCode should have returned");
     260             :     return false;
     261             :   }
     262           1 :   case GIPFP_I64_Predicate_imm0_127: {
     263             :     
     264           1 :   return ((uint32_t)Imm) < 128;
     265             : 
     266             :     llvm_unreachable("ImmediateCode should have returned");
     267             :     return false;
     268             :   }
     269           0 :   case GIPFP_I64_Predicate_imm0_15: {
     270             :     
     271           0 :   return ((uint64_t)Imm) < 16;
     272             : 
     273             :     llvm_unreachable("ImmediateCode should have returned");
     274             :     return false;
     275             :   }
     276           0 :   case GIPFP_I64_Predicate_imm0_255: {
     277             :     
     278           0 :   return ((uint32_t)Imm) < 256;
     279             : 
     280             :     llvm_unreachable("ImmediateCode should have returned");
     281             :     return false;
     282             :   }
     283           0 :   case GIPFP_I64_Predicate_imm0_31: {
     284             :     
     285           0 :   return ((uint64_t)Imm) < 32;
     286             : 
     287             :     llvm_unreachable("ImmediateCode should have returned");
     288             :     return false;
     289             :   }
     290           2 :   case GIPFP_I64_Predicate_imm0_63: {
     291             :     
     292           2 :   return ((uint64_t)Imm) < 64;
     293             : 
     294             :     llvm_unreachable("ImmediateCode should have returned");
     295             :     return false;
     296             :   }
     297           0 :   case GIPFP_I64_Predicate_imm0_65535: {
     298             :     
     299           0 :   return ((uint32_t)Imm) < 65536;
     300             : 
     301             :     llvm_unreachable("ImmediateCode should have returned");
     302             :     return false;
     303             :   }
     304           0 :   case GIPFP_I64_Predicate_imm0_7: {
     305             :     
     306           0 :   return ((uint64_t)Imm) < 8;
     307             : 
     308             :     llvm_unreachable("ImmediateCode should have returned");
     309             :     return false;
     310             :   }
     311           0 :   case GIPFP_I64_Predicate_imm32_0_15: {
     312             :     
     313           0 :   return ((uint32_t)Imm) < 16;
     314             : 
     315             :     llvm_unreachable("ImmediateCode should have returned");
     316             :     return false;
     317             :   }
     318           0 :   case GIPFP_I64_Predicate_imm32_0_31: {
     319             :     
     320           0 :   return ((uint64_t)Imm) < 32;
     321             : 
     322             :     llvm_unreachable("ImmediateCode should have returned");
     323             :     return false;
     324             :   }
     325           0 :   case GIPFP_I64_Predicate_maski16_or_more: {
     326           0 :      return (Imm & 0xffff) == 0xffff; 
     327             :     llvm_unreachable("ImmediateCode should have returned");
     328             :     return false;
     329             :   }
     330           0 :   case GIPFP_I64_Predicate_maski8_or_more: {
     331           0 :      return (Imm & 0xff) == 0xff; 
     332             :     llvm_unreachable("ImmediateCode should have returned");
     333             :     return false;
     334             :   }
     335           1 :   case GIPFP_I64_Predicate_s64imm_32bit: {
     336             :     
     337             :   int64_t Imm64 = static_cast<int64_t>(Imm);
     338           1 :   return Imm64 >= std::numeric_limits<int32_t>::min() &&
     339           1 :          Imm64 <= std::numeric_limits<int32_t>::max();
     340             : 
     341             :     llvm_unreachable("ImmediateCode should have returned");
     342             :     return false;
     343             :   }
     344           0 :   case GIPFP_I64_Predicate_simm6_32b: {
     345           0 :      return Imm >= -32 && Imm < 32; 
     346             :     llvm_unreachable("ImmediateCode should have returned");
     347             :     return false;
     348             :   }
     349           0 :   case GIPFP_I64_Predicate_simm9: {
     350           0 :      return Imm >= -256 && Imm < 256; 
     351             :     llvm_unreachable("ImmediateCode should have returned");
     352             :     return false;
     353             :   }
     354           0 :   case GIPFP_I64_Predicate_sve_pred_enum: {
     355             :     
     356           0 :   return (((uint32_t)Imm) < 32);
     357             :   
     358             :     llvm_unreachable("ImmediateCode should have returned");
     359             :     return false;
     360             :   }
     361           0 :   case GIPFP_I64_Predicate_tbz_imm0_31_diag: {
     362             :     
     363           0 :   return (((uint32_t)Imm) < 32);
     364             : 
     365             :     llvm_unreachable("ImmediateCode should have returned");
     366             :     return false;
     367             :   }
     368           0 :   case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: {
     369             :     
     370           0 :   return (((uint32_t)Imm) < 32);
     371             : 
     372             :     llvm_unreachable("ImmediateCode should have returned");
     373             :     return false;
     374             :   }
     375           0 :   case GIPFP_I64_Predicate_tbz_imm32_63: {
     376             :     
     377           0 :   return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
     378             : 
     379             :     llvm_unreachable("ImmediateCode should have returned");
     380             :     return false;
     381             :   }
     382           0 :   case GIPFP_I64_Predicate_vecshiftL16: {
     383             :     
     384           0 :   return (((uint32_t)Imm) < 16);
     385             : 
     386             :     llvm_unreachable("ImmediateCode should have returned");
     387             :     return false;
     388             :   }
     389           0 :   case GIPFP_I64_Predicate_vecshiftL32: {
     390             :     
     391           0 :   return (((uint32_t)Imm) < 32);
     392             : 
     393             :     llvm_unreachable("ImmediateCode should have returned");
     394             :     return false;
     395             :   }
     396           0 :   case GIPFP_I64_Predicate_vecshiftL64: {
     397             :     
     398           0 :   return (((uint32_t)Imm) < 64);
     399             : 
     400             :     llvm_unreachable("ImmediateCode should have returned");
     401             :     return false;
     402             :   }
     403           0 :   case GIPFP_I64_Predicate_vecshiftL8: {
     404             :     
     405           0 :   return (((uint32_t)Imm) < 8);
     406             : 
     407             :     llvm_unreachable("ImmediateCode should have returned");
     408             :     return false;
     409             :   }
     410           0 :   case GIPFP_I64_Predicate_vecshiftR16: {
     411             :     
     412           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
     413             : 
     414             :     llvm_unreachable("ImmediateCode should have returned");
     415             :     return false;
     416             :   }
     417           0 :   case GIPFP_I64_Predicate_vecshiftR16Narrow: {
     418             :     
     419           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
     420             : 
     421             :     llvm_unreachable("ImmediateCode should have returned");
     422             :     return false;
     423             :   }
     424           0 :   case GIPFP_I64_Predicate_vecshiftR32: {
     425             :     
     426           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
     427             : 
     428             :     llvm_unreachable("ImmediateCode should have returned");
     429             :     return false;
     430             :   }
     431           0 :   case GIPFP_I64_Predicate_vecshiftR32Narrow: {
     432             :     
     433           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
     434             : 
     435             :     llvm_unreachable("ImmediateCode should have returned");
     436             :     return false;
     437             :   }
     438           1 :   case GIPFP_I64_Predicate_vecshiftR64: {
     439             :     
     440           1 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
     441             : 
     442             :     llvm_unreachable("ImmediateCode should have returned");
     443             :     return false;
     444             :   }
     445           0 :   case GIPFP_I64_Predicate_vecshiftR64Narrow: {
     446             :     
     447           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
     448             : 
     449             :     llvm_unreachable("ImmediateCode should have returned");
     450             :     return false;
     451             :   }
     452           0 :   case GIPFP_I64_Predicate_vecshiftR8: {
     453             :     
     454           0 :   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
     455             : 
     456             :     llvm_unreachable("ImmediateCode should have returned");
     457             :     return false;
     458             :   }
     459             :   }
     460           0 :   llvm_unreachable("Unknown predicate");
     461             :   return false;
     462             : }
     463             : // PatFrag predicates.
     464             : enum {
     465             :   GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
     466             :   GIPFP_APFloat_Predicate_fpimm16,
     467             :   GIPFP_APFloat_Predicate_fpimm32,
     468             :   GIPFP_APFloat_Predicate_fpimm64,
     469             :   GIPFP_APFloat_Predicate_simdimmtype10,
     470             : };
     471          59 : bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
     472          59 :   switch (PredicateID) {
     473          59 :   case GIPFP_APFloat_Predicate_fpimm0: {
     474             :     
     475          59 :   return Imm.isExactlyValue(+0.0);
     476             : 
     477             :     llvm_unreachable("ImmediateCode should have returned");
     478             :     return false;
     479             :   }
     480           0 :   case GIPFP_APFloat_Predicate_fpimm16: {
     481             :     
     482           0 :       return AArch64_AM::getFP16Imm(Imm) != -1;
     483             :     
     484             :     llvm_unreachable("ImmediateCode should have returned");
     485             :     return false;
     486             :   }
     487           0 :   case GIPFP_APFloat_Predicate_fpimm32: {
     488             :     
     489           0 :       return AArch64_AM::getFP32Imm(Imm) != -1;
     490             :     
     491             :     llvm_unreachable("ImmediateCode should have returned");
     492             :     return false;
     493             :   }
     494           0 :   case GIPFP_APFloat_Predicate_fpimm64: {
     495             :     
     496           0 :       return AArch64_AM::getFP64Imm(Imm) != -1;
     497             :     
     498             :     llvm_unreachable("ImmediateCode should have returned");
     499             :     return false;
     500             :   }
     501           0 :   case GIPFP_APFloat_Predicate_simdimmtype10: {
     502             :     
     503             :       return AArch64_AM::isAdvSIMDModImmType10(
     504           0 :                  Imm.bitcastToAPInt().getZExtValue());
     505             :     
     506             :     llvm_unreachable("ImmediateCode should have returned");
     507             :     return false;
     508             :   }
     509             :   }
     510           0 :   llvm_unreachable("Unknown predicate");
     511             :   return false;
     512             : }
     513             : // PatFrag predicates.
     514             : enum {
     515             :   GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1,
     516             :   GIPFP_APInt_Predicate_logical_imm64,
     517             : };
     518           0 : bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
     519           0 :   switch (PredicateID) {
     520             :   case GIPFP_APInt_Predicate_logical_imm32: {
     521             :     
     522           0 :   return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
     523             : 
     524             :     llvm_unreachable("ImmediateCode should have returned");
     525             :     return false;
     526             :   }
     527             :   case GIPFP_APInt_Predicate_logical_imm64: {
     528             :     
     529           0 :   return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
     530             : 
     531             :     llvm_unreachable("ImmediateCode should have returned");
     532             :     return false;
     533             :   }
     534             :   }
     535           0 :   llvm_unreachable("Unknown predicate");
     536             :   return false;
     537             : }
     538             : 
     539             : AArch64InstructionSelector::ComplexMatcherMemFn
     540             : AArch64InstructionSelector::ComplexPredicateFns[] = {
     541             :   nullptr, // GICP_Invalid
     542             :   &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
     543             :   &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
     544             :   &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
     545             :   &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
     546             :   &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
     547             :   &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
     548             :   &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
     549             :   &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
     550             :   &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
     551             :   &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
     552             :   &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
     553             :   &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
     554             : };
     555             : 
     556             : // Custom renderers.
     557             : enum {
     558             :   GICR_Invalid,
     559             :   GICR_renderTruncImm, 
     560             : };
     561             : AArch64InstructionSelector::CustomRendererFn
     562             : AArch64InstructionSelector::CustomRenderers[] = {
     563             :   nullptr, // GICP_Invalid
     564             :   &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm
     565             : };
     566             : 
     567         612 : bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
     568         612 :   MachineFunction &MF = *I.getParent()->getParent();
     569         612 :   MachineRegisterInfo &MRI = MF.getRegInfo();
     570             :   // FIXME: This should be computed on a per-function basis rather than per-insn.
     571         612 :   AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
     572         612 :   const PredicateBitset AvailableFeatures = getAvailableFeatures();
     573             :   NewMIVector OutMIs;
     574             :   State.MIs.clear();
     575         612 :   State.MIs.push_back(&I);
     576             : 
     577             :   constexpr static int64_t MatchTable0[] = {
     578             :     GIM_Try, /*On fail goto*//*Label 0*/ 357,
     579             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXT,
     580             :       GIM_Try, /*On fail goto*//*Label 1*/ 75,
     581             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     582             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     583             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
     584             :         // No instruction predicates
     585             :         // MIs[0] Rt
     586             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     587             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
     588             :         // MIs[0] Operand 1
     589             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
     590             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
     591             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     592             :         // MIs[1] Operand 0
     593             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
     594             :         // MIs[1] Operand 1
     595             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     596             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
     597             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     598             :         // (sext:{ *:[i32] } (ld:{ *:[i16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     599             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWui,
     600             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     601             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     602             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     603             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
     604             :         GIR_EraseFromParent, /*InsnID*/0,
     605             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     606             :         GIR_Done,
     607             :       // Label 1: @75
     608             :       GIM_Try, /*On fail goto*//*Label 2*/ 145,
     609             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     610             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     611             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
     612             :         // No instruction predicates
     613             :         // MIs[0] Rt
     614             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     615             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     616             :         // MIs[0] Operand 1
     617             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
     618             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
     619             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     620             :         // MIs[1] Operand 0
     621             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
     622             :         // MIs[1] Operand 1
     623             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     624             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
     625             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     626             :         // (sext:{ *:[i64] } (ld:{ *:[i16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     627             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXui,
     628             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     629             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     630             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     631             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
     632             :         GIR_EraseFromParent, /*InsnID*/0,
     633             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     634             :         GIR_Done,
     635             :       // Label 2: @145
     636             :       GIM_Try, /*On fail goto*//*Label 3*/ 215,
     637             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     638             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     639             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
     640             :         // No instruction predicates
     641             :         // MIs[0] Rt
     642             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     643             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
     644             :         // MIs[0] Operand 1
     645             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
     646             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
     647             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     648             :         // MIs[1] Operand 0
     649             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
     650             :         // MIs[1] Operand 1
     651             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     652             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
     653             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     654             :         // (sext:{ *:[i32] } (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     655             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWui,
     656             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     657             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     658             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     659             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
     660             :         GIR_EraseFromParent, /*InsnID*/0,
     661             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     662             :         GIR_Done,
     663             :       // Label 3: @215
     664             :       GIM_Try, /*On fail goto*//*Label 4*/ 285,
     665             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     666             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     667             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
     668             :         // No instruction predicates
     669             :         // MIs[0] Rt
     670             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     671             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     672             :         // MIs[0] Operand 1
     673             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
     674             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
     675             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     676             :         // MIs[1] Operand 0
     677             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
     678             :         // MIs[1] Operand 1
     679             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     680             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
     681             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     682             :         // (sext:{ *:[i64] } (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     683             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXui,
     684             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     685             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     686             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     687             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
     688             :         GIR_EraseFromParent, /*InsnID*/0,
     689             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     690             :         GIR_Done,
     691             :       // Label 4: @285
     692             :       GIM_Try, /*On fail goto*//*Label 5*/ 355,
     693             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     694             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     695             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
     696             :         // No instruction predicates
     697             :         // MIs[0] Rt
     698             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     699             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     700             :         // MIs[0] Operand 1
     701             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
     702             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
     703             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     704             :         // MIs[1] Operand 0
     705             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
     706             :         // MIs[1] Operand 1
     707             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     708             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
     709             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     710             :         // (sext:{ *:[i64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     711             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWui,
     712             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     713             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     714             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     715             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
     716             :         GIR_EraseFromParent, /*InsnID*/0,
     717             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     718             :         GIR_Done,
     719             :       // Label 5: @355
     720             :       GIM_Reject,
     721             :       GIR_Done,
     722             :     // Label 0: @357
     723             :     GIM_Try, /*On fail goto*//*Label 6*/ 504,
     724             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT,
     725             :       GIM_Try, /*On fail goto*//*Label 7*/ 432,
     726             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     727             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     728             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
     729             :         // No instruction predicates
     730             :         // MIs[0] Rt
     731             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     732             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
     733             :         // MIs[0] Operand 1
     734             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
     735             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
     736             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     737             :         // MIs[1] Operand 0
     738             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
     739             :         // MIs[1] Operand 1
     740             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     741             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
     742             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     743             :         // (zext:{ *:[i32] } (ld:{ *:[i16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     744             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui,
     745             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     746             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     747             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     748             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
     749             :         GIR_EraseFromParent, /*InsnID*/0,
     750             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     751             :         GIR_Done,
     752             :       // Label 7: @432
     753             :       GIM_Try, /*On fail goto*//*Label 8*/ 502,
     754             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     755             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     756             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
     757             :         // No instruction predicates
     758             :         // MIs[0] Rt
     759             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     760             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
     761             :         // MIs[0] Operand 1
     762             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
     763             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
     764             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     765             :         // MIs[1] Operand 0
     766             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
     767             :         // MIs[1] Operand 1
     768             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     769             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
     770             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     771             :         // (zext:{ *:[i32] } (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     772             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
     773             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     774             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     775             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     776             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
     777             :         GIR_EraseFromParent, /*InsnID*/0,
     778             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     779             :         GIR_Done,
     780             :       // Label 8: @502
     781             :       GIM_Reject,
     782             :       GIR_Done,
     783             :     // Label 6: @504
     784             :     GIM_Try, /*On fail goto*//*Label 9*/ 773,
     785             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
     786             :       GIM_Try, /*On fail goto*//*Label 10*/ 640,
     787             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     788             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     789             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     790             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     791             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
     792             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     793             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
     794             :         // No instruction predicates
     795             :         // MIs[0] Rd
     796             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     797             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     798             :         // MIs[0] Operand 1
     799             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
     800             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
     801             :         // MIs[0] Operand 2
     802             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
     803             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
     804             :         // MIs[1] Operand 0
     805             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
     806             :         // MIs[1] Operand 1
     807             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     808             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
     809             :         // MIs[2] Operand 0
     810             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
     811             :         // MIs[2] Rn
     812             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     813             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
     814             :         // MIs[1] C
     815             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     816             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
     817             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
     818             :         // MIs[3] Operand 0
     819             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
     820             :         // MIs[3] Operand 1
     821             :         // No operand predicates
     822             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     823             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
     824             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
     825             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     826             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     827             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
     828             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     829             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
     830             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     831             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
     832             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     833             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     834             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     835             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
     836             :         GIR_EraseFromParent, /*InsnID*/0,
     837             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     838             :         GIR_Done,
     839             :       // Label 10: @640
     840             :       GIM_Try, /*On fail goto*//*Label 11*/ 771,
     841             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     842             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     843             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     844             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     845             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
     846             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     847             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
     848             :         // No instruction predicates
     849             :         // MIs[0] Rd
     850             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     851             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     852             :         // MIs[0] Operand 1
     853             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
     854             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
     855             :         // MIs[0] Operand 2
     856             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
     857             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
     858             :         // MIs[1] Operand 0
     859             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
     860             :         // MIs[1] Operand 1
     861             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     862             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
     863             :         // MIs[2] Operand 0
     864             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
     865             :         // MIs[2] Rn
     866             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     867             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
     868             :         // MIs[1] C
     869             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     870             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
     871             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
     872             :         // MIs[3] Operand 0
     873             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
     874             :         // MIs[3] Operand 1
     875             :         // No operand predicates
     876             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     877             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
     878             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
     879             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     880             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     881             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
     882             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     883             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
     884             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     885             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
     886             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     887             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     888             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     889             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
     890             :         GIR_EraseFromParent, /*InsnID*/0,
     891             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     892             :         GIR_Done,
     893             :       // Label 11: @771
     894             :       GIM_Reject,
     895             :       GIR_Done,
     896             :     // Label 9: @773
     897             :     GIM_Try, /*On fail goto*//*Label 12*/ 1074,
     898             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
     899             :       GIM_Try, /*On fail goto*//*Label 13*/ 827,
     900             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     901             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     902             :         // MIs[0] Rt
     903             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     904             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
     905             :         // MIs[0] Operand 1
     906             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     907             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
     908             :         // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     909             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui,
     910             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     911             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     912             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     913             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     914             :         GIR_EraseFromParent, /*InsnID*/0,
     915             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     916             :         GIR_Done,
     917             :       // Label 13: @827
     918             :       GIM_Try, /*On fail goto*//*Label 14*/ 876,
     919             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     920             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     921             :         // MIs[0] Rt
     922             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     923             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
     924             :         // MIs[0] Operand 1
     925             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     926             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
     927             :         // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     928             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui,
     929             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     930             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     931             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     932             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     933             :         GIR_EraseFromParent, /*InsnID*/0,
     934             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     935             :         GIR_Done,
     936             :       // Label 14: @876
     937             :       GIM_Try, /*On fail goto*//*Label 15*/ 925,
     938             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     939             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     940             :         // MIs[0] Rt
     941             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
     942             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID,
     943             :         // MIs[0] Operand 1
     944             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     945             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
     946             :         // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     947             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui,
     948             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     949             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     950             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     951             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     952             :         GIR_EraseFromParent, /*InsnID*/0,
     953             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     954             :         GIR_Done,
     955             :       // Label 15: @925
     956             :       GIM_Try, /*On fail goto*//*Label 16*/ 974,
     957             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     958             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     959             :         // MIs[0] Rt
     960             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     961             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
     962             :         // MIs[0] Operand 1
     963             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     964             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
     965             :         // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     966             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSui,
     967             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     968             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     969             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     970             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     971             :         GIR_EraseFromParent, /*InsnID*/0,
     972             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     973             :         GIR_Done,
     974             :       // Label 16: @974
     975             :       GIM_Try, /*On fail goto*//*Label 17*/ 1023,
     976             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     977             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     978             :         // MIs[0] Rt
     979             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     980             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
     981             :         // MIs[0] Operand 1
     982             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     983             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
     984             :         // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     985             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
     986             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
     987             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
     988             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
     989             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
     990             :         GIR_EraseFromParent, /*InsnID*/0,
     991             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     992             :         GIR_Done,
     993             :       // Label 17: @1023
     994             :       GIM_Try, /*On fail goto*//*Label 18*/ 1072,
     995             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     996             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
     997             :         // MIs[0] Rt
     998             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
     999             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1000             :         // MIs[0] Operand 1
    1001             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1002             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1003             :         // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1004             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    1005             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1006             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1007             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1008             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1009             :         GIR_EraseFromParent, /*InsnID*/0,
    1010             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1011             :         GIR_Done,
    1012             :       // Label 18: @1072
    1013             :       GIM_Reject,
    1014             :       GIR_Done,
    1015             :     // Label 12: @1074
    1016             :     GIM_Try, /*On fail goto*//*Label 19*/ 2087,
    1017             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE,
    1018             :       GIM_Try, /*On fail goto*//*Label 20*/ 1129,
    1019             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1020             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1021             :         // MIs[0] Rt
    1022             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1023             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1024             :         // MIs[0] Operand 1
    1025             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1026             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1027             :         // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1028             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui,
    1029             :         GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt
    1030             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1031             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1032             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1033             :         GIR_EraseFromParent, /*InsnID*/0,
    1034             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1035             :         GIR_Done,
    1036             :       // Label 20: @1129
    1037             :       GIM_Try, /*On fail goto*//*Label 21*/ 1179,
    1038             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1039             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1040             :         // MIs[0] Rt
    1041             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1042             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    1043             :         // MIs[0] Operand 1
    1044             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1045             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
    1046             :         // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
    1047             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui,
    1048             :         GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt
    1049             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1050             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1051             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1052             :         GIR_EraseFromParent, /*InsnID*/0,
    1053             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1054             :         GIR_Done,
    1055             :       // Label 21: @1179
    1056             :       GIM_Try, /*On fail goto*//*Label 22*/ 1228,
    1057             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1058             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1059             :         // MIs[0] Rt
    1060             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
    1061             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID,
    1062             :         // MIs[0] Operand 1
    1063             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1064             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
    1065             :         // (st FPR16:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHui FPR16:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
    1066             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui,
    1067             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1068             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1069             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1070             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1071             :         GIR_EraseFromParent, /*InsnID*/0,
    1072             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1073             :         GIR_Done,
    1074             :       // Label 22: @1228
    1075             :       GIM_Try, /*On fail goto*//*Label 23*/ 1277,
    1076             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1077             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1078             :         // MIs[0] Rt
    1079             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1080             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    1081             :         // MIs[0] Operand 1
    1082             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1083             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32,
    1084             :         // (st FPR32:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui FPR32:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
    1085             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSui,
    1086             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1087             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1088             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1089             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1090             :         GIR_EraseFromParent, /*InsnID*/0,
    1091             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1092             :         GIR_Done,
    1093             :       // Label 23: @1277
    1094             :       GIM_Try, /*On fail goto*//*Label 24*/ 1326,
    1095             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1096             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1097             :         // MIs[0] Rt
    1098             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1099             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1100             :         // MIs[0] Operand 1
    1101             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1102             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1103             :         // (st FPR64:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1104             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1105             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1106             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1107             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1108             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1109             :         GIR_EraseFromParent, /*InsnID*/0,
    1110             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1111             :         GIR_Done,
    1112             :       // Label 24: @1326
    1113             :       GIM_Try, /*On fail goto*//*Label 25*/ 1377,
    1114             :         GIM_CheckFeatures, GIFBS_IsLE,
    1115             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1116             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1117             :         // MIs[0] Rt
    1118             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1119             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1120             :         // MIs[0] Operand 1
    1121             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1122             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1123             :         // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1124             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1125             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1126             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1127             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1128             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1129             :         GIR_EraseFromParent, /*InsnID*/0,
    1130             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1131             :         GIR_Done,
    1132             :       // Label 25: @1377
    1133             :       GIM_Try, /*On fail goto*//*Label 26*/ 1428,
    1134             :         GIM_CheckFeatures, GIFBS_IsLE,
    1135             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1136             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1137             :         // MIs[0] Rt
    1138             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    1139             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1140             :         // MIs[0] Operand 1
    1141             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1142             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1143             :         // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1144             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1145             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1146             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1147             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1148             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1149             :         GIR_EraseFromParent, /*InsnID*/0,
    1150             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1151             :         GIR_Done,
    1152             :       // Label 26: @1428
    1153             :       GIM_Try, /*On fail goto*//*Label 27*/ 1479,
    1154             :         GIM_CheckFeatures, GIFBS_IsLE,
    1155             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1156             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1157             :         // MIs[0] Rt
    1158             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    1159             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1160             :         // MIs[0] Operand 1
    1161             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1162             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1163             :         // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1164             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1165             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1166             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1167             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1168             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1169             :         GIR_EraseFromParent, /*InsnID*/0,
    1170             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1171             :         GIR_Done,
    1172             :       // Label 27: @1479
    1173             :       GIM_Try, /*On fail goto*//*Label 28*/ 1530,
    1174             :         GIM_CheckFeatures, GIFBS_IsLE,
    1175             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1176             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1177             :         // MIs[0] Rt
    1178             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1179             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1180             :         // MIs[0] Operand 1
    1181             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1182             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1183             :         // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1184             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1185             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1186             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1187             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1188             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1189             :         GIR_EraseFromParent, /*InsnID*/0,
    1190             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1191             :         GIR_Done,
    1192             :       // Label 28: @1530
    1193             :       GIM_Try, /*On fail goto*//*Label 29*/ 1581,
    1194             :         GIM_CheckFeatures, GIFBS_IsLE,
    1195             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1196             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1197             :         // MIs[0] Rt
    1198             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    1199             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1200             :         // MIs[0] Operand 1
    1201             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1202             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1203             :         // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1204             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1205             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1206             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1207             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1208             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1209             :         GIR_EraseFromParent, /*InsnID*/0,
    1210             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1211             :         GIR_Done,
    1212             :       // Label 29: @1581
    1213             :       GIM_Try, /*On fail goto*//*Label 30*/ 1630,
    1214             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1215             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1216             :         // MIs[0] Rt
    1217             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1218             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1219             :         // MIs[0] Operand 1
    1220             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1221             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1222             :         // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1223             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1224             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1225             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1226             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1227             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1228             :         GIR_EraseFromParent, /*InsnID*/0,
    1229             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1230             :         GIR_Done,
    1231             :       // Label 30: @1630
    1232             :       GIM_Try, /*On fail goto*//*Label 31*/ 1679,
    1233             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1234             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1235             :         // MIs[0] Rt
    1236             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1237             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    1238             :         // MIs[0] Operand 1
    1239             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1240             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    1241             :         // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    1242             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui,
    1243             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1244             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1245             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1246             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1247             :         GIR_EraseFromParent, /*InsnID*/0,
    1248             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1249             :         GIR_Done,
    1250             :       // Label 31: @1679
    1251             :       GIM_Try, /*On fail goto*//*Label 32*/ 1730,
    1252             :         GIM_CheckFeatures, GIFBS_IsLE,
    1253             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1254             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1255             :         // MIs[0] Rt
    1256             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1257             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1258             :         // MIs[0] Operand 1
    1259             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1260             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1261             :         // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1262             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1263             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1264             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1265             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1266             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1267             :         GIR_EraseFromParent, /*InsnID*/0,
    1268             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1269             :         GIR_Done,
    1270             :       // Label 32: @1730
    1271             :       GIM_Try, /*On fail goto*//*Label 33*/ 1781,
    1272             :         GIM_CheckFeatures, GIFBS_IsLE,
    1273             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1274             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1275             :         // MIs[0] Rt
    1276             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    1277             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1278             :         // MIs[0] Operand 1
    1279             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1280             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1281             :         // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1282             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1283             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1284             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1285             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1286             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1287             :         GIR_EraseFromParent, /*InsnID*/0,
    1288             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1289             :         GIR_Done,
    1290             :       // Label 33: @1781
    1291             :       GIM_Try, /*On fail goto*//*Label 34*/ 1832,
    1292             :         GIM_CheckFeatures, GIFBS_IsLE,
    1293             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1294             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1295             :         // MIs[0] Rt
    1296             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    1297             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1298             :         // MIs[0] Operand 1
    1299             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1300             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1301             :         // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1302             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1303             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1304             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1305             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1306             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1307             :         GIR_EraseFromParent, /*InsnID*/0,
    1308             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1309             :         GIR_Done,
    1310             :       // Label 34: @1832
    1311             :       GIM_Try, /*On fail goto*//*Label 35*/ 1883,
    1312             :         GIM_CheckFeatures, GIFBS_IsLE,
    1313             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1314             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1315             :         // MIs[0] Rt
    1316             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    1317             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1318             :         // MIs[0] Operand 1
    1319             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1320             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1321             :         // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1322             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1323             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1324             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1325             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1326             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1327             :         GIR_EraseFromParent, /*InsnID*/0,
    1328             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1329             :         GIR_Done,
    1330             :       // Label 35: @1883
    1331             :       GIM_Try, /*On fail goto*//*Label 36*/ 1934,
    1332             :         GIM_CheckFeatures, GIFBS_IsLE,
    1333             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1334             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1335             :         // MIs[0] Rt
    1336             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1337             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1338             :         // MIs[0] Operand 1
    1339             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1340             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1341             :         // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1342             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1343             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1344             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1345             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1346             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1347             :         GIR_EraseFromParent, /*InsnID*/0,
    1348             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1349             :         GIR_Done,
    1350             :       // Label 36: @1934
    1351             :       GIM_Try, /*On fail goto*//*Label 37*/ 1985,
    1352             :         GIM_CheckFeatures, GIFBS_IsLE,
    1353             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1354             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1355             :         // MIs[0] Rt
    1356             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    1357             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1358             :         // MIs[0] Operand 1
    1359             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1360             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1361             :         // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1362             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1363             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1364             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1365             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1366             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1367             :         GIR_EraseFromParent, /*InsnID*/0,
    1368             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1369             :         GIR_Done,
    1370             :       // Label 37: @1985
    1371             :       GIM_Try, /*On fail goto*//*Label 38*/ 2036,
    1372             :         GIM_CheckFeatures, GIFBS_IsLE,
    1373             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1374             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1375             :         // MIs[0] Rt
    1376             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    1377             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1378             :         // MIs[0] Operand 1
    1379             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1380             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1381             :         // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1382             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1383             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1384             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1385             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1386             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1387             :         GIR_EraseFromParent, /*InsnID*/0,
    1388             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1389             :         GIR_Done,
    1390             :       // Label 38: @2036
    1391             :       GIM_Try, /*On fail goto*//*Label 39*/ 2085,
    1392             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    1393             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    1394             :         // MIs[0] Rt
    1395             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    1396             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    1397             :         // MIs[0] Operand 1
    1398             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    1399             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    1400             :         // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    1401             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui,
    1402             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    1403             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    1404             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    1405             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    1406             :         GIR_EraseFromParent, /*InsnID*/0,
    1407             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1408             :         GIR_Done,
    1409             :       // Label 39: @2085
    1410             :       GIM_Reject,
    1411             :       GIR_Done,
    1412             :     // Label 19: @2087
    1413             :     GIM_Try, /*On fail goto*//*Label 40*/ 2334,
    1414             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    1415             :       GIM_Try, /*On fail goto*//*Label 41*/ 2212,
    1416             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1417             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1418             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1419             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1420             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1421             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1422             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1423             :         // No instruction predicates
    1424             :         // MIs[0] Rd
    1425             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1426             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1427             :         // MIs[0] Operand 1
    1428             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1429             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
    1430             :         // MIs[0] Operand 2
    1431             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1432             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1433             :         // MIs[1] Operand 0
    1434             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1435             :         // MIs[1] Operand 1
    1436             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1437             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    1438             :         // MIs[2] Operand 0
    1439             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1440             :         // MIs[2] Rn
    1441             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1442             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1443             :         // MIs[1] Operand 2
    1444             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1445             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
    1446             :         // MIs[3] Operand 0
    1447             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1448             :         // MIs[3] Rm
    1449             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    1450             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1451             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1452             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1453             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1454             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
    1455             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
    1456             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1457             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1458             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    1459             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    1460             :         GIR_EraseFromParent, /*InsnID*/0,
    1461             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1462             :         GIR_Done,
    1463             :       // Label 41: @2212
    1464             :       GIM_Try, /*On fail goto*//*Label 42*/ 2332,
    1465             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1466             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1467             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1468             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1469             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1470             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1471             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1472             :         // No instruction predicates
    1473             :         // MIs[0] Rd
    1474             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1475             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1476             :         // MIs[0] Operand 1
    1477             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1478             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
    1479             :         // MIs[0] Operand 2
    1480             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1481             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1482             :         // MIs[1] Operand 0
    1483             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1484             :         // MIs[1] Operand 1
    1485             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1486             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    1487             :         // MIs[2] Operand 0
    1488             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1489             :         // MIs[2] Rn
    1490             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1491             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1492             :         // MIs[1] Operand 2
    1493             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1494             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
    1495             :         // MIs[3] Operand 0
    1496             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1497             :         // MIs[3] Rm
    1498             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    1499             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1500             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1501             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1502             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1503             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
    1504             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
    1505             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1506             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1507             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    1508             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    1509             :         GIR_EraseFromParent, /*InsnID*/0,
    1510             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1511             :         GIR_Done,
    1512             :       // Label 42: @2332
    1513             :       GIM_Reject,
    1514             :       GIR_Done,
    1515             :     // Label 40: @2334
    1516             :     GIM_Try, /*On fail goto*//*Label 43*/ 3065,
    1517             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
    1518             :       GIM_Try, /*On fail goto*//*Label 44*/ 2388,
    1519             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1520             :         // No instruction predicates
    1521             :         // MIs[0] Rd
    1522             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1523             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
    1524             :         // MIs[0] imm
    1525             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1526             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
    1527             :         // MIs[0] Rn
    1528             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1529             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
    1530             :         // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
    1531             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
    1532             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1533             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    1534             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    1535             :         GIR_EraseFromParent, /*InsnID*/0,
    1536             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1537             :         GIR_Done,
    1538             :       // Label 44: @2388
    1539             :       GIM_Try, /*On fail goto*//*Label 45*/ 2437,
    1540             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1541             :         // No instruction predicates
    1542             :         // MIs[0] Rd
    1543             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1544             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
    1545             :         // MIs[0] imm
    1546             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1547             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
    1548             :         // MIs[0] Rn
    1549             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1550             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID,
    1551             :         // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
    1552             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
    1553             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1554             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    1555             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    1556             :         GIR_EraseFromParent, /*InsnID*/0,
    1557             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1558             :         GIR_Done,
    1559             :       // Label 45: @2437
    1560             :       GIM_Try, /*On fail goto*//*Label 46*/ 2569,
    1561             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1562             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1563             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1564             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1565             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1566             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1567             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1568             :         // No instruction predicates
    1569             :         // MIs[0] Rd
    1570             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1571             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1572             :         // MIs[0] Operand 1
    1573             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1574             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1575             :         // MIs[1] Operand 0
    1576             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1577             :         // MIs[1] Operand 1
    1578             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1579             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    1580             :         // MIs[2] Operand 0
    1581             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1582             :         // MIs[2] Rn
    1583             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1584             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1585             :         // MIs[1] C
    1586             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1587             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    1588             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
    1589             :         // MIs[3] Operand 0
    1590             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1591             :         // MIs[3] Operand 1
    1592             :         // No operand predicates
    1593             :         // MIs[0] Ra
    1594             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1595             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    1596             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1597             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1598             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1599             :         // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    1600             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    1601             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    1602             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    1603             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    1604             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    1605             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    1606             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1607             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1608             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    1609             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
    1610             :         GIR_EraseFromParent, /*InsnID*/0,
    1611             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1612             :         GIR_Done,
    1613             :       // Label 46: @2569
    1614             :       GIM_Try, /*On fail goto*//*Label 47*/ 2701,
    1615             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1616             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1617             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1618             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1619             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1620             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1621             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1622             :         // No instruction predicates
    1623             :         // MIs[0] Rd
    1624             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1625             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1626             :         // MIs[0] Operand 1
    1627             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1628             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1629             :         // MIs[1] Operand 0
    1630             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1631             :         // MIs[1] Operand 1
    1632             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1633             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    1634             :         // MIs[2] Operand 0
    1635             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1636             :         // MIs[2] Rn
    1637             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1638             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1639             :         // MIs[1] C
    1640             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1641             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    1642             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
    1643             :         // MIs[3] Operand 0
    1644             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1645             :         // MIs[3] Operand 1
    1646             :         // No operand predicates
    1647             :         // MIs[0] Ra
    1648             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1649             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    1650             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1651             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1652             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1653             :         // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    1654             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    1655             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    1656             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    1657             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    1658             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    1659             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    1660             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1661             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1662             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    1663             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
    1664             :         GIR_EraseFromParent, /*InsnID*/0,
    1665             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1666             :         GIR_Done,
    1667             :       // Label 47: @2701
    1668             :       GIM_Try, /*On fail goto*//*Label 48*/ 2750,
    1669             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1670             :         // No instruction predicates
    1671             :         // MIs[0] Rd
    1672             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1673             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
    1674             :         // MIs[0] Rn
    1675             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1676             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
    1677             :         // MIs[0] imm
    1678             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1679             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
    1680             :         // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
    1681             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
    1682             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1683             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    1684             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    1685             :         GIR_EraseFromParent, /*InsnID*/0,
    1686             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1687             :         GIR_Done,
    1688             :       // Label 48: @2750
    1689             :       GIM_Try, /*On fail goto*//*Label 49*/ 2799,
    1690             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1691             :         // No instruction predicates
    1692             :         // MIs[0] Rd
    1693             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1694             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
    1695             :         // MIs[0] Rn
    1696             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1697             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
    1698             :         // MIs[0] imm
    1699             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1700             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
    1701             :         // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
    1702             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
    1703             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1704             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    1705             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    1706             :         GIR_EraseFromParent, /*InsnID*/0,
    1707             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1708             :         GIR_Done,
    1709             :       // Label 49: @2799
    1710             :       GIM_Try, /*On fail goto*//*Label 50*/ 2931,
    1711             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1712             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1713             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1714             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1715             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1716             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1717             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1718             :         // No instruction predicates
    1719             :         // MIs[0] Rd
    1720             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1721             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1722             :         // MIs[0] Ra
    1723             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1724             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    1725             :         // MIs[0] Operand 2
    1726             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1727             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1728             :         // MIs[1] Operand 0
    1729             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1730             :         // MIs[1] Operand 1
    1731             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1732             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    1733             :         // MIs[2] Operand 0
    1734             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1735             :         // MIs[2] Rn
    1736             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1737             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1738             :         // MIs[1] C
    1739             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1740             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    1741             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
    1742             :         // MIs[3] Operand 0
    1743             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1744             :         // MIs[3] Operand 1
    1745             :         // No operand predicates
    1746             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1747             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1748             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1749             :         // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    1750             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    1751             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    1752             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    1753             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    1754             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    1755             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    1756             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1757             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1758             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    1759             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    1760             :         GIR_EraseFromParent, /*InsnID*/0,
    1761             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1762             :         GIR_Done,
    1763             :       // Label 50: @2931
    1764             :       GIM_Try, /*On fail goto*//*Label 51*/ 3063,
    1765             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1766             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1767             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1768             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1769             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1770             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1771             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1772             :         // No instruction predicates
    1773             :         // MIs[0] Rd
    1774             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1775             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1776             :         // MIs[0] Ra
    1777             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1778             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    1779             :         // MIs[0] Operand 2
    1780             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1781             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1782             :         // MIs[1] Operand 0
    1783             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1784             :         // MIs[1] Operand 1
    1785             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1786             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    1787             :         // MIs[2] Operand 0
    1788             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1789             :         // MIs[2] Rn
    1790             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1791             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1792             :         // MIs[1] C
    1793             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1794             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    1795             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
    1796             :         // MIs[3] Operand 0
    1797             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1798             :         // MIs[3] Operand 1
    1799             :         // No operand predicates
    1800             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1801             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1802             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1803             :         // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    1804             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    1805             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    1806             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    1807             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    1808             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    1809             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    1810             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1811             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1812             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    1813             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    1814             :         GIR_EraseFromParent, /*InsnID*/0,
    1815             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1816             :         GIR_Done,
    1817             :       // Label 51: @3063
    1818             :       GIM_Reject,
    1819             :       GIR_Done,
    1820             :     // Label 43: @3065
    1821             :     GIM_Try, /*On fail goto*//*Label 52*/ 3336,
    1822             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    1823             :       GIM_Try, /*On fail goto*//*Label 53*/ 3202,
    1824             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1825             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1826             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1827             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1828             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1829             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1830             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1831             :         // No instruction predicates
    1832             :         // MIs[0] Rd
    1833             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1834             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1835             :         // MIs[0] Ra
    1836             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1837             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    1838             :         // MIs[0] Operand 2
    1839             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1840             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1841             :         // MIs[1] Operand 0
    1842             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1843             :         // MIs[1] Operand 1
    1844             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1845             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    1846             :         // MIs[2] Operand 0
    1847             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1848             :         // MIs[2] Rn
    1849             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1850             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1851             :         // MIs[1] C
    1852             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1853             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    1854             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
    1855             :         // MIs[3] Operand 0
    1856             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1857             :         // MIs[3] Operand 1
    1858             :         // No operand predicates
    1859             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1860             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1861             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1862             :         // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    1863             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    1864             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    1865             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    1866             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    1867             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    1868             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
    1869             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1870             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1871             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    1872             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    1873             :         GIR_EraseFromParent, /*InsnID*/0,
    1874             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1875             :         GIR_Done,
    1876             :       // Label 53: @3202
    1877             :       GIM_Try, /*On fail goto*//*Label 54*/ 3334,
    1878             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1879             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1880             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1881             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1882             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1883             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1884             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1885             :         // No instruction predicates
    1886             :         // MIs[0] Rd
    1887             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1888             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1889             :         // MIs[0] Ra
    1890             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1891             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    1892             :         // MIs[0] Operand 2
    1893             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1894             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1895             :         // MIs[1] Operand 0
    1896             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1897             :         // MIs[1] Operand 1
    1898             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1899             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    1900             :         // MIs[2] Operand 0
    1901             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1902             :         // MIs[2] Rn
    1903             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1904             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1905             :         // MIs[1] C
    1906             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1907             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
    1908             :         GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
    1909             :         // MIs[3] Operand 0
    1910             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1911             :         // MIs[3] Operand 1
    1912             :         // No operand predicates
    1913             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1914             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1915             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1916             :         // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
    1917             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    1918             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    1919             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    1920             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
    1921             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    1922             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
    1923             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1924             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1925             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    1926             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    1927             :         GIR_EraseFromParent, /*InsnID*/0,
    1928             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1929             :         GIR_Done,
    1930             :       // Label 54: @3334
    1931             :       GIM_Reject,
    1932             :       GIR_Done,
    1933             :     // Label 52: @3336
    1934             :     GIM_Try, /*On fail goto*//*Label 55*/ 3827,
    1935             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
    1936             :       GIM_Try, /*On fail goto*//*Label 56*/ 3462,
    1937             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1938             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1939             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1940             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1941             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1942             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1943             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1944             :         // No instruction predicates
    1945             :         // MIs[0] Rd
    1946             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1947             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1948             :         // MIs[0] Operand 1
    1949             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1950             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    1951             :         // MIs[1] Operand 0
    1952             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1953             :         // MIs[1] Operand 1
    1954             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1955             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    1956             :         // MIs[2] Operand 0
    1957             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1958             :         // MIs[2] Rn
    1959             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1960             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1961             :         // MIs[1] Operand 2
    1962             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    1963             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
    1964             :         // MIs[3] Operand 0
    1965             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    1966             :         // MIs[3] Rm
    1967             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    1968             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    1969             :         // MIs[0] Ra
    1970             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1971             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    1972             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    1973             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    1974             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    1975             :         // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    1976             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    1977             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1978             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    1979             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    1980             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
    1981             :         GIR_EraseFromParent, /*InsnID*/0,
    1982             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1983             :         GIR_Done,
    1984             :       // Label 56: @3462
    1985             :       GIM_Try, /*On fail goto*//*Label 57*/ 3583,
    1986             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    1987             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1988             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    1989             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    1990             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1991             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    1992             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    1993             :         // No instruction predicates
    1994             :         // MIs[0] Rd
    1995             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1996             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    1997             :         // MIs[0] Operand 1
    1998             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1999             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2000             :         // MIs[1] Operand 0
    2001             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2002             :         // MIs[1] Operand 1
    2003             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2004             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2005             :         // MIs[2] Operand 0
    2006             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2007             :         // MIs[2] Rn
    2008             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2009             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2010             :         // MIs[1] Operand 2
    2011             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2012             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
    2013             :         // MIs[3] Operand 0
    2014             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2015             :         // MIs[3] Rm
    2016             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2017             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2018             :         // MIs[0] Ra
    2019             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2020             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    2021             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2022             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2023             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2024             :         // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2025             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    2026             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2027             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2028             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2029             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
    2030             :         GIR_EraseFromParent, /*InsnID*/0,
    2031             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2032             :         GIR_Done,
    2033             :       // Label 57: @3583
    2034             :       GIM_Try, /*On fail goto*//*Label 58*/ 3704,
    2035             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2036             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2037             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2038             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2039             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2040             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2041             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2042             :         // No instruction predicates
    2043             :         // MIs[0] Rd
    2044             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2045             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2046             :         // MIs[0] Ra
    2047             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2048             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2049             :         // MIs[0] Operand 2
    2050             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2051             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2052             :         // MIs[1] Operand 0
    2053             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2054             :         // MIs[1] Operand 1
    2055             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2056             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    2057             :         // MIs[2] Operand 0
    2058             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2059             :         // MIs[2] Rn
    2060             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2061             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2062             :         // MIs[1] Operand 2
    2063             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2064             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
    2065             :         // MIs[3] Operand 0
    2066             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2067             :         // MIs[3] Rm
    2068             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2069             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2070             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2071             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2072             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2073             :         // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2074             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    2075             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2076             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2077             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2078             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2079             :         GIR_EraseFromParent, /*InsnID*/0,
    2080             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2081             :         GIR_Done,
    2082             :       // Label 58: @3704
    2083             :       GIM_Try, /*On fail goto*//*Label 59*/ 3825,
    2084             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2085             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2086             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2087             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2088             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2089             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2090             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2091             :         // No instruction predicates
    2092             :         // MIs[0] Rd
    2093             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2094             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2095             :         // MIs[0] Ra
    2096             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2097             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2098             :         // MIs[0] Operand 2
    2099             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2100             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2101             :         // MIs[1] Operand 0
    2102             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2103             :         // MIs[1] Operand 1
    2104             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2105             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2106             :         // MIs[2] Operand 0
    2107             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2108             :         // MIs[2] Rn
    2109             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2110             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2111             :         // MIs[1] Operand 2
    2112             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2113             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
    2114             :         // MIs[3] Operand 0
    2115             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2116             :         // MIs[3] Rm
    2117             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2118             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2119             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2120             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2121             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2122             :         // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2123             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    2124             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2125             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2126             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2127             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2128             :         GIR_EraseFromParent, /*InsnID*/0,
    2129             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2130             :         GIR_Done,
    2131             :       // Label 59: @3825
    2132             :       GIM_Reject,
    2133             :       GIR_Done,
    2134             :     // Label 55: @3827
    2135             :     GIM_Try, /*On fail goto*//*Label 60*/ 3966,
    2136             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ASHR,
    2137             :       GIM_Try, /*On fail goto*//*Label 61*/ 3898,
    2138             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2139             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2140             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2141             :         // No instruction predicates
    2142             :         // MIs[0] Rd
    2143             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2144             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    2145             :         // MIs[0] Rn
    2146             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    2147             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2148             :         // MIs[0] imm
    2149             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2150             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2151             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
    2152             :         // MIs[1] Operand 0
    2153             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2154             :         // MIs[1] Operand 1
    2155             :         // No operand predicates
    2156             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2157             :         // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
    2158             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMWri,
    2159             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2160             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    2161             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    2162             :         GIR_AddImm, /*InsnID*/0, /*Imm*/31,
    2163             :         GIR_EraseFromParent, /*InsnID*/0,
    2164             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2165             :         GIR_Done,
    2166             :       // Label 61: @3898
    2167             :       GIM_Try, /*On fail goto*//*Label 62*/ 3964,
    2168             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2169             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2170             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2171             :         // No instruction predicates
    2172             :         // MIs[0] Rd
    2173             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2174             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2175             :         // MIs[0] Rn
    2176             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2177             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2178             :         // MIs[0] imm
    2179             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2180             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2181             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63,
    2182             :         // MIs[1] Operand 0
    2183             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2184             :         // MIs[1] Operand 1
    2185             :         // No operand predicates
    2186             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2187             :         // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] })
    2188             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri,
    2189             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2190             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    2191             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    2192             :         GIR_AddImm, /*InsnID*/0, /*Imm*/63,
    2193             :         GIR_EraseFromParent, /*InsnID*/0,
    2194             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2195             :         GIR_Done,
    2196             :       // Label 62: @3964
    2197             :       GIM_Reject,
    2198             :       GIR_Done,
    2199             :     // Label 60: @3966
    2200             :     GIM_Try, /*On fail goto*//*Label 63*/ 4215,
    2201             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    2202             :       GIM_Try, /*On fail goto*//*Label 64*/ 4092,
    2203             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2204             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2205             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2206             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2207             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2208             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2209             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2210             :         // No instruction predicates
    2211             :         // MIs[0] Rd
    2212             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2213             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2214             :         // MIs[0] Ra
    2215             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2216             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2217             :         // MIs[0] Operand 2
    2218             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2219             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2220             :         // MIs[1] Operand 0
    2221             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2222             :         // MIs[1] Operand 1
    2223             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2224             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    2225             :         // MIs[2] Operand 0
    2226             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2227             :         // MIs[2] Rn
    2228             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2229             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2230             :         // MIs[1] Operand 2
    2231             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2232             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
    2233             :         // MIs[3] Operand 0
    2234             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2235             :         // MIs[3] Rm
    2236             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2237             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2238             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2239             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2240             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2241             :         // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2242             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
    2243             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2244             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2245             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2246             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2247             :         GIR_EraseFromParent, /*InsnID*/0,
    2248             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2249             :         GIR_Done,
    2250             :       // Label 64: @4092
    2251             :       GIM_Try, /*On fail goto*//*Label 65*/ 4213,
    2252             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2253             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2254             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    2255             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    2256             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2257             :         GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
    2258             :         GIM_CheckNumOperands, /*MI*/3, /*Expected*/2,
    2259             :         // No instruction predicates
    2260             :         // MIs[0] Rd
    2261             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2262             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2263             :         // MIs[0] Ra
    2264             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    2265             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    2266             :         // MIs[0] Operand 2
    2267             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2268             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    2269             :         // MIs[1] Operand 0
    2270             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2271             :         // MIs[1] Operand 1
    2272             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    2273             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    2274             :         // MIs[2] Operand 0
    2275             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2276             :         // MIs[2] Rn
    2277             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    2278             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2279             :         // MIs[1] Operand 2
    2280             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    2281             :         GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
    2282             :         // MIs[3] Operand 0
    2283             :         GIM_CheckType, /*MI*/3, /*Op*/0, /*Type*/GILLT_s64,
    2284             :         // MIs[3] Rm
    2285             :         GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
    2286             :         GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    2287             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2288             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2289             :         GIM_CheckIsSafeToFold, /*InsnID*/3,
    2290             :         // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
    2291             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
    2292             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2293             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
    2294             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
    2295             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
    2296             :         GIR_EraseFromParent, /*InsnID*/0,
    2297             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2298             :         GIR_Done,
    2299             :       // Label 65: @4213
    2300             :       GIM_Reject,
    2301             :       GIR_Done,
    2302             :     // Label 63: @4215
    2303             :     GIM_Try, /*On fail goto*//*Label 66*/ 4572,
    2304             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXT,
    2305             :       GIM_Try, /*On fail goto*//*Label 67*/ 4290,
    2306             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    2307             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2308             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2309             :         // No instruction predicates
    2310             :         // MIs[0] Rt
    2311             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2312             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    2313             :         // MIs[0] Operand 1
    2314             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    2315             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    2316             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    2317             :         // MIs[1] Operand 0
    2318             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
    2319             :         // MIs[1] Operand 1
    2320             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    2321             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    2322             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2323             :         // (sext:{ *:[i32] } (ld:{ *:[i16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    2324             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHWi,
    2325             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    2326             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    2327             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    2328             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    2329             :         GIR_EraseFromParent, /*InsnID*/0,
    2330             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2331             :         GIR_Done,
    2332             :       // Label 67: @4290
    2333             :       GIM_Try, /*On fail goto*//*Label 68*/ 4360,
    2334             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    2335             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2336             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2337             :         // No instruction predicates
    2338             :         // MIs[0] Rt
    2339             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2340             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2341             :         // MIs[0] Operand 1
    2342             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    2343             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    2344             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    2345             :         // MIs[1] Operand 0
    2346             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
    2347             :         // MIs[1] Operand 1
    2348             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    2349             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    2350             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2351             :         // (sext:{ *:[i64] } (ld:{ *:[i16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    2352             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHXi,
    2353             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    2354             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    2355             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    2356             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    2357             :         GIR_EraseFromParent, /*InsnID*/0,
    2358             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2359             :         GIR_Done,
    2360             :       // Label 68: @4360
    2361             :       GIM_Try, /*On fail goto*//*Label 69*/ 4430,
    2362             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    2363             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2364             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2365             :         // No instruction predicates
    2366             :         // MIs[0] Rt
    2367             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2368             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    2369             :         // MIs[0] Operand 1
    2370             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
    2371             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    2372             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    2373             :         // MIs[1] Operand 0
    2374             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
    2375             :         // MIs[1] Operand 1
    2376             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    2377             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    2378             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2379             :         // (sext:{ *:[i32] } (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    2380             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBWi,
    2381             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    2382             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    2383             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    2384             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    2385             :         GIR_EraseFromParent, /*InsnID*/0,
    2386             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2387             :         GIR_Done,
    2388             :       // Label 69: @4430
    2389             :       GIM_Try, /*On fail goto*//*Label 70*/ 4500,
    2390             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    2391             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2392             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2393             :         // No instruction predicates
    2394             :         // MIs[0] Rt
    2395             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2396             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2397             :         // MIs[0] Operand 1
    2398             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
    2399             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    2400             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    2401             :         // MIs[1] Operand 0
    2402             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
    2403             :         // MIs[1] Operand 1
    2404             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    2405             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    2406             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2407             :         // (sext:{ *:[i64] } (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    2408             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBXi,
    2409             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    2410             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    2411             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    2412             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    2413             :         GIR_EraseFromParent, /*InsnID*/0,
    2414             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2415             :         GIR_Done,
    2416             :       // Label 70: @4500
    2417             :       GIM_Try, /*On fail goto*//*Label 71*/ 4570,
    2418             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    2419             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2420             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2421             :         // No instruction predicates
    2422             :         // MIs[0] Rt
    2423             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2424             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    2425             :         // MIs[0] Operand 1
    2426             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    2427             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    2428             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    2429             :         // MIs[1] Operand 0
    2430             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    2431             :         // MIs[1] Operand 1
    2432             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    2433             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    2434             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2435             :         // (sext:{ *:[i64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    2436             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSWi,
    2437             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    2438             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    2439             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    2440             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    2441             :         GIR_EraseFromParent, /*InsnID*/0,
    2442             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2443             :         GIR_Done,
    2444             :       // Label 71: @4570
    2445             :       GIM_Reject,
    2446             :       GIR_Done,
    2447             :     // Label 66: @4572
    2448             :     GIM_Try, /*On fail goto*//*Label 72*/ 4719,
    2449             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT,
    2450             :       GIM_Try, /*On fail goto*//*Label 73*/ 4647,
    2451             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    2452             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2453             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2454             :         // No instruction predicates
    2455             :         // MIs[0] Rt
    2456             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2457             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    2458             :         // MIs[0] Operand 1
    2459             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    2460             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    2461             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    2462             :         // MIs[1] Operand 0
    2463             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
    2464             :         // MIs[1] Operand 1
    2465             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    2466             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    2467             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2468             :         // (zext:{ *:[i32] } (ld:{ *:[i16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    2469             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
    2470             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    2471             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    2472             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    2473             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    2474             :         GIR_EraseFromParent, /*InsnID*/0,
    2475             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2476             :         GIR_Done,
    2477             :       // Label 73: @4647
    2478             :       GIM_Try, /*On fail goto*//*Label 74*/ 4717,
    2479             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    2480             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    2481             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2482             :         // No instruction predicates
    2483             :         // MIs[0] Rt
    2484             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2485             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    2486             :         // MIs[0] Operand 1
    2487             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
    2488             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    2489             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    2490             :         // MIs[1] Operand 0
    2491             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
    2492             :         // MIs[1] Operand 1
    2493             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    2494             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    2495             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2496             :         // (zext:{ *:[i32] } (ld:{ *:[i8] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    2497             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    2498             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    2499             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    2500             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    2501             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    2502             :         GIR_EraseFromParent, /*InsnID*/0,
    2503             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2504             :         GIR_Done,
    2505             :       // Label 74: @4717
    2506             :       GIM_Reject,
    2507             :       GIR_Done,
    2508             :     // Label 72: @4719
    2509             :     GIM_Try, /*On fail goto*//*Label 75*/ 6788,
    2510             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2511             :       GIM_Try, /*On fail goto*//*Label 76*/ 4829,
    2512             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
    2513             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2514             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2515             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
    2516             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2517             :         // No instruction predicates
    2518             :         // MIs[0] dst
    2519             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    2520             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2521             :         // MIs[0] Operand 1
    2522             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane,
    2523             :         // MIs[0] Vd
    2524             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    2525             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2526             :         // MIs[0] idx
    2527             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2528             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2529             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB,
    2530             :         // MIs[1] Operand 0
    2531             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2532             :         // MIs[1] Operand 1
    2533             :         // No operand predicates
    2534             :         // MIs[0] Vs
    2535             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
    2536             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID,
    2537             :         // MIs[0] idx2
    2538             :         GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
    2539             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    2540             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB,
    2541             :         // MIs[2] Operand 0
    2542             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2543             :         // MIs[2] Operand 1
    2544             :         // No operand predicates
    2545             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2546             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2547             :         // (intrinsic_wo_chain:{ *:[v16i8] } 346:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)
    2548             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi8lane,
    2549             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2550             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
    2551             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
    2552             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs
    2553             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
    2554             :         GIR_EraseFromParent, /*InsnID*/0,
    2555             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2556             :         GIR_Done,
    2557             :       // Label 76: @4829
    2558             :       GIM_Try, /*On fail goto*//*Label 77*/ 4934,
    2559             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
    2560             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2561             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2562             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
    2563             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2564             :         // No instruction predicates
    2565             :         // MIs[0] dst
    2566             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    2567             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2568             :         // MIs[0] Operand 1
    2569             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane,
    2570             :         // MIs[0] Vd
    2571             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    2572             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2573             :         // MIs[0] idx
    2574             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2575             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2576             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH,
    2577             :         // MIs[1] Operand 0
    2578             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2579             :         // MIs[1] Operand 1
    2580             :         // No operand predicates
    2581             :         // MIs[0] Vs
    2582             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
    2583             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID,
    2584             :         // MIs[0] idx2
    2585             :         GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
    2586             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    2587             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH,
    2588             :         // MIs[2] Operand 0
    2589             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2590             :         // MIs[2] Operand 1
    2591             :         // No operand predicates
    2592             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2593             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2594             :         // (intrinsic_wo_chain:{ *:[v8i16] } 346:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)
    2595             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi16lane,
    2596             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2597             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
    2598             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
    2599             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs
    2600             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
    2601             :         GIR_EraseFromParent, /*InsnID*/0,
    2602             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2603             :         GIR_Done,
    2604             :       // Label 77: @4934
    2605             :       GIM_Try, /*On fail goto*//*Label 78*/ 5039,
    2606             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
    2607             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2608             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2609             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
    2610             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2611             :         // No instruction predicates
    2612             :         // MIs[0] dst
    2613             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2614             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2615             :         // MIs[0] Operand 1
    2616             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane,
    2617             :         // MIs[0] Vd
    2618             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2619             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2620             :         // MIs[0] idx
    2621             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2622             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2623             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS,
    2624             :         // MIs[1] Operand 0
    2625             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2626             :         // MIs[1] Operand 1
    2627             :         // No operand predicates
    2628             :         // MIs[0] Vs
    2629             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
    2630             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID,
    2631             :         // MIs[0] idx2
    2632             :         GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
    2633             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    2634             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS,
    2635             :         // MIs[2] Operand 0
    2636             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2637             :         // MIs[2] Operand 1
    2638             :         // No operand predicates
    2639             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2640             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2641             :         // (intrinsic_wo_chain:{ *:[v4i32] } 346:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)
    2642             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi32lane,
    2643             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2644             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
    2645             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
    2646             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs
    2647             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
    2648             :         GIR_EraseFromParent, /*InsnID*/0,
    2649             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2650             :         GIR_Done,
    2651             :       // Label 78: @5039
    2652             :       GIM_Try, /*On fail goto*//*Label 79*/ 5144,
    2653             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
    2654             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2655             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    2656             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
    2657             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    2658             :         // No instruction predicates
    2659             :         // MIs[0] dst
    2660             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    2661             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2662             :         // MIs[0] Operand 1
    2663             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane,
    2664             :         // MIs[0] Vd
    2665             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    2666             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2667             :         // MIs[0] idx
    2668             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2669             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    2670             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD,
    2671             :         // MIs[1] Operand 0
    2672             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    2673             :         // MIs[1] Operand 1
    2674             :         // No operand predicates
    2675             :         // MIs[0] Vs
    2676             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
    2677             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID,
    2678             :         // MIs[0] idx2
    2679             :         GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
    2680             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    2681             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD,
    2682             :         // MIs[2] Operand 0
    2683             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    2684             :         // MIs[2] Operand 1
    2685             :         // No operand predicates
    2686             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2687             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    2688             :         // (intrinsic_wo_chain:{ *:[v2i64] } 346:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)
    2689             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
    2690             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2691             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
    2692             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
    2693             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs
    2694             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
    2695             :         GIR_EraseFromParent, /*InsnID*/0,
    2696             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2697             :         GIR_Done,
    2698             :       // Label 79: @5144
    2699             :       GIM_Try, /*On fail goto*//*Label 80*/ 5235,
    2700             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2701             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2702             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2703             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2704             :         // No instruction predicates
    2705             :         // MIs[0] dst
    2706             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    2707             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    2708             :         // MIs[0] Operand 1
    2709             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    2710             :         // MIs[0] Rd
    2711             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    2712             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2713             :         // MIs[0] Operand 3
    2714             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    2715             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2716             :         // MIs[1] Operand 0
    2717             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    2718             :         // MIs[1] Operand 1
    2719             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2720             :         // MIs[1] Rn
    2721             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2722             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2723             :         // MIs[1] Rm
    2724             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2725             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    2726             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2727             :         // (intrinsic_wo_chain:{ *:[v4i16] } 280:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 285:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    2728             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16,
    2729             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2730             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2731             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2732             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2733             :         GIR_EraseFromParent, /*InsnID*/0,
    2734             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2735             :         GIR_Done,
    2736             :       // Label 80: @5235
    2737             :       GIM_Try, /*On fail goto*//*Label 81*/ 5326,
    2738             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2739             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2740             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2741             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2742             :         // No instruction predicates
    2743             :         // MIs[0] dst
    2744             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    2745             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2746             :         // MIs[0] Operand 1
    2747             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    2748             :         // MIs[0] Rd
    2749             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    2750             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2751             :         // MIs[0] Operand 3
    2752             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    2753             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2754             :         // MIs[1] Operand 0
    2755             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    2756             :         // MIs[1] Operand 1
    2757             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2758             :         // MIs[1] Rn
    2759             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    2760             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2761             :         // MIs[1] Rm
    2762             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    2763             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    2764             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2765             :         // (intrinsic_wo_chain:{ *:[v8i16] } 280:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 285:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
    2766             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16,
    2767             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2768             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2769             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2770             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2771             :         GIR_EraseFromParent, /*InsnID*/0,
    2772             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2773             :         GIR_Done,
    2774             :       // Label 81: @5326
    2775             :       GIM_Try, /*On fail goto*//*Label 82*/ 5417,
    2776             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2777             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2778             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2779             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2780             :         // No instruction predicates
    2781             :         // MIs[0] dst
    2782             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    2783             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    2784             :         // MIs[0] Operand 1
    2785             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    2786             :         // MIs[0] Rd
    2787             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    2788             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2789             :         // MIs[0] Operand 3
    2790             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    2791             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2792             :         // MIs[1] Operand 0
    2793             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    2794             :         // MIs[1] Operand 1
    2795             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2796             :         // MIs[1] Rn
    2797             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    2798             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2799             :         // MIs[1] Rm
    2800             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    2801             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    2802             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2803             :         // (intrinsic_wo_chain:{ *:[v2i32] } 280:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 285:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    2804             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32,
    2805             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2806             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2807             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2808             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2809             :         GIR_EraseFromParent, /*InsnID*/0,
    2810             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2811             :         GIR_Done,
    2812             :       // Label 82: @5417
    2813             :       GIM_Try, /*On fail goto*//*Label 83*/ 5508,
    2814             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2815             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2816             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2817             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2818             :         // No instruction predicates
    2819             :         // MIs[0] dst
    2820             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2821             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2822             :         // MIs[0] Operand 1
    2823             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    2824             :         // MIs[0] Rd
    2825             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2826             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2827             :         // MIs[0] Operand 3
    2828             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2829             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2830             :         // MIs[1] Operand 0
    2831             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    2832             :         // MIs[1] Operand 1
    2833             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2834             :         // MIs[1] Rn
    2835             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    2836             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2837             :         // MIs[1] Rm
    2838             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    2839             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    2840             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2841             :         // (intrinsic_wo_chain:{ *:[v4i32] } 280:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 285:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
    2842             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32,
    2843             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2844             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2845             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2846             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2847             :         GIR_EraseFromParent, /*InsnID*/0,
    2848             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2849             :         GIR_Done,
    2850             :       // Label 83: @5508
    2851             :       GIM_Try, /*On fail goto*//*Label 84*/ 5599,
    2852             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2853             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2854             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2855             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2856             :         // No instruction predicates
    2857             :         // MIs[0] dst
    2858             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    2859             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    2860             :         // MIs[0] Operand 1
    2861             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    2862             :         // MIs[0] Rd
    2863             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    2864             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2865             :         // MIs[0] Operand 3
    2866             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    2867             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2868             :         // MIs[1] Operand 0
    2869             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    2870             :         // MIs[1] Operand 1
    2871             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2872             :         // MIs[1] Rn
    2873             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2874             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2875             :         // MIs[1] Rm
    2876             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2877             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    2878             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2879             :         // (intrinsic_wo_chain:{ *:[v4i16] } 293:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 285:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    2880             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16,
    2881             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2882             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2883             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2884             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2885             :         GIR_EraseFromParent, /*InsnID*/0,
    2886             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2887             :         GIR_Done,
    2888             :       // Label 84: @5599
    2889             :       GIM_Try, /*On fail goto*//*Label 85*/ 5690,
    2890             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2891             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2892             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2893             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2894             :         // No instruction predicates
    2895             :         // MIs[0] dst
    2896             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    2897             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2898             :         // MIs[0] Operand 1
    2899             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    2900             :         // MIs[0] Rd
    2901             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    2902             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2903             :         // MIs[0] Operand 3
    2904             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    2905             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2906             :         // MIs[1] Operand 0
    2907             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    2908             :         // MIs[1] Operand 1
    2909             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2910             :         // MIs[1] Rn
    2911             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    2912             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2913             :         // MIs[1] Rm
    2914             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    2915             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    2916             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2917             :         // (intrinsic_wo_chain:{ *:[v8i16] } 293:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 285:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
    2918             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16,
    2919             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2920             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2921             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2922             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2923             :         GIR_EraseFromParent, /*InsnID*/0,
    2924             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2925             :         GIR_Done,
    2926             :       // Label 85: @5690
    2927             :       GIM_Try, /*On fail goto*//*Label 86*/ 5781,
    2928             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2929             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2930             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2931             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2932             :         // No instruction predicates
    2933             :         // MIs[0] dst
    2934             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    2935             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    2936             :         // MIs[0] Operand 1
    2937             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    2938             :         // MIs[0] Rd
    2939             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    2940             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2941             :         // MIs[0] Operand 3
    2942             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    2943             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2944             :         // MIs[1] Operand 0
    2945             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    2946             :         // MIs[1] Operand 1
    2947             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2948             :         // MIs[1] Rn
    2949             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    2950             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    2951             :         // MIs[1] Rm
    2952             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    2953             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    2954             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2955             :         // (intrinsic_wo_chain:{ *:[v2i32] } 293:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 285:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    2956             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32,
    2957             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2958             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2959             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2960             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2961             :         GIR_EraseFromParent, /*InsnID*/0,
    2962             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2963             :         GIR_Done,
    2964             :       // Label 86: @5781
    2965             :       GIM_Try, /*On fail goto*//*Label 87*/ 5872,
    2966             :         GIM_CheckFeatures, GIFBS_HasNEON_HasRDM,
    2967             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2968             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2969             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2970             :         // No instruction predicates
    2971             :         // MIs[0] dst
    2972             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2973             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    2974             :         // MIs[0] Operand 1
    2975             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    2976             :         // MIs[0] Rd
    2977             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2978             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2979             :         // MIs[0] Operand 3
    2980             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2981             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2982             :         // MIs[1] Operand 0
    2983             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    2984             :         // MIs[1] Operand 1
    2985             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    2986             :         // MIs[1] Rn
    2987             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    2988             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    2989             :         // MIs[1] Rm
    2990             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    2991             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    2992             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    2993             :         // (intrinsic_wo_chain:{ *:[v4i32] } 293:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 285:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
    2994             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32,
    2995             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2996             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    2997             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2998             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    2999             :         GIR_EraseFromParent, /*InsnID*/0,
    3000             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3001             :         GIR_Done,
    3002             :       // Label 87: @5872
    3003             :       GIM_Try, /*On fail goto*//*Label 88*/ 5963,
    3004             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3005             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3006             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3007             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3008             :         // No instruction predicates
    3009             :         // MIs[0] dst
    3010             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3011             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3012             :         // MIs[0] Operand 1
    3013             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3014             :         // MIs[0] Rd
    3015             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3016             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3017             :         // MIs[0] Operand 3
    3018             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    3019             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3020             :         // MIs[1] Operand 0
    3021             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    3022             :         // MIs[1] Operand 1
    3023             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull,
    3024             :         // MIs[1] Rn
    3025             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    3026             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3027             :         // MIs[1] Rm
    3028             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    3029             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3030             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3031             :         // (intrinsic_wo_chain:{ *:[v4i32] } 280:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 282:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    3032             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_v4i32,
    3033             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3034             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3035             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3036             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3037             :         GIR_EraseFromParent, /*InsnID*/0,
    3038             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3039             :         GIR_Done,
    3040             :       // Label 88: @5963
    3041             :       GIM_Try, /*On fail goto*//*Label 89*/ 6054,
    3042             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3043             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3044             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3045             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3046             :         // No instruction predicates
    3047             :         // MIs[0] dst
    3048             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    3049             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3050             :         // MIs[0] Operand 1
    3051             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3052             :         // MIs[0] Rd
    3053             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    3054             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3055             :         // MIs[0] Operand 3
    3056             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    3057             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3058             :         // MIs[1] Operand 0
    3059             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    3060             :         // MIs[1] Operand 1
    3061             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull,
    3062             :         // MIs[1] Rn
    3063             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    3064             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3065             :         // MIs[1] Rm
    3066             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    3067             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3068             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3069             :         // (intrinsic_wo_chain:{ *:[v2i64] } 280:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 282:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    3070             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_v2i64,
    3071             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3072             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3073             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3074             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3075             :         GIR_EraseFromParent, /*InsnID*/0,
    3076             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3077             :         GIR_Done,
    3078             :       // Label 89: @6054
    3079             :       GIM_Try, /*On fail goto*//*Label 90*/ 6145,
    3080             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3081             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3082             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3083             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3084             :         // No instruction predicates
    3085             :         // MIs[0] dst
    3086             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3087             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3088             :         // MIs[0] Operand 1
    3089             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3090             :         // MIs[0] Rd
    3091             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3092             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3093             :         // MIs[0] Operand 3
    3094             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    3095             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3096             :         // MIs[1] Operand 0
    3097             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    3098             :         // MIs[1] Operand 1
    3099             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull,
    3100             :         // MIs[1] Rn
    3101             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    3102             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3103             :         // MIs[1] Rm
    3104             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    3105             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3106             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3107             :         // (intrinsic_wo_chain:{ *:[v4i32] } 293:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 282:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    3108             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_v4i32,
    3109             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3110             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3111             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3112             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3113             :         GIR_EraseFromParent, /*InsnID*/0,
    3114             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3115             :         GIR_Done,
    3116             :       // Label 90: @6145
    3117             :       GIM_Try, /*On fail goto*//*Label 91*/ 6236,
    3118             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3119             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3120             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3121             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3122             :         // No instruction predicates
    3123             :         // MIs[0] dst
    3124             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    3125             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3126             :         // MIs[0] Operand 1
    3127             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3128             :         // MIs[0] Rd
    3129             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    3130             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3131             :         // MIs[0] Operand 3
    3132             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    3133             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3134             :         // MIs[1] Operand 0
    3135             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    3136             :         // MIs[1] Operand 1
    3137             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull,
    3138             :         // MIs[1] Rn
    3139             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    3140             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3141             :         // MIs[1] Rm
    3142             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    3143             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    3144             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3145             :         // (intrinsic_wo_chain:{ *:[v2i64] } 293:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 282:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    3146             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_v2i64,
    3147             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3148             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3149             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3150             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3151             :         GIR_EraseFromParent, /*InsnID*/0,
    3152             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3153             :         GIR_Done,
    3154             :       // Label 91: @6236
    3155             :       GIM_Try, /*On fail goto*//*Label 92*/ 6327,
    3156             :         GIM_CheckFeatures, GIFBS_HasRDM,
    3157             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3158             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3159             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3160             :         // No instruction predicates
    3161             :         // MIs[0] dst
    3162             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3163             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    3164             :         // MIs[0] Operand 1
    3165             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3166             :         // MIs[0] Rd
    3167             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3168             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3169             :         // MIs[0] Operand 3
    3170             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3171             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3172             :         // MIs[1] Operand 0
    3173             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3174             :         // MIs[1] Operand 1
    3175             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3176             :         // MIs[1] Rn
    3177             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3178             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3179             :         // MIs[1] Rm
    3180             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3181             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID,
    3182             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3183             :         // (intrinsic_wo_chain:{ *:[i32] } 280:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 285:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
    3184             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv1i32,
    3185             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3186             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3187             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3188             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3189             :         GIR_EraseFromParent, /*InsnID*/0,
    3190             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3191             :         GIR_Done,
    3192             :       // Label 92: @6327
    3193             :       GIM_Try, /*On fail goto*//*Label 93*/ 6418,
    3194             :         GIM_CheckFeatures, GIFBS_HasRDM,
    3195             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3196             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3197             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3198             :         // No instruction predicates
    3199             :         // MIs[0] dst
    3200             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3201             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    3202             :         // MIs[0] Operand 1
    3203             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3204             :         // MIs[0] Rd
    3205             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3206             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3207             :         // MIs[0] Operand 3
    3208             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3209             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3210             :         // MIs[1] Operand 0
    3211             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3212             :         // MIs[1] Operand 1
    3213             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh,
    3214             :         // MIs[1] Rn
    3215             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3216             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3217             :         // MIs[1] Rm
    3218             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3219             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID,
    3220             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3221             :         // (intrinsic_wo_chain:{ *:[i32] } 293:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 285:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
    3222             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv1i32,
    3223             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3224             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3225             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3226             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3227             :         GIR_EraseFromParent, /*InsnID*/0,
    3228             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3229             :         GIR_Done,
    3230             :       // Label 93: @6418
    3231             :       GIM_Try, /*On fail goto*//*Label 94*/ 6507,
    3232             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3233             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3234             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3235             :         // No instruction predicates
    3236             :         // MIs[0] dst
    3237             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3238             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    3239             :         // MIs[0] Operand 1
    3240             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd,
    3241             :         // MIs[0] Rd
    3242             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3243             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3244             :         // MIs[0] Operand 3
    3245             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    3246             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3247             :         // MIs[1] Operand 0
    3248             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3249             :         // MIs[1] Operand 1
    3250             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar,
    3251             :         // MIs[1] Rn
    3252             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3253             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3254             :         // MIs[1] Rm
    3255             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3256             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID,
    3257             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3258             :         // (intrinsic_wo_chain:{ *:[i64] } 280:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 283:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQDMLALi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
    3259             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALi32,
    3260             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3261             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3262             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3263             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3264             :         GIR_EraseFromParent, /*InsnID*/0,
    3265             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3266             :         GIR_Done,
    3267             :       // Label 94: @6507
    3268             :       GIM_Try, /*On fail goto*//*Label 95*/ 6596,
    3269             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3270             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3271             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3272             :         // No instruction predicates
    3273             :         // MIs[0] dst
    3274             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3275             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    3276             :         // MIs[0] Operand 1
    3277             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub,
    3278             :         // MIs[0] Rd
    3279             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3280             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    3281             :         // MIs[0] Operand 3
    3282             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    3283             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3284             :         // MIs[1] Operand 0
    3285             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3286             :         // MIs[1] Operand 1
    3287             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar,
    3288             :         // MIs[1] Rn
    3289             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3290             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    3291             :         // MIs[1] Rm
    3292             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3293             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID,
    3294             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3295             :         // (intrinsic_wo_chain:{ *:[i64] } 293:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 283:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQDMLSLi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
    3296             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLi32,
    3297             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    3298             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    3299             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3300             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    3301             :         GIR_EraseFromParent, /*InsnID*/0,
    3302             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3303             :         GIR_Done,
    3304             :       // Label 95: @6596
    3305             :       GIM_Try, /*On fail goto*//*Label 96*/ 6691,
    3306             :         GIM_CheckFeatures, GIFBS_HasFuseAES,
    3307             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3308             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3309             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3310             :         // No instruction predicates
    3311             :         // MIs[0] Rd
    3312             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    3313             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3314             :         // MIs[0] Operand 1
    3315             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc,
    3316             :         // MIs[0] Operand 2
    3317             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    3318             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3319             :         // MIs[1] Operand 0
    3320             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    3321             :         // MIs[1] Operand 1
    3322             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aese,
    3323             :         // MIs[1] src1
    3324             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    3325             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3326             :         // MIs[1] src2
    3327             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    3328             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    3329             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3330             :         // (intrinsic_wo_chain:{ *:[v16i8] } 186:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 184:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))  =>  (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
    3331             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
    3332             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESErr,
    3333             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3334             :         GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
    3335             :         GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
    3336             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3337             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrrTied,
    3338             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3339             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3340             :         GIR_EraseFromParent, /*InsnID*/0,
    3341             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3342             :         GIR_Done,
    3343             :       // Label 96: @6691
    3344             :       GIM_Try, /*On fail goto*//*Label 97*/ 6786,
    3345             :         GIM_CheckFeatures, GIFBS_HasFuseAES,
    3346             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3347             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3348             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3349             :         // No instruction predicates
    3350             :         // MIs[0] Rd
    3351             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    3352             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3353             :         // MIs[0] Operand 1
    3354             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc,
    3355             :         // MIs[0] Operand 2
    3356             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    3357             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3358             :         // MIs[1] Operand 0
    3359             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    3360             :         // MIs[1] Operand 1
    3361             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aesd,
    3362             :         // MIs[1] src1
    3363             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    3364             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    3365             :         // MIs[1] src2
    3366             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    3367             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    3368             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3369             :         // (intrinsic_wo_chain:{ *:[v16i8] } 185:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 183:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))  =>  (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
    3370             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
    3371             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESDrr,
    3372             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3373             :         GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
    3374             :         GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
    3375             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3376             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrrTied,
    3377             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3378             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3379             :         GIR_EraseFromParent, /*InsnID*/0,
    3380             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3381             :         GIR_Done,
    3382             :       // Label 97: @6786
    3383             :       GIM_Reject,
    3384             :       GIR_Done,
    3385             :     // Label 75: @6788
    3386             :     GIM_Try, /*On fail goto*//*Label 98*/ 7115,
    3387             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
    3388             :       GIM_Try, /*On fail goto*//*Label 99*/ 6873,
    3389             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3390             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3391             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3392             :         // No instruction predicates
    3393             :         // MIs[0] Rd
    3394             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3395             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3396             :         // MIs[0] Operand 1
    3397             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3398             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
    3399             :         // MIs[1] Operand 0
    3400             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3401             :         // MIs[1] Operand 1
    3402             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3403             :         GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
    3404             :         // MIs[1] Rn
    3405             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3406             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
    3407             :         // MIs[0] Rm
    3408             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3409             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
    3410             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3411             :         // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm)  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
    3412             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
    3413             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3414             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3415             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
    3416             :         GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
    3417             :         GIR_EraseFromParent, /*InsnID*/0,
    3418             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3419             :         GIR_Done,
    3420             :       // Label 99: @6873
    3421             :       GIM_Try, /*On fail goto*//*Label 100*/ 6953,
    3422             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3423             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3424             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3425             :         // No instruction predicates
    3426             :         // MIs[0] Rd
    3427             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3428             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3429             :         // MIs[0] Operand 1
    3430             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3431             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
    3432             :         // MIs[1] Operand 0
    3433             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3434             :         // MIs[1] Operand 1
    3435             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    3436             :         GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
    3437             :         // MIs[1] Rn
    3438             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    3439             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    3440             :         // MIs[0] Rm
    3441             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3442             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    3443             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3444             :         // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm)  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
    3445             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
    3446             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3447             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3448             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
    3449             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3450             :         GIR_EraseFromParent, /*InsnID*/0,
    3451             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3452             :         GIR_Done,
    3453             :       // Label 100: @6953
    3454             :       GIM_Try, /*On fail goto*//*Label 101*/ 7033,
    3455             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3456             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3457             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3458             :         // No instruction predicates
    3459             :         // MIs[0] Rd
    3460             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3461             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3462             :         // MIs[0] Rm
    3463             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3464             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    3465             :         // MIs[0] Operand 2
    3466             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3467             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
    3468             :         // MIs[1] Operand 0
    3469             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3470             :         // MIs[1] Operand 1
    3471             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3472             :         GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
    3473             :         // MIs[1] Rn
    3474             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3475             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
    3476             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3477             :         // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
    3478             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
    3479             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3480             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3481             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
    3482             :         GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
    3483             :         GIR_EraseFromParent, /*InsnID*/0,
    3484             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3485             :         GIR_Done,
    3486             :       // Label 101: @7033
    3487             :       GIM_Try, /*On fail goto*//*Label 102*/ 7113,
    3488             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3489             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3490             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3491             :         // No instruction predicates
    3492             :         // MIs[0] Rd
    3493             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3494             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3495             :         // MIs[0] Rm
    3496             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3497             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    3498             :         // MIs[0] Operand 2
    3499             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3500             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
    3501             :         // MIs[1] Operand 0
    3502             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3503             :         // MIs[1] Operand 1
    3504             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    3505             :         GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
    3506             :         // MIs[1] Rn
    3507             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    3508             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    3509             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3510             :         // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
    3511             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
    3512             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3513             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    3514             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
    3515             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3516             :         GIR_EraseFromParent, /*InsnID*/0,
    3517             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3518             :         GIR_Done,
    3519             :       // Label 102: @7113
    3520             :       GIM_Reject,
    3521             :       GIR_Done,
    3522             :     // Label 98: @7115
    3523             :     GIM_Try, /*On fail goto*//*Label 103*/ 7282,
    3524             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    3525             :       GIM_Try, /*On fail goto*//*Label 104*/ 7200,
    3526             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3527             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3528             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3529             :         // No instruction predicates
    3530             :         // MIs[0] Rd
    3531             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3532             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3533             :         // MIs[0] Operand 1
    3534             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3535             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
    3536             :         // MIs[0] Operand 2
    3537             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3538             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    3539             :         // MIs[1] Operand 0
    3540             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3541             :         // MIs[1] Rn
    3542             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3543             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    3544             :         // MIs[1] Rm
    3545             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3546             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
    3547             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3548             :         // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
    3549             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
    3550             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3551             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    3552             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
    3553             :         GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
    3554             :         GIR_EraseFromParent, /*InsnID*/0,
    3555             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3556             :         GIR_Done,
    3557             :       // Label 104: @7200
    3558             :       GIM_Try, /*On fail goto*//*Label 105*/ 7280,
    3559             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3560             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    3561             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    3562             :         // No instruction predicates
    3563             :         // MIs[0] Rd
    3564             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3565             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3566             :         // MIs[0] Operand 1
    3567             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3568             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
    3569             :         // MIs[0] Operand 2
    3570             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3571             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
    3572             :         // MIs[1] Operand 0
    3573             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3574             :         // MIs[1] Rn
    3575             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    3576             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
    3577             :         // MIs[1] Rm
    3578             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
    3579             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
    3580             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3581             :         // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
    3582             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
    3583             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3584             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    3585             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
    3586             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3587             :         GIR_EraseFromParent, /*InsnID*/0,
    3588             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3589             :         GIR_Done,
    3590             :       // Label 105: @7280
    3591             :       GIM_Reject,
    3592             :       GIR_Done,
    3593             :     // Label 103: @7282
    3594             :     GIM_Try, /*On fail goto*//*Label 106*/ 7709,
    3595             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ANYEXT,
    3596             :       GIM_Try, /*On fail goto*//*Label 107*/ 7357,
    3597             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3598             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3599             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3600             :         // No instruction predicates
    3601             :         // MIs[0] Rt
    3602             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3603             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3604             :         // MIs[0] Operand 1
    3605             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3606             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3607             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3608             :         // MIs[1] Operand 0
    3609             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
    3610             :         // MIs[1] Operand 1
    3611             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3612             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16,
    3613             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3614             :         // (anyext:{ *:[i32] } (ld:{ *:[i16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
    3615             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui,
    3616             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3617             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3618             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3619             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3620             :         GIR_EraseFromParent, /*InsnID*/0,
    3621             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3622             :         GIR_Done,
    3623             :       // Label 107: @7357
    3624             :       GIM_Try, /*On fail goto*//*Label 108*/ 7427,
    3625             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3626             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3627             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3628             :         // No instruction predicates
    3629             :         // MIs[0] Rt
    3630             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3631             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3632             :         // MIs[0] Operand 1
    3633             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
    3634             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3635             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3636             :         // MIs[1] Operand 0
    3637             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
    3638             :         // MIs[1] Operand 1
    3639             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3640             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
    3641             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3642             :         // (anyext:{ *:[i32] } (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
    3643             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
    3644             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3645             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3646             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3647             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3648             :         GIR_EraseFromParent, /*InsnID*/0,
    3649             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3650             :         GIR_Done,
    3651             :       // Label 108: @7427
    3652             :       GIM_Try, /*On fail goto*//*Label 109*/ 7497,
    3653             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3654             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3655             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3656             :         // No instruction predicates
    3657             :         // MIs[0] Rt
    3658             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3659             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3660             :         // MIs[0] Operand 1
    3661             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
    3662             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3663             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3664             :         // MIs[1] Operand 0
    3665             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s1,
    3666             :         // MIs[1] Operand 1
    3667             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3668             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
    3669             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3670             :         // (anyext:{ *:[i32] } (ld:{ *:[i1] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
    3671             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
    3672             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3673             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3674             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3675             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3676             :         GIR_EraseFromParent, /*InsnID*/0,
    3677             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3678             :         GIR_Done,
    3679             :       // Label 109: @7497
    3680             :       GIM_Try, /*On fail goto*//*Label 110*/ 7567,
    3681             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3682             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3683             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3684             :         // No instruction predicates
    3685             :         // MIs[0] Rt
    3686             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3687             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3688             :         // MIs[0] Operand 1
    3689             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3690             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3691             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3692             :         // MIs[1] Operand 0
    3693             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
    3694             :         // MIs[1] Operand 1
    3695             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3696             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    3697             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3698             :         // (anyext:{ *:[i32] } (ld:{ *:[i16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    3699             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
    3700             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3701             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3702             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3703             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3704             :         GIR_EraseFromParent, /*InsnID*/0,
    3705             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3706             :         GIR_Done,
    3707             :       // Label 110: @7567
    3708             :       GIM_Try, /*On fail goto*//*Label 111*/ 7637,
    3709             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3710             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3711             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3712             :         // No instruction predicates
    3713             :         // MIs[0] Rt
    3714             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3715             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3716             :         // MIs[0] Operand 1
    3717             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
    3718             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3719             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3720             :         // MIs[1] Operand 0
    3721             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
    3722             :         // MIs[1] Operand 1
    3723             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3724             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    3725             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3726             :         // (anyext:{ *:[i32] } (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    3727             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    3728             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3729             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3730             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3731             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3732             :         GIR_EraseFromParent, /*InsnID*/0,
    3733             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3734             :         GIR_Done,
    3735             :       // Label 111: @7637
    3736             :       GIM_Try, /*On fail goto*//*Label 112*/ 7707,
    3737             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3738             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3739             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3740             :         // No instruction predicates
    3741             :         // MIs[0] Rt
    3742             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3743             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3744             :         // MIs[0] Operand 1
    3745             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
    3746             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3747             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3748             :         // MIs[1] Operand 0
    3749             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s1,
    3750             :         // MIs[1] Operand 1
    3751             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3752             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    3753             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3754             :         // (anyext:{ *:[i32] } (ld:{ *:[i1] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    3755             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    3756             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3757             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3758             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3759             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3760             :         GIR_EraseFromParent, /*InsnID*/0,
    3761             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3762             :         GIR_Done,
    3763             :       // Label 112: @7707
    3764             :       GIM_Reject,
    3765             :       GIR_Done,
    3766             :     // Label 106: @7709
    3767             :     GIM_Try, /*On fail goto*//*Label 113*/ 7996,
    3768             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT,
    3769             :       GIM_Try, /*On fail goto*//*Label 114*/ 7784,
    3770             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3771             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3772             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3773             :         // No instruction predicates
    3774             :         // MIs[0] Rt
    3775             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3776             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3777             :         // MIs[0] Operand 1
    3778             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
    3779             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3780             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3781             :         // MIs[1] Operand 0
    3782             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s1,
    3783             :         // MIs[1] Operand 1
    3784             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3785             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8,
    3786             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3787             :         // (zext:{ *:[i32] } (ld:{ *:[i1] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>>)  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
    3788             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui,
    3789             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3790             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3791             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3792             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3793             :         GIR_EraseFromParent, /*InsnID*/0,
    3794             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3795             :         GIR_Done,
    3796             :       // Label 114: @7784
    3797             :       GIM_Try, /*On fail goto*//*Label 115*/ 7854,
    3798             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3799             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3800             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3801             :         // No instruction predicates
    3802             :         // MIs[0] Rt
    3803             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3804             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3805             :         // MIs[0] Operand 1
    3806             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3807             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3808             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3809             :         // MIs[1] Operand 0
    3810             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s16,
    3811             :         // MIs[1] Operand 1
    3812             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3813             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    3814             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3815             :         // (zext:{ *:[i32] } (ld:{ *:[i16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    3816             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi,
    3817             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3818             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3819             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3820             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3821             :         GIR_EraseFromParent, /*InsnID*/0,
    3822             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3823             :         GIR_Done,
    3824             :       // Label 115: @7854
    3825             :       GIM_Try, /*On fail goto*//*Label 116*/ 7924,
    3826             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3827             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3828             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3829             :         // No instruction predicates
    3830             :         // MIs[0] Rt
    3831             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3832             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3833             :         // MIs[0] Operand 1
    3834             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
    3835             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3836             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3837             :         // MIs[1] Operand 0
    3838             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s8,
    3839             :         // MIs[1] Operand 1
    3840             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3841             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    3842             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3843             :         // (zext:{ *:[i32] } (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    3844             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    3845             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3846             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3847             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3848             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3849             :         GIR_EraseFromParent, /*InsnID*/0,
    3850             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3851             :         GIR_Done,
    3852             :       // Label 116: @7924
    3853             :       GIM_Try, /*On fail goto*//*Label 117*/ 7994,
    3854             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3855             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3856             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3857             :         // No instruction predicates
    3858             :         // MIs[0] Rt
    3859             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3860             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    3861             :         // MIs[0] Operand 1
    3862             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
    3863             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD,
    3864             :         GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    3865             :         // MIs[1] Operand 0
    3866             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s1,
    3867             :         // MIs[1] Operand 1
    3868             :         GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
    3869             :         GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8,
    3870             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3871             :         // (zext:{ *:[i32] } (ld:{ *:[i1] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>>)  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    3872             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi,
    3873             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    3874             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    3875             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    3876             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    3877             :         GIR_EraseFromParent, /*InsnID*/0,
    3878             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3879             :         GIR_Done,
    3880             :       // Label 117: @7994
    3881             :       GIM_Reject,
    3882             :       GIR_Done,
    3883             :     // Label 113: @7996
    3884             :     GIM_Try, /*On fail goto*//*Label 118*/ 8209,
    3885             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
    3886             :       GIM_Try, /*On fail goto*//*Label 119*/ 8104,
    3887             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3888             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3889             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3890             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    3891             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    3892             :         // No instruction predicates
    3893             :         // MIs[0] Rd
    3894             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3895             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3896             :         // MIs[0] Operand 1
    3897             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3898             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
    3899             :         // MIs[1] Operand 0
    3900             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3901             :         // MIs[1] Rn
    3902             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3903             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    3904             :         // MIs[0] C
    3905             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3906             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    3907             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
    3908             :         // MIs[2] Operand 0
    3909             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    3910             :         // MIs[2] Operand 1
    3911             :         // No operand predicates
    3912             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3913             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    3914             :         // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
    3915             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    3916             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    3917             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3918             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C
    3919             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3920             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    3921             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3922             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    3923             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3924             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3925             :         GIR_EraseFromParent, /*InsnID*/0,
    3926             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3927             :         GIR_Done,
    3928             :       // Label 119: @8104
    3929             :       GIM_Try, /*On fail goto*//*Label 120*/ 8207,
    3930             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3931             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3932             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3933             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    3934             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    3935             :         // No instruction predicates
    3936             :         // MIs[0] Rd
    3937             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3938             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    3939             :         // MIs[0] Operand 1
    3940             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3941             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    3942             :         // MIs[1] Operand 0
    3943             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    3944             :         // MIs[1] Rn
    3945             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    3946             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    3947             :         // MIs[0] C
    3948             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3949             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
    3950             :         GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
    3951             :         // MIs[2] Operand 0
    3952             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    3953             :         // MIs[2] Operand 1
    3954             :         // No operand predicates
    3955             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    3956             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    3957             :         // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
    3958             :         GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
    3959             :         GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
    3960             :         GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3961             :         GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C
    3962             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3963             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    3964             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3965             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    3966             :         GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3967             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    3968             :         GIR_EraseFromParent, /*InsnID*/0,
    3969             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3970             :         GIR_Done,
    3971             :       // Label 120: @8207
    3972             :       GIM_Reject,
    3973             :       GIR_Done,
    3974             :     // Label 118: @8209
    3975             :     GIM_Try, /*On fail goto*//*Label 121*/ 9500,
    3976             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
    3977             :       GIM_Try, /*On fail goto*//*Label 122*/ 8321,
    3978             :         GIM_CheckFeatures, GIFBS_HasNEON,
    3979             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    3980             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    3981             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3982             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    3983             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    3984             :         // No instruction predicates
    3985             :         // MIs[0] dst
    3986             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    3987             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    3988             :         // MIs[0] Operand 1
    3989             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    3990             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    3991             :         // MIs[1] Operand 0
    3992             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    3993             :         // MIs[1] Operand 1
    3994             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
    3995             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    3996             :         // MIs[2] Operand 0
    3997             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v8s8,
    3998             :         // MIs[2] Operand 1
    3999             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4000             :         // MIs[2] Rn
    4001             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
    4002             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4003             :         // MIs[2] Rm
    4004             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
    4005             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4006             :         // MIs[0] Rd
    4007             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    4008             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4009             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4010             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4011             :         // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 262:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    4012             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
    4013             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4014             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4015             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4016             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4017             :         GIR_EraseFromParent, /*InsnID*/0,
    4018             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4019             :         GIR_Done,
    4020             :       // Label 122: @8321
    4021             :       GIM_Try, /*On fail goto*//*Label 123*/ 8428,
    4022             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4023             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4024             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4025             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4026             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4027             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4028             :         // No instruction predicates
    4029             :         // MIs[0] dst
    4030             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    4031             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4032             :         // MIs[0] Operand 1
    4033             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    4034             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4035             :         // MIs[1] Operand 0
    4036             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    4037             :         // MIs[1] Operand 1
    4038             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
    4039             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4040             :         // MIs[2] Operand 0
    4041             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v4s16,
    4042             :         // MIs[2] Operand 1
    4043             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4044             :         // MIs[2] Rn
    4045             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
    4046             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4047             :         // MIs[2] Rm
    4048             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
    4049             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4050             :         // MIs[0] Rd
    4051             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    4052             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4053             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4054             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4055             :         // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 262:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    4056             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
    4057             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4058             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4059             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4060             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4061             :         GIR_EraseFromParent, /*InsnID*/0,
    4062             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4063             :         GIR_Done,
    4064             :       // Label 123: @8428
    4065             :       GIM_Try, /*On fail goto*//*Label 124*/ 8535,
    4066             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4067             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4068             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4069             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4070             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4071             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4072             :         // No instruction predicates
    4073             :         // MIs[0] dst
    4074             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4075             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4076             :         // MIs[0] Operand 1
    4077             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    4078             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4079             :         // MIs[1] Operand 0
    4080             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    4081             :         // MIs[1] Operand 1
    4082             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    4083             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4084             :         // MIs[2] Operand 0
    4085             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v2s32,
    4086             :         // MIs[2] Operand 1
    4087             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4088             :         // MIs[2] Rn
    4089             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
    4090             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4091             :         // MIs[2] Rm
    4092             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
    4093             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4094             :         // MIs[0] Rd
    4095             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    4096             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4097             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4098             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4099             :         // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 262:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    4100             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
    4101             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4102             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4103             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4104             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4105             :         GIR_EraseFromParent, /*InsnID*/0,
    4106             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4107             :         GIR_Done,
    4108             :       // Label 124: @8535
    4109             :       GIM_Try, /*On fail goto*//*Label 125*/ 8642,
    4110             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4111             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4112             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4113             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4114             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4115             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4116             :         // No instruction predicates
    4117             :         // MIs[0] dst
    4118             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    4119             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4120             :         // MIs[0] Operand 1
    4121             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    4122             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4123             :         // MIs[1] Operand 0
    4124             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    4125             :         // MIs[1] Operand 1
    4126             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
    4127             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4128             :         // MIs[2] Operand 0
    4129             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v8s8,
    4130             :         // MIs[2] Operand 1
    4131             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4132             :         // MIs[2] Rn
    4133             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
    4134             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4135             :         // MIs[2] Rm
    4136             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
    4137             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4138             :         // MIs[0] Rd
    4139             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    4140             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4141             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4142             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4143             :         // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 319:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    4144             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
    4145             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4146             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4147             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4148             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4149             :         GIR_EraseFromParent, /*InsnID*/0,
    4150             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4151             :         GIR_Done,
    4152             :       // Label 125: @8642
    4153             :       GIM_Try, /*On fail goto*//*Label 126*/ 8749,
    4154             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4155             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4156             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4157             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4158             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4159             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4160             :         // No instruction predicates
    4161             :         // MIs[0] dst
    4162             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    4163             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4164             :         // MIs[0] Operand 1
    4165             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    4166             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4167             :         // MIs[1] Operand 0
    4168             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    4169             :         // MIs[1] Operand 1
    4170             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
    4171             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4172             :         // MIs[2] Operand 0
    4173             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v4s16,
    4174             :         // MIs[2] Operand 1
    4175             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4176             :         // MIs[2] Rn
    4177             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
    4178             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4179             :         // MIs[2] Rm
    4180             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
    4181             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4182             :         // MIs[0] Rd
    4183             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    4184             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4185             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4186             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4187             :         // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 319:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    4188             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
    4189             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4190             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4191             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4192             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4193             :         GIR_EraseFromParent, /*InsnID*/0,
    4194             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4195             :         GIR_Done,
    4196             :       // Label 126: @8749
    4197             :       GIM_Try, /*On fail goto*//*Label 127*/ 8856,
    4198             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4199             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4200             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4201             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4202             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4203             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4204             :         // No instruction predicates
    4205             :         // MIs[0] dst
    4206             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4207             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4208             :         // MIs[0] Operand 1
    4209             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    4210             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4211             :         // MIs[1] Operand 0
    4212             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    4213             :         // MIs[1] Operand 1
    4214             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    4215             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4216             :         // MIs[2] Operand 0
    4217             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v2s32,
    4218             :         // MIs[2] Operand 1
    4219             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4220             :         // MIs[2] Rn
    4221             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
    4222             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4223             :         // MIs[2] Rm
    4224             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
    4225             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4226             :         // MIs[0] Rd
    4227             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    4228             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    4229             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4230             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4231             :         // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 319:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    4232             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
    4233             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4234             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    4235             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4236             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4237             :         GIR_EraseFromParent, /*InsnID*/0,
    4238             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4239             :         GIR_Done,
    4240             :       // Label 127: @8856
    4241             :       GIM_Try, /*On fail goto*//*Label 128*/ 8963,
    4242             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4243             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4244             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4245             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4246             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4247             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4248             :         // No instruction predicates
    4249             :         // MIs[0] dst
    4250             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    4251             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4252             :         // MIs[0] Rd
    4253             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    4254             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4255             :         // MIs[0] Operand 2
    4256             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    4257             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4258             :         // MIs[1] Operand 0
    4259             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    4260             :         // MIs[1] Operand 1
    4261             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
    4262             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4263             :         // MIs[2] Operand 0
    4264             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v8s8,
    4265             :         // MIs[2] Operand 1
    4266             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4267             :         // MIs[2] Rn
    4268             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
    4269             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4270             :         // MIs[2] Rm
    4271             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
    4272             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4273             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4274             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4275             :         // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 262:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    4276             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
    4277             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4278             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4279             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4280             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4281             :         GIR_EraseFromParent, /*InsnID*/0,
    4282             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4283             :         GIR_Done,
    4284             :       // Label 128: @8963
    4285             :       GIM_Try, /*On fail goto*//*Label 129*/ 9070,
    4286             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4287             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4288             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4289             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4290             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4291             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4292             :         // No instruction predicates
    4293             :         // MIs[0] dst
    4294             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    4295             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4296             :         // MIs[0] Rd
    4297             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    4298             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4299             :         // MIs[0] Operand 2
    4300             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    4301             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4302             :         // MIs[1] Operand 0
    4303             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    4304             :         // MIs[1] Operand 1
    4305             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
    4306             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4307             :         // MIs[2] Operand 0
    4308             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v4s16,
    4309             :         // MIs[2] Operand 1
    4310             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4311             :         // MIs[2] Rn
    4312             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
    4313             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4314             :         // MIs[2] Rm
    4315             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
    4316             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4317             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4318             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4319             :         // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 262:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    4320             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
    4321             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4322             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4323             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4324             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4325             :         GIR_EraseFromParent, /*InsnID*/0,
    4326             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4327             :         GIR_Done,
    4328             :       // Label 129: @9070
    4329             :       GIM_Try, /*On fail goto*//*Label 130*/ 9177,
    4330             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4331             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4332             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4333             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4334             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4335             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4336             :         // No instruction predicates
    4337             :         // MIs[0] dst
    4338             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4339             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4340             :         // MIs[0] Rd
    4341             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    4342             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4343             :         // MIs[0] Operand 2
    4344             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    4345             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4346             :         // MIs[1] Operand 0
    4347             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    4348             :         // MIs[1] Operand 1
    4349             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    4350             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4351             :         // MIs[2] Operand 0
    4352             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v2s32,
    4353             :         // MIs[2] Operand 1
    4354             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    4355             :         // MIs[2] Rn
    4356             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
    4357             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4358             :         // MIs[2] Rm
    4359             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
    4360             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4361             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4362             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4363             :         // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 262:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    4364             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
    4365             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4366             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4367             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4368             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4369             :         GIR_EraseFromParent, /*InsnID*/0,
    4370             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4371             :         GIR_Done,
    4372             :       // Label 130: @9177
    4373             :       GIM_Try, /*On fail goto*//*Label 131*/ 9284,
    4374             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4375             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4376             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4377             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4378             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4379             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4380             :         // No instruction predicates
    4381             :         // MIs[0] dst
    4382             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    4383             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4384             :         // MIs[0] Rd
    4385             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    4386             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4387             :         // MIs[0] Operand 2
    4388             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    4389             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4390             :         // MIs[1] Operand 0
    4391             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    4392             :         // MIs[1] Operand 1
    4393             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
    4394             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4395             :         // MIs[2] Operand 0
    4396             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v8s8,
    4397             :         // MIs[2] Operand 1
    4398             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4399             :         // MIs[2] Rn
    4400             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
    4401             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4402             :         // MIs[2] Rm
    4403             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
    4404             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4405             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4406             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4407             :         // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 319:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    4408             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
    4409             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4410             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4411             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4412             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4413             :         GIR_EraseFromParent, /*InsnID*/0,
    4414             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4415             :         GIR_Done,
    4416             :       // Label 131: @9284
    4417             :       GIM_Try, /*On fail goto*//*Label 132*/ 9391,
    4418             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4419             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4420             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4421             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4422             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4423             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4424             :         // No instruction predicates
    4425             :         // MIs[0] dst
    4426             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    4427             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4428             :         // MIs[0] Rd
    4429             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    4430             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4431             :         // MIs[0] Operand 2
    4432             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    4433             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4434             :         // MIs[1] Operand 0
    4435             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    4436             :         // MIs[1] Operand 1
    4437             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
    4438             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4439             :         // MIs[2] Operand 0
    4440             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v4s16,
    4441             :         // MIs[2] Operand 1
    4442             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4443             :         // MIs[2] Rn
    4444             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
    4445             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4446             :         // MIs[2] Rm
    4447             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
    4448             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4449             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4450             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4451             :         // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 319:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    4452             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
    4453             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4454             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4455             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4456             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4457             :         GIR_EraseFromParent, /*InsnID*/0,
    4458             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4459             :         GIR_Done,
    4460             :       // Label 132: @9391
    4461             :       GIM_Try, /*On fail goto*//*Label 133*/ 9498,
    4462             :         GIM_CheckFeatures, GIFBS_HasNEON,
    4463             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4464             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    4465             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4466             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
    4467             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
    4468             :         // No instruction predicates
    4469             :         // MIs[0] dst
    4470             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4471             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4472             :         // MIs[0] Rd
    4473             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    4474             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    4475             :         // MIs[0] Operand 2
    4476             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    4477             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4478             :         // MIs[1] Operand 0
    4479             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    4480             :         // MIs[1] Operand 1
    4481             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    4482             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
    4483             :         // MIs[2] Operand 0
    4484             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_v2s32,
    4485             :         // MIs[2] Operand 1
    4486             :         GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    4487             :         // MIs[2] Rn
    4488             :         GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
    4489             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    4490             :         // MIs[2] Rm
    4491             :         GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
    4492             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    4493             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4494             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4495             :         // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 319:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    4496             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
    4497             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    4498             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    4499             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
    4500             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
    4501             :         GIR_EraseFromParent, /*InsnID*/0,
    4502             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4503             :         GIR_Done,
    4504             :       // Label 133: @9498
    4505             :       GIM_Reject,
    4506             :       GIR_Done,
    4507             :     // Label 121: @9500
    4508             :     GIM_Try, /*On fail goto*//*Label 134*/ 9691,
    4509             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
    4510             :       GIM_Try, /*On fail goto*//*Label 135*/ 9597,
    4511             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4512             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4513             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4514             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    4515             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    4516             :         // No instruction predicates
    4517             :         // MIs[0] Rd
    4518             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4519             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4520             :         // MIs[0] Operand 1
    4521             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    4522             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
    4523             :         // MIs[1] Operand 0
    4524             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    4525             :         // MIs[1] Rn
    4526             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    4527             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    4528             :         // MIs[0] Operand 2
    4529             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    4530             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
    4531             :         // MIs[2] Operand 0
    4532             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    4533             :         // MIs[2] Rm
    4534             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    4535             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    4536             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4537             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4538             :         // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
    4539             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
    4540             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4541             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    4542             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
    4543             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    4544             :         GIR_EraseFromParent, /*InsnID*/0,
    4545             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4546             :         GIR_Done,
    4547             :       // Label 135: @9597
    4548             :       GIM_Try, /*On fail goto*//*Label 136*/ 9689,
    4549             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    4550             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    4551             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    4552             :         GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    4553             :         GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    4554             :         // No instruction predicates
    4555             :         // MIs[0] Rd
    4556             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4557             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4558             :         // MIs[0] Operand 1
    4559             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    4560             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
    4561             :         // MIs[1] Operand 0
    4562             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    4563             :         // MIs[1] Rn
    4564             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    4565             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    4566             :         // MIs[0] Operand 2
    4567             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    4568             :         GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
    4569             :         // MIs[2] Operand 0
    4570             :         GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    4571             :         // MIs[2] Rm
    4572             :         GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    4573             :         GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
    4574             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    4575             :         GIM_CheckIsSafeToFold, /*InsnID*/2,
    4576             :         // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
    4577             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
    4578             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4579             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
    4580             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
    4581             :         GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
    4582             :         GIR_EraseFromParent, /*InsnID*/0,
    4583             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4584             :         GIR_Done,
    4585             :       // Label 136: @9689
    4586             :       GIM_Reject,
    4587             :       GIR_Done,
    4588             :     // Label 134: @9691
    4589             :     GIM_Try, /*On fail goto*//*Label 137*/ 9992,
    4590             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
    4591             :       GIM_Try, /*On fail goto*//*Label 138*/ 9745,
    4592             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4593             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4594             :         // MIs[0] Rt
    4595             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4596             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4597             :         // MIs[0] Operand 1
    4598             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4599             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    4600             :         // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4601             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi,
    4602             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4603             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4604             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4605             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4606             :         GIR_EraseFromParent, /*InsnID*/0,
    4607             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4608             :         GIR_Done,
    4609             :       // Label 138: @9745
    4610             :       GIM_Try, /*On fail goto*//*Label 139*/ 9794,
    4611             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4612             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4613             :         // MIs[0] Rt
    4614             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4615             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    4616             :         // MIs[0] Operand 1
    4617             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4618             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4619             :         // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4620             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi,
    4621             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4622             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4623             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4624             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4625             :         GIR_EraseFromParent, /*InsnID*/0,
    4626             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4627             :         GIR_Done,
    4628             :       // Label 139: @9794
    4629             :       GIM_Try, /*On fail goto*//*Label 140*/ 9843,
    4630             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4631             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4632             :         // MIs[0] Rt
    4633             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
    4634             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID,
    4635             :         // MIs[0] Operand 1
    4636             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4637             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    4638             :         // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4639             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHi,
    4640             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4641             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4642             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4643             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4644             :         GIR_EraseFromParent, /*InsnID*/0,
    4645             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4646             :         GIR_Done,
    4647             :       // Label 140: @9843
    4648             :       GIM_Try, /*On fail goto*//*Label 141*/ 9892,
    4649             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4650             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4651             :         // MIs[0] Rt
    4652             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4653             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    4654             :         // MIs[0] Operand 1
    4655             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4656             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4657             :         // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4658             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSi,
    4659             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4660             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4661             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4662             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4663             :         GIR_EraseFromParent, /*InsnID*/0,
    4664             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4665             :         GIR_Done,
    4666             :       // Label 141: @9892
    4667             :       GIM_Try, /*On fail goto*//*Label 142*/ 9941,
    4668             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4669             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4670             :         // MIs[0] Rt
    4671             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4672             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4673             :         // MIs[0] Operand 1
    4674             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4675             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    4676             :         // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4677             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    4678             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4679             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4680             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4681             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4682             :         GIR_EraseFromParent, /*InsnID*/0,
    4683             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4684             :         GIR_Done,
    4685             :       // Label 142: @9941
    4686             :       GIM_Try, /*On fail goto*//*Label 143*/ 9990,
    4687             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4688             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4689             :         // MIs[0] Rt
    4690             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    4691             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4692             :         // MIs[0] Operand 1
    4693             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4694             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    4695             :         // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4696             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    4697             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4698             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4699             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4700             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4701             :         GIR_EraseFromParent, /*InsnID*/0,
    4702             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4703             :         GIR_Done,
    4704             :       // Label 143: @9990
    4705             :       GIM_Reject,
    4706             :       GIR_Done,
    4707             :     // Label 137: @9992
    4708             :     GIM_Try, /*On fail goto*//*Label 144*/ 10293,
    4709             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE,
    4710             :       GIM_Try, /*On fail goto*//*Label 145*/ 10046,
    4711             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4712             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4713             :         // MIs[0] Rt
    4714             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4715             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    4716             :         // MIs[0] Operand 1
    4717             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4718             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    4719             :         // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURXi GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4720             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi,
    4721             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4722             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4723             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4724             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4725             :         GIR_EraseFromParent, /*InsnID*/0,
    4726             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4727             :         GIR_Done,
    4728             :       // Label 145: @10046
    4729             :       GIM_Try, /*On fail goto*//*Label 146*/ 10095,
    4730             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4731             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4732             :         // MIs[0] Rt
    4733             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4734             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    4735             :         // MIs[0] Operand 1
    4736             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4737             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4738             :         // (st GPR32:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURWi GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4739             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi,
    4740             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4741             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4742             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4743             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4744             :         GIR_EraseFromParent, /*InsnID*/0,
    4745             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4746             :         GIR_Done,
    4747             :       // Label 146: @10095
    4748             :       GIM_Try, /*On fail goto*//*Label 147*/ 10144,
    4749             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4750             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4751             :         // MIs[0] Rt
    4752             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
    4753             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID,
    4754             :         // MIs[0] Operand 1
    4755             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4756             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16,
    4757             :         // (st FPR16:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURHi FPR16:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4758             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHi,
    4759             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4760             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4761             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4762             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4763             :         GIR_EraseFromParent, /*InsnID*/0,
    4764             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4765             :         GIR_Done,
    4766             :       // Label 147: @10144
    4767             :       GIM_Try, /*On fail goto*//*Label 148*/ 10193,
    4768             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4769             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4770             :         // MIs[0] Rt
    4771             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4772             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    4773             :         // MIs[0] Operand 1
    4774             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4775             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32,
    4776             :         // (st FPR32:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi FPR32:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4777             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURSi,
    4778             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4779             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4780             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4781             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4782             :         GIR_EraseFromParent, /*InsnID*/0,
    4783             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4784             :         GIR_Done,
    4785             :       // Label 148: @10193
    4786             :       GIM_Try, /*On fail goto*//*Label 149*/ 10242,
    4787             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4788             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4789             :         // MIs[0] Rt
    4790             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4791             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4792             :         // MIs[0] Operand 1
    4793             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4794             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    4795             :         // (st FPR64:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4796             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    4797             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4798             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4799             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4800             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4801             :         GIR_EraseFromParent, /*InsnID*/0,
    4802             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4803             :         GIR_Done,
    4804             :       // Label 149: @10242
    4805             :       GIM_Try, /*On fail goto*//*Label 150*/ 10291,
    4806             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4807             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4808             :         // MIs[0] Rt
    4809             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    4810             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4811             :         // MIs[0] Operand 1
    4812             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4813             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    4814             :         // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
    4815             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    4816             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4817             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4818             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4819             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4820             :         GIR_EraseFromParent, /*InsnID*/0,
    4821             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4822             :         GIR_Done,
    4823             :       // Label 150: @10291
    4824             :       GIM_Reject,
    4825             :       GIR_Done,
    4826             :     // Label 144: @10293
    4827             :     GIM_Try, /*On fail goto*//*Label 151*/ 11769,
    4828             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
    4829             :       GIM_Try, /*On fail goto*//*Label 152*/ 10349,
    4830             :         GIM_CheckFeatures, GIFBS_IsLE,
    4831             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4832             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4833             :         // MIs[0] Rt
    4834             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    4835             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4836             :         // MIs[0] Operand 1
    4837             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4838             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4839             :         // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4840             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4841             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4842             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4843             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4844             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4845             :         GIR_EraseFromParent, /*InsnID*/0,
    4846             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4847             :         GIR_Done,
    4848             :       // Label 152: @10349
    4849             :       GIM_Try, /*On fail goto*//*Label 153*/ 10400,
    4850             :         GIM_CheckFeatures, GIFBS_IsLE,
    4851             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4852             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4853             :         // MIs[0] Rt
    4854             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    4855             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4856             :         // MIs[0] Operand 1
    4857             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4858             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4859             :         // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4860             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4861             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4862             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4863             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4864             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4865             :         GIR_EraseFromParent, /*InsnID*/0,
    4866             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4867             :         GIR_Done,
    4868             :       // Label 153: @10400
    4869             :       GIM_Try, /*On fail goto*//*Label 154*/ 10451,
    4870             :         GIM_CheckFeatures, GIFBS_IsLE,
    4871             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4872             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4873             :         // MIs[0] Rt
    4874             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    4875             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4876             :         // MIs[0] Operand 1
    4877             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4878             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4879             :         // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4880             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4881             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4882             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4883             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4884             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4885             :         GIR_EraseFromParent, /*InsnID*/0,
    4886             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4887             :         GIR_Done,
    4888             :       // Label 154: @10451
    4889             :       GIM_Try, /*On fail goto*//*Label 155*/ 10502,
    4890             :         GIM_CheckFeatures, GIFBS_IsLE,
    4891             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4892             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4893             :         // MIs[0] Rt
    4894             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    4895             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4896             :         // MIs[0] Operand 1
    4897             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4898             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4899             :         // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4900             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4901             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4902             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4903             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4904             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4905             :         GIR_EraseFromParent, /*InsnID*/0,
    4906             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4907             :         GIR_Done,
    4908             :       // Label 155: @10502
    4909             :       GIM_Try, /*On fail goto*//*Label 156*/ 10553,
    4910             :         GIM_CheckFeatures, GIFBS_IsLE,
    4911             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4912             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4913             :         // MIs[0] Rt
    4914             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    4915             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4916             :         // MIs[0] Operand 1
    4917             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4918             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4919             :         // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4920             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4921             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4922             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4923             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4924             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4925             :         GIR_EraseFromParent, /*InsnID*/0,
    4926             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4927             :         GIR_Done,
    4928             :       // Label 156: @10553
    4929             :       GIM_Try, /*On fail goto*//*Label 157*/ 10602,
    4930             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4931             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4932             :         // MIs[0] Rt
    4933             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4934             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4935             :         // MIs[0] Operand 1
    4936             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4937             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4938             :         // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4939             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4940             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4941             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4942             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4943             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4944             :         GIR_EraseFromParent, /*InsnID*/0,
    4945             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4946             :         GIR_Done,
    4947             :       // Label 157: @10602
    4948             :       GIM_Try, /*On fail goto*//*Label 158*/ 10651,
    4949             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4950             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4951             :         // MIs[0] Rt
    4952             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    4953             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    4954             :         // MIs[0] Operand 1
    4955             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4956             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64,
    4957             :         // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
    4958             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui,
    4959             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4960             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4961             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4962             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4963             :         GIR_EraseFromParent, /*InsnID*/0,
    4964             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4965             :         GIR_Done,
    4966             :       // Label 158: @10651
    4967             :       GIM_Try, /*On fail goto*//*Label 159*/ 10702,
    4968             :         GIM_CheckFeatures, GIFBS_IsLE,
    4969             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4970             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4971             :         // MIs[0] Rt
    4972             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    4973             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4974             :         // MIs[0] Operand 1
    4975             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4976             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    4977             :         // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    4978             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    4979             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    4980             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    4981             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    4982             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    4983             :         GIR_EraseFromParent, /*InsnID*/0,
    4984             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4985             :         GIR_Done,
    4986             :       // Label 159: @10702
    4987             :       GIM_Try, /*On fail goto*//*Label 160*/ 10753,
    4988             :         GIM_CheckFeatures, GIFBS_IsLE,
    4989             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    4990             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    4991             :         // MIs[0] Rt
    4992             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    4993             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    4994             :         // MIs[0] Operand 1
    4995             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    4996             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    4997             :         // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    4998             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    4999             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5000             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5001             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5002             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5003             :         GIR_EraseFromParent, /*InsnID*/0,
    5004             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5005             :         GIR_Done,
    5006             :       // Label 160: @10753
    5007             :       GIM_Try, /*On fail goto*//*Label 161*/ 10804,
    5008             :         GIM_CheckFeatures, GIFBS_IsLE,
    5009             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5010             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5011             :         // MIs[0] Rt
    5012             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5013             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5014             :         // MIs[0] Operand 1
    5015             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5016             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5017             :         // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5018             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5019             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5020             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5021             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5022             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5023             :         GIR_EraseFromParent, /*InsnID*/0,
    5024             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5025             :         GIR_Done,
    5026             :       // Label 161: @10804
    5027             :       GIM_Try, /*On fail goto*//*Label 162*/ 10855,
    5028             :         GIM_CheckFeatures, GIFBS_IsLE,
    5029             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5030             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5031             :         // MIs[0] Rt
    5032             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5033             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5034             :         // MIs[0] Operand 1
    5035             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5036             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5037             :         // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5038             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5039             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5040             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5041             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5042             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5043             :         GIR_EraseFromParent, /*InsnID*/0,
    5044             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5045             :         GIR_Done,
    5046             :       // Label 162: @10855
    5047             :       GIM_Try, /*On fail goto*//*Label 163*/ 10906,
    5048             :         GIM_CheckFeatures, GIFBS_IsLE,
    5049             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5050             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5051             :         // MIs[0] Rt
    5052             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5053             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5054             :         // MIs[0] Operand 1
    5055             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5056             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5057             :         // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5058             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5059             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5060             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5061             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5062             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5063             :         GIR_EraseFromParent, /*InsnID*/0,
    5064             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5065             :         GIR_Done,
    5066             :       // Label 163: @10906
    5067             :       GIM_Try, /*On fail goto*//*Label 164*/ 10957,
    5068             :         GIM_CheckFeatures, GIFBS_IsLE,
    5069             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5070             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5071             :         // MIs[0] Rt
    5072             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5073             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5074             :         // MIs[0] Operand 1
    5075             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5076             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5077             :         // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5078             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5079             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5080             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5081             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5082             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5083             :         GIR_EraseFromParent, /*InsnID*/0,
    5084             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5085             :         GIR_Done,
    5086             :       // Label 164: @10957
    5087             :       GIM_Try, /*On fail goto*//*Label 165*/ 11008,
    5088             :         GIM_CheckFeatures, GIFBS_IsLE,
    5089             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5090             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5091             :         // MIs[0] Rt
    5092             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5093             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5094             :         // MIs[0] Operand 1
    5095             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5096             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5097             :         // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5098             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5099             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5100             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5101             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5102             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5103             :         GIR_EraseFromParent, /*InsnID*/0,
    5104             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5105             :         GIR_Done,
    5106             :       // Label 165: @11008
    5107             :       GIM_Try, /*On fail goto*//*Label 166*/ 11057,
    5108             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5109             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5110             :         // MIs[0] Rt
    5111             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128,
    5112             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5113             :         // MIs[0] Operand 1
    5114             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5115             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128,
    5116             :         // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
    5117             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui,
    5118             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5119             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5120             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5121             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5122             :         GIR_EraseFromParent, /*InsnID*/0,
    5123             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5124             :         GIR_Done,
    5125             :       // Label 166: @11057
    5126             :       GIM_Try, /*On fail goto*//*Label 167*/ 11108,
    5127             :         GIM_CheckFeatures, GIFBS_IsLE,
    5128             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5129             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5130             :         // MIs[0] Rt
    5131             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5132             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5133             :         // MIs[0] Operand 1
    5134             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5135             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5136             :         // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5137             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5138             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5139             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5140             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5141             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5142             :         GIR_EraseFromParent, /*InsnID*/0,
    5143             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5144             :         GIR_Done,
    5145             :       // Label 167: @11108
    5146             :       GIM_Try, /*On fail goto*//*Label 168*/ 11159,
    5147             :         GIM_CheckFeatures, GIFBS_IsLE,
    5148             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5149             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5150             :         // MIs[0] Rt
    5151             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5152             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5153             :         // MIs[0] Operand 1
    5154             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5155             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5156             :         // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5157             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5158             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5159             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5160             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5161             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5162             :         GIR_EraseFromParent, /*InsnID*/0,
    5163             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5164             :         GIR_Done,
    5165             :       // Label 168: @11159
    5166             :       GIM_Try, /*On fail goto*//*Label 169*/ 11210,
    5167             :         GIM_CheckFeatures, GIFBS_IsLE,
    5168             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5169             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5170             :         // MIs[0] Rt
    5171             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5172             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5173             :         // MIs[0] Operand 1
    5174             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5175             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5176             :         // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5177             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5178             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5179             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5180             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5181             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5182             :         GIR_EraseFromParent, /*InsnID*/0,
    5183             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5184             :         GIR_Done,
    5185             :       // Label 169: @11210
    5186             :       GIM_Try, /*On fail goto*//*Label 170*/ 11261,
    5187             :         GIM_CheckFeatures, GIFBS_IsLE,
    5188             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5189             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5190             :         // MIs[0] Rt
    5191             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5192             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5193             :         // MIs[0] Operand 1
    5194             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5195             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5196             :         // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5197             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5198             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5199             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5200             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5201             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5202             :         GIR_EraseFromParent, /*InsnID*/0,
    5203             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5204             :         GIR_Done,
    5205             :       // Label 170: @11261
    5206             :       GIM_Try, /*On fail goto*//*Label 171*/ 11312,
    5207             :         GIM_CheckFeatures, GIFBS_IsLE,
    5208             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5209             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5210             :         // MIs[0] Rt
    5211             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5212             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5213             :         // MIs[0] Operand 1
    5214             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5215             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5216             :         // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5217             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5218             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5219             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5220             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5221             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5222             :         GIR_EraseFromParent, /*InsnID*/0,
    5223             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5224             :         GIR_Done,
    5225             :       // Label 171: @11312
    5226             :       GIM_Try, /*On fail goto*//*Label 172*/ 11361,
    5227             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5228             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5229             :         // MIs[0] Rt
    5230             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5231             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5232             :         // MIs[0] Operand 1
    5233             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5234             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5235             :         // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5236             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5237             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5238             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5239             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5240             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5241             :         GIR_EraseFromParent, /*InsnID*/0,
    5242             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5243             :         GIR_Done,
    5244             :       // Label 172: @11361
    5245             :       GIM_Try, /*On fail goto*//*Label 173*/ 11410,
    5246             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5247             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5248             :         // MIs[0] Rt
    5249             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5250             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5251             :         // MIs[0] Operand 1
    5252             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5253             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5254             :         // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5255             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi,
    5256             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5257             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5258             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5259             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5260             :         GIR_EraseFromParent, /*InsnID*/0,
    5261             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5262             :         GIR_Done,
    5263             :       // Label 173: @11410
    5264             :       GIM_Try, /*On fail goto*//*Label 174*/ 11461,
    5265             :         GIM_CheckFeatures, GIFBS_IsLE,
    5266             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5267             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5268             :         // MIs[0] Rt
    5269             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5270             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5271             :         // MIs[0] Operand 1
    5272             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5273             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5274             :         // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5275             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5276             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5277             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5278             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5279             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5280             :         GIR_EraseFromParent, /*InsnID*/0,
    5281             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5282             :         GIR_Done,
    5283             :       // Label 174: @11461
    5284             :       GIM_Try, /*On fail goto*//*Label 175*/ 11512,
    5285             :         GIM_CheckFeatures, GIFBS_IsLE,
    5286             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5287             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5288             :         // MIs[0] Rt
    5289             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5290             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5291             :         // MIs[0] Operand 1
    5292             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5293             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5294             :         // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5295             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5296             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5297             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5298             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5299             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5300             :         GIR_EraseFromParent, /*InsnID*/0,
    5301             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5302             :         GIR_Done,
    5303             :       // Label 175: @11512
    5304             :       GIM_Try, /*On fail goto*//*Label 176*/ 11563,
    5305             :         GIM_CheckFeatures, GIFBS_IsLE,
    5306             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5307             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5308             :         // MIs[0] Rt
    5309             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5310             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5311             :         // MIs[0] Operand 1
    5312             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5313             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5314             :         // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5315             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5316             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5317             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5318             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5319             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5320             :         GIR_EraseFromParent, /*InsnID*/0,
    5321             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5322             :         GIR_Done,
    5323             :       // Label 176: @11563
    5324             :       GIM_Try, /*On fail goto*//*Label 177*/ 11614,
    5325             :         GIM_CheckFeatures, GIFBS_IsLE,
    5326             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5327             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5328             :         // MIs[0] Rt
    5329             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5330             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5331             :         // MIs[0] Operand 1
    5332             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5333             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5334             :         // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5335             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5336             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5337             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5338             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5339             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5340             :         GIR_EraseFromParent, /*InsnID*/0,
    5341             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5342             :         GIR_Done,
    5343             :       // Label 177: @11614
    5344             :       GIM_Try, /*On fail goto*//*Label 178*/ 11665,
    5345             :         GIM_CheckFeatures, GIFBS_IsLE,
    5346             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5347             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5348             :         // MIs[0] Rt
    5349             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5350             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5351             :         // MIs[0] Operand 1
    5352             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5353             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5354             :         // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5355             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5356             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5357             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5358             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5359             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5360             :         GIR_EraseFromParent, /*InsnID*/0,
    5361             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5362             :         GIR_Done,
    5363             :       // Label 178: @11665
    5364             :       GIM_Try, /*On fail goto*//*Label 179*/ 11716,
    5365             :         GIM_CheckFeatures, GIFBS_IsLE,
    5366             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5367             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5368             :         // MIs[0] Rt
    5369             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5370             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5371             :         // MIs[0] Operand 1
    5372             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5373             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5374             :         // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5375             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5376             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5377             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5378             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5379             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5380             :         GIR_EraseFromParent, /*InsnID*/0,
    5381             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5382             :         GIR_Done,
    5383             :       // Label 179: @11716
    5384             :       GIM_Try, /*On fail goto*//*Label 180*/ 11767,
    5385             :         GIM_CheckFeatures, GIFBS_IsLE,
    5386             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5387             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5388             :         // MIs[0] Rt
    5389             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5390             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5391             :         // MIs[0] Operand 1
    5392             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5393             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5394             :         // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5395             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi,
    5396             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5397             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5398             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5399             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5400             :         GIR_EraseFromParent, /*InsnID*/0,
    5401             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5402             :         GIR_Done,
    5403             :       // Label 180: @11767
    5404             :       GIM_Reject,
    5405             :       GIR_Done,
    5406             :     // Label 151: @11769
    5407             :     GIM_Try, /*On fail goto*//*Label 181*/ 12537,
    5408             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE,
    5409             :       GIM_Try, /*On fail goto*//*Label 182*/ 11825,
    5410             :         GIM_CheckFeatures, GIFBS_IsLE,
    5411             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5412             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5413             :         // MIs[0] Rt
    5414             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5415             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5416             :         // MIs[0] Operand 1
    5417             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5418             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5419             :         // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5420             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5421             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5422             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5423             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5424             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5425             :         GIR_EraseFromParent, /*InsnID*/0,
    5426             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5427             :         GIR_Done,
    5428             :       // Label 182: @11825
    5429             :       GIM_Try, /*On fail goto*//*Label 183*/ 11876,
    5430             :         GIM_CheckFeatures, GIFBS_IsLE,
    5431             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5432             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5433             :         // MIs[0] Rt
    5434             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5435             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5436             :         // MIs[0] Operand 1
    5437             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5438             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5439             :         // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5440             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5441             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5442             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5443             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5444             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5445             :         GIR_EraseFromParent, /*InsnID*/0,
    5446             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5447             :         GIR_Done,
    5448             :       // Label 183: @11876
    5449             :       GIM_Try, /*On fail goto*//*Label 184*/ 11927,
    5450             :         GIM_CheckFeatures, GIFBS_IsLE,
    5451             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5452             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5453             :         // MIs[0] Rt
    5454             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5455             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5456             :         // MIs[0] Operand 1
    5457             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5458             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5459             :         // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5460             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5461             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5462             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5463             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5464             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5465             :         GIR_EraseFromParent, /*InsnID*/0,
    5466             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5467             :         GIR_Done,
    5468             :       // Label 184: @11927
    5469             :       GIM_Try, /*On fail goto*//*Label 185*/ 11978,
    5470             :         GIM_CheckFeatures, GIFBS_IsLE,
    5471             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5472             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5473             :         // MIs[0] Rt
    5474             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5475             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5476             :         // MIs[0] Operand 1
    5477             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5478             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5479             :         // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5480             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5481             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5482             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5483             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5484             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5485             :         GIR_EraseFromParent, /*InsnID*/0,
    5486             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5487             :         GIR_Done,
    5488             :       // Label 185: @11978
    5489             :       GIM_Try, /*On fail goto*//*Label 186*/ 12029,
    5490             :         GIM_CheckFeatures, GIFBS_IsLE,
    5491             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5492             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5493             :         // MIs[0] Rt
    5494             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5495             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5496             :         // MIs[0] Operand 1
    5497             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5498             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5499             :         // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5500             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5501             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5502             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5503             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5504             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5505             :         GIR_EraseFromParent, /*InsnID*/0,
    5506             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5507             :         GIR_Done,
    5508             :       // Label 186: @12029
    5509             :       GIM_Try, /*On fail goto*//*Label 187*/ 12078,
    5510             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5511             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5512             :         // MIs[0] Rt
    5513             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5514             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5515             :         // MIs[0] Operand 1
    5516             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5517             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5518             :         // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5519             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5520             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5521             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5522             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5523             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5524             :         GIR_EraseFromParent, /*InsnID*/0,
    5525             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5526             :         GIR_Done,
    5527             :       // Label 187: @12078
    5528             :       GIM_Try, /*On fail goto*//*Label 188*/ 12127,
    5529             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5530             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5531             :         // MIs[0] Rt
    5532             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    5533             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5534             :         // MIs[0] Operand 1
    5535             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5536             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64,
    5537             :         // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5538             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi,
    5539             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5540             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5541             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5542             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5543             :         GIR_EraseFromParent, /*InsnID*/0,
    5544             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5545             :         GIR_Done,
    5546             :       // Label 188: @12127
    5547             :       GIM_Try, /*On fail goto*//*Label 189*/ 12178,
    5548             :         GIM_CheckFeatures, GIFBS_IsLE,
    5549             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5550             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5551             :         // MIs[0] Rt
    5552             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5553             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5554             :         // MIs[0] Operand 1
    5555             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5556             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5557             :         // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5558             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    5559             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5560             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5561             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5562             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5563             :         GIR_EraseFromParent, /*InsnID*/0,
    5564             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5565             :         GIR_Done,
    5566             :       // Label 189: @12178
    5567             :       GIM_Try, /*On fail goto*//*Label 190*/ 12229,
    5568             :         GIM_CheckFeatures, GIFBS_IsLE,
    5569             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5570             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5571             :         // MIs[0] Rt
    5572             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5573             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5574             :         // MIs[0] Operand 1
    5575             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5576             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5577             :         // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5578             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    5579             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5580             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5581             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5582             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5583             :         GIR_EraseFromParent, /*InsnID*/0,
    5584             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5585             :         GIR_Done,
    5586             :       // Label 190: @12229
    5587             :       GIM_Try, /*On fail goto*//*Label 191*/ 12280,
    5588             :         GIM_CheckFeatures, GIFBS_IsLE,
    5589             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5590             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5591             :         // MIs[0] Rt
    5592             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5593             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5594             :         // MIs[0] Operand 1
    5595             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5596             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5597             :         // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5598             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    5599             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5600             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5601             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5602             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5603             :         GIR_EraseFromParent, /*InsnID*/0,
    5604             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5605             :         GIR_Done,
    5606             :       // Label 191: @12280
    5607             :       GIM_Try, /*On fail goto*//*Label 192*/ 12331,
    5608             :         GIM_CheckFeatures, GIFBS_IsLE,
    5609             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5610             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5611             :         // MIs[0] Rt
    5612             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5613             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5614             :         // MIs[0] Operand 1
    5615             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5616             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5617             :         // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5618             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    5619             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5620             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5621             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5622             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5623             :         GIR_EraseFromParent, /*InsnID*/0,
    5624             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5625             :         GIR_Done,
    5626             :       // Label 192: @12331
    5627             :       GIM_Try, /*On fail goto*//*Label 193*/ 12382,
    5628             :         GIM_CheckFeatures, GIFBS_IsLE,
    5629             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5630             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5631             :         // MIs[0] Rt
    5632             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5633             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5634             :         // MIs[0] Operand 1
    5635             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5636             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5637             :         // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5638             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    5639             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5640             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5641             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5642             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5643             :         GIR_EraseFromParent, /*InsnID*/0,
    5644             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5645             :         GIR_Done,
    5646             :       // Label 193: @12382
    5647             :       GIM_Try, /*On fail goto*//*Label 194*/ 12433,
    5648             :         GIM_CheckFeatures, GIFBS_IsLE,
    5649             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5650             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5651             :         // MIs[0] Rt
    5652             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5653             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5654             :         // MIs[0] Operand 1
    5655             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5656             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5657             :         // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5658             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    5659             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5660             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5661             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5662             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5663             :         GIR_EraseFromParent, /*InsnID*/0,
    5664             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5665             :         GIR_Done,
    5666             :       // Label 194: @12433
    5667             :       GIM_Try, /*On fail goto*//*Label 195*/ 12484,
    5668             :         GIM_CheckFeatures, GIFBS_IsLE,
    5669             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5670             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5671             :         // MIs[0] Rt
    5672             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5673             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5674             :         // MIs[0] Operand 1
    5675             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5676             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5677             :         // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5678             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    5679             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5680             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5681             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5682             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5683             :         GIR_EraseFromParent, /*InsnID*/0,
    5684             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5685             :         GIR_Done,
    5686             :       // Label 195: @12484
    5687             :       GIM_Try, /*On fail goto*//*Label 196*/ 12535,
    5688             :         GIM_CheckFeatures, GIFBS_IsLE,
    5689             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    5690             :         GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
    5691             :         // MIs[0] Rt
    5692             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5693             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5694             :         // MIs[0] Operand 1
    5695             :         GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
    5696             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128,
    5697             :         // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
    5698             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi,
    5699             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
    5700             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn
    5701             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset
    5702             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    5703             :         GIR_EraseFromParent, /*InsnID*/0,
    5704             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5705             :         GIR_Done,
    5706             :       // Label 196: @12535
    5707             :       GIM_Reject,
    5708             :       GIR_Done,
    5709             :     // Label 181: @12537
    5710             :     GIM_Try, /*On fail goto*//*Label 197*/ 16503,
    5711             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5712             :       GIM_Try, /*On fail goto*//*Label 198*/ 12623,
    5713             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5714             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5715             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5716             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5717             :         // No instruction predicates
    5718             :         // MIs[0] dst
    5719             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5720             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5721             :         // MIs[0] Operand 1
    5722             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5723             :         // MIs[0] Rd
    5724             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    5725             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    5726             :         // MIs[0] Rn
    5727             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    5728             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    5729             :         // MIs[0] imm
    5730             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5731             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5732             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL8,
    5733             :         // MIs[1] Operand 0
    5734             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5735             :         // MIs[1] Operand 1
    5736             :         // No operand predicates
    5737             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5738             :         // (intrinsic_wo_chain:{ *:[v8i8] } 353:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm)  =>  (SLIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
    5739             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i8_shift,
    5740             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5741             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5742             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5743             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5744             :         GIR_EraseFromParent, /*InsnID*/0,
    5745             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5746             :         GIR_Done,
    5747             :       // Label 198: @12623
    5748             :       GIM_Try, /*On fail goto*//*Label 199*/ 12704,
    5749             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5750             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5751             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5752             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5753             :         // No instruction predicates
    5754             :         // MIs[0] dst
    5755             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5756             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5757             :         // MIs[0] Operand 1
    5758             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5759             :         // MIs[0] Rd
    5760             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    5761             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    5762             :         // MIs[0] Rn
    5763             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    5764             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    5765             :         // MIs[0] imm
    5766             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5767             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5768             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL8,
    5769             :         // MIs[1] Operand 0
    5770             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5771             :         // MIs[1] Operand 1
    5772             :         // No operand predicates
    5773             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5774             :         // (intrinsic_wo_chain:{ *:[v16i8] } 353:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm)  =>  (SLIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
    5775             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv16i8_shift,
    5776             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5777             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5778             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5779             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5780             :         GIR_EraseFromParent, /*InsnID*/0,
    5781             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5782             :         GIR_Done,
    5783             :       // Label 199: @12704
    5784             :       GIM_Try, /*On fail goto*//*Label 200*/ 12785,
    5785             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5786             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5787             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5788             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5789             :         // No instruction predicates
    5790             :         // MIs[0] dst
    5791             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5792             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5793             :         // MIs[0] Operand 1
    5794             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5795             :         // MIs[0] Rd
    5796             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    5797             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    5798             :         // MIs[0] Rn
    5799             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    5800             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    5801             :         // MIs[0] imm
    5802             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5803             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5804             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL16,
    5805             :         // MIs[1] Operand 0
    5806             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5807             :         // MIs[1] Operand 1
    5808             :         // No operand predicates
    5809             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5810             :         // (intrinsic_wo_chain:{ *:[v4i16] } 353:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm)  =>  (SLIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    5811             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i16_shift,
    5812             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5813             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5814             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5815             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5816             :         GIR_EraseFromParent, /*InsnID*/0,
    5817             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5818             :         GIR_Done,
    5819             :       // Label 200: @12785
    5820             :       GIM_Try, /*On fail goto*//*Label 201*/ 12866,
    5821             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5822             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5823             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5824             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5825             :         // No instruction predicates
    5826             :         // MIs[0] dst
    5827             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5828             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5829             :         // MIs[0] Operand 1
    5830             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5831             :         // MIs[0] Rd
    5832             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    5833             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    5834             :         // MIs[0] Rn
    5835             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    5836             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    5837             :         // MIs[0] imm
    5838             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5839             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5840             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL16,
    5841             :         // MIs[1] Operand 0
    5842             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5843             :         // MIs[1] Operand 1
    5844             :         // No operand predicates
    5845             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5846             :         // (intrinsic_wo_chain:{ *:[v8i16] } 353:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm)  =>  (SLIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    5847             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i16_shift,
    5848             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5849             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5850             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5851             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5852             :         GIR_EraseFromParent, /*InsnID*/0,
    5853             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5854             :         GIR_Done,
    5855             :       // Label 201: @12866
    5856             :       GIM_Try, /*On fail goto*//*Label 202*/ 12947,
    5857             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5858             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5859             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5860             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5861             :         // No instruction predicates
    5862             :         // MIs[0] dst
    5863             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5864             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5865             :         // MIs[0] Operand 1
    5866             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5867             :         // MIs[0] Rd
    5868             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    5869             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    5870             :         // MIs[0] Rn
    5871             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    5872             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    5873             :         // MIs[0] imm
    5874             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5875             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5876             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL32,
    5877             :         // MIs[1] Operand 0
    5878             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5879             :         // MIs[1] Operand 1
    5880             :         // No operand predicates
    5881             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5882             :         // (intrinsic_wo_chain:{ *:[v2i32] } 353:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SLIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    5883             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i32_shift,
    5884             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5885             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5886             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5887             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5888             :         GIR_EraseFromParent, /*InsnID*/0,
    5889             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5890             :         GIR_Done,
    5891             :       // Label 202: @12947
    5892             :       GIM_Try, /*On fail goto*//*Label 203*/ 13028,
    5893             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5894             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5895             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5896             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5897             :         // No instruction predicates
    5898             :         // MIs[0] dst
    5899             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5900             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5901             :         // MIs[0] Operand 1
    5902             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5903             :         // MIs[0] Rd
    5904             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    5905             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    5906             :         // MIs[0] Rn
    5907             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    5908             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    5909             :         // MIs[0] imm
    5910             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5911             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5912             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL32,
    5913             :         // MIs[1] Operand 0
    5914             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5915             :         // MIs[1] Operand 1
    5916             :         // No operand predicates
    5917             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5918             :         // (intrinsic_wo_chain:{ *:[v4i32] } 353:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SLIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    5919             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i32_shift,
    5920             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5921             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5922             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5923             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5924             :         GIR_EraseFromParent, /*InsnID*/0,
    5925             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5926             :         GIR_Done,
    5927             :       // Label 203: @13028
    5928             :       GIM_Try, /*On fail goto*//*Label 204*/ 13109,
    5929             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5930             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5931             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5932             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5933             :         // No instruction predicates
    5934             :         // MIs[0] dst
    5935             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    5936             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    5937             :         // MIs[0] Operand 1
    5938             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    5939             :         // MIs[0] Rd
    5940             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    5941             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    5942             :         // MIs[0] Rn
    5943             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    5944             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    5945             :         // MIs[0] imm
    5946             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5947             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5948             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL64,
    5949             :         // MIs[1] Operand 0
    5950             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5951             :         // MIs[1] Operand 1
    5952             :         // No operand predicates
    5953             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5954             :         // (intrinsic_wo_chain:{ *:[v2i64] } 353:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SLIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    5955             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i64_shift,
    5956             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5957             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5958             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5959             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5960             :         GIR_EraseFromParent, /*InsnID*/0,
    5961             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5962             :         GIR_Done,
    5963             :       // Label 204: @13109
    5964             :       GIM_Try, /*On fail goto*//*Label 205*/ 13190,
    5965             :         GIM_CheckFeatures, GIFBS_HasNEON,
    5966             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    5967             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    5968             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    5969             :         // No instruction predicates
    5970             :         // MIs[0] dst
    5971             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5972             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    5973             :         // MIs[0] Operand 1
    5974             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    5975             :         // MIs[0] Rd
    5976             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    5977             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    5978             :         // MIs[0] Rn
    5979             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    5980             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    5981             :         // MIs[0] imm
    5982             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    5983             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    5984             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8,
    5985             :         // MIs[1] Operand 0
    5986             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    5987             :         // MIs[1] Operand 1
    5988             :         // No operand predicates
    5989             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    5990             :         // (intrinsic_wo_chain:{ *:[v8i8] } 354:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SRIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
    5991             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i8_shift,
    5992             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    5993             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    5994             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    5995             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    5996             :         GIR_EraseFromParent, /*InsnID*/0,
    5997             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5998             :         GIR_Done,
    5999             :       // Label 205: @13190
    6000             :       GIM_Try, /*On fail goto*//*Label 206*/ 13271,
    6001             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6002             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6003             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6004             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6005             :         // No instruction predicates
    6006             :         // MIs[0] dst
    6007             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    6008             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6009             :         // MIs[0] Operand 1
    6010             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6011             :         // MIs[0] Rd
    6012             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    6013             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6014             :         // MIs[0] Rn
    6015             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    6016             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6017             :         // MIs[0] imm
    6018             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6019             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6020             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8,
    6021             :         // MIs[1] Operand 0
    6022             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6023             :         // MIs[1] Operand 1
    6024             :         // No operand predicates
    6025             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6026             :         // (intrinsic_wo_chain:{ *:[v16i8] } 354:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SRIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
    6027             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv16i8_shift,
    6028             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6029             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6030             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6031             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6032             :         GIR_EraseFromParent, /*InsnID*/0,
    6033             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6034             :         GIR_Done,
    6035             :       // Label 206: @13271
    6036             :       GIM_Try, /*On fail goto*//*Label 207*/ 13352,
    6037             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6038             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6039             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6040             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6041             :         // No instruction predicates
    6042             :         // MIs[0] dst
    6043             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6044             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6045             :         // MIs[0] Operand 1
    6046             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6047             :         // MIs[0] Rd
    6048             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    6049             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6050             :         // MIs[0] Rn
    6051             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    6052             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6053             :         // MIs[0] imm
    6054             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6055             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6056             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16,
    6057             :         // MIs[1] Operand 0
    6058             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6059             :         // MIs[1] Operand 1
    6060             :         // No operand predicates
    6061             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6062             :         // (intrinsic_wo_chain:{ *:[v4i16] } 354:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SRIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6063             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i16_shift,
    6064             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6065             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6066             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6067             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6068             :         GIR_EraseFromParent, /*InsnID*/0,
    6069             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6070             :         GIR_Done,
    6071             :       // Label 207: @13352
    6072             :       GIM_Try, /*On fail goto*//*Label 208*/ 13433,
    6073             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6074             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6075             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6076             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6077             :         // No instruction predicates
    6078             :         // MIs[0] dst
    6079             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    6080             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6081             :         // MIs[0] Operand 1
    6082             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6083             :         // MIs[0] Rd
    6084             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6085             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6086             :         // MIs[0] Rn
    6087             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    6088             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6089             :         // MIs[0] imm
    6090             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6091             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6092             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16,
    6093             :         // MIs[1] Operand 0
    6094             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6095             :         // MIs[1] Operand 1
    6096             :         // No operand predicates
    6097             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6098             :         // (intrinsic_wo_chain:{ *:[v8i16] } 354:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SRIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6099             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i16_shift,
    6100             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6101             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6102             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6103             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6104             :         GIR_EraseFromParent, /*InsnID*/0,
    6105             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6106             :         GIR_Done,
    6107             :       // Label 208: @13433
    6108             :       GIM_Try, /*On fail goto*//*Label 209*/ 13514,
    6109             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6110             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6111             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6112             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6113             :         // No instruction predicates
    6114             :         // MIs[0] dst
    6115             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6116             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6117             :         // MIs[0] Operand 1
    6118             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6119             :         // MIs[0] Rd
    6120             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6121             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6122             :         // MIs[0] Rn
    6123             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6124             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6125             :         // MIs[0] imm
    6126             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6127             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6128             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6129             :         // MIs[1] Operand 0
    6130             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6131             :         // MIs[1] Operand 1
    6132             :         // No operand predicates
    6133             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6134             :         // (intrinsic_wo_chain:{ *:[v2i32] } 354:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SRIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6135             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i32_shift,
    6136             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6137             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6138             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6139             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6140             :         GIR_EraseFromParent, /*InsnID*/0,
    6141             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6142             :         GIR_Done,
    6143             :       // Label 209: @13514
    6144             :       GIM_Try, /*On fail goto*//*Label 210*/ 13595,
    6145             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6146             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6147             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6148             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6149             :         // No instruction predicates
    6150             :         // MIs[0] dst
    6151             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6152             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6153             :         // MIs[0] Operand 1
    6154             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6155             :         // MIs[0] Rd
    6156             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6157             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6158             :         // MIs[0] Rn
    6159             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6160             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6161             :         // MIs[0] imm
    6162             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6163             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6164             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6165             :         // MIs[1] Operand 0
    6166             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6167             :         // MIs[1] Operand 1
    6168             :         // No operand predicates
    6169             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6170             :         // (intrinsic_wo_chain:{ *:[v4i32] } 354:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SRIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6171             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i32_shift,
    6172             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6173             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6174             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6175             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6176             :         GIR_EraseFromParent, /*InsnID*/0,
    6177             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6178             :         GIR_Done,
    6179             :       // Label 210: @13595
    6180             :       GIM_Try, /*On fail goto*//*Label 211*/ 13676,
    6181             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6182             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6183             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6184             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6185             :         // No instruction predicates
    6186             :         // MIs[0] dst
    6187             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    6188             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    6189             :         // MIs[0] Operand 1
    6190             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6191             :         // MIs[0] Rd
    6192             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6193             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6194             :         // MIs[0] Rn
    6195             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    6196             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    6197             :         // MIs[0] imm
    6198             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6199             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6200             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    6201             :         // MIs[1] Operand 0
    6202             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6203             :         // MIs[1] Operand 1
    6204             :         // No operand predicates
    6205             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6206             :         // (intrinsic_wo_chain:{ *:[v2i64] } 354:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6207             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i64_shift,
    6208             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6209             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6210             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6211             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6212             :         GIR_EraseFromParent, /*InsnID*/0,
    6213             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6214             :         GIR_Done,
    6215             :       // Label 211: @13676
    6216             :       GIM_Try, /*On fail goto*//*Label 212*/ 13755,
    6217             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6218             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6219             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6220             :         // No instruction predicates
    6221             :         // MIs[0] dst
    6222             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    6223             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6224             :         // MIs[0] Operand 1
    6225             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli,
    6226             :         // MIs[0] Rd
    6227             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6228             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6229             :         // MIs[0] Rn
    6230             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    6231             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6232             :         // MIs[0] imm
    6233             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6234             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6235             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL64,
    6236             :         // MIs[1] Operand 0
    6237             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6238             :         // MIs[1] Operand 1
    6239             :         // No operand predicates
    6240             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6241             :         // (intrinsic_wo_chain:{ *:[v1i64] } 353:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SLId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)
    6242             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLId,
    6243             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6244             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6245             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6246             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6247             :         GIR_EraseFromParent, /*InsnID*/0,
    6248             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6249             :         GIR_Done,
    6250             :       // Label 212: @13755
    6251             :       GIM_Try, /*On fail goto*//*Label 213*/ 13834,
    6252             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    6253             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
    6254             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6255             :         // No instruction predicates
    6256             :         // MIs[0] dst
    6257             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    6258             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6259             :         // MIs[0] Operand 1
    6260             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri,
    6261             :         // MIs[0] Rd
    6262             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6263             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6264             :         // MIs[0] Rn
    6265             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    6266             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    6267             :         // MIs[0] imm
    6268             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    6269             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6270             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    6271             :         // MIs[1] Operand 0
    6272             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6273             :         // MIs[1] Operand 1
    6274             :         // No operand predicates
    6275             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6276             :         // (intrinsic_wo_chain:{ *:[v1i64] } 354:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    6277             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRId,
    6278             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    6279             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    6280             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    6281             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6282             :         GIR_EraseFromParent, /*InsnID*/0,
    6283             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6284             :         GIR_Done,
    6285             :       // Label 213: @13834
    6286             :       GIM_Try, /*On fail goto*//*Label 214*/ 13903,
    6287             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6288             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6289             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6290             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6291             :         // No instruction predicates
    6292             :         // MIs[0] Rd
    6293             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6294             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6295             :         // MIs[0] Operand 1
    6296             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn,
    6297             :         // MIs[0] Rn
    6298             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6299             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6300             :         // MIs[0] imm
    6301             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6302             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6303             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6304             :         // MIs[1] Operand 0
    6305             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6306             :         // MIs[1] Operand 1
    6307             :         // No operand predicates
    6308             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6309             :         // (intrinsic_wo_chain:{ *:[i32] } 287:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6310             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNs,
    6311             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6312             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6313             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6314             :         GIR_EraseFromParent, /*InsnID*/0,
    6315             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6316             :         GIR_Done,
    6317             :       // Label 214: @13903
    6318             :       GIM_Try, /*On fail goto*//*Label 215*/ 13972,
    6319             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6320             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6321             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6322             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6323             :         // No instruction predicates
    6324             :         // MIs[0] Rd
    6325             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6326             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6327             :         // MIs[0] Operand 1
    6328             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun,
    6329             :         // MIs[0] Rn
    6330             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6331             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6332             :         // MIs[0] imm
    6333             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6334             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6335             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6336             :         // MIs[1] Operand 0
    6337             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6338             :         // MIs[1] Operand 1
    6339             :         // No operand predicates
    6340             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6341             :         // (intrinsic_wo_chain:{ *:[i32] } 288:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6342             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNs,
    6343             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6344             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6345             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6346             :         GIR_EraseFromParent, /*InsnID*/0,
    6347             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6348             :         GIR_Done,
    6349             :       // Label 215: @13972
    6350             :       GIM_Try, /*On fail goto*//*Label 216*/ 14041,
    6351             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6352             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6353             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6354             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6355             :         // No instruction predicates
    6356             :         // MIs[0] Rd
    6357             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6358             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6359             :         // MIs[0] Operand 1
    6360             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn,
    6361             :         // MIs[0] Rn
    6362             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6363             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6364             :         // MIs[0] imm
    6365             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6366             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6367             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6368             :         // MIs[1] Operand 0
    6369             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6370             :         // MIs[1] Operand 1
    6371             :         // No operand predicates
    6372             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6373             :         // (intrinsic_wo_chain:{ *:[i32] } 291:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6374             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNs,
    6375             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6376             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6377             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6378             :         GIR_EraseFromParent, /*InsnID*/0,
    6379             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6380             :         GIR_Done,
    6381             :       // Label 216: @14041
    6382             :       GIM_Try, /*On fail goto*//*Label 217*/ 14110,
    6383             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6384             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6385             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6386             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6387             :         // No instruction predicates
    6388             :         // MIs[0] Rd
    6389             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6390             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6391             :         // MIs[0] Operand 1
    6392             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun,
    6393             :         // MIs[0] Rn
    6394             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6395             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6396             :         // MIs[0] imm
    6397             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6398             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6399             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6400             :         // MIs[1] Operand 0
    6401             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6402             :         // MIs[1] Operand 1
    6403             :         // No operand predicates
    6404             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6405             :         // (intrinsic_wo_chain:{ *:[i32] } 292:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6406             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNs,
    6407             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6408             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6409             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6410             :         GIR_EraseFromParent, /*InsnID*/0,
    6411             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6412             :         GIR_Done,
    6413             :       // Label 217: @14110
    6414             :       GIM_Try, /*On fail goto*//*Label 218*/ 14179,
    6415             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6416             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6417             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6418             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6419             :         // No instruction predicates
    6420             :         // MIs[0] Rd
    6421             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6422             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6423             :         // MIs[0] Operand 1
    6424             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn,
    6425             :         // MIs[0] Rn
    6426             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6427             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6428             :         // MIs[0] imm
    6429             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6430             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6431             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6432             :         // MIs[1] Operand 0
    6433             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6434             :         // MIs[1] Operand 1
    6435             :         // No operand predicates
    6436             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6437             :         // (intrinsic_wo_chain:{ *:[i32] } 334:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6438             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNs,
    6439             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6440             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6441             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6442             :         GIR_EraseFromParent, /*InsnID*/0,
    6443             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6444             :         GIR_Done,
    6445             :       // Label 218: @14179
    6446             :       GIM_Try, /*On fail goto*//*Label 219*/ 14248,
    6447             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6448             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6449             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6450             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6451             :         // No instruction predicates
    6452             :         // MIs[0] Rd
    6453             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    6454             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    6455             :         // MIs[0] Operand 1
    6456             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn,
    6457             :         // MIs[0] Rn
    6458             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6459             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    6460             :         // MIs[0] imm
    6461             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6462             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6463             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    6464             :         // MIs[1] Operand 0
    6465             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6466             :         // MIs[1] Operand 1
    6467             :         // No operand predicates
    6468             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6469             :         // (intrinsic_wo_chain:{ *:[i32] } 336:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6470             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNs,
    6471             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6472             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6473             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6474             :         GIR_EraseFromParent, /*InsnID*/0,
    6475             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6476             :         GIR_Done,
    6477             :       // Label 219: @14248
    6478             :       GIM_Try, /*On fail goto*//*Label 220*/ 14317,
    6479             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6480             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6481             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6482             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6483             :         // No instruction predicates
    6484             :         // MIs[0] Rd
    6485             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6486             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6487             :         // MIs[0] Operand 1
    6488             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn,
    6489             :         // MIs[0] Rn
    6490             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6491             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6492             :         // MIs[0] imm
    6493             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6494             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6495             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6496             :         // MIs[1] Operand 0
    6497             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6498             :         // MIs[1] Operand 1
    6499             :         // No operand predicates
    6500             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6501             :         // (intrinsic_wo_chain:{ *:[v8i8] } 260:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (RSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6502             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i8_shift,
    6503             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6504             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6505             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6506             :         GIR_EraseFromParent, /*InsnID*/0,
    6507             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6508             :         GIR_Done,
    6509             :       // Label 220: @14317
    6510             :       GIM_Try, /*On fail goto*//*Label 221*/ 14386,
    6511             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6512             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6513             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6514             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6515             :         // No instruction predicates
    6516             :         // MIs[0] Rd
    6517             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6518             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6519             :         // MIs[0] Operand 1
    6520             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn,
    6521             :         // MIs[0] Rn
    6522             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6523             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6524             :         // MIs[0] imm
    6525             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6526             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6527             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6528             :         // MIs[1] Operand 0
    6529             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6530             :         // MIs[1] Operand 1
    6531             :         // No operand predicates
    6532             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6533             :         // (intrinsic_wo_chain:{ *:[v4i16] } 260:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (RSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6534             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i16_shift,
    6535             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6536             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6537             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6538             :         GIR_EraseFromParent, /*InsnID*/0,
    6539             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6540             :         GIR_Done,
    6541             :       // Label 221: @14386
    6542             :       GIM_Try, /*On fail goto*//*Label 222*/ 14455,
    6543             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6544             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6545             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6546             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6547             :         // No instruction predicates
    6548             :         // MIs[0] Rd
    6549             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6550             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6551             :         // MIs[0] Operand 1
    6552             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn,
    6553             :         // MIs[0] Rn
    6554             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6555             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6556             :         // MIs[0] imm
    6557             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6558             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6559             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    6560             :         // MIs[1] Operand 0
    6561             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6562             :         // MIs[1] Operand 1
    6563             :         // No operand predicates
    6564             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6565             :         // (intrinsic_wo_chain:{ *:[v2i32] } 260:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (RSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6566             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv2i32_shift,
    6567             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6568             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6569             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6570             :         GIR_EraseFromParent, /*InsnID*/0,
    6571             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6572             :         GIR_Done,
    6573             :       // Label 222: @14455
    6574             :       GIM_Try, /*On fail goto*//*Label 223*/ 14524,
    6575             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6576             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6577             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6578             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6579             :         // No instruction predicates
    6580             :         // MIs[0] Rd
    6581             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6582             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6583             :         // MIs[0] Operand 1
    6584             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn,
    6585             :         // MIs[0] Rn
    6586             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6587             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6588             :         // MIs[0] imm
    6589             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6590             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6591             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6592             :         // MIs[1] Operand 0
    6593             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6594             :         // MIs[1] Operand 1
    6595             :         // No operand predicates
    6596             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6597             :         // (intrinsic_wo_chain:{ *:[v8i8] } 287:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (SQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6598             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i8_shift,
    6599             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6600             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6601             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6602             :         GIR_EraseFromParent, /*InsnID*/0,
    6603             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6604             :         GIR_Done,
    6605             :       // Label 223: @14524
    6606             :       GIM_Try, /*On fail goto*//*Label 224*/ 14593,
    6607             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6608             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6609             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6610             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6611             :         // No instruction predicates
    6612             :         // MIs[0] Rd
    6613             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6614             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6615             :         // MIs[0] Operand 1
    6616             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn,
    6617             :         // MIs[0] Rn
    6618             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6619             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6620             :         // MIs[0] imm
    6621             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6622             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6623             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6624             :         // MIs[1] Operand 0
    6625             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6626             :         // MIs[1] Operand 1
    6627             :         // No operand predicates
    6628             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6629             :         // (intrinsic_wo_chain:{ *:[v4i16] } 287:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (SQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6630             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i16_shift,
    6631             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6632             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6633             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6634             :         GIR_EraseFromParent, /*InsnID*/0,
    6635             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6636             :         GIR_Done,
    6637             :       // Label 224: @14593
    6638             :       GIM_Try, /*On fail goto*//*Label 225*/ 14662,
    6639             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6640             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6641             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6642             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6643             :         // No instruction predicates
    6644             :         // MIs[0] Rd
    6645             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6646             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6647             :         // MIs[0] Operand 1
    6648             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn,
    6649             :         // MIs[0] Rn
    6650             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6651             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6652             :         // MIs[0] imm
    6653             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6654             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6655             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    6656             :         // MIs[1] Operand 0
    6657             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6658             :         // MIs[1] Operand 1
    6659             :         // No operand predicates
    6660             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6661             :         // (intrinsic_wo_chain:{ *:[v2i32] } 287:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (SQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6662             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv2i32_shift,
    6663             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6664             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6665             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6666             :         GIR_EraseFromParent, /*InsnID*/0,
    6667             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6668             :         GIR_Done,
    6669             :       // Label 225: @14662
    6670             :       GIM_Try, /*On fail goto*//*Label 226*/ 14731,
    6671             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6672             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6673             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6674             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6675             :         // No instruction predicates
    6676             :         // MIs[0] Rd
    6677             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6678             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6679             :         // MIs[0] Operand 1
    6680             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun,
    6681             :         // MIs[0] Rn
    6682             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6683             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6684             :         // MIs[0] imm
    6685             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6686             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6687             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6688             :         // MIs[1] Operand 0
    6689             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6690             :         // MIs[1] Operand 1
    6691             :         // No operand predicates
    6692             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6693             :         // (intrinsic_wo_chain:{ *:[v8i8] } 288:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (SQRSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6694             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i8_shift,
    6695             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6696             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6697             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6698             :         GIR_EraseFromParent, /*InsnID*/0,
    6699             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6700             :         GIR_Done,
    6701             :       // Label 226: @14731
    6702             :       GIM_Try, /*On fail goto*//*Label 227*/ 14800,
    6703             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6704             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6705             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6706             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6707             :         // No instruction predicates
    6708             :         // MIs[0] Rd
    6709             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6710             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6711             :         // MIs[0] Operand 1
    6712             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun,
    6713             :         // MIs[0] Rn
    6714             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6715             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6716             :         // MIs[0] imm
    6717             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6718             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6719             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6720             :         // MIs[1] Operand 0
    6721             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6722             :         // MIs[1] Operand 1
    6723             :         // No operand predicates
    6724             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6725             :         // (intrinsic_wo_chain:{ *:[v4i16] } 288:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (SQRSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6726             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i16_shift,
    6727             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6728             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6729             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6730             :         GIR_EraseFromParent, /*InsnID*/0,
    6731             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6732             :         GIR_Done,
    6733             :       // Label 227: @14800
    6734             :       GIM_Try, /*On fail goto*//*Label 228*/ 14869,
    6735             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6736             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6737             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6738             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6739             :         // No instruction predicates
    6740             :         // MIs[0] Rd
    6741             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6742             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6743             :         // MIs[0] Operand 1
    6744             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun,
    6745             :         // MIs[0] Rn
    6746             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6747             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6748             :         // MIs[0] imm
    6749             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6750             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6751             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    6752             :         // MIs[1] Operand 0
    6753             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6754             :         // MIs[1] Operand 1
    6755             :         // No operand predicates
    6756             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6757             :         // (intrinsic_wo_chain:{ *:[v2i32] } 288:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (SQRSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6758             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv2i32_shift,
    6759             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6760             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6761             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6762             :         GIR_EraseFromParent, /*InsnID*/0,
    6763             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6764             :         GIR_Done,
    6765             :       // Label 228: @14869
    6766             :       GIM_Try, /*On fail goto*//*Label 229*/ 14938,
    6767             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6768             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6769             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6770             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6771             :         // No instruction predicates
    6772             :         // MIs[0] Rd
    6773             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6774             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6775             :         // MIs[0] Operand 1
    6776             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn,
    6777             :         // MIs[0] Rn
    6778             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6779             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6780             :         // MIs[0] imm
    6781             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6782             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6783             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6784             :         // MIs[1] Operand 0
    6785             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6786             :         // MIs[1] Operand 1
    6787             :         // No operand predicates
    6788             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6789             :         // (intrinsic_wo_chain:{ *:[v8i8] } 291:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (SQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6790             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i8_shift,
    6791             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6792             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6793             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6794             :         GIR_EraseFromParent, /*InsnID*/0,
    6795             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6796             :         GIR_Done,
    6797             :       // Label 229: @14938
    6798             :       GIM_Try, /*On fail goto*//*Label 230*/ 15007,
    6799             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6800             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6801             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6802             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6803             :         // No instruction predicates
    6804             :         // MIs[0] Rd
    6805             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6806             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6807             :         // MIs[0] Operand 1
    6808             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn,
    6809             :         // MIs[0] Rn
    6810             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6811             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6812             :         // MIs[0] imm
    6813             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6814             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6815             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6816             :         // MIs[1] Operand 0
    6817             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6818             :         // MIs[1] Operand 1
    6819             :         // No operand predicates
    6820             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6821             :         // (intrinsic_wo_chain:{ *:[v4i16] } 291:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (SQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6822             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i16_shift,
    6823             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6824             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6825             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6826             :         GIR_EraseFromParent, /*InsnID*/0,
    6827             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6828             :         GIR_Done,
    6829             :       // Label 230: @15007
    6830             :       GIM_Try, /*On fail goto*//*Label 231*/ 15076,
    6831             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6832             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6833             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6834             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6835             :         // No instruction predicates
    6836             :         // MIs[0] Rd
    6837             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6838             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6839             :         // MIs[0] Operand 1
    6840             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn,
    6841             :         // MIs[0] Rn
    6842             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6843             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6844             :         // MIs[0] imm
    6845             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6846             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6847             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    6848             :         // MIs[1] Operand 0
    6849             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6850             :         // MIs[1] Operand 1
    6851             :         // No operand predicates
    6852             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6853             :         // (intrinsic_wo_chain:{ *:[v2i32] } 291:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (SQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6854             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv2i32_shift,
    6855             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6856             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6857             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6858             :         GIR_EraseFromParent, /*InsnID*/0,
    6859             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6860             :         GIR_Done,
    6861             :       // Label 231: @15076
    6862             :       GIM_Try, /*On fail goto*//*Label 232*/ 15145,
    6863             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6864             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6865             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6866             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6867             :         // No instruction predicates
    6868             :         // MIs[0] Rd
    6869             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6870             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6871             :         // MIs[0] Operand 1
    6872             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun,
    6873             :         // MIs[0] Rn
    6874             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6875             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6876             :         // MIs[0] imm
    6877             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6878             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6879             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6880             :         // MIs[1] Operand 0
    6881             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6882             :         // MIs[1] Operand 1
    6883             :         // No operand predicates
    6884             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6885             :         // (intrinsic_wo_chain:{ *:[v8i8] } 292:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (SQSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6886             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i8_shift,
    6887             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6888             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6889             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6890             :         GIR_EraseFromParent, /*InsnID*/0,
    6891             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6892             :         GIR_Done,
    6893             :       // Label 232: @15145
    6894             :       GIM_Try, /*On fail goto*//*Label 233*/ 15214,
    6895             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6896             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6897             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6898             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6899             :         // No instruction predicates
    6900             :         // MIs[0] Rd
    6901             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6902             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6903             :         // MIs[0] Operand 1
    6904             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun,
    6905             :         // MIs[0] Rn
    6906             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6907             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6908             :         // MIs[0] imm
    6909             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6910             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6911             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    6912             :         // MIs[1] Operand 0
    6913             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6914             :         // MIs[1] Operand 1
    6915             :         // No operand predicates
    6916             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6917             :         // (intrinsic_wo_chain:{ *:[v4i16] } 292:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (SQSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    6918             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i16_shift,
    6919             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6920             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6921             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6922             :         GIR_EraseFromParent, /*InsnID*/0,
    6923             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6924             :         GIR_Done,
    6925             :       // Label 233: @15214
    6926             :       GIM_Try, /*On fail goto*//*Label 234*/ 15283,
    6927             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6928             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6929             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6930             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6931             :         // No instruction predicates
    6932             :         // MIs[0] Rd
    6933             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6934             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6935             :         // MIs[0] Operand 1
    6936             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun,
    6937             :         // MIs[0] Rn
    6938             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6939             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6940             :         // MIs[0] imm
    6941             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6942             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6943             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    6944             :         // MIs[1] Operand 0
    6945             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6946             :         // MIs[1] Operand 1
    6947             :         // No operand predicates
    6948             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6949             :         // (intrinsic_wo_chain:{ *:[v2i32] } 292:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (SQSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    6950             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv2i32_shift,
    6951             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6952             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6953             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6954             :         GIR_EraseFromParent, /*InsnID*/0,
    6955             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6956             :         GIR_Done,
    6957             :       // Label 234: @15283
    6958             :       GIM_Try, /*On fail goto*//*Label 235*/ 15352,
    6959             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6960             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6961             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6962             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6963             :         // No instruction predicates
    6964             :         // MIs[0] Rd
    6965             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6966             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6967             :         // MIs[0] Operand 1
    6968             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn,
    6969             :         // MIs[0] Rn
    6970             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6971             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    6972             :         // MIs[0] imm
    6973             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    6974             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    6975             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    6976             :         // MIs[1] Operand 0
    6977             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    6978             :         // MIs[1] Operand 1
    6979             :         // No operand predicates
    6980             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    6981             :         // (intrinsic_wo_chain:{ *:[v8i8] } 334:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (UQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    6982             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i8_shift,
    6983             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    6984             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    6985             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    6986             :         GIR_EraseFromParent, /*InsnID*/0,
    6987             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6988             :         GIR_Done,
    6989             :       // Label 235: @15352
    6990             :       GIM_Try, /*On fail goto*//*Label 236*/ 15421,
    6991             :         GIM_CheckFeatures, GIFBS_HasNEON,
    6992             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6993             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    6994             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    6995             :         // No instruction predicates
    6996             :         // MIs[0] Rd
    6997             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6998             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    6999             :         // MIs[0] Operand 1
    7000             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn,
    7001             :         // MIs[0] Rn
    7002             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7003             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7004             :         // MIs[0] imm
    7005             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7006             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7007             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    7008             :         // MIs[1] Operand 0
    7009             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7010             :         // MIs[1] Operand 1
    7011             :         // No operand predicates
    7012             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7013             :         // (intrinsic_wo_chain:{ *:[v4i16] } 334:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (UQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7014             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i16_shift,
    7015             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7016             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7017             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7018             :         GIR_EraseFromParent, /*InsnID*/0,
    7019             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7020             :         GIR_Done,
    7021             :       // Label 236: @15421
    7022             :       GIM_Try, /*On fail goto*//*Label 237*/ 15490,
    7023             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7024             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7025             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7026             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7027             :         // No instruction predicates
    7028             :         // MIs[0] Rd
    7029             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7030             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7031             :         // MIs[0] Operand 1
    7032             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn,
    7033             :         // MIs[0] Rn
    7034             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7035             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7036             :         // MIs[0] imm
    7037             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7038             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7039             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    7040             :         // MIs[1] Operand 0
    7041             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7042             :         // MIs[1] Operand 1
    7043             :         // No operand predicates
    7044             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7045             :         // (intrinsic_wo_chain:{ *:[v2i32] } 334:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (UQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    7046             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv2i32_shift,
    7047             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7048             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7049             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7050             :         GIR_EraseFromParent, /*InsnID*/0,
    7051             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7052             :         GIR_Done,
    7053             :       // Label 237: @15490
    7054             :       GIM_Try, /*On fail goto*//*Label 238*/ 15559,
    7055             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7056             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7057             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7058             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7059             :         // No instruction predicates
    7060             :         // MIs[0] Rd
    7061             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7062             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7063             :         // MIs[0] Operand 1
    7064             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn,
    7065             :         // MIs[0] Rn
    7066             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7067             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7068             :         // MIs[0] imm
    7069             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7070             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7071             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow,
    7072             :         // MIs[1] Operand 0
    7073             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7074             :         // MIs[1] Operand 1
    7075             :         // No operand predicates
    7076             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7077             :         // (intrinsic_wo_chain:{ *:[v8i8] } 336:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (UQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7078             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i8_shift,
    7079             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7080             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7081             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7082             :         GIR_EraseFromParent, /*InsnID*/0,
    7083             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7084             :         GIR_Done,
    7085             :       // Label 238: @15559
    7086             :       GIM_Try, /*On fail goto*//*Label 239*/ 15628,
    7087             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7088             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7089             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7090             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7091             :         // No instruction predicates
    7092             :         // MIs[0] Rd
    7093             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7094             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7095             :         // MIs[0] Operand 1
    7096             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn,
    7097             :         // MIs[0] Rn
    7098             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7099             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7100             :         // MIs[0] imm
    7101             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7102             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7103             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow,
    7104             :         // MIs[1] Operand 0
    7105             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7106             :         // MIs[1] Operand 1
    7107             :         // No operand predicates
    7108             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7109             :         // (intrinsic_wo_chain:{ *:[v4i16] } 336:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (UQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7110             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i16_shift,
    7111             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7112             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7113             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7114             :         GIR_EraseFromParent, /*InsnID*/0,
    7115             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7116             :         GIR_Done,
    7117             :       // Label 239: @15628
    7118             :       GIM_Try, /*On fail goto*//*Label 240*/ 15697,
    7119             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7120             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7121             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7122             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7123             :         // No instruction predicates
    7124             :         // MIs[0] Rd
    7125             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7126             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7127             :         // MIs[0] Operand 1
    7128             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn,
    7129             :         // MIs[0] Rn
    7130             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7131             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7132             :         // MIs[0] imm
    7133             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7134             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7135             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow,
    7136             :         // MIs[1] Operand 0
    7137             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7138             :         // MIs[1] Operand 1
    7139             :         // No operand predicates
    7140             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7141             :         // (intrinsic_wo_chain:{ *:[v2i32] } 336:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (UQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    7142             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv2i32_shift,
    7143             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7144             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7145             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7146             :         GIR_EraseFromParent, /*InsnID*/0,
    7147             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7148             :         GIR_Done,
    7149             :       // Label 240: @15697
    7150             :       GIM_Try, /*On fail goto*//*Label 241*/ 15764,
    7151             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7152             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7153             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7154             :         // No instruction predicates
    7155             :         // MIs[0] Rd
    7156             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7157             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    7158             :         // MIs[0] Operand 1
    7159             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7160             :         // MIs[0] Rn
    7161             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7162             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    7163             :         // MIs[0] imm
    7164             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7165             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7166             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    7167             :         // MIs[1] Operand 0
    7168             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7169             :         // MIs[1] Operand 1
    7170             :         // No operand predicates
    7171             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7172             :         // (intrinsic_wo_chain:{ *:[i32] } 347:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
    7173             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSs,
    7174             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7175             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7176             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7177             :         GIR_EraseFromParent, /*InsnID*/0,
    7178             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7179             :         GIR_Done,
    7180             :       // Label 241: @15764
    7181             :       GIM_Try, /*On fail goto*//*Label 242*/ 15831,
    7182             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7183             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7184             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7185             :         // No instruction predicates
    7186             :         // MIs[0] Rd
    7187             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7188             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    7189             :         // MIs[0] Operand 1
    7190             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7191             :         // MIs[0] Rn
    7192             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7193             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    7194             :         // MIs[0] imm
    7195             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7196             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7197             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    7198             :         // MIs[1] Operand 0
    7199             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7200             :         // MIs[1] Operand 1
    7201             :         // No operand predicates
    7202             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7203             :         // (intrinsic_wo_chain:{ *:[i32] } 348:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
    7204             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUs,
    7205             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7206             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7207             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7208             :         GIR_EraseFromParent, /*InsnID*/0,
    7209             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7210             :         GIR_Done,
    7211             :       // Label 242: @15831
    7212             :       GIM_Try, /*On fail goto*//*Label 243*/ 15898,
    7213             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7214             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7215             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7216             :         // No instruction predicates
    7217             :         // MIs[0] Rd
    7218             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7219             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7220             :         // MIs[0] Operand 1
    7221             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7222             :         // MIs[0] Rn
    7223             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7224             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7225             :         // MIs[0] imm
    7226             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7227             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7228             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7229             :         // MIs[1] Operand 0
    7230             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7231             :         // MIs[1] Operand 1
    7232             :         // No operand predicates
    7233             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7234             :         // (intrinsic_wo_chain:{ *:[i64] } 347:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7235             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd,
    7236             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7237             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7238             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7239             :         GIR_EraseFromParent, /*InsnID*/0,
    7240             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7241             :         GIR_Done,
    7242             :       // Label 243: @15898
    7243             :       GIM_Try, /*On fail goto*//*Label 244*/ 15965,
    7244             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7245             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7246             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7247             :         // No instruction predicates
    7248             :         // MIs[0] Rd
    7249             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7250             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7251             :         // MIs[0] Operand 1
    7252             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7253             :         // MIs[0] Rn
    7254             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7255             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7256             :         // MIs[0] imm
    7257             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7258             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7259             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7260             :         // MIs[1] Operand 0
    7261             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7262             :         // MIs[1] Operand 1
    7263             :         // No operand predicates
    7264             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7265             :         // (intrinsic_wo_chain:{ *:[i64] } 348:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7266             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd,
    7267             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7268             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7269             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7270             :         GIR_EraseFromParent, /*InsnID*/0,
    7271             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7272             :         GIR_Done,
    7273             :       // Label 244: @15965
    7274             :       GIM_Try, /*On fail goto*//*Label 245*/ 16032,
    7275             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7276             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7277             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7278             :         // No instruction predicates
    7279             :         // MIs[0] Rd
    7280             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7281             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7282             :         // MIs[0] Operand 1
    7283             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7284             :         // MIs[0] Rn
    7285             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7286             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7287             :         // MIs[0] imm
    7288             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7289             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7290             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7291             :         // MIs[1] Operand 0
    7292             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7293             :         // MIs[1] Operand 1
    7294             :         // No operand predicates
    7295             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7296             :         // (intrinsic_wo_chain:{ *:[v1i64] } 347:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7297             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd,
    7298             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7299             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7300             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7301             :         GIR_EraseFromParent, /*InsnID*/0,
    7302             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7303             :         GIR_Done,
    7304             :       // Label 245: @16032
    7305             :       GIM_Try, /*On fail goto*//*Label 246*/ 16099,
    7306             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7307             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7308             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7309             :         // No instruction predicates
    7310             :         // MIs[0] Rd
    7311             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7312             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7313             :         // MIs[0] Operand 1
    7314             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7315             :         // MIs[0] Rn
    7316             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7317             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7318             :         // MIs[0] imm
    7319             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7320             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7321             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7322             :         // MIs[1] Operand 0
    7323             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7324             :         // MIs[1] Operand 1
    7325             :         // No operand predicates
    7326             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7327             :         // (intrinsic_wo_chain:{ *:[v1i64] } 348:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7328             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd,
    7329             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7330             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7331             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7332             :         GIR_EraseFromParent, /*InsnID*/0,
    7333             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7334             :         GIR_Done,
    7335             :       // Label 246: @16099
    7336             :       GIM_Try, /*On fail goto*//*Label 247*/ 16166,
    7337             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7338             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7339             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7340             :         // No instruction predicates
    7341             :         // MIs[0] Rd
    7342             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7343             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    7344             :         // MIs[0] Operand 1
    7345             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    7346             :         // MIs[0] Rn
    7347             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7348             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    7349             :         // MIs[0] imm
    7350             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7351             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7352             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    7353             :         // MIs[1] Operand 0
    7354             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7355             :         // MIs[1] Operand 1
    7356             :         // No operand predicates
    7357             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7358             :         // (intrinsic_wo_chain:{ *:[f32] } 350:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
    7359             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFs,
    7360             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7361             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7362             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7363             :         GIR_EraseFromParent, /*InsnID*/0,
    7364             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7365             :         GIR_Done,
    7366             :       // Label 247: @16166
    7367             :       GIM_Try, /*On fail goto*//*Label 248*/ 16233,
    7368             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7369             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7370             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7371             :         // No instruction predicates
    7372             :         // MIs[0] Rd
    7373             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7374             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID,
    7375             :         // MIs[0] Operand 1
    7376             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    7377             :         // MIs[0] Rn
    7378             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7379             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID,
    7380             :         // MIs[0] imm
    7381             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7382             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7383             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32,
    7384             :         // MIs[1] Operand 0
    7385             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7386             :         // MIs[1] Operand 1
    7387             :         // No operand predicates
    7388             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7389             :         // (intrinsic_wo_chain:{ *:[f32] } 351:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
    7390             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFs,
    7391             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7392             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7393             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7394             :         GIR_EraseFromParent, /*InsnID*/0,
    7395             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7396             :         GIR_Done,
    7397             :       // Label 248: @16233
    7398             :       GIM_Try, /*On fail goto*//*Label 249*/ 16300,
    7399             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7400             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7401             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7402             :         // No instruction predicates
    7403             :         // MIs[0] Rd
    7404             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7405             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7406             :         // MIs[0] Operand 1
    7407             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    7408             :         // MIs[0] Rn
    7409             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7410             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7411             :         // MIs[0] imm
    7412             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7413             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7414             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7415             :         // MIs[1] Operand 0
    7416             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7417             :         // MIs[1] Operand 1
    7418             :         // No operand predicates
    7419             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7420             :         // (intrinsic_wo_chain:{ *:[f64] } 350:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7421             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd,
    7422             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7423             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7424             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7425             :         GIR_EraseFromParent, /*InsnID*/0,
    7426             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7427             :         GIR_Done,
    7428             :       // Label 249: @16300
    7429             :       GIM_Try, /*On fail goto*//*Label 250*/ 16367,
    7430             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7431             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7432             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7433             :         // No instruction predicates
    7434             :         // MIs[0] Rd
    7435             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7436             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7437             :         // MIs[0] Operand 1
    7438             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    7439             :         // MIs[0] Rn
    7440             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7441             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7442             :         // MIs[0] imm
    7443             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7444             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7445             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7446             :         // MIs[1] Operand 0
    7447             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7448             :         // MIs[1] Operand 1
    7449             :         // No operand predicates
    7450             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7451             :         // (intrinsic_wo_chain:{ *:[f64] } 351:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7452             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd,
    7453             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7454             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7455             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7456             :         GIR_EraseFromParent, /*InsnID*/0,
    7457             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7458             :         GIR_Done,
    7459             :       // Label 250: @16367
    7460             :       GIM_Try, /*On fail goto*//*Label 251*/ 16434,
    7461             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7462             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7463             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7464             :         // No instruction predicates
    7465             :         // MIs[0] Rd
    7466             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7467             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7468             :         // MIs[0] Operand 1
    7469             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    7470             :         // MIs[0] Rn
    7471             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7472             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7473             :         // MIs[0] imm
    7474             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7475             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7476             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7477             :         // MIs[1] Operand 0
    7478             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7479             :         // MIs[1] Operand 1
    7480             :         // No operand predicates
    7481             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7482             :         // (intrinsic_wo_chain:{ *:[v1f64] } 350:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7483             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd,
    7484             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7485             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7486             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7487             :         GIR_EraseFromParent, /*InsnID*/0,
    7488             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7489             :         GIR_Done,
    7490             :       // Label 251: @16434
    7491             :       GIM_Try, /*On fail goto*//*Label 252*/ 16501,
    7492             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7493             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7494             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7495             :         // No instruction predicates
    7496             :         // MIs[0] Rd
    7497             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7498             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7499             :         // MIs[0] Operand 1
    7500             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    7501             :         // MIs[0] Rn
    7502             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7503             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7504             :         // MIs[0] imm
    7505             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7506             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7507             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64,
    7508             :         // MIs[1] Operand 0
    7509             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7510             :         // MIs[1] Operand 1
    7511             :         // No operand predicates
    7512             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7513             :         // (intrinsic_wo_chain:{ *:[v1f64] } 351:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
    7514             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd,
    7515             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7516             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7517             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7518             :         GIR_EraseFromParent, /*InsnID*/0,
    7519             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7520             :         GIR_Done,
    7521             :       // Label 252: @16501
    7522             :       GIM_Reject,
    7523             :       GIR_Done,
    7524             :     // Label 197: @16503
    7525             :     GIM_Try, /*On fail goto*//*Label 253*/ 16608,
    7526             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
    7527             :       GIM_Try, /*On fail goto*//*Label 254*/ 16557,
    7528             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    7529             :         // No instruction predicates
    7530             :         // MIs[0] Rd
    7531             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    7532             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
    7533             :         // MIs[0] Rn
    7534             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7535             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
    7536             :         // MIs[0] imm
    7537             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    7538             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
    7539             :         // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
    7540             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
    7541             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7542             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    7543             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    7544             :         GIR_EraseFromParent, /*InsnID*/0,
    7545             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7546             :         GIR_Done,
    7547             :       // Label 254: @16557
    7548             :       GIM_Try, /*On fail goto*//*Label 255*/ 16606,
    7549             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    7550             :         // No instruction predicates
    7551             :         // MIs[0] Rd
    7552             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7553             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
    7554             :         // MIs[0] Rn
    7555             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    7556             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
    7557             :         // MIs[0] imm
    7558             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7559             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
    7560             :         // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
    7561             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
    7562             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7563             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
    7564             :         GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
    7565             :         GIR_EraseFromParent, /*InsnID*/0,
    7566             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7567             :         GIR_Done,
    7568             :       // Label 255: @16606
    7569             :       GIM_Reject,
    7570             :       GIR_Done,
    7571             :     // Label 253: @16608
    7572             :     GIM_Try, /*On fail goto*//*Label 256*/ 16807,
    7573             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS,
    7574             :       GIM_Try, /*On fail goto*//*Label 257*/ 16661,
    7575             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    7576             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    7577             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7578             :         // No instruction predicates
    7579             :         // MIs[0] Operand 0
    7580             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_hint,
    7581             :         // MIs[0] imm
    7582             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7583             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7584             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_127,
    7585             :         // MIs[1] Operand 0
    7586             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7587             :         // MIs[1] Operand 1
    7588             :         // No operand predicates
    7589             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7590             :         // (intrinsic_void 199:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_127>>:$imm)  =>  (HINT (imm:{ *:[i32] }):$imm)
    7591             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HINT,
    7592             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7593             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    7594             :         GIR_EraseFromParent, /*InsnID*/0,
    7595             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7596             :         GIR_Done,
    7597             :       // Label 257: @16661
    7598             :       GIM_Try, /*On fail goto*//*Label 258*/ 16709,
    7599             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    7600             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    7601             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7602             :         // No instruction predicates
    7603             :         // MIs[0] Operand 0
    7604             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dmb,
    7605             :         // MIs[0] CRm
    7606             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7607             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7608             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15,
    7609             :         // MIs[1] Operand 0
    7610             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7611             :         // MIs[1] Operand 1
    7612             :         // No operand predicates
    7613             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7614             :         // (intrinsic_void 197:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (DMB (imm:{ *:[i32] }):$CRm)
    7615             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB,
    7616             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
    7617             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    7618             :         GIR_EraseFromParent, /*InsnID*/0,
    7619             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7620             :         GIR_Done,
    7621             :       // Label 258: @16709
    7622             :       GIM_Try, /*On fail goto*//*Label 259*/ 16757,
    7623             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    7624             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    7625             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7626             :         // No instruction predicates
    7627             :         // MIs[0] Operand 0
    7628             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dsb,
    7629             :         // MIs[0] CRm
    7630             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7631             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7632             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15,
    7633             :         // MIs[1] Operand 0
    7634             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7635             :         // MIs[1] Operand 1
    7636             :         // No operand predicates
    7637             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7638             :         // (intrinsic_void 198:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (DSB (imm:{ *:[i32] }):$CRm)
    7639             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DSB,
    7640             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
    7641             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    7642             :         GIR_EraseFromParent, /*InsnID*/0,
    7643             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7644             :         GIR_Done,
    7645             :       // Label 259: @16757
    7646             :       GIM_Try, /*On fail goto*//*Label 260*/ 16805,
    7647             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    7648             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    7649             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7650             :         // No instruction predicates
    7651             :         // MIs[0] Operand 0
    7652             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_isb,
    7653             :         // MIs[0] CRm
    7654             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    7655             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7656             :         GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15,
    7657             :         // MIs[1] Operand 0
    7658             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7659             :         // MIs[1] Operand 1
    7660             :         // No operand predicates
    7661             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7662             :         // (intrinsic_void 200:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (ISB (imm:{ *:[i32] }):$CRm)
    7663             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ISB,
    7664             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
    7665             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
    7666             :         GIR_EraseFromParent, /*InsnID*/0,
    7667             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7668             :         GIR_Done,
    7669             :       // Label 260: @16805
    7670             :       GIM_Reject,
    7671             :       GIR_Done,
    7672             :     // Label 256: @16807
    7673             :     GIM_Try, /*On fail goto*//*Label 261*/ 18134,
    7674             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7675             :       GIM_Try, /*On fail goto*//*Label 262*/ 16878,
    7676             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    7677             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7678             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7679             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7680             :         // No instruction predicates
    7681             :         // MIs[0] Rd
    7682             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7683             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7684             :         // MIs[0] Operand 1
    7685             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7686             :         // MIs[0] Rn
    7687             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7688             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7689             :         // MIs[0] imm
    7690             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7691             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7692             :         // MIs[1] Operand 0
    7693             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7694             :         // MIs[1] Operand 1
    7695             :         // No operand predicates
    7696             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7697             :         // (intrinsic_wo_chain:{ *:[v4i16] } 347:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7698             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i16_shift,
    7699             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7700             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7701             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7702             :         GIR_EraseFromParent, /*InsnID*/0,
    7703             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7704             :         GIR_Done,
    7705             :       // Label 262: @16878
    7706             :       GIM_Try, /*On fail goto*//*Label 263*/ 16944,
    7707             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    7708             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7709             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7710             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7711             :         // No instruction predicates
    7712             :         // MIs[0] Rd
    7713             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7714             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    7715             :         // MIs[0] Operand 1
    7716             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7717             :         // MIs[0] Rn
    7718             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7719             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7720             :         // MIs[0] imm
    7721             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7722             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7723             :         // MIs[1] Operand 0
    7724             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7725             :         // MIs[1] Operand 1
    7726             :         // No operand predicates
    7727             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7728             :         // (intrinsic_wo_chain:{ *:[v8i16] } 347:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7729             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv8i16_shift,
    7730             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7731             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7732             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7733             :         GIR_EraseFromParent, /*InsnID*/0,
    7734             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7735             :         GIR_Done,
    7736             :       // Label 263: @16944
    7737             :       GIM_Try, /*On fail goto*//*Label 264*/ 17010,
    7738             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7739             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7740             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7741             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7742             :         // No instruction predicates
    7743             :         // MIs[0] Rd
    7744             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7745             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7746             :         // MIs[0] Operand 1
    7747             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7748             :         // MIs[0] Rn
    7749             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7750             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7751             :         // MIs[0] imm
    7752             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7753             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7754             :         // MIs[1] Operand 0
    7755             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7756             :         // MIs[1] Operand 1
    7757             :         // No operand predicates
    7758             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7759             :         // (intrinsic_wo_chain:{ *:[v2i32] } 347:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7760             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i32_shift,
    7761             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7762             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7763             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7764             :         GIR_EraseFromParent, /*InsnID*/0,
    7765             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7766             :         GIR_Done,
    7767             :       // Label 264: @17010
    7768             :       GIM_Try, /*On fail goto*//*Label 265*/ 17076,
    7769             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7770             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7771             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7772             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7773             :         // No instruction predicates
    7774             :         // MIs[0] Rd
    7775             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7776             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    7777             :         // MIs[0] Operand 1
    7778             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7779             :         // MIs[0] Rn
    7780             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7781             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7782             :         // MIs[0] imm
    7783             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7784             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7785             :         // MIs[1] Operand 0
    7786             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7787             :         // MIs[1] Operand 1
    7788             :         // No operand predicates
    7789             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7790             :         // (intrinsic_wo_chain:{ *:[v4i32] } 347:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7791             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i32_shift,
    7792             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7793             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7794             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7795             :         GIR_EraseFromParent, /*InsnID*/0,
    7796             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7797             :         GIR_Done,
    7798             :       // Label 265: @17076
    7799             :       GIM_Try, /*On fail goto*//*Label 266*/ 17142,
    7800             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7801             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7802             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7803             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7804             :         // No instruction predicates
    7805             :         // MIs[0] Rd
    7806             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    7807             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    7808             :         // MIs[0] Operand 1
    7809             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs,
    7810             :         // MIs[0] Rn
    7811             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7812             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7813             :         // MIs[0] imm
    7814             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7815             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7816             :         // MIs[1] Operand 0
    7817             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7818             :         // MIs[1] Operand 1
    7819             :         // No operand predicates
    7820             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7821             :         // (intrinsic_wo_chain:{ *:[v2i64] } 347:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)
    7822             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i64_shift,
    7823             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7824             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7825             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7826             :         GIR_EraseFromParent, /*InsnID*/0,
    7827             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7828             :         GIR_Done,
    7829             :       // Label 266: @17142
    7830             :       GIM_Try, /*On fail goto*//*Label 267*/ 17208,
    7831             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    7832             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7833             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7834             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7835             :         // No instruction predicates
    7836             :         // MIs[0] Rd
    7837             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7838             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7839             :         // MIs[0] Operand 1
    7840             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7841             :         // MIs[0] Rn
    7842             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7843             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7844             :         // MIs[0] imm
    7845             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7846             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7847             :         // MIs[1] Operand 0
    7848             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7849             :         // MIs[1] Operand 1
    7850             :         // No operand predicates
    7851             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7852             :         // (intrinsic_wo_chain:{ *:[v4i16] } 348:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7853             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i16_shift,
    7854             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7855             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7856             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7857             :         GIR_EraseFromParent, /*InsnID*/0,
    7858             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7859             :         GIR_Done,
    7860             :       // Label 267: @17208
    7861             :       GIM_Try, /*On fail goto*//*Label 268*/ 17274,
    7862             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    7863             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7864             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7865             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7866             :         // No instruction predicates
    7867             :         // MIs[0] Rd
    7868             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7869             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    7870             :         // MIs[0] Operand 1
    7871             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7872             :         // MIs[0] Rn
    7873             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7874             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7875             :         // MIs[0] imm
    7876             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7877             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7878             :         // MIs[1] Operand 0
    7879             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7880             :         // MIs[1] Operand 1
    7881             :         // No operand predicates
    7882             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7883             :         // (intrinsic_wo_chain:{ *:[v8i16] } 348:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)
    7884             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv8i16_shift,
    7885             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7886             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7887             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7888             :         GIR_EraseFromParent, /*InsnID*/0,
    7889             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7890             :         GIR_Done,
    7891             :       // Label 268: @17274
    7892             :       GIM_Try, /*On fail goto*//*Label 269*/ 17340,
    7893             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7894             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7895             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7896             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7897             :         // No instruction predicates
    7898             :         // MIs[0] Rd
    7899             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7900             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7901             :         // MIs[0] Operand 1
    7902             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7903             :         // MIs[0] Rn
    7904             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7905             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7906             :         // MIs[0] imm
    7907             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7908             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7909             :         // MIs[1] Operand 0
    7910             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7911             :         // MIs[1] Operand 1
    7912             :         // No operand predicates
    7913             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7914             :         // (intrinsic_wo_chain:{ *:[v2i32] } 348:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7915             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i32_shift,
    7916             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7917             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7918             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7919             :         GIR_EraseFromParent, /*InsnID*/0,
    7920             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7921             :         GIR_Done,
    7922             :       // Label 269: @17340
    7923             :       GIM_Try, /*On fail goto*//*Label 270*/ 17406,
    7924             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7925             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7926             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7927             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7928             :         // No instruction predicates
    7929             :         // MIs[0] Rd
    7930             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7931             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    7932             :         // MIs[0] Operand 1
    7933             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7934             :         // MIs[0] Rn
    7935             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7936             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7937             :         // MIs[0] imm
    7938             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7939             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7940             :         // MIs[1] Operand 0
    7941             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7942             :         // MIs[1] Operand 1
    7943             :         // No operand predicates
    7944             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7945             :         // (intrinsic_wo_chain:{ *:[v4i32] } 348:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)
    7946             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i32_shift,
    7947             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7948             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7949             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7950             :         GIR_EraseFromParent, /*InsnID*/0,
    7951             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7952             :         GIR_Done,
    7953             :       // Label 270: @17406
    7954             :       GIM_Try, /*On fail goto*//*Label 271*/ 17472,
    7955             :         GIM_CheckFeatures, GIFBS_HasNEON,
    7956             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7957             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7958             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7959             :         // No instruction predicates
    7960             :         // MIs[0] Rd
    7961             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    7962             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    7963             :         // MIs[0] Operand 1
    7964             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu,
    7965             :         // MIs[0] Rn
    7966             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7967             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    7968             :         // MIs[0] imm
    7969             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    7970             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    7971             :         // MIs[1] Operand 0
    7972             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    7973             :         // MIs[1] Operand 1
    7974             :         // No operand predicates
    7975             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    7976             :         // (intrinsic_wo_chain:{ *:[v2i64] } 348:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)
    7977             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i64_shift,
    7978             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    7979             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    7980             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    7981             :         GIR_EraseFromParent, /*InsnID*/0,
    7982             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7983             :         GIR_Done,
    7984             :       // Label 271: @17472
    7985             :       GIM_Try, /*On fail goto*//*Label 272*/ 17538,
    7986             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    7987             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7988             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    7989             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    7990             :         // No instruction predicates
    7991             :         // MIs[0] Rd
    7992             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7993             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    7994             :         // MIs[0] Operand 1
    7995             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    7996             :         // MIs[0] Rn
    7997             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7998             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    7999             :         // MIs[0] imm
    8000             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8001             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8002             :         // MIs[1] Operand 0
    8003             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8004             :         // MIs[1] Operand 1
    8005             :         // No operand predicates
    8006             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8007             :         // (intrinsic_wo_chain:{ *:[v4f16] } 350:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8008             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i16_shift,
    8009             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8010             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8011             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8012             :         GIR_EraseFromParent, /*InsnID*/0,
    8013             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8014             :         GIR_Done,
    8015             :       // Label 272: @17538
    8016             :       GIM_Try, /*On fail goto*//*Label 273*/ 17604,
    8017             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8018             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8019             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8020             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8021             :         // No instruction predicates
    8022             :         // MIs[0] Rd
    8023             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8024             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8025             :         // MIs[0] Operand 1
    8026             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8027             :         // MIs[0] Rn
    8028             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8029             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8030             :         // MIs[0] imm
    8031             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8032             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8033             :         // MIs[1] Operand 0
    8034             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8035             :         // MIs[1] Operand 1
    8036             :         // No operand predicates
    8037             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8038             :         // (intrinsic_wo_chain:{ *:[v8f16] } 350:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8039             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv8i16_shift,
    8040             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8041             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8042             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8043             :         GIR_EraseFromParent, /*InsnID*/0,
    8044             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8045             :         GIR_Done,
    8046             :       // Label 273: @17604
    8047             :       GIM_Try, /*On fail goto*//*Label 274*/ 17670,
    8048             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8049             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8050             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8051             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8052             :         // No instruction predicates
    8053             :         // MIs[0] Rd
    8054             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8055             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8056             :         // MIs[0] Operand 1
    8057             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8058             :         // MIs[0] Rn
    8059             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8060             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8061             :         // MIs[0] imm
    8062             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8063             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8064             :         // MIs[1] Operand 0
    8065             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8066             :         // MIs[1] Operand 1
    8067             :         // No operand predicates
    8068             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8069             :         // (intrinsic_wo_chain:{ *:[v2f32] } 350:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8070             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i32_shift,
    8071             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8072             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8073             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8074             :         GIR_EraseFromParent, /*InsnID*/0,
    8075             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8076             :         GIR_Done,
    8077             :       // Label 274: @17670
    8078             :       GIM_Try, /*On fail goto*//*Label 275*/ 17736,
    8079             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8080             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8081             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8082             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8083             :         // No instruction predicates
    8084             :         // MIs[0] Rd
    8085             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8086             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8087             :         // MIs[0] Operand 1
    8088             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8089             :         // MIs[0] Rn
    8090             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8091             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8092             :         // MIs[0] imm
    8093             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8094             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8095             :         // MIs[1] Operand 0
    8096             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8097             :         // MIs[1] Operand 1
    8098             :         // No operand predicates
    8099             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8100             :         // (intrinsic_wo_chain:{ *:[v4f32] } 350:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8101             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i32_shift,
    8102             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8103             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8104             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8105             :         GIR_EraseFromParent, /*InsnID*/0,
    8106             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8107             :         GIR_Done,
    8108             :       // Label 275: @17736
    8109             :       GIM_Try, /*On fail goto*//*Label 276*/ 17802,
    8110             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8111             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8112             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8113             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8114             :         // No instruction predicates
    8115             :         // MIs[0] Rd
    8116             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8117             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8118             :         // MIs[0] Operand 1
    8119             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp,
    8120             :         // MIs[0] Rn
    8121             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8122             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8123             :         // MIs[0] imm
    8124             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8125             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8126             :         // MIs[1] Operand 0
    8127             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8128             :         // MIs[1] Operand 1
    8129             :         // No operand predicates
    8130             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8131             :         // (intrinsic_wo_chain:{ *:[v2f64] } 350:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    8132             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i64_shift,
    8133             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8134             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8135             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8136             :         GIR_EraseFromParent, /*InsnID*/0,
    8137             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8138             :         GIR_Done,
    8139             :       // Label 276: @17802
    8140             :       GIM_Try, /*On fail goto*//*Label 277*/ 17868,
    8141             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8142             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8143             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8144             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8145             :         // No instruction predicates
    8146             :         // MIs[0] Rd
    8147             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8148             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8149             :         // MIs[0] Operand 1
    8150             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8151             :         // MIs[0] Rn
    8152             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8153             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8154             :         // MIs[0] imm
    8155             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8156             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8157             :         // MIs[1] Operand 0
    8158             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8159             :         // MIs[1] Operand 1
    8160             :         // No operand predicates
    8161             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8162             :         // (intrinsic_wo_chain:{ *:[v4f16] } 351:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8163             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i16_shift,
    8164             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8165             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8166             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8167             :         GIR_EraseFromParent, /*InsnID*/0,
    8168             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8169             :         GIR_Done,
    8170             :       // Label 277: @17868
    8171             :       GIM_Try, /*On fail goto*//*Label 278*/ 17934,
    8172             :         GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
    8173             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8174             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8175             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8176             :         // No instruction predicates
    8177             :         // MIs[0] Rd
    8178             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8179             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8180             :         // MIs[0] Operand 1
    8181             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8182             :         // MIs[0] Rn
    8183             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8184             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8185             :         // MIs[0] imm
    8186             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8187             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8188             :         // MIs[1] Operand 0
    8189             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8190             :         // MIs[1] Operand 1
    8191             :         // No operand predicates
    8192             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8193             :         // (intrinsic_wo_chain:{ *:[v8f16] } 351:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
    8194             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv8i16_shift,
    8195             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8196             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8197             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8198             :         GIR_EraseFromParent, /*InsnID*/0,
    8199             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8200             :         GIR_Done,
    8201             :       // Label 278: @17934
    8202             :       GIM_Try, /*On fail goto*//*Label 279*/ 18000,
    8203             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8204             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8205             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8206             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8207             :         // No instruction predicates
    8208             :         // MIs[0] Rd
    8209             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8210             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8211             :         // MIs[0] Operand 1
    8212             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8213             :         // MIs[0] Rn
    8214             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8215             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8216             :         // MIs[0] imm
    8217             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8218             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8219             :         // MIs[1] Operand 0
    8220             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8221             :         // MIs[1] Operand 1
    8222             :         // No operand predicates
    8223             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8224             :         // (intrinsic_wo_chain:{ *:[v2f32] } 351:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8225             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i32_shift,
    8226             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8227             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8228             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8229             :         GIR_EraseFromParent, /*InsnID*/0,
    8230             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8231             :         GIR_Done,
    8232             :       // Label 279: @18000
    8233             :       GIM_Try, /*On fail goto*//*Label 280*/ 18066,
    8234             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8235             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8236             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8237             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8238             :         // No instruction predicates
    8239             :         // MIs[0] Rd
    8240             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8241             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8242             :         // MIs[0] Operand 1
    8243             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8244             :         // MIs[0] Rn
    8245             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8246             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8247             :         // MIs[0] imm
    8248             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8249             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8250             :         // MIs[1] Operand 0
    8251             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8252             :         // MIs[1] Operand 1
    8253             :         // No operand predicates
    8254             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8255             :         // (intrinsic_wo_chain:{ *:[v4f32] } 351:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
    8256             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i32_shift,
    8257             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8258             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8259             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8260             :         GIR_EraseFromParent, /*InsnID*/0,
    8261             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8262             :         GIR_Done,
    8263             :       // Label 280: @18066
    8264             :       GIM_Try, /*On fail goto*//*Label 281*/ 18132,
    8265             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8266             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8267             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    8268             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    8269             :         // No instruction predicates
    8270             :         // MIs[0] Rd
    8271             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8272             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8273             :         // MIs[0] Operand 1
    8274             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp,
    8275             :         // MIs[0] Rn
    8276             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8277             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8278             :         // MIs[0] imm
    8279             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    8280             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    8281             :         // MIs[1] Operand 0
    8282             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    8283             :         // MIs[1] Operand 1
    8284             :         // No operand predicates
    8285             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8286             :         // (intrinsic_wo_chain:{ *:[v2f64] } 351:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
    8287             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i64_shift,
    8288             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    8289             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    8290             :         GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
    8291             :         GIR_EraseFromParent, /*InsnID*/0,
    8292             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8293             :         GIR_Done,
    8294             :       // Label 281: @18132
    8295             :       GIM_Reject,
    8296             :       GIR_Done,
    8297             :     // Label 261: @18134
    8298             :     GIM_Try, /*On fail goto*//*Label 282*/ 23073,
    8299             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
    8300             :       GIM_Try, /*On fail goto*//*Label 283*/ 18226,
    8301             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8302             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8303             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8304             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8305             :         // No instruction predicates
    8306             :         // MIs[0] dst
    8307             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8308             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8309             :         // MIs[0] Operand 1
    8310             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
    8311             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8312             :         // MIs[1] Operand 0
    8313             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s8,
    8314             :         // MIs[1] Operand 1
    8315             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8316             :         // MIs[1] Rn
    8317             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    8318             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8319             :         // MIs[1] Rm
    8320             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    8321             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8322             :         // MIs[0] Rd
    8323             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8324             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8325             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8326             :         // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 262:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    8327             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
    8328             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8329             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8330             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8331             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8332             :         GIR_EraseFromParent, /*InsnID*/0,
    8333             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8334             :         GIR_Done,
    8335             :       // Label 283: @18226
    8336             :       GIM_Try, /*On fail goto*//*Label 284*/ 18313,
    8337             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8338             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8339             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8340             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8341             :         // No instruction predicates
    8342             :         // MIs[0] dst
    8343             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    8344             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8345             :         // MIs[0] Operand 1
    8346             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
    8347             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8348             :         // MIs[1] Operand 0
    8349             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    8350             :         // MIs[1] Operand 1
    8351             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8352             :         // MIs[1] Rn
    8353             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    8354             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8355             :         // MIs[1] Rm
    8356             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    8357             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8358             :         // MIs[0] Rd
    8359             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    8360             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8361             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8362             :         // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 262:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
    8363             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
    8364             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8365             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8366             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8367             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8368             :         GIR_EraseFromParent, /*InsnID*/0,
    8369             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8370             :         GIR_Done,
    8371             :       // Label 284: @18313
    8372             :       GIM_Try, /*On fail goto*//*Label 285*/ 18400,
    8373             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8374             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8375             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8376             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8377             :         // No instruction predicates
    8378             :         // MIs[0] dst
    8379             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8380             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8381             :         // MIs[0] Operand 1
    8382             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    8383             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8384             :         // MIs[1] Operand 0
    8385             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    8386             :         // MIs[1] Operand 1
    8387             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8388             :         // MIs[1] Rn
    8389             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    8390             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8391             :         // MIs[1] Rm
    8392             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    8393             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8394             :         // MIs[0] Rd
    8395             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8396             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8397             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8398             :         // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 262:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    8399             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
    8400             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8401             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8402             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8403             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8404             :         GIR_EraseFromParent, /*InsnID*/0,
    8405             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8406             :         GIR_Done,
    8407             :       // Label 285: @18400
    8408             :       GIM_Try, /*On fail goto*//*Label 286*/ 18487,
    8409             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8410             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8411             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8412             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8413             :         // No instruction predicates
    8414             :         // MIs[0] dst
    8415             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8416             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8417             :         // MIs[0] Operand 1
    8418             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    8419             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8420             :         // MIs[1] Operand 0
    8421             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    8422             :         // MIs[1] Operand 1
    8423             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8424             :         // MIs[1] Rn
    8425             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    8426             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8427             :         // MIs[1] Rm
    8428             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    8429             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8430             :         // MIs[0] Rd
    8431             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8432             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8433             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8434             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 262:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
    8435             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
    8436             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8437             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8438             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8439             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8440             :         GIR_EraseFromParent, /*InsnID*/0,
    8441             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8442             :         GIR_Done,
    8443             :       // Label 286: @18487
    8444             :       GIM_Try, /*On fail goto*//*Label 287*/ 18574,
    8445             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8446             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8447             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8448             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8449             :         // No instruction predicates
    8450             :         // MIs[0] dst
    8451             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8452             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8453             :         // MIs[0] Operand 1
    8454             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    8455             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8456             :         // MIs[1] Operand 0
    8457             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    8458             :         // MIs[1] Operand 1
    8459             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8460             :         // MIs[1] Rn
    8461             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    8462             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8463             :         // MIs[1] Rm
    8464             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    8465             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8466             :         // MIs[0] Rd
    8467             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8468             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8469             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8470             :         // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 262:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    8471             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
    8472             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8473             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8474             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8475             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8476             :         GIR_EraseFromParent, /*InsnID*/0,
    8477             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8478             :         GIR_Done,
    8479             :       // Label 287: @18574
    8480             :       GIM_Try, /*On fail goto*//*Label 288*/ 18661,
    8481             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8482             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8483             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8484             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8485             :         // No instruction predicates
    8486             :         // MIs[0] dst
    8487             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8488             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8489             :         // MIs[0] Operand 1
    8490             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    8491             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8492             :         // MIs[1] Operand 0
    8493             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    8494             :         // MIs[1] Operand 1
    8495             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    8496             :         // MIs[1] Rn
    8497             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    8498             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8499             :         // MIs[1] Rm
    8500             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    8501             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8502             :         // MIs[0] Rd
    8503             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8504             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8505             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8506             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 262:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
    8507             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
    8508             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8509             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8510             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8511             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8512             :         GIR_EraseFromParent, /*InsnID*/0,
    8513             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8514             :         GIR_Done,
    8515             :       // Label 288: @18661
    8516             :       GIM_Try, /*On fail goto*//*Label 289*/ 18748,
    8517             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8518             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8519             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8520             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8521             :         // No instruction predicates
    8522             :         // MIs[0] dst
    8523             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8524             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8525             :         // MIs[0] Operand 1
    8526             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
    8527             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8528             :         // MIs[1] Operand 0
    8529             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s8,
    8530             :         // MIs[1] Operand 1
    8531             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8532             :         // MIs[1] Rn
    8533             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    8534             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8535             :         // MIs[1] Rm
    8536             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    8537             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8538             :         // MIs[0] Rd
    8539             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8540             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8541             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8542             :         // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 319:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    8543             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
    8544             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8545             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8546             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8547             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8548             :         GIR_EraseFromParent, /*InsnID*/0,
    8549             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8550             :         GIR_Done,
    8551             :       // Label 289: @18748
    8552             :       GIM_Try, /*On fail goto*//*Label 290*/ 18835,
    8553             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8554             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8555             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8556             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8557             :         // No instruction predicates
    8558             :         // MIs[0] dst
    8559             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    8560             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8561             :         // MIs[0] Operand 1
    8562             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
    8563             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8564             :         // MIs[1] Operand 0
    8565             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    8566             :         // MIs[1] Operand 1
    8567             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8568             :         // MIs[1] Rn
    8569             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    8570             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8571             :         // MIs[1] Rm
    8572             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    8573             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8574             :         // MIs[0] Rd
    8575             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    8576             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8577             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8578             :         // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 319:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
    8579             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
    8580             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8581             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8582             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8583             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8584             :         GIR_EraseFromParent, /*InsnID*/0,
    8585             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8586             :         GIR_Done,
    8587             :       // Label 290: @18835
    8588             :       GIM_Try, /*On fail goto*//*Label 291*/ 18922,
    8589             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8590             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8591             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8592             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8593             :         // No instruction predicates
    8594             :         // MIs[0] dst
    8595             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8596             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8597             :         // MIs[0] Operand 1
    8598             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    8599             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8600             :         // MIs[1] Operand 0
    8601             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    8602             :         // MIs[1] Operand 1
    8603             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8604             :         // MIs[1] Rn
    8605             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    8606             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8607             :         // MIs[1] Rm
    8608             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    8609             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8610             :         // MIs[0] Rd
    8611             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8612             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8613             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8614             :         // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 319:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    8615             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
    8616             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8617             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8618             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8619             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8620             :         GIR_EraseFromParent, /*InsnID*/0,
    8621             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8622             :         GIR_Done,
    8623             :       // Label 291: @18922
    8624             :       GIM_Try, /*On fail goto*//*Label 292*/ 19009,
    8625             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8626             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8627             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8628             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8629             :         // No instruction predicates
    8630             :         // MIs[0] dst
    8631             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8632             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8633             :         // MIs[0] Operand 1
    8634             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    8635             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8636             :         // MIs[1] Operand 0
    8637             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    8638             :         // MIs[1] Operand 1
    8639             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8640             :         // MIs[1] Rn
    8641             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    8642             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8643             :         // MIs[1] Rm
    8644             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    8645             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8646             :         // MIs[0] Rd
    8647             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8648             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8649             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8650             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 319:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
    8651             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
    8652             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8653             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8654             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8655             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8656             :         GIR_EraseFromParent, /*InsnID*/0,
    8657             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8658             :         GIR_Done,
    8659             :       // Label 292: @19009
    8660             :       GIM_Try, /*On fail goto*//*Label 293*/ 19096,
    8661             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8662             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8663             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8664             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8665             :         // No instruction predicates
    8666             :         // MIs[0] dst
    8667             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8668             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8669             :         // MIs[0] Operand 1
    8670             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    8671             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8672             :         // MIs[1] Operand 0
    8673             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    8674             :         // MIs[1] Operand 1
    8675             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8676             :         // MIs[1] Rn
    8677             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    8678             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8679             :         // MIs[1] Rm
    8680             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    8681             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8682             :         // MIs[0] Rd
    8683             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8684             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8685             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8686             :         // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 319:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    8687             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
    8688             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8689             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8690             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8691             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8692             :         GIR_EraseFromParent, /*InsnID*/0,
    8693             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8694             :         GIR_Done,
    8695             :       // Label 293: @19096
    8696             :       GIM_Try, /*On fail goto*//*Label 294*/ 19183,
    8697             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8698             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8699             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8700             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8701             :         // No instruction predicates
    8702             :         // MIs[0] dst
    8703             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8704             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8705             :         // MIs[0] Operand 1
    8706             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    8707             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8708             :         // MIs[1] Operand 0
    8709             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    8710             :         // MIs[1] Operand 1
    8711             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
    8712             :         // MIs[1] Rn
    8713             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    8714             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8715             :         // MIs[1] Rm
    8716             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    8717             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    8718             :         // MIs[0] Rd
    8719             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8720             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8721             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8722             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 319:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
    8723             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
    8724             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8725             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8726             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8727             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8728             :         GIR_EraseFromParent, /*InsnID*/0,
    8729             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8730             :         GIR_Done,
    8731             :       // Label 294: @19183
    8732             :       GIM_Try, /*On fail goto*//*Label 295*/ 19270,
    8733             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8734             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8735             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8736             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8737             :         // No instruction predicates
    8738             :         // MIs[0] dst
    8739             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8740             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8741             :         // MIs[0] Operand 1
    8742             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    8743             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8744             :         // MIs[1] Operand 0
    8745             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    8746             :         // MIs[1] Operand 1
    8747             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
    8748             :         // MIs[1] Rn
    8749             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    8750             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8751             :         // MIs[1] Rm
    8752             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    8753             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8754             :         // MIs[0] Rd
    8755             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8756             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8757             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8758             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 278:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    8759             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
    8760             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8761             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8762             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8763             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8764             :         GIR_EraseFromParent, /*InsnID*/0,
    8765             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8766             :         GIR_Done,
    8767             :       // Label 295: @19270
    8768             :       GIM_Try, /*On fail goto*//*Label 296*/ 19357,
    8769             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8770             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8771             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8772             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8773             :         // No instruction predicates
    8774             :         // MIs[0] dst
    8775             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8776             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8777             :         // MIs[0] Operand 1
    8778             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    8779             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8780             :         // MIs[1] Operand 0
    8781             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    8782             :         // MIs[1] Operand 1
    8783             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
    8784             :         // MIs[1] Rn
    8785             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    8786             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8787             :         // MIs[1] Rm
    8788             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    8789             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8790             :         // MIs[0] Rd
    8791             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8792             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8793             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8794             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 278:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    8795             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
    8796             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8797             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8798             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8799             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8800             :         GIR_EraseFromParent, /*InsnID*/0,
    8801             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8802             :         GIR_Done,
    8803             :       // Label 296: @19357
    8804             :       GIM_Try, /*On fail goto*//*Label 297*/ 19444,
    8805             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8806             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8807             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8808             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8809             :         // No instruction predicates
    8810             :         // MIs[0] dst
    8811             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8812             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8813             :         // MIs[0] Operand 1
    8814             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    8815             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8816             :         // MIs[1] Operand 0
    8817             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    8818             :         // MIs[1] Operand 1
    8819             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
    8820             :         // MIs[1] Rn
    8821             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    8822             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8823             :         // MIs[1] Rm
    8824             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    8825             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8826             :         // MIs[0] Rd
    8827             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8828             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8829             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8830             :         // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 278:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    8831             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
    8832             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8833             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8834             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8835             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8836             :         GIR_EraseFromParent, /*InsnID*/0,
    8837             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8838             :         GIR_Done,
    8839             :       // Label 297: @19444
    8840             :       GIM_Try, /*On fail goto*//*Label 298*/ 19531,
    8841             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8842             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8843             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8844             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8845             :         // No instruction predicates
    8846             :         // MIs[0] dst
    8847             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8848             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8849             :         // MIs[0] Operand 1
    8850             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    8851             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8852             :         // MIs[1] Operand 0
    8853             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    8854             :         // MIs[1] Operand 1
    8855             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
    8856             :         // MIs[1] Rn
    8857             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    8858             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8859             :         // MIs[1] Rm
    8860             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    8861             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8862             :         // MIs[0] Rd
    8863             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8864             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8865             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8866             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 331:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    8867             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
    8868             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8869             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8870             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8871             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8872             :         GIR_EraseFromParent, /*InsnID*/0,
    8873             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8874             :         GIR_Done,
    8875             :       // Label 298: @19531
    8876             :       GIM_Try, /*On fail goto*//*Label 299*/ 19618,
    8877             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8878             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8879             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8880             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8881             :         // No instruction predicates
    8882             :         // MIs[0] dst
    8883             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8884             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8885             :         // MIs[0] Operand 1
    8886             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    8887             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8888             :         // MIs[1] Operand 0
    8889             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    8890             :         // MIs[1] Operand 1
    8891             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
    8892             :         // MIs[1] Rn
    8893             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    8894             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8895             :         // MIs[1] Rm
    8896             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    8897             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8898             :         // MIs[0] Rd
    8899             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8900             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8901             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8902             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 331:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
    8903             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
    8904             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8905             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8906             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8907             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8908             :         GIR_EraseFromParent, /*InsnID*/0,
    8909             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8910             :         GIR_Done,
    8911             :       // Label 299: @19618
    8912             :       GIM_Try, /*On fail goto*//*Label 300*/ 19705,
    8913             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8914             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8915             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8916             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    8917             :         // No instruction predicates
    8918             :         // MIs[0] dst
    8919             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8920             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8921             :         // MIs[0] Operand 1
    8922             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    8923             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8924             :         // MIs[1] Operand 0
    8925             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    8926             :         // MIs[1] Operand 1
    8927             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
    8928             :         // MIs[1] Rn
    8929             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    8930             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8931             :         // MIs[1] Rm
    8932             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    8933             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    8934             :         // MIs[0] Rd
    8935             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8936             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8937             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8938             :         // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 331:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
    8939             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
    8940             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8941             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8942             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8943             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    8944             :         GIR_EraseFromParent, /*InsnID*/0,
    8945             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8946             :         GIR_Done,
    8947             :       // Label 300: @19705
    8948             :       GIM_Try, /*On fail goto*//*Label 301*/ 19780,
    8949             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8950             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8951             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8952             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    8953             :         // No instruction predicates
    8954             :         // MIs[0] dst
    8955             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8956             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    8957             :         // MIs[0] Operand 1
    8958             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    8959             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8960             :         // MIs[1] Operand 0
    8961             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    8962             :         // MIs[1] Operand 1
    8963             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    8964             :         // MIs[1] Rn
    8965             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    8966             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8967             :         // MIs[0] Rd
    8968             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8969             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    8970             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    8971             :         // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 263:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
    8972             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
    8973             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    8974             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    8975             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    8976             :         GIR_EraseFromParent, /*InsnID*/0,
    8977             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8978             :         GIR_Done,
    8979             :       // Label 301: @19780
    8980             :       GIM_Try, /*On fail goto*//*Label 302*/ 19855,
    8981             :         GIM_CheckFeatures, GIFBS_HasNEON,
    8982             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    8983             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    8984             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    8985             :         // No instruction predicates
    8986             :         // MIs[0] dst
    8987             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8988             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    8989             :         // MIs[0] Operand 1
    8990             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    8991             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    8992             :         // MIs[1] Operand 0
    8993             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    8994             :         // MIs[1] Operand 1
    8995             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    8996             :         // MIs[1] Rn
    8997             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    8998             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    8999             :         // MIs[0] Rd
    9000             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9001             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9002             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9003             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 263:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
    9004             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
    9005             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9006             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9007             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9008             :         GIR_EraseFromParent, /*InsnID*/0,
    9009             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9010             :         GIR_Done,
    9011             :       // Label 302: @19855
    9012             :       GIM_Try, /*On fail goto*//*Label 303*/ 19930,
    9013             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9014             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9015             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9016             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9017             :         // No instruction predicates
    9018             :         // MIs[0] dst
    9019             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9020             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9021             :         // MIs[0] Operand 1
    9022             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    9023             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9024             :         // MIs[1] Operand 0
    9025             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    9026             :         // MIs[1] Operand 1
    9027             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9028             :         // MIs[1] Rn
    9029             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    9030             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9031             :         // MIs[0] Rd
    9032             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9033             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9034             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9035             :         // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 263:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
    9036             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
    9037             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9038             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9039             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9040             :         GIR_EraseFromParent, /*InsnID*/0,
    9041             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9042             :         GIR_Done,
    9043             :       // Label 303: @19930
    9044             :       GIM_Try, /*On fail goto*//*Label 304*/ 20005,
    9045             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9046             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9047             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9048             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9049             :         // No instruction predicates
    9050             :         // MIs[0] dst
    9051             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9052             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9053             :         // MIs[0] Operand 1
    9054             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    9055             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9056             :         // MIs[1] Operand 0
    9057             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    9058             :         // MIs[1] Operand 1
    9059             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9060             :         // MIs[1] Rn
    9061             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    9062             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9063             :         // MIs[0] Rd
    9064             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9065             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9066             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9067             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 263:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
    9068             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
    9069             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9070             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9071             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9072             :         GIR_EraseFromParent, /*InsnID*/0,
    9073             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9074             :         GIR_Done,
    9075             :       // Label 304: @20005
    9076             :       GIM_Try, /*On fail goto*//*Label 305*/ 20080,
    9077             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9078             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9079             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9080             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9081             :         // No instruction predicates
    9082             :         // MIs[0] dst
    9083             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    9084             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9085             :         // MIs[0] Operand 1
    9086             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    9087             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9088             :         // MIs[1] Operand 0
    9089             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    9090             :         // MIs[1] Operand 1
    9091             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9092             :         // MIs[1] Rn
    9093             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    9094             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9095             :         // MIs[0] Rd
    9096             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    9097             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9098             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9099             :         // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 263:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
    9100             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
    9101             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9102             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9103             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9104             :         GIR_EraseFromParent, /*InsnID*/0,
    9105             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9106             :         GIR_Done,
    9107             :       // Label 305: @20080
    9108             :       GIM_Try, /*On fail goto*//*Label 306*/ 20155,
    9109             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9110             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9111             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9112             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9113             :         // No instruction predicates
    9114             :         // MIs[0] dst
    9115             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    9116             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9117             :         // MIs[0] Operand 1
    9118             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    9119             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9120             :         // MIs[1] Operand 0
    9121             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    9122             :         // MIs[1] Operand 1
    9123             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
    9124             :         // MIs[1] Rn
    9125             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    9126             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9127             :         // MIs[0] Rd
    9128             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    9129             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9130             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9131             :         // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 263:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
    9132             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
    9133             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9134             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9135             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9136             :         GIR_EraseFromParent, /*InsnID*/0,
    9137             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9138             :         GIR_Done,
    9139             :       // Label 306: @20155
    9140             :       GIM_Try, /*On fail goto*//*Label 307*/ 20230,
    9141             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9142             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9143             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9144             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9145             :         // No instruction predicates
    9146             :         // MIs[0] dst
    9147             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9148             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9149             :         // MIs[0] Operand 1
    9150             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    9151             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9152             :         // MIs[1] Operand 0
    9153             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    9154             :         // MIs[1] Operand 1
    9155             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
    9156             :         // MIs[1] Rn
    9157             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    9158             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9159             :         // MIs[0] Rd
    9160             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9161             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9162             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9163             :         // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 320:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
    9164             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
    9165             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9166             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9167             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9168             :         GIR_EraseFromParent, /*InsnID*/0,
    9169             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9170             :         GIR_Done,
    9171             :       // Label 307: @20230
    9172             :       GIM_Try, /*On fail goto*//*Label 308*/ 20305,
    9173             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9174             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9175             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9176             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9177             :         // No instruction predicates
    9178             :         // MIs[0] dst
    9179             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9180             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9181             :         // MIs[0] Operand 1
    9182             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
    9183             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9184             :         // MIs[1] Operand 0
    9185             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    9186             :         // MIs[1] Operand 1
    9187             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
    9188             :         // MIs[1] Rn
    9189             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    9190             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9191             :         // MIs[0] Rd
    9192             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9193             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9194             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9195             :         // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 320:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
    9196             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
    9197             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9198             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9199             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9200             :         GIR_EraseFromParent, /*InsnID*/0,
    9201             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9202             :         GIR_Done,
    9203             :       // Label 308: @20305
    9204             :       GIM_Try, /*On fail goto*//*Label 309*/ 20380,
    9205             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9206             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9207             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9208             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9209             :         // No instruction predicates
    9210             :         // MIs[0] dst
    9211             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9212             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9213             :         // MIs[0] Operand 1
    9214             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    9215             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9216             :         // MIs[1] Operand 0
    9217             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    9218             :         // MIs[1] Operand 1
    9219             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
    9220             :         // MIs[1] Rn
    9221             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    9222             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9223             :         // MIs[0] Rd
    9224             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9225             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9226             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9227             :         // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 320:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
    9228             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
    9229             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9230             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9231             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9232             :         GIR_EraseFromParent, /*InsnID*/0,
    9233             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9234             :         GIR_Done,
    9235             :       // Label 309: @20380
    9236             :       GIM_Try, /*On fail goto*//*Label 310*/ 20455,
    9237             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9238             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9239             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9240             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9241             :         // No instruction predicates
    9242             :         // MIs[0] dst
    9243             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9244             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9245             :         // MIs[0] Operand 1
    9246             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    9247             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9248             :         // MIs[1] Operand 0
    9249             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    9250             :         // MIs[1] Operand 1
    9251             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
    9252             :         // MIs[1] Rn
    9253             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    9254             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9255             :         // MIs[0] Rd
    9256             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9257             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9258             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9259             :         // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 320:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
    9260             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
    9261             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9262             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9263             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9264             :         GIR_EraseFromParent, /*InsnID*/0,
    9265             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9266             :         GIR_Done,
    9267             :       // Label 310: @20455
    9268             :       GIM_Try, /*On fail goto*//*Label 311*/ 20530,
    9269             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9270             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9271             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9272             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9273             :         // No instruction predicates
    9274             :         // MIs[0] dst
    9275             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    9276             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9277             :         // MIs[0] Operand 1
    9278             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    9279             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9280             :         // MIs[1] Operand 0
    9281             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    9282             :         // MIs[1] Operand 1
    9283             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
    9284             :         // MIs[1] Rn
    9285             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    9286             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9287             :         // MIs[0] Rd
    9288             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    9289             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9290             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9291             :         // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 320:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
    9292             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
    9293             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9294             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9295             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9296             :         GIR_EraseFromParent, /*InsnID*/0,
    9297             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9298             :         GIR_Done,
    9299             :       // Label 311: @20530
    9300             :       GIM_Try, /*On fail goto*//*Label 312*/ 20605,
    9301             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9302             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9303             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    9304             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
    9305             :         // No instruction predicates
    9306             :         // MIs[0] dst
    9307             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    9308             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9309             :         // MIs[0] Operand 1
    9310             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    9311             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9312             :         // MIs[1] Operand 0
    9313             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    9314             :         // MIs[1] Operand 1
    9315             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
    9316             :         // MIs[1] Rn
    9317             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    9318             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9319             :         // MIs[0] Rd
    9320             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    9321             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9322             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9323             :         // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 320:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
    9324             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
    9325             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9326             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
    9327             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9328             :         GIR_EraseFromParent, /*InsnID*/0,
    9329             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9330             :         GIR_Done,
    9331             :       // Label 312: @20605
    9332             :       GIM_Try, /*On fail goto*//*Label 313*/ 20692,
    9333             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9334             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9335             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    9336             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    9337             :         // No instruction predicates
    9338             :         // MIs[0] dst
    9339             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    9340             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
    9341             :         // MIs[0] Rd
    9342             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
    9343             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
    9344             :         // MIs[0] Operand 2
    9345             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    9346             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9347             :         // MIs[1] Operand 0
    9348             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s8,
    9349             :         // MIs[1] Operand 1
    9350             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    9351             :         // MIs[1] Rn
    9352             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
    9353             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
    9354             :         // MIs[1] Rm
    9355             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
    9356             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
    9357             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9358             :         // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 262:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
    9359             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
    9360             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9361             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    9362             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9363             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    9364             :         GIR_EraseFromParent, /*InsnID*/0,
    9365             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9366             :         GIR_Done,
    9367             :       // Label 313: @20692
    9368             :       GIM_Try, /*On fail goto*//*Label 314*/ 20779,
    9369             :         GIM_CheckFeatures, GIFBS_HasNEON,
    9370             :         GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    9371             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    9372             :         GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    9373             :         // No instruction predicates
    9374             :         // MIs[0] dst
    9375             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    9376             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
    9377             :         // MIs[0] Rd
    9378             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
    9379             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
    9380             :         // MIs[0] Operand 2
    9381             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    9382             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    9383             :         // MIs[1] Operand 0
    9384             :         GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v16s8,
    9385             :         // MIs[1] Operand 1
    9386             :         GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
    9387             :         // MIs[1] Rn
    9388             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
    9389             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
    9390             :         // MIs[1] Rm
    9391             :         GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
    9392             :         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
    9393             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
    9394             :         // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 262:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
    9395             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
    9396             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    9397             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
    9398             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    9399             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
    9400             :         GIR_EraseFromParent, /*InsnID*/0,
    9401             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9402             :         GIR_Done,
    9403             :       // Label 314: @20779
    9404             :       GIM_Try, /*On fail goto*//*Label 315*/ 20866,
    9405             :         GIM_Che