LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenRegisterBank.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 6 6 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Register Bank Source Fragments                                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_REGBANK_DECLARATIONS
      10             : #undef GET_REGBANK_DECLARATIONS
      11             : namespace llvm {
      12             : namespace AArch64 {
      13             : enum {
      14             :   CCRRegBankID,
      15             :   FPRRegBankID,
      16             :   GPRRegBankID,
      17             :   NumRegisterBanks,
      18             : };
      19             : } // end namespace AArch64
      20             : } // end namespace llvm
      21             : #endif // GET_REGBANK_DECLARATIONS
      22             : 
      23             : #ifdef GET_TARGET_REGBANK_CLASS
      24             : #undef GET_TARGET_REGBANK_CLASS
      25             : private:
      26             :   static RegisterBank *RegBanks[];
      27             : 
      28             : protected:
      29             :   AArch64GenRegisterBankInfo();
      30             : 
      31             : #endif // GET_TARGET_REGBANK_CLASS
      32             : 
      33             : #ifdef GET_TARGET_REGBANK_IMPL
      34             : #undef GET_TARGET_REGBANK_IMPL
      35             : namespace llvm {
      36             : namespace AArch64 {
      37             : const uint32_t CCRRegBankCoverageData[] = {
      38             :     // 0-31
      39             :     (1u << (AArch64::CCRRegClassID - 0)) |
      40             :     0,
      41             :     // 32-63
      42             :     0,
      43             : };
      44             : const uint32_t FPRRegBankCoverageData[] = {
      45             :     // 0-31
      46             :     (1u << (AArch64::FPR8RegClassID - 0)) |
      47             :     (1u << (AArch64::FPR16RegClassID - 0)) |
      48             :     (1u << (AArch64::FPR32RegClassID - 0)) |
      49             :     (1u << (AArch64::FPR64RegClassID - 0)) |
      50             :     (1u << (AArch64::DDRegClassID - 0)) |
      51             :     (1u << (AArch64::FPR128RegClassID - 0)) |
      52             :     (1u << (AArch64::DDDRegClassID - 0)) |
      53             :     (1u << (AArch64::DDDDRegClassID - 0)) |
      54             :     (1u << (AArch64::FPR128_loRegClassID - 0)) |
      55             :     0,
      56             :     // 32-63
      57             :     (1u << (AArch64::QQQQRegClassID - 32)) |
      58             :     (1u << (AArch64::QQRegClassID - 32)) |
      59             :     (1u << (AArch64::QQQRegClassID - 32)) |
      60             :     (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
      61             :     (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
      62             :     (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
      63             :     (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      64             :     (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      65             :     (1u << (AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      66             :     (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      67             :     (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      68             :     (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
      69             :     (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
      70             :     (1u << (AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
      71             :     (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
      72             :     (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
      73             :     (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      74             :     (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
      75             :     (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
      76             :     (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
      77             :     (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
      78             :     (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
      79             :     0,
      80             : };
      81             : const uint32_t GPRRegBankCoverageData[] = {
      82             :     // 0-31
      83             :     (1u << (AArch64::GPR64allRegClassID - 0)) |
      84             :     (1u << (AArch64::GPR32allRegClassID - 0)) |
      85             :     (1u << (AArch64::GPR64RegClassID - 0)) |
      86             :     (1u << (AArch64::GPR32RegClassID - 0)) |
      87             :     (1u << (AArch64::GPR64commonRegClassID - 0)) |
      88             :     (1u << (AArch64::GPR32spRegClassID - 0)) |
      89             :     (1u << (AArch64::GPR32commonRegClassID - 0)) |
      90             :     (1u << (AArch64::tcGPR64RegClassID - 0)) |
      91             :     (1u << (AArch64::GPR64spRegClassID - 0)) |
      92             :     (1u << (AArch64::GPR64sponlyRegClassID - 0)) |
      93             :     (1u << (AArch64::GPR32sponlyRegClassID - 0)) |
      94             :     0,
      95             :     // 32-63
      96             :     0,
      97             : };
      98             : 
      99       72306 : RegisterBank CCRRegBank(/* ID */ AArch64::CCRRegBankID, /* Name */ "CCR", /* Size */ 32, /* CoveredRegClasses */ CCRRegBankCoverageData, /* NumRegClasses */ 54);
     100       72306 : RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 54);
     101       72306 : RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 54);
     102             : } // end namespace AArch64
     103             : 
     104             : RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
     105             :     &AArch64::CCRRegBank,
     106             :     &AArch64::FPRRegBank,
     107             :     &AArch64::GPRRegBank,
     108             : };
     109             : 
     110        1214 : AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo()
     111        1214 :     : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {
     112             :   // Assert that RegBank indices match their ID's
     113             : #ifndef NDEBUG
     114             :   unsigned Index = 0;
     115             :   for (const auto &RB : RegBanks)
     116             :     assert(Index++ == RB->getID() && "Index != ID");
     117             : #endif // NDEBUG
     118        1214 : }
     119             : } // end namespace llvm
     120             : #endif // GET_TARGET_REGBANK_IMPL

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