Line data    Source code

       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Register Bank Source Fragments                                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_REGBANK_DECLARATIONS
      10             : #undef GET_REGBANK_DECLARATIONS
      11             : namespace llvm {
      12             : namespace AArch64 {
      13             : enum {
      14             :   CCRegBankID,
      15             :   FPRRegBankID,
      16             :   GPRRegBankID,
      17             :   NumRegisterBanks,
      18             : };
      19             : } // end namespace AArch64
      20             : } // end namespace llvm
      21             : #endif // GET_REGBANK_DECLARATIONS
      22             : 
      23             : #ifdef GET_TARGET_REGBANK_CLASS
      24             : #undef GET_TARGET_REGBANK_CLASS
      25             : private:
      26             :   static RegisterBank *RegBanks[];
      27             : 
      28             : protected:
      29             :   AArch64GenRegisterBankInfo();
      30             : 
      31             : #endif // GET_TARGET_REGBANK_CLASS
      32             : 
      33             : #ifdef GET_TARGET_REGBANK_IMPL
      34             : #undef GET_TARGET_REGBANK_IMPL
      35             : namespace llvm {
      36             : namespace AArch64 {
      37             : const uint32_t CCRegBankCoverageData[] = {
      38             :     // 0-31
      39             :     (1u << (AArch64::CCRRegClassID - 0)) |
      40             :     0,
      41             :     // 32-63
      42             :     0,
      43             :     // 64-95
      44             :     0,
      45             :     // 96-127
      46             :     0,
      47             : };
      48             : const uint32_t FPRRegBankCoverageData[] = {
      49             :     // 0-31
      50             :     (1u << (AArch64::FPR8RegClassID - 0)) |
      51             :     (1u << (AArch64::FPR16RegClassID - 0)) |
      52             :     (1u << (AArch64::FPR32RegClassID - 0)) |
      53             :     (1u << (AArch64::FPR64RegClassID - 0)) |
      54             :     (1u << (AArch64::DDRegClassID - 0)) |
      55             :     0,
      56             :     // 32-63
      57             :     (1u << (AArch64::FPR128RegClassID - 32)) |
      58             :     (1u << (AArch64::DDDRegClassID - 32)) |
      59             :     (1u << (AArch64::DDDDRegClassID - 32)) |
      60             :     (1u << (AArch64::QQRegClassID - 32)) |
      61             :     (1u << (AArch64::QQQRegClassID - 32)) |
      62             :     (1u << (AArch64::FPR128_loRegClassID - 32)) |
      63             :     (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
      64             :     (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
      65             :     (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      66             :     (1u << (AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      67             :     (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      68             :     (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
      69             :     (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
      70             :     (1u << (AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
      71             :     0,
      72             :     // 64-95
      73             :     (1u << (AArch64::QQQQRegClassID - 64)) |
      74             :     (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 64)) |
      75             :     (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - 64)) |
      76             :     (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
      77             :     (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
      78             :     (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
      79             :     (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 64)) |
      80             :     (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
      81             :     (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
      82             :     (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
      83             :     (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
      84             :     (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
      85             :     0,
      86             :     // 96-127
      87             :     0,
      88             : };
      89             : const uint32_t GPRRegBankCoverageData[] = {
      90             :     // 0-31
      91             :     (1u << (AArch64::GPR64allRegClassID - 0)) |
      92             :     (1u << (AArch64::GPR32allRegClassID - 0)) |
      93             :     (1u << (AArch64::GPR64RegClassID - 0)) |
      94             :     (1u << (AArch64::GPR32RegClassID - 0)) |
      95             :     (1u << (AArch64::GPR64commonRegClassID - 0)) |
      96             :     (1u << (AArch64::GPR32spRegClassID - 0)) |
      97             :     (1u << (AArch64::GPR32commonRegClassID - 0)) |
      98             :     (1u << (AArch64::tcGPR64RegClassID - 0)) |
      99             :     (1u << (AArch64::rtcGPR64RegClassID - 0)) |
     100             :     (1u << (AArch64::GPR64spRegClassID - 0)) |
     101             :     (1u << (AArch64::GPR64sponlyRegClassID - 0)) |
     102             :     (1u << (AArch64::GPR32sponlyRegClassID - 0)) |
     103             :     0,
     104             :     // 32-63
     105             :     0,
     106             :     // 64-95
     107             :     0,
     108             :     // 96-127
     109             :     0,
     110             : };
     111             : 
     112             : RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* Size */ 32, /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 104);
     113             : RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 104);
     114             : RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 104);
     115             : } // end namespace AArch64
     116             : 
     117             : RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
     118             :     &AArch64::CCRegBank,
     119             :     &AArch64::FPRRegBank,
     120             :     &AArch64::GPRRegBank,
     121             : };
     122             : 
     123        1570 : AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo()
     124        1570 :     : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {
     125             :   // Assert that RegBank indices match their ID's
     126             : #ifndef NDEBUG
     127             :   unsigned Index = 0;
     128             :   for (const auto &RB : RegBanks)
     129             :     assert(Index++ == RB->getID() && "Index != ID");
     130             : #endif // NDEBUG
     131        1570 : }
     132             : } // end namespace llvm
     133             : #endif // GET_TARGET_REGBANK_IMPL