LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenRegisterInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 93 122 76.2 %
Date: 2017-09-14 15:23:50 Functions: 18 21 85.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Register Enum Values                                                *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_REGINFO_ENUM
      11             : #undef GET_REGINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : 
      15             : class MCRegisterClass;
      16             : extern const MCRegisterClass AArch64MCRegisterClasses[];
      17             : 
      18             : namespace AArch64 {
      19             : enum {
      20             :   NoRegister,
      21             :   FP = 1,
      22             :   LR = 2,
      23             :   NZCV = 3,
      24             :   SP = 4,
      25             :   WSP = 5,
      26             :   WZR = 6,
      27             :   XZR = 7,
      28             :   B0 = 8,
      29             :   B1 = 9,
      30             :   B2 = 10,
      31             :   B3 = 11,
      32             :   B4 = 12,
      33             :   B5 = 13,
      34             :   B6 = 14,
      35             :   B7 = 15,
      36             :   B8 = 16,
      37             :   B9 = 17,
      38             :   B10 = 18,
      39             :   B11 = 19,
      40             :   B12 = 20,
      41             :   B13 = 21,
      42             :   B14 = 22,
      43             :   B15 = 23,
      44             :   B16 = 24,
      45             :   B17 = 25,
      46             :   B18 = 26,
      47             :   B19 = 27,
      48             :   B20 = 28,
      49             :   B21 = 29,
      50             :   B22 = 30,
      51             :   B23 = 31,
      52             :   B24 = 32,
      53             :   B25 = 33,
      54             :   B26 = 34,
      55             :   B27 = 35,
      56             :   B28 = 36,
      57             :   B29 = 37,
      58             :   B30 = 38,
      59             :   B31 = 39,
      60             :   D0 = 40,
      61             :   D1 = 41,
      62             :   D2 = 42,
      63             :   D3 = 43,
      64             :   D4 = 44,
      65             :   D5 = 45,
      66             :   D6 = 46,
      67             :   D7 = 47,
      68             :   D8 = 48,
      69             :   D9 = 49,
      70             :   D10 = 50,
      71             :   D11 = 51,
      72             :   D12 = 52,
      73             :   D13 = 53,
      74             :   D14 = 54,
      75             :   D15 = 55,
      76             :   D16 = 56,
      77             :   D17 = 57,
      78             :   D18 = 58,
      79             :   D19 = 59,
      80             :   D20 = 60,
      81             :   D21 = 61,
      82             :   D22 = 62,
      83             :   D23 = 63,
      84             :   D24 = 64,
      85             :   D25 = 65,
      86             :   D26 = 66,
      87             :   D27 = 67,
      88             :   D28 = 68,
      89             :   D29 = 69,
      90             :   D30 = 70,
      91             :   D31 = 71,
      92             :   H0 = 72,
      93             :   H1 = 73,
      94             :   H2 = 74,
      95             :   H3 = 75,
      96             :   H4 = 76,
      97             :   H5 = 77,
      98             :   H6 = 78,
      99             :   H7 = 79,
     100             :   H8 = 80,
     101             :   H9 = 81,
     102             :   H10 = 82,
     103             :   H11 = 83,
     104             :   H12 = 84,
     105             :   H13 = 85,
     106             :   H14 = 86,
     107             :   H15 = 87,
     108             :   H16 = 88,
     109             :   H17 = 89,
     110             :   H18 = 90,
     111             :   H19 = 91,
     112             :   H20 = 92,
     113             :   H21 = 93,
     114             :   H22 = 94,
     115             :   H23 = 95,
     116             :   H24 = 96,
     117             :   H25 = 97,
     118             :   H26 = 98,
     119             :   H27 = 99,
     120             :   H28 = 100,
     121             :   H29 = 101,
     122             :   H30 = 102,
     123             :   H31 = 103,
     124             :   Q0 = 104,
     125             :   Q1 = 105,
     126             :   Q2 = 106,
     127             :   Q3 = 107,
     128             :   Q4 = 108,
     129             :   Q5 = 109,
     130             :   Q6 = 110,
     131             :   Q7 = 111,
     132             :   Q8 = 112,
     133             :   Q9 = 113,
     134             :   Q10 = 114,
     135             :   Q11 = 115,
     136             :   Q12 = 116,
     137             :   Q13 = 117,
     138             :   Q14 = 118,
     139             :   Q15 = 119,
     140             :   Q16 = 120,
     141             :   Q17 = 121,
     142             :   Q18 = 122,
     143             :   Q19 = 123,
     144             :   Q20 = 124,
     145             :   Q21 = 125,
     146             :   Q22 = 126,
     147             :   Q23 = 127,
     148             :   Q24 = 128,
     149             :   Q25 = 129,
     150             :   Q26 = 130,
     151             :   Q27 = 131,
     152             :   Q28 = 132,
     153             :   Q29 = 133,
     154             :   Q30 = 134,
     155             :   Q31 = 135,
     156             :   S0 = 136,
     157             :   S1 = 137,
     158             :   S2 = 138,
     159             :   S3 = 139,
     160             :   S4 = 140,
     161             :   S5 = 141,
     162             :   S6 = 142,
     163             :   S7 = 143,
     164             :   S8 = 144,
     165             :   S9 = 145,
     166             :   S10 = 146,
     167             :   S11 = 147,
     168             :   S12 = 148,
     169             :   S13 = 149,
     170             :   S14 = 150,
     171             :   S15 = 151,
     172             :   S16 = 152,
     173             :   S17 = 153,
     174             :   S18 = 154,
     175             :   S19 = 155,
     176             :   S20 = 156,
     177             :   S21 = 157,
     178             :   S22 = 158,
     179             :   S23 = 159,
     180             :   S24 = 160,
     181             :   S25 = 161,
     182             :   S26 = 162,
     183             :   S27 = 163,
     184             :   S28 = 164,
     185             :   S29 = 165,
     186             :   S30 = 166,
     187             :   S31 = 167,
     188             :   W0 = 168,
     189             :   W1 = 169,
     190             :   W2 = 170,
     191             :   W3 = 171,
     192             :   W4 = 172,
     193             :   W5 = 173,
     194             :   W6 = 174,
     195             :   W7 = 175,
     196             :   W8 = 176,
     197             :   W9 = 177,
     198             :   W10 = 178,
     199             :   W11 = 179,
     200             :   W12 = 180,
     201             :   W13 = 181,
     202             :   W14 = 182,
     203             :   W15 = 183,
     204             :   W16 = 184,
     205             :   W17 = 185,
     206             :   W18 = 186,
     207             :   W19 = 187,
     208             :   W20 = 188,
     209             :   W21 = 189,
     210             :   W22 = 190,
     211             :   W23 = 191,
     212             :   W24 = 192,
     213             :   W25 = 193,
     214             :   W26 = 194,
     215             :   W27 = 195,
     216             :   W28 = 196,
     217             :   W29 = 197,
     218             :   W30 = 198,
     219             :   X0 = 199,
     220             :   X1 = 200,
     221             :   X2 = 201,
     222             :   X3 = 202,
     223             :   X4 = 203,
     224             :   X5 = 204,
     225             :   X6 = 205,
     226             :   X7 = 206,
     227             :   X8 = 207,
     228             :   X9 = 208,
     229             :   X10 = 209,
     230             :   X11 = 210,
     231             :   X12 = 211,
     232             :   X13 = 212,
     233             :   X14 = 213,
     234             :   X15 = 214,
     235             :   X16 = 215,
     236             :   X17 = 216,
     237             :   X18 = 217,
     238             :   X19 = 218,
     239             :   X20 = 219,
     240             :   X21 = 220,
     241             :   X22 = 221,
     242             :   X23 = 222,
     243             :   X24 = 223,
     244             :   X25 = 224,
     245             :   X26 = 225,
     246             :   X27 = 226,
     247             :   X28 = 227,
     248             :   D0_D1 = 228,
     249             :   D1_D2 = 229,
     250             :   D2_D3 = 230,
     251             :   D3_D4 = 231,
     252             :   D4_D5 = 232,
     253             :   D5_D6 = 233,
     254             :   D6_D7 = 234,
     255             :   D7_D8 = 235,
     256             :   D8_D9 = 236,
     257             :   D9_D10 = 237,
     258             :   D10_D11 = 238,
     259             :   D11_D12 = 239,
     260             :   D12_D13 = 240,
     261             :   D13_D14 = 241,
     262             :   D14_D15 = 242,
     263             :   D15_D16 = 243,
     264             :   D16_D17 = 244,
     265             :   D17_D18 = 245,
     266             :   D18_D19 = 246,
     267             :   D19_D20 = 247,
     268             :   D20_D21 = 248,
     269             :   D21_D22 = 249,
     270             :   D22_D23 = 250,
     271             :   D23_D24 = 251,
     272             :   D24_D25 = 252,
     273             :   D25_D26 = 253,
     274             :   D26_D27 = 254,
     275             :   D27_D28 = 255,
     276             :   D28_D29 = 256,
     277             :   D29_D30 = 257,
     278             :   D30_D31 = 258,
     279             :   D31_D0 = 259,
     280             :   D0_D1_D2_D3 = 260,
     281             :   D1_D2_D3_D4 = 261,
     282             :   D2_D3_D4_D5 = 262,
     283             :   D3_D4_D5_D6 = 263,
     284             :   D4_D5_D6_D7 = 264,
     285             :   D5_D6_D7_D8 = 265,
     286             :   D6_D7_D8_D9 = 266,
     287             :   D7_D8_D9_D10 = 267,
     288             :   D8_D9_D10_D11 = 268,
     289             :   D9_D10_D11_D12 = 269,
     290             :   D10_D11_D12_D13 = 270,
     291             :   D11_D12_D13_D14 = 271,
     292             :   D12_D13_D14_D15 = 272,
     293             :   D13_D14_D15_D16 = 273,
     294             :   D14_D15_D16_D17 = 274,
     295             :   D15_D16_D17_D18 = 275,
     296             :   D16_D17_D18_D19 = 276,
     297             :   D17_D18_D19_D20 = 277,
     298             :   D18_D19_D20_D21 = 278,
     299             :   D19_D20_D21_D22 = 279,
     300             :   D20_D21_D22_D23 = 280,
     301             :   D21_D22_D23_D24 = 281,
     302             :   D22_D23_D24_D25 = 282,
     303             :   D23_D24_D25_D26 = 283,
     304             :   D24_D25_D26_D27 = 284,
     305             :   D25_D26_D27_D28 = 285,
     306             :   D26_D27_D28_D29 = 286,
     307             :   D27_D28_D29_D30 = 287,
     308             :   D28_D29_D30_D31 = 288,
     309             :   D29_D30_D31_D0 = 289,
     310             :   D30_D31_D0_D1 = 290,
     311             :   D31_D0_D1_D2 = 291,
     312             :   D0_D1_D2 = 292,
     313             :   D1_D2_D3 = 293,
     314             :   D2_D3_D4 = 294,
     315             :   D3_D4_D5 = 295,
     316             :   D4_D5_D6 = 296,
     317             :   D5_D6_D7 = 297,
     318             :   D6_D7_D8 = 298,
     319             :   D7_D8_D9 = 299,
     320             :   D8_D9_D10 = 300,
     321             :   D9_D10_D11 = 301,
     322             :   D10_D11_D12 = 302,
     323             :   D11_D12_D13 = 303,
     324             :   D12_D13_D14 = 304,
     325             :   D13_D14_D15 = 305,
     326             :   D14_D15_D16 = 306,
     327             :   D15_D16_D17 = 307,
     328             :   D16_D17_D18 = 308,
     329             :   D17_D18_D19 = 309,
     330             :   D18_D19_D20 = 310,
     331             :   D19_D20_D21 = 311,
     332             :   D20_D21_D22 = 312,
     333             :   D21_D22_D23 = 313,
     334             :   D22_D23_D24 = 314,
     335             :   D23_D24_D25 = 315,
     336             :   D24_D25_D26 = 316,
     337             :   D25_D26_D27 = 317,
     338             :   D26_D27_D28 = 318,
     339             :   D27_D28_D29 = 319,
     340             :   D28_D29_D30 = 320,
     341             :   D29_D30_D31 = 321,
     342             :   D30_D31_D0 = 322,
     343             :   D31_D0_D1 = 323,
     344             :   Q0_Q1 = 324,
     345             :   Q1_Q2 = 325,
     346             :   Q2_Q3 = 326,
     347             :   Q3_Q4 = 327,
     348             :   Q4_Q5 = 328,
     349             :   Q5_Q6 = 329,
     350             :   Q6_Q7 = 330,
     351             :   Q7_Q8 = 331,
     352             :   Q8_Q9 = 332,
     353             :   Q9_Q10 = 333,
     354             :   Q10_Q11 = 334,
     355             :   Q11_Q12 = 335,
     356             :   Q12_Q13 = 336,
     357             :   Q13_Q14 = 337,
     358             :   Q14_Q15 = 338,
     359             :   Q15_Q16 = 339,
     360             :   Q16_Q17 = 340,
     361             :   Q17_Q18 = 341,
     362             :   Q18_Q19 = 342,
     363             :   Q19_Q20 = 343,
     364             :   Q20_Q21 = 344,
     365             :   Q21_Q22 = 345,
     366             :   Q22_Q23 = 346,
     367             :   Q23_Q24 = 347,
     368             :   Q24_Q25 = 348,
     369             :   Q25_Q26 = 349,
     370             :   Q26_Q27 = 350,
     371             :   Q27_Q28 = 351,
     372             :   Q28_Q29 = 352,
     373             :   Q29_Q30 = 353,
     374             :   Q30_Q31 = 354,
     375             :   Q31_Q0 = 355,
     376             :   Q0_Q1_Q2_Q3 = 356,
     377             :   Q1_Q2_Q3_Q4 = 357,
     378             :   Q2_Q3_Q4_Q5 = 358,
     379             :   Q3_Q4_Q5_Q6 = 359,
     380             :   Q4_Q5_Q6_Q7 = 360,
     381             :   Q5_Q6_Q7_Q8 = 361,
     382             :   Q6_Q7_Q8_Q9 = 362,
     383             :   Q7_Q8_Q9_Q10 = 363,
     384             :   Q8_Q9_Q10_Q11 = 364,
     385             :   Q9_Q10_Q11_Q12 = 365,
     386             :   Q10_Q11_Q12_Q13 = 366,
     387             :   Q11_Q12_Q13_Q14 = 367,
     388             :   Q12_Q13_Q14_Q15 = 368,
     389             :   Q13_Q14_Q15_Q16 = 369,
     390             :   Q14_Q15_Q16_Q17 = 370,
     391             :   Q15_Q16_Q17_Q18 = 371,
     392             :   Q16_Q17_Q18_Q19 = 372,
     393             :   Q17_Q18_Q19_Q20 = 373,
     394             :   Q18_Q19_Q20_Q21 = 374,
     395             :   Q19_Q20_Q21_Q22 = 375,
     396             :   Q20_Q21_Q22_Q23 = 376,
     397             :   Q21_Q22_Q23_Q24 = 377,
     398             :   Q22_Q23_Q24_Q25 = 378,
     399             :   Q23_Q24_Q25_Q26 = 379,
     400             :   Q24_Q25_Q26_Q27 = 380,
     401             :   Q25_Q26_Q27_Q28 = 381,
     402             :   Q26_Q27_Q28_Q29 = 382,
     403             :   Q27_Q28_Q29_Q30 = 383,
     404             :   Q28_Q29_Q30_Q31 = 384,
     405             :   Q29_Q30_Q31_Q0 = 385,
     406             :   Q30_Q31_Q0_Q1 = 386,
     407             :   Q31_Q0_Q1_Q2 = 387,
     408             :   Q0_Q1_Q2 = 388,
     409             :   Q1_Q2_Q3 = 389,
     410             :   Q2_Q3_Q4 = 390,
     411             :   Q3_Q4_Q5 = 391,
     412             :   Q4_Q5_Q6 = 392,
     413             :   Q5_Q6_Q7 = 393,
     414             :   Q6_Q7_Q8 = 394,
     415             :   Q7_Q8_Q9 = 395,
     416             :   Q8_Q9_Q10 = 396,
     417             :   Q9_Q10_Q11 = 397,
     418             :   Q10_Q11_Q12 = 398,
     419             :   Q11_Q12_Q13 = 399,
     420             :   Q12_Q13_Q14 = 400,
     421             :   Q13_Q14_Q15 = 401,
     422             :   Q14_Q15_Q16 = 402,
     423             :   Q15_Q16_Q17 = 403,
     424             :   Q16_Q17_Q18 = 404,
     425             :   Q17_Q18_Q19 = 405,
     426             :   Q18_Q19_Q20 = 406,
     427             :   Q19_Q20_Q21 = 407,
     428             :   Q20_Q21_Q22 = 408,
     429             :   Q21_Q22_Q23 = 409,
     430             :   Q22_Q23_Q24 = 410,
     431             :   Q23_Q24_Q25 = 411,
     432             :   Q24_Q25_Q26 = 412,
     433             :   Q25_Q26_Q27 = 413,
     434             :   Q26_Q27_Q28 = 414,
     435             :   Q27_Q28_Q29 = 415,
     436             :   Q28_Q29_Q30 = 416,
     437             :   Q29_Q30_Q31 = 417,
     438             :   Q30_Q31_Q0 = 418,
     439             :   Q31_Q0_Q1 = 419,
     440             :   WZR_W0 = 420,
     441             :   W30_WZR = 421,
     442             :   W0_W1 = 422,
     443             :   W1_W2 = 423,
     444             :   W2_W3 = 424,
     445             :   W3_W4 = 425,
     446             :   W4_W5 = 426,
     447             :   W5_W6 = 427,
     448             :   W6_W7 = 428,
     449             :   W7_W8 = 429,
     450             :   W8_W9 = 430,
     451             :   W9_W10 = 431,
     452             :   W10_W11 = 432,
     453             :   W11_W12 = 433,
     454             :   W12_W13 = 434,
     455             :   W13_W14 = 435,
     456             :   W14_W15 = 436,
     457             :   W15_W16 = 437,
     458             :   W16_W17 = 438,
     459             :   W17_W18 = 439,
     460             :   W18_W19 = 440,
     461             :   W19_W20 = 441,
     462             :   W20_W21 = 442,
     463             :   W21_W22 = 443,
     464             :   W22_W23 = 444,
     465             :   W23_W24 = 445,
     466             :   W24_W25 = 446,
     467             :   W25_W26 = 447,
     468             :   W26_W27 = 448,
     469             :   W27_W28 = 449,
     470             :   W28_W29 = 450,
     471             :   W29_W30 = 451,
     472             :   FP_LR = 452,
     473             :   LR_XZR = 453,
     474             :   XZR_X0 = 454,
     475             :   X28_FP = 455,
     476             :   X0_X1 = 456,
     477             :   X1_X2 = 457,
     478             :   X2_X3 = 458,
     479             :   X3_X4 = 459,
     480             :   X4_X5 = 460,
     481             :   X5_X6 = 461,
     482             :   X6_X7 = 462,
     483             :   X7_X8 = 463,
     484             :   X8_X9 = 464,
     485             :   X9_X10 = 465,
     486             :   X10_X11 = 466,
     487             :   X11_X12 = 467,
     488             :   X12_X13 = 468,
     489             :   X13_X14 = 469,
     490             :   X14_X15 = 470,
     491             :   X15_X16 = 471,
     492             :   X16_X17 = 472,
     493             :   X17_X18 = 473,
     494             :   X18_X19 = 474,
     495             :   X19_X20 = 475,
     496             :   X20_X21 = 476,
     497             :   X21_X22 = 477,
     498             :   X22_X23 = 478,
     499             :   X23_X24 = 479,
     500             :   X24_X25 = 480,
     501             :   X25_X26 = 481,
     502             :   X26_X27 = 482,
     503             :   X27_X28 = 483,
     504             :   NUM_TARGET_REGS       // 484
     505             : };
     506             : } // end namespace AArch64
     507             : 
     508             : // Register classes
     509             : 
     510             : namespace AArch64 {
     511             : enum {
     512             :   FPR8RegClassID = 0,
     513             :   FPR16RegClassID = 1,
     514             :   GPR32allRegClassID = 2,
     515             :   FPR32RegClassID = 3,
     516             :   GPR32RegClassID = 4,
     517             :   GPR32spRegClassID = 5,
     518             :   GPR32commonRegClassID = 6,
     519             :   CCRRegClassID = 7,
     520             :   GPR32sponlyRegClassID = 8,
     521             :   WSeqPairsClassRegClassID = 9,
     522             :   WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 10,
     523             :   WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 11,
     524             :   WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 12,
     525             :   GPR64allRegClassID = 13,
     526             :   FPR64RegClassID = 14,
     527             :   GPR64RegClassID = 15,
     528             :   GPR64spRegClassID = 16,
     529             :   GPR64commonRegClassID = 17,
     530             :   tcGPR64RegClassID = 18,
     531             :   GPR64sponlyRegClassID = 19,
     532             :   DDRegClassID = 20,
     533             :   XSeqPairsClassRegClassID = 21,
     534             :   XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 22,
     535             :   XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 23,
     536             :   XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 24,
     537             :   XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 25,
     538             :   XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 26,
     539             :   XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 27,
     540             :   FPR128RegClassID = 28,
     541             :   FPR128_loRegClassID = 29,
     542             :   DDDRegClassID = 30,
     543             :   DDDDRegClassID = 31,
     544             :   QQRegClassID = 32,
     545             :   QQ_with_qsub0_in_FPR128_loRegClassID = 33,
     546             :   QQ_with_qsub1_in_FPR128_loRegClassID = 34,
     547             :   QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 35,
     548             :   QQQRegClassID = 36,
     549             :   QQQ_with_qsub0_in_FPR128_loRegClassID = 37,
     550             :   QQQ_with_qsub1_in_FPR128_loRegClassID = 38,
     551             :   QQQ_with_qsub2_in_FPR128_loRegClassID = 39,
     552             :   QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 40,
     553             :   QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 41,
     554             :   QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 42,
     555             :   QQQQRegClassID = 43,
     556             :   QQQQ_with_qsub0_in_FPR128_loRegClassID = 44,
     557             :   QQQQ_with_qsub1_in_FPR128_loRegClassID = 45,
     558             :   QQQQ_with_qsub2_in_FPR128_loRegClassID = 46,
     559             :   QQQQ_with_qsub3_in_FPR128_loRegClassID = 47,
     560             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 48,
     561             :   QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 49,
     562             :   QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 50,
     563             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 51,
     564             :   QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 52,
     565             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 53,
     566             : 
     567             :   };
     568             : } // end namespace AArch64
     569             : 
     570             : 
     571             : // Register alternate name indices
     572             : 
     573             : namespace AArch64 {
     574             : enum {
     575             :   NoRegAltName, // 0
     576             :   vlist1,       // 1
     577             :   vreg, // 2
     578             :   NUM_TARGET_REG_ALT_NAMES = 3
     579             : };
     580             : } // end namespace AArch64
     581             : 
     582             : 
     583             : // Subregister indices
     584             : 
     585             : namespace AArch64 {
     586             : enum {
     587             :   NoSubRegister,
     588             :   bsub, // 1
     589             :   dsub, // 2
     590             :   dsub0,        // 3
     591             :   dsub1,        // 4
     592             :   dsub2,        // 5
     593             :   dsub3,        // 6
     594             :   hsub, // 7
     595             :   qhisub,       // 8
     596             :   qsub, // 9
     597             :   qsub0,        // 10
     598             :   qsub1,        // 11
     599             :   qsub2,        // 12
     600             :   qsub3,        // 13
     601             :   ssub, // 14
     602             :   sub_32,       // 15
     603             :   sube32,       // 16
     604             :   sube64,       // 17
     605             :   subo32,       // 18
     606             :   subo64,       // 19
     607             :   dsub1_then_bsub,      // 20
     608             :   dsub1_then_hsub,      // 21
     609             :   dsub1_then_ssub,      // 22
     610             :   dsub3_then_bsub,      // 23
     611             :   dsub3_then_hsub,      // 24
     612             :   dsub3_then_ssub,      // 25
     613             :   dsub2_then_bsub,      // 26
     614             :   dsub2_then_hsub,      // 27
     615             :   dsub2_then_ssub,      // 28
     616             :   qsub1_then_bsub,      // 29
     617             :   qsub1_then_dsub,      // 30
     618             :   qsub1_then_hsub,      // 31
     619             :   qsub1_then_ssub,      // 32
     620             :   qsub3_then_bsub,      // 33
     621             :   qsub3_then_dsub,      // 34
     622             :   qsub3_then_hsub,      // 35
     623             :   qsub3_then_ssub,      // 36
     624             :   qsub2_then_bsub,      // 37
     625             :   qsub2_then_dsub,      // 38
     626             :   qsub2_then_hsub,      // 39
     627             :   qsub2_then_ssub,      // 40
     628             :   subo64_then_sub_32,   // 41
     629             :   dsub0_dsub1,  // 42
     630             :   dsub0_dsub1_dsub2,    // 43
     631             :   dsub1_dsub2,  // 44
     632             :   dsub1_dsub2_dsub3,    // 45
     633             :   dsub2_dsub3,  // 46
     634             :   dsub_qsub1_then_dsub, // 47
     635             :   dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 48
     636             :   dsub_qsub1_then_dsub_qsub2_then_dsub, // 49
     637             :   qsub0_qsub1,  // 50
     638             :   qsub0_qsub1_qsub2,    // 51
     639             :   qsub1_qsub2,  // 52
     640             :   qsub1_qsub2_qsub3,    // 53
     641             :   qsub2_qsub3,  // 54
     642             :   qsub1_then_dsub_qsub2_then_dsub,      // 55
     643             :   qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,      // 56
     644             :   qsub2_then_dsub_qsub3_then_dsub,      // 57
     645             :   sub_32_subo64_then_sub_32,    // 58
     646             :   NUM_TARGET_SUBREGS
     647             : };
     648             : } // end namespace AArch64
     649             : 
     650             : } // end namespace llvm
     651             : 
     652             : #endif // GET_REGINFO_ENUM
     653             : 
     654             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
     655             : |*                                                                            *|
     656             : |* MC Register Information                                                    *|
     657             : |*                                                                            *|
     658             : |* Automatically generated file, do not edit!                                 *|
     659             : |*                                                                            *|
     660             : \*===----------------------------------------------------------------------===*/
     661             : 
     662             : 
     663             : #ifdef GET_REGINFO_MC_DESC
     664             : #undef GET_REGINFO_MC_DESC
     665             : 
     666             : namespace llvm {
     667             : 
     668             : extern const MCPhysReg AArch64RegDiffLists[] = {
     669             :   /* 0 */ 0, 1, 0,
     670             :   /* 3 */ 65185, 1, 1, 1, 0,
     671             :   /* 8 */ 65281, 1, 1, 1, 0,
     672             :   /* 13 */ 5, 29, 1, 1, 0,
     673             :   /* 18 */ 65340, 419, 30, 1, 1, 0,
     674             :   /* 24 */ 65153, 1, 1, 0,
     675             :   /* 28 */ 65249, 1, 1, 0,
     676             :   /* 32 */ 5, 1, 29, 1, 0,
     677             :   /* 37 */ 5, 30, 1, 0,
     678             :   /* 41 */ 1, 413, 1, 32, 1, 0,
     679             :   /* 47 */ 31, 222, 1, 33, 1, 0,
     680             :   /* 53 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 218, 1, 0,
     681             :   /* 68 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 250, 1, 0,
     682             :   /* 83 */ 256, 1, 0,
     683             :   /* 86 */ 446, 1, 0,
     684             :   /* 89 */ 450, 1, 0,
     685             :   /* 92 */ 65117, 1, 0,
     686             :   /* 95 */ 65151, 1, 0,
     687             :   /* 98 */ 65217, 1, 0,
     688             :   /* 101 */ 65282, 1, 0,
     689             :   /* 104 */ 65313, 1, 0,
     690             :   /* 107 */ 64, 64, 65440, 64, 123, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     691             :   /* 130 */ 219, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     692             :   /* 140 */ 64, 64, 65440, 64, 124, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     693             :   /* 163 */ 220, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     694             :   /* 173 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 0,
     695             :   /* 185 */ 64, 64, 65440, 64, 123, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     696             :   /* 208 */ 219, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     697             :   /* 218 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 0,
     698             :   /* 230 */ 65503, 1, 128, 65503, 1, 0,
     699             :   /* 236 */ 31, 221, 2, 32, 2, 0,
     700             :   /* 242 */ 255, 2, 0,
     701             :   /* 245 */ 65340, 449, 1, 1, 3, 0,
     702             :   /* 251 */ 451, 3, 0,
     703             :   /* 254 */ 65084, 3, 0,
     704             :   /* 257 */ 4, 0,
     705             :   /* 259 */ 5, 0,
     706             :   /* 261 */ 31, 222, 1, 5, 28, 0,
     707             :   /* 267 */ 228, 28, 0,
     708             :   /* 270 */ 5, 1, 1, 29, 0,
     709             :   /* 275 */ 64, 64, 65440, 64, 123, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     710             :   /* 298 */ 219, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     711             :   /* 308 */ 5, 1, 30, 0,
     712             :   /* 312 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 0,
     713             :   /* 324 */ 5, 31, 0,
     714             :   /* 327 */ 65504, 31, 97, 65504, 31, 0,
     715             :   /* 333 */ 32, 0,
     716             :   /* 335 */ 4, 33, 0,
     717             :   /* 338 */ 64178, 33, 0,
     718             :   /* 341 */ 34, 0,
     719             :   /* 343 */ 0, 65, 0,
     720             :   /* 346 */ 96, 0,
     721             :   /* 348 */ 65122, 162, 0,
     722             :   /* 351 */ 196, 0,
     723             :   /* 353 */ 65316, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 219, 0,
     724             :   /* 365 */ 65316, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 251, 0,
     725             :   /* 377 */ 65089, 65535, 193, 65505, 252, 0,
     726             :   /* 383 */ 65085, 196, 65341, 196, 253, 0,
     727             :   /* 389 */ 65308, 65505, 65341, 196, 253, 0,
     728             :   /* 395 */ 65279, 65505, 32, 65505, 253, 0,
     729             :   /* 401 */ 65085, 196, 65345, 65535, 415, 0,
     730             :   /* 407 */ 65339, 0,
     731             :   /* 409 */ 65313, 65344, 0,
     732             :   /* 412 */ 65374, 0,
     733             :   /* 414 */ 65405, 0,
     734             :   /* 416 */ 65437, 0,
     735             :   /* 418 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 218, 64, 32, 1, 65440, 0,
     736             :   /* 439 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 250, 64, 32, 1, 65440, 0,
     737             :   /* 460 */ 65252, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 250, 64, 32, 65505, 65440, 0,
     738             :   /* 481 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
     739             :   /* 513 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65473, 64, 65441, 0,
     740             :   /* 535 */ 65469, 0,
     741             :   /* 537 */ 65348, 96, 65472, 65472, 1, 96, 65472, 65472, 0,
     742             :   /* 546 */ 65348, 96, 65472, 65472, 33, 96, 65472, 65472, 0,
     743             :   /* 555 */ 65472, 96, 65472, 65472, 0,
     744             :   /* 560 */ 65284, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
     745             :   /* 592 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 217, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
     746             :   /* 624 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
     747             :   /* 656 */ 65316, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65441, 64, 65473, 0,
     748             :   /* 678 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 217, 64, 65473, 64, 65473, 0,
     749             :   /* 700 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 249, 64, 65473, 64, 65473, 0,
     750             :   /* 722 */ 65501, 0,
     751             :   /* 724 */ 65284, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 250, 65505, 0,
     752             :   /* 739 */ 65533, 0,
     753             :   /* 741 */ 65535, 0,
     754             : };
     755             : 
     756             : extern const LaneBitmask AArch64LaneMaskLists[] = {
     757             :   /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
     758             :   /* 2 */ LaneBitmask(0x00000040), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     759             :   /* 5 */ LaneBitmask(0x00000040), LaneBitmask(0x00000100), LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     760             :   /* 10 */ LaneBitmask(0x00000040), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     761             :   /* 14 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     762             :   /* 17 */ LaneBitmask(0x00000200), LaneBitmask(0x00000800), LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     763             :   /* 22 */ LaneBitmask(0x00000200), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     764             :   /* 26 */ LaneBitmask(0x00001000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
     765             :   /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
     766             :   /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
     767             :   /* 35 */ LaneBitmask(0x00000100), LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
     768             :   /* 40 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
     769             :   /* 44 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask(0x00000100), LaneBitmask(0x00000080), LaneBitmask::getAll(),
     770             :   /* 49 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask(0x00000100), LaneBitmask::getAll(),
     771             :   /* 54 */ LaneBitmask(0x00000800), LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask(0x00000200), LaneBitmask::getAll(),
     772             :   /* 59 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000200), LaneBitmask::getAll(),
     773             :   /* 63 */ LaneBitmask(0x00000001), LaneBitmask(0x00000200), LaneBitmask(0x00000800), LaneBitmask(0x00000400), LaneBitmask::getAll(),
     774             :   /* 68 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask(0x00000200), LaneBitmask(0x00000800), LaneBitmask::getAll(),
     775             :   /* 73 */ LaneBitmask(0x00000008), LaneBitmask(0x00001000), LaneBitmask::getAll(),
     776       72306 : };
     777             : 
     778             : extern const uint16_t AArch64SubRegIdxLists[] = {
     779             :   /* 0 */ 2, 14, 7, 1, 0,
     780             :   /* 5 */ 15, 0,
     781             :   /* 7 */ 16, 18, 0,
     782             :   /* 10 */ 3, 14, 7, 1, 4, 22, 21, 20, 0,
     783             :   /* 19 */ 3, 14, 7, 1, 4, 22, 21, 20, 5, 28, 27, 26, 42, 44, 0,
     784             :   /* 34 */ 3, 14, 7, 1, 4, 22, 21, 20, 5, 28, 27, 26, 6, 25, 24, 23, 42, 43, 44, 45, 46, 0,
     785             :   /* 56 */ 10, 2, 14, 7, 1, 11, 30, 32, 31, 29, 47, 0,
     786             :   /* 68 */ 10, 2, 14, 7, 1, 11, 30, 32, 31, 29, 12, 38, 40, 39, 37, 47, 49, 50, 52, 55, 0,
     787             :   /* 89 */ 10, 2, 14, 7, 1, 11, 30, 32, 31, 29, 12, 38, 40, 39, 37, 13, 34, 36, 35, 33, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 0,
     788             :   /* 121 */ 17, 15, 19, 41, 58, 0,
     789             : };
     790             : 
     791             : extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
     792             :   { 65535, 65535 },
     793             :   { 0, 8 },     // bsub
     794             :   { 0, 32 },    // dsub
     795             :   { 0, 64 },    // dsub0
     796             :   { 0, 64 },    // dsub1
     797             :   { 0, 64 },    // dsub2
     798             :   { 0, 64 },    // dsub3
     799             :   { 0, 16 },    // hsub
     800             :   { 0, 64 },    // qhisub
     801             :   { 0, 64 },    // qsub
     802             :   { 0, 128 },   // qsub0
     803             :   { 0, 128 },   // qsub1
     804             :   { 0, 128 },   // qsub2
     805             :   { 0, 128 },   // qsub3
     806             :   { 0, 32 },    // ssub
     807             :   { 0, 32 },    // sub_32
     808             :   { 0, 32 },    // sube32
     809             :   { 0, 64 },    // sube64
     810             :   { 0, 32 },    // subo32
     811             :   { 0, 64 },    // subo64
     812             :   { 0, 8 },     // dsub1_then_bsub
     813             :   { 0, 16 },    // dsub1_then_hsub
     814             :   { 0, 32 },    // dsub1_then_ssub
     815             :   { 0, 8 },     // dsub3_then_bsub
     816             :   { 0, 16 },    // dsub3_then_hsub
     817             :   { 0, 32 },    // dsub3_then_ssub
     818             :   { 0, 8 },     // dsub2_then_bsub
     819             :   { 0, 16 },    // dsub2_then_hsub
     820             :   { 0, 32 },    // dsub2_then_ssub
     821             :   { 0, 8 },     // qsub1_then_bsub
     822             :   { 0, 32 },    // qsub1_then_dsub
     823             :   { 0, 16 },    // qsub1_then_hsub
     824             :   { 0, 32 },    // qsub1_then_ssub
     825             :   { 0, 8 },     // qsub3_then_bsub
     826             :   { 0, 32 },    // qsub3_then_dsub
     827             :   { 0, 16 },    // qsub3_then_hsub
     828             :   { 0, 32 },    // qsub3_then_ssub
     829             :   { 0, 8 },     // qsub2_then_bsub
     830             :   { 0, 32 },    // qsub2_then_dsub
     831             :   { 0, 16 },    // qsub2_then_hsub
     832             :   { 0, 32 },    // qsub2_then_ssub
     833             :   { 0, 32 },    // subo64_then_sub_32
     834             :   { 65535, 128 },       // dsub0_dsub1
     835             :   { 65535, 192 },       // dsub0_dsub1_dsub2
     836             :   { 65535, 128 },       // dsub1_dsub2
     837             :   { 65535, 192 },       // dsub1_dsub2_dsub3
     838             :   { 65535, 128 },       // dsub2_dsub3
     839             :   { 65535, 64 },        // dsub_qsub1_then_dsub
     840             :   { 65535, 128 },       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
     841             :   { 65535, 96 },        // dsub_qsub1_then_dsub_qsub2_then_dsub
     842             :   { 65535, 256 },       // qsub0_qsub1
     843             :   { 65535, 384 },       // qsub0_qsub1_qsub2
     844             :   { 65535, 256 },       // qsub1_qsub2
     845             :   { 65535, 384 },       // qsub1_qsub2_qsub3
     846             :   { 65535, 256 },       // qsub2_qsub3
     847             :   { 65535, 64 },        // qsub1_then_dsub_qsub2_then_dsub
     848             :   { 65535, 96 },        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
     849             :   { 65535, 64 },        // qsub2_then_dsub_qsub3_then_dsub
     850             :   { 65535, 64 },        // sub_32_subo64_then_sub_32
     851             : };
     852             : 
     853             : extern const char AArch64RegStrings[] = {
     854             :   /* 0 */ 'B', '1', '0', 0,
     855             :   /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
     856             :   /* 17 */ 'H', '1', '0', 0,
     857             :   /* 21 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
     858             :   /* 34 */ 'S', '1', '0', 0,
     859             :   /* 38 */ 'W', '9', '_', 'W', '1', '0', 0,
     860             :   /* 45 */ 'X', '9', '_', 'X', '1', '0', 0,
     861             :   /* 52 */ 'B', '2', '0', 0,
     862             :   /* 56 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
     863             :   /* 72 */ 'H', '2', '0', 0,
     864             :   /* 76 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
     865             :   /* 92 */ 'S', '2', '0', 0,
     866             :   /* 96 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
     867             :   /* 104 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
     868             :   /* 112 */ 'B', '3', '0', 0,
     869             :   /* 116 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
     870             :   /* 132 */ 'H', '3', '0', 0,
     871             :   /* 136 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
     872             :   /* 152 */ 'S', '3', '0', 0,
     873             :   /* 156 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
     874             :   /* 164 */ 'B', '0', 0,
     875             :   /* 167 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
     876             :   /* 182 */ 'H', '0', 0,
     877             :   /* 185 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
     878             :   /* 200 */ 'S', '0', 0,
     879             :   /* 203 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
     880             :   /* 210 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
     881             :   /* 217 */ 'B', '1', '1', 0,
     882             :   /* 221 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
     883             :   /* 235 */ 'H', '1', '1', 0,
     884             :   /* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
     885             :   /* 253 */ 'S', '1', '1', 0,
     886             :   /* 257 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
     887             :   /* 265 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
     888             :   /* 273 */ 'B', '2', '1', 0,
     889             :   /* 277 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
     890             :   /* 293 */ 'H', '2', '1', 0,
     891             :   /* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
     892             :   /* 313 */ 'S', '2', '1', 0,
     893             :   /* 317 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
     894             :   /* 325 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
     895             :   /* 333 */ 'B', '3', '1', 0,
     896             :   /* 337 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
     897             :   /* 353 */ 'H', '3', '1', 0,
     898             :   /* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
     899             :   /* 373 */ 'S', '3', '1', 0,
     900             :   /* 377 */ 'B', '1', 0,
     901             :   /* 380 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
     902             :   /* 394 */ 'H', '1', 0,
     903             :   /* 397 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
     904             :   /* 411 */ 'S', '1', 0,
     905             :   /* 414 */ 'W', '0', '_', 'W', '1', 0,
     906             :   /* 420 */ 'X', '0', '_', 'X', '1', 0,
     907             :   /* 426 */ 'B', '1', '2', 0,
     908             :   /* 430 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
     909             :   /* 445 */ 'H', '1', '2', 0,
     910             :   /* 449 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
     911             :   /* 464 */ 'S', '1', '2', 0,
     912             :   /* 468 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
     913             :   /* 476 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
     914             :   /* 484 */ 'B', '2', '2', 0,
     915             :   /* 488 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
     916             :   /* 504 */ 'H', '2', '2', 0,
     917             :   /* 508 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
     918             :   /* 524 */ 'S', '2', '2', 0,
     919             :   /* 528 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
     920             :   /* 536 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
     921             :   /* 544 */ 'B', '2', 0,
     922             :   /* 547 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
     923             :   /* 560 */ 'H', '2', 0,
     924             :   /* 563 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
     925             :   /* 576 */ 'S', '2', 0,
     926             :   /* 579 */ 'W', '1', '_', 'W', '2', 0,
     927             :   /* 585 */ 'X', '1', '_', 'X', '2', 0,
     928             :   /* 591 */ 'B', '1', '3', 0,
     929             :   /* 595 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
     930             :   /* 611 */ 'H', '1', '3', 0,
     931             :   /* 615 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
     932             :   /* 631 */ 'S', '1', '3', 0,
     933             :   /* 635 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
     934             :   /* 643 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
     935             :   /* 651 */ 'B', '2', '3', 0,
     936             :   /* 655 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
     937             :   /* 671 */ 'H', '2', '3', 0,
     938             :   /* 675 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
     939             :   /* 691 */ 'S', '2', '3', 0,
     940             :   /* 695 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
     941             :   /* 703 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
     942             :   /* 711 */ 'B', '3', 0,
     943             :   /* 714 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
     944             :   /* 726 */ 'H', '3', 0,
     945             :   /* 729 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
     946             :   /* 741 */ 'S', '3', 0,
     947             :   /* 744 */ 'W', '2', '_', 'W', '3', 0,
     948             :   /* 750 */ 'X', '2', '_', 'X', '3', 0,
     949             :   /* 756 */ 'B', '1', '4', 0,
     950             :   /* 760 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
     951             :   /* 776 */ 'H', '1', '4', 0,
     952             :   /* 780 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
     953             :   /* 796 */ 'S', '1', '4', 0,
     954             :   /* 800 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
     955             :   /* 808 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
     956             :   /* 816 */ 'B', '2', '4', 0,
     957             :   /* 820 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
     958             :   /* 836 */ 'H', '2', '4', 0,
     959             :   /* 840 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
     960             :   /* 856 */ 'S', '2', '4', 0,
     961             :   /* 860 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
     962             :   /* 868 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
     963             :   /* 876 */ 'B', '4', 0,
     964             :   /* 879 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
     965             :   /* 891 */ 'H', '4', 0,
     966             :   /* 894 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
     967             :   /* 906 */ 'S', '4', 0,
     968             :   /* 909 */ 'W', '3', '_', 'W', '4', 0,
     969             :   /* 915 */ 'X', '3', '_', 'X', '4', 0,
     970             :   /* 921 */ 'B', '1', '5', 0,
     971             :   /* 925 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
     972             :   /* 941 */ 'H', '1', '5', 0,
     973             :   /* 945 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
     974             :   /* 961 */ 'S', '1', '5', 0,
     975             :   /* 965 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
     976             :   /* 973 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
     977             :   /* 981 */ 'B', '2', '5', 0,
     978             :   /* 985 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
     979             :   /* 1001 */ 'H', '2', '5', 0,
     980             :   /* 1005 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
     981             :   /* 1021 */ 'S', '2', '5', 0,
     982             :   /* 1025 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
     983             :   /* 1033 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
     984             :   /* 1041 */ 'B', '5', 0,
     985             :   /* 1044 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
     986             :   /* 1056 */ 'H', '5', 0,
     987             :   /* 1059 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
     988             :   /* 1071 */ 'S', '5', 0,
     989             :   /* 1074 */ 'W', '4', '_', 'W', '5', 0,
     990             :   /* 1080 */ 'X', '4', '_', 'X', '5', 0,
     991             :   /* 1086 */ 'B', '1', '6', 0,
     992             :   /* 1090 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
     993             :   /* 1106 */ 'H', '1', '6', 0,
     994             :   /* 1110 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
     995             :   /* 1126 */ 'S', '1', '6', 0,
     996             :   /* 1130 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
     997             :   /* 1138 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
     998             :   /* 1146 */ 'B', '2', '6', 0,
     999             :   /* 1150 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
    1000             :   /* 1166 */ 'H', '2', '6', 0,
    1001             :   /* 1170 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
    1002             :   /* 1186 */ 'S', '2', '6', 0,
    1003             :   /* 1190 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
    1004             :   /* 1198 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
    1005             :   /* 1206 */ 'B', '6', 0,
    1006             :   /* 1209 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
    1007             :   /* 1221 */ 'H', '6', 0,
    1008             :   /* 1224 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
    1009             :   /* 1236 */ 'S', '6', 0,
    1010             :   /* 1239 */ 'W', '5', '_', 'W', '6', 0,
    1011             :   /* 1245 */ 'X', '5', '_', 'X', '6', 0,
    1012             :   /* 1251 */ 'B', '1', '7', 0,
    1013             :   /* 1255 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
    1014             :   /* 1271 */ 'H', '1', '7', 0,
    1015             :   /* 1275 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
    1016             :   /* 1291 */ 'S', '1', '7', 0,
    1017             :   /* 1295 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
    1018             :   /* 1303 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
    1019             :   /* 1311 */ 'B', '2', '7', 0,
    1020             :   /* 1315 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
    1021             :   /* 1331 */ 'H', '2', '7', 0,
    1022             :   /* 1335 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
    1023             :   /* 1351 */ 'S', '2', '7', 0,
    1024             :   /* 1355 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
    1025             :   /* 1363 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
    1026             :   /* 1371 */ 'B', '7', 0,
    1027             :   /* 1374 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
    1028             :   /* 1386 */ 'H', '7', 0,
    1029             :   /* 1389 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
    1030             :   /* 1401 */ 'S', '7', 0,
    1031             :   /* 1404 */ 'W', '6', '_', 'W', '7', 0,
    1032             :   /* 1410 */ 'X', '6', '_', 'X', '7', 0,
    1033             :   /* 1416 */ 'B', '1', '8', 0,
    1034             :   /* 1420 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
    1035             :   /* 1436 */ 'H', '1', '8', 0,
    1036             :   /* 1440 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
    1037             :   /* 1456 */ 'S', '1', '8', 0,
    1038             :   /* 1460 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
    1039             :   /* 1468 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
    1040             :   /* 1476 */ 'B', '2', '8', 0,
    1041             :   /* 1480 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
    1042             :   /* 1496 */ 'H', '2', '8', 0,
    1043             :   /* 1500 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
    1044             :   /* 1516 */ 'S', '2', '8', 0,
    1045             :   /* 1520 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
    1046             :   /* 1528 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
    1047             :   /* 1536 */ 'B', '8', 0,
    1048             :   /* 1539 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
    1049             :   /* 1551 */ 'H', '8', 0,
    1050             :   /* 1554 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
    1051             :   /* 1566 */ 'S', '8', 0,
    1052             :   /* 1569 */ 'W', '7', '_', 'W', '8', 0,
    1053             :   /* 1575 */ 'X', '7', '_', 'X', '8', 0,
    1054             :   /* 1581 */ 'B', '1', '9', 0,
    1055             :   /* 1585 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
    1056             :   /* 1601 */ 'H', '1', '9', 0,
    1057             :   /* 1605 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
    1058             :   /* 1621 */ 'S', '1', '9', 0,
    1059             :   /* 1625 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
    1060             :   /* 1633 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
    1061             :   /* 1641 */ 'B', '2', '9', 0,
    1062             :   /* 1645 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
    1063             :   /* 1661 */ 'H', '2', '9', 0,
    1064             :   /* 1665 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
    1065             :   /* 1681 */ 'S', '2', '9', 0,
    1066             :   /* 1685 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
    1067             :   /* 1693 */ 'B', '9', 0,
    1068             :   /* 1696 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
    1069             :   /* 1708 */ 'H', '9', 0,
    1070             :   /* 1711 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
    1071             :   /* 1723 */ 'S', '9', 0,
    1072             :   /* 1726 */ 'W', '8', '_', 'W', '9', 0,
    1073             :   /* 1732 */ 'X', '8', '_', 'X', '9', 0,
    1074             :   /* 1738 */ 'X', '2', '8', '_', 'F', 'P', 0,
    1075             :   /* 1745 */ 'W', 'S', 'P', 0,
    1076             :   /* 1749 */ 'F', 'P', '_', 'L', 'R', 0,
    1077             :   /* 1755 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
    1078             :   /* 1763 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
    1079             :   /* 1770 */ 'N', 'Z', 'C', 'V', 0,
    1080             : };
    1081             : 
    1082             : extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
    1083             :   { 3, 0, 0, 0, 0, 0 },
    1084             :   { 1742, 351, 251, 5, 11857, 27 },
    1085             :   { 1752, 351, 89, 5, 11857, 27 },
    1086             :   { 1770, 2, 2, 4, 11857, 0 },
    1087             :   { 1746, 1, 2, 5, 3984, 27 },
    1088             :   { 1745, 2, 741, 4, 3984, 0 },
    1089             :   { 1759, 2, 41, 4, 4112, 0 },
    1090             :   { 1766, 741, 86, 5, 4112, 27 },
    1091             :   { 164, 2, 140, 4, 11825, 0 },
    1092             :   { 377, 2, 185, 4, 11825, 0 },
    1093             :   { 544, 2, 275, 4, 11825, 0 },
    1094             :   { 711, 2, 107, 4, 11825, 0 },
    1095             :   { 876, 2, 107, 4, 11825, 0 },
    1096             :   { 1041, 2, 107, 4, 11825, 0 },
    1097             :   { 1206, 2, 107, 4, 11825, 0 },
    1098             :   { 1371, 2, 107, 4, 11825, 0 },
    1099             :   { 1536, 2, 107, 4, 11825, 0 },
    1100             :   { 1693, 2, 107, 4, 11825, 0 },
    1101             :   { 0, 2, 107, 4, 11825, 0 },
    1102             :   { 217, 2, 107, 4, 11825, 0 },
    1103             :   { 426, 2, 107, 4, 11825, 0 },
    1104             :   { 591, 2, 107, 4, 11825, 0 },
    1105             :   { 756, 2, 107, 4, 11825, 0 },
    1106             :   { 921, 2, 107, 4, 11825, 0 },
    1107             :   { 1086, 2, 107, 4, 11825, 0 },
    1108             :   { 1251, 2, 107, 4, 11825, 0 },
    1109             :   { 1416, 2, 107, 4, 11825, 0 },
    1110             :   { 1581, 2, 107, 4, 11825, 0 },
    1111             :   { 52, 2, 107, 4, 11825, 0 },
    1112             :   { 273, 2, 107, 4, 11825, 0 },
    1113             :   { 484, 2, 107, 4, 11825, 0 },
    1114             :   { 651, 2, 107, 4, 11825, 0 },
    1115             :   { 816, 2, 107, 4, 11825, 0 },
    1116             :   { 981, 2, 107, 4, 11825, 0 },
    1117             :   { 1146, 2, 107, 4, 11825, 0 },
    1118             :   { 1311, 2, 107, 4, 11825, 0 },
    1119             :   { 1476, 2, 107, 4, 11825, 0 },
    1120             :   { 1641, 2, 107, 4, 11825, 0 },
    1121             :   { 112, 2, 107, 4, 11825, 0 },
    1122             :   { 333, 2, 107, 4, 11825, 0 },
    1123             :   { 179, 542, 143, 1, 11553, 3 },
    1124             :   { 391, 542, 188, 1, 11553, 3 },
    1125             :   { 557, 542, 278, 1, 11553, 3 },
    1126             :   { 723, 542, 110, 1, 11553, 3 },
    1127             :   { 888, 542, 110, 1, 11553, 3 },
    1128             :   { 1053, 542, 110, 1, 11553, 3 },
    1129             :   { 1218, 542, 110, 1, 11553, 3 },
    1130             :   { 1383, 542, 110, 1, 11553, 3 },
    1131             :   { 1548, 542, 110, 1, 11553, 3 },
    1132             :   { 1705, 542, 110, 1, 11553, 3 },
    1133             :   { 13, 542, 110, 1, 11553, 3 },
    1134             :   { 231, 542, 110, 1, 11553, 3 },
    1135             :   { 441, 542, 110, 1, 11553, 3 },
    1136             :   { 607, 542, 110, 1, 11553, 3 },
    1137             :   { 772, 542, 110, 1, 11553, 3 },
    1138             :   { 937, 542, 110, 1, 11553, 3 },
    1139             :   { 1102, 542, 110, 1, 11553, 3 },
    1140             :   { 1267, 542, 110, 1, 11553, 3 },
    1141             :   { 1432, 542, 110, 1, 11553, 3 },
    1142             :   { 1597, 542, 110, 1, 11553, 3 },
    1143             :   { 68, 542, 110, 1, 11553, 3 },
    1144             :   { 289, 542, 110, 1, 11553, 3 },
    1145             :   { 500, 542, 110, 1, 11553, 3 },
    1146             :   { 667, 542, 110, 1, 11553, 3 },
    1147             :   { 832, 542, 110, 1, 11553, 3 },
    1148             :   { 997, 542, 110, 1, 11553, 3 },
    1149             :   { 1162, 542, 110, 1, 11553, 3 },
    1150             :   { 1327, 542, 110, 1, 11553, 3 },
    1151             :   { 1492, 542, 110, 1, 11553, 3 },
    1152             :   { 1657, 542, 110, 1, 11553, 3 },
    1153             :   { 128, 542, 110, 1, 11553, 3 },
    1154             :   { 349, 542, 110, 1, 11553, 3 },
    1155             :   { 182, 544, 141, 3, 8561, 3 },
    1156             :   { 394, 544, 186, 3, 8561, 3 },
    1157             :   { 560, 544, 276, 3, 8561, 3 },
    1158             :   { 726, 544, 108, 3, 8561, 3 },
    1159             :   { 891, 544, 108, 3, 8561, 3 },
    1160             :   { 1056, 544, 108, 3, 8561, 3 },
    1161             :   { 1221, 544, 108, 3, 8561, 3 },
    1162             :   { 1386, 544, 108, 3, 8561, 3 },
    1163             :   { 1551, 544, 108, 3, 8561, 3 },
    1164             :   { 1708, 544, 108, 3, 8561, 3 },
    1165             :   { 17, 544, 108, 3, 8561, 3 },
    1166             :   { 235, 544, 108, 3, 8561, 3 },
    1167             :   { 445, 544, 108, 3, 8561, 3 },
    1168             :   { 611, 544, 108, 3, 8561, 3 },
    1169             :   { 776, 544, 108, 3, 8561, 3 },
    1170             :   { 941, 544, 108, 3, 8561, 3 },
    1171             :   { 1106, 544, 108, 3, 8561, 3 },
    1172             :   { 1271, 544, 108, 3, 8561, 3 },
    1173             :   { 1436, 544, 108, 3, 8561, 3 },
    1174             :   { 1601, 544, 108, 3, 8561, 3 },
    1175             :   { 72, 544, 108, 3, 8561, 3 },
    1176             :   { 293, 544, 108, 3, 8561, 3 },
    1177             :   { 504, 544, 108, 3, 8561, 3 },
    1178             :   { 671, 544, 108, 3, 8561, 3 },
    1179             :   { 836, 544, 108, 3, 8561, 3 },
    1180             :   { 1001, 544, 108, 3, 8561, 3 },
    1181             :   { 1166, 544, 108, 3, 8561, 3 },
    1182             :   { 1331, 544, 108, 3, 8561, 3 },
    1183             :   { 1496, 544, 108, 3, 8561, 3 },
    1184             :   { 1661, 544, 108, 3, 8561, 3 },
    1185             :   { 132, 544, 108, 3, 8561, 3 },
    1186             :   { 353, 544, 108, 3, 8561, 3 },
    1187             :   { 197, 555, 163, 0, 6657, 3 },
    1188             :   { 408, 555, 208, 0, 6657, 3 },
    1189             :   { 573, 555, 298, 0, 6657, 3 },
    1190             :   { 738, 555, 130, 0, 6657, 3 },
    1191             :   { 903, 555, 130, 0, 6657, 3 },
    1192             :   { 1068, 555, 130, 0, 6657, 3 },
    1193             :   { 1233, 555, 130, 0, 6657, 3 },
    1194             :   { 1398, 555, 130, 0, 6657, 3 },
    1195             :   { 1563, 555, 130, 0, 6657, 3 },
    1196             :   { 1720, 555, 130, 0, 6657, 3 },
    1197             :   { 30, 555, 130, 0, 6657, 3 },
    1198             :   { 249, 555, 130, 0, 6657, 3 },
    1199             :   { 460, 555, 130, 0, 6657, 3 },
    1200             :   { 627, 555, 130, 0, 6657, 3 },
    1201             :   { 792, 555, 130, 0, 6657, 3 },
    1202             :   { 957, 555, 130, 0, 6657, 3 },
    1203             :   { 1122, 555, 130, 0, 6657, 3 },
    1204             :   { 1287, 555, 130, 0, 6657, 3 },
    1205             :   { 1452, 555, 130, 0, 6657, 3 },
    1206             :   { 1617, 555, 130, 0, 6657, 3 },
    1207             :   { 88, 555, 130, 0, 6657, 3 },
    1208             :   { 309, 555, 130, 0, 6657, 3 },
    1209             :   { 520, 555, 130, 0, 6657, 3 },
    1210             :   { 687, 555, 130, 0, 6657, 3 },
    1211             :   { 852, 555, 130, 0, 6657, 3 },
    1212             :   { 1017, 555, 130, 0, 6657, 3 },
    1213             :   { 1182, 555, 130, 0, 6657, 3 },
    1214             :   { 1347, 555, 130, 0, 6657, 3 },
    1215             :   { 1512, 555, 130, 0, 6657, 3 },
    1216             :   { 1677, 555, 130, 0, 6657, 3 },
    1217             :   { 148, 555, 130, 0, 6657, 3 },
    1218             :   { 369, 555, 130, 0, 6657, 3 },
    1219             :   { 200, 543, 142, 2, 6625, 3 },
    1220             :   { 411, 543, 187, 2, 6625, 3 },
    1221             :   { 576, 543, 277, 2, 6625, 3 },
    1222             :   { 741, 543, 109, 2, 6625, 3 },
    1223             :   { 906, 543, 109, 2, 6625, 3 },
    1224             :   { 1071, 543, 109, 2, 6625, 3 },
    1225             :   { 1236, 543, 109, 2, 6625, 3 },
    1226             :   { 1401, 543, 109, 2, 6625, 3 },
    1227             :   { 1566, 543, 109, 2, 6625, 3 },
    1228             :   { 1723, 543, 109, 2, 6625, 3 },
    1229             :   { 34, 543, 109, 2, 6625, 3 },
    1230             :   { 253, 543, 109, 2, 6625, 3 },
    1231             :   { 464, 543, 109, 2, 6625, 3 },
    1232             :   { 631, 543, 109, 2, 6625, 3 },
    1233             :   { 796, 543, 109, 2, 6625, 3 },
    1234             :   { 961, 543, 109, 2, 6625, 3 },
    1235             :   { 1126, 543, 109, 2, 6625, 3 },
    1236             :   { 1291, 543, 109, 2, 6625, 3 },
    1237             :   { 1456, 543, 109, 2, 6625, 3 },
    1238             :   { 1621, 543, 109, 2, 6625, 3 },
    1239             :   { 92, 543, 109, 2, 6625, 3 },
    1240             :   { 313, 543, 109, 2, 6625, 3 },
    1241             :   { 524, 543, 109, 2, 6625, 3 },
    1242             :   { 691, 543, 109, 2, 6625, 3 },
    1243             :   { 856, 543, 109, 2, 6625, 3 },
    1244             :   { 1021, 543, 109, 2, 6625, 3 },
    1245             :   { 1186, 543, 109, 2, 6625, 3 },
    1246             :   { 1351, 543, 109, 2, 6625, 3 },
    1247             :   { 1516, 543, 109, 2, 6625, 3 },
    1248             :   { 1681, 543, 109, 2, 6625, 3 },
    1249             :   { 152, 543, 109, 2, 6625, 3 },
    1250             :   { 373, 543, 109, 2, 6625, 3 },
    1251             :   { 207, 2, 236, 4, 6625, 0 },
    1252             :   { 417, 2, 47, 4, 6625, 0 },
    1253             :   { 582, 2, 47, 4, 6625, 0 },
    1254             :   { 747, 2, 47, 4, 6625, 0 },
    1255             :   { 912, 2, 47, 4, 6625, 0 },
    1256             :   { 1077, 2, 47, 4, 6625, 0 },
    1257             :   { 1242, 2, 47, 4, 6625, 0 },
    1258             :   { 1407, 2, 47, 4, 6625, 0 },
    1259             :   { 1572, 2, 47, 4, 6625, 0 },
    1260             :   { 1729, 2, 47, 4, 6625, 0 },
    1261             :   { 41, 2, 47, 4, 6625, 0 },
    1262             :   { 261, 2, 47, 4, 6625, 0 },
    1263             :   { 472, 2, 47, 4, 6625, 0 },
    1264             :   { 639, 2, 47, 4, 6625, 0 },
    1265             :   { 804, 2, 47, 4, 6625, 0 },
    1266             :   { 969, 2, 47, 4, 6625, 0 },
    1267             :   { 1134, 2, 47, 4, 6625, 0 },
    1268             :   { 1299, 2, 47, 4, 6625, 0 },
    1269             :   { 1464, 2, 47, 4, 6625, 0 },
    1270             :   { 1629, 2, 47, 4, 6625, 0 },
    1271             :   { 100, 2, 47, 4, 6625, 0 },
    1272             :   { 321, 2, 47, 4, 6625, 0 },
    1273             :   { 532, 2, 47, 4, 6625, 0 },
    1274             :   { 699, 2, 47, 4, 6625, 0 },
    1275             :   { 864, 2, 47, 4, 6625, 0 },
    1276             :   { 1029, 2, 47, 4, 6625, 0 },
    1277             :   { 1194, 2, 47, 4, 6625, 0 },
    1278             :   { 1359, 2, 47, 4, 6625, 0 },
    1279             :   { 1524, 2, 261, 4, 6625, 0 },
    1280             :   { 1689, 2, 245, 4, 6513, 0 },
    1281             :   { 160, 2, 18, 4, 6513, 0 },
    1282             :   { 214, 737, 242, 5, 6593, 27 },
    1283             :   { 423, 737, 83, 5, 6593, 27 },
    1284             :   { 588, 737, 83, 5, 6593, 27 },
    1285             :   { 753, 737, 83, 5, 6593, 27 },
    1286             :   { 918, 737, 83, 5, 6593, 27 },
    1287             :   { 1083, 737, 83, 5, 6593, 27 },
    1288             :   { 1248, 737, 83, 5, 6593, 27 },
    1289             :   { 1413, 737, 83, 5, 6593, 27 },
    1290             :   { 1578, 737, 83, 5, 6593, 27 },
    1291             :   { 1735, 737, 83, 5, 6593, 27 },
    1292             :   { 48, 737, 83, 5, 6593, 27 },
    1293             :   { 269, 737, 83, 5, 6593, 27 },
    1294             :   { 480, 737, 83, 5, 6593, 27 },
    1295             :   { 647, 737, 83, 5, 6593, 27 },
    1296             :   { 812, 737, 83, 5, 6593, 27 },
    1297             :   { 977, 737, 83, 5, 6593, 27 },
    1298             :   { 1142, 737, 83, 5, 6593, 27 },
    1299             :   { 1307, 737, 83, 5, 6593, 27 },
    1300             :   { 1472, 737, 83, 5, 6593, 27 },
    1301             :   { 1637, 737, 83, 5, 6593, 27 },
    1302             :   { 108, 737, 83, 5, 6593, 27 },
    1303             :   { 329, 737, 83, 5, 6593, 27 },
    1304             :   { 540, 737, 83, 5, 6593, 27 },
    1305             :   { 707, 737, 83, 5, 6593, 27 },
    1306             :   { 872, 737, 83, 5, 6593, 27 },
    1307             :   { 1037, 737, 83, 5, 6593, 27 },
    1308             :   { 1202, 737, 83, 5, 6593, 27 },
    1309             :   { 1367, 737, 83, 5, 6593, 27 },
    1310             :   { 1532, 737, 267, 5, 6593, 27 },
    1311             :   { 388, 546, 218, 10, 1665, 37 },
    1312             :   { 554, 546, 312, 10, 1665, 37 },
    1313             :   { 720, 546, 173, 10, 1665, 37 },
    1314             :   { 885, 546, 173, 10, 1665, 37 },
    1315             :   { 1050, 546, 173, 10, 1665, 37 },
    1316             :   { 1215, 546, 173, 10, 1665, 37 },
    1317             :   { 1380, 546, 173, 10, 1665, 37 },
    1318             :   { 1545, 546, 173, 10, 1665, 37 },
    1319             :   { 1702, 546, 173, 10, 1665, 37 },
    1320             :   { 10, 546, 173, 10, 1665, 37 },
    1321             :   { 227, 546, 173, 10, 1665, 37 },
    1322             :   { 437, 546, 173, 10, 1665, 37 },
    1323             :   { 603, 546, 173, 10, 1665, 37 },
    1324             :   { 768, 546, 173, 10, 1665, 37 },
    1325             :   { 933, 546, 173, 10, 1665, 37 },
    1326             :   { 1098, 546, 173, 10, 1665, 37 },
    1327             :   { 1263, 546, 173, 10, 1665, 37 },
    1328             :   { 1428, 546, 173, 10, 1665, 37 },
    1329             :   { 1593, 546, 173, 10, 1665, 37 },
    1330             :   { 64, 546, 173, 10, 1665, 37 },
    1331             :   { 285, 546, 173, 10, 1665, 37 },
    1332             :   { 496, 546, 173, 10, 1665, 37 },
    1333             :   { 663, 546, 173, 10, 1665, 37 },
    1334             :   { 828, 546, 173, 10, 1665, 37 },
    1335             :   { 993, 546, 173, 10, 1665, 37 },
    1336             :   { 1158, 546, 173, 10, 1665, 37 },
    1337             :   { 1323, 546, 173, 10, 1665, 37 },
    1338             :   { 1488, 546, 173, 10, 1665, 37 },
    1339             :   { 1653, 546, 173, 10, 1665, 37 },
    1340             :   { 124, 546, 173, 10, 1665, 37 },
    1341             :   { 345, 546, 173, 10, 1665, 37 },
    1342             :   { 175, 537, 173, 10, 5184, 2 },
    1343             :   { 714, 678, 346, 34, 129, 44 },
    1344             :   { 879, 678, 346, 34, 129, 44 },
    1345             :   { 1044, 678, 346, 34, 129, 44 },
    1346             :   { 1209, 678, 346, 34, 129, 44 },
    1347             :   { 1374, 678, 346, 34, 129, 44 },
    1348             :   { 1539, 678, 346, 34, 129, 44 },
    1349             :   { 1696, 678, 346, 34, 129, 44 },
    1350             :   { 4, 678, 346, 34, 129, 44 },
    1351             :   { 221, 678, 346, 34, 129, 44 },
    1352             :   { 430, 678, 346, 34, 129, 44 },
    1353             :   { 595, 678, 346, 34, 129, 44 },
    1354             :   { 760, 678, 346, 34, 129, 44 },
    1355             :   { 925, 678, 346, 34, 129, 44 },
    1356             :   { 1090, 678, 346, 34, 129, 44 },
    1357             :   { 1255, 678, 346, 34, 129, 44 },
    1358             :   { 1420, 678, 346, 34, 129, 44 },
    1359             :   { 1585, 678, 346, 34, 129, 44 },
    1360             :   { 56, 678, 346, 34, 129, 44 },
    1361             :   { 277, 678, 346, 34, 129, 44 },
    1362             :   { 488, 678, 346, 34, 129, 44 },
    1363             :   { 655, 678, 346, 34, 129, 44 },
    1364             :   { 820, 678, 346, 34, 129, 44 },
    1365             :   { 985, 678, 346, 34, 129, 44 },
    1366             :   { 1150, 678, 346, 34, 129, 44 },
    1367             :   { 1315, 678, 346, 34, 129, 44 },
    1368             :   { 1480, 678, 346, 34, 129, 44 },
    1369             :   { 1645, 678, 346, 34, 129, 44 },
    1370             :   { 116, 678, 346, 34, 129, 44 },
    1371             :   { 337, 678, 346, 34, 129, 44 },
    1372             :   { 167, 700, 346, 34, 208, 49 },
    1373             :   { 380, 513, 346, 34, 512, 35 },
    1374             :   { 547, 656, 346, 34, 4320, 5 },
    1375             :   { 551, 53, 327, 19, 449, 50 },
    1376             :   { 717, 53, 230, 19, 449, 50 },
    1377             :   { 882, 53, 230, 19, 449, 50 },
    1378             :   { 1047, 53, 230, 19, 449, 50 },
    1379             :   { 1212, 53, 230, 19, 449, 50 },
    1380             :   { 1377, 53, 230, 19, 449, 50 },
    1381             :   { 1542, 53, 230, 19, 449, 50 },
    1382             :   { 1699, 53, 230, 19, 449, 50 },
    1383             :   { 7, 53, 230, 19, 449, 50 },
    1384             :   { 224, 53, 230, 19, 449, 50 },
    1385             :   { 433, 53, 230, 19, 449, 50 },
    1386             :   { 599, 53, 230, 19, 449, 50 },
    1387             :   { 764, 53, 230, 19, 449, 50 },
    1388             :   { 929, 53, 230, 19, 449, 50 },
    1389             :   { 1094, 53, 230, 19, 449, 50 },
    1390             :   { 1259, 53, 230, 19, 449, 50 },
    1391             :   { 1424, 53, 230, 19, 449, 50 },
    1392             :   { 1589, 53, 230, 19, 449, 50 },
    1393             :   { 60, 53, 230, 19, 449, 50 },
    1394             :   { 281, 53, 230, 19, 449, 50 },
    1395             :   { 492, 53, 230, 19, 449, 50 },
    1396             :   { 659, 53, 230, 19, 449, 50 },
    1397             :   { 824, 53, 230, 19, 449, 50 },
    1398             :   { 989, 53, 230, 19, 449, 50 },
    1399             :   { 1154, 53, 230, 19, 449, 50 },
    1400             :   { 1319, 53, 230, 19, 449, 50 },
    1401             :   { 1484, 53, 230, 19, 449, 50 },
    1402             :   { 1649, 53, 230, 19, 449, 50 },
    1403             :   { 120, 53, 230, 19, 449, 50 },
    1404             :   { 341, 53, 230, 19, 449, 50 },
    1405             :   { 171, 68, 230, 19, 592, 40 },
    1406             :   { 384, 724, 230, 19, 4928, 10 },
    1407             :   { 405, 353, 224, 56, 1569, 56 },
    1408             :   { 570, 353, 318, 56, 1569, 56 },
    1409             :   { 735, 353, 179, 56, 1569, 56 },
    1410             :   { 900, 353, 179, 56, 1569, 56 },
    1411             :   { 1065, 353, 179, 56, 1569, 56 },
    1412             :   { 1230, 353, 179, 56, 1569, 56 },
    1413             :   { 1395, 353, 179, 56, 1569, 56 },
    1414             :   { 1560, 353, 179, 56, 1569, 56 },
    1415             :   { 1717, 353, 179, 56, 1569, 56 },
    1416             :   { 27, 353, 179, 56, 1569, 56 },
    1417             :   { 245, 353, 179, 56, 1569, 56 },
    1418             :   { 456, 353, 179, 56, 1569, 56 },
    1419             :   { 623, 353, 179, 56, 1569, 56 },
    1420             :   { 788, 353, 179, 56, 1569, 56 },
    1421             :   { 953, 353, 179, 56, 1569, 56 },
    1422             :   { 1118, 353, 179, 56, 1569, 56 },
    1423             :   { 1283, 353, 179, 56, 1569, 56 },
    1424             :   { 1448, 353, 179, 56, 1569, 56 },
    1425             :   { 1613, 353, 179, 56, 1569, 56 },
    1426             :   { 84, 353, 179, 56, 1569, 56 },
    1427             :   { 305, 353, 179, 56, 1569, 56 },
    1428             :   { 516, 353, 179, 56, 1569, 56 },
    1429             :   { 683, 353, 179, 56, 1569, 56 },
    1430             :   { 848, 353, 179, 56, 1569, 56 },
    1431             :   { 1013, 353, 179, 56, 1569, 56 },
    1432             :   { 1178, 353, 179, 56, 1569, 56 },
    1433             :   { 1343, 353, 179, 56, 1569, 56 },
    1434             :   { 1508, 353, 179, 56, 1569, 56 },
    1435             :   { 1673, 353, 179, 56, 1569, 56 },
    1436             :   { 144, 353, 179, 56, 1569, 56 },
    1437             :   { 365, 353, 179, 56, 1569, 56 },
    1438             :   { 193, 365, 179, 56, 5184, 14 },
    1439             :   { 729, 592, 2, 89, 49, 63 },
    1440             :   { 894, 592, 2, 89, 49, 63 },
    1441             :   { 1059, 592, 2, 89, 49, 63 },
    1442             :   { 1224, 592, 2, 89, 49, 63 },
    1443             :   { 1389, 592, 2, 89, 49, 63 },
    1444             :   { 1554, 592, 2, 89, 49, 63 },
    1445             :   { 1711, 592, 2, 89, 49, 63 },
    1446             :   { 21, 592, 2, 89, 49, 63 },
    1447             :   { 239, 592, 2, 89, 49, 63 },
    1448             :   { 449, 592, 2, 89, 49, 63 },
    1449             :   { 615, 592, 2, 89, 49, 63 },
    1450             :   { 780, 592, 2, 89, 49, 63 },
    1451             :   { 945, 592, 2, 89, 49, 63 },
    1452             :   { 1110, 592, 2, 89, 49, 63 },
    1453             :   { 1275, 592, 2, 89, 49, 63 },
    1454             :   { 1440, 592, 2, 89, 49, 63 },
    1455             :   { 1605, 592, 2, 89, 49, 63 },
    1456             :   { 76, 592, 2, 89, 49, 63 },
    1457             :   { 297, 592, 2, 89, 49, 63 },
    1458             :   { 508, 592, 2, 89, 49, 63 },
    1459             :   { 675, 592, 2, 89, 49, 63 },
    1460             :   { 840, 592, 2, 89, 49, 63 },
    1461             :   { 1005, 592, 2, 89, 49, 63 },
    1462             :   { 1170, 592, 2, 89, 49, 63 },
    1463             :   { 1335, 592, 2, 89, 49, 63 },
    1464             :   { 1500, 592, 2, 89, 49, 63 },
    1465             :   { 1665, 592, 2, 89, 49, 63 },
    1466             :   { 136, 592, 2, 89, 49, 63 },
    1467             :   { 357, 592, 2, 89, 49, 63 },
    1468             :   { 185, 624, 2, 89, 208, 68 },
    1469             :   { 397, 481, 2, 89, 512, 54 },
    1470             :   { 563, 560, 2, 89, 4320, 17 },
    1471             :   { 567, 418, 330, 68, 385, 69 },
    1472             :   { 732, 418, 127, 68, 385, 69 },
    1473             :   { 897, 418, 127, 68, 385, 69 },
    1474             :   { 1062, 418, 127, 68, 385, 69 },
    1475             :   { 1227, 418, 127, 68, 385, 69 },
    1476             :   { 1392, 418, 127, 68, 385, 69 },
    1477             :   { 1557, 418, 127, 68, 385, 69 },
    1478             :   { 1714, 418, 127, 68, 385, 69 },
    1479             :   { 24, 418, 127, 68, 385, 69 },
    1480             :   { 242, 418, 127, 68, 385, 69 },
    1481             :   { 452, 418, 127, 68, 385, 69 },
    1482             :   { 619, 418, 127, 68, 385, 69 },
    1483             :   { 784, 418, 127, 68, 385, 69 },
    1484             :   { 949, 418, 127, 68, 385, 69 },
    1485             :   { 1114, 418, 127, 68, 385, 69 },
    1486             :   { 1279, 418, 127, 68, 385, 69 },
    1487             :   { 1444, 418, 127, 68, 385, 69 },
    1488             :   { 1609, 418, 127, 68, 385, 69 },
    1489             :   { 80, 418, 127, 68, 385, 69 },
    1490             :   { 301, 418, 127, 68, 385, 69 },
    1491             :   { 512, 418, 127, 68, 385, 69 },
    1492             :   { 679, 418, 127, 68, 385, 69 },
    1493             :   { 844, 418, 127, 68, 385, 69 },
    1494             :   { 1009, 418, 127, 68, 385, 69 },
    1495             :   { 1174, 418, 127, 68, 385, 69 },
    1496             :   { 1339, 418, 127, 68, 385, 69 },
    1497             :   { 1504, 418, 127, 68, 385, 69 },
    1498             :   { 1669, 418, 127, 68, 385, 69 },
    1499             :   { 140, 418, 127, 68, 385, 69 },
    1500             :   { 361, 418, 127, 68, 385, 69 },
    1501             :   { 189, 439, 127, 68, 592, 59 },
    1502             :   { 401, 460, 127, 68, 4928, 22 },
    1503             :   { 203, 348, 341, 7, 5360, 32 },
    1504             :   { 1755, 409, 333, 7, 3968, 32 },
    1505             :   { 414, 101, 341, 7, 1521, 32 },
    1506             :   { 579, 101, 341, 7, 1521, 32 },
    1507             :   { 744, 101, 341, 7, 1521, 32 },
    1508             :   { 909, 101, 341, 7, 1521, 32 },
    1509             :   { 1074, 101, 341, 7, 1521, 32 },
    1510             :   { 1239, 101, 341, 7, 1521, 32 },
    1511             :   { 1404, 101, 341, 7, 1521, 32 },
    1512             :   { 1569, 101, 341, 7, 1521, 32 },
    1513             :   { 1726, 101, 341, 7, 1521, 32 },
    1514             :   { 38, 101, 341, 7, 1521, 32 },
    1515             :   { 257, 101, 341, 7, 1521, 32 },
    1516             :   { 468, 101, 341, 7, 1521, 32 },
    1517             :   { 635, 101, 341, 7, 1521, 32 },
    1518             :   { 800, 101, 341, 7, 1521, 32 },
    1519             :   { 965, 101, 341, 7, 1521, 32 },
    1520             :   { 1130, 101, 341, 7, 1521, 32 },
    1521             :   { 1295, 101, 341, 7, 1521, 32 },
    1522             :   { 1460, 101, 341, 7, 1521, 32 },
    1523             :   { 1625, 101, 341, 7, 1521, 32 },
    1524             :   { 96, 101, 341, 7, 1521, 32 },
    1525             :   { 317, 101, 341, 7, 1521, 32 },
    1526             :   { 528, 101, 341, 7, 1521, 32 },
    1527             :   { 695, 101, 341, 7, 1521, 32 },
    1528             :   { 860, 101, 341, 7, 1521, 32 },
    1529             :   { 1025, 101, 341, 7, 1521, 32 },
    1530             :   { 1190, 101, 341, 7, 1521, 32 },
    1531             :   { 1355, 101, 341, 7, 1521, 32 },
    1532             :   { 1520, 101, 341, 7, 1521, 32 },
    1533             :   { 1685, 101, 259, 7, 5488, 29 },
    1534             :   { 156, 101, 1, 7, 0, 32 },
    1535             :   { 1749, 383, 2, 121, 0, 73 },
    1536             :   { 1763, 401, 2, 121, 4065, 73 },
    1537             :   { 210, 377, 2, 121, 5411, 73 },
    1538             :   { 1738, 389, 2, 121, 5488, 26 },
    1539             :   { 420, 395, 2, 121, 1473, 73 },
    1540             :   { 585, 395, 2, 121, 1473, 73 },
    1541             :   { 750, 395, 2, 121, 1473, 73 },
    1542             :   { 915, 395, 2, 121, 1473, 73 },
    1543             :   { 1080, 395, 2, 121, 1473, 73 },
    1544             :   { 1245, 395, 2, 121, 1473, 73 },
    1545             :   { 1410, 395, 2, 121, 1473, 73 },
    1546             :   { 1575, 395, 2, 121, 1473, 73 },
    1547             :   { 1732, 395, 2, 121, 1473, 73 },
    1548             :   { 45, 395, 2, 121, 1473, 73 },
    1549             :   { 265, 395, 2, 121, 1473, 73 },
    1550             :   { 476, 395, 2, 121, 1473, 73 },
    1551             :   { 643, 395, 2, 121, 1473, 73 },
    1552             :   { 808, 395, 2, 121, 1473, 73 },
    1553             :   { 973, 395, 2, 121, 1473, 73 },
    1554             :   { 1138, 395, 2, 121, 1473, 73 },
    1555             :   { 1303, 395, 2, 121, 1473, 73 },
    1556             :   { 1468, 395, 2, 121, 1473, 73 },
    1557             :   { 1633, 395, 2, 121, 1473, 73 },
    1558             :   { 104, 395, 2, 121, 1473, 73 },
    1559             :   { 325, 395, 2, 121, 1473, 73 },
    1560             :   { 536, 395, 2, 121, 1473, 73 },
    1561             :   { 703, 395, 2, 121, 1473, 73 },
    1562             :   { 868, 395, 2, 121, 1473, 73 },
    1563             :   { 1033, 395, 2, 121, 1473, 73 },
    1564             :   { 1198, 395, 2, 121, 1473, 73 },
    1565             :   { 1363, 395, 2, 121, 1473, 73 },
    1566             :   { 1528, 395, 2, 121, 1473, 73 },
    1567             : };
    1568             : 
    1569             : extern const MCPhysReg AArch64RegUnitRoots[][2] = {
    1570             :   { AArch64::W29 },
    1571             :   { AArch64::W30 },
    1572             :   { AArch64::NZCV },
    1573             :   { AArch64::WSP },
    1574             :   { AArch64::WZR },
    1575             :   { AArch64::B0 },
    1576             :   { AArch64::B1 },
    1577             :   { AArch64::B2 },
    1578             :   { AArch64::B3 },
    1579             :   { AArch64::B4 },
    1580             :   { AArch64::B5 },
    1581             :   { AArch64::B6 },
    1582             :   { AArch64::B7 },
    1583             :   { AArch64::B8 },
    1584             :   { AArch64::B9 },
    1585             :   { AArch64::B10 },
    1586             :   { AArch64::B11 },
    1587             :   { AArch64::B12 },
    1588             :   { AArch64::B13 },
    1589             :   { AArch64::B14 },
    1590             :   { AArch64::B15 },
    1591             :   { AArch64::B16 },
    1592             :   { AArch64::B17 },
    1593             :   { AArch64::B18 },
    1594             :   { AArch64::B19 },
    1595             :   { AArch64::B20 },
    1596             :   { AArch64::B21 },
    1597             :   { AArch64::B22 },
    1598             :   { AArch64::B23 },
    1599             :   { AArch64::B24 },
    1600             :   { AArch64::B25 },
    1601             :   { AArch64::B26 },
    1602             :   { AArch64::B27 },
    1603             :   { AArch64::B28 },
    1604             :   { AArch64::B29 },
    1605             :   { AArch64::B30 },
    1606             :   { AArch64::B31 },
    1607             :   { AArch64::W0 },
    1608             :   { AArch64::W1 },
    1609             :   { AArch64::W2 },
    1610             :   { AArch64::W3 },
    1611             :   { AArch64::W4 },
    1612             :   { AArch64::W5 },
    1613             :   { AArch64::W6 },
    1614             :   { AArch64::W7 },
    1615             :   { AArch64::W8 },
    1616             :   { AArch64::W9 },
    1617             :   { AArch64::W10 },
    1618             :   { AArch64::W11 },
    1619             :   { AArch64::W12 },
    1620             :   { AArch64::W13 },
    1621             :   { AArch64::W14 },
    1622             :   { AArch64::W15 },
    1623             :   { AArch64::W16 },
    1624             :   { AArch64::W17 },
    1625             :   { AArch64::W18 },
    1626             :   { AArch64::W19 },
    1627             :   { AArch64::W20 },
    1628             :   { AArch64::W21 },
    1629             :   { AArch64::W22 },
    1630             :   { AArch64::W23 },
    1631             :   { AArch64::W24 },
    1632             :   { AArch64::W25 },
    1633             :   { AArch64::W26 },
    1634             :   { AArch64::W27 },
    1635             :   { AArch64::W28 },
    1636             : };
    1637             : 
    1638             : namespace {     // Register classes...
    1639             :   // FPR8 Register Class...
    1640             :   const MCPhysReg FPR8[] = {
    1641             :     AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, 
    1642             :   };
    1643             : 
    1644             :   // FPR8 Bit set.
    1645             :   const uint8_t FPR8Bits[] = {
    1646             :     0x00, 0xff, 0xff, 0xff, 0xff, 
    1647             :   };
    1648             : 
    1649             :   // FPR16 Register Class...
    1650             :   const MCPhysReg FPR16[] = {
    1651             :     AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, 
    1652             :   };
    1653             : 
    1654             :   // FPR16 Bit set.
    1655             :   const uint8_t FPR16Bits[] = {
    1656             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
    1657             :   };
    1658             : 
    1659             :   // GPR32all Register Class...
    1660             :   const MCPhysReg GPR32all[] = {
    1661             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, 
    1662             :   };
    1663             : 
    1664             :   // GPR32all Bit set.
    1665             :   const uint8_t GPR32allBits[] = {
    1666             :     0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
    1667             :   };
    1668             : 
    1669             :   // FPR32 Register Class...
    1670             :   const MCPhysReg FPR32[] = {
    1671             :     AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, 
    1672             :   };
    1673             : 
    1674             :   // FPR32 Bit set.
    1675             :   const uint8_t FPR32Bits[] = {
    1676             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
    1677             :   };
    1678             : 
    1679             :   // GPR32 Register Class...
    1680             :   const MCPhysReg GPR32[] = {
    1681             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, 
    1682             :   };
    1683             : 
    1684             :   // GPR32 Bit set.
    1685             :   const uint8_t GPR32Bits[] = {
    1686             :     0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
    1687             :   };
    1688             : 
    1689             :   // GPR32sp Register Class...
    1690             :   const MCPhysReg GPR32sp[] = {
    1691             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, 
    1692             :   };
    1693             : 
    1694             :   // GPR32sp Bit set.
    1695             :   const uint8_t GPR32spBits[] = {
    1696             :     0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
    1697             :   };
    1698             : 
    1699             :   // GPR32common Register Class...
    1700             :   const MCPhysReg GPR32common[] = {
    1701             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, 
    1702             :   };
    1703             : 
    1704             :   // GPR32common Bit set.
    1705             :   const uint8_t GPR32commonBits[] = {
    1706             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
    1707             :   };
    1708             : 
    1709             :   // CCR Register Class...
    1710             :   const MCPhysReg CCR[] = {
    1711             :     AArch64::NZCV, 
    1712             :   };
    1713             : 
    1714             :   // CCR Bit set.
    1715             :   const uint8_t CCRBits[] = {
    1716             :     0x08, 
    1717             :   };
    1718             : 
    1719             :   // GPR32sponly Register Class...
    1720             :   const MCPhysReg GPR32sponly[] = {
    1721             :     AArch64::WSP, 
    1722             :   };
    1723             : 
    1724             :   // GPR32sponly Bit set.
    1725             :   const uint8_t GPR32sponlyBits[] = {
    1726             :     0x20, 
    1727             :   };
    1728             : 
    1729             :   // WSeqPairsClass Register Class...
    1730             :   const MCPhysReg WSeqPairsClass[] = {
    1731             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, AArch64::WZR_W0, 
    1732             :   };
    1733             : 
    1734             :   // WSeqPairsClass Bit set.
    1735             :   const uint8_t WSeqPairsClassBits[] = {
    1736             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    1737             :   };
    1738             : 
    1739             :   // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
    1740             :   const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
    1741             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, 
    1742             :   };
    1743             : 
    1744             :   // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
    1745             :   const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
    1746             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, 
    1747             :   };
    1748             : 
    1749             :   // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
    1750             :   const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
    1751             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::WZR_W0, 
    1752             :   };
    1753             : 
    1754             :   // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
    1755             :   const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    1756             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff, 0xff, 0xff, 0x0f, 
    1757             :   };
    1758             : 
    1759             :   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
    1760             :   const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
    1761             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, 
    1762             :   };
    1763             : 
    1764             :   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
    1765             :   const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    1766             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, 
    1767             :   };
    1768             : 
    1769             :   // GPR64all Register Class...
    1770             :   const MCPhysReg GPR64all[] = {
    1771             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, 
    1772             :   };
    1773             : 
    1774             :   // GPR64all Bit set.
    1775             :   const uint8_t GPR64allBits[] = {
    1776             :     0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
    1777             :   };
    1778             : 
    1779             :   // FPR64 Register Class...
    1780             :   const MCPhysReg FPR64[] = {
    1781             :     AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 
    1782             :   };
    1783             : 
    1784             :   // FPR64 Bit set.
    1785             :   const uint8_t FPR64Bits[] = {
    1786             :     0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
    1787             :   };
    1788             : 
    1789             :   // GPR64 Register Class...
    1790             :   const MCPhysReg GPR64[] = {
    1791             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, 
    1792             :   };
    1793             : 
    1794             :   // GPR64 Bit set.
    1795             :   const uint8_t GPR64Bits[] = {
    1796             :     0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
    1797             :   };
    1798             : 
    1799             :   // GPR64sp Register Class...
    1800             :   const MCPhysReg GPR64sp[] = {
    1801             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, 
    1802             :   };
    1803             : 
    1804             :   // GPR64sp Bit set.
    1805             :   const uint8_t GPR64spBits[] = {
    1806             :     0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
    1807             :   };
    1808             : 
    1809             :   // GPR64common Register Class...
    1810             :   const MCPhysReg GPR64common[] = {
    1811             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, 
    1812             :   };
    1813             : 
    1814             :   // GPR64common Bit set.
    1815             :   const uint8_t GPR64commonBits[] = {
    1816             :     0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
    1817             :   };
    1818             : 
    1819             :   // tcGPR64 Register Class...
    1820             :   const MCPhysReg tcGPR64[] = {
    1821             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, 
    1822             :   };
    1823             : 
    1824             :   // tcGPR64 Bit set.
    1825             :   const uint8_t tcGPR64Bits[] = {
    1826             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03, 
    1827             :   };
    1828             : 
    1829             :   // GPR64sponly Register Class...
    1830             :   const MCPhysReg GPR64sponly[] = {
    1831             :     AArch64::SP, 
    1832             :   };
    1833             : 
    1834             :   // GPR64sponly Bit set.
    1835             :   const uint8_t GPR64sponlyBits[] = {
    1836             :     0x10, 
    1837             :   };
    1838             : 
    1839             :   // DD Register Class...
    1840             :   const MCPhysReg DD[] = {
    1841             :     AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, 
    1842             :   };
    1843             : 
    1844             :   // DD Bit set.
    1845             :   const uint8_t DDBits[] = {
    1846             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    1847             :   };
    1848             : 
    1849             :   // XSeqPairsClass Register Class...
    1850             :   const MCPhysReg XSeqPairsClass[] = {
    1851             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, AArch64::XZR_X0, 
    1852             :   };
    1853             : 
    1854             :   // XSeqPairsClass Bit set.
    1855             :   const uint8_t XSeqPairsClassBits[] = {
    1856             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    1857             :   };
    1858             : 
    1859             :   // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
    1860             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
    1861             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, 
    1862             :   };
    1863             : 
    1864             :   // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
    1865             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
    1866             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0xff, 0xff, 0xff, 0x0f, 
    1867             :   };
    1868             : 
    1869             :   // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
    1870             :   const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
    1871             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::XZR_X0, 
    1872             :   };
    1873             : 
    1874             :   // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
    1875             :   const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    1876             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff, 0xff, 0xff, 0x0f, 
    1877             :   };
    1878             : 
    1879             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
    1880             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
    1881             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, 
    1882             :   };
    1883             : 
    1884             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
    1885             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    1886             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0xff, 0xff, 0xff, 0x0f, 
    1887             :   };
    1888             : 
    1889             :   // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
    1890             :   const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
    1891             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, 
    1892             :   };
    1893             : 
    1894             :   // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
    1895             :   const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
    1896             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, 
    1897             :   };
    1898             : 
    1899             :   // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
    1900             :   const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    1901             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::XZR_X0, 
    1902             :   };
    1903             : 
    1904             :   // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
    1905             :   const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    1906             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xff, 0xff, 0x03, 
    1907             :   };
    1908             : 
    1909             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
    1910             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    1911             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, 
    1912             :   };
    1913             : 
    1914             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
    1915             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    1916             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x03, 
    1917             :   };
    1918             : 
    1919             :   // FPR128 Register Class...
    1920             :   const MCPhysReg FPR128[] = {
    1921             :     AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 
    1922             :   };
    1923             : 
    1924             :   // FPR128 Bit set.
    1925             :   const uint8_t FPR128Bits[] = {
    1926             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
    1927             :   };
    1928             : 
    1929             :   // FPR128_lo Register Class...
    1930             :   const MCPhysReg FPR128_lo[] = {
    1931             :     AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, 
    1932             :   };
    1933             : 
    1934             :   // FPR128_lo Bit set.
    1935             :   const uint8_t FPR128_loBits[] = {
    1936             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
    1937             :   };
    1938             : 
    1939             :   // DDD Register Class...
    1940             :   const MCPhysReg DDD[] = {
    1941             :     AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, 
    1942             :   };
    1943             : 
    1944             :   // DDD Bit set.
    1945             :   const uint8_t DDDBits[] = {
    1946             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    1947             :   };
    1948             : 
    1949             :   // DDDD Register Class...
    1950             :   const MCPhysReg DDDD[] = {
    1951             :     AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, 
    1952             :   };
    1953             : 
    1954             :   // DDDD Bit set.
    1955             :   const uint8_t DDDDBits[] = {
    1956             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    1957             :   };
    1958             : 
    1959             :   // QQ Register Class...
    1960             :   const MCPhysReg QQ[] = {
    1961             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, 
    1962             :   };
    1963             : 
    1964             :   // QQ Bit set.
    1965             :   const uint8_t QQBits[] = {
    1966             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    1967             :   };
    1968             : 
    1969             :   // QQ_with_qsub0_in_FPR128_lo Register Class...
    1970             :   const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
    1971             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 
    1972             :   };
    1973             : 
    1974             :   // QQ_with_qsub0_in_FPR128_lo Bit set.
    1975             :   const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
    1976             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
    1977             :   };
    1978             : 
    1979             :   // QQ_with_qsub1_in_FPR128_lo Register Class...
    1980             :   const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
    1981             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, 
    1982             :   };
    1983             : 
    1984             :   // QQ_with_qsub1_in_FPR128_lo Bit set.
    1985             :   const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
    1986             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
    1987             :   };
    1988             : 
    1989             :   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
    1990             :   const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
    1991             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, 
    1992             :   };
    1993             : 
    1994             :   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
    1995             :   const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
    1996             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
    1997             :   };
    1998             : 
    1999             :   // QQQ Register Class...
    2000             :   const MCPhysReg QQQ[] = {
    2001             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
    2002             :   };
    2003             : 
    2004             :   // QQQ Bit set.
    2005             :   const uint8_t QQQBits[] = {
    2006             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2007             :   };
    2008             : 
    2009             :   // QQQ_with_qsub0_in_FPR128_lo Register Class...
    2010             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
    2011             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, 
    2012             :   };
    2013             : 
    2014             :   // QQQ_with_qsub0_in_FPR128_lo Bit set.
    2015             :   const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
    2016             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
    2017             :   };
    2018             : 
    2019             :   // QQQ_with_qsub1_in_FPR128_lo Register Class...
    2020             :   const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
    2021             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, 
    2022             :   };
    2023             : 
    2024             :   // QQQ_with_qsub1_in_FPR128_lo Bit set.
    2025             :   const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
    2026             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
    2027             :   };
    2028             : 
    2029             :   // QQQ_with_qsub2_in_FPR128_lo Register Class...
    2030             :   const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
    2031             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
    2032             :   };
    2033             : 
    2034             :   // QQQ_with_qsub2_in_FPR128_lo Bit set.
    2035             :   const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
    2036             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, 
    2037             :   };
    2038             : 
    2039             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
    2040             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
    2041             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 
    2042             :   };
    2043             : 
    2044             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
    2045             :   const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
    2046             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
    2047             :   };
    2048             : 
    2049             :   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
    2050             :   const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    2051             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, 
    2052             :   };
    2053             : 
    2054             :   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
    2055             :   const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    2056             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, 
    2057             :   };
    2058             : 
    2059             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
    2060             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    2061             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, 
    2062             :   };
    2063             : 
    2064             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
    2065             :   const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    2066             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 
    2067             :   };
    2068             : 
    2069             :   // QQQQ Register Class...
    2070             :   const MCPhysReg QQQQ[] = {
    2071             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2072             :   };
    2073             : 
    2074             :   // QQQQ Bit set.
    2075             :   const uint8_t QQQQBits[] = {
    2076             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2077             :   };
    2078             : 
    2079             :   // QQQQ_with_qsub0_in_FPR128_lo Register Class...
    2080             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
    2081             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, 
    2082             :   };
    2083             : 
    2084             :   // QQQQ_with_qsub0_in_FPR128_lo Bit set.
    2085             :   const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
    2086             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
    2087             :   };
    2088             : 
    2089             :   // QQQQ_with_qsub1_in_FPR128_lo Register Class...
    2090             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
    2091             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, 
    2092             :   };
    2093             : 
    2094             :   // QQQQ_with_qsub1_in_FPR128_lo Bit set.
    2095             :   const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
    2096             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
    2097             :   };
    2098             : 
    2099             :   // QQQQ_with_qsub2_in_FPR128_lo Register Class...
    2100             :   const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
    2101             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2102             :   };
    2103             : 
    2104             :   // QQQQ_with_qsub2_in_FPR128_lo Bit set.
    2105             :   const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
    2106             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, 
    2107             :   };
    2108             : 
    2109             :   // QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2110             :   const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
    2111             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2112             :   };
    2113             : 
    2114             :   // QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2115             :   const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2116             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e, 
    2117             :   };
    2118             : 
    2119             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
    2120             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
    2121             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 
    2122             :   };
    2123             : 
    2124             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
    2125             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
    2126             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
    2127             :   };
    2128             : 
    2129             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
    2130             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    2131             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, 
    2132             :   };
    2133             : 
    2134             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
    2135             :   const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    2136             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, 
    2137             :   };
    2138             : 
    2139             :   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2140             :   const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    2141             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2142             :   };
    2143             : 
    2144             :   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2145             :   const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2146             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c, 
    2147             :   };
    2148             : 
    2149             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
    2150             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    2151             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, 
    2152             :   };
    2153             : 
    2154             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
    2155             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    2156             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 
    2157             :   };
    2158             : 
    2159             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2160             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    2161             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, 
    2162             :   };
    2163             : 
    2164             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2165             :   const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2166             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08, 
    2167             :   };
    2168             : 
    2169             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2170             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    2171             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, 
    2172             :   };
    2173             : 
    2174             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2175             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2176             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
    2177             :   };
    2178             : 
    2179             : } // end anonymous namespace
    2180             : 
    2181             : extern const char AArch64RegClassStrings[] = {
    2182             :   /* 0 */ 'F', 'P', 'R', '3', '2', 0,
    2183             :   /* 6 */ 'G', 'P', 'R', '3', '2', 0,
    2184             :   /* 12 */ 'F', 'P', 'R', '6', '4', 0,
    2185             :   /* 18 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
    2186             :   /* 56 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
    2187             :   /* 140 */ 'F', 'P', 'R', '1', '6', 0,
    2188             :   /* 146 */ 'F', 'P', 'R', '1', '2', '8', 0,
    2189             :   /* 153 */ 'F', 'P', 'R', '8', 0,
    2190             :   /* 158 */ 'D', 'D', 'D', 'D', 0,
    2191             :   /* 163 */ 'Q', 'Q', 'Q', 'Q', 0,
    2192             :   /* 168 */ 'C', 'C', 'R', 0,
    2193             :   /* 172 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
    2194             :   /* 181 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
    2195             :   /* 190 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    2196             :   /* 232 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    2197             :   /* 274 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    2198             :   /* 362 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    2199             :   /* 450 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2200             :   /* 479 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2201             :   /* 541 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2202             :   /* 601 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2203             :   /* 659 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2204             :   /* 721 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2205             :   /* 783 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2206             :   /* 843 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2207             :   /* 903 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2208             :   /* 965 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2209             :   /* 1027 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2210             :   /* 1089 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
    2211             :   /* 1097 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
    2212             :   /* 1105 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
    2213             :   /* 1120 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
    2214             :   /* 1135 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
    2215             :   /* 1147 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
    2216             : };
    2217             : 
    2218             : extern const MCRegisterClass AArch64MCRegisterClasses[] = {
    2219             :   { FPR8, FPR8Bits, 153, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, 1, true },
    2220             :   { FPR16, FPR16Bits, 140, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 2, 1, true },
    2221             :   { GPR32all, GPR32allBits, 172, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 4, 1, true },
    2222             :   { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 4, 1, true },
    2223             :   { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 4, 1, true },
    2224             :   { GPR32sp, GPR32spBits, 1089, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 4, 1, true },
    2225             :   { GPR32common, GPR32commonBits, 220, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 4, 1, true },
    2226             :   { CCR, CCRBits, 168, 1, sizeof(CCRBits), AArch64::CCRRegClassID, 4, -1, false },
    2227             :   { GPR32sponly, GPR32sponlyBits, 1135, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 4, 1, true },
    2228             :   { WSeqPairsClass, WSeqPairsClassBits, 1105, 32, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 8, 1, true },
    2229             :   { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, 232, 31, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClassID, 8, 1, true },
    2230             :   { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 320, 31, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 1, true },
    2231             :   { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, 274, 30, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 1, true },
    2232             :   { GPR64all, GPR64allBits, 181, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 8, 1, true },
    2233             :   { FPR64, FPR64Bits, 12, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 8, 1, true },
    2234             :   { GPR64, GPR64Bits, 50, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 8, 1, true },
    2235             :   { GPR64sp, GPR64spBits, 1097, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 8, 1, true },
    2236             :   { GPR64common, GPR64commonBits, 438, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 8, 1, true },
    2237             :   { tcGPR64, tcGPR64Bits, 48, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 8, 1, true },
    2238             :   { GPR64sponly, GPR64sponlyBits, 1147, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 8, 1, true },
    2239             :   { DD, DDBits, 160, 32, sizeof(DDBits), AArch64::DDRegClassID, 16, 1, true },
    2240             :   { XSeqPairsClass, XSeqPairsClassBits, 1120, 32, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 16, 1, true },
    2241             :   { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, 190, 31, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID, 16, 1, true },
    2242             :   { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 408, 31, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 1, true },
    2243             :   { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, 362, 30, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 1, true },
    2244             :   { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 18, 19, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 16, 1, true },
    2245             :   { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 102, 19, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 1, true },
    2246             :   { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, 56, 18, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 1, true },
    2247             :   { FPR128, FPR128Bits, 146, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 16, 1, true },
    2248             :   { FPR128_lo, FPR128_loBits, 469, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 16, 1, true },
    2249             :   { DDD, DDDBits, 159, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 24, 1, true },
    2250             :   { DDDD, DDDDBits, 158, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 32, 1, true },
    2251             :   { QQ, QQBits, 165, 32, sizeof(QQBits), AArch64::QQRegClassID, 32, 1, true },
    2252             :   { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 452, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 32, 1, true },
    2253             :   { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 514, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 32, 1, true },
    2254             :   { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 601, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 1, true },
    2255             :   { QQQ, QQQBits, 164, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 48, 1, true },
    2256             :   { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 451, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 1, true },
    2257             :   { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 513, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 1, true },
    2258             :   { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 693, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    2259             :   { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 541, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 1, true },
    2260             :   { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 843, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    2261             :   { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 783, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    2262             :   { QQQQ, QQQQBits, 163, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 64, 1, true },
    2263             :   { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 450, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 1, true },
    2264             :   { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 512, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 1, true },
    2265             :   { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 692, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    2266             :   { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 936, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    2267             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 479, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 1, true },
    2268             :   { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 721, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    2269             :   { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 1027, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    2270             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 659, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    2271             :   { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 965, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    2272             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 903, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    2273             : };
    2274             : 
    2275             : // AArch64 Dwarf<->LLVM register mappings.
    2276             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
    2277             :   { 0U, AArch64::W0 },
    2278             :   { 1U, AArch64::W1 },
    2279             :   { 2U, AArch64::W2 },
    2280             :   { 3U, AArch64::W3 },
    2281             :   { 4U, AArch64::W4 },
    2282             :   { 5U, AArch64::W5 },
    2283             :   { 6U, AArch64::W6 },
    2284             :   { 7U, AArch64::W7 },
    2285             :   { 8U, AArch64::W8 },
    2286             :   { 9U, AArch64::W9 },
    2287             :   { 10U, AArch64::W10 },
    2288             :   { 11U, AArch64::W11 },
    2289             :   { 12U, AArch64::W12 },
    2290             :   { 13U, AArch64::W13 },
    2291             :   { 14U, AArch64::W14 },
    2292             :   { 15U, AArch64::W15 },
    2293             :   { 16U, AArch64::W16 },
    2294             :   { 17U, AArch64::W17 },
    2295             :   { 18U, AArch64::W18 },
    2296             :   { 19U, AArch64::W19 },
    2297             :   { 20U, AArch64::W20 },
    2298             :   { 21U, AArch64::W21 },
    2299             :   { 22U, AArch64::W22 },
    2300             :   { 23U, AArch64::W23 },
    2301             :   { 24U, AArch64::W24 },
    2302             :   { 25U, AArch64::W25 },
    2303             :   { 26U, AArch64::W26 },
    2304             :   { 27U, AArch64::W27 },
    2305             :   { 28U, AArch64::W28 },
    2306             :   { 29U, AArch64::W29 },
    2307             :   { 30U, AArch64::W30 },
    2308             :   { 31U, AArch64::WSP },
    2309             :   { 64U, AArch64::B0 },
    2310             :   { 65U, AArch64::B1 },
    2311             :   { 66U, AArch64::B2 },
    2312             :   { 67U, AArch64::B3 },
    2313             :   { 68U, AArch64::B4 },
    2314             :   { 69U, AArch64::B5 },
    2315             :   { 70U, AArch64::B6 },
    2316             :   { 71U, AArch64::B7 },
    2317             :   { 72U, AArch64::B8 },
    2318             :   { 73U, AArch64::B9 },
    2319             :   { 74U, AArch64::B10 },
    2320             :   { 75U, AArch64::B11 },
    2321             :   { 76U, AArch64::B12 },
    2322             :   { 77U, AArch64::B13 },
    2323             :   { 78U, AArch64::B14 },
    2324             :   { 79U, AArch64::B15 },
    2325             :   { 80U, AArch64::B16 },
    2326             :   { 81U, AArch64::B17 },
    2327             :   { 82U, AArch64::B18 },
    2328             :   { 83U, AArch64::B19 },
    2329             :   { 84U, AArch64::B20 },
    2330             :   { 85U, AArch64::B21 },
    2331             :   { 86U, AArch64::B22 },
    2332             :   { 87U, AArch64::B23 },
    2333             :   { 88U, AArch64::B24 },
    2334             :   { 89U, AArch64::B25 },
    2335             :   { 90U, AArch64::B26 },
    2336             :   { 91U, AArch64::B27 },
    2337             :   { 92U, AArch64::B28 },
    2338             :   { 93U, AArch64::B29 },
    2339             :   { 94U, AArch64::B30 },
    2340             :   { 95U, AArch64::B31 },
    2341             : };
    2342             : extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
    2343             : 
    2344             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
    2345             :   { 0U, AArch64::W0 },
    2346             :   { 1U, AArch64::W1 },
    2347             :   { 2U, AArch64::W2 },
    2348             :   { 3U, AArch64::W3 },
    2349             :   { 4U, AArch64::W4 },
    2350             :   { 5U, AArch64::W5 },
    2351             :   { 6U, AArch64::W6 },
    2352             :   { 7U, AArch64::W7 },
    2353             :   { 8U, AArch64::W8 },
    2354             :   { 9U, AArch64::W9 },
    2355             :   { 10U, AArch64::W10 },
    2356             :   { 11U, AArch64::W11 },
    2357             :   { 12U, AArch64::W12 },
    2358             :   { 13U, AArch64::W13 },
    2359             :   { 14U, AArch64::W14 },
    2360             :   { 15U, AArch64::W15 },
    2361             :   { 16U, AArch64::W16 },
    2362             :   { 17U, AArch64::W17 },
    2363             :   { 18U, AArch64::W18 },
    2364             :   { 19U, AArch64::W19 },
    2365             :   { 20U, AArch64::W20 },
    2366             :   { 21U, AArch64::W21 },
    2367             :   { 22U, AArch64::W22 },
    2368             :   { 23U, AArch64::W23 },
    2369             :   { 24U, AArch64::W24 },
    2370             :   { 25U, AArch64::W25 },
    2371             :   { 26U, AArch64::W26 },
    2372             :   { 27U, AArch64::W27 },
    2373             :   { 28U, AArch64::W28 },
    2374             :   { 29U, AArch64::W29 },
    2375             :   { 30U, AArch64::W30 },
    2376             :   { 31U, AArch64::WSP },
    2377             :   { 64U, AArch64::B0 },
    2378             :   { 65U, AArch64::B1 },
    2379             :   { 66U, AArch64::B2 },
    2380             :   { 67U, AArch64::B3 },
    2381             :   { 68U, AArch64::B4 },
    2382             :   { 69U, AArch64::B5 },
    2383             :   { 70U, AArch64::B6 },
    2384             :   { 71U, AArch64::B7 },
    2385             :   { 72U, AArch64::B8 },
    2386             :   { 73U, AArch64::B9 },
    2387             :   { 74U, AArch64::B10 },
    2388             :   { 75U, AArch64::B11 },
    2389             :   { 76U, AArch64::B12 },
    2390             :   { 77U, AArch64::B13 },
    2391             :   { 78U, AArch64::B14 },
    2392             :   { 79U, AArch64::B15 },
    2393             :   { 80U, AArch64::B16 },
    2394             :   { 81U, AArch64::B17 },
    2395             :   { 82U, AArch64::B18 },
    2396             :   { 83U, AArch64::B19 },
    2397             :   { 84U, AArch64::B20 },
    2398             :   { 85U, AArch64::B21 },
    2399             :   { 86U, AArch64::B22 },
    2400             :   { 87U, AArch64::B23 },
    2401             :   { 88U, AArch64::B24 },
    2402             :   { 89U, AArch64::B25 },
    2403             :   { 90U, AArch64::B26 },
    2404             :   { 91U, AArch64::B27 },
    2405             :   { 92U, AArch64::B28 },
    2406             :   { 93U, AArch64::B29 },
    2407             :   { 94U, AArch64::B30 },
    2408             :   { 95U, AArch64::B31 },
    2409             : };
    2410             : extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
    2411             : 
    2412             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
    2413             :   { AArch64::FP, 29U },
    2414             :   { AArch64::LR, 30U },
    2415             :   { AArch64::SP, 31U },
    2416             :   { AArch64::WSP, 31U },
    2417             :   { AArch64::WZR, 31U },
    2418             :   { AArch64::XZR, 31U },
    2419             :   { AArch64::B0, 64U },
    2420             :   { AArch64::B1, 65U },
    2421             :   { AArch64::B2, 66U },
    2422             :   { AArch64::B3, 67U },
    2423             :   { AArch64::B4, 68U },
    2424             :   { AArch64::B5, 69U },
    2425             :   { AArch64::B6, 70U },
    2426             :   { AArch64::B7, 71U },
    2427             :   { AArch64::B8, 72U },
    2428             :   { AArch64::B9, 73U },
    2429             :   { AArch64::B10, 74U },
    2430             :   { AArch64::B11, 75U },
    2431             :   { AArch64::B12, 76U },
    2432             :   { AArch64::B13, 77U },
    2433             :   { AArch64::B14, 78U },
    2434             :   { AArch64::B15, 79U },
    2435             :   { AArch64::B16, 80U },
    2436             :   { AArch64::B17, 81U },
    2437             :   { AArch64::B18, 82U },
    2438             :   { AArch64::B19, 83U },
    2439             :   { AArch64::B20, 84U },
    2440             :   { AArch64::B21, 85U },
    2441             :   { AArch64::B22, 86U },
    2442             :   { AArch64::B23, 87U },
    2443             :   { AArch64::B24, 88U },
    2444             :   { AArch64::B25, 89U },
    2445             :   { AArch64::B26, 90U },
    2446             :   { AArch64::B27, 91U },
    2447             :   { AArch64::B28, 92U },
    2448             :   { AArch64::B29, 93U },
    2449             :   { AArch64::B30, 94U },
    2450             :   { AArch64::B31, 95U },
    2451             :   { AArch64::D0, 64U },
    2452             :   { AArch64::D1, 65U },
    2453             :   { AArch64::D2, 66U },
    2454             :   { AArch64::D3, 67U },
    2455             :   { AArch64::D4, 68U },
    2456             :   { AArch64::D5, 69U },
    2457             :   { AArch64::D6, 70U },
    2458             :   { AArch64::D7, 71U },
    2459             :   { AArch64::D8, 72U },
    2460             :   { AArch64::D9, 73U },
    2461             :   { AArch64::D10, 74U },
    2462             :   { AArch64::D11, 75U },
    2463             :   { AArch64::D12, 76U },
    2464             :   { AArch64::D13, 77U },
    2465             :   { AArch64::D14, 78U },
    2466             :   { AArch64::D15, 79U },
    2467             :   { AArch64::D16, 80U },
    2468             :   { AArch64::D17, 81U },
    2469             :   { AArch64::D18, 82U },
    2470             :   { AArch64::D19, 83U },
    2471             :   { AArch64::D20, 84U },
    2472             :   { AArch64::D21, 85U },
    2473             :   { AArch64::D22, 86U },
    2474             :   { AArch64::D23, 87U },
    2475             :   { AArch64::D24, 88U },
    2476             :   { AArch64::D25, 89U },
    2477             :   { AArch64::D26, 90U },
    2478             :   { AArch64::D27, 91U },
    2479             :   { AArch64::D28, 92U },
    2480             :   { AArch64::D29, 93U },
    2481             :   { AArch64::D30, 94U },
    2482             :   { AArch64::D31, 95U },
    2483             :   { AArch64::H0, 64U },
    2484             :   { AArch64::H1, 65U },
    2485             :   { AArch64::H2, 66U },
    2486             :   { AArch64::H3, 67U },
    2487             :   { AArch64::H4, 68U },
    2488             :   { AArch64::H5, 69U },
    2489             :   { AArch64::H6, 70U },
    2490             :   { AArch64::H7, 71U },
    2491             :   { AArch64::H8, 72U },
    2492             :   { AArch64::H9, 73U },
    2493             :   { AArch64::H10, 74U },
    2494             :   { AArch64::H11, 75U },
    2495             :   { AArch64::H12, 76U },
    2496             :   { AArch64::H13, 77U },
    2497             :   { AArch64::H14, 78U },
    2498             :   { AArch64::H15, 79U },
    2499             :   { AArch64::H16, 80U },
    2500             :   { AArch64::H17, 81U },
    2501             :   { AArch64::H18, 82U },
    2502             :   { AArch64::H19, 83U },
    2503             :   { AArch64::H20, 84U },
    2504             :   { AArch64::H21, 85U },
    2505             :   { AArch64::H22, 86U },
    2506             :   { AArch64::H23, 87U },
    2507             :   { AArch64::H24, 88U },
    2508             :   { AArch64::H25, 89U },
    2509             :   { AArch64::H26, 90U },
    2510             :   { AArch64::H27, 91U },
    2511             :   { AArch64::H28, 92U },
    2512             :   { AArch64::H29, 93U },
    2513             :   { AArch64::H30, 94U },
    2514             :   { AArch64::H31, 95U },
    2515             :   { AArch64::Q0, 64U },
    2516             :   { AArch64::Q1, 65U },
    2517             :   { AArch64::Q2, 66U },
    2518             :   { AArch64::Q3, 67U },
    2519             :   { AArch64::Q4, 68U },
    2520             :   { AArch64::Q5, 69U },
    2521             :   { AArch64::Q6, 70U },
    2522             :   { AArch64::Q7, 71U },
    2523             :   { AArch64::Q8, 72U },
    2524             :   { AArch64::Q9, 73U },
    2525             :   { AArch64::Q10, 74U },
    2526             :   { AArch64::Q11, 75U },
    2527             :   { AArch64::Q12, 76U },
    2528             :   { AArch64::Q13, 77U },
    2529             :   { AArch64::Q14, 78U },
    2530             :   { AArch64::Q15, 79U },
    2531             :   { AArch64::Q16, 80U },
    2532             :   { AArch64::Q17, 81U },
    2533             :   { AArch64::Q18, 82U },
    2534             :   { AArch64::Q19, 83U },
    2535             :   { AArch64::Q20, 84U },
    2536             :   { AArch64::Q21, 85U },
    2537             :   { AArch64::Q22, 86U },
    2538             :   { AArch64::Q23, 87U },
    2539             :   { AArch64::Q24, 88U },
    2540             :   { AArch64::Q25, 89U },
    2541             :   { AArch64::Q26, 90U },
    2542             :   { AArch64::Q27, 91U },
    2543             :   { AArch64::Q28, 92U },
    2544             :   { AArch64::Q29, 93U },
    2545             :   { AArch64::Q30, 94U },
    2546             :   { AArch64::Q31, 95U },
    2547             :   { AArch64::S0, 64U },
    2548             :   { AArch64::S1, 65U },
    2549             :   { AArch64::S2, 66U },
    2550             :   { AArch64::S3, 67U },
    2551             :   { AArch64::S4, 68U },
    2552             :   { AArch64::S5, 69U },
    2553             :   { AArch64::S6, 70U },
    2554             :   { AArch64::S7, 71U },
    2555             :   { AArch64::S8, 72U },
    2556             :   { AArch64::S9, 73U },
    2557             :   { AArch64::S10, 74U },
    2558             :   { AArch64::S11, 75U },
    2559             :   { AArch64::S12, 76U },
    2560             :   { AArch64::S13, 77U },
    2561             :   { AArch64::S14, 78U },
    2562             :   { AArch64::S15, 79U },
    2563             :   { AArch64::S16, 80U },
    2564             :   { AArch64::S17, 81U },
    2565             :   { AArch64::S18, 82U },
    2566             :   { AArch64::S19, 83U },
    2567             :   { AArch64::S20, 84U },
    2568             :   { AArch64::S21, 85U },
    2569             :   { AArch64::S22, 86U },
    2570             :   { AArch64::S23, 87U },
    2571             :   { AArch64::S24, 88U },
    2572             :   { AArch64::S25, 89U },
    2573             :   { AArch64::S26, 90U },
    2574             :   { AArch64::S27, 91U },
    2575             :   { AArch64::S28, 92U },
    2576             :   { AArch64::S29, 93U },
    2577             :   { AArch64::S30, 94U },
    2578             :   { AArch64::S31, 95U },
    2579             :   { AArch64::W0, 0U },
    2580             :   { AArch64::W1, 1U },
    2581             :   { AArch64::W2, 2U },
    2582             :   { AArch64::W3, 3U },
    2583             :   { AArch64::W4, 4U },
    2584             :   { AArch64::W5, 5U },
    2585             :   { AArch64::W6, 6U },
    2586             :   { AArch64::W7, 7U },
    2587             :   { AArch64::W8, 8U },
    2588             :   { AArch64::W9, 9U },
    2589             :   { AArch64::W10, 10U },
    2590             :   { AArch64::W11, 11U },
    2591             :   { AArch64::W12, 12U },
    2592             :   { AArch64::W13, 13U },
    2593             :   { AArch64::W14, 14U },
    2594             :   { AArch64::W15, 15U },
    2595             :   { AArch64::W16, 16U },
    2596             :   { AArch64::W17, 17U },
    2597             :   { AArch64::W18, 18U },
    2598             :   { AArch64::W19, 19U },
    2599             :   { AArch64::W20, 20U },
    2600             :   { AArch64::W21, 21U },
    2601             :   { AArch64::W22, 22U },
    2602             :   { AArch64::W23, 23U },
    2603             :   { AArch64::W24, 24U },
    2604             :   { AArch64::W25, 25U },
    2605             :   { AArch64::W26, 26U },
    2606             :   { AArch64::W27, 27U },
    2607             :   { AArch64::W28, 28U },
    2608             :   { AArch64::W29, 29U },
    2609             :   { AArch64::W30, 30U },
    2610             :   { AArch64::X0, 0U },
    2611             :   { AArch64::X1, 1U },
    2612             :   { AArch64::X2, 2U },
    2613             :   { AArch64::X3, 3U },
    2614             :   { AArch64::X4, 4U },
    2615             :   { AArch64::X5, 5U },
    2616             :   { AArch64::X6, 6U },
    2617             :   { AArch64::X7, 7U },
    2618             :   { AArch64::X8, 8U },
    2619             :   { AArch64::X9, 9U },
    2620             :   { AArch64::X10, 10U },
    2621             :   { AArch64::X11, 11U },
    2622             :   { AArch64::X12, 12U },
    2623             :   { AArch64::X13, 13U },
    2624             :   { AArch64::X14, 14U },
    2625             :   { AArch64::X15, 15U },
    2626             :   { AArch64::X16, 16U },
    2627             :   { AArch64::X17, 17U },
    2628             :   { AArch64::X18, 18U },
    2629             :   { AArch64::X19, 19U },
    2630             :   { AArch64::X20, 20U },
    2631             :   { AArch64::X21, 21U },
    2632             :   { AArch64::X22, 22U },
    2633             :   { AArch64::X23, 23U },
    2634             :   { AArch64::X24, 24U },
    2635             :   { AArch64::X25, 25U },
    2636             :   { AArch64::X26, 26U },
    2637             :   { AArch64::X27, 27U },
    2638             :   { AArch64::X28, 28U },
    2639             : };
    2640             : extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
    2641             : 
    2642             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
    2643             :   { AArch64::FP, 29U },
    2644             :   { AArch64::LR, 30U },
    2645             :   { AArch64::SP, 31U },
    2646             :   { AArch64::WSP, 31U },
    2647             :   { AArch64::WZR, 31U },
    2648             :   { AArch64::XZR, 31U },
    2649             :   { AArch64::B0, 64U },
    2650             :   { AArch64::B1, 65U },
    2651             :   { AArch64::B2, 66U },
    2652             :   { AArch64::B3, 67U },
    2653             :   { AArch64::B4, 68U },
    2654             :   { AArch64::B5, 69U },
    2655             :   { AArch64::B6, 70U },
    2656             :   { AArch64::B7, 71U },
    2657             :   { AArch64::B8, 72U },
    2658             :   { AArch64::B9, 73U },
    2659             :   { AArch64::B10, 74U },
    2660             :   { AArch64::B11, 75U },
    2661             :   { AArch64::B12, 76U },
    2662             :   { AArch64::B13, 77U },
    2663             :   { AArch64::B14, 78U },
    2664             :   { AArch64::B15, 79U },
    2665             :   { AArch64::B16, 80U },
    2666             :   { AArch64::B17, 81U },
    2667             :   { AArch64::B18, 82U },
    2668             :   { AArch64::B19, 83U },
    2669             :   { AArch64::B20, 84U },
    2670             :   { AArch64::B21, 85U },
    2671             :   { AArch64::B22, 86U },
    2672             :   { AArch64::B23, 87U },
    2673             :   { AArch64::B24, 88U },
    2674             :   { AArch64::B25, 89U },
    2675             :   { AArch64::B26, 90U },
    2676             :   { AArch64::B27, 91U },
    2677             :   { AArch64::B28, 92U },
    2678             :   { AArch64::B29, 93U },
    2679             :   { AArch64::B30, 94U },
    2680             :   { AArch64::B31, 95U },
    2681             :   { AArch64::D0, 64U },
    2682             :   { AArch64::D1, 65U },
    2683             :   { AArch64::D2, 66U },
    2684             :   { AArch64::D3, 67U },
    2685             :   { AArch64::D4, 68U },
    2686             :   { AArch64::D5, 69U },
    2687             :   { AArch64::D6, 70U },
    2688             :   { AArch64::D7, 71U },
    2689             :   { AArch64::D8, 72U },
    2690             :   { AArch64::D9, 73U },
    2691             :   { AArch64::D10, 74U },
    2692             :   { AArch64::D11, 75U },
    2693             :   { AArch64::D12, 76U },
    2694             :   { AArch64::D13, 77U },
    2695             :   { AArch64::D14, 78U },
    2696             :   { AArch64::D15, 79U },
    2697             :   { AArch64::D16, 80U },
    2698             :   { AArch64::D17, 81U },
    2699             :   { AArch64::D18, 82U },
    2700             :   { AArch64::D19, 83U },
    2701             :   { AArch64::D20, 84U },
    2702             :   { AArch64::D21, 85U },
    2703             :   { AArch64::D22, 86U },
    2704             :   { AArch64::D23, 87U },
    2705             :   { AArch64::D24, 88U },
    2706             :   { AArch64::D25, 89U },
    2707             :   { AArch64::D26, 90U },
    2708             :   { AArch64::D27, 91U },
    2709             :   { AArch64::D28, 92U },
    2710             :   { AArch64::D29, 93U },
    2711             :   { AArch64::D30, 94U },
    2712             :   { AArch64::D31, 95U },
    2713             :   { AArch64::H0, 64U },
    2714             :   { AArch64::H1, 65U },
    2715             :   { AArch64::H2, 66U },
    2716             :   { AArch64::H3, 67U },
    2717             :   { AArch64::H4, 68U },
    2718             :   { AArch64::H5, 69U },
    2719             :   { AArch64::H6, 70U },
    2720             :   { AArch64::H7, 71U },
    2721             :   { AArch64::H8, 72U },
    2722             :   { AArch64::H9, 73U },
    2723             :   { AArch64::H10, 74U },
    2724             :   { AArch64::H11, 75U },
    2725             :   { AArch64::H12, 76U },
    2726             :   { AArch64::H13, 77U },
    2727             :   { AArch64::H14, 78U },
    2728             :   { AArch64::H15, 79U },
    2729             :   { AArch64::H16, 80U },
    2730             :   { AArch64::H17, 81U },
    2731             :   { AArch64::H18, 82U },
    2732             :   { AArch64::H19, 83U },
    2733             :   { AArch64::H20, 84U },
    2734             :   { AArch64::H21, 85U },
    2735             :   { AArch64::H22, 86U },
    2736             :   { AArch64::H23, 87U },
    2737             :   { AArch64::H24, 88U },
    2738             :   { AArch64::H25, 89U },
    2739             :   { AArch64::H26, 90U },
    2740             :   { AArch64::H27, 91U },
    2741             :   { AArch64::H28, 92U },
    2742             :   { AArch64::H29, 93U },
    2743             :   { AArch64::H30, 94U },
    2744             :   { AArch64::H31, 95U },
    2745             :   { AArch64::Q0, 64U },
    2746             :   { AArch64::Q1, 65U },
    2747             :   { AArch64::Q2, 66U },
    2748             :   { AArch64::Q3, 67U },
    2749             :   { AArch64::Q4, 68U },
    2750             :   { AArch64::Q5, 69U },
    2751             :   { AArch64::Q6, 70U },
    2752             :   { AArch64::Q7, 71U },
    2753             :   { AArch64::Q8, 72U },
    2754             :   { AArch64::Q9, 73U },
    2755             :   { AArch64::Q10, 74U },
    2756             :   { AArch64::Q11, 75U },
    2757             :   { AArch64::Q12, 76U },
    2758             :   { AArch64::Q13, 77U },
    2759             :   { AArch64::Q14, 78U },
    2760             :   { AArch64::Q15, 79U },
    2761             :   { AArch64::Q16, 80U },
    2762             :   { AArch64::Q17, 81U },
    2763             :   { AArch64::Q18, 82U },
    2764             :   { AArch64::Q19, 83U },
    2765             :   { AArch64::Q20, 84U },
    2766             :   { AArch64::Q21, 85U },
    2767             :   { AArch64::Q22, 86U },
    2768             :   { AArch64::Q23, 87U },
    2769             :   { AArch64::Q24, 88U },
    2770             :   { AArch64::Q25, 89U },
    2771             :   { AArch64::Q26, 90U },
    2772             :   { AArch64::Q27, 91U },
    2773             :   { AArch64::Q28, 92U },
    2774             :   { AArch64::Q29, 93U },
    2775             :   { AArch64::Q30, 94U },
    2776             :   { AArch64::Q31, 95U },
    2777             :   { AArch64::S0, 64U },
    2778             :   { AArch64::S1, 65U },
    2779             :   { AArch64::S2, 66U },
    2780             :   { AArch64::S3, 67U },
    2781             :   { AArch64::S4, 68U },
    2782             :   { AArch64::S5, 69U },
    2783             :   { AArch64::S6, 70U },
    2784             :   { AArch64::S7, 71U },
    2785             :   { AArch64::S8, 72U },
    2786             :   { AArch64::S9, 73U },
    2787             :   { AArch64::S10, 74U },
    2788             :   { AArch64::S11, 75U },
    2789             :   { AArch64::S12, 76U },
    2790             :   { AArch64::S13, 77U },
    2791             :   { AArch64::S14, 78U },
    2792             :   { AArch64::S15, 79U },
    2793             :   { AArch64::S16, 80U },
    2794             :   { AArch64::S17, 81U },
    2795             :   { AArch64::S18, 82U },
    2796             :   { AArch64::S19, 83U },
    2797             :   { AArch64::S20, 84U },
    2798             :   { AArch64::S21, 85U },
    2799             :   { AArch64::S22, 86U },
    2800             :   { AArch64::S23, 87U },
    2801             :   { AArch64::S24, 88U },
    2802             :   { AArch64::S25, 89U },
    2803             :   { AArch64::S26, 90U },
    2804             :   { AArch64::S27, 91U },
    2805             :   { AArch64::S28, 92U },
    2806             :   { AArch64::S29, 93U },
    2807             :   { AArch64::S30, 94U },
    2808             :   { AArch64::S31, 95U },
    2809             :   { AArch64::W0, 0U },
    2810             :   { AArch64::W1, 1U },
    2811             :   { AArch64::W2, 2U },
    2812             :   { AArch64::W3, 3U },
    2813             :   { AArch64::W4, 4U },
    2814             :   { AArch64::W5, 5U },
    2815             :   { AArch64::W6, 6U },
    2816             :   { AArch64::W7, 7U },
    2817             :   { AArch64::W8, 8U },
    2818             :   { AArch64::W9, 9U },
    2819             :   { AArch64::W10, 10U },
    2820             :   { AArch64::W11, 11U },
    2821             :   { AArch64::W12, 12U },
    2822             :   { AArch64::W13, 13U },
    2823             :   { AArch64::W14, 14U },
    2824             :   { AArch64::W15, 15U },
    2825             :   { AArch64::W16, 16U },
    2826             :   { AArch64::W17, 17U },
    2827             :   { AArch64::W18, 18U },
    2828             :   { AArch64::W19, 19U },
    2829             :   { AArch64::W20, 20U },
    2830             :   { AArch64::W21, 21U },
    2831             :   { AArch64::W22, 22U },
    2832             :   { AArch64::W23, 23U },
    2833             :   { AArch64::W24, 24U },
    2834             :   { AArch64::W25, 25U },
    2835             :   { AArch64::W26, 26U },
    2836             :   { AArch64::W27, 27U },
    2837             :   { AArch64::W28, 28U },
    2838             :   { AArch64::W29, 29U },
    2839             :   { AArch64::W30, 30U },
    2840             :   { AArch64::X0, 0U },
    2841             :   { AArch64::X1, 1U },
    2842             :   { AArch64::X2, 2U },
    2843             :   { AArch64::X3, 3U },
    2844             :   { AArch64::X4, 4U },
    2845             :   { AArch64::X5, 5U },
    2846             :   { AArch64::X6, 6U },
    2847             :   { AArch64::X7, 7U },
    2848             :   { AArch64::X8, 8U },
    2849             :   { AArch64::X9, 9U },
    2850             :   { AArch64::X10, 10U },
    2851             :   { AArch64::X11, 11U },
    2852             :   { AArch64::X12, 12U },
    2853             :   { AArch64::X13, 13U },
    2854             :   { AArch64::X14, 14U },
    2855             :   { AArch64::X15, 15U },
    2856             :   { AArch64::X16, 16U },
    2857             :   { AArch64::X17, 17U },
    2858             :   { AArch64::X18, 18U },
    2859             :   { AArch64::X19, 19U },
    2860             :   { AArch64::X20, 20U },
    2861             :   { AArch64::X21, 21U },
    2862             :   { AArch64::X22, 22U },
    2863             :   { AArch64::X23, 23U },
    2864             :   { AArch64::X24, 24U },
    2865             :   { AArch64::X25, 25U },
    2866             :   { AArch64::X26, 26U },
    2867             :   { AArch64::X27, 27U },
    2868             :   { AArch64::X28, 28U },
    2869             : };
    2870             : extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
    2871             : 
    2872             : extern const uint16_t AArch64RegEncodingTable[] = {
    2873             :   0,
    2874             :   29,
    2875             :   30,
    2876             :   0,
    2877             :   31,
    2878             :   31,
    2879             :   31,
    2880             :   31,
    2881             :   0,
    2882             :   1,
    2883             :   2,
    2884             :   3,
    2885             :   4,
    2886             :   5,
    2887             :   6,
    2888             :   7,
    2889             :   8,
    2890             :   9,
    2891             :   10,
    2892             :   11,
    2893             :   12,
    2894             :   13,
    2895             :   14,
    2896             :   15,
    2897             :   16,
    2898             :   17,
    2899             :   18,
    2900             :   19,
    2901             :   20,
    2902             :   21,
    2903             :   22,
    2904             :   23,
    2905             :   24,
    2906             :   25,
    2907             :   26,
    2908             :   27,
    2909             :   28,
    2910             :   29,
    2911             :   30,
    2912             :   31,
    2913             :   0,
    2914             :   1,
    2915             :   2,
    2916             :   3,
    2917             :   4,
    2918             :   5,
    2919             :   6,
    2920             :   7,
    2921             :   8,
    2922             :   9,
    2923             :   10,
    2924             :   11,
    2925             :   12,
    2926             :   13,
    2927             :   14,
    2928             :   15,
    2929             :   16,
    2930             :   17,
    2931             :   18,
    2932             :   19,
    2933             :   20,
    2934             :   21,
    2935             :   22,
    2936             :   23,
    2937             :   24,
    2938             :   25,
    2939             :   26,
    2940             :   27,
    2941             :   28,
    2942             :   29,
    2943             :   30,
    2944             :   31,
    2945             :   0,
    2946             :   1,
    2947             :   2,
    2948             :   3,
    2949             :   4,
    2950             :   5,
    2951             :   6,
    2952             :   7,
    2953             :   8,
    2954             :   9,
    2955             :   10,
    2956             :   11,
    2957             :   12,
    2958             :   13,
    2959             :   14,
    2960             :   15,
    2961             :   16,
    2962             :   17,
    2963             :   18,
    2964             :   19,
    2965             :   20,
    2966             :   21,
    2967             :   22,
    2968             :   23,
    2969             :   24,
    2970             :   25,
    2971             :   26,
    2972             :   27,
    2973             :   28,
    2974             :   29,
    2975             :   30,
    2976             :   31,
    2977             :   0,
    2978             :   1,
    2979             :   2,
    2980             :   3,
    2981             :   4,
    2982             :   5,
    2983             :   6,
    2984             :   7,
    2985             :   8,
    2986             :   9,
    2987             :   10,
    2988             :   11,
    2989             :   12,
    2990             :   13,
    2991             :   14,
    2992             :   15,
    2993             :   16,
    2994             :   17,
    2995             :   18,
    2996             :   19,
    2997             :   20,
    2998             :   21,
    2999             :   22,
    3000             :   23,
    3001             :   24,
    3002             :   25,
    3003             :   26,
    3004             :   27,
    3005             :   28,
    3006             :   29,
    3007             :   30,
    3008             :   31,
    3009             :   0,
    3010             :   1,
    3011             :   2,
    3012             :   3,
    3013             :   4,
    3014             :   5,
    3015             :   6,
    3016             :   7,
    3017             :   8,
    3018             :   9,
    3019             :   10,
    3020             :   11,
    3021             :   12,
    3022             :   13,
    3023             :   14,
    3024             :   15,
    3025             :   16,
    3026             :   17,
    3027             :   18,
    3028             :   19,
    3029             :   20,
    3030             :   21,
    3031             :   22,
    3032             :   23,
    3033             :   24,
    3034             :   25,
    3035             :   26,
    3036             :   27,
    3037             :   28,
    3038             :   29,
    3039             :   30,
    3040             :   31,
    3041             :   0,
    3042             :   1,
    3043             :   2,
    3044             :   3,
    3045             :   4,
    3046             :   5,
    3047             :   6,
    3048             :   7,
    3049             :   8,
    3050             :   9,
    3051             :   10,
    3052             :   11,
    3053             :   12,
    3054             :   13,
    3055             :   14,
    3056             :   15,
    3057             :   16,
    3058             :   17,
    3059             :   18,
    3060             :   19,
    3061             :   20,
    3062             :   21,
    3063             :   22,
    3064             :   23,
    3065             :   24,
    3066             :   25,
    3067             :   26,
    3068             :   27,
    3069             :   28,
    3070             :   29,
    3071             :   30,
    3072             :   0,
    3073             :   1,
    3074             :   2,
    3075             :   3,
    3076             :   4,
    3077             :   5,
    3078             :   6,
    3079             :   7,
    3080             :   8,
    3081             :   9,
    3082             :   10,
    3083             :   11,
    3084             :   12,
    3085             :   13,
    3086             :   14,
    3087             :   15,
    3088             :   16,
    3089             :   17,
    3090             :   18,
    3091             :   19,
    3092             :   20,
    3093             :   21,
    3094             :   22,
    3095             :   23,
    3096             :   24,
    3097             :   25,
    3098             :   26,
    3099             :   27,
    3100             :   28,
    3101             :   0,
    3102             :   1,
    3103             :   2,
    3104             :   3,
    3105             :   4,
    3106             :   5,
    3107             :   6,
    3108             :   7,
    3109             :   8,
    3110             :   9,
    3111             :   10,
    3112             :   11,
    3113             :   12,
    3114             :   13,
    3115             :   14,
    3116             :   15,
    3117             :   16,
    3118             :   17,
    3119             :   18,
    3120             :   19,
    3121             :   20,
    3122             :   21,
    3123             :   22,
    3124             :   23,
    3125             :   24,
    3126             :   25,
    3127             :   26,
    3128             :   27,
    3129             :   28,
    3130             :   29,
    3131             :   30,
    3132             :   31,
    3133             :   0,
    3134             :   1,
    3135             :   2,
    3136             :   3,
    3137             :   4,
    3138             :   5,
    3139             :   6,
    3140             :   7,
    3141             :   8,
    3142             :   9,
    3143             :   10,
    3144             :   11,
    3145             :   12,
    3146             :   13,
    3147             :   14,
    3148             :   15,
    3149             :   16,
    3150             :   17,
    3151             :   18,
    3152             :   19,
    3153             :   20,
    3154             :   21,
    3155             :   22,
    3156             :   23,
    3157             :   24,
    3158             :   25,
    3159             :   26,
    3160             :   27,
    3161             :   28,
    3162             :   29,
    3163             :   30,
    3164             :   31,
    3165             :   0,
    3166             :   1,
    3167             :   2,
    3168             :   3,
    3169             :   4,
    3170             :   5,
    3171             :   6,
    3172             :   7,
    3173             :   8,
    3174             :   9,
    3175             :   10,
    3176             :   11,
    3177             :   12,
    3178             :   13,
    3179             :   14,
    3180             :   15,
    3181             :   16,
    3182             :   17,
    3183             :   18,
    3184             :   19,
    3185             :   20,
    3186             :   21,
    3187             :   22,
    3188             :   23,
    3189             :   24,
    3190             :   25,
    3191             :   26,
    3192             :   27,
    3193             :   28,
    3194             :   29,
    3195             :   30,
    3196             :   31,
    3197             :   0,
    3198             :   1,
    3199             :   2,
    3200             :   3,
    3201             :   4,
    3202             :   5,
    3203             :   6,
    3204             :   7,
    3205             :   8,
    3206             :   9,
    3207             :   10,
    3208             :   11,
    3209             :   12,
    3210             :   13,
    3211             :   14,
    3212             :   15,
    3213             :   16,
    3214             :   17,
    3215             :   18,
    3216             :   19,
    3217             :   20,
    3218             :   21,
    3219             :   22,
    3220             :   23,
    3221             :   24,
    3222             :   25,
    3223             :   26,
    3224             :   27,
    3225             :   28,
    3226             :   29,
    3227             :   30,
    3228             :   31,
    3229             :   0,
    3230             :   1,
    3231             :   2,
    3232             :   3,
    3233             :   4,
    3234             :   5,
    3235             :   6,
    3236             :   7,
    3237             :   8,
    3238             :   9,
    3239             :   10,
    3240             :   11,
    3241             :   12,
    3242             :   13,
    3243             :   14,
    3244             :   15,
    3245             :   16,
    3246             :   17,
    3247             :   18,
    3248             :   19,
    3249             :   20,
    3250             :   21,
    3251             :   22,
    3252             :   23,
    3253             :   24,
    3254             :   25,
    3255             :   26,
    3256             :   27,
    3257             :   28,
    3258             :   29,
    3259             :   30,
    3260             :   31,
    3261             :   0,
    3262             :   1,
    3263             :   2,
    3264             :   3,
    3265             :   4,
    3266             :   5,
    3267             :   6,
    3268             :   7,
    3269             :   8,
    3270             :   9,
    3271             :   10,
    3272             :   11,
    3273             :   12,
    3274             :   13,
    3275             :   14,
    3276             :   15,
    3277             :   16,
    3278             :   17,
    3279             :   18,
    3280             :   19,
    3281             :   20,
    3282             :   21,
    3283             :   22,
    3284             :   23,
    3285             :   24,
    3286             :   25,
    3287             :   26,
    3288             :   27,
    3289             :   28,
    3290             :   29,
    3291             :   30,
    3292             :   31,
    3293             :   31,
    3294             :   30,
    3295             :   0,
    3296             :   1,
    3297             :   2,
    3298             :   3,
    3299             :   4,
    3300             :   5,
    3301             :   6,
    3302             :   7,
    3303             :   8,
    3304             :   9,
    3305             :   10,
    3306             :   11,
    3307             :   12,
    3308             :   13,
    3309             :   14,
    3310             :   15,
    3311             :   16,
    3312             :   17,
    3313             :   18,
    3314             :   19,
    3315             :   20,
    3316             :   21,
    3317             :   22,
    3318             :   23,
    3319             :   24,
    3320             :   25,
    3321             :   26,
    3322             :   27,
    3323             :   28,
    3324             :   29,
    3325             :   29,
    3326             :   30,
    3327             :   31,
    3328             :   28,
    3329             :   0,
    3330             :   1,
    3331             :   2,
    3332             :   3,
    3333             :   4,
    3334             :   5,
    3335             :   6,
    3336             :   7,
    3337             :   8,
    3338             :   9,
    3339             :   10,
    3340             :   11,
    3341             :   12,
    3342             :   13,
    3343             :   14,
    3344             :   15,
    3345             :   16,
    3346             :   17,
    3347             :   18,
    3348             :   19,
    3349             :   20,
    3350             :   21,
    3351             :   22,
    3352             :   23,
    3353             :   24,
    3354             :   25,
    3355             :   26,
    3356             :   27,
    3357             : };
    3358             : static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
    3359        1988 :   RI->InitMCRegisterInfo(AArch64RegDesc, 484, RA, PC, AArch64MCRegisterClasses, 54, AArch64RegUnitRoots, 66, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 59,
    3360             : AArch64SubRegIdxRanges, AArch64RegEncodingTable);
    3361             : 
    3362             :   switch (DwarfFlavour) {
    3363             :   default:
    3364             :     llvm_unreachable("Unknown DWARF flavour");
    3365        1988 :   case 0:
    3366        1988 :     RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
    3367             :     break;
    3368             :   }
    3369             :   switch (EHFlavour) {
    3370             :   default:
    3371             :     llvm_unreachable("Unknown DWARF flavour");
    3372        1988 :   case 0:
    3373        1988 :     RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
    3374             :     break;
    3375             :   }
    3376             :   switch (DwarfFlavour) {
    3377             :   default:
    3378             :     llvm_unreachable("Unknown DWARF flavour");
    3379        1988 :   case 0:
    3380        1988 :     RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
    3381             :     break;
    3382             :   }
    3383             :   switch (EHFlavour) {
    3384             :   default:
    3385             :     llvm_unreachable("Unknown DWARF flavour");
    3386        1988 :   case 0:
    3387        1988 :     RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
    3388             :     break;
    3389             :   }
    3390             : }
    3391             : 
    3392             : } // end namespace llvm
    3393             : 
    3394             : #endif // GET_REGINFO_MC_DESC
    3395             : 
    3396             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    3397             : |*                                                                            *|
    3398             : |* Register Information Header Fragment                                       *|
    3399             : |*                                                                            *|
    3400             : |* Automatically generated file, do not edit!                                 *|
    3401             : |*                                                                            *|
    3402             : \*===----------------------------------------------------------------------===*/
    3403             : 
    3404             : 
    3405             : #ifdef GET_REGINFO_HEADER
    3406             : #undef GET_REGINFO_HEADER
    3407             : 
    3408             : #include "llvm/Target/TargetRegisterInfo.h"
    3409             : 
    3410             : namespace llvm {
    3411             : 
    3412             : class AArch64FrameLowering;
    3413             : 
    3414        1196 : struct AArch64GenRegisterInfo : public TargetRegisterInfo {
    3415             :   explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);
    3416             :   unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
    3417             :   LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    3418             :   LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    3419             :   const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
    3420             :   const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
    3421             :   unsigned getRegUnitWeight(unsigned RegUnit) const override;
    3422             :   unsigned getNumRegPressureSets() const override;
    3423             :   const char *getRegPressureSetName(unsigned Idx) const override;
    3424             :   unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
    3425             :   const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
    3426             :   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
    3427             :   ArrayRef<const char *> getRegMaskNames() const override;
    3428             :   ArrayRef<const uint32_t *> getRegMasks() const override;
    3429             :   /// Devirtualized TargetFrameLowering.
    3430             :   static const AArch64FrameLowering *getFrameLowering(
    3431             :       const MachineFunction &MF);
    3432             : };
    3433             : 
    3434             : namespace AArch64 { // Register classes
    3435             :   extern const TargetRegisterClass FPR8RegClass;
    3436             :   extern const TargetRegisterClass FPR16RegClass;
    3437             :   extern const TargetRegisterClass GPR32allRegClass;
    3438             :   extern const TargetRegisterClass FPR32RegClass;
    3439             :   extern const TargetRegisterClass GPR32RegClass;
    3440             :   extern const TargetRegisterClass GPR32spRegClass;
    3441             :   extern const TargetRegisterClass GPR32commonRegClass;
    3442             :   extern const TargetRegisterClass CCRRegClass;
    3443             :   extern const TargetRegisterClass GPR32sponlyRegClass;
    3444             :   extern const TargetRegisterClass WSeqPairsClassRegClass;
    3445             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass;
    3446             :   extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
    3447             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
    3448             :   extern const TargetRegisterClass GPR64allRegClass;
    3449             :   extern const TargetRegisterClass FPR64RegClass;
    3450             :   extern const TargetRegisterClass GPR64RegClass;
    3451             :   extern const TargetRegisterClass GPR64spRegClass;
    3452             :   extern const TargetRegisterClass GPR64commonRegClass;
    3453             :   extern const TargetRegisterClass tcGPR64RegClass;
    3454             :   extern const TargetRegisterClass GPR64sponlyRegClass;
    3455             :   extern const TargetRegisterClass DDRegClass;
    3456             :   extern const TargetRegisterClass XSeqPairsClassRegClass;
    3457             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass;
    3458             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
    3459             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
    3460             :   extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
    3461             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
    3462             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
    3463             :   extern const TargetRegisterClass FPR128RegClass;
    3464             :   extern const TargetRegisterClass FPR128_loRegClass;
    3465             :   extern const TargetRegisterClass DDDRegClass;
    3466             :   extern const TargetRegisterClass DDDDRegClass;
    3467             :   extern const TargetRegisterClass QQRegClass;
    3468             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
    3469             :   extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;
    3470             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass;
    3471             :   extern const TargetRegisterClass QQQRegClass;
    3472             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass;
    3473             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass;
    3474             :   extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass;
    3475             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass;
    3476             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
    3477             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
    3478             :   extern const TargetRegisterClass QQQQRegClass;
    3479             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass;
    3480             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass;
    3481             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass;
    3482             :   extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass;
    3483             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass;
    3484             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
    3485             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    3486             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
    3487             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    3488             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    3489             : } // end namespace AArch64
    3490             : 
    3491             : } // end namespace llvm
    3492             : 
    3493             : #endif // GET_REGINFO_HEADER
    3494             : 
    3495             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    3496             : |*                                                                            *|
    3497             : |* Target Register and Register Classes Information                           *|
    3498             : |*                                                                            *|
    3499             : |* Automatically generated file, do not edit!                                 *|
    3500             : |*                                                                            *|
    3501             : \*===----------------------------------------------------------------------===*/
    3502             : 
    3503             : 
    3504             : #ifdef GET_REGINFO_TARGET_DESC
    3505             : #undef GET_REGINFO_TARGET_DESC
    3506             : 
    3507             : namespace llvm {
    3508             : 
    3509             : extern const MCRegisterClass AArch64MCRegisterClasses[];
    3510             : 
    3511             : static const MVT::SimpleValueType VTLists[] = {
    3512             :   /* 0 */ MVT::f32, MVT::i32, MVT::Other,
    3513             :   /* 3 */ MVT::i64, MVT::Other,
    3514             :   /* 5 */ MVT::f16, MVT::Other,
    3515             :   /* 7 */ MVT::f64, MVT::i64, MVT::v2f32, MVT::v1f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v4f16, MVT::Other,
    3516             :   /* 17 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::v8f16, MVT::Other,
    3517             :   /* 26 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
    3518             :   /* 34 */ MVT::Untyped, MVT::Other,
    3519             : };
    3520             : 
    3521             : static const char *const SubRegIndexNameTable[] = { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1", "qsub2", "qsub3", "ssub", "sub_32", "sube32", "sube64", "subo32", "subo64", "dsub1_then_bsub", "dsub1_then_hsub", "dsub1_then_ssub", "dsub3_then_bsub", "dsub3_then_hsub", "dsub3_then_ssub", "dsub2_then_bsub", "dsub2_then_hsub", "dsub2_then_ssub", "qsub1_then_bsub", "qsub1_then_dsub", "qsub1_then_hsub", "qsub1_then_ssub", "qsub3_then_bsub", "qsub3_then_dsub", "qsub3_then_hsub", "qsub3_then_ssub", "qsub2_then_bsub", "qsub2_then_dsub", "qsub2_then_hsub", "qsub2_then_ssub", "subo64_then_sub_32", "dsub0_dsub1", "dsub0_dsub1_dsub2", "dsub1_dsub2", "dsub1_dsub2_dsub3", "dsub2_dsub3", "dsub_qsub1_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub", "qsub0_qsub1", "qsub0_qsub1_qsub2", "qsub1_qsub2", "qsub1_qsub2_qsub3", "qsub2_qsub3", "qsub1_then_dsub_qsub2_then_dsub", "qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "qsub2_then_dsub_qsub3_then_dsub", "sub_32_subo64_then_sub_32", "" };
    3522             : 
    3523             : 
    3524             : static const LaneBitmask SubRegIndexLaneMaskTable[] = {
    3525             :   LaneBitmask::getAll(),
    3526             :   LaneBitmask(0x00000001), // bsub
    3527             :   LaneBitmask(0x00000001), // dsub
    3528             :   LaneBitmask(0x00000001), // dsub0
    3529             :   LaneBitmask(0x00000040), // dsub1
    3530             :   LaneBitmask(0x00000100), // dsub2
    3531             :   LaneBitmask(0x00000080), // dsub3
    3532             :   LaneBitmask(0x00000001), // hsub
    3533             :   LaneBitmask(0x00000002), // qhisub
    3534             :   LaneBitmask(0x00000004), // qsub
    3535             :   LaneBitmask(0x00000001), // qsub0
    3536             :   LaneBitmask(0x00000200), // qsub1
    3537             :   LaneBitmask(0x00000800), // qsub2
    3538             :   LaneBitmask(0x00000400), // qsub3
    3539             :   LaneBitmask(0x00000001), // ssub
    3540             :   LaneBitmask(0x00000008), // sub_32
    3541             :   LaneBitmask(0x00000010), // sube32
    3542             :   LaneBitmask(0x00000008), // sube64
    3543             :   LaneBitmask(0x00000020), // subo32
    3544             :   LaneBitmask(0x00001000), // subo64
    3545             :   LaneBitmask(0x00000040), // dsub1_then_bsub
    3546             :   LaneBitmask(0x00000040), // dsub1_then_hsub
    3547             :   LaneBitmask(0x00000040), // dsub1_then_ssub
    3548             :   LaneBitmask(0x00000080), // dsub3_then_bsub
    3549             :   LaneBitmask(0x00000080), // dsub3_then_hsub
    3550             :   LaneBitmask(0x00000080), // dsub3_then_ssub
    3551             :   LaneBitmask(0x00000100), // dsub2_then_bsub
    3552             :   LaneBitmask(0x00000100), // dsub2_then_hsub
    3553             :   LaneBitmask(0x00000100), // dsub2_then_ssub
    3554             :   LaneBitmask(0x00000200), // qsub1_then_bsub
    3555             :   LaneBitmask(0x00000200), // qsub1_then_dsub
    3556             :   LaneBitmask(0x00000200), // qsub1_then_hsub
    3557             :   LaneBitmask(0x00000200), // qsub1_then_ssub
    3558             :   LaneBitmask(0x00000400), // qsub3_then_bsub
    3559             :   LaneBitmask(0x00000400), // qsub3_then_dsub
    3560             :   LaneBitmask(0x00000400), // qsub3_then_hsub
    3561             :   LaneBitmask(0x00000400), // qsub3_then_ssub
    3562             :   LaneBitmask(0x00000800), // qsub2_then_bsub
    3563             :   LaneBitmask(0x00000800), // qsub2_then_dsub
    3564             :   LaneBitmask(0x00000800), // qsub2_then_hsub
    3565             :   LaneBitmask(0x00000800), // qsub2_then_ssub
    3566             :   LaneBitmask(0x00001000), // subo64_then_sub_32
    3567             :   LaneBitmask(0x00000041), // dsub0_dsub1
    3568             :   LaneBitmask(0x00000141), // dsub0_dsub1_dsub2
    3569             :   LaneBitmask(0x00000140), // dsub1_dsub2
    3570             :   LaneBitmask(0x000001C0), // dsub1_dsub2_dsub3
    3571             :   LaneBitmask(0x00000180), // dsub2_dsub3
    3572             :   LaneBitmask(0x00000201), // dsub_qsub1_then_dsub
    3573             :   LaneBitmask(0x00000E01), // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    3574             :   LaneBitmask(0x00000A01), // dsub_qsub1_then_dsub_qsub2_then_dsub
    3575             :   LaneBitmask(0x00000201), // qsub0_qsub1
    3576             :   LaneBitmask(0x00000A01), // qsub0_qsub1_qsub2
    3577             :   LaneBitmask(0x00000A00), // qsub1_qsub2
    3578             :   LaneBitmask(0x00000E00), // qsub1_qsub2_qsub3
    3579             :   LaneBitmask(0x00000C00), // qsub2_qsub3
    3580             :   LaneBitmask(0x00000A00), // qsub1_then_dsub_qsub2_then_dsub
    3581             :   LaneBitmask(0x00000E00), // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    3582             :   LaneBitmask(0x00000C00), // qsub2_then_dsub_qsub3_then_dsub
    3583             :   LaneBitmask(0x00001008), // sub_32_subo64_then_sub_32
    3584       72306 :  };
    3585             : 
    3586             : 
    3587             : 
    3588             : static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
    3589             : 
    3590             : static const uint32_t FPR8SubClassMask[] = {
    3591             :   0x00000001, 0x00000000, 
    3592             :   0xf010400a, 0x003fffff, // bsub
    3593             :   0xc0100000, 0x00000000, // dsub1_then_bsub
    3594             :   0x80000000, 0x00000000, // dsub3_then_bsub
    3595             :   0xc0000000, 0x00000000, // dsub2_then_bsub
    3596             :   0x00000000, 0x003fffff, // qsub1_then_bsub
    3597             :   0x00000000, 0x003ff800, // qsub3_then_bsub
    3598             :   0x00000000, 0x003ffff0, // qsub2_then_bsub
    3599             : };
    3600             : 
    3601             : static const uint32_t FPR16SubClassMask[] = {
    3602             :   0x00000002, 0x00000000, 
    3603             :   0xf0104008, 0x003fffff, // hsub
    3604             :   0xc0100000, 0x00000000, // dsub1_then_hsub
    3605             :   0x80000000, 0x00000000, // dsub3_then_hsub
    3606             :   0xc0000000, 0x00000000, // dsub2_then_hsub
    3607             :   0x00000000, 0x003fffff, // qsub1_then_hsub
    3608             :   0x00000000, 0x003ff800, // qsub3_then_hsub
    3609             :   0x00000000, 0x003ffff0, // qsub2_then_hsub
    3610             : };
    3611             : 
    3612             : static const uint32_t GPR32allSubClassMask[] = {
    3613             :   0x00000174, 0x00000000, 
    3614             :   0x0fefa000, 0x00000000, // sub_32
    3615             :   0x00001e00, 0x00000000, // sube32
    3616             :   0x00001e00, 0x00000000, // subo32
    3617             :   0x0fe00000, 0x00000000, // subo64_then_sub_32
    3618             : };
    3619             : 
    3620             : static const uint32_t FPR32SubClassMask[] = {
    3621             :   0x00000008, 0x00000000, 
    3622             :   0xf0104000, 0x003fffff, // ssub
    3623             :   0xc0100000, 0x00000000, // dsub1_then_ssub
    3624             :   0x80000000, 0x00000000, // dsub3_then_ssub
    3625             :   0xc0000000, 0x00000000, // dsub2_then_ssub
    3626             :   0x00000000, 0x003fffff, // qsub1_then_ssub
    3627             :   0x00000000, 0x003ff800, // qsub3_then_ssub
    3628             :   0x00000000, 0x003ffff0, // qsub2_then_ssub
    3629             : };
    3630             : 
    3631             : static const uint32_t GPR32SubClassMask[] = {
    3632             :   0x00000050, 0x00000000, 
    3633             :   0x0fe68000, 0x00000000, // sub_32
    3634             :   0x00001e00, 0x00000000, // sube32
    3635             :   0x00001e00, 0x00000000, // subo32
    3636             :   0x0fe00000, 0x00000000, // subo64_then_sub_32
    3637             : };
    3638             : 
    3639             : static const uint32_t GPR32spSubClassMask[] = {
    3640             :   0x00000160, 0x00000000, 
    3641             :   0x0b4f0000, 0x00000000, // sub_32
    3642             :   0x00001400, 0x00000000, // sube32
    3643             :   0x00001800, 0x00000000, // subo32
    3644             :   0x0f800000, 0x00000000, // subo64_then_sub_32
    3645             : };
    3646             : 
    3647             : static const uint32_t GPR32commonSubClassMask[] = {
    3648             :   0x00000040, 0x00000000, 
    3649             :   0x0b460000, 0x00000000, // sub_32
    3650             :   0x00001400, 0x00000000, // sube32
    3651             :   0x00001800, 0x00000000, // subo32
    3652             :   0x0f800000, 0x00000000, // subo64_then_sub_32
    3653             : };
    3654             : 
    3655             : static const uint32_t CCRSubClassMask[] = {
    3656             :   0x00000080, 0x00000000, 
    3657             : };
    3658             : 
    3659             : static const uint32_t GPR32sponlySubClassMask[] = {
    3660             :   0x00000100, 0x00000000, 
    3661             :   0x00080000, 0x00000000, // sub_32
    3662             : };
    3663             : 
    3664             : static const uint32_t WSeqPairsClassSubClassMask[] = {
    3665             :   0x00001e00, 0x00000000, 
    3666             :   0x0fe00000, 0x00000000, // sub_32_subo64_then_sub_32
    3667             : };
    3668             : 
    3669             : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask[] = {
    3670             :   0x00001400, 0x00000000, 
    3671             :   0x0b400000, 0x00000000, // sub_32_subo64_then_sub_32
    3672             : };
    3673             : 
    3674             : static const uint32_t WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
    3675             :   0x00001800, 0x00000000, 
    3676             :   0x0f800000, 0x00000000, // sub_32_subo64_then_sub_32
    3677             : };
    3678             : 
    3679             : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
    3680             :   0x00001000, 0x00000000, 
    3681             :   0x0b000000, 0x00000000, // sub_32_subo64_then_sub_32
    3682             : };
    3683             : 
    3684             : static const uint32_t GPR64allSubClassMask[] = {
    3685             :   0x000fa000, 0x00000000, 
    3686             :   0x0fe00000, 0x00000000, // sube64
    3687             :   0x0fe00000, 0x00000000, // subo64
    3688             : };
    3689             : 
    3690             : static const uint32_t FPR64SubClassMask[] = {
    3691             :   0x00004000, 0x00000000, 
    3692             :   0x30000000, 0x003fffff, // dsub
    3693             :   0xc0100000, 0x00000000, // dsub0
    3694             :   0xc0100000, 0x00000000, // dsub1
    3695             :   0xc0000000, 0x00000000, // dsub2
    3696             :   0x80000000, 0x00000000, // dsub3
    3697             :   0x00000000, 0x003fffff, // qsub1_then_dsub
    3698             :   0x00000000, 0x003ff800, // qsub3_then_dsub
    3699             :   0x00000000, 0x003ffff0, // qsub2_then_dsub
    3700             : };
    3701             : 
    3702             : static const uint32_t GPR64SubClassMask[] = {
    3703             :   0x00068000, 0x00000000, 
    3704             :   0x0fe00000, 0x00000000, // sube64
    3705             :   0x0fe00000, 0x00000000, // subo64
    3706             : };
    3707             : 
    3708             : static const uint32_t GPR64spSubClassMask[] = {
    3709             :   0x000f0000, 0x00000000, 
    3710             :   0x0b400000, 0x00000000, // sube64
    3711             :   0x0f800000, 0x00000000, // subo64
    3712             : };
    3713             : 
    3714             : static const uint32_t GPR64commonSubClassMask[] = {
    3715             :   0x00060000, 0x00000000, 
    3716             :   0x0b400000, 0x00000000, // sube64
    3717             :   0x0f800000, 0x00000000, // subo64
    3718             : };
    3719             : 
    3720             : static const uint32_t tcGPR64SubClassMask[] = {
    3721             :   0x00040000, 0x00000000, 
    3722             :   0x0a000000, 0x00000000, // sube64
    3723             :   0x0c000000, 0x00000000, // subo64
    3724             : };
    3725             : 
    3726             : static const uint32_t GPR64sponlySubClassMask[] = {
    3727             :   0x00080000, 0x00000000, 
    3728             : };
    3729             : 
    3730             : static const uint32_t DDSubClassMask[] = {
    3731             :   0x00100000, 0x00000000, 
    3732             :   0xc0000000, 0x00000000, // dsub0_dsub1
    3733             :   0xc0000000, 0x00000000, // dsub1_dsub2
    3734             :   0x80000000, 0x00000000, // dsub2_dsub3
    3735             :   0x00000000, 0x003fffff, // dsub_qsub1_then_dsub
    3736             :   0x00000000, 0x003ffff0, // qsub1_then_dsub_qsub2_then_dsub
    3737             :   0x00000000, 0x003ff800, // qsub2_then_dsub_qsub3_then_dsub
    3738             : };
    3739             : 
    3740             : static const uint32_t XSeqPairsClassSubClassMask[] = {
    3741             :   0x0fe00000, 0x00000000, 
    3742             : };
    3743             : 
    3744             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask[] = {
    3745             :   0x0b400000, 0x00000000, 
    3746             : };
    3747             : 
    3748             : static const uint32_t XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
    3749             :   0x0f800000, 0x00000000, 
    3750             : };
    3751             : 
    3752             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
    3753             :   0x0b000000, 0x00000000, 
    3754             : };
    3755             : 
    3756             : static const uint32_t XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask[] = {
    3757             :   0x0a000000, 0x00000000, 
    3758             : };
    3759             : 
    3760             : static const uint32_t XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
    3761             :   0x0c000000, 0x00000000, 
    3762             : };
    3763             : 
    3764             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
    3765             :   0x08000000, 0x00000000, 
    3766             : };
    3767             : 
    3768             : static const uint32_t FPR128SubClassMask[] = {
    3769             :   0x30000000, 0x00000000, 
    3770             :   0x00000000, 0x003fffff, // qsub0
    3771             :   0x00000000, 0x003fffff, // qsub1
    3772             :   0x00000000, 0x003ffff0, // qsub2
    3773             :   0x00000000, 0x003ff800, // qsub3
    3774             : };
    3775             : 
    3776             : static const uint32_t FPR128_loSubClassMask[] = {
    3777             :   0x20000000, 0x00000000, 
    3778             :   0x00000000, 0x0029152a, // qsub0
    3779             :   0x00000000, 0x003b274c, // qsub1
    3780             :   0x00000000, 0x003e4680, // qsub2
    3781             :   0x00000000, 0x00348000, // qsub3
    3782             : };
    3783             : 
    3784             : static const uint32_t DDDSubClassMask[] = {
    3785             :   0x40000000, 0x00000000, 
    3786             :   0x80000000, 0x00000000, // dsub0_dsub1_dsub2
    3787             :   0x80000000, 0x00000000, // dsub1_dsub2_dsub3
    3788             :   0x00000000, 0x003ffff0, // dsub_qsub1_then_dsub_qsub2_then_dsub
    3789             :   0x00000000, 0x003ff800, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    3790             : };
    3791             : 
    3792             : static const uint32_t DDDDSubClassMask[] = {
    3793             :   0x80000000, 0x00000000, 
    3794             :   0x00000000, 0x003ff800, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    3795             : };
    3796             : 
    3797             : static const uint32_t QQSubClassMask[] = {
    3798             :   0x00000000, 0x0000000f, 
    3799             :   0x00000000, 0x003ffff0, // qsub0_qsub1
    3800             :   0x00000000, 0x003ffff0, // qsub1_qsub2
    3801             :   0x00000000, 0x003ff800, // qsub2_qsub3
    3802             : };
    3803             : 
    3804             : static const uint32_t QQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    3805             :   0x00000000, 0x0000000a, 
    3806             :   0x00000000, 0x00291520, // qsub0_qsub1
    3807             :   0x00000000, 0x003b2740, // qsub1_qsub2
    3808             :   0x00000000, 0x003e4000, // qsub2_qsub3
    3809             : };
    3810             : 
    3811             : static const uint32_t QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    3812             :   0x00000000, 0x0000000c, 
    3813             :   0x00000000, 0x003b2740, // qsub0_qsub1
    3814             :   0x00000000, 0x003e4680, // qsub1_qsub2
    3815             :   0x00000000, 0x00348000, // qsub2_qsub3
    3816             : };
    3817             : 
    3818             : static const uint32_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    3819             :   0x00000000, 0x00000008, 
    3820             :   0x00000000, 0x00290500, // qsub0_qsub1
    3821             :   0x00000000, 0x003a0600, // qsub1_qsub2
    3822             :   0x00000000, 0x00340000, // qsub2_qsub3
    3823             : };
    3824             : 
    3825             : static const uint32_t QQQSubClassMask[] = {
    3826             :   0x00000000, 0x000007f0, 
    3827             :   0x00000000, 0x003ff800, // qsub0_qsub1_qsub2
    3828             :   0x00000000, 0x003ff800, // qsub1_qsub2_qsub3
    3829             : };
    3830             : 
    3831             : static const uint32_t QQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    3832             :   0x00000000, 0x00000520, 
    3833             :   0x00000000, 0x00291000, // qsub0_qsub1_qsub2
    3834             :   0x00000000, 0x003b2000, // qsub1_qsub2_qsub3
    3835             : };
    3836             : 
    3837             : static const uint32_t QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    3838             :   0x00000000, 0x00000740, 
    3839             :   0x00000000, 0x003b2000, // qsub0_qsub1_qsub2
    3840             :   0x00000000, 0x003e4000, // qsub1_qsub2_qsub3
    3841             : };
    3842             : 
    3843             : static const uint32_t QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    3844             :   0x00000000, 0x00000680, 
    3845             :   0x00000000, 0x003e4000, // qsub0_qsub1_qsub2
    3846             :   0x00000000, 0x00348000, // qsub1_qsub2_qsub3
    3847             : };
    3848             : 
    3849             : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    3850             :   0x00000000, 0x00000500, 
    3851             :   0x00000000, 0x00290000, // qsub0_qsub1_qsub2
    3852             :   0x00000000, 0x003a0000, // qsub1_qsub2_qsub3
    3853             : };
    3854             : 
    3855             : static const uint32_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    3856             :   0x00000000, 0x00000600, 
    3857             :   0x00000000, 0x003a0000, // qsub0_qsub1_qsub2
    3858             :   0x00000000, 0x00340000, // qsub1_qsub2_qsub3
    3859             : };
    3860             : 
    3861             : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    3862             :   0x00000000, 0x00000400, 
    3863             :   0x00000000, 0x00280000, // qsub0_qsub1_qsub2
    3864             :   0x00000000, 0x00300000, // qsub1_qsub2_qsub3
    3865             : };
    3866             : 
    3867             : static const uint32_t QQQQSubClassMask[] = {
    3868             :   0x00000000, 0x003ff800, 
    3869             : };
    3870             : 
    3871             : static const uint32_t QQQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    3872             :   0x00000000, 0x00291000, 
    3873             : };
    3874             : 
    3875             : static const uint32_t QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    3876             :   0x00000000, 0x003b2000, 
    3877             : };
    3878             : 
    3879             : static const uint32_t QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    3880             :   0x00000000, 0x003e4000, 
    3881             : };
    3882             : 
    3883             : static const uint32_t QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    3884             :   0x00000000, 0x00348000, 
    3885             : };
    3886             : 
    3887             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    3888             :   0x00000000, 0x00290000, 
    3889             : };
    3890             : 
    3891             : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    3892             :   0x00000000, 0x003a0000, 
    3893             : };
    3894             : 
    3895             : static const uint32_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    3896             :   0x00000000, 0x00340000, 
    3897             : };
    3898             : 
    3899             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    3900             :   0x00000000, 0x00280000, 
    3901             : };
    3902             : 
    3903             : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    3904             :   0x00000000, 0x00300000, 
    3905             : };
    3906             : 
    3907             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    3908             :   0x00000000, 0x00200000, 
    3909             : };
    3910             : 
    3911             : static const uint16_t SuperRegIdxSeqs[] = {
    3912             :   /* 0 */ 10, 11, 12, 13, 0,
    3913             :   /* 5 */ 15, 0,
    3914             :   /* 7 */ 17, 19, 0,
    3915             :   /* 10 */ 1, 20, 23, 26, 29, 33, 37, 0,
    3916             :   /* 18 */ 2, 3, 4, 5, 6, 30, 34, 38, 0,
    3917             :   /* 27 */ 7, 21, 24, 27, 31, 35, 39, 0,
    3918             :   /* 35 */ 14, 22, 25, 28, 32, 36, 40, 0,
    3919             :   /* 43 */ 15, 16, 18, 41, 0,
    3920             :   /* 48 */ 48, 0,
    3921             :   /* 50 */ 51, 53, 0,
    3922             :   /* 53 */ 50, 52, 54, 0,
    3923             :   /* 57 */ 43, 45, 49, 56, 0,
    3924             :   /* 62 */ 42, 44, 46, 47, 55, 57, 0,
    3925             :   /* 69 */ 58, 0,
    3926             : };
    3927             : 
    3928             : static const TargetRegisterClass *const GPR32Superclasses[] = {
    3929             :   &AArch64::GPR32allRegClass,
    3930             :   nullptr
    3931             : };
    3932             : 
    3933             : static const TargetRegisterClass *const GPR32spSuperclasses[] = {
    3934             :   &AArch64::GPR32allRegClass,
    3935             :   nullptr
    3936             : };
    3937             : 
    3938             : static const TargetRegisterClass *const GPR32commonSuperclasses[] = {
    3939             :   &AArch64::GPR32allRegClass,
    3940             :   &AArch64::GPR32RegClass,
    3941             :   &AArch64::GPR32spRegClass,
    3942             :   nullptr
    3943             : };
    3944             : 
    3945             : static const TargetRegisterClass *const GPR32sponlySuperclasses[] = {
    3946             :   &AArch64::GPR32allRegClass,
    3947             :   &AArch64::GPR32spRegClass,
    3948             :   nullptr
    3949             : };
    3950             : 
    3951             : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses[] = {
    3952             :   &AArch64::WSeqPairsClassRegClass,
    3953             :   nullptr
    3954             : };
    3955             : 
    3956             : static const TargetRegisterClass *const WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
    3957             :   &AArch64::WSeqPairsClassRegClass,
    3958             :   nullptr
    3959             : };
    3960             : 
    3961             : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
    3962             :   &AArch64::WSeqPairsClassRegClass,
    3963             :   &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
    3964             :   &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    3965             :   nullptr
    3966             : };
    3967             : 
    3968             : static const TargetRegisterClass *const GPR64Superclasses[] = {
    3969             :   &AArch64::GPR64allRegClass,
    3970             :   nullptr
    3971             : };
    3972             : 
    3973             : static const TargetRegisterClass *const GPR64spSuperclasses[] = {
    3974             :   &AArch64::GPR64allRegClass,
    3975             :   nullptr
    3976             : };
    3977             : 
    3978             : static const TargetRegisterClass *const GPR64commonSuperclasses[] = {
    3979             :   &AArch64::GPR64allRegClass,
    3980             :   &AArch64::GPR64RegClass,
    3981             :   &AArch64::GPR64spRegClass,
    3982             :   nullptr
    3983             : };
    3984             : 
    3985             : static const TargetRegisterClass *const tcGPR64Superclasses[] = {
    3986             :   &AArch64::GPR64allRegClass,
    3987             :   &AArch64::GPR64RegClass,
    3988             :   &AArch64::GPR64spRegClass,
    3989             :   &AArch64::GPR64commonRegClass,
    3990             :   nullptr
    3991             : };
    3992             : 
    3993             : static const TargetRegisterClass *const GPR64sponlySuperclasses[] = {
    3994             :   &AArch64::GPR64allRegClass,
    3995             :   &AArch64::GPR64spRegClass,
    3996             :   nullptr
    3997             : };
    3998             : 
    3999             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses[] = {
    4000             :   &AArch64::XSeqPairsClassRegClass,
    4001             :   nullptr
    4002             : };
    4003             : 
    4004             : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
    4005             :   &AArch64::XSeqPairsClassRegClass,
    4006             :   nullptr
    4007             : };
    4008             : 
    4009             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
    4010             :   &AArch64::XSeqPairsClassRegClass,
    4011             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    4012             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4013             :   nullptr
    4014             : };
    4015             : 
    4016             : static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_tcGPR64Superclasses[] = {
    4017             :   &AArch64::XSeqPairsClassRegClass,
    4018             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    4019             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4020             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4021             :   nullptr
    4022             : };
    4023             : 
    4024             : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
    4025             :   &AArch64::XSeqPairsClassRegClass,
    4026             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4027             :   nullptr
    4028             : };
    4029             : 
    4030             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
    4031             :   &AArch64::XSeqPairsClassRegClass,
    4032             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    4033             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4034             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4035             :   &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
    4036             :   &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    4037             :   nullptr
    4038             : };
    4039             : 
    4040             : static const TargetRegisterClass *const FPR128_loSuperclasses[] = {
    4041             :   &AArch64::FPR128RegClass,
    4042             :   nullptr
    4043             : };
    4044             : 
    4045             : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    4046             :   &AArch64::QQRegClass,
    4047             :   nullptr
    4048             : };
    4049             : 
    4050             : static const TargetRegisterClass *const QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4051             :   &AArch64::QQRegClass,
    4052             :   nullptr
    4053             : };
    4054             : 
    4055             : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4056             :   &AArch64::QQRegClass,
    4057             :   &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
    4058             :   &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
    4059             :   nullptr
    4060             : };
    4061             : 
    4062             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    4063             :   &AArch64::QQQRegClass,
    4064             :   nullptr
    4065             : };
    4066             : 
    4067             : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4068             :   &AArch64::QQQRegClass,
    4069             :   nullptr
    4070             : };
    4071             : 
    4072             : static const TargetRegisterClass *const QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4073             :   &AArch64::QQQRegClass,
    4074             :   nullptr
    4075             : };
    4076             : 
    4077             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4078             :   &AArch64::QQQRegClass,
    4079             :   &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    4080             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    4081             :   nullptr
    4082             : };
    4083             : 
    4084             : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4085             :   &AArch64::QQQRegClass,
    4086             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    4087             :   &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    4088             :   nullptr
    4089             : };
    4090             : 
    4091             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4092             :   &AArch64::QQQRegClass,
    4093             :   &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    4094             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    4095             :   &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    4096             :   &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
    4097             :   &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    4098             :   nullptr
    4099             : };
    4100             : 
    4101             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    4102             :   &AArch64::QQQQRegClass,
    4103             :   nullptr
    4104             : };
    4105             : 
    4106             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4107             :   &AArch64::QQQQRegClass,
    4108             :   nullptr
    4109             : };
    4110             : 
    4111             : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4112             :   &AArch64::QQQQRegClass,
    4113             :   nullptr
    4114             : };
    4115             : 
    4116             : static const TargetRegisterClass *const QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    4117             :   &AArch64::QQQQRegClass,
    4118             :   nullptr
    4119             : };
    4120             : 
    4121             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4122             :   &AArch64::QQQQRegClass,
    4123             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    4124             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4125             :   nullptr
    4126             : };
    4127             : 
    4128             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4129             :   &AArch64::QQQQRegClass,
    4130             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4131             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4132             :   nullptr
    4133             : };
    4134             : 
    4135             : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    4136             :   &AArch64::QQQQRegClass,
    4137             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4138             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    4139             :   nullptr
    4140             : };
    4141             : 
    4142             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4143             :   &AArch64::QQQQRegClass,
    4144             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    4145             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4146             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4147             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    4148             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    4149             :   nullptr
    4150             : };
    4151             : 
    4152             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    4153             :   &AArch64::QQQQRegClass,
    4154             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4155             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4156             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    4157             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    4158             :   &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    4159             :   nullptr
    4160             : };
    4161             : 
    4162             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    4163             :   &AArch64::QQQQRegClass,
    4164             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    4165             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4166             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4167             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    4168             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    4169             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    4170             :   &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    4171             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    4172             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    4173             :   nullptr
    4174             : };
    4175             : 
    4176             : 
    4177             : static inline unsigned GPR32AltOrderSelect(const MachineFunction &MF) { return 1; }
    4178             : 
    4179         520 : static ArrayRef<MCPhysReg> GPR32GetRawAllocationOrder(const MachineFunction &MF) {
    4180             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    4181         520 :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
    4182             :   const ArrayRef<MCPhysReg> Order[] = {
    4183         520 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4184             :     makeArrayRef(AltOrder1)
    4185        1040 :   };
    4186         520 :   const unsigned Select = GPR32AltOrderSelect(MF);
    4187             :   assert(Select < 2);
    4188         520 :   return Order[Select];
    4189             : }
    4190             : 
    4191             : static inline unsigned GPR32spAltOrderSelect(const MachineFunction &MF) { return 1; }
    4192             : 
    4193          81 : static ArrayRef<MCPhysReg> GPR32spGetRawAllocationOrder(const MachineFunction &MF) {
    4194             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    4195          81 :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
    4196             :   const ArrayRef<MCPhysReg> Order[] = {
    4197          81 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4198             :     makeArrayRef(AltOrder1)
    4199         162 :   };
    4200          81 :   const unsigned Select = GPR32spAltOrderSelect(MF);
    4201             :   assert(Select < 2);
    4202          81 :   return Order[Select];
    4203             : }
    4204             : 
    4205             : static inline unsigned GPR32commonAltOrderSelect(const MachineFunction &MF) { return 1; }
    4206             : 
    4207         199 : static ArrayRef<MCPhysReg> GPR32commonGetRawAllocationOrder(const MachineFunction &MF) {
    4208             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    4209         199 :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];
    4210             :   const ArrayRef<MCPhysReg> Order[] = {
    4211         199 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4212             :     makeArrayRef(AltOrder1)
    4213         398 :   };
    4214         199 :   const unsigned Select = GPR32commonAltOrderSelect(MF);
    4215             :   assert(Select < 2);
    4216         199 :   return Order[Select];
    4217             : }
    4218             : 
    4219             : static inline unsigned GPR64AltOrderSelect(const MachineFunction &MF) { return 1; }
    4220             : 
    4221         690 : static ArrayRef<MCPhysReg> GPR64GetRawAllocationOrder(const MachineFunction &MF) {
    4222             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    4223         690 :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
    4224             :   const ArrayRef<MCPhysReg> Order[] = {
    4225         690 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4226             :     makeArrayRef(AltOrder1)
    4227        1380 :   };
    4228         690 :   const unsigned Select = GPR64AltOrderSelect(MF);
    4229             :   assert(Select < 2);
    4230         690 :   return Order[Select];
    4231             : }
    4232             : 
    4233             : static inline unsigned GPR64spAltOrderSelect(const MachineFunction &MF) { return 1; }
    4234             : 
    4235         163 : static ArrayRef<MCPhysReg> GPR64spGetRawAllocationOrder(const MachineFunction &MF) {
    4236             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    4237         163 :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];
    4238             :   const ArrayRef<MCPhysReg> Order[] = {
    4239         163 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4240             :     makeArrayRef(AltOrder1)
    4241         326 :   };
    4242         163 :   const unsigned Select = GPR64spAltOrderSelect(MF);
    4243             :   assert(Select < 2);
    4244         163 :   return Order[Select];
    4245             : }
    4246             : 
    4247             : static inline unsigned GPR64commonAltOrderSelect(const MachineFunction &MF) { return 1; }
    4248             : 
    4249         682 : static ArrayRef<MCPhysReg> GPR64commonGetRawAllocationOrder(const MachineFunction &MF) {
    4250             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    4251         682 :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID];
    4252             :   const ArrayRef<MCPhysReg> Order[] = {
    4253         682 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4254             :     makeArrayRef(AltOrder1)
    4255        1364 :   };
    4256         682 :   const unsigned Select = GPR64commonAltOrderSelect(MF);
    4257             :   assert(Select < 2);
    4258         682 :   return Order[Select];
    4259             : }
    4260             : 
    4261             : namespace AArch64 {   // Register class instances
    4262             :   extern const TargetRegisterClass FPR8RegClass = {
    4263             :     &AArch64MCRegisterClasses[FPR8RegClassID],
    4264             :     1, /* SpillSize */
    4265             :     1, /* SpillAlignment */
    4266             :     VTLists + 34,
    4267             :     FPR8SubClassMask,
    4268             :     SuperRegIdxSeqs + 10,
    4269             :     LaneBitmask(0x00000001),
    4270             :     0,
    4271             :     false, /* HasDisjunctSubRegs */
    4272             :     false, /* CoveredBySubRegs */
    4273             :     NullRegClasses,
    4274             :     nullptr
    4275             :   };
    4276             : 
    4277             :   extern const TargetRegisterClass FPR16RegClass = {
    4278             :     &AArch64MCRegisterClasses[FPR16RegClassID],
    4279             :     2, /* SpillSize */
    4280             :     2, /* SpillAlignment */
    4281             :     VTLists + 5,
    4282             :     FPR16SubClassMask,
    4283             :     SuperRegIdxSeqs + 27,
    4284             :     LaneBitmask(0x00000001),
    4285             :     0,
    4286             :     false, /* HasDisjunctSubRegs */
    4287             :     false, /* CoveredBySubRegs */
    4288             :     NullRegClasses,
    4289             :     nullptr
    4290             :   };
    4291             : 
    4292             :   extern const TargetRegisterClass GPR32allRegClass = {
    4293             :     &AArch64MCRegisterClasses[GPR32allRegClassID],
    4294             :     4, /* SpillSize */
    4295             :     4, /* SpillAlignment */
    4296             :     VTLists + 1,
    4297             :     GPR32allSubClassMask,
    4298             :     SuperRegIdxSeqs + 43,
    4299             :     LaneBitmask(0x00000001),
    4300             :     0,
    4301             :     false, /* HasDisjunctSubRegs */
    4302             :     false, /* CoveredBySubRegs */
    4303             :     NullRegClasses,
    4304             :     nullptr
    4305             :   };
    4306             : 
    4307             :   extern const TargetRegisterClass FPR32RegClass = {
    4308             :     &AArch64MCRegisterClasses[FPR32RegClassID],
    4309             :     4, /* SpillSize */
    4310             :     4, /* SpillAlignment */
    4311             :     VTLists + 0,
    4312             :     FPR32SubClassMask,
    4313             :     SuperRegIdxSeqs + 35,
    4314             :     LaneBitmask(0x00000001),
    4315             :     0,
    4316             :     false, /* HasDisjunctSubRegs */
    4317             :     false, /* CoveredBySubRegs */
    4318             :     NullRegClasses,
    4319             :     nullptr
    4320             :   };
    4321             : 
    4322             :   extern const TargetRegisterClass GPR32RegClass = {
    4323             :     &AArch64MCRegisterClasses[GPR32RegClassID],
    4324             :     4, /* SpillSize */
    4325             :     4, /* SpillAlignment */
    4326             :     VTLists + 1,
    4327             :     GPR32SubClassMask,
    4328             :     SuperRegIdxSeqs + 43,
    4329             :     LaneBitmask(0x00000001),
    4330             :     0,
    4331             :     false, /* HasDisjunctSubRegs */
    4332             :     false, /* CoveredBySubRegs */
    4333             :     GPR32Superclasses,
    4334             :     GPR32GetRawAllocationOrder
    4335             :   };
    4336             : 
    4337             :   extern const TargetRegisterClass GPR32spRegClass = {
    4338             :     &AArch64MCRegisterClasses[GPR32spRegClassID],
    4339             :     4, /* SpillSize */
    4340             :     4, /* SpillAlignment */
    4341             :     VTLists + 1,
    4342             :     GPR32spSubClassMask,
    4343             :     SuperRegIdxSeqs + 43,
    4344             :     LaneBitmask(0x00000001),
    4345             :     0,
    4346             :     false, /* HasDisjunctSubRegs */
    4347             :     false, /* CoveredBySubRegs */
    4348             :     GPR32spSuperclasses,
    4349             :     GPR32spGetRawAllocationOrder
    4350             :   };
    4351             : 
    4352             :   extern const TargetRegisterClass GPR32commonRegClass = {
    4353             :     &AArch64MCRegisterClasses[GPR32commonRegClassID],
    4354             :     4, /* SpillSize */
    4355             :     4, /* SpillAlignment */
    4356             :     VTLists + 1,
    4357             :     GPR32commonSubClassMask,
    4358             :     SuperRegIdxSeqs + 43,
    4359             :     LaneBitmask(0x00000001),
    4360             :     0,
    4361             :     false, /* HasDisjunctSubRegs */
    4362             :     false, /* CoveredBySubRegs */
    4363             :     GPR32commonSuperclasses,
    4364             :     GPR32commonGetRawAllocationOrder
    4365             :   };
    4366             : 
    4367             :   extern const TargetRegisterClass CCRRegClass = {
    4368             :     &AArch64MCRegisterClasses[CCRRegClassID],
    4369             :     4, /* SpillSize */
    4370             :     4, /* SpillAlignment */
    4371             :     VTLists + 1,
    4372             :     CCRSubClassMask,
    4373             :     SuperRegIdxSeqs + 4,
    4374             :     LaneBitmask(0x00000001),
    4375             :     0,
    4376             :     false, /* HasDisjunctSubRegs */
    4377             :     false, /* CoveredBySubRegs */
    4378             :     NullRegClasses,
    4379             :     nullptr
    4380             :   };
    4381             : 
    4382             :   extern const TargetRegisterClass GPR32sponlyRegClass = {
    4383             :     &AArch64MCRegisterClasses[GPR32sponlyRegClassID],
    4384             :     4, /* SpillSize */
    4385             :     4, /* SpillAlignment */
    4386             :     VTLists + 1,
    4387             :     GPR32sponlySubClassMask,
    4388             :     SuperRegIdxSeqs + 5,
    4389             :     LaneBitmask(0x00000001),
    4390             :     0,
    4391             :     false, /* HasDisjunctSubRegs */
    4392             :     false, /* CoveredBySubRegs */
    4393             :     GPR32sponlySuperclasses,
    4394             :     nullptr
    4395             :   };
    4396             : 
    4397             :   extern const TargetRegisterClass WSeqPairsClassRegClass = {
    4398             :     &AArch64MCRegisterClasses[WSeqPairsClassRegClassID],
    4399             :     8, /* SpillSize */
    4400             :     4, /* SpillAlignment */
    4401             :     VTLists + 34,
    4402             :     WSeqPairsClassSubClassMask,
    4403             :     SuperRegIdxSeqs + 69,
    4404             :     LaneBitmask(0x00000030),
    4405             :     0,
    4406             :     true, /* HasDisjunctSubRegs */
    4407             :     true, /* CoveredBySubRegs */
    4408             :     NullRegClasses,
    4409             :     nullptr
    4410             :   };
    4411             : 
    4412             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass = {
    4413             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32commonRegClassID],
    4414             :     8, /* SpillSize */
    4415             :     4, /* SpillAlignment */
    4416             :     VTLists + 34,
    4417             :     WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask,
    4418             :     SuperRegIdxSeqs + 69,
    4419             :     LaneBitmask(0x00000030),
    4420             :     0,
    4421             :     true, /* HasDisjunctSubRegs */
    4422             :     true, /* CoveredBySubRegs */
    4423             :     WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses,
    4424             :     nullptr
    4425             :   };
    4426             : 
    4427             :   extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
    4428             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
    4429             :     8, /* SpillSize */
    4430             :     4, /* SpillAlignment */
    4431             :     VTLists + 34,
    4432             :     WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
    4433             :     SuperRegIdxSeqs + 69,
    4434             :     LaneBitmask(0x00000030),
    4435             :     0,
    4436             :     true, /* HasDisjunctSubRegs */
    4437             :     true, /* CoveredBySubRegs */
    4438             :     WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
    4439             :     nullptr
    4440             :   };
    4441             : 
    4442             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
    4443             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
    4444             :     8, /* SpillSize */
    4445             :     4, /* SpillAlignment */
    4446             :     VTLists + 34,
    4447             :     WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
    4448             :     SuperRegIdxSeqs + 69,
    4449             :     LaneBitmask(0x00000030),
    4450             :     0,
    4451             :     true, /* HasDisjunctSubRegs */
    4452             :     true, /* CoveredBySubRegs */
    4453             :     WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
    4454             :     nullptr
    4455             :   };
    4456             : 
    4457             :   extern const TargetRegisterClass GPR64allRegClass = {
    4458             :     &AArch64MCRegisterClasses[GPR64allRegClassID],
    4459             :     8, /* SpillSize */
    4460             :     8, /* SpillAlignment */
    4461             :     VTLists + 3,
    4462             :     GPR64allSubClassMask,
    4463             :     SuperRegIdxSeqs + 7,
    4464             :     LaneBitmask(0x00000008),
    4465             :     0,
    4466             :     false, /* HasDisjunctSubRegs */
    4467             :     false, /* CoveredBySubRegs */
    4468             :     NullRegClasses,
    4469             :     nullptr
    4470             :   };
    4471             : 
    4472             :   extern const TargetRegisterClass FPR64RegClass = {
    4473             :     &AArch64MCRegisterClasses[FPR64RegClassID],
    4474             :     8, /* SpillSize */
    4475             :     8, /* SpillAlignment */
    4476             :     VTLists + 7,
    4477             :     FPR64SubClassMask,
    4478             :     SuperRegIdxSeqs + 18,
    4479             :     LaneBitmask(0x00000001),
    4480             :     0,
    4481             :     false, /* HasDisjunctSubRegs */
    4482             :     false, /* CoveredBySubRegs */
    4483             :     NullRegClasses,
    4484             :     nullptr
    4485             :   };
    4486             : 
    4487             :   extern const TargetRegisterClass GPR64RegClass = {
    4488             :     &AArch64MCRegisterClasses[GPR64RegClassID],
    4489             :     8, /* SpillSize */
    4490             :     8, /* SpillAlignment */
    4491             :     VTLists + 3,
    4492             :     GPR64SubClassMask,
    4493             :     SuperRegIdxSeqs + 7,
    4494             :     LaneBitmask(0x00000008),
    4495             :     0,
    4496             :     false, /* HasDisjunctSubRegs */
    4497             :     false, /* CoveredBySubRegs */
    4498             :     GPR64Superclasses,
    4499             :     GPR64GetRawAllocationOrder
    4500             :   };
    4501             : 
    4502             :   extern const TargetRegisterClass GPR64spRegClass = {
    4503             :     &AArch64MCRegisterClasses[GPR64spRegClassID],
    4504             :     8, /* SpillSize */
    4505             :     8, /* SpillAlignment */
    4506             :     VTLists + 3,
    4507             :     GPR64spSubClassMask,
    4508             :     SuperRegIdxSeqs + 7,
    4509             :     LaneBitmask(0x00000008),
    4510             :     0,
    4511             :     false, /* HasDisjunctSubRegs */
    4512             :     false, /* CoveredBySubRegs */
    4513             :     GPR64spSuperclasses,
    4514             :     GPR64spGetRawAllocationOrder
    4515             :   };
    4516             : 
    4517             :   extern const TargetRegisterClass GPR64commonRegClass = {
    4518             :     &AArch64MCRegisterClasses[GPR64commonRegClassID],
    4519             :     8, /* SpillSize */
    4520             :     8, /* SpillAlignment */
    4521             :     VTLists + 3,
    4522             :     GPR64commonSubClassMask,
    4523             :     SuperRegIdxSeqs + 7,
    4524             :     LaneBitmask(0x00000008),
    4525             :     0,
    4526             :     false, /* HasDisjunctSubRegs */
    4527             :     false, /* CoveredBySubRegs */
    4528             :     GPR64commonSuperclasses,
    4529             :     GPR64commonGetRawAllocationOrder
    4530             :   };
    4531             : 
    4532             :   extern const TargetRegisterClass tcGPR64RegClass = {
    4533             :     &AArch64MCRegisterClasses[tcGPR64RegClassID],
    4534             :     8, /* SpillSize */
    4535             :     8, /* SpillAlignment */
    4536             :     VTLists + 3,
    4537             :     tcGPR64SubClassMask,
    4538             :     SuperRegIdxSeqs + 7,
    4539             :     LaneBitmask(0x00000008),
    4540             :     0,
    4541             :     false, /* HasDisjunctSubRegs */
    4542             :     false, /* CoveredBySubRegs */
    4543             :     tcGPR64Superclasses,
    4544             :     nullptr
    4545             :   };
    4546             : 
    4547             :   extern const TargetRegisterClass GPR64sponlyRegClass = {
    4548             :     &AArch64MCRegisterClasses[GPR64sponlyRegClassID],
    4549             :     8, /* SpillSize */
    4550             :     8, /* SpillAlignment */
    4551             :     VTLists + 3,
    4552             :     GPR64sponlySubClassMask,
    4553             :     SuperRegIdxSeqs + 4,
    4554             :     LaneBitmask(0x00000008),
    4555             :     0,
    4556             :     false, /* HasDisjunctSubRegs */
    4557             :     false, /* CoveredBySubRegs */
    4558             :     GPR64sponlySuperclasses,
    4559             :     nullptr
    4560             :   };
    4561             : 
    4562             :   extern const TargetRegisterClass DDRegClass = {
    4563             :     &AArch64MCRegisterClasses[DDRegClassID],
    4564             :     16, /* SpillSize */
    4565             :     8, /* SpillAlignment */
    4566             :     VTLists + 34,
    4567             :     DDSubClassMask,
    4568             :     SuperRegIdxSeqs + 62,
    4569             :     LaneBitmask(0x00000041),
    4570             :     0,
    4571             :     true, /* HasDisjunctSubRegs */
    4572             :     true, /* CoveredBySubRegs */
    4573             :     NullRegClasses,
    4574             :     nullptr
    4575             :   };
    4576             : 
    4577             :   extern const TargetRegisterClass XSeqPairsClassRegClass = {
    4578             :     &AArch64MCRegisterClasses[XSeqPairsClassRegClassID],
    4579             :     16, /* SpillSize */
    4580             :     8, /* SpillAlignment */
    4581             :     VTLists + 34,
    4582             :     XSeqPairsClassSubClassMask,
    4583             :     SuperRegIdxSeqs + 4,
    4584             :     LaneBitmask(0x00001008),
    4585             :     0,
    4586             :     true, /* HasDisjunctSubRegs */
    4587             :     true, /* CoveredBySubRegs */
    4588             :     NullRegClasses,
    4589             :     nullptr
    4590             :   };
    4591             : 
    4592             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass = {
    4593             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID],
    4594             :     16, /* SpillSize */
    4595             :     8, /* SpillAlignment */
    4596             :     VTLists + 34,
    4597             :     XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask,
    4598             :     SuperRegIdxSeqs + 4,
    4599             :     LaneBitmask(0x00001008),
    4600             :     0,
    4601             :     true, /* HasDisjunctSubRegs */
    4602             :     true, /* CoveredBySubRegs */
    4603             :     XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses,
    4604             :     nullptr
    4605             :   };
    4606             : 
    4607             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
    4608             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
    4609             :     16, /* SpillSize */
    4610             :     8, /* SpillAlignment */
    4611             :     VTLists + 34,
    4612             :     XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
    4613             :     SuperRegIdxSeqs + 4,
    4614             :     LaneBitmask(0x00001008),
    4615             :     0,
    4616             :     true, /* HasDisjunctSubRegs */
    4617             :     true, /* CoveredBySubRegs */
    4618             :     XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
    4619             :     nullptr
    4620             :   };
    4621             : 
    4622             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
    4623             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
    4624             :     16, /* SpillSize */
    4625             :     8, /* SpillAlignment */
    4626             :     VTLists + 34,
    4627             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
    4628             :     SuperRegIdxSeqs + 4,
    4629             :     LaneBitmask(0x00001008),
    4630             :     0,
    4631             :     true, /* HasDisjunctSubRegs */
    4632             :     true, /* CoveredBySubRegs */
    4633             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
    4634             :     nullptr
    4635             :   };
    4636             : 
    4637             :   extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass = {
    4638             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_tcGPR64RegClassID],
    4639             :     16, /* SpillSize */
    4640             :     8, /* SpillAlignment */
    4641             :     VTLists + 34,
    4642             :     XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask,
    4643             :     SuperRegIdxSeqs + 4,
    4644             :     LaneBitmask(0x00001008),
    4645             :     0,
    4646             :     true, /* HasDisjunctSubRegs */
    4647             :     true, /* CoveredBySubRegs */
    4648             :     XSeqPairsClass_with_sube64_in_tcGPR64Superclasses,
    4649             :     nullptr
    4650             :   };
    4651             : 
    4652             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
    4653             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
    4654             :     16, /* SpillSize */
    4655             :     8, /* SpillAlignment */
    4656             :     VTLists + 34,
    4657             :     XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
    4658             :     SuperRegIdxSeqs + 4,
    4659             :     LaneBitmask(0x00001008),
    4660             :     0,
    4661             :     true, /* HasDisjunctSubRegs */
    4662             :     true, /* CoveredBySubRegs */
    4663             :     XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
    4664             :     nullptr
    4665             :   };
    4666             : 
    4667             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
    4668             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
    4669             :     16, /* SpillSize */
    4670             :     8, /* SpillAlignment */
    4671             :     VTLists + 34,
    4672             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
    4673             :     SuperRegIdxSeqs + 4,
    4674             :     LaneBitmask(0x00001008),
    4675             :     0,
    4676             :     true, /* HasDisjunctSubRegs */
    4677             :     true, /* CoveredBySubRegs */
    4678             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
    4679             :     nullptr
    4680             :   };
    4681             : 
    4682             :   extern const TargetRegisterClass FPR128RegClass = {
    4683             :     &AArch64MCRegisterClasses[FPR128RegClassID],
    4684             :     16, /* SpillSize */
    4685             :     16, /* SpillAlignment */
    4686             :     VTLists + 17,
    4687             :     FPR128SubClassMask,
    4688             :     SuperRegIdxSeqs + 0,
    4689             :     LaneBitmask(0x00000001),
    4690             :     0,
    4691             :     false, /* HasDisjunctSubRegs */
    4692             :     false, /* CoveredBySubRegs */
    4693             :     NullRegClasses,
    4694             :     nullptr
    4695             :   };
    4696             : 
    4697             :   extern const TargetRegisterClass FPR128_loRegClass = {
    4698             :     &AArch64MCRegisterClasses[FPR128_loRegClassID],
    4699             :     16, /* SpillSize */
    4700             :     16, /* SpillAlignment */
    4701             :     VTLists + 26,
    4702             :     FPR128_loSubClassMask,
    4703             :     SuperRegIdxSeqs + 0,
    4704             :     LaneBitmask(0x00000001),
    4705             :     0,
    4706             :     false, /* HasDisjunctSubRegs */
    4707             :     false, /* CoveredBySubRegs */
    4708             :     FPR128_loSuperclasses,
    4709             :     nullptr
    4710             :   };
    4711             : 
    4712             :   extern const TargetRegisterClass DDDRegClass = {
    4713             :     &AArch64MCRegisterClasses[DDDRegClassID],
    4714             :     24, /* SpillSize */
    4715             :     8, /* SpillAlignment */
    4716             :     VTLists + 34,
    4717             :     DDDSubClassMask,
    4718             :     SuperRegIdxSeqs + 57,
    4719             :     LaneBitmask(0x00000141),
    4720             :     0,
    4721             :     true, /* HasDisjunctSubRegs */
    4722             :     true, /* CoveredBySubRegs */
    4723             :     NullRegClasses,
    4724             :     nullptr
    4725             :   };
    4726             : 
    4727             :   extern const TargetRegisterClass DDDDRegClass = {
    4728             :     &AArch64MCRegisterClasses[DDDDRegClassID],
    4729             :     32, /* SpillSize */
    4730             :     8, /* SpillAlignment */
    4731             :     VTLists + 34,
    4732             :     DDDDSubClassMask,
    4733             :     SuperRegIdxSeqs + 48,
    4734             :     LaneBitmask(0x000001C1),
    4735             :     0,
    4736             :     true, /* HasDisjunctSubRegs */
    4737             :     true, /* CoveredBySubRegs */
    4738             :     NullRegClasses,
    4739             :     nullptr
    4740             :   };
    4741             : 
    4742             :   extern const TargetRegisterClass QQRegClass = {
    4743             :     &AArch64MCRegisterClasses[QQRegClassID],
    4744             :     32, /* SpillSize */
    4745             :     16, /* SpillAlignment */
    4746             :     VTLists + 34,
    4747             :     QQSubClassMask,
    4748             :     SuperRegIdxSeqs + 53,
    4749             :     LaneBitmask(0x00000201),
    4750             :     0,
    4751             :     true, /* HasDisjunctSubRegs */
    4752             :     true, /* CoveredBySubRegs */
    4753             :     NullRegClasses,
    4754             :     nullptr
    4755             :   };
    4756             : 
    4757             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass = {
    4758             :     &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_loRegClassID],
    4759             :     32, /* SpillSize */
    4760             :     16, /* SpillAlignment */
    4761             :     VTLists + 34,
    4762             :     QQ_with_qsub0_in_FPR128_loSubClassMask,
    4763             :     SuperRegIdxSeqs + 53,
    4764             :     LaneBitmask(0x00000201),
    4765             :     0,
    4766             :     true, /* HasDisjunctSubRegs */
    4767             :     true, /* CoveredBySubRegs */
    4768             :     QQ_with_qsub0_in_FPR128_loSuperclasses,
    4769             :     nullptr
    4770             :   };
    4771             : 
    4772             :   extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass = {
    4773             :     &AArch64MCRegisterClasses[QQ_with_qsub1_in_FPR128_loRegClassID],
    4774             :     32, /* SpillSize */
    4775             :     16, /* SpillAlignment */
    4776             :     VTLists + 34,
    4777             :     QQ_with_qsub1_in_FPR128_loSubClassMask,
    4778             :     SuperRegIdxSeqs + 53,
    4779             :     LaneBitmask(0x00000201),
    4780             :     0,
    4781             :     true, /* HasDisjunctSubRegs */
    4782             :     true, /* CoveredBySubRegs */
    4783             :     QQ_with_qsub1_in_FPR128_loSuperclasses,
    4784             :     nullptr
    4785             :   };
    4786             : 
    4787             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass = {
    4788             :     &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID],
    4789             :     32, /* SpillSize */
    4790             :     16, /* SpillAlignment */
    4791             :     VTLists + 34,
    4792             :     QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask,
    4793             :     SuperRegIdxSeqs + 53,
    4794             :     LaneBitmask(0x00000201),
    4795             :     0,
    4796             :     true, /* HasDisjunctSubRegs */
    4797             :     true, /* CoveredBySubRegs */
    4798             :     QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses,
    4799             :     nullptr
    4800             :   };
    4801             : 
    4802             :   extern const TargetRegisterClass QQQRegClass = {
    4803             :     &AArch64MCRegisterClasses[QQQRegClassID],
    4804             :     48, /* SpillSize */
    4805             :     16, /* SpillAlignment */
    4806             :     VTLists + 34,
    4807             :     QQQSubClassMask,
    4808             :     SuperRegIdxSeqs + 50,
    4809             :     LaneBitmask(0x00000A01),
    4810             :     0,
    4811             :     true, /* HasDisjunctSubRegs */
    4812             :     true, /* CoveredBySubRegs */
    4813             :     NullRegClasses,
    4814             :     nullptr
    4815             :   };
    4816             : 
    4817             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass = {
    4818             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_loRegClassID],
    4819             :     48, /* SpillSize */
    4820             :     16, /* SpillAlignment */
    4821             :     VTLists + 34,
    4822             :     QQQ_with_qsub0_in_FPR128_loSubClassMask,
    4823             :     SuperRegIdxSeqs + 50,
    4824             :     LaneBitmask(0x00000A01),
    4825             :     0,
    4826             :     true, /* HasDisjunctSubRegs */
    4827             :     true, /* CoveredBySubRegs */
    4828             :     QQQ_with_qsub0_in_FPR128_loSuperclasses,
    4829             :     nullptr
    4830             :   };
    4831             : 
    4832             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass = {
    4833             :     &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_loRegClassID],
    4834             :     48, /* SpillSize */
    4835             :     16, /* SpillAlignment */
    4836             :     VTLists + 34,
    4837             :     QQQ_with_qsub1_in_FPR128_loSubClassMask,
    4838             :     SuperRegIdxSeqs + 50,
    4839             :     LaneBitmask(0x00000A01),
    4840             :     0,
    4841             :     true, /* HasDisjunctSubRegs */
    4842             :     true, /* CoveredBySubRegs */
    4843             :     QQQ_with_qsub1_in_FPR128_loSuperclasses,
    4844             :     nullptr
    4845             :   };
    4846             : 
    4847             :   extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass = {
    4848             :     &AArch64MCRegisterClasses[QQQ_with_qsub2_in_FPR128_loRegClassID],
    4849             :     48, /* SpillSize */
    4850             :     16, /* SpillAlignment */
    4851             :     VTLists + 34,
    4852             :     QQQ_with_qsub2_in_FPR128_loSubClassMask,
    4853             :     SuperRegIdxSeqs + 50,
    4854             :     LaneBitmask(0x00000A01),
    4855             :     0,
    4856             :     true, /* HasDisjunctSubRegs */
    4857             :     true, /* CoveredBySubRegs */
    4858             :     QQQ_with_qsub2_in_FPR128_loSuperclasses,
    4859             :     nullptr
    4860             :   };
    4861             : 
    4862             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass = {
    4863             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID],
    4864             :     48, /* SpillSize */
    4865             :     16, /* SpillAlignment */
    4866             :     VTLists + 34,
    4867             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask,
    4868             :     SuperRegIdxSeqs + 50,
    4869             :     LaneBitmask(0x00000A01),
    4870             :     0,
    4871             :     true, /* HasDisjunctSubRegs */
    4872             :     true, /* CoveredBySubRegs */
    4873             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses,
    4874             :     nullptr
    4875             :   };
    4876             : 
    4877             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
    4878             :     &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
    4879             :     48, /* SpillSize */
    4880             :     16, /* SpillAlignment */
    4881             :     VTLists + 34,
    4882             :     QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
    4883             :     SuperRegIdxSeqs + 50,
    4884             :     LaneBitmask(0x00000A01),
    4885             :     0,
    4886             :     true, /* HasDisjunctSubRegs */
    4887             :     true, /* CoveredBySubRegs */
    4888             :     QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
    4889             :     nullptr
    4890             :   };
    4891             : 
    4892             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
    4893             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
    4894             :     48, /* SpillSize */
    4895             :     16, /* SpillAlignment */
    4896             :     VTLists + 34,
    4897             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
    4898             :     SuperRegIdxSeqs + 50,
    4899             :     LaneBitmask(0x00000A01),
    4900             :     0,
    4901             :     true, /* HasDisjunctSubRegs */
    4902             :     true, /* CoveredBySubRegs */
    4903             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
    4904             :     nullptr
    4905             :   };
    4906             : 
    4907             :   extern const TargetRegisterClass QQQQRegClass = {
    4908             :     &AArch64MCRegisterClasses[QQQQRegClassID],
    4909             :     64, /* SpillSize */
    4910             :     16, /* SpillAlignment */
    4911             :     VTLists + 34,
    4912             :     QQQQSubClassMask,
    4913             :     SuperRegIdxSeqs + 4,
    4914             :     LaneBitmask(0x00000E01),
    4915             :     0,
    4916             :     true, /* HasDisjunctSubRegs */
    4917             :     true, /* CoveredBySubRegs */
    4918             :     NullRegClasses,
    4919             :     nullptr
    4920             :   };
    4921             : 
    4922             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass = {
    4923             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_loRegClassID],
    4924             :     64, /* SpillSize */
    4925             :     16, /* SpillAlignment */
    4926             :     VTLists + 34,
    4927             :     QQQQ_with_qsub0_in_FPR128_loSubClassMask,
    4928             :     SuperRegIdxSeqs + 4,
    4929             :     LaneBitmask(0x00000E01),
    4930             :     0,
    4931             :     true, /* HasDisjunctSubRegs */
    4932             :     true, /* CoveredBySubRegs */
    4933             :     QQQQ_with_qsub0_in_FPR128_loSuperclasses,
    4934             :     nullptr
    4935             :   };
    4936             : 
    4937             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass = {
    4938             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_loRegClassID],
    4939             :     64, /* SpillSize */
    4940             :     16, /* SpillAlignment */
    4941             :     VTLists + 34,
    4942             :     QQQQ_with_qsub1_in_FPR128_loSubClassMask,
    4943             :     SuperRegIdxSeqs + 4,
    4944             :     LaneBitmask(0x00000E01),
    4945             :     0,
    4946             :     true, /* HasDisjunctSubRegs */
    4947             :     true, /* CoveredBySubRegs */
    4948             :     QQQQ_with_qsub1_in_FPR128_loSuperclasses,
    4949             :     nullptr
    4950             :   };
    4951             : 
    4952             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass = {
    4953             :     &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_loRegClassID],
    4954             :     64, /* SpillSize */
    4955             :     16, /* SpillAlignment */
    4956             :     VTLists + 34,
    4957             :     QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    4958             :     SuperRegIdxSeqs + 4,
    4959             :     LaneBitmask(0x00000E01),
    4960             :     0,
    4961             :     true, /* HasDisjunctSubRegs */
    4962             :     true, /* CoveredBySubRegs */
    4963             :     QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    4964             :     nullptr
    4965             :   };
    4966             : 
    4967             :   extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass = {
    4968             :     &AArch64MCRegisterClasses[QQQQ_with_qsub3_in_FPR128_loRegClassID],
    4969             :     64, /* SpillSize */
    4970             :     16, /* SpillAlignment */
    4971             :     VTLists + 34,
    4972             :     QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    4973             :     SuperRegIdxSeqs + 4,
    4974             :     LaneBitmask(0x00000E01),
    4975             :     0,
    4976             :     true, /* HasDisjunctSubRegs */
    4977             :     true, /* CoveredBySubRegs */
    4978             :     QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    4979             :     nullptr
    4980             :   };
    4981             : 
    4982             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass = {
    4983             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID],
    4984             :     64, /* SpillSize */
    4985             :     16, /* SpillAlignment */
    4986             :     VTLists + 34,
    4987             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask,
    4988             :     SuperRegIdxSeqs + 4,
    4989             :     LaneBitmask(0x00000E01),
    4990             :     0,
    4991             :     true, /* HasDisjunctSubRegs */
    4992             :     true, /* CoveredBySubRegs */
    4993             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses,
    4994             :     nullptr
    4995             :   };
    4996             : 
    4997             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
    4998             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
    4999             :     64, /* SpillSize */
    5000             :     16, /* SpillAlignment */
    5001             :     VTLists + 34,
    5002             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    5003             :     SuperRegIdxSeqs + 4,
    5004             :     LaneBitmask(0x00000E01),
    5005             :     0,
    5006             :     true, /* HasDisjunctSubRegs */
    5007             :     true, /* CoveredBySubRegs */
    5008             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    5009             :     nullptr
    5010             :   };
    5011             : 
    5012             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    5013             :     &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    5014             :     64, /* SpillSize */
    5015             :     16, /* SpillAlignment */
    5016             :     VTLists + 34,
    5017             :     QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    5018             :     SuperRegIdxSeqs + 4,
    5019             :     LaneBitmask(0x00000E01),
    5020             :     0,
    5021             :     true, /* HasDisjunctSubRegs */
    5022             :     true, /* CoveredBySubRegs */
    5023             :     QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    5024             :     nullptr
    5025             :   };
    5026             : 
    5027             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
    5028             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
    5029             :     64, /* SpillSize */
    5030             :     16, /* SpillAlignment */
    5031             :     VTLists + 34,
    5032             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    5033             :     SuperRegIdxSeqs + 4,
    5034             :     LaneBitmask(0x00000E01),
    5035             :     0,
    5036             :     true, /* HasDisjunctSubRegs */
    5037             :     true, /* CoveredBySubRegs */
    5038             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    5039             :     nullptr
    5040             :   };
    5041             : 
    5042             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    5043             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    5044             :     64, /* SpillSize */
    5045             :     16, /* SpillAlignment */
    5046             :     VTLists + 34,
    5047             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    5048             :     SuperRegIdxSeqs + 4,
    5049             :     LaneBitmask(0x00000E01),
    5050             :     0,
    5051             :     true, /* HasDisjunctSubRegs */
    5052             :     true, /* CoveredBySubRegs */
    5053             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    5054             :     nullptr
    5055             :   };
    5056             : 
    5057             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    5058             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    5059             :     64, /* SpillSize */
    5060             :     16, /* SpillAlignment */
    5061             :     VTLists + 34,
    5062             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    5063             :     SuperRegIdxSeqs + 4,
    5064             :     LaneBitmask(0x00000E01),
    5065             :     0,
    5066             :     true, /* HasDisjunctSubRegs */
    5067             :     true, /* CoveredBySubRegs */
    5068             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    5069             :     nullptr
    5070             :   };
    5071             : 
    5072             : } // end namespace AArch64
    5073             : 
    5074             : namespace {
    5075             :   const TargetRegisterClass* const RegisterClasses[] = {
    5076             :     &AArch64::FPR8RegClass,
    5077             :     &AArch64::FPR16RegClass,
    5078             :     &AArch64::GPR32allRegClass,
    5079             :     &AArch64::FPR32RegClass,
    5080             :     &AArch64::GPR32RegClass,
    5081             :     &AArch64::GPR32spRegClass,
    5082             :     &AArch64::GPR32commonRegClass,
    5083             :     &AArch64::CCRRegClass,
    5084             :     &AArch64::GPR32sponlyRegClass,
    5085             :     &AArch64::WSeqPairsClassRegClass,
    5086             :     &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
    5087             :     &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    5088             :     &AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    5089             :     &AArch64::GPR64allRegClass,
    5090             :     &AArch64::FPR64RegClass,
    5091             :     &AArch64::GPR64RegClass,
    5092             :     &AArch64::GPR64spRegClass,
    5093             :     &AArch64::GPR64commonRegClass,
    5094             :     &AArch64::tcGPR64RegClass,
    5095             :     &AArch64::GPR64sponlyRegClass,
    5096             :     &AArch64::DDRegClass,
    5097             :     &AArch64::XSeqPairsClassRegClass,
    5098             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    5099             :     &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5100             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5101             :     &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
    5102             :     &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    5103             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    5104             :     &AArch64::FPR128RegClass,
    5105             :     &AArch64::FPR128_loRegClass,
    5106             :     &AArch64::DDDRegClass,
    5107             :     &AArch64::DDDDRegClass,
    5108             :     &AArch64::QQRegClass,
    5109             :     &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
    5110             :     &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
    5111             :     &AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass,
    5112             :     &AArch64::QQQRegClass,
    5113             :     &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    5114             :     &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    5115             :     &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    5116             :     &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
    5117             :     &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    5118             :     &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    5119             :     &AArch64::QQQQRegClass,
    5120             :     &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    5121             :     &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    5122             :     &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    5123             :     &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    5124             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    5125             :     &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    5126             :     &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5127             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    5128             :     &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5129             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5130             :   };
    5131             : } // end anonymous namespace
    5132             : 
    5133             : static const TargetRegisterInfoDesc AArch64RegInfoDesc[] = { // Extra Descriptors
    5134             :   { 0, false },
    5135             :   { 0, true },
    5136             :   { 0, true },
    5137             :   { 0, false },
    5138             :   { 0, true },
    5139             :   { 0, true },
    5140             :   { 0, true },
    5141             :   { 0, true },
    5142             :   { 0, true },
    5143             :   { 0, true },
    5144             :   { 0, true },
    5145             :   { 0, true },
    5146             :   { 0, true },
    5147             :   { 0, true },
    5148             :   { 0, true },
    5149             :   { 0, true },
    5150             :   { 0, true },
    5151             :   { 0, true },
    5152             :   { 0, true },
    5153             :   { 0, true },
    5154             :   { 0, true },
    5155             :   { 0, true },
    5156             :   { 0, true },
    5157             :   { 0, true },
    5158             :   { 0, true },
    5159             :   { 0, true },
    5160             :   { 0, true },
    5161             :   { 0, true },
    5162             :   { 0, true },
    5163             :   { 0, true },
    5164             :   { 0, true },
    5165             :   { 0, true },
    5166             :   { 0, true },
    5167             :   { 0, true },
    5168             :   { 0, true },
    5169             :   { 0, true },
    5170             :   { 0, true },
    5171             :   { 0, true },
    5172             :   { 0, true },
    5173             :   { 0, true },
    5174             :   { 0, true },
    5175             :   { 0, true },
    5176             :   { 0, true },
    5177             :   { 0, true },
    5178             :   { 0, true },
    5179             :   { 0, true },
    5180             :   { 0, true },
    5181             :   { 0, true },
    5182             :   { 0, true },
    5183             :   { 0, true },
    5184             :   { 0, true },
    5185             :   { 0, true },
    5186             :   { 0, true },
    5187             :   { 0, true },
    5188             :   { 0, true },
    5189             :   { 0, true },
    5190             :   { 0, true },
    5191             :   { 0, true },
    5192             :   { 0, true },
    5193             :   { 0, true },
    5194             :   { 0, true },
    5195             :   { 0, true },
    5196             :   { 0, true },
    5197             :   { 0, true },
    5198             :   { 0, true },
    5199             :   { 0, true },
    5200             :   { 0, true },
    5201             :   { 0, true },
    5202             :   { 0, true },
    5203             :   { 0, true },
    5204             :   { 0, true },
    5205             :   { 0, true },
    5206             :   { 0, true },
    5207             :   { 0, true },
    5208             :   { 0, true },
    5209             :   { 0, true },
    5210             :   { 0, true },
    5211             :   { 0, true },
    5212             :   { 0, true },
    5213             :   { 0, true },
    5214             :   { 0, true },
    5215             :   { 0, true },
    5216             :   { 0, true },
    5217             :   { 0, true },
    5218             :   { 0, true },
    5219             :   { 0, true },
    5220             :   { 0, true },
    5221             :   { 0, true },
    5222             :   { 0, true },
    5223             :   { 0, true },
    5224             :   { 0, true },
    5225             :   { 0, true },
    5226             :   { 0, true },
    5227             :   { 0, true },
    5228             :   { 0, true },
    5229             :   { 0, true },
    5230             :   { 0, true },
    5231             :   { 0, true },
    5232             :   { 0, true },
    5233             :   { 0, true },
    5234             :   { 0, true },
    5235             :   { 0, true },
    5236             :   { 0, true },
    5237             :   { 0, true },
    5238             :   { 0, true },
    5239             :   { 0, true },
    5240             :   { 0, true },
    5241             :   { 0, true },
    5242             :   { 0, true },
    5243             :   { 0, true },
    5244             :   { 0, true },
    5245             :   { 0, true },
    5246             :   { 0, true },
    5247             :   { 0, true },
    5248             :   { 0, true },
    5249             :   { 0, true },
    5250             :   { 0, true },
    5251             :   { 0, true },
    5252             :   { 0, true },
    5253             :   { 0, true },
    5254             :   { 0, true },
    5255             :   { 0, true },
    5256             :   { 0, true },
    5257             :   { 0, true },
    5258             :   { 0, true },
    5259             :   { 0, true },
    5260             :   { 0, true },
    5261             :   { 0, true },
    5262             :   { 0, true },
    5263             :   { 0, true },
    5264             :   { 0, true },
    5265             :   { 0, true },
    5266             :   { 0, true },
    5267             :   { 0, true },
    5268             :   { 0, true },
    5269             :   { 0, true },
    5270             :   { 0, true },
    5271             :   { 0, true },
    5272             :   { 0, true },
    5273             :   { 0, true },
    5274             :   { 0, true },
    5275             :   { 0, true },
    5276             :   { 0, true },
    5277             :   { 0, true },
    5278             :   { 0, true },
    5279             :   { 0, true },
    5280             :   { 0, true },
    5281             :   { 0, true },
    5282             :   { 0, true },
    5283             :   { 0, true },
    5284             :   { 0, true },
    5285             :   { 0, true },
    5286             :   { 0, true },
    5287             :   { 0, true },
    5288             :   { 0, true },
    5289             :   { 0, true },
    5290             :   { 0, true },
    5291             :   { 0, true },
    5292             :   { 0, true },
    5293             :   { 0, true },
    5294             :   { 0, true },
    5295             :   { 0, true },
    5296             :   { 0, true },
    5297             :   { 0, true },
    5298             :   { 0, true },
    5299             :   { 0, true },
    5300             :   { 0, true },
    5301             :   { 0, true },
    5302             :   { 0, true },
    5303             :   { 0, true },
    5304             :   { 0, true },
    5305             :   { 0, true },
    5306             :   { 0, true },
    5307             :   { 0, true },
    5308             :   { 0, true },
    5309             :   { 0, true },
    5310             :   { 0, true },
    5311             :   { 0, true },
    5312             :   { 0, true },
    5313             :   { 0, true },
    5314             :   { 0, true },
    5315             :   { 0, true },
    5316             :   { 0, true },
    5317             :   { 0, true },
    5318             :   { 0, true },
    5319             :   { 0, true },
    5320             :   { 0, true },
    5321             :   { 0, true },
    5322             :   { 0, true },
    5323             :   { 0, true },
    5324             :   { 0, true },
    5325             :   { 0, true },
    5326             :   { 0, true },
    5327             :   { 0, true },
    5328             :   { 0, true },
    5329             :   { 0, true },
    5330             :   { 0, true },
    5331             :   { 0, true },
    5332             :   { 0, true },
    5333             :   { 0, true },
    5334             :   { 0, true },
    5335             :   { 0, true },
    5336             :   { 0, true },
    5337             :   { 0, true },
    5338             :   { 0, true },
    5339             :   { 0, true },
    5340             :   { 0, true },
    5341             :   { 0, true },
    5342             :   { 0, true },
    5343             :   { 0, true },
    5344             :   { 0, true },
    5345             :   { 0, true },
    5346             :   { 0, true },
    5347             :   { 0, true },
    5348             :   { 0, true },
    5349             :   { 0, true },
    5350             :   { 0, true },
    5351             :   { 0, true },
    5352             :   { 0, true },
    5353             :   { 0, true },
    5354             :   { 0, true },
    5355             :   { 0, true },
    5356             :   { 0, true },
    5357             :   { 0, true },
    5358             :   { 0, true },
    5359             :   { 0, true },
    5360             :   { 0, true },
    5361             :   { 0, true },
    5362             :   { 0, true },
    5363             :   { 0, true },
    5364             :   { 0, true },
    5365             :   { 0, true },
    5366             :   { 0, true },
    5367             :   { 0, true },
    5368             :   { 0, true },
    5369             :   { 0, true },
    5370             :   { 0, true },
    5371             :   { 0, true },
    5372             :   { 0, true },
    5373             :   { 0, true },
    5374             :   { 0, true },
    5375             :   { 0, true },
    5376             :   { 0, true },
    5377             :   { 0, true },
    5378             :   { 0, true },
    5379             :   { 0, true },
    5380             :   { 0, true },
    5381             :   { 0, true },
    5382             :   { 0, true },
    5383             :   { 0, true },
    5384             :   { 0, true },
    5385             :   { 0, true },
    5386             :   { 0, true },
    5387             :   { 0, true },
    5388             :   { 0, true },
    5389             :   { 0, true },
    5390             :   { 0, true },
    5391             :   { 0, true },
    5392             :   { 0, true },
    5393             :   { 0, true },
    5394             :   { 0, true },
    5395             :   { 0, true },
    5396             :   { 0, true },
    5397             :   { 0, true },
    5398             :   { 0, true },
    5399             :   { 0, true },
    5400             :   { 0, true },
    5401             :   { 0, true },
    5402             :   { 0, true },
    5403             :   { 0, true },
    5404             :   { 0, true },
    5405             :   { 0, true },
    5406             :   { 0, true },
    5407             :   { 0, true },
    5408             :   { 0, true },
    5409             :   { 0, true },
    5410             :   { 0, true },
    5411             :   { 0, true },
    5412             :   { 0, true },
    5413             :   { 0, true },
    5414             :   { 0, true },
    5415             :   { 0, true },
    5416             :   { 0, true },
    5417             :   { 0, true },
    5418             :   { 0, true },
    5419             :   { 0, true },
    5420             :   { 0, true },
    5421             :   { 0, true },
    5422             :   { 0, true },
    5423             :   { 0, true },
    5424             :   { 0, true },
    5425             :   { 0, true },
    5426             :   { 0, true },
    5427             :   { 0, true },
    5428             :   { 0, true },
    5429             :   { 0, true },
    5430             :   { 0, true },
    5431             :   { 0, true },
    5432             :   { 0, true },
    5433             :   { 0, true },
    5434             :   { 0, true },
    5435             :   { 0, true },
    5436             :   { 0, true },
    5437             :   { 0, true },
    5438             :   { 0, true },
    5439             :   { 0, true },
    5440             :   { 0, true },
    5441             :   { 0, true },
    5442             :   { 0, true },
    5443             :   { 0, true },
    5444             :   { 0, true },
    5445             :   { 0, true },
    5446             :   { 0, true },
    5447             :   { 0, true },
    5448             :   { 0, true },
    5449             :   { 0, true },
    5450             :   { 0, true },
    5451             :   { 0, true },
    5452             :   { 0, true },
    5453             :   { 0, true },
    5454             :   { 0, true },
    5455             :   { 0, true },
    5456             :   { 0, true },
    5457             :   { 0, true },
    5458             :   { 0, true },
    5459             :   { 0, true },
    5460             :   { 0, true },
    5461             :   { 0, true },
    5462             :   { 0, true },
    5463             :   { 0, true },
    5464             :   { 0, true },
    5465             :   { 0, true },
    5466             :   { 0, true },
    5467             :   { 0, true },
    5468             :   { 0, true },
    5469             :   { 0, true },
    5470             :   { 0, true },
    5471             :   { 0, true },
    5472             :   { 0, true },
    5473             :   { 0, true },
    5474             :   { 0, true },
    5475             :   { 0, true },
    5476             :   { 0, true },
    5477             :   { 0, true },
    5478             :   { 0, true },
    5479             :   { 0, true },
    5480             :   { 0, true },
    5481             :   { 0, true },
    5482             :   { 0, true },
    5483             :   { 0, true },
    5484             :   { 0, true },
    5485             :   { 0, true },
    5486             :   { 0, true },
    5487             :   { 0, true },
    5488             :   { 0, true },
    5489             :   { 0, true },
    5490             :   { 0, true },
    5491             :   { 0, true },
    5492             :   { 0, true },
    5493             :   { 0, true },
    5494             :   { 0, true },
    5495             :   { 0, true },
    5496             :   { 0, true },
    5497             :   { 0, true },
    5498             :   { 0, true },
    5499             :   { 0, true },
    5500             :   { 0, true },
    5501             :   { 0, true },
    5502             :   { 0, true },
    5503             :   { 0, true },
    5504             :   { 0, true },
    5505             :   { 0, true },
    5506             :   { 0, true },
    5507             :   { 0, true },
    5508             :   { 0, true },
    5509             :   { 0, true },
    5510             :   { 0, true },
    5511             :   { 0, true },
    5512             :   { 0, true },
    5513             :   { 0, true },
    5514             :   { 0, true },
    5515             :   { 0, true },
    5516             :   { 0, true },
    5517             :   { 0, true },
    5518             :   { 0, true },
    5519             :   { 0, true },
    5520             :   { 0, true },
    5521             :   { 0, true },
    5522             :   { 0, true },
    5523             :   { 0, true },
    5524             :   { 0, true },
    5525             :   { 0, true },
    5526             :   { 0, true },
    5527             :   { 0, true },
    5528             :   { 0, true },
    5529             :   { 0, true },
    5530             :   { 0, true },
    5531             :   { 0, true },
    5532             :   { 0, true },
    5533             :   { 0, true },
    5534             :   { 0, true },
    5535             :   { 0, true },
    5536             :   { 0, true },
    5537             :   { 0, true },
    5538             :   { 0, true },
    5539             :   { 0, true },
    5540             :   { 0, true },
    5541             :   { 0, true },
    5542             :   { 0, true },
    5543             :   { 0, true },
    5544             :   { 0, true },
    5545             :   { 0, true },
    5546             :   { 0, true },
    5547             :   { 0, true },
    5548             :   { 0, true },
    5549             :   { 0, true },
    5550             :   { 0, true },
    5551             :   { 0, true },
    5552             :   { 0, true },
    5553             :   { 0, true },
    5554             :   { 0, true },
    5555             :   { 0, true },
    5556             :   { 0, true },
    5557             :   { 0, true },
    5558             :   { 0, true },
    5559             :   { 0, true },
    5560             :   { 0, true },
    5561             :   { 0, true },
    5562             :   { 0, true },
    5563             :   { 0, true },
    5564             :   { 0, true },
    5565             :   { 0, true },
    5566             :   { 0, true },
    5567             :   { 0, true },
    5568             :   { 0, true },
    5569             :   { 0, true },
    5570             :   { 0, true },
    5571             :   { 0, true },
    5572             :   { 0, true },
    5573             :   { 0, true },
    5574             :   { 0, true },
    5575             :   { 0, true },
    5576             :   { 0, true },
    5577             :   { 0, true },
    5578             :   { 0, true },
    5579             :   { 0, true },
    5580             :   { 0, true },
    5581             :   { 0, true },
    5582             :   { 0, true },
    5583             :   { 0, true },
    5584             :   { 0, true },
    5585             :   { 0, true },
    5586             :   { 0, true },
    5587             :   { 0, true },
    5588             :   { 0, true },
    5589             :   { 0, true },
    5590             :   { 0, true },
    5591             :   { 0, true },
    5592             :   { 0, true },
    5593             :   { 0, true },
    5594             :   { 0, true },
    5595             :   { 0, true },
    5596             :   { 0, true },
    5597             :   { 0, true },
    5598             :   { 0, true },
    5599             :   { 0, true },
    5600             :   { 0, true },
    5601             :   { 0, true },
    5602             :   { 0, true },
    5603             :   { 0, true },
    5604             :   { 0, true },
    5605             :   { 0, true },
    5606             :   { 0, true },
    5607             :   { 0, true },
    5608             :   { 0, true },
    5609             :   { 0, true },
    5610             :   { 0, true },
    5611             :   { 0, true },
    5612             :   { 0, true },
    5613             :   { 0, true },
    5614             :   { 0, true },
    5615             :   { 0, true },
    5616             :   { 0, true },
    5617             :   { 0, true },
    5618             : };
    5619        1087 : unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
    5620             :   static const uint8_t RowMap[58] = {
    5621             :     0, 0, 0, 1, 2, 3, 0, 0, 0, 0, 4, 5, 6, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 3, 3, 0, 2, 2, 0, 4, 4, 4, 0, 6, 6, 6, 0, 5, 5, 5, 0, 0, 0, 1, 1, 2, 7, 7, 7, 0, 0, 4, 4, 5, 4, 4, 5, 0, 
    5622             :   };
    5623             :   static const uint8_t Rows[8][58] = {
    5624             :     { 1, 2, 3, 4, 5, 0, 7, 0, 0, 10, 11, 12, 0, 14, 15, 15, 0, 41, 0, 20, 21, 22, 0, 0, 0, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 37, 38, 39, 40, 0, 42, 0, 44, 0, 0, 47, 0, 49, 50, 0, 52, 0, 0, 55, 0, 0, 0, },
    5625             :     { 20, 0, 4, 5, 6, 0, 21, 0, 0, 0, 0, 0, 0, 22, 41, 0, 0, 0, 0, 26, 27, 28, 0, 0, 0, 23, 24, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 44, 0, 46, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    5626             :     { 26, 0, 5, 6, 0, 0, 27, 0, 0, 0, 0, 0, 0, 28, 0, 0, 0, 0, 0, 23, 24, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    5627             :     { 23, 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    5628             :     { 29, 30, 30, 38, 34, 0, 31, 0, 0, 11, 12, 13, 0, 32, 0, 0, 0, 0, 0, 37, 39, 40, 0, 0, 0, 33, 35, 36, 37, 38, 39, 40, 0, 0, 0, 0, 33, 34, 35, 36, 0, 55, 0, 57, 0, 0, 55, 0, 56, 52, 0, 54, 0, 0, 57, 0, 0, 0, },
    5629             :     { 37, 38, 38, 34, 0, 0, 39, 0, 0, 12, 13, 0, 0, 40, 0, 0, 0, 0, 0, 33, 35, 36, 0, 0, 0, 0, 0, 0, 33, 34, 35, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    5630             :     { 33, 34, 0, 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    5631             :     { 1, 0, 2, 30, 38, 34, 7, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 29, 31, 32, 33, 35, 36, 37, 39, 40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 47, 49, 55, 56, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    5632             :   };
    5633             : 
    5634        1087 :   --IdxA; assert(IdxA < 58);
    5635        1087 :   --IdxB; assert(IdxB < 58);
    5636        1087 :   return Rows[RowMap[IdxA]][IdxB];
    5637             : }
    5638             : 
    5639             :   struct MaskRolOp {
    5640             :     LaneBitmask Mask;
    5641             :     uint8_t  RotateLeft;
    5642             :   };
    5643             :   static const MaskRolOp LaneMaskComposeSequences[] = {
    5644             :     { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    5645             :     { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    5646             :     { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    5647             :     { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    5648             :     { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    5649             :     { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    5650             :     { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    5651             :     { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    5652             :     { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
    5653             :     { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
    5654             :     { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
    5655             :     { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
    5656             :     { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
    5657             :     { LaneBitmask(0x00000001),  6 }, { LaneBitmask(0x00000040),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 26
    5658             :     { LaneBitmask(0x00000001),  6 }, { LaneBitmask(0x00000040),  2 }, { LaneBitmask(0x00000100), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 29
    5659             :     { LaneBitmask(0x00000001),  8 }, { LaneBitmask(0x00000040),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 33
    5660             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000040),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 36
    5661             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x000001C0),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 39
    5662             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000140),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 42
    5663             :     { LaneBitmask(0x00000001),  9 }, { LaneBitmask(0x00000200),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 45
    5664             :     { LaneBitmask(0x00000001),  9 }, { LaneBitmask(0x00000200),  2 }, { LaneBitmask(0x00000800), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 48
    5665             :     { LaneBitmask(0x00000001), 11 }, { LaneBitmask(0x00000200),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 52
    5666             :     { LaneBitmask(0x00000001),  9 }, { LaneBitmask(0x00000040),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 55
    5667             :     { LaneBitmask(0x00000001),  9 }, { LaneBitmask(0x00000040),  5 }, { LaneBitmask(0x00000100),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 58
    5668             :     { LaneBitmask(0x00000001), 11 }, { LaneBitmask(0x00000040),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 62
    5669             :     { LaneBitmask(0x00000010), 31 }, { LaneBitmask(0x00000020),  7 }, { LaneBitmask::getNone(), 0 }  // Sequence 65
    5670     1879956 :   };
    5671             :   static const MaskRolOp *const CompositeSequences[] = {
    5672             :     &LaneMaskComposeSequences[0], // to bsub
    5673             :     &LaneMaskComposeSequences[0], // to dsub
    5674             :     &LaneMaskComposeSequences[0], // to dsub0
    5675             :     &LaneMaskComposeSequences[2], // to dsub1
    5676             :     &LaneMaskComposeSequences[4], // to dsub2
    5677             :     &LaneMaskComposeSequences[6], // to dsub3
    5678             :     &LaneMaskComposeSequences[0], // to hsub
    5679             :     &LaneMaskComposeSequences[8], // to qhisub
    5680             :     &LaneMaskComposeSequences[10], // to qsub
    5681             :     &LaneMaskComposeSequences[0], // to qsub0
    5682             :     &LaneMaskComposeSequences[12], // to qsub1
    5683             :     &LaneMaskComposeSequences[14], // to qsub2
    5684             :     &LaneMaskComposeSequences[16], // to qsub3
    5685             :     &LaneMaskComposeSequences[0], // to ssub
    5686             :     &LaneMaskComposeSequences[18], // to sub_32
    5687             :     &LaneMaskComposeSequences[20], // to sube32
    5688             :     &LaneMaskComposeSequences[0], // to sube64
    5689             :     &LaneMaskComposeSequences[22], // to subo32
    5690             :     &LaneMaskComposeSequences[12], // to subo64
    5691             :     &LaneMaskComposeSequences[2], // to dsub1_then_bsub
    5692             :     &LaneMaskComposeSequences[2], // to dsub1_then_hsub
    5693             :     &LaneMaskComposeSequences[2], // to dsub1_then_ssub
    5694             :     &LaneMaskComposeSequences[6], // to dsub3_then_bsub
    5695             :     &LaneMaskComposeSequences[6], // to dsub3_then_hsub
    5696             :     &LaneMaskComposeSequences[6], // to dsub3_then_ssub
    5697             :     &LaneMaskComposeSequences[4], // to dsub2_then_bsub
    5698             :     &LaneMaskComposeSequences[4], // to dsub2_then_hsub
    5699             :     &LaneMaskComposeSequences[4], // to dsub2_then_ssub
    5700             :     &LaneMaskComposeSequences[12], // to qsub1_then_bsub
    5701             :     &LaneMaskComposeSequences[12], // to qsub1_then_dsub
    5702             :     &LaneMaskComposeSequences[12], // to qsub1_then_hsub
    5703             :     &LaneMaskComposeSequences[12], // to qsub1_then_ssub
    5704             :     &LaneMaskComposeSequences[16], // to qsub3_then_bsub
    5705             :     &LaneMaskComposeSequences[16], // to qsub3_then_dsub
    5706             :     &LaneMaskComposeSequences[16], // to qsub3_then_hsub
    5707             :     &LaneMaskComposeSequences[16], // to qsub3_then_ssub
    5708             :     &LaneMaskComposeSequences[14], // to qsub2_then_bsub
    5709             :     &LaneMaskComposeSequences[14], // to qsub2_then_dsub
    5710             :     &LaneMaskComposeSequences[14], // to qsub2_then_hsub
    5711             :     &LaneMaskComposeSequences[14], // to qsub2_then_ssub
    5712             :     &LaneMaskComposeSequences[24], // to subo64_then_sub_32
    5713             :     &LaneMaskComposeSequences[0], // to dsub0_dsub1
    5714             :     &LaneMaskComposeSequences[0], // to dsub0_dsub1_dsub2
    5715             :     &LaneMaskComposeSequences[26], // to dsub1_dsub2
    5716             :     &LaneMaskComposeSequences[29], // to dsub1_dsub2_dsub3
    5717             :     &LaneMaskComposeSequences[33], // to dsub2_dsub3
    5718             :     &LaneMaskComposeSequences[36], // to dsub_qsub1_then_dsub
    5719             :     &LaneMaskComposeSequences[39], // to dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5720             :     &LaneMaskComposeSequences[42], // to dsub_qsub1_then_dsub_qsub2_then_dsub
    5721             :     &LaneMaskComposeSequences[0], // to qsub0_qsub1
    5722             :     &LaneMaskComposeSequences[0], // to qsub0_qsub1_qsub2
    5723             :     &LaneMaskComposeSequences[45], // to qsub1_qsub2
    5724             :     &LaneMaskComposeSequences[48], // to qsub1_qsub2_qsub3
    5725             :     &LaneMaskComposeSequences[52], // to qsub2_qsub3
    5726             :     &LaneMaskComposeSequences[55], // to qsub1_then_dsub_qsub2_then_dsub
    5727             :     &LaneMaskComposeSequences[58], // to qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5728             :     &LaneMaskComposeSequences[62], // to qsub2_then_dsub_qsub3_then_dsub
    5729             :     &LaneMaskComposeSequences[65] // to sub_32_subo64_then_sub_32
    5730             :   };
    5731             : 
    5732           0 : LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
    5733           0 :   --IdxA; assert(IdxA < 58 && "Subregister index out of bounds");
    5734           0 :   LaneBitmask Result;
    5735           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    5736           0 :     LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    5737           0 :     if (unsigned S = Ops->RotateLeft)
    5738           0 :       Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    5739             :     else
    5740           0 :       Result |= LaneBitmask(M);
    5741             :   }
    5742           0 :   return Result;
    5743             : }
    5744             : 
    5745           0 : LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
    5746           0 :   LaneMask &= getSubRegIndexLaneMask(IdxA);
    5747           0 :   --IdxA; assert(IdxA < 58 && "Subregister index out of bounds");
    5748           0 :   LaneBitmask Result;
    5749           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    5750           0 :     LaneBitmask::Type M = LaneMask.getAsInteger();
    5751           0 :     if (unsigned S = Ops->RotateLeft)
    5752           0 :       Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    5753             :     else
    5754           0 :       Result |= LaneBitmask(M);
    5755             :   }
    5756           0 :   return Result;
    5757             : }
    5758             : 
    5759       29015 : const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
    5760             :   static const uint8_t Table[54][58] = {
    5761             :     {   // FPR8
    5762             :       0,        // bsub
    5763             :       0,        // dsub
    5764             :       0,        // dsub0
    5765             :       0,        // dsub1
    5766             :       0,        // dsub2
    5767             :       0,        // dsub3
    5768             :       0,        // hsub
    5769             :       0,        // qhisub
    5770             :       0,        // qsub
    5771             :       0,        // qsub0
    5772             :       0,        // qsub1
    5773             :       0,        // qsub2
    5774             :       0,        // qsub3
    5775             :       0,        // ssub
    5776             :       0,        // sub_32
    5777             :       0,        // sube32
    5778             :       0,        // sube64
    5779             :       0,        // subo32
    5780             :       0,        // subo64
    5781             :       0,        // dsub1_then_bsub
    5782             :       0,        // dsub1_then_hsub
    5783             :       0,        // dsub1_then_ssub
    5784             :       0,        // dsub3_then_bsub
    5785             :       0,        // dsub3_then_hsub
    5786             :       0,        // dsub3_then_ssub
    5787             :       0,        // dsub2_then_bsub
    5788             :       0,        // dsub2_then_hsub
    5789             :       0,        // dsub2_then_ssub
    5790             :       0,        // qsub1_then_bsub
    5791             :       0,        // qsub1_then_dsub
    5792             :       0,        // qsub1_then_hsub
    5793             :       0,        // qsub1_then_ssub
    5794             :       0,        // qsub3_then_bsub
    5795             :       0,        // qsub3_then_dsub
    5796             :       0,        // qsub3_then_hsub
    5797             :       0,        // qsub3_then_ssub
    5798             :       0,        // qsub2_then_bsub
    5799             :       0,        // qsub2_then_dsub
    5800             :       0,        // qsub2_then_hsub
    5801             :       0,        // qsub2_then_ssub
    5802             :       0,        // subo64_then_sub_32
    5803             :       0,        // dsub0_dsub1
    5804             :       0,        // dsub0_dsub1_dsub2
    5805             :       0,        // dsub1_dsub2
    5806             :       0,        // dsub1_dsub2_dsub3
    5807             :       0,        // dsub2_dsub3
    5808             :       0,        // dsub_qsub1_then_dsub
    5809             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5810             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    5811             :       0,        // qsub0_qsub1
    5812             :       0,        // qsub0_qsub1_qsub2
    5813             :       0,        // qsub1_qsub2
    5814             :       0,        // qsub1_qsub2_qsub3
    5815             :       0,        // qsub2_qsub3
    5816             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    5817             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5818             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    5819             :       0,        // sub_32_subo64_then_sub_32
    5820             :     },
    5821             :     {   // FPR16
    5822             :       2,        // bsub -> FPR16
    5823             :       0,        // dsub
    5824             :       0,        // dsub0
    5825             :       0,        // dsub1
    5826             :       0,        // dsub2
    5827             :       0,        // dsub3
    5828             :       0,        // hsub
    5829             :       0,        // qhisub
    5830             :       0,        // qsub
    5831             :       0,        // qsub0
    5832             :       0,        // qsub1
    5833             :       0,        // qsub2
    5834             :       0,        // qsub3
    5835             :       0,        // ssub
    5836             :       0,        // sub_32
    5837             :       0,        // sube32
    5838             :       0,        // sube64
    5839             :       0,        // subo32
    5840             :       0,        // subo64
    5841             :       0,        // dsub1_then_bsub
    5842             :       0,        // dsub1_then_hsub
    5843             :       0,        // dsub1_then_ssub
    5844             :       0,        // dsub3_then_bsub
    5845             :       0,        // dsub3_then_hsub
    5846             :       0,        // dsub3_then_ssub
    5847             :       0,        // dsub2_then_bsub
    5848             :       0,        // dsub2_then_hsub
    5849             :       0,        // dsub2_then_ssub
    5850             :       0,        // qsub1_then_bsub
    5851             :       0,        // qsub1_then_dsub
    5852             :       0,        // qsub1_then_hsub
    5853             :       0,        // qsub1_then_ssub
    5854             :       0,        // qsub3_then_bsub
    5855             :       0,        // qsub3_then_dsub
    5856             :       0,        // qsub3_then_hsub
    5857             :       0,        // qsub3_then_ssub
    5858             :       0,        // qsub2_then_bsub
    5859             :       0,        // qsub2_then_dsub
    5860             :       0,        // qsub2_then_hsub
    5861             :       0,        // qsub2_then_ssub
    5862             :       0,        // subo64_then_sub_32
    5863             :       0,        // dsub0_dsub1
    5864             :       0,        // dsub0_dsub1_dsub2
    5865             :       0,        // dsub1_dsub2
    5866             :       0,        // dsub1_dsub2_dsub3
    5867             :       0,        // dsub2_dsub3
    5868             :       0,        // dsub_qsub1_then_dsub
    5869             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5870             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    5871             :       0,        // qsub0_qsub1
    5872             :       0,        // qsub0_qsub1_qsub2
    5873             :       0,        // qsub1_qsub2
    5874             :       0,        // qsub1_qsub2_qsub3
    5875             :       0,        // qsub2_qsub3
    5876             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    5877             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5878             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    5879             :       0,        // sub_32_subo64_then_sub_32
    5880             :     },
    5881             :     {   // GPR32all
    5882             :       0,        // bsub
    5883             :       0,        // dsub
    5884             :       0,        // dsub0
    5885             :       0,        // dsub1
    5886             :       0,        // dsub2
    5887             :       0,        // dsub3
    5888             :       0,        // hsub
    5889             :       0,        // qhisub
    5890             :       0,        // qsub
    5891             :       0,        // qsub0
    5892             :       0,        // qsub1
    5893             :       0,        // qsub2
    5894             :       0,        // qsub3
    5895             :       0,        // ssub
    5896             :       0,        // sub_32
    5897             :       0,        // sube32
    5898             :       0,        // sube64
    5899             :       0,        // subo32
    5900             :       0,        // subo64
    5901             :       0,        // dsub1_then_bsub
    5902             :       0,        // dsub1_then_hsub
    5903             :       0,        // dsub1_then_ssub
    5904             :       0,        // dsub3_then_bsub
    5905             :       0,        // dsub3_then_hsub
    5906             :       0,        // dsub3_then_ssub
    5907             :       0,        // dsub2_then_bsub
    5908             :       0,        // dsub2_then_hsub
    5909             :       0,        // dsub2_then_ssub
    5910             :       0,        // qsub1_then_bsub
    5911             :       0,        // qsub1_then_dsub
    5912             :       0,        // qsub1_then_hsub
    5913             :       0,        // qsub1_then_ssub
    5914             :       0,        // qsub3_then_bsub
    5915             :       0,        // qsub3_then_dsub
    5916             :       0,        // qsub3_then_hsub
    5917             :       0,        // qsub3_then_ssub
    5918             :       0,        // qsub2_then_bsub
    5919             :       0,        // qsub2_then_dsub
    5920             :       0,        // qsub2_then_hsub
    5921             :       0,        // qsub2_then_ssub
    5922             :       0,        // subo64_then_sub_32
    5923             :       0,        // dsub0_dsub1
    5924             :       0,        // dsub0_dsub1_dsub2
    5925             :       0,        // dsub1_dsub2
    5926             :       0,        // dsub1_dsub2_dsub3
    5927             :       0,        // dsub2_dsub3
    5928             :       0,        // dsub_qsub1_then_dsub
    5929             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5930             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    5931             :       0,        // qsub0_qsub1
    5932             :       0,        // qsub0_qsub1_qsub2
    5933             :       0,        // qsub1_qsub2
    5934             :       0,        // qsub1_qsub2_qsub3
    5935             :       0,        // qsub2_qsub3
    5936             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    5937             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5938             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    5939             :       0,        // sub_32_subo64_then_sub_32
    5940             :     },
    5941             :     {   // FPR32
    5942             :       4,        // bsub -> FPR32
    5943             :       0,        // dsub
    5944             :       0,        // dsub0
    5945             :       0,        // dsub1
    5946             :       0,        // dsub2
    5947             :       0,        // dsub3
    5948             :       4,        // hsub -> FPR32
    5949             :       0,        // qhisub
    5950             :       0,        // qsub
    5951             :       0,        // qsub0
    5952             :       0,        // qsub1
    5953             :       0,        // qsub2
    5954             :       0,        // qsub3
    5955             :       0,        // ssub
    5956             :       0,        // sub_32
    5957             :       0,        // sube32
    5958             :       0,        // sube64
    5959             :       0,        // subo32
    5960             :       0,        // subo64
    5961             :       0,        // dsub1_then_bsub
    5962             :       0,        // dsub1_then_hsub
    5963             :       0,        // dsub1_then_ssub
    5964             :       0,        // dsub3_then_bsub
    5965             :       0,        // dsub3_then_hsub
    5966             :       0,        // dsub3_then_ssub
    5967             :       0,        // dsub2_then_bsub
    5968             :       0,        // dsub2_then_hsub
    5969             :       0,        // dsub2_then_ssub
    5970             :       0,        // qsub1_then_bsub
    5971             :       0,        // qsub1_then_dsub
    5972             :       0,        // qsub1_then_hsub
    5973             :       0,        // qsub1_then_ssub
    5974             :       0,        // qsub3_then_bsub
    5975             :       0,        // qsub3_then_dsub
    5976             :       0,        // qsub3_then_hsub
    5977             :       0,        // qsub3_then_ssub
    5978             :       0,        // qsub2_then_bsub
    5979             :       0,        // qsub2_then_dsub
    5980             :       0,        // qsub2_then_hsub
    5981             :       0,        // qsub2_then_ssub
    5982             :       0,        // subo64_then_sub_32
    5983             :       0,        // dsub0_dsub1
    5984             :       0,        // dsub0_dsub1_dsub2
    5985             :       0,        // dsub1_dsub2
    5986             :       0,        // dsub1_dsub2_dsub3
    5987             :       0,        // dsub2_dsub3
    5988             :       0,        // dsub_qsub1_then_dsub
    5989             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5990             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    5991             :       0,        // qsub0_qsub1
    5992             :       0,        // qsub0_qsub1_qsub2
    5993             :       0,        // qsub1_qsub2
    5994             :       0,        // qsub1_qsub2_qsub3
    5995             :       0,        // qsub2_qsub3
    5996             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    5997             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5998             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    5999             :       0,        // sub_32_subo64_then_sub_32
    6000             :     },
    6001             :     {   // GPR32
    6002             :       0,        // bsub
    6003             :       0,        // dsub
    6004             :       0,        // dsub0
    6005             :       0,        // dsub1
    6006             :       0,        // dsub2
    6007             :       0,        // dsub3
    6008             :       0,        // hsub
    6009             :       0,        // qhisub
    6010             :       0,        // qsub
    6011             :       0,        // qsub0
    6012             :       0,        // qsub1
    6013             :       0,        // qsub2
    6014             :       0,        // qsub3
    6015             :       0,        // ssub
    6016             :       0,        // sub_32
    6017             :       0,        // sube32
    6018             :       0,        // sube64
    6019             :       0,        // subo32
    6020             :       0,        // subo64
    6021             :       0,        // dsub1_then_bsub
    6022             :       0,        // dsub1_then_hsub
    6023             :       0,        // dsub1_then_ssub
    6024             :       0,        // dsub3_then_bsub
    6025             :       0,        // dsub3_then_hsub
    6026             :       0,        // dsub3_then_ssub
    6027             :       0,        // dsub2_then_bsub
    6028             :       0,        // dsub2_then_hsub
    6029             :       0,        // dsub2_then_ssub
    6030             :       0,        // qsub1_then_bsub
    6031             :       0,        // qsub1_then_dsub
    6032             :       0,        // qsub1_then_hsub
    6033             :       0,        // qsub1_then_ssub
    6034             :       0,        // qsub3_then_bsub
    6035             :       0,        // qsub3_then_dsub
    6036             :       0,        // qsub3_then_hsub
    6037             :       0,        // qsub3_then_ssub
    6038             :       0,        // qsub2_then_bsub
    6039             :       0,        // qsub2_then_dsub
    6040             :       0,        // qsub2_then_hsub
    6041             :       0,        // qsub2_then_ssub
    6042             :       0,        // subo64_then_sub_32
    6043             :       0,        // dsub0_dsub1
    6044             :       0,        // dsub0_dsub1_dsub2
    6045             :       0,        // dsub1_dsub2
    6046             :       0,        // dsub1_dsub2_dsub3
    6047             :       0,        // dsub2_dsub3
    6048             :       0,        // dsub_qsub1_then_dsub
    6049             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6050             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6051             :       0,        // qsub0_qsub1
    6052             :       0,        // qsub0_qsub1_qsub2
    6053             :       0,        // qsub1_qsub2
    6054             :       0,        // qsub1_qsub2_qsub3
    6055             :       0,        // qsub2_qsub3
    6056             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6057             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6058             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6059             :       0,        // sub_32_subo64_then_sub_32
    6060             :     },
    6061             :     {   // GPR32sp
    6062             :       0,        // bsub
    6063             :       0,        // dsub
    6064             :       0,        // dsub0
    6065             :       0,        // dsub1
    6066             :       0,        // dsub2
    6067             :       0,        // dsub3
    6068             :       0,        // hsub
    6069             :       0,        // qhisub
    6070             :       0,        // qsub
    6071             :       0,        // qsub0
    6072             :       0,        // qsub1
    6073             :       0,        // qsub2
    6074             :       0,        // qsub3
    6075             :       0,        // ssub
    6076             :       0,        // sub_32
    6077             :       0,        // sube32
    6078             :       0,        // sube64
    6079             :       0,        // subo32
    6080             :       0,        // subo64
    6081             :       0,        // dsub1_then_bsub
    6082             :       0,        // dsub1_then_hsub
    6083             :       0,        // dsub1_then_ssub
    6084             :       0,        // dsub3_then_bsub
    6085             :       0,        // dsub3_then_hsub
    6086             :       0,        // dsub3_then_ssub
    6087             :       0,        // dsub2_then_bsub
    6088             :       0,        // dsub2_then_hsub
    6089             :       0,        // dsub2_then_ssub
    6090             :       0,        // qsub1_then_bsub
    6091             :       0,        // qsub1_then_dsub
    6092             :       0,        // qsub1_then_hsub
    6093             :       0,        // qsub1_then_ssub
    6094             :       0,        // qsub3_then_bsub
    6095             :       0,        // qsub3_then_dsub
    6096             :       0,        // qsub3_then_hsub
    6097             :       0,        // qsub3_then_ssub
    6098             :       0,        // qsub2_then_bsub
    6099             :       0,        // qsub2_then_dsub
    6100             :       0,        // qsub2_then_hsub
    6101             :       0,        // qsub2_then_ssub
    6102             :       0,        // subo64_then_sub_32
    6103             :       0,        // dsub0_dsub1
    6104             :       0,        // dsub0_dsub1_dsub2
    6105             :       0,        // dsub1_dsub2
    6106             :       0,        // dsub1_dsub2_dsub3
    6107             :       0,        // dsub2_dsub3
    6108             :       0,        // dsub_qsub1_then_dsub
    6109             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6110             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6111             :       0,        // qsub0_qsub1
    6112             :       0,        // qsub0_qsub1_qsub2
    6113             :       0,        // qsub1_qsub2
    6114             :       0,        // qsub1_qsub2_qsub3
    6115             :       0,        // qsub2_qsub3
    6116             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6117             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6118             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6119             :       0,        // sub_32_subo64_then_sub_32
    6120             :     },
    6121             :     {   // GPR32common
    6122             :       0,        // bsub
    6123             :       0,        // dsub
    6124             :       0,        // dsub0
    6125             :       0,        // dsub1
    6126             :       0,        // dsub2
    6127             :       0,        // dsub3
    6128             :       0,        // hsub
    6129             :       0,        // qhisub
    6130             :       0,        // qsub
    6131             :       0,        // qsub0
    6132             :       0,        // qsub1
    6133             :       0,        // qsub2
    6134             :       0,        // qsub3
    6135             :       0,        // ssub
    6136             :       0,        // sub_32
    6137             :       0,        // sube32
    6138             :       0,        // sube64
    6139             :       0,        // subo32
    6140             :       0,        // subo64
    6141             :       0,        // dsub1_then_bsub
    6142             :       0,        // dsub1_then_hsub
    6143             :       0,        // dsub1_then_ssub
    6144             :       0,        // dsub3_then_bsub
    6145             :       0,        // dsub3_then_hsub
    6146             :       0,        // dsub3_then_ssub
    6147             :       0,        // dsub2_then_bsub
    6148             :       0,        // dsub2_then_hsub
    6149             :       0,        // dsub2_then_ssub
    6150             :       0,        // qsub1_then_bsub
    6151             :       0,        // qsub1_then_dsub
    6152             :       0,        // qsub1_then_hsub
    6153             :       0,        // qsub1_then_ssub
    6154             :       0,        // qsub3_then_bsub
    6155             :       0,        // qsub3_then_dsub
    6156             :       0,        // qsub3_then_hsub
    6157             :       0,        // qsub3_then_ssub
    6158             :       0,        // qsub2_then_bsub
    6159             :       0,        // qsub2_then_dsub
    6160             :       0,        // qsub2_then_hsub
    6161             :       0,        // qsub2_then_ssub
    6162             :       0,        // subo64_then_sub_32
    6163             :       0,        // dsub0_dsub1
    6164             :       0,        // dsub0_dsub1_dsub2
    6165             :       0,        // dsub1_dsub2
    6166             :       0,        // dsub1_dsub2_dsub3
    6167             :       0,        // dsub2_dsub3
    6168             :       0,        // dsub_qsub1_then_dsub
    6169             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6170             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6171             :       0,        // qsub0_qsub1
    6172             :       0,        // qsub0_qsub1_qsub2
    6173             :       0,        // qsub1_qsub2
    6174             :       0,        // qsub1_qsub2_qsub3
    6175             :       0,        // qsub2_qsub3
    6176             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6177             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6178             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6179             :       0,        // sub_32_subo64_then_sub_32
    6180             :     },
    6181             :     {   // CCR
    6182             :       0,        // bsub
    6183             :       0,        // dsub
    6184             :       0,        // dsub0
    6185             :       0,        // dsub1
    6186             :       0,        // dsub2
    6187             :       0,        // dsub3
    6188             :       0,        // hsub
    6189             :       0,        // qhisub
    6190             :       0,        // qsub
    6191             :       0,        // qsub0
    6192             :       0,        // qsub1
    6193             :       0,        // qsub2
    6194             :       0,        // qsub3
    6195             :       0,        // ssub
    6196             :       0,        // sub_32
    6197             :       0,        // sube32
    6198             :       0,        // sube64
    6199             :       0,        // subo32
    6200             :       0,        // subo64
    6201             :       0,        // dsub1_then_bsub
    6202             :       0,        // dsub1_then_hsub
    6203             :       0,        // dsub1_then_ssub
    6204             :       0,        // dsub3_then_bsub
    6205             :       0,        // dsub3_then_hsub
    6206             :       0,        // dsub3_then_ssub
    6207             :       0,        // dsub2_then_bsub
    6208             :       0,        // dsub2_then_hsub
    6209             :       0,        // dsub2_then_ssub
    6210             :       0,        // qsub1_then_bsub
    6211             :       0,        // qsub1_then_dsub
    6212             :       0,        // qsub1_then_hsub
    6213             :       0,        // qsub1_then_ssub
    6214             :       0,        // qsub3_then_bsub
    6215             :       0,        // qsub3_then_dsub
    6216             :       0,        // qsub3_then_hsub
    6217             :       0,        // qsub3_then_ssub
    6218             :       0,        // qsub2_then_bsub
    6219             :       0,        // qsub2_then_dsub
    6220             :       0,        // qsub2_then_hsub
    6221             :       0,        // qsub2_then_ssub
    6222             :       0,        // subo64_then_sub_32
    6223             :       0,        // dsub0_dsub1
    6224             :       0,        // dsub0_dsub1_dsub2
    6225             :       0,        // dsub1_dsub2
    6226             :       0,        // dsub1_dsub2_dsub3
    6227             :       0,        // dsub2_dsub3
    6228             :       0,        // dsub_qsub1_then_dsub
    6229             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6230             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6231             :       0,        // qsub0_qsub1
    6232             :       0,        // qsub0_qsub1_qsub2
    6233             :       0,        // qsub1_qsub2
    6234             :       0,        // qsub1_qsub2_qsub3
    6235             :       0,        // qsub2_qsub3
    6236             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6237             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6238             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6239             :       0,        // sub_32_subo64_then_sub_32
    6240             :     },
    6241             :     {   // GPR32sponly
    6242             :       0,        // bsub
    6243             :       0,        // dsub
    6244             :       0,        // dsub0
    6245             :       0,        // dsub1
    6246             :       0,        // dsub2
    6247             :       0,        // dsub3
    6248             :       0,        // hsub
    6249             :       0,        // qhisub
    6250             :       0,        // qsub
    6251             :       0,        // qsub0
    6252             :       0,        // qsub1
    6253             :       0,        // qsub2
    6254             :       0,        // qsub3
    6255             :       0,        // ssub
    6256             :       0,        // sub_32
    6257             :       0,        // sube32
    6258             :       0,        // sube64
    6259             :       0,        // subo32
    6260             :       0,        // subo64
    6261             :       0,        // dsub1_then_bsub
    6262             :       0,        // dsub1_then_hsub
    6263             :       0,        // dsub1_then_ssub
    6264             :       0,        // dsub3_then_bsub
    6265             :       0,        // dsub3_then_hsub
    6266             :       0,        // dsub3_then_ssub
    6267             :       0,        // dsub2_then_bsub
    6268             :       0,        // dsub2_then_hsub
    6269             :       0,        // dsub2_then_ssub
    6270             :       0,        // qsub1_then_bsub
    6271             :       0,        // qsub1_then_dsub
    6272             :       0,        // qsub1_then_hsub
    6273             :       0,        // qsub1_then_ssub
    6274             :       0,        // qsub3_then_bsub
    6275             :       0,        // qsub3_then_dsub
    6276             :       0,        // qsub3_then_hsub
    6277             :       0,        // qsub3_then_ssub
    6278             :       0,        // qsub2_then_bsub
    6279             :       0,        // qsub2_then_dsub
    6280             :       0,        // qsub2_then_hsub
    6281             :       0,        // qsub2_then_ssub
    6282             :       0,        // subo64_then_sub_32
    6283             :       0,        // dsub0_dsub1
    6284             :       0,        // dsub0_dsub1_dsub2
    6285             :       0,        // dsub1_dsub2
    6286             :       0,        // dsub1_dsub2_dsub3
    6287             :       0,        // dsub2_dsub3
    6288             :       0,        // dsub_qsub1_then_dsub
    6289             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6290             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6291             :       0,        // qsub0_qsub1
    6292             :       0,        // qsub0_qsub1_qsub2
    6293             :       0,        // qsub1_qsub2
    6294             :       0,        // qsub1_qsub2_qsub3
    6295             :       0,        // qsub2_qsub3
    6296             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6297             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6298             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6299             :       0,        // sub_32_subo64_then_sub_32
    6300             :     },
    6301             :     {   // WSeqPairsClass
    6302             :       0,        // bsub
    6303             :       0,        // dsub
    6304             :       0,        // dsub0
    6305             :       0,        // dsub1
    6306             :       0,        // dsub2
    6307             :       0,        // dsub3
    6308             :       0,        // hsub
    6309             :       0,        // qhisub
    6310             :       0,        // qsub
    6311             :       0,        // qsub0
    6312             :       0,        // qsub1
    6313             :       0,        // qsub2
    6314             :       0,        // qsub3
    6315             :       0,        // ssub
    6316             :       0,        // sub_32
    6317             :       10,       // sube32 -> WSeqPairsClass
    6318             :       0,        // sube64
    6319             :       10,       // subo32 -> WSeqPairsClass
    6320             :       0,        // subo64
    6321             :       0,        // dsub1_then_bsub
    6322             :       0,        // dsub1_then_hsub
    6323             :       0,        // dsub1_then_ssub
    6324             :       0,        // dsub3_then_bsub
    6325             :       0,        // dsub3_then_hsub
    6326             :       0,        // dsub3_then_ssub
    6327             :       0,        // dsub2_then_bsub
    6328             :       0,        // dsub2_then_hsub
    6329             :       0,        // dsub2_then_ssub
    6330             :       0,        // qsub1_then_bsub
    6331             :       0,        // qsub1_then_dsub
    6332             :       0,        // qsub1_then_hsub
    6333             :       0,        // qsub1_then_ssub
    6334             :       0,        // qsub3_then_bsub
    6335             :       0,        // qsub3_then_dsub
    6336             :       0,        // qsub3_then_hsub
    6337             :       0,        // qsub3_then_ssub
    6338             :       0,        // qsub2_then_bsub
    6339             :       0,        // qsub2_then_dsub
    6340             :       0,        // qsub2_then_hsub
    6341             :       0,        // qsub2_then_ssub
    6342             :       0,        // subo64_then_sub_32
    6343             :       0,        // dsub0_dsub1
    6344             :       0,        // dsub0_dsub1_dsub2
    6345             :       0,        // dsub1_dsub2
    6346             :       0,        // dsub1_dsub2_dsub3
    6347             :       0,        // dsub2_dsub3
    6348             :       0,        // dsub_qsub1_then_dsub
    6349             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6350             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6351             :       0,        // qsub0_qsub1
    6352             :       0,        // qsub0_qsub1_qsub2
    6353             :       0,        // qsub1_qsub2
    6354             :       0,        // qsub1_qsub2_qsub3
    6355             :       0,        // qsub2_qsub3
    6356             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6357             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6358             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6359             :       0,        // sub_32_subo64_then_sub_32
    6360             :     },
    6361             :     {   // WSeqPairsClass_with_sube32_in_GPR32common
    6362             :       0,        // bsub
    6363             :       0,        // dsub
    6364             :       0,        // dsub0
    6365             :       0,        // dsub1
    6366             :       0,        // dsub2
    6367             :       0,        // dsub3
    6368             :       0,        // hsub
    6369             :       0,        // qhisub
    6370             :       0,        // qsub
    6371             :       0,        // qsub0
    6372             :       0,        // qsub1
    6373             :       0,        // qsub2
    6374             :       0,        // qsub3
    6375             :       0,        // ssub
    6376             :       0,        // sub_32
    6377             :       11,       // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common
    6378             :       0,        // sube64
    6379             :       11,       // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common
    6380             :       0,        // subo64
    6381             :       0,        // dsub1_then_bsub
    6382             :       0,        // dsub1_then_hsub
    6383             :       0,        // dsub1_then_ssub
    6384             :       0,        // dsub3_then_bsub
    6385             :       0,        // dsub3_then_hsub
    6386             :       0,        // dsub3_then_ssub
    6387             :       0,        // dsub2_then_bsub
    6388             :       0,        // dsub2_then_hsub
    6389             :       0,        // dsub2_then_ssub
    6390             :       0,        // qsub1_then_bsub
    6391             :       0,        // qsub1_then_dsub
    6392             :       0,        // qsub1_then_hsub
    6393             :       0,        // qsub1_then_ssub
    6394             :       0,        // qsub3_then_bsub
    6395             :       0,        // qsub3_then_dsub
    6396             :       0,        // qsub3_then_hsub
    6397             :       0,        // qsub3_then_ssub
    6398             :       0,        // qsub2_then_bsub
    6399             :       0,        // qsub2_then_dsub
    6400             :       0,        // qsub2_then_hsub
    6401             :       0,        // qsub2_then_ssub
    6402             :       0,        // subo64_then_sub_32
    6403             :       0,        // dsub0_dsub1
    6404             :       0,        // dsub0_dsub1_dsub2
    6405             :       0,        // dsub1_dsub2
    6406             :       0,        // dsub1_dsub2_dsub3
    6407             :       0,        // dsub2_dsub3
    6408             :       0,        // dsub_qsub1_then_dsub
    6409             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6410             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6411             :       0,        // qsub0_qsub1
    6412             :       0,        // qsub0_qsub1_qsub2
    6413             :       0,        // qsub1_qsub2
    6414             :       0,        // qsub1_qsub2_qsub3
    6415             :       0,        // qsub2_qsub3
    6416             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6417             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6418             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6419             :       0,        // sub_32_subo64_then_sub_32
    6420             :     },
    6421             :     {   // WSeqPairsClass_with_subo32_in_GPR32common
    6422             :       0,        // bsub
    6423             :       0,        // dsub
    6424             :       0,        // dsub0
    6425             :       0,        // dsub1
    6426             :       0,        // dsub2
    6427             :       0,        // dsub3
    6428             :       0,        // hsub
    6429             :       0,        // qhisub
    6430             :       0,        // qsub
    6431             :       0,        // qsub0
    6432             :       0,        // qsub1
    6433             :       0,        // qsub2
    6434             :       0,        // qsub3
    6435             :       0,        // ssub
    6436             :       0,        // sub_32
    6437             :       12,       // sube32 -> WSeqPairsClass_with_subo32_in_GPR32common
    6438             :       0,        // sube64
    6439             :       12,       // subo32 -> WSeqPairsClass_with_subo32_in_GPR32common
    6440             :       0,        // subo64
    6441             :       0,        // dsub1_then_bsub
    6442             :       0,        // dsub1_then_hsub
    6443             :       0,        // dsub1_then_ssub
    6444             :       0,        // dsub3_then_bsub
    6445             :       0,        // dsub3_then_hsub
    6446             :       0,        // dsub3_then_ssub
    6447             :       0,        // dsub2_then_bsub
    6448             :       0,        // dsub2_then_hsub
    6449             :       0,        // dsub2_then_ssub
    6450             :       0,        // qsub1_then_bsub
    6451             :       0,        // qsub1_then_dsub
    6452             :       0,        // qsub1_then_hsub
    6453             :       0,        // qsub1_then_ssub
    6454             :       0,        // qsub3_then_bsub
    6455             :       0,        // qsub3_then_dsub
    6456             :       0,        // qsub3_then_hsub
    6457             :       0,        // qsub3_then_ssub
    6458             :       0,        // qsub2_then_bsub
    6459             :       0,        // qsub2_then_dsub
    6460             :       0,        // qsub2_then_hsub
    6461             :       0,        // qsub2_then_ssub
    6462             :       0,        // subo64_then_sub_32
    6463             :       0,        // dsub0_dsub1
    6464             :       0,        // dsub0_dsub1_dsub2
    6465             :       0,        // dsub1_dsub2
    6466             :       0,        // dsub1_dsub2_dsub3
    6467             :       0,        // dsub2_dsub3
    6468             :       0,        // dsub_qsub1_then_dsub
    6469             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6470             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6471             :       0,        // qsub0_qsub1
    6472             :       0,        // qsub0_qsub1_qsub2
    6473             :       0,        // qsub1_qsub2
    6474             :       0,        // qsub1_qsub2_qsub3
    6475             :       0,        // qsub2_qsub3
    6476             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6477             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6478             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6479             :       0,        // sub_32_subo64_then_sub_32
    6480             :     },
    6481             :     {   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    6482             :       0,        // bsub
    6483             :       0,        // dsub
    6484             :       0,        // dsub0
    6485             :       0,        // dsub1
    6486             :       0,        // dsub2
    6487             :       0,        // dsub3
    6488             :       0,        // hsub
    6489             :       0,        // qhisub
    6490             :       0,        // qsub
    6491             :       0,        // qsub0
    6492             :       0,        // qsub1
    6493             :       0,        // qsub2
    6494             :       0,        // qsub3
    6495             :       0,        // ssub
    6496             :       0,        // sub_32
    6497             :       13,       // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    6498             :       0,        // sube64
    6499             :       13,       // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    6500             :       0,        // subo64
    6501             :       0,        // dsub1_then_bsub
    6502             :       0,        // dsub1_then_hsub
    6503             :       0,        // dsub1_then_ssub
    6504             :       0,        // dsub3_then_bsub
    6505             :       0,        // dsub3_then_hsub
    6506             :       0,        // dsub3_then_ssub
    6507             :       0,        // dsub2_then_bsub
    6508             :       0,        // dsub2_then_hsub
    6509             :       0,        // dsub2_then_ssub
    6510             :       0,        // qsub1_then_bsub
    6511             :       0,        // qsub1_then_dsub
    6512             :       0,        // qsub1_then_hsub
    6513             :       0,        // qsub1_then_ssub
    6514             :       0,        // qsub3_then_bsub
    6515             :       0,        // qsub3_then_dsub
    6516             :       0,        // qsub3_then_hsub
    6517             :       0,        // qsub3_then_ssub
    6518             :       0,        // qsub2_then_bsub
    6519             :       0,        // qsub2_then_dsub
    6520             :       0,        // qsub2_then_hsub
    6521             :       0,        // qsub2_then_ssub
    6522             :       0,        // subo64_then_sub_32
    6523             :       0,        // dsub0_dsub1
    6524             :       0,        // dsub0_dsub1_dsub2
    6525             :       0,        // dsub1_dsub2
    6526             :       0,        // dsub1_dsub2_dsub3
    6527             :       0,        // dsub2_dsub3
    6528             :       0,        // dsub_qsub1_then_dsub
    6529             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6530             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6531             :       0,        // qsub0_qsub1
    6532             :       0,        // qsub0_qsub1_qsub2
    6533             :       0,        // qsub1_qsub2
    6534             :       0,        // qsub1_qsub2_qsub3
    6535             :       0,        // qsub2_qsub3
    6536             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6537             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6538             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6539             :       0,        // sub_32_subo64_then_sub_32
    6540             :     },
    6541             :     {   // GPR64all
    6542             :       0,        // bsub
    6543             :       0,        // dsub
    6544             :       0,        // dsub0
    6545             :       0,        // dsub1
    6546             :       0,        // dsub2
    6547             :       0,        // dsub3
    6548             :       0,        // hsub
    6549             :       0,        // qhisub
    6550             :       0,        // qsub
    6551             :       0,        // qsub0
    6552             :       0,        // qsub1
    6553             :       0,        // qsub2
    6554             :       0,        // qsub3
    6555             :       0,        // ssub
    6556             :       14,       // sub_32 -> GPR64all
    6557             :       0,        // sube32
    6558             :       0,        // sube64
    6559             :       0,        // subo32
    6560             :       0,        // subo64
    6561             :       0,        // dsub1_then_bsub
    6562             :       0,        // dsub1_then_hsub
    6563             :       0,        // dsub1_then_ssub
    6564             :       0,        // dsub3_then_bsub
    6565             :       0,        // dsub3_then_hsub
    6566             :       0,        // dsub3_then_ssub
    6567             :       0,        // dsub2_then_bsub
    6568             :       0,        // dsub2_then_hsub
    6569             :       0,        // dsub2_then_ssub
    6570             :       0,        // qsub1_then_bsub
    6571             :       0,        // qsub1_then_dsub
    6572             :       0,        // qsub1_then_hsub
    6573             :       0,        // qsub1_then_ssub
    6574             :       0,        // qsub3_then_bsub
    6575             :       0,        // qsub3_then_dsub
    6576             :       0,        // qsub3_then_hsub
    6577             :       0,        // qsub3_then_ssub
    6578             :       0,        // qsub2_then_bsub
    6579             :       0,        // qsub2_then_dsub
    6580             :       0,        // qsub2_then_hsub
    6581             :       0,        // qsub2_then_ssub
    6582             :       0,        // subo64_then_sub_32
    6583             :       0,        // dsub0_dsub1
    6584             :       0,        // dsub0_dsub1_dsub2
    6585             :       0,        // dsub1_dsub2
    6586             :       0,        // dsub1_dsub2_dsub3
    6587             :       0,        // dsub2_dsub3
    6588             :       0,        // dsub_qsub1_then_dsub
    6589             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6590             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6591             :       0,        // qsub0_qsub1
    6592             :       0,        // qsub0_qsub1_qsub2
    6593             :       0,        // qsub1_qsub2
    6594             :       0,        // qsub1_qsub2_qsub3
    6595             :       0,        // qsub2_qsub3
    6596             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6597             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6598             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6599             :       0,        // sub_32_subo64_then_sub_32
    6600             :     },
    6601             :     {   // FPR64
    6602             :       15,       // bsub -> FPR64
    6603             :       0,        // dsub
    6604             :       0,        // dsub0
    6605             :       0,        // dsub1
    6606             :       0,        // dsub2
    6607             :       0,        // dsub3
    6608             :       15,       // hsub -> FPR64
    6609             :       0,        // qhisub
    6610             :       0,        // qsub
    6611             :       0,        // qsub0
    6612             :       0,        // qsub1
    6613             :       0,        // qsub2
    6614             :       0,        // qsub3
    6615             :       15,       // ssub -> FPR64
    6616             :       0,        // sub_32
    6617             :       0,        // sube32
    6618             :       0,        // sube64
    6619             :       0,        // subo32
    6620             :       0,        // subo64
    6621             :       0,        // dsub1_then_bsub
    6622             :       0,        // dsub1_then_hsub
    6623             :       0,        // dsub1_then_ssub
    6624             :       0,        // dsub3_then_bsub
    6625             :       0,        // dsub3_then_hsub
    6626             :       0,        // dsub3_then_ssub
    6627             :       0,        // dsub2_then_bsub
    6628             :       0,        // dsub2_then_hsub
    6629             :       0,        // dsub2_then_ssub
    6630             :       0,        // qsub1_then_bsub
    6631             :       0,        // qsub1_then_dsub
    6632             :       0,        // qsub1_then_hsub
    6633             :       0,        // qsub1_then_ssub
    6634             :       0,        // qsub3_then_bsub
    6635             :       0,        // qsub3_then_dsub
    6636             :       0,        // qsub3_then_hsub
    6637             :       0,        // qsub3_then_ssub
    6638             :       0,        // qsub2_then_bsub
    6639             :       0,        // qsub2_then_dsub
    6640             :       0,        // qsub2_then_hsub
    6641             :       0,        // qsub2_then_ssub
    6642             :       0,        // subo64_then_sub_32
    6643             :       0,        // dsub0_dsub1
    6644             :       0,        // dsub0_dsub1_dsub2
    6645             :       0,        // dsub1_dsub2
    6646             :       0,        // dsub1_dsub2_dsub3
    6647             :       0,        // dsub2_dsub3
    6648             :       0,        // dsub_qsub1_then_dsub
    6649             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6650             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6651             :       0,        // qsub0_qsub1
    6652             :       0,        // qsub0_qsub1_qsub2
    6653             :       0,        // qsub1_qsub2
    6654             :       0,        // qsub1_qsub2_qsub3
    6655             :       0,        // qsub2_qsub3
    6656             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6657             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6658             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6659             :       0,        // sub_32_subo64_then_sub_32
    6660             :     },
    6661             :     {   // GPR64
    6662             :       0,        // bsub
    6663             :       0,        // dsub
    6664             :       0,        // dsub0
    6665             :       0,        // dsub1
    6666             :       0,        // dsub2
    6667             :       0,        // dsub3
    6668             :       0,        // hsub
    6669             :       0,        // qhisub
    6670             :       0,        // qsub
    6671             :       0,        // qsub0
    6672             :       0,        // qsub1
    6673             :       0,        // qsub2
    6674             :       0,        // qsub3
    6675             :       0,        // ssub
    6676             :       16,       // sub_32 -> GPR64
    6677             :       0,        // sube32
    6678             :       0,        // sube64
    6679             :       0,        // subo32
    6680             :       0,        // subo64
    6681             :       0,        // dsub1_then_bsub
    6682             :       0,        // dsub1_then_hsub
    6683             :       0,        // dsub1_then_ssub
    6684             :       0,        // dsub3_then_bsub
    6685             :       0,        // dsub3_then_hsub
    6686             :       0,        // dsub3_then_ssub
    6687             :       0,        // dsub2_then_bsub
    6688             :       0,        // dsub2_then_hsub
    6689             :       0,        // dsub2_then_ssub
    6690             :       0,        // qsub1_then_bsub
    6691             :       0,        // qsub1_then_dsub
    6692             :       0,        // qsub1_then_hsub
    6693             :       0,        // qsub1_then_ssub
    6694             :       0,        // qsub3_then_bsub
    6695             :       0,        // qsub3_then_dsub
    6696             :       0,        // qsub3_then_hsub
    6697             :       0,        // qsub3_then_ssub
    6698             :       0,        // qsub2_then_bsub
    6699             :       0,        // qsub2_then_dsub
    6700             :       0,        // qsub2_then_hsub
    6701             :       0,        // qsub2_then_ssub
    6702             :       0,        // subo64_then_sub_32
    6703             :       0,        // dsub0_dsub1
    6704             :       0,        // dsub0_dsub1_dsub2
    6705             :       0,        // dsub1_dsub2
    6706             :       0,        // dsub1_dsub2_dsub3
    6707             :       0,        // dsub2_dsub3
    6708             :       0,        // dsub_qsub1_then_dsub
    6709             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6710             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6711             :       0,        // qsub0_qsub1
    6712             :       0,        // qsub0_qsub1_qsub2
    6713             :       0,        // qsub1_qsub2
    6714             :       0,        // qsub1_qsub2_qsub3
    6715             :       0,        // qsub2_qsub3
    6716             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6717             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6718             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6719             :       0,        // sub_32_subo64_then_sub_32
    6720             :     },
    6721             :     {   // GPR64sp
    6722             :       0,        // bsub
    6723             :       0,        // dsub
    6724             :       0,        // dsub0
    6725             :       0,        // dsub1
    6726             :       0,        // dsub2
    6727             :       0,        // dsub3
    6728             :       0,        // hsub
    6729             :       0,        // qhisub
    6730             :       0,        // qsub
    6731             :       0,        // qsub0
    6732             :       0,        // qsub1
    6733             :       0,        // qsub2
    6734             :       0,        // qsub3
    6735             :       0,        // ssub
    6736             :       17,       // sub_32 -> GPR64sp
    6737             :       0,        // sube32
    6738             :       0,        // sube64
    6739             :       0,        // subo32
    6740             :       0,        // subo64
    6741             :       0,        // dsub1_then_bsub
    6742             :       0,        // dsub1_then_hsub
    6743             :       0,        // dsub1_then_ssub
    6744             :       0,        // dsub3_then_bsub
    6745             :       0,        // dsub3_then_hsub
    6746             :       0,        // dsub3_then_ssub
    6747             :       0,        // dsub2_then_bsub
    6748             :       0,        // dsub2_then_hsub
    6749             :       0,        // dsub2_then_ssub
    6750             :       0,        // qsub1_then_bsub
    6751             :       0,        // qsub1_then_dsub
    6752             :       0,        // qsub1_then_hsub
    6753             :       0,        // qsub1_then_ssub
    6754             :       0,        // qsub3_then_bsub
    6755             :       0,        // qsub3_then_dsub
    6756             :       0,        // qsub3_then_hsub
    6757             :       0,        // qsub3_then_ssub
    6758             :       0,        // qsub2_then_bsub
    6759             :       0,        // qsub2_then_dsub
    6760             :       0,        // qsub2_then_hsub
    6761             :       0,        // qsub2_then_ssub
    6762             :       0,        // subo64_then_sub_32
    6763             :       0,        // dsub0_dsub1
    6764             :       0,        // dsub0_dsub1_dsub2
    6765             :       0,        // dsub1_dsub2
    6766             :       0,        // dsub1_dsub2_dsub3
    6767             :       0,        // dsub2_dsub3
    6768             :       0,        // dsub_qsub1_then_dsub
    6769             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6770             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6771             :       0,        // qsub0_qsub1
    6772             :       0,        // qsub0_qsub1_qsub2
    6773             :       0,        // qsub1_qsub2
    6774             :       0,        // qsub1_qsub2_qsub3
    6775             :       0,        // qsub2_qsub3
    6776             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6777             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6778             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6779             :       0,        // sub_32_subo64_then_sub_32
    6780             :     },
    6781             :     {   // GPR64common
    6782             :       0,        // bsub
    6783             :       0,        // dsub
    6784             :       0,        // dsub0
    6785             :       0,        // dsub1
    6786             :       0,        // dsub2
    6787             :       0,        // dsub3
    6788             :       0,        // hsub
    6789             :       0,        // qhisub
    6790             :       0,        // qsub
    6791             :       0,        // qsub0
    6792             :       0,        // qsub1
    6793             :       0,        // qsub2
    6794             :       0,        // qsub3
    6795             :       0,        // ssub
    6796             :       18,       // sub_32 -> GPR64common
    6797             :       0,        // sube32
    6798             :       0,        // sube64
    6799             :       0,        // subo32
    6800             :       0,        // subo64
    6801             :       0,        // dsub1_then_bsub
    6802             :       0,        // dsub1_then_hsub
    6803             :       0,        // dsub1_then_ssub
    6804             :       0,        // dsub3_then_bsub
    6805             :       0,        // dsub3_then_hsub
    6806             :       0,        // dsub3_then_ssub
    6807             :       0,        // dsub2_then_bsub
    6808             :       0,        // dsub2_then_hsub
    6809             :       0,        // dsub2_then_ssub
    6810             :       0,        // qsub1_then_bsub
    6811             :       0,        // qsub1_then_dsub
    6812             :       0,        // qsub1_then_hsub
    6813             :       0,        // qsub1_then_ssub
    6814             :       0,        // qsub3_then_bsub
    6815             :       0,        // qsub3_then_dsub
    6816             :       0,        // qsub3_then_hsub
    6817             :       0,        // qsub3_then_ssub
    6818             :       0,        // qsub2_then_bsub
    6819             :       0,        // qsub2_then_dsub
    6820             :       0,        // qsub2_then_hsub
    6821             :       0,        // qsub2_then_ssub
    6822             :       0,        // subo64_then_sub_32
    6823             :       0,        // dsub0_dsub1
    6824             :       0,        // dsub0_dsub1_dsub2
    6825             :       0,        // dsub1_dsub2
    6826             :       0,        // dsub1_dsub2_dsub3
    6827             :       0,        // dsub2_dsub3
    6828             :       0,        // dsub_qsub1_then_dsub
    6829             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6830             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6831             :       0,        // qsub0_qsub1
    6832             :       0,        // qsub0_qsub1_qsub2
    6833             :       0,        // qsub1_qsub2
    6834             :       0,        // qsub1_qsub2_qsub3
    6835             :       0,        // qsub2_qsub3
    6836             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6837             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6838             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6839             :       0,        // sub_32_subo64_then_sub_32
    6840             :     },
    6841             :     {   // tcGPR64
    6842             :       0,        // bsub
    6843             :       0,        // dsub
    6844             :       0,        // dsub0
    6845             :       0,        // dsub1
    6846             :       0,        // dsub2
    6847             :       0,        // dsub3
    6848             :       0,        // hsub
    6849             :       0,        // qhisub
    6850             :       0,        // qsub
    6851             :       0,        // qsub0
    6852             :       0,        // qsub1
    6853             :       0,        // qsub2
    6854             :       0,        // qsub3
    6855             :       0,        // ssub
    6856             :       19,       // sub_32 -> tcGPR64
    6857             :       0,        // sube32
    6858             :       0,        // sube64
    6859             :       0,        // subo32
    6860             :       0,        // subo64
    6861             :       0,        // dsub1_then_bsub
    6862             :       0,        // dsub1_then_hsub
    6863             :       0,        // dsub1_then_ssub
    6864             :       0,        // dsub3_then_bsub
    6865             :       0,        // dsub3_then_hsub
    6866             :       0,        // dsub3_then_ssub
    6867             :       0,        // dsub2_then_bsub
    6868             :       0,        // dsub2_then_hsub
    6869             :       0,        // dsub2_then_ssub
    6870             :       0,        // qsub1_then_bsub
    6871             :       0,        // qsub1_then_dsub
    6872             :       0,        // qsub1_then_hsub
    6873             :       0,        // qsub1_then_ssub
    6874             :       0,        // qsub3_then_bsub
    6875             :       0,        // qsub3_then_dsub
    6876             :       0,        // qsub3_then_hsub
    6877             :       0,        // qsub3_then_ssub
    6878             :       0,        // qsub2_then_bsub
    6879             :       0,        // qsub2_then_dsub
    6880             :       0,        // qsub2_then_hsub
    6881             :       0,        // qsub2_then_ssub
    6882             :       0,        // subo64_then_sub_32
    6883             :       0,        // dsub0_dsub1
    6884             :       0,        // dsub0_dsub1_dsub2
    6885             :       0,        // dsub1_dsub2
    6886             :       0,        // dsub1_dsub2_dsub3
    6887             :       0,        // dsub2_dsub3
    6888             :       0,        // dsub_qsub1_then_dsub
    6889             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6890             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6891             :       0,        // qsub0_qsub1
    6892             :       0,        // qsub0_qsub1_qsub2
    6893             :       0,        // qsub1_qsub2
    6894             :       0,        // qsub1_qsub2_qsub3
    6895             :       0,        // qsub2_qsub3
    6896             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6897             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6898             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6899             :       0,        // sub_32_subo64_then_sub_32
    6900             :     },
    6901             :     {   // GPR64sponly
    6902             :       0,        // bsub
    6903             :       0,        // dsub
    6904             :       0,        // dsub0
    6905             :       0,        // dsub1
    6906             :       0,        // dsub2
    6907             :       0,        // dsub3
    6908             :       0,        // hsub
    6909             :       0,        // qhisub
    6910             :       0,        // qsub
    6911             :       0,        // qsub0
    6912             :       0,        // qsub1
    6913             :       0,        // qsub2
    6914             :       0,        // qsub3
    6915             :       0,        // ssub
    6916             :       20,       // sub_32 -> GPR64sponly
    6917             :       0,        // sube32
    6918             :       0,        // sube64
    6919             :       0,        // subo32
    6920             :       0,        // subo64
    6921             :       0,        // dsub1_then_bsub
    6922             :       0,        // dsub1_then_hsub
    6923             :       0,        // dsub1_then_ssub
    6924             :       0,        // dsub3_then_bsub
    6925             :       0,        // dsub3_then_hsub
    6926             :       0,        // dsub3_then_ssub
    6927             :       0,        // dsub2_then_bsub
    6928             :       0,        // dsub2_then_hsub
    6929             :       0,        // dsub2_then_ssub
    6930             :       0,        // qsub1_then_bsub
    6931             :       0,        // qsub1_then_dsub
    6932             :       0,        // qsub1_then_hsub
    6933             :       0,        // qsub1_then_ssub
    6934             :       0,        // qsub3_then_bsub
    6935             :       0,        // qsub3_then_dsub
    6936             :       0,        // qsub3_then_hsub
    6937             :       0,        // qsub3_then_ssub
    6938             :       0,        // qsub2_then_bsub
    6939             :       0,        // qsub2_then_dsub
    6940             :       0,        // qsub2_then_hsub
    6941             :       0,        // qsub2_then_ssub
    6942             :       0,        // subo64_then_sub_32
    6943             :       0,        // dsub0_dsub1
    6944             :       0,        // dsub0_dsub1_dsub2
    6945             :       0,        // dsub1_dsub2
    6946             :       0,        // dsub1_dsub2_dsub3
    6947             :       0,        // dsub2_dsub3
    6948             :       0,        // dsub_qsub1_then_dsub
    6949             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6950             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6951             :       0,        // qsub0_qsub1
    6952             :       0,        // qsub0_qsub1_qsub2
    6953             :       0,        // qsub1_qsub2
    6954             :       0,        // qsub1_qsub2_qsub3
    6955             :       0,        // qsub2_qsub3
    6956             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6957             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6958             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6959             :       0,        // sub_32_subo64_then_sub_32
    6960             :     },
    6961             :     {   // DD
    6962             :       21,       // bsub -> DD
    6963             :       0,        // dsub
    6964             :       21,       // dsub0 -> DD
    6965             :       21,       // dsub1 -> DD
    6966             :       0,        // dsub2
    6967             :       0,        // dsub3
    6968             :       21,       // hsub -> DD
    6969             :       0,        // qhisub
    6970             :       0,        // qsub
    6971             :       0,        // qsub0
    6972             :       0,        // qsub1
    6973             :       0,        // qsub2
    6974             :       0,        // qsub3
    6975             :       21,       // ssub -> DD
    6976             :       0,        // sub_32
    6977             :       0,        // sube32
    6978             :       0,        // sube64
    6979             :       0,        // subo32
    6980             :       0,        // subo64
    6981             :       21,       // dsub1_then_bsub -> DD
    6982             :       21,       // dsub1_then_hsub -> DD
    6983             :       21,       // dsub1_then_ssub -> DD
    6984             :       0,        // dsub3_then_bsub
    6985             :       0,        // dsub3_then_hsub
    6986             :       0,        // dsub3_then_ssub
    6987             :       0,        // dsub2_then_bsub
    6988             :       0,        // dsub2_then_hsub
    6989             :       0,        // dsub2_then_ssub
    6990             :       0,        // qsub1_then_bsub
    6991             :       0,        // qsub1_then_dsub
    6992             :       0,        // qsub1_then_hsub
    6993             :       0,        // qsub1_then_ssub
    6994             :       0,        // qsub3_then_bsub
    6995             :       0,        // qsub3_then_dsub
    6996             :       0,        // qsub3_then_hsub
    6997             :       0,        // qsub3_then_ssub
    6998             :       0,        // qsub2_then_bsub
    6999             :       0,        // qsub2_then_dsub
    7000             :       0,        // qsub2_then_hsub
    7001             :       0,        // qsub2_then_ssub
    7002             :       0,        // subo64_then_sub_32
    7003             :       0,        // dsub0_dsub1
    7004             :       0,        // dsub0_dsub1_dsub2
    7005             :       0,        // dsub1_dsub2
    7006             :       0,        // dsub1_dsub2_dsub3
    7007             :       0,        // dsub2_dsub3
    7008             :       0,        // dsub_qsub1_then_dsub
    7009             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7010             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7011             :       0,        // qsub0_qsub1
    7012             :       0,        // qsub0_qsub1_qsub2
    7013             :       0,        // qsub1_qsub2
    7014             :       0,        // qsub1_qsub2_qsub3
    7015             :       0,        // qsub2_qsub3
    7016             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7017             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7018             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7019             :       0,        // sub_32_subo64_then_sub_32
    7020             :     },
    7021             :     {   // XSeqPairsClass
    7022             :       0,        // bsub
    7023             :       0,        // dsub
    7024             :       0,        // dsub0
    7025             :       0,        // dsub1
    7026             :       0,        // dsub2
    7027             :       0,        // dsub3
    7028             :       0,        // hsub
    7029             :       0,        // qhisub
    7030             :       0,        // qsub
    7031             :       0,        // qsub0
    7032             :       0,        // qsub1
    7033             :       0,        // qsub2
    7034             :       0,        // qsub3
    7035             :       0,        // ssub
    7036             :       22,       // sub_32 -> XSeqPairsClass
    7037             :       0,        // sube32
    7038             :       22,       // sube64 -> XSeqPairsClass
    7039             :       0,        // subo32
    7040             :       22,       // subo64 -> XSeqPairsClass
    7041             :       0,        // dsub1_then_bsub
    7042             :       0,        // dsub1_then_hsub
    7043             :       0,        // dsub1_then_ssub
    7044             :       0,        // dsub3_then_bsub
    7045             :       0,        // dsub3_then_hsub
    7046             :       0,        // dsub3_then_ssub
    7047             :       0,        // dsub2_then_bsub
    7048             :       0,        // dsub2_then_hsub
    7049             :       0,        // dsub2_then_ssub
    7050             :       0,        // qsub1_then_bsub
    7051             :       0,        // qsub1_then_dsub
    7052             :       0,        // qsub1_then_hsub
    7053             :       0,        // qsub1_then_ssub
    7054             :       0,        // qsub3_then_bsub
    7055             :       0,        // qsub3_then_dsub
    7056             :       0,        // qsub3_then_hsub
    7057             :       0,        // qsub3_then_ssub
    7058             :       0,        // qsub2_then_bsub
    7059             :       0,        // qsub2_then_dsub
    7060             :       0,        // qsub2_then_hsub
    7061             :       0,        // qsub2_then_ssub
    7062             :       22,       // subo64_then_sub_32 -> XSeqPairsClass
    7063             :       0,        // dsub0_dsub1
    7064             :       0,        // dsub0_dsub1_dsub2
    7065             :       0,        // dsub1_dsub2
    7066             :       0,        // dsub1_dsub2_dsub3
    7067             :       0,        // dsub2_dsub3
    7068             :       0,        // dsub_qsub1_then_dsub
    7069             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7070             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7071             :       0,        // qsub0_qsub1
    7072             :       0,        // qsub0_qsub1_qsub2
    7073             :       0,        // qsub1_qsub2
    7074             :       0,        // qsub1_qsub2_qsub3
    7075             :       0,        // qsub2_qsub3
    7076             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7077             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7078             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7079             :       22,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass
    7080             :     },
    7081             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common
    7082             :       0,        // bsub
    7083             :       0,        // dsub
    7084             :       0,        // dsub0
    7085             :       0,        // dsub1
    7086             :       0,        // dsub2
    7087             :       0,        // dsub3
    7088             :       0,        // hsub
    7089             :       0,        // qhisub
    7090             :       0,        // qsub
    7091             :       0,        // qsub0
    7092             :       0,        // qsub1
    7093             :       0,        // qsub2
    7094             :       0,        // qsub3
    7095             :       0,        // ssub
    7096             :       23,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7097             :       0,        // sube32
    7098             :       23,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7099             :       0,        // subo32
    7100             :       23,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7101             :       0,        // dsub1_then_bsub
    7102             :       0,        // dsub1_then_hsub
    7103             :       0,        // dsub1_then_ssub
    7104             :       0,        // dsub3_then_bsub
    7105             :       0,        // dsub3_then_hsub
    7106             :       0,        // dsub3_then_ssub
    7107             :       0,        // dsub2_then_bsub
    7108             :       0,        // dsub2_then_hsub
    7109             :       0,        // dsub2_then_ssub
    7110             :       0,        // qsub1_then_bsub
    7111             :       0,        // qsub1_then_dsub
    7112             :       0,        // qsub1_then_hsub
    7113             :       0,        // qsub1_then_ssub
    7114             :       0,        // qsub3_then_bsub
    7115             :       0,        // qsub3_then_dsub
    7116             :       0,        // qsub3_then_hsub
    7117             :       0,        // qsub3_then_ssub
    7118             :       0,        // qsub2_then_bsub
    7119             :       0,        // qsub2_then_dsub
    7120             :       0,        // qsub2_then_hsub
    7121             :       0,        // qsub2_then_ssub
    7122             :       23,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7123             :       0,        // dsub0_dsub1
    7124             :       0,        // dsub0_dsub1_dsub2
    7125             :       0,        // dsub1_dsub2
    7126             :       0,        // dsub1_dsub2_dsub3
    7127             :       0,        // dsub2_dsub3
    7128             :       0,        // dsub_qsub1_then_dsub
    7129             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7130             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7131             :       0,        // qsub0_qsub1
    7132             :       0,        // qsub0_qsub1_qsub2
    7133             :       0,        // qsub1_qsub2
    7134             :       0,        // qsub1_qsub2_qsub3
    7135             :       0,        // qsub2_qsub3
    7136             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7137             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7138             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7139             :       23,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7140             :     },
    7141             :     {   // XSeqPairsClass_with_subo64_in_GPR64common
    7142             :       0,        // bsub
    7143             :       0,        // dsub
    7144             :       0,        // dsub0
    7145             :       0,        // dsub1
    7146             :       0,        // dsub2
    7147             :       0,        // dsub3
    7148             :       0,        // hsub
    7149             :       0,        // qhisub
    7150             :       0,        // qsub
    7151             :       0,        // qsub0
    7152             :       0,        // qsub1
    7153             :       0,        // qsub2
    7154             :       0,        // qsub3
    7155             :       0,        // ssub
    7156             :       24,       // sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
    7157             :       0,        // sube32
    7158             :       24,       // sube64 -> XSeqPairsClass_with_subo64_in_GPR64common
    7159             :       0,        // subo32
    7160             :       24,       // subo64 -> XSeqPairsClass_with_subo64_in_GPR64common
    7161             :       0,        // dsub1_then_bsub
    7162             :       0,        // dsub1_then_hsub
    7163             :       0,        // dsub1_then_ssub
    7164             :       0,        // dsub3_then_bsub
    7165             :       0,        // dsub3_then_hsub
    7166             :       0,        // dsub3_then_ssub
    7167             :       0,        // dsub2_then_bsub
    7168             :       0,        // dsub2_then_hsub
    7169             :       0,        // dsub2_then_ssub
    7170             :       0,        // qsub1_then_bsub
    7171             :       0,        // qsub1_then_dsub
    7172             :       0,        // qsub1_then_hsub
    7173             :       0,        // qsub1_then_ssub
    7174             :       0,        // qsub3_then_bsub
    7175             :       0,        // qsub3_then_dsub
    7176             :       0,        // qsub3_then_hsub
    7177             :       0,        // qsub3_then_ssub
    7178             :       0,        // qsub2_then_bsub
    7179             :       0,        // qsub2_then_dsub
    7180             :       0,        // qsub2_then_hsub
    7181             :       0,        // qsub2_then_ssub
    7182             :       24,       // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
    7183             :       0,        // dsub0_dsub1
    7184             :       0,        // dsub0_dsub1_dsub2
    7185             :       0,        // dsub1_dsub2
    7186             :       0,        // dsub1_dsub2_dsub3
    7187             :       0,        // dsub2_dsub3
    7188             :       0,        // dsub_qsub1_then_dsub
    7189             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7190             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7191             :       0,        // qsub0_qsub1
    7192             :       0,        // qsub0_qsub1_qsub2
    7193             :       0,        // qsub1_qsub2
    7194             :       0,        // qsub1_qsub2_qsub3
    7195             :       0,        // qsub2_qsub3
    7196             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7197             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7198             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7199             :       24,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
    7200             :     },
    7201             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    7202             :       0,        // bsub
    7203             :       0,        // dsub
    7204             :       0,        // dsub0
    7205             :       0,        // dsub1
    7206             :       0,        // dsub2
    7207             :       0,        // dsub3
    7208             :       0,        // hsub
    7209             :       0,        // qhisub
    7210             :       0,        // qsub
    7211             :       0,        // qsub0
    7212             :       0,        // qsub1
    7213             :       0,        // qsub2
    7214             :       0,        // qsub3
    7215             :       0,        // ssub
    7216             :       25,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    7217             :       0,        // sube32
    7218             :       25,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    7219             :       0,        // subo32
    7220             :       25,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    7221             :       0,        // dsub1_then_bsub
    7222             :       0,        // dsub1_then_hsub
    7223             :       0,        // dsub1_then_ssub
    7224             :       0,        // dsub3_then_bsub
    7225             :       0,        // dsub3_then_hsub
    7226             :       0,        // dsub3_then_ssub
    7227             :       0,        // dsub2_then_bsub
    7228             :       0,        // dsub2_then_hsub
    7229             :       0,        // dsub2_then_ssub
    7230             :       0,        // qsub1_then_bsub
    7231             :       0,        // qsub1_then_dsub
    7232             :       0,        // qsub1_then_hsub
    7233             :       0,        // qsub1_then_ssub
    7234             :       0,        // qsub3_then_bsub
    7235             :       0,        // qsub3_then_dsub
    7236             :       0,        // qsub3_then_hsub
    7237             :       0,        // qsub3_then_ssub
    7238             :       0,        // qsub2_then_bsub
    7239             :       0,        // qsub2_then_dsub
    7240             :       0,        // qsub2_then_hsub
    7241             :       0,        // qsub2_then_ssub
    7242             :       25,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    7243             :       0,        // dsub0_dsub1
    7244             :       0,        // dsub0_dsub1_dsub2
    7245             :       0,        // dsub1_dsub2
    7246             :       0,        // dsub1_dsub2_dsub3
    7247             :       0,        // dsub2_dsub3
    7248             :       0,        // dsub_qsub1_then_dsub
    7249             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7250             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7251             :       0,        // qsub0_qsub1
    7252             :       0,        // qsub0_qsub1_qsub2
    7253             :       0,        // qsub1_qsub2
    7254             :       0,        // qsub1_qsub2_qsub3
    7255             :       0,        // qsub2_qsub3
    7256             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7257             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7258             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7259             :       25,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    7260             :     },
    7261             :     {   // XSeqPairsClass_with_sube64_in_tcGPR64
    7262             :       0,        // bsub
    7263             :       0,        // dsub
    7264             :       0,        // dsub0
    7265             :       0,        // dsub1
    7266             :       0,        // dsub2
    7267             :       0,        // dsub3
    7268             :       0,        // hsub
    7269             :       0,        // qhisub
    7270             :       0,        // qsub
    7271             :       0,        // qsub0
    7272             :       0,        // qsub1
    7273             :       0,        // qsub2
    7274             :       0,        // qsub3
    7275             :       0,        // ssub
    7276             :       26,       // sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
    7277             :       0,        // sube32
    7278             :       26,       // sube64 -> XSeqPairsClass_with_sube64_in_tcGPR64
    7279             :       0,        // subo32
    7280             :       26,       // subo64 -> XSeqPairsClass_with_sube64_in_tcGPR64
    7281             :       0,        // dsub1_then_bsub
    7282             :       0,        // dsub1_then_hsub
    7283             :       0,        // dsub1_then_ssub
    7284             :       0,        // dsub3_then_bsub
    7285             :       0,        // dsub3_then_hsub
    7286             :       0,        // dsub3_then_ssub
    7287             :       0,        // dsub2_then_bsub
    7288             :       0,        // dsub2_then_hsub
    7289             :       0,        // dsub2_then_ssub
    7290             :       0,        // qsub1_then_bsub
    7291             :       0,        // qsub1_then_dsub
    7292             :       0,        // qsub1_then_hsub
    7293             :       0,        // qsub1_then_ssub
    7294             :       0,        // qsub3_then_bsub
    7295             :       0,        // qsub3_then_dsub
    7296             :       0,        // qsub3_then_hsub
    7297             :       0,        // qsub3_then_ssub
    7298             :       0,        // qsub2_then_bsub
    7299             :       0,        // qsub2_then_dsub
    7300             :       0,        // qsub2_then_hsub
    7301             :       0,        // qsub2_then_ssub
    7302             :       26,       // subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
    7303             :       0,        // dsub0_dsub1
    7304             :       0,        // dsub0_dsub1_dsub2
    7305             :       0,        // dsub1_dsub2
    7306             :       0,        // dsub1_dsub2_dsub3
    7307             :       0,        // dsub2_dsub3
    7308             :       0,        // dsub_qsub1_then_dsub
    7309             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7310             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7311             :       0,        // qsub0_qsub1
    7312             :       0,        // qsub0_qsub1_qsub2
    7313             :       0,        // qsub1_qsub2
    7314             :       0,        // qsub1_qsub2_qsub3
    7315             :       0,        // qsub2_qsub3
    7316             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7317             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7318             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7319             :       26,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
    7320             :     },
    7321             :     {   // XSeqPairsClass_with_subo64_in_tcGPR64
    7322             :       0,        // bsub
    7323             :       0,        // dsub
    7324             :       0,        // dsub0
    7325             :       0,        // dsub1
    7326             :       0,        // dsub2
    7327             :       0,        // dsub3
    7328             :       0,        // hsub
    7329             :       0,        // qhisub
    7330             :       0,        // qsub
    7331             :       0,        // qsub0
    7332             :       0,        // qsub1
    7333             :       0,        // qsub2
    7334             :       0,        // qsub3
    7335             :       0,        // ssub
    7336             :       27,       // sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
    7337             :       0,        // sube32
    7338             :       27,       // sube64 -> XSeqPairsClass_with_subo64_in_tcGPR64
    7339             :       0,        // subo32
    7340             :       27,       // subo64 -> XSeqPairsClass_with_subo64_in_tcGPR64
    7341             :       0,        // dsub1_then_bsub
    7342             :       0,        // dsub1_then_hsub
    7343             :       0,        // dsub1_then_ssub
    7344             :       0,        // dsub3_then_bsub
    7345             :       0,        // dsub3_then_hsub
    7346             :       0,        // dsub3_then_ssub
    7347             :       0,        // dsub2_then_bsub
    7348             :       0,        // dsub2_then_hsub
    7349             :       0,        // dsub2_then_ssub
    7350             :       0,        // qsub1_then_bsub
    7351             :       0,        // qsub1_then_dsub
    7352             :       0,        // qsub1_then_hsub
    7353             :       0,        // qsub1_then_ssub
    7354             :       0,        // qsub3_then_bsub
    7355             :       0,        // qsub3_then_dsub
    7356             :       0,        // qsub3_then_hsub
    7357             :       0,        // qsub3_then_ssub
    7358             :       0,        // qsub2_then_bsub
    7359             :       0,        // qsub2_then_dsub
    7360             :       0,        // qsub2_then_hsub
    7361             :       0,        // qsub2_then_ssub
    7362             :       27,       // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
    7363             :       0,        // dsub0_dsub1
    7364             :       0,        // dsub0_dsub1_dsub2
    7365             :       0,        // dsub1_dsub2
    7366             :       0,        // dsub1_dsub2_dsub3
    7367             :       0,        // dsub2_dsub3
    7368             :       0,        // dsub_qsub1_then_dsub
    7369             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7370             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7371             :       0,        // qsub0_qsub1
    7372             :       0,        // qsub0_qsub1_qsub2
    7373             :       0,        // qsub1_qsub2
    7374             :       0,        // qsub1_qsub2_qsub3
    7375             :       0,        // qsub2_qsub3
    7376             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7377             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7378             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7379             :       27,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
    7380             :     },
    7381             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    7382             :       0,        // bsub
    7383             :       0,        // dsub
    7384             :       0,        // dsub0
    7385             :       0,        // dsub1
    7386             :       0,        // dsub2
    7387             :       0,        // dsub3
    7388             :       0,        // hsub
    7389             :       0,        // qhisub
    7390             :       0,        // qsub
    7391             :       0,        // qsub0
    7392             :       0,        // qsub1
    7393             :       0,        // qsub2
    7394             :       0,        // qsub3
    7395             :       0,        // ssub
    7396             :       28,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    7397             :       0,        // sube32
    7398             :       28,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    7399             :       0,        // subo32
    7400             :       28,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    7401             :       0,        // dsub1_then_bsub
    7402             :       0,        // dsub1_then_hsub
    7403             :       0,        // dsub1_then_ssub
    7404             :       0,        // dsub3_then_bsub
    7405             :       0,        // dsub3_then_hsub
    7406             :       0,        // dsub3_then_ssub
    7407             :       0,        // dsub2_then_bsub
    7408             :       0,        // dsub2_then_hsub
    7409             :       0,        // dsub2_then_ssub
    7410             :       0,        // qsub1_then_bsub
    7411             :       0,        // qsub1_then_dsub
    7412             :       0,        // qsub1_then_hsub
    7413             :       0,        // qsub1_then_ssub
    7414             :       0,        // qsub3_then_bsub
    7415             :       0,        // qsub3_then_dsub
    7416             :       0,        // qsub3_then_hsub
    7417             :       0,        // qsub3_then_ssub
    7418             :       0,        // qsub2_then_bsub
    7419             :       0,        // qsub2_then_dsub
    7420             :       0,        // qsub2_then_hsub
    7421             :       0,        // qsub2_then_ssub
    7422             :       28,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    7423             :       0,        // dsub0_dsub1
    7424             :       0,        // dsub0_dsub1_dsub2
    7425             :       0,        // dsub1_dsub2
    7426             :       0,        // dsub1_dsub2_dsub3
    7427             :       0,        // dsub2_dsub3
    7428             :       0,        // dsub_qsub1_then_dsub
    7429             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7430             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7431             :       0,        // qsub0_qsub1
    7432             :       0,        // qsub0_qsub1_qsub2
    7433             :       0,        // qsub1_qsub2
    7434             :       0,        // qsub1_qsub2_qsub3
    7435             :       0,        // qsub2_qsub3
    7436             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7437             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7438             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7439             :       28,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    7440             :     },
    7441             :     {   // FPR128
    7442             :       29,       // bsub -> FPR128
    7443             :       29,       // dsub -> FPR128
    7444             :       0,        // dsub0
    7445             :       0,        // dsub1
    7446             :       0,        // dsub2
    7447             :       0,        // dsub3
    7448             :       29,       // hsub -> FPR128
    7449             :       0,        // qhisub
    7450             :       0,        // qsub
    7451             :       0,        // qsub0
    7452             :       0,        // qsub1
    7453             :       0,        // qsub2
    7454             :       0,        // qsub3
    7455             :       29,       // ssub -> FPR128
    7456             :       0,        // sub_32
    7457             :       0,        // sube32
    7458             :       0,        // sube64
    7459             :       0,        // subo32
    7460             :       0,        // subo64
    7461             :       0,        // dsub1_then_bsub
    7462             :       0,        // dsub1_then_hsub
    7463             :       0,        // dsub1_then_ssub
    7464             :       0,        // dsub3_then_bsub
    7465             :       0,        // dsub3_then_hsub
    7466             :       0,        // dsub3_then_ssub
    7467             :       0,        // dsub2_then_bsub
    7468             :       0,        // dsub2_then_hsub
    7469             :       0,        // dsub2_then_ssub
    7470             :       0,        // qsub1_then_bsub
    7471             :       0,        // qsub1_then_dsub
    7472             :       0,        // qsub1_then_hsub
    7473             :       0,        // qsub1_then_ssub
    7474             :       0,        // qsub3_then_bsub
    7475             :       0,        // qsub3_then_dsub
    7476             :       0,        // qsub3_then_hsub
    7477             :       0,        // qsub3_then_ssub
    7478             :       0,        // qsub2_then_bsub
    7479             :       0,        // qsub2_then_dsub
    7480             :       0,        // qsub2_then_hsub
    7481             :       0,        // qsub2_then_ssub
    7482             :       0,        // subo64_then_sub_32
    7483             :       0,        // dsub0_dsub1
    7484             :       0,        // dsub0_dsub1_dsub2
    7485             :       0,        // dsub1_dsub2
    7486             :       0,        // dsub1_dsub2_dsub3
    7487             :       0,        // dsub2_dsub3
    7488             :       0,        // dsub_qsub1_then_dsub
    7489             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7490             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7491             :       0,        // qsub0_qsub1
    7492             :       0,        // qsub0_qsub1_qsub2
    7493             :       0,        // qsub1_qsub2
    7494             :       0,        // qsub1_qsub2_qsub3
    7495             :       0,        // qsub2_qsub3
    7496             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7497             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7498             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7499             :       0,        // sub_32_subo64_then_sub_32
    7500             :     },
    7501             :     {   // FPR128_lo
    7502             :       30,       // bsub -> FPR128_lo
    7503             :       30,       // dsub -> FPR128_lo
    7504             :       0,        // dsub0
    7505             :       0,        // dsub1
    7506             :       0,        // dsub2
    7507             :       0,        // dsub3
    7508             :       30,       // hsub -> FPR128_lo
    7509             :       0,        // qhisub
    7510             :       0,        // qsub
    7511             :       0,        // qsub0
    7512             :       0,        // qsub1
    7513             :       0,        // qsub2
    7514             :       0,        // qsub3
    7515             :       30,       // ssub -> FPR128_lo
    7516             :       0,        // sub_32
    7517             :       0,        // sube32
    7518             :       0,        // sube64
    7519             :       0,        // subo32
    7520             :       0,        // subo64
    7521             :       0,        // dsub1_then_bsub
    7522             :       0,        // dsub1_then_hsub
    7523             :       0,        // dsub1_then_ssub
    7524             :       0,        // dsub3_then_bsub
    7525             :       0,        // dsub3_then_hsub
    7526             :       0,        // dsub3_then_ssub
    7527             :       0,        // dsub2_then_bsub
    7528             :       0,        // dsub2_then_hsub
    7529             :       0,        // dsub2_then_ssub
    7530             :       0,        // qsub1_then_bsub
    7531             :       0,        // qsub1_then_dsub
    7532             :       0,        // qsub1_then_hsub
    7533             :       0,        // qsub1_then_ssub
    7534             :       0,        // qsub3_then_bsub
    7535             :       0,        // qsub3_then_dsub
    7536             :       0,        // qsub3_then_hsub
    7537             :       0,        // qsub3_then_ssub
    7538             :       0,        // qsub2_then_bsub
    7539             :       0,        // qsub2_then_dsub
    7540             :       0,        // qsub2_then_hsub
    7541             :       0,        // qsub2_then_ssub
    7542             :       0,        // subo64_then_sub_32
    7543             :       0,        // dsub0_dsub1
    7544             :       0,        // dsub0_dsub1_dsub2
    7545             :       0,        // dsub1_dsub2
    7546             :       0,        // dsub1_dsub2_dsub3
    7547             :       0,        // dsub2_dsub3
    7548             :       0,        // dsub_qsub1_then_dsub
    7549             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7550             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7551             :       0,        // qsub0_qsub1
    7552             :       0,        // qsub0_qsub1_qsub2
    7553             :       0,        // qsub1_qsub2
    7554             :       0,        // qsub1_qsub2_qsub3
    7555             :       0,        // qsub2_qsub3
    7556             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7557             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7558             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7559             :       0,        // sub_32_subo64_then_sub_32
    7560             :     },
    7561             :     {   // DDD
    7562             :       31,       // bsub -> DDD
    7563             :       0,        // dsub
    7564             :       31,       // dsub0 -> DDD
    7565             :       31,       // dsub1 -> DDD
    7566             :       31,       // dsub2 -> DDD
    7567             :       0,        // dsub3
    7568             :       31,       // hsub -> DDD
    7569             :       0,        // qhisub
    7570             :       0,        // qsub
    7571             :       0,        // qsub0
    7572             :       0,        // qsub1
    7573             :       0,        // qsub2
    7574             :       0,        // qsub3
    7575             :       31,       // ssub -> DDD
    7576             :       0,        // sub_32
    7577             :       0,        // sube32
    7578             :       0,        // sube64
    7579             :       0,        // subo32
    7580             :       0,        // subo64
    7581             :       31,       // dsub1_then_bsub -> DDD
    7582             :       31,       // dsub1_then_hsub -> DDD
    7583             :       31,       // dsub1_then_ssub -> DDD
    7584             :       0,        // dsub3_then_bsub
    7585             :       0,        // dsub3_then_hsub
    7586             :       0,        // dsub3_then_ssub
    7587             :       31,       // dsub2_then_bsub -> DDD
    7588             :       31,       // dsub2_then_hsub -> DDD
    7589             :       31,       // dsub2_then_ssub -> DDD
    7590             :       0,        // qsub1_then_bsub
    7591             :       0,        // qsub1_then_dsub
    7592             :       0,        // qsub1_then_hsub
    7593             :       0,        // qsub1_then_ssub
    7594             :       0,        // qsub3_then_bsub
    7595             :       0,        // qsub3_then_dsub
    7596             :       0,        // qsub3_then_hsub
    7597             :       0,        // qsub3_then_ssub
    7598             :       0,        // qsub2_then_bsub
    7599             :       0,        // qsub2_then_dsub
    7600             :       0,        // qsub2_then_hsub
    7601             :       0,        // qsub2_then_ssub
    7602             :       0,        // subo64_then_sub_32
    7603             :       31,       // dsub0_dsub1 -> DDD
    7604             :       0,        // dsub0_dsub1_dsub2
    7605             :       31,       // dsub1_dsub2 -> DDD
    7606             :       0,        // dsub1_dsub2_dsub3
    7607             :       0,        // dsub2_dsub3
    7608             :       0,        // dsub_qsub1_then_dsub
    7609             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7610             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7611             :       0,        // qsub0_qsub1
    7612             :       0,        // qsub0_qsub1_qsub2
    7613             :       0,        // qsub1_qsub2
    7614             :       0,        // qsub1_qsub2_qsub3
    7615             :       0,        // qsub2_qsub3
    7616             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7617             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7618             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7619             :       0,        // sub_32_subo64_then_sub_32
    7620             :     },
    7621             :     {   // DDDD
    7622             :       32,       // bsub -> DDDD
    7623             :       0,        // dsub
    7624             :       32,       // dsub0 -> DDDD
    7625             :       32,       // dsub1 -> DDDD
    7626             :       32,       // dsub2 -> DDDD
    7627             :       32,       // dsub3 -> DDDD
    7628             :       32,       // hsub -> DDDD
    7629             :       0,        // qhisub
    7630             :       0,        // qsub
    7631             :       0,        // qsub0
    7632             :       0,        // qsub1
    7633             :       0,        // qsub2
    7634             :       0,        // qsub3
    7635             :       32,       // ssub -> DDDD
    7636             :       0,        // sub_32
    7637             :       0,        // sube32
    7638             :       0,        // sube64
    7639             :       0,        // subo32
    7640             :       0,        // subo64
    7641             :       32,       // dsub1_then_bsub -> DDDD
    7642             :       32,       // dsub1_then_hsub -> DDDD
    7643             :       32,       // dsub1_then_ssub -> DDDD
    7644             :       32,       // dsub3_then_bsub -> DDDD
    7645             :       32,       // dsub3_then_hsub -> DDDD
    7646             :       32,       // dsub3_then_ssub -> DDDD
    7647             :       32,       // dsub2_then_bsub -> DDDD
    7648             :       32,       // dsub2_then_hsub -> DDDD
    7649             :       32,       // dsub2_then_ssub -> DDDD
    7650             :       0,        // qsub1_then_bsub
    7651             :       0,        // qsub1_then_dsub
    7652             :       0,        // qsub1_then_hsub
    7653             :       0,        // qsub1_then_ssub
    7654             :       0,        // qsub3_then_bsub
    7655             :       0,        // qsub3_then_dsub
    7656             :       0,        // qsub3_then_hsub
    7657             :       0,        // qsub3_then_ssub
    7658             :       0,        // qsub2_then_bsub
    7659             :       0,        // qsub2_then_dsub
    7660             :       0,        // qsub2_then_hsub
    7661             :       0,        // qsub2_then_ssub
    7662             :       0,        // subo64_then_sub_32
    7663             :       32,       // dsub0_dsub1 -> DDDD
    7664             :       32,       // dsub0_dsub1_dsub2 -> DDDD
    7665             :       32,       // dsub1_dsub2 -> DDDD
    7666             :       32,       // dsub1_dsub2_dsub3 -> DDDD
    7667             :       32,       // dsub2_dsub3 -> DDDD
    7668             :       0,        // dsub_qsub1_then_dsub
    7669             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7670             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7671             :       0,        // qsub0_qsub1
    7672             :       0,        // qsub0_qsub1_qsub2
    7673             :       0,        // qsub1_qsub2
    7674             :       0,        // qsub1_qsub2_qsub3
    7675             :       0,        // qsub2_qsub3
    7676             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7677             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7678             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7679             :       0,        // sub_32_subo64_then_sub_32
    7680             :     },
    7681             :     {   // QQ
    7682             :       33,       // bsub -> QQ
    7683             :       33,       // dsub -> QQ
    7684             :       0,        // dsub0
    7685             :       0,        // dsub1
    7686             :       0,        // dsub2
    7687             :       0,        // dsub3
    7688             :       33,       // hsub -> QQ
    7689             :       0,        // qhisub
    7690             :       0,        // qsub
    7691             :       33,       // qsub0 -> QQ
    7692             :       33,       // qsub1 -> QQ
    7693             :       0,        // qsub2
    7694             :       0,        // qsub3
    7695             :       33,       // ssub -> QQ
    7696             :       0,        // sub_32
    7697             :       0,        // sube32
    7698             :       0,        // sube64
    7699             :       0,        // subo32
    7700             :       0,        // subo64
    7701             :       0,        // dsub1_then_bsub
    7702             :       0,        // dsub1_then_hsub
    7703             :       0,        // dsub1_then_ssub
    7704             :       0,        // dsub3_then_bsub
    7705             :       0,        // dsub3_then_hsub
    7706             :       0,        // dsub3_then_ssub
    7707             :       0,        // dsub2_then_bsub
    7708             :       0,        // dsub2_then_hsub
    7709             :       0,        // dsub2_then_ssub
    7710             :       33,       // qsub1_then_bsub -> QQ
    7711             :       33,       // qsub1_then_dsub -> QQ
    7712             :       33,       // qsub1_then_hsub -> QQ
    7713             :       33,       // qsub1_then_ssub -> QQ
    7714             :       0,        // qsub3_then_bsub
    7715             :       0,        // qsub3_then_dsub
    7716             :       0,        // qsub3_then_hsub
    7717             :       0,        // qsub3_then_ssub
    7718             :       0,        // qsub2_then_bsub
    7719             :       0,        // qsub2_then_dsub
    7720             :       0,        // qsub2_then_hsub
    7721             :       0,        // qsub2_then_ssub
    7722             :       0,        // subo64_then_sub_32
    7723             :       0,        // dsub0_dsub1
    7724             :       0,        // dsub0_dsub1_dsub2
    7725             :       0,        // dsub1_dsub2
    7726             :       0,        // dsub1_dsub2_dsub3
    7727             :       0,        // dsub2_dsub3
    7728             :       33,       // dsub_qsub1_then_dsub -> QQ
    7729             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7730             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7731             :       0,        // qsub0_qsub1
    7732             :       0,        // qsub0_qsub1_qsub2
    7733             :       0,        // qsub1_qsub2
    7734             :       0,        // qsub1_qsub2_qsub3
    7735             :       0,        // qsub2_qsub3
    7736             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7737             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7738             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7739             :       0,        // sub_32_subo64_then_sub_32
    7740             :     },
    7741             :     {   // QQ_with_qsub0_in_FPR128_lo
    7742             :       34,       // bsub -> QQ_with_qsub0_in_FPR128_lo
    7743             :       34,       // dsub -> QQ_with_qsub0_in_FPR128_lo
    7744             :       0,        // dsub0
    7745             :       0,        // dsub1
    7746             :       0,        // dsub2
    7747             :       0,        // dsub3
    7748             :       34,       // hsub -> QQ_with_qsub0_in_FPR128_lo
    7749             :       0,        // qhisub
    7750             :       0,        // qsub
    7751             :       34,       // qsub0 -> QQ_with_qsub0_in_FPR128_lo
    7752             :       34,       // qsub1 -> QQ_with_qsub0_in_FPR128_lo
    7753             :       0,        // qsub2
    7754             :       0,        // qsub3
    7755             :       34,       // ssub -> QQ_with_qsub0_in_FPR128_lo
    7756             :       0,        // sub_32
    7757             :       0,        // sube32
    7758             :       0,        // sube64
    7759             :       0,        // subo32
    7760             :       0,        // subo64
    7761             :       0,        // dsub1_then_bsub
    7762             :       0,        // dsub1_then_hsub
    7763             :       0,        // dsub1_then_ssub
    7764             :       0,        // dsub3_then_bsub
    7765             :       0,        // dsub3_then_hsub
    7766             :       0,        // dsub3_then_ssub
    7767             :       0,        // dsub2_then_bsub
    7768             :       0,        // dsub2_then_hsub
    7769             :       0,        // dsub2_then_ssub
    7770             :       34,       // qsub1_then_bsub -> QQ_with_qsub0_in_FPR128_lo
    7771             :       34,       // qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo
    7772             :       34,       // qsub1_then_hsub -> QQ_with_qsub0_in_FPR128_lo
    7773             :       34,       // qsub1_then_ssub -> QQ_with_qsub0_in_FPR128_lo
    7774             :       0,        // qsub3_then_bsub
    7775             :       0,        // qsub3_then_dsub
    7776             :       0,        // qsub3_then_hsub
    7777             :       0,        // qsub3_then_ssub
    7778             :       0,        // qsub2_then_bsub
    7779             :       0,        // qsub2_then_dsub
    7780             :       0,        // qsub2_then_hsub
    7781             :       0,        // qsub2_then_ssub
    7782             :       0,        // subo64_then_sub_32
    7783             :       0,        // dsub0_dsub1
    7784             :       0,        // dsub0_dsub1_dsub2
    7785             :       0,        // dsub1_dsub2
    7786             :       0,        // dsub1_dsub2_dsub3
    7787             :       0,        // dsub2_dsub3
    7788             :       34,       // dsub_qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo
    7789             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7790             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7791             :       0,        // qsub0_qsub1
    7792             :       0,        // qsub0_qsub1_qsub2
    7793             :       0,        // qsub1_qsub2
    7794             :       0,        // qsub1_qsub2_qsub3
    7795             :       0,        // qsub2_qsub3
    7796             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7797             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7798             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7799             :       0,        // sub_32_subo64_then_sub_32
    7800             :     },
    7801             :     {   // QQ_with_qsub1_in_FPR128_lo
    7802             :       35,       // bsub -> QQ_with_qsub1_in_FPR128_lo
    7803             :       35,       // dsub -> QQ_with_qsub1_in_FPR128_lo
    7804             :       0,        // dsub0
    7805             :       0,        // dsub1
    7806             :       0,        // dsub2
    7807             :       0,        // dsub3
    7808             :       35,       // hsub -> QQ_with_qsub1_in_FPR128_lo
    7809             :       0,        // qhisub
    7810             :       0,        // qsub
    7811             :       35,       // qsub0 -> QQ_with_qsub1_in_FPR128_lo
    7812             :       35,       // qsub1 -> QQ_with_qsub1_in_FPR128_lo
    7813             :       0,        // qsub2
    7814             :       0,        // qsub3
    7815             :       35,       // ssub -> QQ_with_qsub1_in_FPR128_lo
    7816             :       0,        // sub_32
    7817             :       0,        // sube32
    7818             :       0,        // sube64
    7819             :       0,        // subo32
    7820             :       0,        // subo64
    7821             :       0,        // dsub1_then_bsub
    7822             :       0,        // dsub1_then_hsub
    7823             :       0,        // dsub1_then_ssub
    7824             :       0,        // dsub3_then_bsub
    7825             :       0,        // dsub3_then_hsub
    7826             :       0,        // dsub3_then_ssub
    7827             :       0,        // dsub2_then_bsub
    7828             :       0,        // dsub2_then_hsub
    7829             :       0,        // dsub2_then_ssub
    7830             :       35,       // qsub1_then_bsub -> QQ_with_qsub1_in_FPR128_lo
    7831             :       35,       // qsub1_then_dsub -> QQ_with_qsub1_in_FPR128_lo
    7832             :       35,       // qsub1_then_hsub -> QQ_with_qsub1_in_FPR128_lo
    7833             :       35,       // qsub1_then_ssub -> QQ_with_qsub1_in_FPR128_lo
    7834             :       0,        // qsub3_then_bsub
    7835             :       0,        // qsub3_then_dsub
    7836             :       0,        // qsub3_then_hsub
    7837             :       0,        // qsub3_then_ssub
    7838             :       0,        // qsub2_then_bsub
    7839             :       0,        // qsub2_then_dsub
    7840             :       0,        // qsub2_then_hsub
    7841             :       0,        // qsub2_then_ssub
    7842             :       0,        // subo64_then_sub_32
    7843             :       0,        // dsub0_dsub1
    7844             :       0,        // dsub0_dsub1_dsub2
    7845             :       0,        // dsub1_dsub2
    7846             :       0,        // dsub1_dsub2_dsub3
    7847             :       0,        // dsub2_dsub3
    7848             :       35,       // dsub_qsub1_then_dsub -> QQ_with_qsub1_in_FPR128_lo
    7849             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7850             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7851             :       0,        // qsub0_qsub1
    7852             :       0,        // qsub0_qsub1_qsub2
    7853             :       0,        // qsub1_qsub2
    7854             :       0,        // qsub1_qsub2_qsub3
    7855             :       0,        // qsub2_qsub3
    7856             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7857             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7858             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7859             :       0,        // sub_32_subo64_then_sub_32
    7860             :     },
    7861             :     {   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7862             :       36,       // bsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7863             :       36,       // dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7864             :       0,        // dsub0
    7865             :       0,        // dsub1
    7866             :       0,        // dsub2
    7867             :       0,        // dsub3
    7868             :       36,       // hsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7869             :       0,        // qhisub
    7870             :       0,        // qsub
    7871             :       36,       // qsub0 -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7872             :       36,       // qsub1 -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7873             :       0,        // qsub2
    7874             :       0,        // qsub3
    7875             :       36,       // ssub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7876             :       0,        // sub_32
    7877             :       0,        // sube32
    7878             :       0,        // sube64
    7879             :       0,        // subo32
    7880             :       0,        // subo64
    7881             :       0,        // dsub1_then_bsub
    7882             :       0,        // dsub1_then_hsub
    7883             :       0,        // dsub1_then_ssub
    7884             :       0,        // dsub3_then_bsub
    7885             :       0,        // dsub3_then_hsub
    7886             :       0,        // dsub3_then_ssub
    7887             :       0,        // dsub2_then_bsub
    7888             :       0,        // dsub2_then_hsub
    7889             :       0,        // dsub2_then_ssub
    7890             :       36,       // qsub1_then_bsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7891             :       36,       // qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7892             :       36,       // qsub1_then_hsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7893             :       36,       // qsub1_then_ssub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7894             :       0,        // qsub3_then_bsub
    7895             :       0,        // qsub3_then_dsub
    7896             :       0,        // qsub3_then_hsub
    7897             :       0,        // qsub3_then_ssub
    7898             :       0,        // qsub2_then_bsub
    7899             :       0,        // qsub2_then_dsub
    7900             :       0,        // qsub2_then_hsub
    7901             :       0,        // qsub2_then_ssub
    7902             :       0,        // subo64_then_sub_32
    7903             :       0,        // dsub0_dsub1
    7904             :       0,        // dsub0_dsub1_dsub2
    7905             :       0,        // dsub1_dsub2
    7906             :       0,        // dsub1_dsub2_dsub3
    7907             :       0,        // dsub2_dsub3
    7908             :       36,       // dsub_qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    7909             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7910             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7911             :       0,        // qsub0_qsub1
    7912             :       0,        // qsub0_qsub1_qsub2
    7913             :       0,        // qsub1_qsub2
    7914             :       0,        // qsub1_qsub2_qsub3
    7915             :       0,        // qsub2_qsub3
    7916             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7917             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7918             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7919             :       0,        // sub_32_subo64_then_sub_32
    7920             :     },
    7921             :     {   // QQQ
    7922             :       37,       // bsub -> QQQ
    7923             :       37,       // dsub -> QQQ
    7924             :       0,        // dsub0
    7925             :       0,        // dsub1
    7926             :       0,        // dsub2
    7927             :       0,        // dsub3
    7928             :       37,       // hsub -> QQQ
    7929             :       0,        // qhisub
    7930             :       0,        // qsub
    7931             :       37,       // qsub0 -> QQQ
    7932             :       37,       // qsub1 -> QQQ
    7933             :       37,       // qsub2 -> QQQ
    7934             :       0,        // qsub3
    7935             :       37,       // ssub -> QQQ
    7936             :       0,        // sub_32
    7937             :       0,        // sube32
    7938             :       0,        // sube64
    7939             :       0,        // subo32
    7940             :       0,        // subo64
    7941             :       0,        // dsub1_then_bsub
    7942             :       0,        // dsub1_then_hsub
    7943             :       0,        // dsub1_then_ssub
    7944             :       0,        // dsub3_then_bsub
    7945             :       0,        // dsub3_then_hsub
    7946             :       0,        // dsub3_then_ssub
    7947             :       0,        // dsub2_then_bsub
    7948             :       0,        // dsub2_then_hsub
    7949             :       0,        // dsub2_then_ssub
    7950             :       37,       // qsub1_then_bsub -> QQQ
    7951             :       37,       // qsub1_then_dsub -> QQQ
    7952             :       37,       // qsub1_then_hsub -> QQQ
    7953             :       37,       // qsub1_then_ssub -> QQQ
    7954             :       0,        // qsub3_then_bsub
    7955             :       0,        // qsub3_then_dsub
    7956             :       0,        // qsub3_then_hsub
    7957             :       0,        // qsub3_then_ssub
    7958             :       37,       // qsub2_then_bsub -> QQQ
    7959             :       37,       // qsub2_then_dsub -> QQQ
    7960             :       37,       // qsub2_then_hsub -> QQQ
    7961             :       37,       // qsub2_then_ssub -> QQQ
    7962             :       0,        // subo64_then_sub_32
    7963             :       0,        // dsub0_dsub1
    7964             :       0,        // dsub0_dsub1_dsub2
    7965             :       0,        // dsub1_dsub2
    7966             :       0,        // dsub1_dsub2_dsub3
    7967             :       0,        // dsub2_dsub3
    7968             :       37,       // dsub_qsub1_then_dsub -> QQQ
    7969             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7970             :       37,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ
    7971             :       37,       // qsub0_qsub1 -> QQQ
    7972             :       0,        // qsub0_qsub1_qsub2
    7973             :       37,       // qsub1_qsub2 -> QQQ
    7974             :       0,        // qsub1_qsub2_qsub3
    7975             :       0,        // qsub2_qsub3
    7976             :       37,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ
    7977             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7978             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7979             :       0,        // sub_32_subo64_then_sub_32
    7980             :     },
    7981             :     {   // QQQ_with_qsub0_in_FPR128_lo
    7982             :       38,       // bsub -> QQQ_with_qsub0_in_FPR128_lo
    7983             :       38,       // dsub -> QQQ_with_qsub0_in_FPR128_lo
    7984             :       0,        // dsub0
    7985             :       0,        // dsub1
    7986             :       0,        // dsub2
    7987             :       0,        // dsub3
    7988             :       38,       // hsub -> QQQ_with_qsub0_in_FPR128_lo
    7989             :       0,        // qhisub
    7990             :       0,        // qsub
    7991             :       38,       // qsub0 -> QQQ_with_qsub0_in_FPR128_lo
    7992             :       38,       // qsub1 -> QQQ_with_qsub0_in_FPR128_lo
    7993             :       38,       // qsub2 -> QQQ_with_qsub0_in_FPR128_lo
    7994             :       0,        // qsub3
    7995             :       38,       // ssub -> QQQ_with_qsub0_in_FPR128_lo
    7996             :       0,        // sub_32
    7997             :       0,        // sube32
    7998             :       0,        // sube64
    7999             :       0,        // subo32
    8000             :       0,        // subo64
    8001             :       0,        // dsub1_then_bsub
    8002             :       0,        // dsub1_then_hsub
    8003             :       0,        // dsub1_then_ssub
    8004             :       0,        // dsub3_then_bsub
    8005             :       0,        // dsub3_then_hsub
    8006             :       0,        // dsub3_then_ssub
    8007             :       0,        // dsub2_then_bsub
    8008             :       0,        // dsub2_then_hsub
    8009             :       0,        // dsub2_then_ssub
    8010             :       38,       // qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo
    8011             :       38,       // qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    8012             :       38,       // qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo
    8013             :       38,       // qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo
    8014             :       0,        // qsub3_then_bsub
    8015             :       0,        // qsub3_then_dsub
    8016             :       0,        // qsub3_then_hsub
    8017             :       0,        // qsub3_then_ssub
    8018             :       38,       // qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo
    8019             :       38,       // qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    8020             :       38,       // qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo
    8021             :       38,       // qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo
    8022             :       0,        // subo64_then_sub_32
    8023             :       0,        // dsub0_dsub1
    8024             :       0,        // dsub0_dsub1_dsub2
    8025             :       0,        // dsub1_dsub2
    8026             :       0,        // dsub1_dsub2_dsub3
    8027             :       0,        // dsub2_dsub3
    8028             :       38,       // dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    8029             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8030             :       38,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    8031             :       38,       // qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo
    8032             :       0,        // qsub0_qsub1_qsub2
    8033             :       38,       // qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo
    8034             :       0,        // qsub1_qsub2_qsub3
    8035             :       0,        // qsub2_qsub3
    8036             :       38,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    8037             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8038             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8039             :       0,        // sub_32_subo64_then_sub_32
    8040             :     },
    8041             :     {   // QQQ_with_qsub1_in_FPR128_lo
    8042             :       39,       // bsub -> QQQ_with_qsub1_in_FPR128_lo
    8043             :       39,       // dsub -> QQQ_with_qsub1_in_FPR128_lo
    8044             :       0,        // dsub0
    8045             :       0,        // dsub1
    8046             :       0,        // dsub2
    8047             :       0,        // dsub3
    8048             :       39,       // hsub -> QQQ_with_qsub1_in_FPR128_lo
    8049             :       0,        // qhisub
    8050             :       0,        // qsub
    8051             :       39,       // qsub0 -> QQQ_with_qsub1_in_FPR128_lo
    8052             :       39,       // qsub1 -> QQQ_with_qsub1_in_FPR128_lo
    8053             :       39,       // qsub2 -> QQQ_with_qsub1_in_FPR128_lo
    8054             :       0,        // qsub3
    8055             :       39,       // ssub -> QQQ_with_qsub1_in_FPR128_lo
    8056             :       0,        // sub_32
    8057             :       0,        // sube32
    8058             :       0,        // sube64
    8059             :       0,        // subo32
    8060             :       0,        // subo64
    8061             :       0,        // dsub1_then_bsub
    8062             :       0,        // dsub1_then_hsub
    8063             :       0,        // dsub1_then_ssub
    8064             :       0,        // dsub3_then_bsub
    8065             :       0,        // dsub3_then_hsub
    8066             :       0,        // dsub3_then_ssub
    8067             :       0,        // dsub2_then_bsub
    8068             :       0,        // dsub2_then_hsub
    8069             :       0,        // dsub2_then_ssub
    8070             :       39,       // qsub1_then_bsub -> QQQ_with_qsub1_in_FPR128_lo
    8071             :       39,       // qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    8072             :       39,       // qsub1_then_hsub -> QQQ_with_qsub1_in_FPR128_lo
    8073             :       39,       // qsub1_then_ssub -> QQQ_with_qsub1_in_FPR128_lo
    8074             :       0,        // qsub3_then_bsub
    8075             :       0,        // qsub3_then_dsub
    8076             :       0,        // qsub3_then_hsub
    8077             :       0,        // qsub3_then_ssub
    8078             :       39,       // qsub2_then_bsub -> QQQ_with_qsub1_in_FPR128_lo
    8079             :       39,       // qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    8080             :       39,       // qsub2_then_hsub -> QQQ_with_qsub1_in_FPR128_lo
    8081             :       39,       // qsub2_then_ssub -> QQQ_with_qsub1_in_FPR128_lo
    8082             :       0,        // subo64_then_sub_32
    8083             :       0,        // dsub0_dsub1
    8084             :       0,        // dsub0_dsub1_dsub2
    8085             :       0,        // dsub1_dsub2
    8086             :       0,        // dsub1_dsub2_dsub3
    8087             :       0,        // dsub2_dsub3
    8088             :       39,       // dsub_qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    8089             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8090             :       39,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    8091             :       39,       // qsub0_qsub1 -> QQQ_with_qsub1_in_FPR128_lo
    8092             :       0,        // qsub0_qsub1_qsub2
    8093             :       39,       // qsub1_qsub2 -> QQQ_with_qsub1_in_FPR128_lo
    8094             :       0,        // qsub1_qsub2_qsub3
    8095             :       0,        // qsub2_qsub3
    8096             :       39,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    8097             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8098             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8099             :       0,        // sub_32_subo64_then_sub_32
    8100             :     },
    8101             :     {   // QQQ_with_qsub2_in_FPR128_lo
    8102             :       40,       // bsub -> QQQ_with_qsub2_in_FPR128_lo
    8103             :       40,       // dsub -> QQQ_with_qsub2_in_FPR128_lo
    8104             :       0,        // dsub0
    8105             :       0,        // dsub1
    8106             :       0,        // dsub2
    8107             :       0,        // dsub3
    8108             :       40,       // hsub -> QQQ_with_qsub2_in_FPR128_lo
    8109             :       0,        // qhisub
    8110             :       0,        // qsub
    8111             :       40,       // qsub0 -> QQQ_with_qsub2_in_FPR128_lo
    8112             :       40,       // qsub1 -> QQQ_with_qsub2_in_FPR128_lo
    8113             :       40,       // qsub2 -> QQQ_with_qsub2_in_FPR128_lo
    8114             :       0,        // qsub3
    8115             :       40,       // ssub -> QQQ_with_qsub2_in_FPR128_lo
    8116             :       0,        // sub_32
    8117             :       0,        // sube32
    8118             :       0,        // sube64
    8119             :       0,        // subo32
    8120             :       0,        // subo64
    8121             :       0,        // dsub1_then_bsub
    8122             :       0,        // dsub1_then_hsub
    8123             :       0,        // dsub1_then_ssub
    8124             :       0,        // dsub3_then_bsub
    8125             :       0,        // dsub3_then_hsub
    8126             :       0,        // dsub3_then_ssub
    8127             :       0,        // dsub2_then_bsub
    8128             :       0,        // dsub2_then_hsub
    8129             :       0,        // dsub2_then_ssub
    8130             :       40,       // qsub1_then_bsub -> QQQ_with_qsub2_in_FPR128_lo
    8131             :       40,       // qsub1_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    8132             :       40,       // qsub1_then_hsub -> QQQ_with_qsub2_in_FPR128_lo
    8133             :       40,       // qsub1_then_ssub -> QQQ_with_qsub2_in_FPR128_lo
    8134             :       0,        // qsub3_then_bsub
    8135             :       0,        // qsub3_then_dsub
    8136             :       0,        // qsub3_then_hsub
    8137             :       0,        // qsub3_then_ssub
    8138             :       40,       // qsub2_then_bsub -> QQQ_with_qsub2_in_FPR128_lo
    8139             :       40,       // qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    8140             :       40,       // qsub2_then_hsub -> QQQ_with_qsub2_in_FPR128_lo
    8141             :       40,       // qsub2_then_ssub -> QQQ_with_qsub2_in_FPR128_lo
    8142             :       0,        // subo64_then_sub_32
    8143             :       0,        // dsub0_dsub1
    8144             :       0,        // dsub0_dsub1_dsub2
    8145             :       0,        // dsub1_dsub2
    8146             :       0,        // dsub1_dsub2_dsub3
    8147             :       0,        // dsub2_dsub3
    8148             :       40,       // dsub_qsub1_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    8149             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8150             :       40,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    8151             :       40,       // qsub0_qsub1 -> QQQ_with_qsub2_in_FPR128_lo
    8152             :       0,        // qsub0_qsub1_qsub2
    8153             :       40,       // qsub1_qsub2 -> QQQ_with_qsub2_in_FPR128_lo
    8154             :       0,        // qsub1_qsub2_qsub3
    8155             :       0,        // qsub2_qsub3
    8156             :       40,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    8157             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8158             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8159             :       0,        // sub_32_subo64_then_sub_32
    8160             :     },
    8161             :     {   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8162             :       41,       // bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8163             :       41,       // dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8164             :       0,        // dsub0
    8165             :       0,        // dsub1
    8166             :       0,        // dsub2
    8167             :       0,        // dsub3
    8168             :       41,       // hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8169             :       0,        // qhisub
    8170             :       0,        // qsub
    8171             :       41,       // qsub0 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8172             :       41,       // qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8173             :       41,       // qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8174             :       0,        // qsub3
    8175             :       41,       // ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8176             :       0,        // sub_32
    8177             :       0,        // sube32
    8178             :       0,        // sube64
    8179             :       0,        // subo32
    8180             :       0,        // subo64
    8181             :       0,        // dsub1_then_bsub
    8182             :       0,        // dsub1_then_hsub
    8183             :       0,        // dsub1_then_ssub
    8184             :       0,        // dsub3_then_bsub
    8185             :       0,        // dsub3_then_hsub
    8186             :       0,        // dsub3_then_ssub
    8187             :       0,        // dsub2_then_bsub
    8188             :       0,        // dsub2_then_hsub
    8189             :       0,        // dsub2_then_ssub
    8190             :       41,       // qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8191             :       41,       // qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8192             :       41,       // qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8193             :       41,       // qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8194             :       0,        // qsub3_then_bsub
    8195             :       0,        // qsub3_then_dsub
    8196             :       0,        // qsub3_then_hsub
    8197             :       0,        // qsub3_then_ssub
    8198             :       41,       // qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8199             :       41,       // qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8200             :       41,       // qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8201             :       41,       // qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8202             :       0,        // subo64_then_sub_32
    8203             :       0,        // dsub0_dsub1
    8204             :       0,        // dsub0_dsub1_dsub2
    8205             :       0,        // dsub1_dsub2
    8206             :       0,        // dsub1_dsub2_dsub3
    8207             :       0,        // dsub2_dsub3
    8208             :       41,       // dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8209             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8210             :       41,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8211             :       41,       // qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8212             :       0,        // qsub0_qsub1_qsub2
    8213             :       41,       // qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8214             :       0,        // qsub1_qsub2_qsub3
    8215             :       0,        // qsub2_qsub3
    8216             :       41,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    8217             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8218             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8219             :       0,        // sub_32_subo64_then_sub_32
    8220             :     },
    8221             :     {   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8222             :       42,       // bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8223             :       42,       // dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8224             :       0,        // dsub0
    8225             :       0,        // dsub1
    8226             :       0,        // dsub2
    8227             :       0,        // dsub3
    8228             :       42,       // hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8229             :       0,        // qhisub
    8230             :       0,        // qsub
    8231             :       42,       // qsub0 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8232             :       42,       // qsub1 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8233             :       42,       // qsub2 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8234             :       0,        // qsub3
    8235             :       42,       // ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8236             :       0,        // sub_32
    8237             :       0,        // sube32
    8238             :       0,        // sube64
    8239             :       0,        // subo32
    8240             :       0,        // subo64
    8241             :       0,        // dsub1_then_bsub
    8242             :       0,        // dsub1_then_hsub
    8243             :       0,        // dsub1_then_ssub
    8244             :       0,        // dsub3_then_bsub
    8245             :       0,        // dsub3_then_hsub
    8246             :       0,        // dsub3_then_ssub
    8247             :       0,        // dsub2_then_bsub
    8248             :       0,        // dsub2_then_hsub
    8249             :       0,        // dsub2_then_ssub
    8250             :       42,       // qsub1_then_bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8251             :       42,       // qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8252             :       42,       // qsub1_then_hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8253             :       42,       // qsub1_then_ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8254             :       0,        // qsub3_then_bsub
    8255             :       0,        // qsub3_then_dsub
    8256             :       0,        // qsub3_then_hsub
    8257             :       0,        // qsub3_then_ssub
    8258             :       42,       // qsub2_then_bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8259             :       42,       // qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8260             :       42,       // qsub2_then_hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8261             :       42,       // qsub2_then_ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8262             :       0,        // subo64_then_sub_32
    8263             :       0,        // dsub0_dsub1
    8264             :       0,        // dsub0_dsub1_dsub2
    8265             :       0,        // dsub1_dsub2
    8266             :       0,        // dsub1_dsub2_dsub3
    8267             :       0,        // dsub2_dsub3
    8268             :       42,       // dsub_qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8269             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8270             :       42,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8271             :       42,       // qsub0_qsub1 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8272             :       0,        // qsub0_qsub1_qsub2
    8273             :       42,       // qsub1_qsub2 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8274             :       0,        // qsub1_qsub2_qsub3
    8275             :       0,        // qsub2_qsub3
    8276             :       42,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8277             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8278             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8279             :       0,        // sub_32_subo64_then_sub_32
    8280             :     },
    8281             :     {   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8282             :       43,       // bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8283             :       43,       // dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8284             :       0,        // dsub0
    8285             :       0,        // dsub1
    8286             :       0,        // dsub2
    8287             :       0,        // dsub3
    8288             :       43,       // hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8289             :       0,        // qhisub
    8290             :       0,        // qsub
    8291             :       43,       // qsub0 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8292             :       43,       // qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8293             :       43,       // qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8294             :       0,        // qsub3
    8295             :       43,       // ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8296             :       0,        // sub_32
    8297             :       0,        // sube32
    8298             :       0,        // sube64
    8299             :       0,        // subo32
    8300             :       0,        // subo64
    8301             :       0,        // dsub1_then_bsub
    8302             :       0,        // dsub1_then_hsub
    8303             :       0,        // dsub1_then_ssub
    8304             :       0,        // dsub3_then_bsub
    8305             :       0,        // dsub3_then_hsub
    8306             :       0,        // dsub3_then_ssub
    8307             :       0,        // dsub2_then_bsub
    8308             :       0,        // dsub2_then_hsub
    8309             :       0,        // dsub2_then_ssub
    8310             :       43,       // qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8311             :       43,       // qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8312             :       43,       // qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8313             :       43,       // qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8314             :       0,        // qsub3_then_bsub
    8315             :       0,        // qsub3_then_dsub
    8316             :       0,        // qsub3_then_hsub
    8317             :       0,        // qsub3_then_ssub
    8318             :       43,       // qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8319             :       43,       // qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8320             :       43,       // qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8321             :       43,       // qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8322             :       0,        // subo64_then_sub_32
    8323             :       0,        // dsub0_dsub1
    8324             :       0,        // dsub0_dsub1_dsub2
    8325             :       0,        // dsub1_dsub2
    8326             :       0,        // dsub1_dsub2_dsub3
    8327             :       0,        // dsub2_dsub3
    8328             :       43,       // dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8329             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8330             :       43,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8331             :       43,       // qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8332             :       0,        // qsub0_qsub1_qsub2
    8333             :       43,       // qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8334             :       0,        // qsub1_qsub2_qsub3
    8335             :       0,        // qsub2_qsub3
    8336             :       43,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    8337             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8338             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8339             :       0,        // sub_32_subo64_then_sub_32
    8340             :     },
    8341             :     {   // QQQQ
    8342             :       44,       // bsub -> QQQQ
    8343             :       44,       // dsub -> QQQQ
    8344             :       0,        // dsub0
    8345             :       0,        // dsub1
    8346             :       0,        // dsub2
    8347             :       0,        // dsub3
    8348             :       44,       // hsub -> QQQQ
    8349             :       0,        // qhisub
    8350             :       0,        // qsub
    8351             :       44,       // qsub0 -> QQQQ
    8352             :       44,       // qsub1 -> QQQQ
    8353             :       44,       // qsub2 -> QQQQ
    8354             :       44,       // qsub3 -> QQQQ
    8355             :       44,       // ssub -> QQQQ
    8356             :       0,        // sub_32
    8357             :       0,        // sube32
    8358             :       0,        // sube64
    8359             :       0,        // subo32
    8360             :       0,        // subo64
    8361             :       0,        // dsub1_then_bsub
    8362             :       0,        // dsub1_then_hsub
    8363             :       0,        // dsub1_then_ssub
    8364             :       0,        // dsub3_then_bsub
    8365             :       0,        // dsub3_then_hsub
    8366             :       0,        // dsub3_then_ssub
    8367             :       0,        // dsub2_then_bsub
    8368             :       0,        // dsub2_then_hsub
    8369             :       0,        // dsub2_then_ssub
    8370             :       44,       // qsub1_then_bsub -> QQQQ
    8371             :       44,       // qsub1_then_dsub -> QQQQ
    8372             :       44,       // qsub1_then_hsub -> QQQQ
    8373             :       44,       // qsub1_then_ssub -> QQQQ
    8374             :       44,       // qsub3_then_bsub -> QQQQ
    8375             :       44,       // qsub3_then_dsub -> QQQQ
    8376             :       44,       // qsub3_then_hsub -> QQQQ
    8377             :       44,       // qsub3_then_ssub -> QQQQ
    8378             :       44,       // qsub2_then_bsub -> QQQQ
    8379             :       44,       // qsub2_then_dsub -> QQQQ
    8380             :       44,       // qsub2_then_hsub -> QQQQ
    8381             :       44,       // qsub2_then_ssub -> QQQQ
    8382             :       0,        // subo64_then_sub_32
    8383             :       0,        // dsub0_dsub1
    8384             :       0,        // dsub0_dsub1_dsub2
    8385             :       0,        // dsub1_dsub2
    8386             :       0,        // dsub1_dsub2_dsub3
    8387             :       0,        // dsub2_dsub3
    8388             :       44,       // dsub_qsub1_then_dsub -> QQQQ
    8389             :       44,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ
    8390             :       44,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ
    8391             :       44,       // qsub0_qsub1 -> QQQQ
    8392             :       44,       // qsub0_qsub1_qsub2 -> QQQQ
    8393             :       44,       // qsub1_qsub2 -> QQQQ
    8394             :       44,       // qsub1_qsub2_qsub3 -> QQQQ
    8395             :       44,       // qsub2_qsub3 -> QQQQ
    8396             :       44,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ
    8397             :       44,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ
    8398             :       44,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ
    8399             :       0,        // sub_32_subo64_then_sub_32
    8400             :     },
    8401             :     {   // QQQQ_with_qsub0_in_FPR128_lo
    8402             :       45,       // bsub -> QQQQ_with_qsub0_in_FPR128_lo
    8403             :       45,       // dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8404             :       0,        // dsub0
    8405             :       0,        // dsub1
    8406             :       0,        // dsub2
    8407             :       0,        // dsub3
    8408             :       45,       // hsub -> QQQQ_with_qsub0_in_FPR128_lo
    8409             :       0,        // qhisub
    8410             :       0,        // qsub
    8411             :       45,       // qsub0 -> QQQQ_with_qsub0_in_FPR128_lo
    8412             :       45,       // qsub1 -> QQQQ_with_qsub0_in_FPR128_lo
    8413             :       45,       // qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
    8414             :       45,       // qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
    8415             :       45,       // ssub -> QQQQ_with_qsub0_in_FPR128_lo
    8416             :       0,        // sub_32
    8417             :       0,        // sube32
    8418             :       0,        // sube64
    8419             :       0,        // subo32
    8420             :       0,        // subo64
    8421             :       0,        // dsub1_then_bsub
    8422             :       0,        // dsub1_then_hsub
    8423             :       0,        // dsub1_then_ssub
    8424             :       0,        // dsub3_then_bsub
    8425             :       0,        // dsub3_then_hsub
    8426             :       0,        // dsub3_then_ssub
    8427             :       0,        // dsub2_then_bsub
    8428             :       0,        // dsub2_then_hsub
    8429             :       0,        // dsub2_then_ssub
    8430             :       45,       // qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
    8431             :       45,       // qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8432             :       45,       // qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
    8433             :       45,       // qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
    8434             :       45,       // qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
    8435             :       45,       // qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8436             :       45,       // qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
    8437             :       45,       // qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
    8438             :       45,       // qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
    8439             :       45,       // qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8440             :       45,       // qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
    8441             :       45,       // qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
    8442             :       0,        // subo64_then_sub_32
    8443             :       0,        // dsub0_dsub1
    8444             :       0,        // dsub0_dsub1_dsub2
    8445             :       0,        // dsub1_dsub2
    8446             :       0,        // dsub1_dsub2_dsub3
    8447             :       0,        // dsub2_dsub3
    8448             :       45,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8449             :       45,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8450             :       45,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8451             :       45,       // qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo
    8452             :       45,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
    8453             :       45,       // qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
    8454             :       45,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
    8455             :       45,       // qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
    8456             :       45,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8457             :       45,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8458             :       45,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    8459             :       0,        // sub_32_subo64_then_sub_32
    8460             :     },
    8461             :     {   // QQQQ_with_qsub1_in_FPR128_lo
    8462             :       46,       // bsub -> QQQQ_with_qsub1_in_FPR128_lo
    8463             :       46,       // dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8464             :       0,        // dsub0
    8465             :       0,        // dsub1
    8466             :       0,        // dsub2
    8467             :       0,        // dsub3
    8468             :       46,       // hsub -> QQQQ_with_qsub1_in_FPR128_lo
    8469             :       0,        // qhisub
    8470             :       0,        // qsub
    8471             :       46,       // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo
    8472             :       46,       // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo
    8473             :       46,       // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
    8474             :       46,       // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
    8475             :       46,       // ssub -> QQQQ_with_qsub1_in_FPR128_lo
    8476             :       0,        // sub_32
    8477             :       0,        // sube32
    8478             :       0,        // sube64
    8479             :       0,        // subo32
    8480             :       0,        // subo64
    8481             :       0,        // dsub1_then_bsub
    8482             :       0,        // dsub1_then_hsub
    8483             :       0,        // dsub1_then_ssub
    8484             :       0,        // dsub3_then_bsub
    8485             :       0,        // dsub3_then_hsub
    8486             :       0,        // dsub3_then_ssub
    8487             :       0,        // dsub2_then_bsub
    8488             :       0,        // dsub2_then_hsub
    8489             :       0,        // dsub2_then_ssub
    8490             :       46,       // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
    8491             :       46,       // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8492             :       46,       // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
    8493             :       46,       // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
    8494             :       46,       // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
    8495             :       46,       // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8496             :       46,       // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
    8497             :       46,       // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
    8498             :       46,       // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
    8499             :       46,       // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8500             :       46,       // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
    8501             :       46,       // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
    8502             :       0,        // subo64_then_sub_32
    8503             :       0,        // dsub0_dsub1
    8504             :       0,        // dsub0_dsub1_dsub2
    8505             :       0,        // dsub1_dsub2
    8506             :       0,        // dsub1_dsub2_dsub3
    8507             :       0,        // dsub2_dsub3
    8508             :       46,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8509             :       46,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8510             :       46,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8511             :       46,       // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo
    8512             :       46,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
    8513             :       46,       // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
    8514             :       46,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
    8515             :       46,       // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
    8516             :       46,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8517             :       46,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8518             :       46,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    8519             :       0,        // sub_32_subo64_then_sub_32
    8520             :     },
    8521             :     {   // QQQQ_with_qsub2_in_FPR128_lo
    8522             :       47,       // bsub -> QQQQ_with_qsub2_in_FPR128_lo
    8523             :       47,       // dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8524             :       0,        // dsub0
    8525             :       0,        // dsub1
    8526             :       0,        // dsub2
    8527             :       0,        // dsub3
    8528             :       47,       // hsub -> QQQQ_with_qsub2_in_FPR128_lo
    8529             :       0,        // qhisub
    8530             :       0,        // qsub
    8531             :       47,       // qsub0 -> QQQQ_with_qsub2_in_FPR128_lo
    8532             :       47,       // qsub1 -> QQQQ_with_qsub2_in_FPR128_lo
    8533             :       47,       // qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
    8534             :       47,       // qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
    8535             :       47,       // ssub -> QQQQ_with_qsub2_in_FPR128_lo
    8536             :       0,        // sub_32
    8537             :       0,        // sube32
    8538             :       0,        // sube64
    8539             :       0,        // subo32
    8540             :       0,        // subo64
    8541             :       0,        // dsub1_then_bsub
    8542             :       0,        // dsub1_then_hsub
    8543             :       0,        // dsub1_then_ssub
    8544             :       0,        // dsub3_then_bsub
    8545             :       0,        // dsub3_then_hsub
    8546             :       0,        // dsub3_then_ssub
    8547             :       0,        // dsub2_then_bsub
    8548             :       0,        // dsub2_then_hsub
    8549             :       0,        // dsub2_then_ssub
    8550             :       47,       // qsub1_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
    8551             :       47,       // qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8552             :       47,       // qsub1_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
    8553             :       47,       // qsub1_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
    8554             :       47,       // qsub3_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
    8555             :       47,       // qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8556             :       47,       // qsub3_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
    8557             :       47,       // qsub3_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
    8558             :       47,       // qsub2_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
    8559             :       47,       // qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8560             :       47,       // qsub2_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
    8561             :       47,       // qsub2_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
    8562             :       0,        // subo64_then_sub_32
    8563             :       0,        // dsub0_dsub1
    8564             :       0,        // dsub0_dsub1_dsub2
    8565             :       0,        // dsub1_dsub2
    8566             :       0,        // dsub1_dsub2_dsub3
    8567             :       0,        // dsub2_dsub3
    8568             :       47,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8569             :       47,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8570             :       47,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8571             :       47,       // qsub0_qsub1 -> QQQQ_with_qsub2_in_FPR128_lo
    8572             :       47,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
    8573             :       47,       // qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
    8574             :       47,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
    8575             :       47,       // qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
    8576             :       47,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8577             :       47,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8578             :       47,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    8579             :       0,        // sub_32_subo64_then_sub_32
    8580             :     },
    8581             :     {   // QQQQ_with_qsub3_in_FPR128_lo
    8582             :       48,       // bsub -> QQQQ_with_qsub3_in_FPR128_lo
    8583             :       48,       // dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8584             :       0,        // dsub0
    8585             :       0,        // dsub1
    8586             :       0,        // dsub2
    8587             :       0,        // dsub3
    8588             :       48,       // hsub -> QQQQ_with_qsub3_in_FPR128_lo
    8589             :       0,        // qhisub
    8590             :       0,        // qsub
    8591             :       48,       // qsub0 -> QQQQ_with_qsub3_in_FPR128_lo
    8592             :       48,       // qsub1 -> QQQQ_with_qsub3_in_FPR128_lo
    8593             :       48,       // qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
    8594             :       48,       // qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
    8595             :       48,       // ssub -> QQQQ_with_qsub3_in_FPR128_lo
    8596             :       0,        // sub_32
    8597             :       0,        // sube32
    8598             :       0,        // sube64
    8599             :       0,        // subo32
    8600             :       0,        // subo64
    8601             :       0,        // dsub1_then_bsub
    8602             :       0,        // dsub1_then_hsub
    8603             :       0,        // dsub1_then_ssub
    8604             :       0,        // dsub3_then_bsub
    8605             :       0,        // dsub3_then_hsub
    8606             :       0,        // dsub3_then_ssub
    8607             :       0,        // dsub2_then_bsub
    8608             :       0,        // dsub2_then_hsub
    8609             :       0,        // dsub2_then_ssub
    8610             :       48,       // qsub1_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
    8611             :       48,       // qsub1_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8612             :       48,       // qsub1_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
    8613             :       48,       // qsub1_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
    8614             :       48,       // qsub3_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
    8615             :       48,       // qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8616             :       48,       // qsub3_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
    8617             :       48,       // qsub3_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
    8618             :       48,       // qsub2_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
    8619             :       48,       // qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8620             :       48,       // qsub2_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
    8621             :       48,       // qsub2_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
    8622             :       0,        // subo64_then_sub_32
    8623             :       0,        // dsub0_dsub1
    8624             :       0,        // dsub0_dsub1_dsub2
    8625             :       0,        // dsub1_dsub2
    8626             :       0,        // dsub1_dsub2_dsub3
    8627             :       0,        // dsub2_dsub3
    8628             :       48,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8629             :       48,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8630             :       48,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8631             :       48,       // qsub0_qsub1 -> QQQQ_with_qsub3_in_FPR128_lo
    8632             :       48,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
    8633             :       48,       // qsub1_qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
    8634             :       48,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
    8635             :       48,       // qsub2_qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
    8636             :       48,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8637             :       48,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8638             :       48,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    8639             :       0,        // sub_32_subo64_then_sub_32
    8640             :     },
    8641             :     {   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8642             :       49,       // bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8643             :       49,       // dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8644             :       0,        // dsub0
    8645             :       0,        // dsub1
    8646             :       0,        // dsub2
    8647             :       0,        // dsub3
    8648             :       49,       // hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8649             :       0,        // qhisub
    8650             :       0,        // qsub
    8651             :       49,       // qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8652             :       49,       // qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8653             :       49,       // qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8654             :       49,       // qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8655             :       49,       // ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8656             :       0,        // sub_32
    8657             :       0,        // sube32
    8658             :       0,        // sube64
    8659             :       0,        // subo32
    8660             :       0,        // subo64
    8661             :       0,        // dsub1_then_bsub
    8662             :       0,        // dsub1_then_hsub
    8663             :       0,        // dsub1_then_ssub
    8664             :       0,        // dsub3_then_bsub
    8665             :       0,        // dsub3_then_hsub
    8666             :       0,        // dsub3_then_ssub
    8667             :       0,        // dsub2_then_bsub
    8668             :       0,        // dsub2_then_hsub
    8669             :       0,        // dsub2_then_ssub
    8670             :       49,       // qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8671             :       49,       // qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8672             :       49,       // qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8673             :       49,       // qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8674             :       49,       // qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8675             :       49,       // qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8676             :       49,       // qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8677             :       49,       // qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8678             :       49,       // qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8679             :       49,       // qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8680             :       49,       // qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8681             :       49,       // qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8682             :       0,        // subo64_then_sub_32
    8683             :       0,        // dsub0_dsub1
    8684             :       0,        // dsub0_dsub1_dsub2
    8685             :       0,        // dsub1_dsub2
    8686             :       0,        // dsub1_dsub2_dsub3
    8687             :       0,        // dsub2_dsub3
    8688             :       49,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8689             :       49,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8690             :       49,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8691             :       49,       // qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8692             :       49,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8693             :       49,       // qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8694             :       49,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8695             :       49,       // qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8696             :       49,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8697             :       49,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8698             :       49,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    8699             :       0,        // sub_32_subo64_then_sub_32
    8700             :     },
    8701             :     {   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8702             :       50,       // bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8703             :       50,       // dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8704             :       0,        // dsub0
    8705             :       0,        // dsub1
    8706             :       0,        // dsub2
    8707             :       0,        // dsub3
    8708             :       50,       // hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8709             :       0,        // qhisub
    8710             :       0,        // qsub
    8711             :       50,       // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8712             :       50,       // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8713             :       50,       // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8714             :       50,       // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8715             :       50,       // ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8716             :       0,        // sub_32
    8717             :       0,        // sube32
    8718             :       0,        // sube64
    8719             :       0,        // subo32
    8720             :       0,        // subo64
    8721             :       0,        // dsub1_then_bsub
    8722             :       0,        // dsub1_then_hsub
    8723             :       0,        // dsub1_then_ssub
    8724             :       0,        // dsub3_then_bsub
    8725             :       0,        // dsub3_then_hsub
    8726             :       0,        // dsub3_then_ssub
    8727             :       0,        // dsub2_then_bsub
    8728             :       0,        // dsub2_then_hsub
    8729             :       0,        // dsub2_then_ssub
    8730             :       50,       // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8731             :       50,       // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8732             :       50,       // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8733             :       50,       // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8734             :       50,       // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8735             :       50,       // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8736             :       50,       // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8737             :       50,       // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8738             :       50,       // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8739             :       50,       // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8740             :       50,       // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8741             :       50,       // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8742             :       0,        // subo64_then_sub_32
    8743             :       0,        // dsub0_dsub1
    8744             :       0,        // dsub0_dsub1_dsub2
    8745             :       0,        // dsub1_dsub2
    8746             :       0,        // dsub1_dsub2_dsub3
    8747             :       0,        // dsub2_dsub3
    8748             :       50,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8749             :       50,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8750             :       50,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8751             :       50,       // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8752             :       50,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8753             :       50,       // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8754             :       50,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8755             :       50,       // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8756             :       50,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8757             :       50,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8758             :       50,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8759             :       0,        // sub_32_subo64_then_sub_32
    8760             :     },
    8761             :     {   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8762             :       51,       // bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8763             :       51,       // dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8764             :       0,        // dsub0
    8765             :       0,        // dsub1
    8766             :       0,        // dsub2
    8767             :       0,        // dsub3
    8768             :       51,       // hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8769             :       0,        // qhisub
    8770             :       0,        // qsub
    8771             :       51,       // qsub0 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8772             :       51,       // qsub1 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8773             :       51,       // qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8774             :       51,       // qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8775             :       51,       // ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8776             :       0,        // sub_32
    8777             :       0,        // sube32
    8778             :       0,        // sube64
    8779             :       0,        // subo32
    8780             :       0,        // subo64
    8781             :       0,        // dsub1_then_bsub
    8782             :       0,        // dsub1_then_hsub
    8783             :       0,        // dsub1_then_ssub
    8784             :       0,        // dsub3_then_bsub
    8785             :       0,        // dsub3_then_hsub
    8786             :       0,        // dsub3_then_ssub
    8787             :       0,        // dsub2_then_bsub
    8788             :       0,        // dsub2_then_hsub
    8789             :       0,        // dsub2_then_ssub
    8790             :       51,       // qsub1_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8791             :       51,       // qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8792             :       51,       // qsub1_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8793             :       51,       // qsub1_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8794             :       51,       // qsub3_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8795             :       51,       // qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8796             :       51,       // qsub3_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8797             :       51,       // qsub3_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8798             :       51,       // qsub2_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8799             :       51,       // qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8800             :       51,       // qsub2_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8801             :       51,       // qsub2_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8802             :       0,        // subo64_then_sub_32
    8803             :       0,        // dsub0_dsub1
    8804             :       0,        // dsub0_dsub1_dsub2
    8805             :       0,        // dsub1_dsub2
    8806             :       0,        // dsub1_dsub2_dsub3
    8807             :       0,        // dsub2_dsub3
    8808             :       51,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8809             :       51,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8810             :       51,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8811             :       51,       // qsub0_qsub1 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8812             :       51,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8813             :       51,       // qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8814             :       51,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8815             :       51,       // qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8816             :       51,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8817             :       51,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8818             :       51,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8819             :       0,        // sub_32_subo64_then_sub_32
    8820             :     },
    8821             :     {   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8822             :       52,       // bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8823             :       52,       // dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8824             :       0,        // dsub0
    8825             :       0,        // dsub1
    8826             :       0,        // dsub2
    8827             :       0,        // dsub3
    8828             :       52,       // hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8829             :       0,        // qhisub
    8830             :       0,        // qsub
    8831             :       52,       // qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8832             :       52,       // qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8833             :       52,       // qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8834             :       52,       // qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8835             :       52,       // ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8836             :       0,        // sub_32
    8837             :       0,        // sube32
    8838             :       0,        // sube64
    8839             :       0,        // subo32
    8840             :       0,        // subo64
    8841             :       0,        // dsub1_then_bsub
    8842             :       0,        // dsub1_then_hsub
    8843             :       0,        // dsub1_then_ssub
    8844             :       0,        // dsub3_then_bsub
    8845             :       0,        // dsub3_then_hsub
    8846             :       0,        // dsub3_then_ssub
    8847             :       0,        // dsub2_then_bsub
    8848             :       0,        // dsub2_then_hsub
    8849             :       0,        // dsub2_then_ssub
    8850             :       52,       // qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8851             :       52,       // qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8852             :       52,       // qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8853             :       52,       // qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8854             :       52,       // qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8855             :       52,       // qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8856             :       52,       // qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8857             :       52,       // qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8858             :       52,       // qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8859             :       52,       // qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8860             :       52,       // qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8861             :       52,       // qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8862             :       0,        // subo64_then_sub_32
    8863             :       0,        // dsub0_dsub1
    8864             :       0,        // dsub0_dsub1_dsub2
    8865             :       0,        // dsub1_dsub2
    8866             :       0,        // dsub1_dsub2_dsub3
    8867             :       0,        // dsub2_dsub3
    8868             :       52,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8869             :       52,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8870             :       52,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8871             :       52,       // qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8872             :       52,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8873             :       52,       // qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8874             :       52,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8875             :       52,       // qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8876             :       52,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8877             :       52,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8878             :       52,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    8879             :       0,        // sub_32_subo64_then_sub_32
    8880             :     },
    8881             :     {   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8882             :       53,       // bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8883             :       53,       // dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8884             :       0,        // dsub0
    8885             :       0,        // dsub1
    8886             :       0,        // dsub2
    8887             :       0,        // dsub3
    8888             :       53,       // hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8889             :       0,        // qhisub
    8890             :       0,        // qsub
    8891             :       53,       // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8892             :       53,       // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8893             :       53,       // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8894             :       53,       // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8895             :       53,       // ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8896             :       0,        // sub_32
    8897             :       0,        // sube32
    8898             :       0,        // sube64
    8899             :       0,        // subo32
    8900             :       0,        // subo64
    8901             :       0,        // dsub1_then_bsub
    8902             :       0,        // dsub1_then_hsub
    8903             :       0,        // dsub1_then_ssub
    8904             :       0,        // dsub3_then_bsub
    8905             :       0,        // dsub3_then_hsub
    8906             :       0,        // dsub3_then_ssub
    8907             :       0,        // dsub2_then_bsub
    8908             :       0,        // dsub2_then_hsub
    8909             :       0,        // dsub2_then_ssub
    8910             :       53,       // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8911             :       53,       // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8912             :       53,       // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8913             :       53,       // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8914             :       53,       // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8915             :       53,       // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8916             :       53,       // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8917             :       53,       // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8918             :       53,       // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8919             :       53,       // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8920             :       53,       // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8921             :       53,       // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8922             :       0,        // subo64_then_sub_32
    8923             :       0,        // dsub0_dsub1
    8924             :       0,        // dsub0_dsub1_dsub2
    8925             :       0,        // dsub1_dsub2
    8926             :       0,        // dsub1_dsub2_dsub3
    8927             :       0,        // dsub2_dsub3
    8928             :       53,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8929             :       53,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8930             :       53,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8931             :       53,       // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8932             :       53,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8933             :       53,       // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8934             :       53,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8935             :       53,       // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8936             :       53,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8937             :       53,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8938             :       53,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8939             :       0,        // sub_32_subo64_then_sub_32
    8940             :     },
    8941             :     {   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8942             :       54,       // bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8943             :       54,       // dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8944             :       0,        // dsub0
    8945             :       0,        // dsub1
    8946             :       0,        // dsub2
    8947             :       0,        // dsub3
    8948             :       54,       // hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8949             :       0,        // qhisub
    8950             :       0,        // qsub
    8951             :       54,       // qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8952             :       54,       // qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8953             :       54,       // qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8954             :       54,       // qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8955             :       54,       // ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8956             :       0,        // sub_32
    8957             :       0,        // sube32
    8958             :       0,        // sube64
    8959             :       0,        // subo32
    8960             :       0,        // subo64
    8961             :       0,        // dsub1_then_bsub
    8962             :       0,        // dsub1_then_hsub
    8963             :       0,        // dsub1_then_ssub
    8964             :       0,        // dsub3_then_bsub
    8965             :       0,        // dsub3_then_hsub
    8966             :       0,        // dsub3_then_ssub
    8967             :       0,        // dsub2_then_bsub
    8968             :       0,        // dsub2_then_hsub
    8969             :       0,        // dsub2_then_ssub
    8970             :       54,       // qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8971             :       54,       // qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8972             :       54,       // qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8973             :       54,       // qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8974             :       54,       // qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8975             :       54,       // qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8976             :       54,       // qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8977             :       54,       // qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8978             :       54,       // qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8979             :       54,       // qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8980             :       54,       // qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8981             :       54,       // qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8982             :       0,        // subo64_then_sub_32
    8983             :       0,        // dsub0_dsub1
    8984             :       0,        // dsub0_dsub1_dsub2
    8985             :       0,        // dsub1_dsub2
    8986             :       0,        // dsub1_dsub2_dsub3
    8987             :       0,        // dsub2_dsub3
    8988             :       54,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8989             :       54,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8990             :       54,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8991             :       54,       // qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8992             :       54,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8993             :       54,       // qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8994             :       54,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8995             :       54,       // qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8996             :       54,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8997             :       54,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8998             :       54,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    8999             :       0,        // sub_32_subo64_then_sub_32
    9000             :     },
    9001             :   };
    9002             :   assert(RC && "Missing regclass");
    9003       29015 :   if (!Idx) return RC;
    9004       29015 :   --Idx;
    9005             :   assert(Idx < 58 && "Bad subreg");
    9006       58030 :   unsigned TV = Table[RC->getID()][Idx];
    9007       58030 :   return TV ? getRegClass(TV - 1) : nullptr;
    9008             : }
    9009             : 
    9010             : /// Get the weight in units of pressure for this register class.
    9011       83841 : const RegClassWeight &AArch64GenRegisterInfo::
    9012             : getRegClassWeight(const TargetRegisterClass *RC) const {
    9013             :   static const RegClassWeight RCWeightTable[] = {
    9014             :     {1, 32},    // FPR8
    9015             :     {1, 32},    // FPR16
    9016             :     {1, 33},    // GPR32all
    9017             :     {1, 32},    // FPR32
    9018             :     {1, 32},    // GPR32
    9019             :     {1, 32},    // GPR32sp
    9020             :     {1, 31},    // GPR32common
    9021             :     {0, 0},     // CCR
    9022             :     {1, 1},     // GPR32sponly
    9023             :     {2, 32},    // WSeqPairsClass
    9024             :     {2, 32},    // WSeqPairsClass_with_sube32_in_GPR32common
    9025             :     {2, 32},    // WSeqPairsClass_with_subo32_in_GPR32common
    9026             :     {2, 31},    // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    9027             :     {1, 33},    // GPR64all
    9028             :     {1, 32},    // FPR64
    9029             :     {1, 32},    // GPR64
    9030             :     {1, 32},    // GPR64sp
    9031             :     {1, 31},    // GPR64common
    9032             :     {1, 19},    // tcGPR64
    9033             :     {1, 1},     // GPR64sponly
    9034             :     {2, 32},    // DD
    9035             :     {2, 32},    // XSeqPairsClass
    9036             :     {2, 32},    // XSeqPairsClass_with_sub_32_in_GPR32common
    9037             :     {2, 32},    // XSeqPairsClass_with_subo64_in_GPR64common
    9038             :     {2, 31},    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    9039             :     {2, 20},    // XSeqPairsClass_with_sube64_in_tcGPR64
    9040             :     {2, 20},    // XSeqPairsClass_with_subo64_in_tcGPR64
    9041             :     {2, 19},    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    9042             :     {1, 32},    // FPR128
    9043             :     {1, 16},    // FPR128_lo
    9044             :     {3, 32},    // DDD
    9045             :     {4, 32},    // DDDD
    9046             :     {2, 32},    // QQ
    9047             :     {2, 17},    // QQ_with_qsub0_in_FPR128_lo
    9048             :     {2, 17},    // QQ_with_qsub1_in_FPR128_lo
    9049             :     {2, 16},    // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    9050             :     {3, 32},    // QQQ
    9051             :     {3, 18},    // QQQ_with_qsub0_in_FPR128_lo
    9052             :     {3, 18},    // QQQ_with_qsub1_in_FPR128_lo
    9053             :     {3, 18},    // QQQ_with_qsub2_in_FPR128_lo
    9054             :     {3, 17},    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9055             :     {3, 17},    // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9056             :     {3, 16},    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9057             :     {4, 32},    // QQQQ
    9058             :     {4, 19},    // QQQQ_with_qsub0_in_FPR128_lo
    9059             :     {4, 19},    // QQQQ_with_qsub1_in_FPR128_lo
    9060             :     {4, 19},    // QQQQ_with_qsub2_in_FPR128_lo
    9061             :     {4, 19},    // QQQQ_with_qsub3_in_FPR128_lo
    9062             :     {4, 18},    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9063             :     {4, 18},    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9064             :     {4, 18},    // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9065             :     {4, 17},    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9066             :     {4, 17},    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9067             :     {4, 16},    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9068             :   };
    9069      167682 :   return RCWeightTable[RC->getID()];
    9070             : }
    9071             : 
    9072             : /// Get the weight in units of pressure for this register unit.
    9073       17893 : unsigned AArch64GenRegisterInfo::
    9074             : getRegUnitWeight(unsigned RegUnit) const {
    9075             :   assert(RegUnit < 66 && "invalid register unit");
    9076             :   // All register units have unit weight.
    9077       17893 :   return 1;
    9078             : }
    9079             : 
    9080             : 
    9081             : // Get the number of dimensions of register pressure.
    9082       16571 : unsigned AArch64GenRegisterInfo::getNumRegPressureSets() const {
    9083       16571 :   return 5;
    9084             : }
    9085             : 
    9086             : // Get the name of this register unit pressure set.
    9087           0 : const char *AArch64GenRegisterInfo::
    9088             : getRegPressureSetName(unsigned Idx) const {
    9089             :   static const char *const PressureNameTable[] = {
    9090             :     "GPR32sponly",
    9091             :     "tcGPR64",
    9092             :     "FPR128_lo",
    9093             :     "FPR8",
    9094             :     "GPR32",
    9095             :   };
    9096           0 :   return PressureNameTable[Idx];
    9097             : }
    9098             : 
    9099             : // Get the register unit pressure limit for this dimension.
    9100             : // This limit must be adjusted dynamically for reserved registers.
    9101       55648 : unsigned AArch64GenRegisterInfo::
    9102             : getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
    9103             :   static const uint8_t PressureLimitTable[] = {
    9104             :     1,          // 0: GPR32sponly
    9105             :     21,         // 1: tcGPR64
    9106             :     22,         // 2: FPR128_lo
    9107             :     32,         // 3: FPR8
    9108             :     33,         // 4: GPR32
    9109             :   };
    9110       55648 :   return PressureLimitTable[Idx];
    9111             : }
    9112             : 
    9113             : /// Table of pressure sets per register class or unit.
    9114             : static const int RCSetsTable[] = {
    9115             :   /* 0 */ 2, 3, -1,
    9116             :   /* 3 */ 0, 4, -1,
    9117             :   /* 6 */ 1, 4, -1,
    9118             : };
    9119             : 
    9120             : /// Get the dimensions of register pressure impacted by this register class.
    9121             : /// Returns a -1 terminated array of pressure set IDs
    9122      108134 : const int* AArch64GenRegisterInfo::
    9123             : getRegClassPressureSets(const TargetRegisterClass *RC) const {
    9124             :   static const uint8_t RCSetStartTable[] = {
    9125             :     1,1,4,1,4,4,4,2,3,4,4,4,4,4,1,4,4,4,6,3,1,4,4,4,4,6,6,6,1,0,1,1,1,0,0,0,1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,};
    9126      216268 :   return &RCSetsTable[RCSetStartTable[RC->getID()]];
    9127             : }
    9128             : 
    9129             : /// Get the dimensions of register pressure impacted by this register unit.
    9130             : /// Returns a -1 terminated array of pressure set IDs
    9131       17893 : const int* AArch64GenRegisterInfo::
    9132             : getRegUnitPressureSets(unsigned RegUnit) const {
    9133             :   assert(RegUnit < 66 && "invalid register unit");
    9134             :   static const uint8_t RUSetStartTable[] = {
    9135             :     4,4,2,3,6,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,0,0,0,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,4,4,4,4,4,4,4,4,4,};
    9136       17893 :   return &RCSetsTable[RUSetStartTable[RegUnit]];
    9137             : }
    9138             : 
    9139             : extern const MCRegisterDesc AArch64RegDesc[];
    9140             : extern const MCPhysReg AArch64RegDiffLists[];
    9141             : extern const LaneBitmask AArch64LaneMaskLists[];
    9142             : extern const char AArch64RegStrings[];
    9143             : extern const char AArch64RegClassStrings[];
    9144             : extern const MCPhysReg AArch64RegUnitRoots[][2];
    9145             : extern const uint16_t AArch64SubRegIdxLists[];
    9146             : extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[];
    9147             : extern const uint16_t AArch64RegEncodingTable[];
    9148             : // AArch64 Dwarf<->LLVM register mappings.
    9149             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[];
    9150             : extern const unsigned AArch64DwarfFlavour0Dwarf2LSize;
    9151             : 
    9152             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[];
    9153             : extern const unsigned AArch64EHFlavour0Dwarf2LSize;
    9154             : 
    9155             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[];
    9156             : extern const unsigned AArch64DwarfFlavour0L2DwarfSize;
    9157             : 
    9158             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[];
    9159             : extern const unsigned AArch64EHFlavour0L2DwarfSize;
    9160             : 
    9161        1217 : AArch64GenRegisterInfo::
    9162        1217 : AArch64GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)
    9163             :   : TargetRegisterInfo(AArch64RegInfoDesc, RegisterClasses, RegisterClasses+54,
    9164        2434 :              SubRegIndexNameTable, SubRegIndexLaneMaskTable, LaneBitmask(0xFFFFFFF6)) {
    9165        2434 :   InitMCRegisterInfo(AArch64RegDesc, 484, RA, PC,
    9166             :                      AArch64MCRegisterClasses, 54,
    9167             :                      AArch64RegUnitRoots,
    9168             :                      66,
    9169             :                      AArch64RegDiffLists,
    9170             :                      AArch64LaneMaskLists,
    9171             :                      AArch64RegStrings,
    9172             :                      AArch64RegClassStrings,
    9173             :                      AArch64SubRegIdxLists,
    9174             :                      59,
    9175             :                      AArch64SubRegIdxRanges,
    9176             :                      AArch64RegEncodingTable);
    9177             : 
    9178        1217 :   switch (DwarfFlavour) {
    9179           0 :   default:
    9180           0 :     llvm_unreachable("Unknown DWARF flavour");
    9181        1217 :   case 0:
    9182        2434 :     mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
    9183             :     break;
    9184             :   }
    9185        1217 :   switch (EHFlavour) {
    9186           0 :   default:
    9187           0 :     llvm_unreachable("Unknown DWARF flavour");
    9188        1217 :   case 0:
    9189        2434 :     mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
    9190             :     break;
    9191             :   }
    9192        1217 :   switch (DwarfFlavour) {
    9193           0 :   default:
    9194           0 :     llvm_unreachable("Unknown DWARF flavour");
    9195        1217 :   case 0:
    9196        2434 :     mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
    9197             :     break;
    9198             :   }
    9199        1217 :   switch (EHFlavour) {
    9200           0 :   default:
    9201           0 :     llvm_unreachable("Unknown DWARF flavour");
    9202        1217 :   case 0:
    9203        2434 :     mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
    9204             :     break;
    9205             :   }
    9206        1217 : }
    9207             : 
    9208             : static const MCPhysReg CSR_AArch64_AAPCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
    9209             : static const uint32_t CSR_AArch64_AAPCS_RegMask[] = { 0x00ff0006, 0x00ff0000, 0x00ff0000, 0x00000000, 0x00ff0000, 0xf8000000, 0xfc00007f, 0x0007f00f, 0x0001f000, 0x0003f000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xf800009f, 0x0000000f, };
    9210             : static const MCPhysReg CSR_AArch64_AAPCS_SwiftError_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
    9211             : static const uint32_t CSR_AArch64_AAPCS_SwiftError_RegMask[] = { 0x00ff0006, 0x00ff0000, 0x00ff0000, 0x00000000, 0x00ff0000, 0xd8000000, 0xec00007f, 0x0007f00f, 0x0001f000, 0x0003f000, 0x00000000, 0x00000000, 0x00000000, 0xf2000000, 0xc800009f, 0x0000000f, };
    9212             : static const MCPhysReg CSR_AArch64_AAPCS_ThisReturn_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, 0 };
    9213             : static const uint32_t CSR_AArch64_AAPCS_ThisReturn_RegMask[] = { 0x00ff0006, 0x00ff0000, 0x00ff0000, 0x00000000, 0x00ff0000, 0xf8000100, 0xfc0000ff, 0x0007f00f, 0x0001f000, 0x0003f000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xf800009f, 0x0000000f, };
    9214             : static const MCPhysReg CSR_AArch64_AllRegs_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
    9215             : static const uint32_t CSR_AArch64_AllRegs_RegMask[] = { 0xffffff36, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffcf, 0xffffff9f, 0x0000000f, };
    9216             : static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 };
    9217             : static const uint32_t CSR_AArch64_CXX_TLS_Darwin_RegMask[] = { 0xffffff06, 0xffffffff, 0xffffffff, 0x000000ff, 0xffffff00, 0xf87ffeff, 0xfc3fff7f, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000000f, 0x00000000, 0x00000000, 0xfe0fff80, 0xf83ffe9f, 0x0000000f, };
    9218             : static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_PE_SaveList[] = { AArch64::LR, AArch64::FP, 0 };
    9219             : static const uint32_t CSR_AArch64_CXX_TLS_Darwin_PE_RegMask[] = { 0x00000006, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000018, 0x00000000, };
    9220             : static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 };
    9221             : static const uint32_t CSR_AArch64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0xffffff00, 0xffffffff, 0xffffffff, 0x000000ff, 0xffffff00, 0xf87ffeff, 0xfc3fff1f, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000000f, 0x00000000, 0x00000000, 0xfe0fff80, 0xf83ffe03, 0x0000000f, };
    9222             : static const MCPhysReg CSR_AArch64_NoRegs_SaveList[] = { 0 };
    9223             : static const uint32_t CSR_AArch64_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
    9224             : static const MCPhysReg CSR_AArch64_RT_MostRegs_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, 0 };
    9225             : static const uint32_t CSR_AArch64_RT_MostRegs_RegMask[] = { 0x00ff0006, 0x00ff0000, 0x00ff0000, 0x00000000, 0x00ff0000, 0xf8fe0000, 0xfc7f007f, 0x0007f00f, 0x0001f000, 0x0003f000, 0x00000000, 0x00000000, 0x00000000, 0xfe1f8000, 0xf87e009f, 0x0000000f, };
    9226             : static const MCPhysReg CSR_AArch64_TLS_Darwin_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
    9227             : static const uint32_t CSR_AArch64_TLS_Darwin_RegMask[] = { 0xffffff02, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xfcfffeff, 0xfe7fff3f, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xff1fff8f, 0xfc7ffe87, 0x0000000f, };
    9228             : static const MCPhysReg CSR_AArch64_TLS_ELF_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
    9229             : static const uint32_t CSR_AArch64_TLS_ELF_RegMask[] = { 0xffffff02, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xfffffeff, 0xffffff3f, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff8f, 0xfffffe87, 0x0000000f, };
    9230             : 
    9231             : 
    9232         647 : ArrayRef<const uint32_t *> AArch64GenRegisterInfo::getRegMasks() const {
    9233             :   static const uint32_t *const Masks[] = {
    9234             :     CSR_AArch64_AAPCS_RegMask,
    9235             :     CSR_AArch64_AAPCS_SwiftError_RegMask,
    9236             :     CSR_AArch64_AAPCS_ThisReturn_RegMask,
    9237             :     CSR_AArch64_AllRegs_RegMask,
    9238             :     CSR_AArch64_CXX_TLS_Darwin_RegMask,
    9239             :     CSR_AArch64_CXX_TLS_Darwin_PE_RegMask,
    9240             :     CSR_AArch64_CXX_TLS_Darwin_ViaCopy_RegMask,
    9241             :     CSR_AArch64_NoRegs_RegMask,
    9242             :     CSR_AArch64_RT_MostRegs_RegMask,
    9243             :     CSR_AArch64_TLS_Darwin_RegMask,
    9244             :     CSR_AArch64_TLS_ELF_RegMask,
    9245             :   };
    9246         647 :   return makeArrayRef(Masks);
    9247             : }
    9248             : 
    9249          50 : ArrayRef<const char *> AArch64GenRegisterInfo::getRegMaskNames() const {
    9250             :   static const char *const Names[] = {
    9251             :     "CSR_AArch64_AAPCS",
    9252             :     "CSR_AArch64_AAPCS_SwiftError",
    9253             :     "CSR_AArch64_AAPCS_ThisReturn",
    9254             :     "CSR_AArch64_AllRegs",
    9255             :     "CSR_AArch64_CXX_TLS_Darwin",
    9256             :     "CSR_AArch64_CXX_TLS_Darwin_PE",
    9257             :     "CSR_AArch64_CXX_TLS_Darwin_ViaCopy",
    9258             :     "CSR_AArch64_NoRegs",
    9259             :     "CSR_AArch64_RT_MostRegs",
    9260             :     "CSR_AArch64_TLS_Darwin",
    9261             :     "CSR_AArch64_TLS_ELF",
    9262             :   };
    9263          50 :   return makeArrayRef(Names);
    9264             : }
    9265             : 
    9266             : const AArch64FrameLowering *
    9267      169791 : AArch64GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
    9268             :   return static_cast<const AArch64FrameLowering *>(
    9269      169791 :       MF.getSubtarget().getFrameLowering());
    9270             : }
    9271             : 
    9272             : } // end namespace llvm
    9273             : 
    9274             : #endif // GET_REGINFO_TARGET_DESC
    9275             : 

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