LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenRegisterInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 56 80 70.0 %
Date: 2018-02-22 04:41:24 Functions: 18 21 85.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Register Enum Values                                                *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_REGINFO_ENUM
      11             : #undef GET_REGINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : 
      15             : class MCRegisterClass;
      16             : extern const MCRegisterClass AArch64MCRegisterClasses[];
      17             : 
      18             : namespace AArch64 {
      19             : enum {
      20             :   NoRegister,
      21             :   FP = 1,
      22             :   LR = 2,
      23             :   NZCV = 3,
      24             :   SP = 4,
      25             :   WSP = 5,
      26             :   WZR = 6,
      27             :   XZR = 7,
      28             :   B0 = 8,
      29             :   B1 = 9,
      30             :   B2 = 10,
      31             :   B3 = 11,
      32             :   B4 = 12,
      33             :   B5 = 13,
      34             :   B6 = 14,
      35             :   B7 = 15,
      36             :   B8 = 16,
      37             :   B9 = 17,
      38             :   B10 = 18,
      39             :   B11 = 19,
      40             :   B12 = 20,
      41             :   B13 = 21,
      42             :   B14 = 22,
      43             :   B15 = 23,
      44             :   B16 = 24,
      45             :   B17 = 25,
      46             :   B18 = 26,
      47             :   B19 = 27,
      48             :   B20 = 28,
      49             :   B21 = 29,
      50             :   B22 = 30,
      51             :   B23 = 31,
      52             :   B24 = 32,
      53             :   B25 = 33,
      54             :   B26 = 34,
      55             :   B27 = 35,
      56             :   B28 = 36,
      57             :   B29 = 37,
      58             :   B30 = 38,
      59             :   B31 = 39,
      60             :   D0 = 40,
      61             :   D1 = 41,
      62             :   D2 = 42,
      63             :   D3 = 43,
      64             :   D4 = 44,
      65             :   D5 = 45,
      66             :   D6 = 46,
      67             :   D7 = 47,
      68             :   D8 = 48,
      69             :   D9 = 49,
      70             :   D10 = 50,
      71             :   D11 = 51,
      72             :   D12 = 52,
      73             :   D13 = 53,
      74             :   D14 = 54,
      75             :   D15 = 55,
      76             :   D16 = 56,
      77             :   D17 = 57,
      78             :   D18 = 58,
      79             :   D19 = 59,
      80             :   D20 = 60,
      81             :   D21 = 61,
      82             :   D22 = 62,
      83             :   D23 = 63,
      84             :   D24 = 64,
      85             :   D25 = 65,
      86             :   D26 = 66,
      87             :   D27 = 67,
      88             :   D28 = 68,
      89             :   D29 = 69,
      90             :   D30 = 70,
      91             :   D31 = 71,
      92             :   H0 = 72,
      93             :   H1 = 73,
      94             :   H2 = 74,
      95             :   H3 = 75,
      96             :   H4 = 76,
      97             :   H5 = 77,
      98             :   H6 = 78,
      99             :   H7 = 79,
     100             :   H8 = 80,
     101             :   H9 = 81,
     102             :   H10 = 82,
     103             :   H11 = 83,
     104             :   H12 = 84,
     105             :   H13 = 85,
     106             :   H14 = 86,
     107             :   H15 = 87,
     108             :   H16 = 88,
     109             :   H17 = 89,
     110             :   H18 = 90,
     111             :   H19 = 91,
     112             :   H20 = 92,
     113             :   H21 = 93,
     114             :   H22 = 94,
     115             :   H23 = 95,
     116             :   H24 = 96,
     117             :   H25 = 97,
     118             :   H26 = 98,
     119             :   H27 = 99,
     120             :   H28 = 100,
     121             :   H29 = 101,
     122             :   H30 = 102,
     123             :   H31 = 103,
     124             :   P0 = 104,
     125             :   P1 = 105,
     126             :   P2 = 106,
     127             :   P3 = 107,
     128             :   P4 = 108,
     129             :   P5 = 109,
     130             :   P6 = 110,
     131             :   P7 = 111,
     132             :   P8 = 112,
     133             :   P9 = 113,
     134             :   P10 = 114,
     135             :   P11 = 115,
     136             :   P12 = 116,
     137             :   P13 = 117,
     138             :   P14 = 118,
     139             :   P15 = 119,
     140             :   Q0 = 120,
     141             :   Q1 = 121,
     142             :   Q2 = 122,
     143             :   Q3 = 123,
     144             :   Q4 = 124,
     145             :   Q5 = 125,
     146             :   Q6 = 126,
     147             :   Q7 = 127,
     148             :   Q8 = 128,
     149             :   Q9 = 129,
     150             :   Q10 = 130,
     151             :   Q11 = 131,
     152             :   Q12 = 132,
     153             :   Q13 = 133,
     154             :   Q14 = 134,
     155             :   Q15 = 135,
     156             :   Q16 = 136,
     157             :   Q17 = 137,
     158             :   Q18 = 138,
     159             :   Q19 = 139,
     160             :   Q20 = 140,
     161             :   Q21 = 141,
     162             :   Q22 = 142,
     163             :   Q23 = 143,
     164             :   Q24 = 144,
     165             :   Q25 = 145,
     166             :   Q26 = 146,
     167             :   Q27 = 147,
     168             :   Q28 = 148,
     169             :   Q29 = 149,
     170             :   Q30 = 150,
     171             :   Q31 = 151,
     172             :   S0 = 152,
     173             :   S1 = 153,
     174             :   S2 = 154,
     175             :   S3 = 155,
     176             :   S4 = 156,
     177             :   S5 = 157,
     178             :   S6 = 158,
     179             :   S7 = 159,
     180             :   S8 = 160,
     181             :   S9 = 161,
     182             :   S10 = 162,
     183             :   S11 = 163,
     184             :   S12 = 164,
     185             :   S13 = 165,
     186             :   S14 = 166,
     187             :   S15 = 167,
     188             :   S16 = 168,
     189             :   S17 = 169,
     190             :   S18 = 170,
     191             :   S19 = 171,
     192             :   S20 = 172,
     193             :   S21 = 173,
     194             :   S22 = 174,
     195             :   S23 = 175,
     196             :   S24 = 176,
     197             :   S25 = 177,
     198             :   S26 = 178,
     199             :   S27 = 179,
     200             :   S28 = 180,
     201             :   S29 = 181,
     202             :   S30 = 182,
     203             :   S31 = 183,
     204             :   W0 = 184,
     205             :   W1 = 185,
     206             :   W2 = 186,
     207             :   W3 = 187,
     208             :   W4 = 188,
     209             :   W5 = 189,
     210             :   W6 = 190,
     211             :   W7 = 191,
     212             :   W8 = 192,
     213             :   W9 = 193,
     214             :   W10 = 194,
     215             :   W11 = 195,
     216             :   W12 = 196,
     217             :   W13 = 197,
     218             :   W14 = 198,
     219             :   W15 = 199,
     220             :   W16 = 200,
     221             :   W17 = 201,
     222             :   W18 = 202,
     223             :   W19 = 203,
     224             :   W20 = 204,
     225             :   W21 = 205,
     226             :   W22 = 206,
     227             :   W23 = 207,
     228             :   W24 = 208,
     229             :   W25 = 209,
     230             :   W26 = 210,
     231             :   W27 = 211,
     232             :   W28 = 212,
     233             :   W29 = 213,
     234             :   W30 = 214,
     235             :   X0 = 215,
     236             :   X1 = 216,
     237             :   X2 = 217,
     238             :   X3 = 218,
     239             :   X4 = 219,
     240             :   X5 = 220,
     241             :   X6 = 221,
     242             :   X7 = 222,
     243             :   X8 = 223,
     244             :   X9 = 224,
     245             :   X10 = 225,
     246             :   X11 = 226,
     247             :   X12 = 227,
     248             :   X13 = 228,
     249             :   X14 = 229,
     250             :   X15 = 230,
     251             :   X16 = 231,
     252             :   X17 = 232,
     253             :   X18 = 233,
     254             :   X19 = 234,
     255             :   X20 = 235,
     256             :   X21 = 236,
     257             :   X22 = 237,
     258             :   X23 = 238,
     259             :   X24 = 239,
     260             :   X25 = 240,
     261             :   X26 = 241,
     262             :   X27 = 242,
     263             :   X28 = 243,
     264             :   Z0 = 244,
     265             :   Z1 = 245,
     266             :   Z2 = 246,
     267             :   Z3 = 247,
     268             :   Z4 = 248,
     269             :   Z5 = 249,
     270             :   Z6 = 250,
     271             :   Z7 = 251,
     272             :   Z8 = 252,
     273             :   Z9 = 253,
     274             :   Z10 = 254,
     275             :   Z11 = 255,
     276             :   Z12 = 256,
     277             :   Z13 = 257,
     278             :   Z14 = 258,
     279             :   Z15 = 259,
     280             :   Z16 = 260,
     281             :   Z17 = 261,
     282             :   Z18 = 262,
     283             :   Z19 = 263,
     284             :   Z20 = 264,
     285             :   Z21 = 265,
     286             :   Z22 = 266,
     287             :   Z23 = 267,
     288             :   Z24 = 268,
     289             :   Z25 = 269,
     290             :   Z26 = 270,
     291             :   Z27 = 271,
     292             :   Z28 = 272,
     293             :   Z29 = 273,
     294             :   Z30 = 274,
     295             :   Z31 = 275,
     296             :   Z0_HI = 276,
     297             :   Z1_HI = 277,
     298             :   Z2_HI = 278,
     299             :   Z3_HI = 279,
     300             :   Z4_HI = 280,
     301             :   Z5_HI = 281,
     302             :   Z6_HI = 282,
     303             :   Z7_HI = 283,
     304             :   Z8_HI = 284,
     305             :   Z9_HI = 285,
     306             :   Z10_HI = 286,
     307             :   Z11_HI = 287,
     308             :   Z12_HI = 288,
     309             :   Z13_HI = 289,
     310             :   Z14_HI = 290,
     311             :   Z15_HI = 291,
     312             :   Z16_HI = 292,
     313             :   Z17_HI = 293,
     314             :   Z18_HI = 294,
     315             :   Z19_HI = 295,
     316             :   Z20_HI = 296,
     317             :   Z21_HI = 297,
     318             :   Z22_HI = 298,
     319             :   Z23_HI = 299,
     320             :   Z24_HI = 300,
     321             :   Z25_HI = 301,
     322             :   Z26_HI = 302,
     323             :   Z27_HI = 303,
     324             :   Z28_HI = 304,
     325             :   Z29_HI = 305,
     326             :   Z30_HI = 306,
     327             :   Z31_HI = 307,
     328             :   D0_D1 = 308,
     329             :   D1_D2 = 309,
     330             :   D2_D3 = 310,
     331             :   D3_D4 = 311,
     332             :   D4_D5 = 312,
     333             :   D5_D6 = 313,
     334             :   D6_D7 = 314,
     335             :   D7_D8 = 315,
     336             :   D8_D9 = 316,
     337             :   D9_D10 = 317,
     338             :   D10_D11 = 318,
     339             :   D11_D12 = 319,
     340             :   D12_D13 = 320,
     341             :   D13_D14 = 321,
     342             :   D14_D15 = 322,
     343             :   D15_D16 = 323,
     344             :   D16_D17 = 324,
     345             :   D17_D18 = 325,
     346             :   D18_D19 = 326,
     347             :   D19_D20 = 327,
     348             :   D20_D21 = 328,
     349             :   D21_D22 = 329,
     350             :   D22_D23 = 330,
     351             :   D23_D24 = 331,
     352             :   D24_D25 = 332,
     353             :   D25_D26 = 333,
     354             :   D26_D27 = 334,
     355             :   D27_D28 = 335,
     356             :   D28_D29 = 336,
     357             :   D29_D30 = 337,
     358             :   D30_D31 = 338,
     359             :   D31_D0 = 339,
     360             :   D0_D1_D2_D3 = 340,
     361             :   D1_D2_D3_D4 = 341,
     362             :   D2_D3_D4_D5 = 342,
     363             :   D3_D4_D5_D6 = 343,
     364             :   D4_D5_D6_D7 = 344,
     365             :   D5_D6_D7_D8 = 345,
     366             :   D6_D7_D8_D9 = 346,
     367             :   D7_D8_D9_D10 = 347,
     368             :   D8_D9_D10_D11 = 348,
     369             :   D9_D10_D11_D12 = 349,
     370             :   D10_D11_D12_D13 = 350,
     371             :   D11_D12_D13_D14 = 351,
     372             :   D12_D13_D14_D15 = 352,
     373             :   D13_D14_D15_D16 = 353,
     374             :   D14_D15_D16_D17 = 354,
     375             :   D15_D16_D17_D18 = 355,
     376             :   D16_D17_D18_D19 = 356,
     377             :   D17_D18_D19_D20 = 357,
     378             :   D18_D19_D20_D21 = 358,
     379             :   D19_D20_D21_D22 = 359,
     380             :   D20_D21_D22_D23 = 360,
     381             :   D21_D22_D23_D24 = 361,
     382             :   D22_D23_D24_D25 = 362,
     383             :   D23_D24_D25_D26 = 363,
     384             :   D24_D25_D26_D27 = 364,
     385             :   D25_D26_D27_D28 = 365,
     386             :   D26_D27_D28_D29 = 366,
     387             :   D27_D28_D29_D30 = 367,
     388             :   D28_D29_D30_D31 = 368,
     389             :   D29_D30_D31_D0 = 369,
     390             :   D30_D31_D0_D1 = 370,
     391             :   D31_D0_D1_D2 = 371,
     392             :   D0_D1_D2 = 372,
     393             :   D1_D2_D3 = 373,
     394             :   D2_D3_D4 = 374,
     395             :   D3_D4_D5 = 375,
     396             :   D4_D5_D6 = 376,
     397             :   D5_D6_D7 = 377,
     398             :   D6_D7_D8 = 378,
     399             :   D7_D8_D9 = 379,
     400             :   D8_D9_D10 = 380,
     401             :   D9_D10_D11 = 381,
     402             :   D10_D11_D12 = 382,
     403             :   D11_D12_D13 = 383,
     404             :   D12_D13_D14 = 384,
     405             :   D13_D14_D15 = 385,
     406             :   D14_D15_D16 = 386,
     407             :   D15_D16_D17 = 387,
     408             :   D16_D17_D18 = 388,
     409             :   D17_D18_D19 = 389,
     410             :   D18_D19_D20 = 390,
     411             :   D19_D20_D21 = 391,
     412             :   D20_D21_D22 = 392,
     413             :   D21_D22_D23 = 393,
     414             :   D22_D23_D24 = 394,
     415             :   D23_D24_D25 = 395,
     416             :   D24_D25_D26 = 396,
     417             :   D25_D26_D27 = 397,
     418             :   D26_D27_D28 = 398,
     419             :   D27_D28_D29 = 399,
     420             :   D28_D29_D30 = 400,
     421             :   D29_D30_D31 = 401,
     422             :   D30_D31_D0 = 402,
     423             :   D31_D0_D1 = 403,
     424             :   Q0_Q1 = 404,
     425             :   Q1_Q2 = 405,
     426             :   Q2_Q3 = 406,
     427             :   Q3_Q4 = 407,
     428             :   Q4_Q5 = 408,
     429             :   Q5_Q6 = 409,
     430             :   Q6_Q7 = 410,
     431             :   Q7_Q8 = 411,
     432             :   Q8_Q9 = 412,
     433             :   Q9_Q10 = 413,
     434             :   Q10_Q11 = 414,
     435             :   Q11_Q12 = 415,
     436             :   Q12_Q13 = 416,
     437             :   Q13_Q14 = 417,
     438             :   Q14_Q15 = 418,
     439             :   Q15_Q16 = 419,
     440             :   Q16_Q17 = 420,
     441             :   Q17_Q18 = 421,
     442             :   Q18_Q19 = 422,
     443             :   Q19_Q20 = 423,
     444             :   Q20_Q21 = 424,
     445             :   Q21_Q22 = 425,
     446             :   Q22_Q23 = 426,
     447             :   Q23_Q24 = 427,
     448             :   Q24_Q25 = 428,
     449             :   Q25_Q26 = 429,
     450             :   Q26_Q27 = 430,
     451             :   Q27_Q28 = 431,
     452             :   Q28_Q29 = 432,
     453             :   Q29_Q30 = 433,
     454             :   Q30_Q31 = 434,
     455             :   Q31_Q0 = 435,
     456             :   Q0_Q1_Q2_Q3 = 436,
     457             :   Q1_Q2_Q3_Q4 = 437,
     458             :   Q2_Q3_Q4_Q5 = 438,
     459             :   Q3_Q4_Q5_Q6 = 439,
     460             :   Q4_Q5_Q6_Q7 = 440,
     461             :   Q5_Q6_Q7_Q8 = 441,
     462             :   Q6_Q7_Q8_Q9 = 442,
     463             :   Q7_Q8_Q9_Q10 = 443,
     464             :   Q8_Q9_Q10_Q11 = 444,
     465             :   Q9_Q10_Q11_Q12 = 445,
     466             :   Q10_Q11_Q12_Q13 = 446,
     467             :   Q11_Q12_Q13_Q14 = 447,
     468             :   Q12_Q13_Q14_Q15 = 448,
     469             :   Q13_Q14_Q15_Q16 = 449,
     470             :   Q14_Q15_Q16_Q17 = 450,
     471             :   Q15_Q16_Q17_Q18 = 451,
     472             :   Q16_Q17_Q18_Q19 = 452,
     473             :   Q17_Q18_Q19_Q20 = 453,
     474             :   Q18_Q19_Q20_Q21 = 454,
     475             :   Q19_Q20_Q21_Q22 = 455,
     476             :   Q20_Q21_Q22_Q23 = 456,
     477             :   Q21_Q22_Q23_Q24 = 457,
     478             :   Q22_Q23_Q24_Q25 = 458,
     479             :   Q23_Q24_Q25_Q26 = 459,
     480             :   Q24_Q25_Q26_Q27 = 460,
     481             :   Q25_Q26_Q27_Q28 = 461,
     482             :   Q26_Q27_Q28_Q29 = 462,
     483             :   Q27_Q28_Q29_Q30 = 463,
     484             :   Q28_Q29_Q30_Q31 = 464,
     485             :   Q29_Q30_Q31_Q0 = 465,
     486             :   Q30_Q31_Q0_Q1 = 466,
     487             :   Q31_Q0_Q1_Q2 = 467,
     488             :   Q0_Q1_Q2 = 468,
     489             :   Q1_Q2_Q3 = 469,
     490             :   Q2_Q3_Q4 = 470,
     491             :   Q3_Q4_Q5 = 471,
     492             :   Q4_Q5_Q6 = 472,
     493             :   Q5_Q6_Q7 = 473,
     494             :   Q6_Q7_Q8 = 474,
     495             :   Q7_Q8_Q9 = 475,
     496             :   Q8_Q9_Q10 = 476,
     497             :   Q9_Q10_Q11 = 477,
     498             :   Q10_Q11_Q12 = 478,
     499             :   Q11_Q12_Q13 = 479,
     500             :   Q12_Q13_Q14 = 480,
     501             :   Q13_Q14_Q15 = 481,
     502             :   Q14_Q15_Q16 = 482,
     503             :   Q15_Q16_Q17 = 483,
     504             :   Q16_Q17_Q18 = 484,
     505             :   Q17_Q18_Q19 = 485,
     506             :   Q18_Q19_Q20 = 486,
     507             :   Q19_Q20_Q21 = 487,
     508             :   Q20_Q21_Q22 = 488,
     509             :   Q21_Q22_Q23 = 489,
     510             :   Q22_Q23_Q24 = 490,
     511             :   Q23_Q24_Q25 = 491,
     512             :   Q24_Q25_Q26 = 492,
     513             :   Q25_Q26_Q27 = 493,
     514             :   Q26_Q27_Q28 = 494,
     515             :   Q27_Q28_Q29 = 495,
     516             :   Q28_Q29_Q30 = 496,
     517             :   Q29_Q30_Q31 = 497,
     518             :   Q30_Q31_Q0 = 498,
     519             :   Q31_Q0_Q1 = 499,
     520             :   WZR_W0 = 500,
     521             :   W30_WZR = 501,
     522             :   W0_W1 = 502,
     523             :   W1_W2 = 503,
     524             :   W2_W3 = 504,
     525             :   W3_W4 = 505,
     526             :   W4_W5 = 506,
     527             :   W5_W6 = 507,
     528             :   W6_W7 = 508,
     529             :   W7_W8 = 509,
     530             :   W8_W9 = 510,
     531             :   W9_W10 = 511,
     532             :   W10_W11 = 512,
     533             :   W11_W12 = 513,
     534             :   W12_W13 = 514,
     535             :   W13_W14 = 515,
     536             :   W14_W15 = 516,
     537             :   W15_W16 = 517,
     538             :   W16_W17 = 518,
     539             :   W17_W18 = 519,
     540             :   W18_W19 = 520,
     541             :   W19_W20 = 521,
     542             :   W20_W21 = 522,
     543             :   W21_W22 = 523,
     544             :   W22_W23 = 524,
     545             :   W23_W24 = 525,
     546             :   W24_W25 = 526,
     547             :   W25_W26 = 527,
     548             :   W26_W27 = 528,
     549             :   W27_W28 = 529,
     550             :   W28_W29 = 530,
     551             :   W29_W30 = 531,
     552             :   FP_LR = 532,
     553             :   LR_XZR = 533,
     554             :   XZR_X0 = 534,
     555             :   X28_FP = 535,
     556             :   X0_X1 = 536,
     557             :   X1_X2 = 537,
     558             :   X2_X3 = 538,
     559             :   X3_X4 = 539,
     560             :   X4_X5 = 540,
     561             :   X5_X6 = 541,
     562             :   X6_X7 = 542,
     563             :   X7_X8 = 543,
     564             :   X8_X9 = 544,
     565             :   X9_X10 = 545,
     566             :   X10_X11 = 546,
     567             :   X11_X12 = 547,
     568             :   X12_X13 = 548,
     569             :   X13_X14 = 549,
     570             :   X14_X15 = 550,
     571             :   X15_X16 = 551,
     572             :   X16_X17 = 552,
     573             :   X17_X18 = 553,
     574             :   X18_X19 = 554,
     575             :   X19_X20 = 555,
     576             :   X20_X21 = 556,
     577             :   X21_X22 = 557,
     578             :   X22_X23 = 558,
     579             :   X23_X24 = 559,
     580             :   X24_X25 = 560,
     581             :   X25_X26 = 561,
     582             :   X26_X27 = 562,
     583             :   X27_X28 = 563,
     584             :   NUM_TARGET_REGS       // 564
     585             : };
     586             : } // end namespace AArch64
     587             : 
     588             : // Register classes
     589             : 
     590             : namespace AArch64 {
     591             : enum {
     592             :   FPR8RegClassID = 0,
     593             :   FPR16RegClassID = 1,
     594             :   PPRRegClassID = 2,
     595             :   PPR_3bRegClassID = 3,
     596             :   GPR32allRegClassID = 4,
     597             :   FPR32RegClassID = 5,
     598             :   GPR32RegClassID = 6,
     599             :   GPR32spRegClassID = 7,
     600             :   GPR32commonRegClassID = 8,
     601             :   CCRRegClassID = 9,
     602             :   GPR32sponlyRegClassID = 10,
     603             :   WSeqPairsClassRegClassID = 11,
     604             :   WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12,
     605             :   WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
     606             :   WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14,
     607             :   GPR64allRegClassID = 15,
     608             :   FPR64RegClassID = 16,
     609             :   GPR64RegClassID = 17,
     610             :   GPR64spRegClassID = 18,
     611             :   GPR64commonRegClassID = 19,
     612             :   tcGPR64RegClassID = 20,
     613             :   GPR64sponlyRegClassID = 21,
     614             :   DDRegClassID = 22,
     615             :   XSeqPairsClassRegClassID = 23,
     616             :   XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 24,
     617             :   XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 25,
     618             :   XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26,
     619             :   XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 27,
     620             :   XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 28,
     621             :   XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29,
     622             :   FPR128RegClassID = 30,
     623             :   ZPRRegClassID = 31,
     624             :   FPR128_loRegClassID = 32,
     625             :   ZPR_with_zsub_in_FPR128_loRegClassID = 33,
     626             :   DDDRegClassID = 34,
     627             :   DDDDRegClassID = 35,
     628             :   QQRegClassID = 36,
     629             :   QQ_with_qsub0_in_FPR128_loRegClassID = 37,
     630             :   QQ_with_qsub1_in_FPR128_loRegClassID = 38,
     631             :   QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 39,
     632             :   QQQRegClassID = 40,
     633             :   QQQ_with_qsub0_in_FPR128_loRegClassID = 41,
     634             :   QQQ_with_qsub1_in_FPR128_loRegClassID = 42,
     635             :   QQQ_with_qsub2_in_FPR128_loRegClassID = 43,
     636             :   QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 44,
     637             :   QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 45,
     638             :   QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 46,
     639             :   QQQQRegClassID = 47,
     640             :   QQQQ_with_qsub0_in_FPR128_loRegClassID = 48,
     641             :   QQQQ_with_qsub1_in_FPR128_loRegClassID = 49,
     642             :   QQQQ_with_qsub2_in_FPR128_loRegClassID = 50,
     643             :   QQQQ_with_qsub3_in_FPR128_loRegClassID = 51,
     644             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 52,
     645             :   QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 53,
     646             :   QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 54,
     647             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 55,
     648             :   QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 56,
     649             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 57,
     650             : 
     651             :   };
     652             : } // end namespace AArch64
     653             : 
     654             : 
     655             : // Register alternate name indices
     656             : 
     657             : namespace AArch64 {
     658             : enum {
     659             :   NoRegAltName, // 0
     660             :   vlist1,       // 1
     661             :   vreg, // 2
     662             :   NUM_TARGET_REG_ALT_NAMES = 3
     663             : };
     664             : } // end namespace AArch64
     665             : 
     666             : 
     667             : // Subregister indices
     668             : 
     669             : namespace AArch64 {
     670             : enum {
     671             :   NoSubRegister,
     672             :   bsub, // 1
     673             :   dsub, // 2
     674             :   dsub0,        // 3
     675             :   dsub1,        // 4
     676             :   dsub2,        // 5
     677             :   dsub3,        // 6
     678             :   hsub, // 7
     679             :   qhisub,       // 8
     680             :   qsub, // 9
     681             :   qsub0,        // 10
     682             :   qsub1,        // 11
     683             :   qsub2,        // 12
     684             :   qsub3,        // 13
     685             :   ssub, // 14
     686             :   sub_32,       // 15
     687             :   sube32,       // 16
     688             :   sube64,       // 17
     689             :   subo32,       // 18
     690             :   subo64,       // 19
     691             :   zsub, // 20
     692             :   zsub_hi,      // 21
     693             :   dsub1_then_bsub,      // 22
     694             :   dsub1_then_hsub,      // 23
     695             :   dsub1_then_ssub,      // 24
     696             :   dsub3_then_bsub,      // 25
     697             :   dsub3_then_hsub,      // 26
     698             :   dsub3_then_ssub,      // 27
     699             :   dsub2_then_bsub,      // 28
     700             :   dsub2_then_hsub,      // 29
     701             :   dsub2_then_ssub,      // 30
     702             :   qsub1_then_bsub,      // 31
     703             :   qsub1_then_dsub,      // 32
     704             :   qsub1_then_hsub,      // 33
     705             :   qsub1_then_ssub,      // 34
     706             :   qsub3_then_bsub,      // 35
     707             :   qsub3_then_dsub,      // 36
     708             :   qsub3_then_hsub,      // 37
     709             :   qsub3_then_ssub,      // 38
     710             :   qsub2_then_bsub,      // 39
     711             :   qsub2_then_dsub,      // 40
     712             :   qsub2_then_hsub,      // 41
     713             :   qsub2_then_ssub,      // 42
     714             :   subo64_then_sub_32,   // 43
     715             :   dsub0_dsub1,  // 44
     716             :   dsub0_dsub1_dsub2,    // 45
     717             :   dsub1_dsub2,  // 46
     718             :   dsub1_dsub2_dsub3,    // 47
     719             :   dsub2_dsub3,  // 48
     720             :   dsub_qsub1_then_dsub, // 49
     721             :   dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 50
     722             :   dsub_qsub1_then_dsub_qsub2_then_dsub, // 51
     723             :   qsub0_qsub1,  // 52
     724             :   qsub0_qsub1_qsub2,    // 53
     725             :   qsub1_qsub2,  // 54
     726             :   qsub1_qsub2_qsub3,    // 55
     727             :   qsub2_qsub3,  // 56
     728             :   qsub1_then_dsub_qsub2_then_dsub,      // 57
     729             :   qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,      // 58
     730             :   qsub2_then_dsub_qsub3_then_dsub,      // 59
     731             :   sub_32_subo64_then_sub_32,    // 60
     732             :   NUM_TARGET_SUBREGS
     733             : };
     734             : } // end namespace AArch64
     735             : 
     736             : } // end namespace llvm
     737             : 
     738             : #endif // GET_REGINFO_ENUM
     739             : 
     740             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
     741             : |*                                                                            *|
     742             : |* MC Register Information                                                    *|
     743             : |*                                                                            *|
     744             : |* Automatically generated file, do not edit!                                 *|
     745             : |*                                                                            *|
     746             : \*===----------------------------------------------------------------------===*/
     747             : 
     748             : 
     749             : #ifdef GET_REGINFO_MC_DESC
     750             : #undef GET_REGINFO_MC_DESC
     751             : 
     752             : namespace llvm {
     753             : 
     754             : extern const MCPhysReg AArch64RegDiffLists[] = {
     755             :   /* 0 */ 0, 1, 0,
     756             :   /* 3 */ 65105, 1, 1, 1, 0,
     757             :   /* 8 */ 65201, 1, 1, 1, 0,
     758             :   /* 13 */ 5, 29, 1, 1, 0,
     759             :   /* 18 */ 65324, 499, 30, 1, 1, 0,
     760             :   /* 24 */ 65073, 1, 1, 0,
     761             :   /* 28 */ 65169, 1, 1, 0,
     762             :   /* 32 */ 5, 1, 29, 1, 0,
     763             :   /* 37 */ 5, 30, 1, 0,
     764             :   /* 41 */ 1, 493, 1, 32, 1, 0,
     765             :   /* 47 */ 31, 286, 1, 33, 1, 0,
     766             :   /* 53 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
     767             :   /* 68 */ 320, 1, 0,
     768             :   /* 71 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
     769             :   /* 86 */ 526, 1, 0,
     770             :   /* 89 */ 530, 1, 0,
     771             :   /* 92 */ 65053, 1, 0,
     772             :   /* 95 */ 65087, 1, 0,
     773             :   /* 98 */ 65137, 1, 0,
     774             :   /* 101 */ 65218, 1, 0,
     775             :   /* 104 */ 65233, 1, 0,
     776             :   /* 107 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     777             :   /* 131 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     778             :   /* 142 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     779             :   /* 166 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     780             :   /* 177 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 0,
     781             :   /* 189 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     782             :   /* 213 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     783             :   /* 224 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 0,
     784             :   /* 236 */ 65503, 1, 128, 65503, 1, 0,
     785             :   /* 242 */ 31, 285, 2, 32, 2, 0,
     786             :   /* 248 */ 319, 2, 0,
     787             :   /* 251 */ 65324, 529, 1, 1, 3, 0,
     788             :   /* 257 */ 531, 3, 0,
     789             :   /* 260 */ 65004, 3, 0,
     790             :   /* 263 */ 4, 0,
     791             :   /* 265 */ 5, 0,
     792             :   /* 267 */ 31, 286, 1, 5, 28, 0,
     793             :   /* 273 */ 292, 28, 0,
     794             :   /* 276 */ 5, 1, 1, 29, 0,
     795             :   /* 281 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     796             :   /* 305 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     797             :   /* 316 */ 5, 1, 30, 0,
     798             :   /* 320 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 0,
     799             :   /* 332 */ 5, 31, 0,
     800             :   /* 335 */ 65504, 31, 97, 65504, 31, 0,
     801             :   /* 341 */ 32, 0,
     802             :   /* 343 */ 34, 0,
     803             :   /* 345 */ 4, 49, 0,
     804             :   /* 348 */ 63938, 49, 0,
     805             :   /* 351 */ 65297, 77, 0,
     806             :   /* 354 */ 0, 81, 0,
     807             :   /* 357 */ 96, 0,
     808             :   /* 359 */ 65042, 178, 0,
     809             :   /* 362 */ 212, 0,
     810             :   /* 364 */ 65412, 65456, 112, 65456, 65472, 268, 0,
     811             :   /* 371 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
     812             :   /* 383 */ 65009, 65535, 209, 65505, 316, 0,
     813             :   /* 389 */ 65005, 212, 65325, 212, 317, 0,
     814             :   /* 395 */ 65244, 65505, 65325, 212, 317, 0,
     815             :   /* 401 */ 65215, 65505, 32, 65505, 317, 0,
     816             :   /* 407 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
     817             :   /* 419 */ 65005, 212, 65329, 65535, 495, 0,
     818             :   /* 425 */ 65323, 0,
     819             :   /* 427 */ 65249, 65328, 0,
     820             :   /* 430 */ 65342, 0,
     821             :   /* 432 */ 65374, 0,
     822             :   /* 434 */ 65389, 0,
     823             :   /* 436 */ 65405, 0,
     824             :   /* 438 */ 65421, 0,
     825             :   /* 440 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
     826             :   /* 461 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
     827             :   /* 482 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
     828             :   /* 503 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
     829             :   /* 535 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
     830             :   /* 557 */ 65469, 0,
     831             :   /* 559 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
     832             :   /* 568 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
     833             :   /* 577 */ 65456, 112, 65456, 65472, 0,
     834             :   /* 582 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
     835             :   /* 614 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
     836             :   /* 646 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
     837             :   /* 678 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
     838             :   /* 700 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
     839             :   /* 722 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
     840             :   /* 744 */ 65501, 0,
     841             :   /* 746 */ 65504, 0,
     842             :   /* 748 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
     843             :   /* 763 */ 65533, 0,
     844             :   /* 765 */ 65535, 0,
     845             : };
     846             : 
     847             : extern const LaneBitmask AArch64LaneMaskLists[] = {
     848             :   /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
     849             :   /* 2 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     850             :   /* 5 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     851             :   /* 10 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     852             :   /* 14 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     853             :   /* 17 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     854             :   /* 22 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     855             :   /* 26 */ LaneBitmask(0x00002000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
     856             :   /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
     857             :   /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
     858             :   /* 35 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
     859             :   /* 38 */ LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
     860             :   /* 43 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
     861             :   /* 47 */ LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask::getAll(),
     862             :   /* 52 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask::getAll(),
     863             :   /* 57 */ LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
     864             :   /* 62 */ LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
     865             :   /* 66 */ LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask::getAll(),
     866             :   /* 71 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask::getAll(),
     867             :   /* 76 */ LaneBitmask(0x00000008), LaneBitmask(0x00002000), LaneBitmask::getAll(),
     868             : };
     869             : 
     870             : extern const uint16_t AArch64SubRegIdxLists[] = {
     871             :   /* 0 */ 2, 14, 7, 1, 0,
     872             :   /* 5 */ 15, 0,
     873             :   /* 7 */ 16, 18, 0,
     874             :   /* 10 */ 20, 2, 14, 7, 1, 21, 0,
     875             :   /* 17 */ 3, 14, 7, 1, 4, 24, 23, 22, 0,
     876             :   /* 26 */ 3, 14, 7, 1, 4, 24, 23, 22, 5, 30, 29, 28, 44, 46, 0,
     877             :   /* 41 */ 3, 14, 7, 1, 4, 24, 23, 22, 5, 30, 29, 28, 6, 27, 26, 25, 44, 45, 46, 47, 48, 0,
     878             :   /* 63 */ 10, 2, 14, 7, 1, 11, 32, 34, 33, 31, 49, 0,
     879             :   /* 75 */ 10, 2, 14, 7, 1, 11, 32, 34, 33, 31, 12, 40, 42, 41, 39, 49, 51, 52, 54, 57, 0,
     880             :   /* 96 */ 10, 2, 14, 7, 1, 11, 32, 34, 33, 31, 12, 40, 42, 41, 39, 13, 36, 38, 37, 35, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 0,
     881             :   /* 128 */ 17, 15, 19, 43, 60, 0,
     882             : };
     883             : 
     884             : extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
     885             :   { 65535, 65535 },
     886             :   { 0, 8 },     // bsub
     887             :   { 0, 32 },    // dsub
     888             :   { 0, 64 },    // dsub0
     889             :   { 0, 64 },    // dsub1
     890             :   { 0, 64 },    // dsub2
     891             :   { 0, 64 },    // dsub3
     892             :   { 0, 16 },    // hsub
     893             :   { 0, 64 },    // qhisub
     894             :   { 0, 64 },    // qsub
     895             :   { 0, 128 },   // qsub0
     896             :   { 0, 128 },   // qsub1
     897             :   { 0, 128 },   // qsub2
     898             :   { 0, 128 },   // qsub3
     899             :   { 0, 32 },    // ssub
     900             :   { 0, 32 },    // sub_32
     901             :   { 0, 32 },    // sube32
     902             :   { 0, 64 },    // sube64
     903             :   { 0, 32 },    // subo32
     904             :   { 0, 64 },    // subo64
     905             :   { 0, 128 },   // zsub
     906             :   { 0, 128 },   // zsub_hi
     907             :   { 0, 8 },     // dsub1_then_bsub
     908             :   { 0, 16 },    // dsub1_then_hsub
     909             :   { 0, 32 },    // dsub1_then_ssub
     910             :   { 0, 8 },     // dsub3_then_bsub
     911             :   { 0, 16 },    // dsub3_then_hsub
     912             :   { 0, 32 },    // dsub3_then_ssub
     913             :   { 0, 8 },     // dsub2_then_bsub
     914             :   { 0, 16 },    // dsub2_then_hsub
     915             :   { 0, 32 },    // dsub2_then_ssub
     916             :   { 0, 8 },     // qsub1_then_bsub
     917             :   { 0, 32 },    // qsub1_then_dsub
     918             :   { 0, 16 },    // qsub1_then_hsub
     919             :   { 0, 32 },    // qsub1_then_ssub
     920             :   { 0, 8 },     // qsub3_then_bsub
     921             :   { 0, 32 },    // qsub3_then_dsub
     922             :   { 0, 16 },    // qsub3_then_hsub
     923             :   { 0, 32 },    // qsub3_then_ssub
     924             :   { 0, 8 },     // qsub2_then_bsub
     925             :   { 0, 32 },    // qsub2_then_dsub
     926             :   { 0, 16 },    // qsub2_then_hsub
     927             :   { 0, 32 },    // qsub2_then_ssub
     928             :   { 0, 32 },    // subo64_then_sub_32
     929             :   { 65535, 128 },       // dsub0_dsub1
     930             :   { 65535, 192 },       // dsub0_dsub1_dsub2
     931             :   { 65535, 128 },       // dsub1_dsub2
     932             :   { 65535, 192 },       // dsub1_dsub2_dsub3
     933             :   { 65535, 128 },       // dsub2_dsub3
     934             :   { 65535, 64 },        // dsub_qsub1_then_dsub
     935             :   { 65535, 128 },       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
     936             :   { 65535, 96 },        // dsub_qsub1_then_dsub_qsub2_then_dsub
     937             :   { 65535, 256 },       // qsub0_qsub1
     938             :   { 65535, 384 },       // qsub0_qsub1_qsub2
     939             :   { 65535, 256 },       // qsub1_qsub2
     940             :   { 65535, 384 },       // qsub1_qsub2_qsub3
     941             :   { 65535, 256 },       // qsub2_qsub3
     942             :   { 65535, 64 },        // qsub1_then_dsub_qsub2_then_dsub
     943             :   { 65535, 96 },        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
     944             :   { 65535, 64 },        // qsub2_then_dsub_qsub3_then_dsub
     945             :   { 65535, 64 },        // sub_32_subo64_then_sub_32
     946             : };
     947             : 
     948             : extern const char AArch64RegStrings[] = {
     949             :   /* 0 */ 'B', '1', '0', 0,
     950             :   /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
     951             :   /* 17 */ 'H', '1', '0', 0,
     952             :   /* 21 */ 'P', '1', '0', 0,
     953             :   /* 25 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
     954             :   /* 38 */ 'S', '1', '0', 0,
     955             :   /* 42 */ 'W', '9', '_', 'W', '1', '0', 0,
     956             :   /* 49 */ 'X', '9', '_', 'X', '1', '0', 0,
     957             :   /* 56 */ 'Z', '1', '0', 0,
     958             :   /* 60 */ 'B', '2', '0', 0,
     959             :   /* 64 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
     960             :   /* 80 */ 'H', '2', '0', 0,
     961             :   /* 84 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
     962             :   /* 100 */ 'S', '2', '0', 0,
     963             :   /* 104 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
     964             :   /* 112 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
     965             :   /* 120 */ 'Z', '2', '0', 0,
     966             :   /* 124 */ 'B', '3', '0', 0,
     967             :   /* 128 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
     968             :   /* 144 */ 'H', '3', '0', 0,
     969             :   /* 148 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
     970             :   /* 164 */ 'S', '3', '0', 0,
     971             :   /* 168 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
     972             :   /* 176 */ 'Z', '3', '0', 0,
     973             :   /* 180 */ 'B', '0', 0,
     974             :   /* 183 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
     975             :   /* 198 */ 'H', '0', 0,
     976             :   /* 201 */ 'P', '0', 0,
     977             :   /* 204 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
     978             :   /* 219 */ 'S', '0', 0,
     979             :   /* 222 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
     980             :   /* 229 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
     981             :   /* 236 */ 'Z', '0', 0,
     982             :   /* 239 */ 'B', '1', '1', 0,
     983             :   /* 243 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
     984             :   /* 257 */ 'H', '1', '1', 0,
     985             :   /* 261 */ 'P', '1', '1', 0,
     986             :   /* 265 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
     987             :   /* 279 */ 'S', '1', '1', 0,
     988             :   /* 283 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
     989             :   /* 291 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
     990             :   /* 299 */ 'Z', '1', '1', 0,
     991             :   /* 303 */ 'B', '2', '1', 0,
     992             :   /* 307 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
     993             :   /* 323 */ 'H', '2', '1', 0,
     994             :   /* 327 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
     995             :   /* 343 */ 'S', '2', '1', 0,
     996             :   /* 347 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
     997             :   /* 355 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
     998             :   /* 363 */ 'Z', '2', '1', 0,
     999             :   /* 367 */ 'B', '3', '1', 0,
    1000             :   /* 371 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
    1001             :   /* 387 */ 'H', '3', '1', 0,
    1002             :   /* 391 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
    1003             :   /* 407 */ 'S', '3', '1', 0,
    1004             :   /* 411 */ 'Z', '3', '1', 0,
    1005             :   /* 415 */ 'B', '1', 0,
    1006             :   /* 418 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
    1007             :   /* 432 */ 'H', '1', 0,
    1008             :   /* 435 */ 'P', '1', 0,
    1009             :   /* 438 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
    1010             :   /* 452 */ 'S', '1', 0,
    1011             :   /* 455 */ 'W', '0', '_', 'W', '1', 0,
    1012             :   /* 461 */ 'X', '0', '_', 'X', '1', 0,
    1013             :   /* 467 */ 'Z', '1', 0,
    1014             :   /* 470 */ 'B', '1', '2', 0,
    1015             :   /* 474 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
    1016             :   /* 489 */ 'H', '1', '2', 0,
    1017             :   /* 493 */ 'P', '1', '2', 0,
    1018             :   /* 497 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
    1019             :   /* 512 */ 'S', '1', '2', 0,
    1020             :   /* 516 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
    1021             :   /* 524 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
    1022             :   /* 532 */ 'Z', '1', '2', 0,
    1023             :   /* 536 */ 'B', '2', '2', 0,
    1024             :   /* 540 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
    1025             :   /* 556 */ 'H', '2', '2', 0,
    1026             :   /* 560 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
    1027             :   /* 576 */ 'S', '2', '2', 0,
    1028             :   /* 580 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
    1029             :   /* 588 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
    1030             :   /* 596 */ 'Z', '2', '2', 0,
    1031             :   /* 600 */ 'B', '2', 0,
    1032             :   /* 603 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
    1033             :   /* 616 */ 'H', '2', 0,
    1034             :   /* 619 */ 'P', '2', 0,
    1035             :   /* 622 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
    1036             :   /* 635 */ 'S', '2', 0,
    1037             :   /* 638 */ 'W', '1', '_', 'W', '2', 0,
    1038             :   /* 644 */ 'X', '1', '_', 'X', '2', 0,
    1039             :   /* 650 */ 'Z', '2', 0,
    1040             :   /* 653 */ 'B', '1', '3', 0,
    1041             :   /* 657 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
    1042             :   /* 673 */ 'H', '1', '3', 0,
    1043             :   /* 677 */ 'P', '1', '3', 0,
    1044             :   /* 681 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
    1045             :   /* 697 */ 'S', '1', '3', 0,
    1046             :   /* 701 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
    1047             :   /* 709 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
    1048             :   /* 717 */ 'Z', '1', '3', 0,
    1049             :   /* 721 */ 'B', '2', '3', 0,
    1050             :   /* 725 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
    1051             :   /* 741 */ 'H', '2', '3', 0,
    1052             :   /* 745 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
    1053             :   /* 761 */ 'S', '2', '3', 0,
    1054             :   /* 765 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
    1055             :   /* 773 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
    1056             :   /* 781 */ 'Z', '2', '3', 0,
    1057             :   /* 785 */ 'B', '3', 0,
    1058             :   /* 788 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
    1059             :   /* 800 */ 'H', '3', 0,
    1060             :   /* 803 */ 'P', '3', 0,
    1061             :   /* 806 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
    1062             :   /* 818 */ 'S', '3', 0,
    1063             :   /* 821 */ 'W', '2', '_', 'W', '3', 0,
    1064             :   /* 827 */ 'X', '2', '_', 'X', '3', 0,
    1065             :   /* 833 */ 'Z', '3', 0,
    1066             :   /* 836 */ 'B', '1', '4', 0,
    1067             :   /* 840 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
    1068             :   /* 856 */ 'H', '1', '4', 0,
    1069             :   /* 860 */ 'P', '1', '4', 0,
    1070             :   /* 864 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
    1071             :   /* 880 */ 'S', '1', '4', 0,
    1072             :   /* 884 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
    1073             :   /* 892 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
    1074             :   /* 900 */ 'Z', '1', '4', 0,
    1075             :   /* 904 */ 'B', '2', '4', 0,
    1076             :   /* 908 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
    1077             :   /* 924 */ 'H', '2', '4', 0,
    1078             :   /* 928 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
    1079             :   /* 944 */ 'S', '2', '4', 0,
    1080             :   /* 948 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
    1081             :   /* 956 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
    1082             :   /* 964 */ 'Z', '2', '4', 0,
    1083             :   /* 968 */ 'B', '4', 0,
    1084             :   /* 971 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
    1085             :   /* 983 */ 'H', '4', 0,
    1086             :   /* 986 */ 'P', '4', 0,
    1087             :   /* 989 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
    1088             :   /* 1001 */ 'S', '4', 0,
    1089             :   /* 1004 */ 'W', '3', '_', 'W', '4', 0,
    1090             :   /* 1010 */ 'X', '3', '_', 'X', '4', 0,
    1091             :   /* 1016 */ 'Z', '4', 0,
    1092             :   /* 1019 */ 'B', '1', '5', 0,
    1093             :   /* 1023 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
    1094             :   /* 1039 */ 'H', '1', '5', 0,
    1095             :   /* 1043 */ 'P', '1', '5', 0,
    1096             :   /* 1047 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
    1097             :   /* 1063 */ 'S', '1', '5', 0,
    1098             :   /* 1067 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
    1099             :   /* 1075 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
    1100             :   /* 1083 */ 'Z', '1', '5', 0,
    1101             :   /* 1087 */ 'B', '2', '5', 0,
    1102             :   /* 1091 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
    1103             :   /* 1107 */ 'H', '2', '5', 0,
    1104             :   /* 1111 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
    1105             :   /* 1127 */ 'S', '2', '5', 0,
    1106             :   /* 1131 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
    1107             :   /* 1139 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
    1108             :   /* 1147 */ 'Z', '2', '5', 0,
    1109             :   /* 1151 */ 'B', '5', 0,
    1110             :   /* 1154 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
    1111             :   /* 1166 */ 'H', '5', 0,
    1112             :   /* 1169 */ 'P', '5', 0,
    1113             :   /* 1172 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
    1114             :   /* 1184 */ 'S', '5', 0,
    1115             :   /* 1187 */ 'W', '4', '_', 'W', '5', 0,
    1116             :   /* 1193 */ 'X', '4', '_', 'X', '5', 0,
    1117             :   /* 1199 */ 'Z', '5', 0,
    1118             :   /* 1202 */ 'B', '1', '6', 0,
    1119             :   /* 1206 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
    1120             :   /* 1222 */ 'H', '1', '6', 0,
    1121             :   /* 1226 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
    1122             :   /* 1242 */ 'S', '1', '6', 0,
    1123             :   /* 1246 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
    1124             :   /* 1254 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
    1125             :   /* 1262 */ 'Z', '1', '6', 0,
    1126             :   /* 1266 */ 'B', '2', '6', 0,
    1127             :   /* 1270 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
    1128             :   /* 1286 */ 'H', '2', '6', 0,
    1129             :   /* 1290 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
    1130             :   /* 1306 */ 'S', '2', '6', 0,
    1131             :   /* 1310 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
    1132             :   /* 1318 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
    1133             :   /* 1326 */ 'Z', '2', '6', 0,
    1134             :   /* 1330 */ 'B', '6', 0,
    1135             :   /* 1333 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
    1136             :   /* 1345 */ 'H', '6', 0,
    1137             :   /* 1348 */ 'P', '6', 0,
    1138             :   /* 1351 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
    1139             :   /* 1363 */ 'S', '6', 0,
    1140             :   /* 1366 */ 'W', '5', '_', 'W', '6', 0,
    1141             :   /* 1372 */ 'X', '5', '_', 'X', '6', 0,
    1142             :   /* 1378 */ 'Z', '6', 0,
    1143             :   /* 1381 */ 'B', '1', '7', 0,
    1144             :   /* 1385 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
    1145             :   /* 1401 */ 'H', '1', '7', 0,
    1146             :   /* 1405 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
    1147             :   /* 1421 */ 'S', '1', '7', 0,
    1148             :   /* 1425 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
    1149             :   /* 1433 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
    1150             :   /* 1441 */ 'Z', '1', '7', 0,
    1151             :   /* 1445 */ 'B', '2', '7', 0,
    1152             :   /* 1449 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
    1153             :   /* 1465 */ 'H', '2', '7', 0,
    1154             :   /* 1469 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
    1155             :   /* 1485 */ 'S', '2', '7', 0,
    1156             :   /* 1489 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
    1157             :   /* 1497 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
    1158             :   /* 1505 */ 'Z', '2', '7', 0,
    1159             :   /* 1509 */ 'B', '7', 0,
    1160             :   /* 1512 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
    1161             :   /* 1524 */ 'H', '7', 0,
    1162             :   /* 1527 */ 'P', '7', 0,
    1163             :   /* 1530 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
    1164             :   /* 1542 */ 'S', '7', 0,
    1165             :   /* 1545 */ 'W', '6', '_', 'W', '7', 0,
    1166             :   /* 1551 */ 'X', '6', '_', 'X', '7', 0,
    1167             :   /* 1557 */ 'Z', '7', 0,
    1168             :   /* 1560 */ 'B', '1', '8', 0,
    1169             :   /* 1564 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
    1170             :   /* 1580 */ 'H', '1', '8', 0,
    1171             :   /* 1584 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
    1172             :   /* 1600 */ 'S', '1', '8', 0,
    1173             :   /* 1604 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
    1174             :   /* 1612 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
    1175             :   /* 1620 */ 'Z', '1', '8', 0,
    1176             :   /* 1624 */ 'B', '2', '8', 0,
    1177             :   /* 1628 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
    1178             :   /* 1644 */ 'H', '2', '8', 0,
    1179             :   /* 1648 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
    1180             :   /* 1664 */ 'S', '2', '8', 0,
    1181             :   /* 1668 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
    1182             :   /* 1676 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
    1183             :   /* 1684 */ 'Z', '2', '8', 0,
    1184             :   /* 1688 */ 'B', '8', 0,
    1185             :   /* 1691 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
    1186             :   /* 1703 */ 'H', '8', 0,
    1187             :   /* 1706 */ 'P', '8', 0,
    1188             :   /* 1709 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
    1189             :   /* 1721 */ 'S', '8', 0,
    1190             :   /* 1724 */ 'W', '7', '_', 'W', '8', 0,
    1191             :   /* 1730 */ 'X', '7', '_', 'X', '8', 0,
    1192             :   /* 1736 */ 'Z', '8', 0,
    1193             :   /* 1739 */ 'B', '1', '9', 0,
    1194             :   /* 1743 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
    1195             :   /* 1759 */ 'H', '1', '9', 0,
    1196             :   /* 1763 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
    1197             :   /* 1779 */ 'S', '1', '9', 0,
    1198             :   /* 1783 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
    1199             :   /* 1791 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
    1200             :   /* 1799 */ 'Z', '1', '9', 0,
    1201             :   /* 1803 */ 'B', '2', '9', 0,
    1202             :   /* 1807 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
    1203             :   /* 1823 */ 'H', '2', '9', 0,
    1204             :   /* 1827 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
    1205             :   /* 1843 */ 'S', '2', '9', 0,
    1206             :   /* 1847 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
    1207             :   /* 1855 */ 'Z', '2', '9', 0,
    1208             :   /* 1859 */ 'B', '9', 0,
    1209             :   /* 1862 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
    1210             :   /* 1874 */ 'H', '9', 0,
    1211             :   /* 1877 */ 'P', '9', 0,
    1212             :   /* 1880 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
    1213             :   /* 1892 */ 'S', '9', 0,
    1214             :   /* 1895 */ 'W', '8', '_', 'W', '9', 0,
    1215             :   /* 1901 */ 'X', '8', '_', 'X', '9', 0,
    1216             :   /* 1907 */ 'Z', '9', 0,
    1217             :   /* 1910 */ 'Z', '1', '0', '_', 'H', 'I', 0,
    1218             :   /* 1917 */ 'Z', '2', '0', '_', 'H', 'I', 0,
    1219             :   /* 1924 */ 'Z', '3', '0', '_', 'H', 'I', 0,
    1220             :   /* 1931 */ 'Z', '0', '_', 'H', 'I', 0,
    1221             :   /* 1937 */ 'Z', '1', '1', '_', 'H', 'I', 0,
    1222             :   /* 1944 */ 'Z', '2', '1', '_', 'H', 'I', 0,
    1223             :   /* 1951 */ 'Z', '3', '1', '_', 'H', 'I', 0,
    1224             :   /* 1958 */ 'Z', '1', '_', 'H', 'I', 0,
    1225             :   /* 1964 */ 'Z', '1', '2', '_', 'H', 'I', 0,
    1226             :   /* 1971 */ 'Z', '2', '2', '_', 'H', 'I', 0,
    1227             :   /* 1978 */ 'Z', '2', '_', 'H', 'I', 0,
    1228             :   /* 1984 */ 'Z', '1', '3', '_', 'H', 'I', 0,
    1229             :   /* 1991 */ 'Z', '2', '3', '_', 'H', 'I', 0,
    1230             :   /* 1998 */ 'Z', '3', '_', 'H', 'I', 0,
    1231             :   /* 2004 */ 'Z', '1', '4', '_', 'H', 'I', 0,
    1232             :   /* 2011 */ 'Z', '2', '4', '_', 'H', 'I', 0,
    1233             :   /* 2018 */ 'Z', '4', '_', 'H', 'I', 0,
    1234             :   /* 2024 */ 'Z', '1', '5', '_', 'H', 'I', 0,
    1235             :   /* 2031 */ 'Z', '2', '5', '_', 'H', 'I', 0,
    1236             :   /* 2038 */ 'Z', '5', '_', 'H', 'I', 0,
    1237             :   /* 2044 */ 'Z', '1', '6', '_', 'H', 'I', 0,
    1238             :   /* 2051 */ 'Z', '2', '6', '_', 'H', 'I', 0,
    1239             :   /* 2058 */ 'Z', '6', '_', 'H', 'I', 0,
    1240             :   /* 2064 */ 'Z', '1', '7', '_', 'H', 'I', 0,
    1241             :   /* 2071 */ 'Z', '2', '7', '_', 'H', 'I', 0,
    1242             :   /* 2078 */ 'Z', '7', '_', 'H', 'I', 0,
    1243             :   /* 2084 */ 'Z', '1', '8', '_', 'H', 'I', 0,
    1244             :   /* 2091 */ 'Z', '2', '8', '_', 'H', 'I', 0,
    1245             :   /* 2098 */ 'Z', '8', '_', 'H', 'I', 0,
    1246             :   /* 2104 */ 'Z', '1', '9', '_', 'H', 'I', 0,
    1247             :   /* 2111 */ 'Z', '2', '9', '_', 'H', 'I', 0,
    1248             :   /* 2118 */ 'Z', '9', '_', 'H', 'I', 0,
    1249             :   /* 2124 */ 'X', '2', '8', '_', 'F', 'P', 0,
    1250             :   /* 2131 */ 'W', 'S', 'P', 0,
    1251             :   /* 2135 */ 'F', 'P', '_', 'L', 'R', 0,
    1252             :   /* 2141 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
    1253             :   /* 2149 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
    1254             :   /* 2156 */ 'N', 'Z', 'C', 'V', 0,
    1255             : };
    1256             : 
    1257             : extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
    1258             :   { 3, 0, 0, 0, 0, 0 },
    1259             :   { 2128, 362, 257, 5, 12241, 27 },
    1260             :   { 2138, 362, 89, 5, 12241, 27 },
    1261             :   { 2156, 2, 2, 4, 12241, 0 },
    1262             :   { 2132, 1, 2, 5, 4080, 27 },
    1263             :   { 2131, 2, 765, 4, 4080, 0 },
    1264             :   { 2145, 2, 41, 4, 4208, 0 },
    1265             :   { 2152, 765, 86, 5, 4208, 27 },
    1266             :   { 180, 2, 142, 4, 12209, 0 },
    1267             :   { 415, 2, 189, 4, 12209, 0 },
    1268             :   { 600, 2, 281, 4, 12209, 0 },
    1269             :   { 785, 2, 107, 4, 12209, 0 },
    1270             :   { 968, 2, 107, 4, 12209, 0 },
    1271             :   { 1151, 2, 107, 4, 12209, 0 },
    1272             :   { 1330, 2, 107, 4, 12209, 0 },
    1273             :   { 1509, 2, 107, 4, 12209, 0 },
    1274             :   { 1688, 2, 107, 4, 12209, 0 },
    1275             :   { 1859, 2, 107, 4, 12209, 0 },
    1276             :   { 0, 2, 107, 4, 12209, 0 },
    1277             :   { 239, 2, 107, 4, 12209, 0 },
    1278             :   { 470, 2, 107, 4, 12209, 0 },
    1279             :   { 653, 2, 107, 4, 12209, 0 },
    1280             :   { 836, 2, 107, 4, 12209, 0 },
    1281             :   { 1019, 2, 107, 4, 12209, 0 },
    1282             :   { 1202, 2, 107, 4, 12209, 0 },
    1283             :   { 1381, 2, 107, 4, 12209, 0 },
    1284             :   { 1560, 2, 107, 4, 12209, 0 },
    1285             :   { 1739, 2, 107, 4, 12209, 0 },
    1286             :   { 60, 2, 107, 4, 12209, 0 },
    1287             :   { 303, 2, 107, 4, 12209, 0 },
    1288             :   { 536, 2, 107, 4, 12209, 0 },
    1289             :   { 721, 2, 107, 4, 12209, 0 },
    1290             :   { 904, 2, 107, 4, 12209, 0 },
    1291             :   { 1087, 2, 107, 4, 12209, 0 },
    1292             :   { 1266, 2, 107, 4, 12209, 0 },
    1293             :   { 1445, 2, 107, 4, 12209, 0 },
    1294             :   { 1624, 2, 107, 4, 12209, 0 },
    1295             :   { 1803, 2, 107, 4, 12209, 0 },
    1296             :   { 124, 2, 107, 4, 12209, 0 },
    1297             :   { 367, 2, 107, 4, 12209, 0 },
    1298             :   { 195, 564, 145, 1, 11905, 3 },
    1299             :   { 429, 564, 192, 1, 11905, 3 },
    1300             :   { 613, 564, 284, 1, 11905, 3 },
    1301             :   { 797, 564, 110, 1, 11905, 3 },
    1302             :   { 980, 564, 110, 1, 11905, 3 },
    1303             :   { 1163, 564, 110, 1, 11905, 3 },
    1304             :   { 1342, 564, 110, 1, 11905, 3 },
    1305             :   { 1521, 564, 110, 1, 11905, 3 },
    1306             :   { 1700, 564, 110, 1, 11905, 3 },
    1307             :   { 1871, 564, 110, 1, 11905, 3 },
    1308             :   { 13, 564, 110, 1, 11905, 3 },
    1309             :   { 253, 564, 110, 1, 11905, 3 },
    1310             :   { 485, 564, 110, 1, 11905, 3 },
    1311             :   { 669, 564, 110, 1, 11905, 3 },
    1312             :   { 852, 564, 110, 1, 11905, 3 },
    1313             :   { 1035, 564, 110, 1, 11905, 3 },
    1314             :   { 1218, 564, 110, 1, 11905, 3 },
    1315             :   { 1397, 564, 110, 1, 11905, 3 },
    1316             :   { 1576, 564, 110, 1, 11905, 3 },
    1317             :   { 1755, 564, 110, 1, 11905, 3 },
    1318             :   { 76, 564, 110, 1, 11905, 3 },
    1319             :   { 319, 564, 110, 1, 11905, 3 },
    1320             :   { 552, 564, 110, 1, 11905, 3 },
    1321             :   { 737, 564, 110, 1, 11905, 3 },
    1322             :   { 920, 564, 110, 1, 11905, 3 },
    1323             :   { 1103, 564, 110, 1, 11905, 3 },
    1324             :   { 1282, 564, 110, 1, 11905, 3 },
    1325             :   { 1461, 564, 110, 1, 11905, 3 },
    1326             :   { 1640, 564, 110, 1, 11905, 3 },
    1327             :   { 1819, 564, 110, 1, 11905, 3 },
    1328             :   { 140, 564, 110, 1, 11905, 3 },
    1329             :   { 383, 564, 110, 1, 11905, 3 },
    1330             :   { 198, 566, 143, 3, 8913, 3 },
    1331             :   { 432, 566, 190, 3, 8913, 3 },
    1332             :   { 616, 566, 282, 3, 8913, 3 },
    1333             :   { 800, 566, 108, 3, 8913, 3 },
    1334             :   { 983, 566, 108, 3, 8913, 3 },
    1335             :   { 1166, 566, 108, 3, 8913, 3 },
    1336             :   { 1345, 566, 108, 3, 8913, 3 },
    1337             :   { 1524, 566, 108, 3, 8913, 3 },
    1338             :   { 1703, 566, 108, 3, 8913, 3 },
    1339             :   { 1874, 566, 108, 3, 8913, 3 },
    1340             :   { 17, 566, 108, 3, 8913, 3 },
    1341             :   { 257, 566, 108, 3, 8913, 3 },
    1342             :   { 489, 566, 108, 3, 8913, 3 },
    1343             :   { 673, 566, 108, 3, 8913, 3 },
    1344             :   { 856, 566, 108, 3, 8913, 3 },
    1345             :   { 1039, 566, 108, 3, 8913, 3 },
    1346             :   { 1222, 566, 108, 3, 8913, 3 },
    1347             :   { 1401, 566, 108, 3, 8913, 3 },
    1348             :   { 1580, 566, 108, 3, 8913, 3 },
    1349             :   { 1759, 566, 108, 3, 8913, 3 },
    1350             :   { 80, 566, 108, 3, 8913, 3 },
    1351             :   { 323, 566, 108, 3, 8913, 3 },
    1352             :   { 556, 566, 108, 3, 8913, 3 },
    1353             :   { 741, 566, 108, 3, 8913, 3 },
    1354             :   { 924, 566, 108, 3, 8913, 3 },
    1355             :   { 1107, 566, 108, 3, 8913, 3 },
    1356             :   { 1286, 566, 108, 3, 8913, 3 },
    1357             :   { 1465, 566, 108, 3, 8913, 3 },
    1358             :   { 1644, 566, 108, 3, 8913, 3 },
    1359             :   { 1823, 566, 108, 3, 8913, 3 },
    1360             :   { 144, 566, 108, 3, 8913, 3 },
    1361             :   { 387, 566, 108, 3, 8913, 3 },
    1362             :   { 201, 2, 2, 4, 8913, 0 },
    1363             :   { 435, 2, 2, 4, 8913, 0 },
    1364             :   { 619, 2, 2, 4, 8913, 0 },
    1365             :   { 803, 2, 2, 4, 8913, 0 },
    1366             :   { 986, 2, 2, 4, 8913, 0 },
    1367             :   { 1169, 2, 2, 4, 8913, 0 },
    1368             :   { 1348, 2, 2, 4, 8913, 0 },
    1369             :   { 1527, 2, 2, 4, 8913, 0 },
    1370             :   { 1706, 2, 2, 4, 8913, 0 },
    1371             :   { 1877, 2, 2, 4, 8913, 0 },
    1372             :   { 21, 2, 2, 4, 8913, 0 },
    1373             :   { 261, 2, 2, 4, 8913, 0 },
    1374             :   { 493, 2, 2, 4, 8913, 0 },
    1375             :   { 677, 2, 2, 4, 8913, 0 },
    1376             :   { 860, 2, 2, 4, 8913, 0 },
    1377             :   { 1043, 2, 2, 4, 8913, 0 },
    1378             :   { 216, 577, 166, 0, 7009, 3 },
    1379             :   { 449, 577, 213, 0, 7009, 3 },
    1380             :   { 632, 577, 305, 0, 7009, 3 },
    1381             :   { 815, 577, 131, 0, 7009, 3 },
    1382             :   { 998, 577, 131, 0, 7009, 3 },
    1383             :   { 1181, 577, 131, 0, 7009, 3 },
    1384             :   { 1360, 577, 131, 0, 7009, 3 },
    1385             :   { 1539, 577, 131, 0, 7009, 3 },
    1386             :   { 1718, 577, 131, 0, 7009, 3 },
    1387             :   { 1889, 577, 131, 0, 7009, 3 },
    1388             :   { 34, 577, 131, 0, 7009, 3 },
    1389             :   { 275, 577, 131, 0, 7009, 3 },
    1390             :   { 508, 577, 131, 0, 7009, 3 },
    1391             :   { 693, 577, 131, 0, 7009, 3 },
    1392             :   { 876, 577, 131, 0, 7009, 3 },
    1393             :   { 1059, 577, 131, 0, 7009, 3 },
    1394             :   { 1238, 577, 131, 0, 7009, 3 },
    1395             :   { 1417, 577, 131, 0, 7009, 3 },
    1396             :   { 1596, 577, 131, 0, 7009, 3 },
    1397             :   { 1775, 577, 131, 0, 7009, 3 },
    1398             :   { 96, 577, 131, 0, 7009, 3 },
    1399             :   { 339, 577, 131, 0, 7009, 3 },
    1400             :   { 572, 577, 131, 0, 7009, 3 },
    1401             :   { 757, 577, 131, 0, 7009, 3 },
    1402             :   { 940, 577, 131, 0, 7009, 3 },
    1403             :   { 1123, 577, 131, 0, 7009, 3 },
    1404             :   { 1302, 577, 131, 0, 7009, 3 },
    1405             :   { 1481, 577, 131, 0, 7009, 3 },
    1406             :   { 1660, 577, 131, 0, 7009, 3 },
    1407             :   { 1839, 577, 131, 0, 7009, 3 },
    1408             :   { 160, 577, 131, 0, 7009, 3 },
    1409             :   { 403, 577, 131, 0, 7009, 3 },
    1410             :   { 219, 565, 144, 2, 6945, 3 },
    1411             :   { 452, 565, 191, 2, 6945, 3 },
    1412             :   { 635, 565, 283, 2, 6945, 3 },
    1413             :   { 818, 565, 109, 2, 6945, 3 },
    1414             :   { 1001, 565, 109, 2, 6945, 3 },
    1415             :   { 1184, 565, 109, 2, 6945, 3 },
    1416             :   { 1363, 565, 109, 2, 6945, 3 },
    1417             :   { 1542, 565, 109, 2, 6945, 3 },
    1418             :   { 1721, 565, 109, 2, 6945, 3 },
    1419             :   { 1892, 565, 109, 2, 6945, 3 },
    1420             :   { 38, 565, 109, 2, 6945, 3 },
    1421             :   { 279, 565, 109, 2, 6945, 3 },
    1422             :   { 512, 565, 109, 2, 6945, 3 },
    1423             :   { 697, 565, 109, 2, 6945, 3 },
    1424             :   { 880, 565, 109, 2, 6945, 3 },
    1425             :   { 1063, 565, 109, 2, 6945, 3 },
    1426             :   { 1242, 565, 109, 2, 6945, 3 },
    1427             :   { 1421, 565, 109, 2, 6945, 3 },
    1428             :   { 1600, 565, 109, 2, 6945, 3 },
    1429             :   { 1779, 565, 109, 2, 6945, 3 },
    1430             :   { 100, 565, 109, 2, 6945, 3 },
    1431             :   { 343, 565, 109, 2, 6945, 3 },
    1432             :   { 576, 565, 109, 2, 6945, 3 },
    1433             :   { 761, 565, 109, 2, 6945, 3 },
    1434             :   { 944, 565, 109, 2, 6945, 3 },
    1435             :   { 1127, 565, 109, 2, 6945, 3 },
    1436             :   { 1306, 565, 109, 2, 6945, 3 },
    1437             :   { 1485, 565, 109, 2, 6945, 3 },
    1438             :   { 1664, 565, 109, 2, 6945, 3 },
    1439             :   { 1843, 565, 109, 2, 6945, 3 },
    1440             :   { 164, 565, 109, 2, 6945, 3 },
    1441             :   { 407, 565, 109, 2, 6945, 3 },
    1442             :   { 226, 2, 242, 4, 6977, 0 },
    1443             :   { 458, 2, 47, 4, 6977, 0 },
    1444             :   { 641, 2, 47, 4, 6977, 0 },
    1445             :   { 824, 2, 47, 4, 6977, 0 },
    1446             :   { 1007, 2, 47, 4, 6977, 0 },
    1447             :   { 1190, 2, 47, 4, 6977, 0 },
    1448             :   { 1369, 2, 47, 4, 6977, 0 },
    1449             :   { 1548, 2, 47, 4, 6977, 0 },
    1450             :   { 1727, 2, 47, 4, 6977, 0 },
    1451             :   { 1898, 2, 47, 4, 6977, 0 },
    1452             :   { 45, 2, 47, 4, 6977, 0 },
    1453             :   { 287, 2, 47, 4, 6977, 0 },
    1454             :   { 520, 2, 47, 4, 6977, 0 },
    1455             :   { 705, 2, 47, 4, 6977, 0 },
    1456             :   { 888, 2, 47, 4, 6977, 0 },
    1457             :   { 1071, 2, 47, 4, 6977, 0 },
    1458             :   { 1250, 2, 47, 4, 6977, 0 },
    1459             :   { 1429, 2, 47, 4, 6977, 0 },
    1460             :   { 1608, 2, 47, 4, 6977, 0 },
    1461             :   { 1787, 2, 47, 4, 6977, 0 },
    1462             :   { 108, 2, 47, 4, 6977, 0 },
    1463             :   { 351, 2, 47, 4, 6977, 0 },
    1464             :   { 584, 2, 47, 4, 6977, 0 },
    1465             :   { 769, 2, 47, 4, 6977, 0 },
    1466             :   { 952, 2, 47, 4, 6977, 0 },
    1467             :   { 1135, 2, 47, 4, 6977, 0 },
    1468             :   { 1314, 2, 47, 4, 6977, 0 },
    1469             :   { 1493, 2, 47, 4, 6977, 0 },
    1470             :   { 1672, 2, 267, 4, 6977, 0 },
    1471             :   { 1851, 2, 251, 4, 6801, 0 },
    1472             :   { 172, 2, 18, 4, 6801, 0 },
    1473             :   { 233, 761, 248, 5, 6913, 27 },
    1474             :   { 464, 761, 68, 5, 6913, 27 },
    1475             :   { 647, 761, 68, 5, 6913, 27 },
    1476             :   { 830, 761, 68, 5, 6913, 27 },
    1477             :   { 1013, 761, 68, 5, 6913, 27 },
    1478             :   { 1196, 761, 68, 5, 6913, 27 },
    1479             :   { 1375, 761, 68, 5, 6913, 27 },
    1480             :   { 1554, 761, 68, 5, 6913, 27 },
    1481             :   { 1733, 761, 68, 5, 6913, 27 },
    1482             :   { 1904, 761, 68, 5, 6913, 27 },
    1483             :   { 52, 761, 68, 5, 6913, 27 },
    1484             :   { 295, 761, 68, 5, 6913, 27 },
    1485             :   { 528, 761, 68, 5, 6913, 27 },
    1486             :   { 713, 761, 68, 5, 6913, 27 },
    1487             :   { 896, 761, 68, 5, 6913, 27 },
    1488             :   { 1079, 761, 68, 5, 6913, 27 },
    1489             :   { 1258, 761, 68, 5, 6913, 27 },
    1490             :   { 1437, 761, 68, 5, 6913, 27 },
    1491             :   { 1616, 761, 68, 5, 6913, 27 },
    1492             :   { 1795, 761, 68, 5, 6913, 27 },
    1493             :   { 116, 761, 68, 5, 6913, 27 },
    1494             :   { 359, 761, 68, 5, 6913, 27 },
    1495             :   { 592, 761, 68, 5, 6913, 27 },
    1496             :   { 777, 761, 68, 5, 6913, 27 },
    1497             :   { 960, 761, 68, 5, 6913, 27 },
    1498             :   { 1143, 761, 68, 5, 6913, 27 },
    1499             :   { 1322, 761, 68, 5, 6913, 27 },
    1500             :   { 1501, 761, 68, 5, 6913, 27 },
    1501             :   { 1680, 761, 273, 5, 6913, 27 },
    1502             :   { 236, 364, 2, 10, 5617, 35 },
    1503             :   { 467, 364, 2, 10, 5617, 35 },
    1504             :   { 650, 364, 2, 10, 5617, 35 },
    1505             :   { 833, 364, 2, 10, 5617, 35 },
    1506             :   { 1016, 364, 2, 10, 5617, 35 },
    1507             :   { 1199, 364, 2, 10, 5617, 35 },
    1508             :   { 1378, 364, 2, 10, 5617, 35 },
    1509             :   { 1557, 364, 2, 10, 5617, 35 },
    1510             :   { 1736, 364, 2, 10, 5617, 35 },
    1511             :   { 1907, 364, 2, 10, 5617, 35 },
    1512             :   { 56, 364, 2, 10, 5617, 35 },
    1513             :   { 299, 364, 2, 10, 5617, 35 },
    1514             :   { 532, 364, 2, 10, 5617, 35 },
    1515             :   { 717, 364, 2, 10, 5617, 35 },
    1516             :   { 900, 364, 2, 10, 5617, 35 },
    1517             :   { 1083, 364, 2, 10, 5617, 35 },
    1518             :   { 1262, 364, 2, 10, 5617, 35 },
    1519             :   { 1441, 364, 2, 10, 5617, 35 },
    1520             :   { 1620, 364, 2, 10, 5617, 35 },
    1521             :   { 1799, 364, 2, 10, 5617, 35 },
    1522             :   { 120, 364, 2, 10, 5617, 35 },
    1523             :   { 363, 364, 2, 10, 5617, 35 },
    1524             :   { 596, 364, 2, 10, 5617, 35 },
    1525             :   { 781, 364, 2, 10, 5617, 35 },
    1526             :   { 964, 364, 2, 10, 5617, 35 },
    1527             :   { 1147, 364, 2, 10, 5617, 35 },
    1528             :   { 1326, 364, 2, 10, 5617, 35 },
    1529             :   { 1505, 364, 2, 10, 5617, 35 },
    1530             :   { 1684, 364, 2, 10, 5617, 35 },
    1531             :   { 1855, 364, 2, 10, 5617, 35 },
    1532             :   { 176, 364, 2, 10, 5617, 35 },
    1533             :   { 411, 364, 2, 10, 5617, 35 },
    1534             :   { 1931, 2, 746, 4, 6881, 0 },
    1535             :   { 1958, 2, 746, 4, 6881, 0 },
    1536             :   { 1978, 2, 746, 4, 6881, 0 },
    1537             :   { 1998, 2, 746, 4, 6881, 0 },
    1538             :   { 2018, 2, 746, 4, 6881, 0 },
    1539             :   { 2038, 2, 746, 4, 6881, 0 },
    1540             :   { 2058, 2, 746, 4, 6881, 0 },
    1541             :   { 2078, 2, 746, 4, 6881, 0 },
    1542             :   { 2098, 2, 746, 4, 6881, 0 },
    1543             :   { 2118, 2, 746, 4, 6881, 0 },
    1544             :   { 1910, 2, 746, 4, 6881, 0 },
    1545             :   { 1937, 2, 746, 4, 6881, 0 },
    1546             :   { 1964, 2, 746, 4, 6881, 0 },
    1547             :   { 1984, 2, 746, 4, 6881, 0 },
    1548             :   { 2004, 2, 746, 4, 6881, 0 },
    1549             :   { 2024, 2, 746, 4, 6881, 0 },
    1550             :   { 2044, 2, 746, 4, 6881, 0 },
    1551             :   { 2064, 2, 746, 4, 6881, 0 },
    1552             :   { 2084, 2, 746, 4, 6881, 0 },
    1553             :   { 2104, 2, 746, 4, 6881, 0 },
    1554             :   { 1917, 2, 746, 4, 6881, 0 },
    1555             :   { 1944, 2, 746, 4, 6881, 0 },
    1556             :   { 1971, 2, 746, 4, 6881, 0 },
    1557             :   { 1991, 2, 746, 4, 6881, 0 },
    1558             :   { 2011, 2, 746, 4, 6881, 0 },
    1559             :   { 2031, 2, 746, 4, 6881, 0 },
    1560             :   { 2051, 2, 746, 4, 6881, 0 },
    1561             :   { 2071, 2, 746, 4, 6881, 0 },
    1562             :   { 2091, 2, 746, 4, 6881, 0 },
    1563             :   { 2111, 2, 746, 4, 6881, 0 },
    1564             :   { 1924, 2, 746, 4, 6881, 0 },
    1565             :   { 1951, 2, 746, 4, 6881, 0 },
    1566             :   { 426, 568, 224, 17, 1665, 40 },
    1567             :   { 610, 568, 320, 17, 1665, 40 },
    1568             :   { 794, 568, 177, 17, 1665, 40 },
    1569             :   { 977, 568, 177, 17, 1665, 40 },
    1570             :   { 1160, 568, 177, 17, 1665, 40 },
    1571             :   { 1339, 568, 177, 17, 1665, 40 },
    1572             :   { 1518, 568, 177, 17, 1665, 40 },
    1573             :   { 1697, 568, 177, 17, 1665, 40 },
    1574             :   { 1868, 568, 177, 17, 1665, 40 },
    1575             :   { 10, 568, 177, 17, 1665, 40 },
    1576             :   { 249, 568, 177, 17, 1665, 40 },
    1577             :   { 481, 568, 177, 17, 1665, 40 },
    1578             :   { 665, 568, 177, 17, 1665, 40 },
    1579             :   { 848, 568, 177, 17, 1665, 40 },
    1580             :   { 1031, 568, 177, 17, 1665, 40 },
    1581             :   { 1214, 568, 177, 17, 1665, 40 },
    1582             :   { 1393, 568, 177, 17, 1665, 40 },
    1583             :   { 1572, 568, 177, 17, 1665, 40 },
    1584             :   { 1751, 568, 177, 17, 1665, 40 },
    1585             :   { 72, 568, 177, 17, 1665, 40 },
    1586             :   { 315, 568, 177, 17, 1665, 40 },
    1587             :   { 548, 568, 177, 17, 1665, 40 },
    1588             :   { 733, 568, 177, 17, 1665, 40 },
    1589             :   { 916, 568, 177, 17, 1665, 40 },
    1590             :   { 1099, 568, 177, 17, 1665, 40 },
    1591             :   { 1278, 568, 177, 17, 1665, 40 },
    1592             :   { 1457, 568, 177, 17, 1665, 40 },
    1593             :   { 1636, 568, 177, 17, 1665, 40 },
    1594             :   { 1815, 568, 177, 17, 1665, 40 },
    1595             :   { 136, 568, 177, 17, 1665, 40 },
    1596             :   { 379, 568, 177, 17, 1665, 40 },
    1597             :   { 191, 559, 177, 17, 5312, 2 },
    1598             :   { 788, 700, 357, 41, 129, 47 },
    1599             :   { 971, 700, 357, 41, 129, 47 },
    1600             :   { 1154, 700, 357, 41, 129, 47 },
    1601             :   { 1333, 700, 357, 41, 129, 47 },
    1602             :   { 1512, 700, 357, 41, 129, 47 },
    1603             :   { 1691, 700, 357, 41, 129, 47 },
    1604             :   { 1862, 700, 357, 41, 129, 47 },
    1605             :   { 4, 700, 357, 41, 129, 47 },
    1606             :   { 243, 700, 357, 41, 129, 47 },
    1607             :   { 474, 700, 357, 41, 129, 47 },
    1608             :   { 657, 700, 357, 41, 129, 47 },
    1609             :   { 840, 700, 357, 41, 129, 47 },
    1610             :   { 1023, 700, 357, 41, 129, 47 },
    1611             :   { 1206, 700, 357, 41, 129, 47 },
    1612             :   { 1385, 700, 357, 41, 129, 47 },
    1613             :   { 1564, 700, 357, 41, 129, 47 },
    1614             :   { 1743, 700, 357, 41, 129, 47 },
    1615             :   { 64, 700, 357, 41, 129, 47 },
    1616             :   { 307, 700, 357, 41, 129, 47 },
    1617             :   { 540, 700, 357, 41, 129, 47 },
    1618             :   { 725, 700, 357, 41, 129, 47 },
    1619             :   { 908, 700, 357, 41, 129, 47 },
    1620             :   { 1091, 700, 357, 41, 129, 47 },
    1621             :   { 1270, 700, 357, 41, 129, 47 },
    1622             :   { 1449, 700, 357, 41, 129, 47 },
    1623             :   { 1628, 700, 357, 41, 129, 47 },
    1624             :   { 1807, 700, 357, 41, 129, 47 },
    1625             :   { 128, 700, 357, 41, 129, 47 },
    1626             :   { 371, 700, 357, 41, 129, 47 },
    1627             :   { 183, 722, 357, 41, 208, 52 },
    1628             :   { 418, 535, 357, 41, 512, 38 },
    1629             :   { 603, 678, 357, 41, 4416, 5 },
    1630             :   { 607, 53, 335, 26, 449, 53 },
    1631             :   { 791, 53, 236, 26, 449, 53 },
    1632             :   { 974, 53, 236, 26, 449, 53 },
    1633             :   { 1157, 53, 236, 26, 449, 53 },
    1634             :   { 1336, 53, 236, 26, 449, 53 },
    1635             :   { 1515, 53, 236, 26, 449, 53 },
    1636             :   { 1694, 53, 236, 26, 449, 53 },
    1637             :   { 1865, 53, 236, 26, 449, 53 },
    1638             :   { 7, 53, 236, 26, 449, 53 },
    1639             :   { 246, 53, 236, 26, 449, 53 },
    1640             :   { 477, 53, 236, 26, 449, 53 },
    1641             :   { 661, 53, 236, 26, 449, 53 },
    1642             :   { 844, 53, 236, 26, 449, 53 },
    1643             :   { 1027, 53, 236, 26, 449, 53 },
    1644             :   { 1210, 53, 236, 26, 449, 53 },
    1645             :   { 1389, 53, 236, 26, 449, 53 },
    1646             :   { 1568, 53, 236, 26, 449, 53 },
    1647             :   { 1747, 53, 236, 26, 449, 53 },
    1648             :   { 68, 53, 236, 26, 449, 53 },
    1649             :   { 311, 53, 236, 26, 449, 53 },
    1650             :   { 544, 53, 236, 26, 449, 53 },
    1651             :   { 729, 53, 236, 26, 449, 53 },
    1652             :   { 912, 53, 236, 26, 449, 53 },
    1653             :   { 1095, 53, 236, 26, 449, 53 },
    1654             :   { 1274, 53, 236, 26, 449, 53 },
    1655             :   { 1453, 53, 236, 26, 449, 53 },
    1656             :   { 1632, 53, 236, 26, 449, 53 },
    1657             :   { 1811, 53, 236, 26, 449, 53 },
    1658             :   { 132, 53, 236, 26, 449, 53 },
    1659             :   { 375, 53, 236, 26, 449, 53 },
    1660             :   { 187, 71, 236, 26, 592, 43 },
    1661             :   { 422, 748, 236, 26, 5056, 10 },
    1662             :   { 446, 371, 230, 63, 1569, 59 },
    1663             :   { 629, 371, 326, 63, 1569, 59 },
    1664             :   { 812, 371, 183, 63, 1569, 59 },
    1665             :   { 995, 371, 183, 63, 1569, 59 },
    1666             :   { 1178, 371, 183, 63, 1569, 59 },
    1667             :   { 1357, 371, 183, 63, 1569, 59 },
    1668             :   { 1536, 371, 183, 63, 1569, 59 },
    1669             :   { 1715, 371, 183, 63, 1569, 59 },
    1670             :   { 1886, 371, 183, 63, 1569, 59 },
    1671             :   { 31, 371, 183, 63, 1569, 59 },
    1672             :   { 271, 371, 183, 63, 1569, 59 },
    1673             :   { 504, 371, 183, 63, 1569, 59 },
    1674             :   { 689, 371, 183, 63, 1569, 59 },
    1675             :   { 872, 371, 183, 63, 1569, 59 },
    1676             :   { 1055, 371, 183, 63, 1569, 59 },
    1677             :   { 1234, 371, 183, 63, 1569, 59 },
    1678             :   { 1413, 371, 183, 63, 1569, 59 },
    1679             :   { 1592, 371, 183, 63, 1569, 59 },
    1680             :   { 1771, 371, 183, 63, 1569, 59 },
    1681             :   { 92, 371, 183, 63, 1569, 59 },
    1682             :   { 335, 371, 183, 63, 1569, 59 },
    1683             :   { 568, 371, 183, 63, 1569, 59 },
    1684             :   { 753, 371, 183, 63, 1569, 59 },
    1685             :   { 936, 371, 183, 63, 1569, 59 },
    1686             :   { 1119, 371, 183, 63, 1569, 59 },
    1687             :   { 1298, 371, 183, 63, 1569, 59 },
    1688             :   { 1477, 371, 183, 63, 1569, 59 },
    1689             :   { 1656, 371, 183, 63, 1569, 59 },
    1690             :   { 1835, 371, 183, 63, 1569, 59 },
    1691             :   { 156, 371, 183, 63, 1569, 59 },
    1692             :   { 399, 371, 183, 63, 1569, 59 },
    1693             :   { 212, 407, 183, 63, 5312, 14 },
    1694             :   { 806, 614, 2, 96, 49, 66 },
    1695             :   { 989, 614, 2, 96, 49, 66 },
    1696             :   { 1172, 614, 2, 96, 49, 66 },
    1697             :   { 1351, 614, 2, 96, 49, 66 },
    1698             :   { 1530, 614, 2, 96, 49, 66 },
    1699             :   { 1709, 614, 2, 96, 49, 66 },
    1700             :   { 1880, 614, 2, 96, 49, 66 },
    1701             :   { 25, 614, 2, 96, 49, 66 },
    1702             :   { 265, 614, 2, 96, 49, 66 },
    1703             :   { 497, 614, 2, 96, 49, 66 },
    1704             :   { 681, 614, 2, 96, 49, 66 },
    1705             :   { 864, 614, 2, 96, 49, 66 },
    1706             :   { 1047, 614, 2, 96, 49, 66 },
    1707             :   { 1226, 614, 2, 96, 49, 66 },
    1708             :   { 1405, 614, 2, 96, 49, 66 },
    1709             :   { 1584, 614, 2, 96, 49, 66 },
    1710             :   { 1763, 614, 2, 96, 49, 66 },
    1711             :   { 84, 614, 2, 96, 49, 66 },
    1712             :   { 327, 614, 2, 96, 49, 66 },
    1713             :   { 560, 614, 2, 96, 49, 66 },
    1714             :   { 745, 614, 2, 96, 49, 66 },
    1715             :   { 928, 614, 2, 96, 49, 66 },
    1716             :   { 1111, 614, 2, 96, 49, 66 },
    1717             :   { 1290, 614, 2, 96, 49, 66 },
    1718             :   { 1469, 614, 2, 96, 49, 66 },
    1719             :   { 1648, 614, 2, 96, 49, 66 },
    1720             :   { 1827, 614, 2, 96, 49, 66 },
    1721             :   { 148, 614, 2, 96, 49, 66 },
    1722             :   { 391, 614, 2, 96, 49, 66 },
    1723             :   { 204, 646, 2, 96, 208, 71 },
    1724             :   { 438, 503, 2, 96, 512, 57 },
    1725             :   { 622, 582, 2, 96, 4416, 17 },
    1726             :   { 626, 440, 338, 75, 385, 72 },
    1727             :   { 809, 440, 128, 75, 385, 72 },
    1728             :   { 992, 440, 128, 75, 385, 72 },
    1729             :   { 1175, 440, 128, 75, 385, 72 },
    1730             :   { 1354, 440, 128, 75, 385, 72 },
    1731             :   { 1533, 440, 128, 75, 385, 72 },
    1732             :   { 1712, 440, 128, 75, 385, 72 },
    1733             :   { 1883, 440, 128, 75, 385, 72 },
    1734             :   { 28, 440, 128, 75, 385, 72 },
    1735             :   { 268, 440, 128, 75, 385, 72 },
    1736             :   { 500, 440, 128, 75, 385, 72 },
    1737             :   { 685, 440, 128, 75, 385, 72 },
    1738             :   { 868, 440, 128, 75, 385, 72 },
    1739             :   { 1051, 440, 128, 75, 385, 72 },
    1740             :   { 1230, 440, 128, 75, 385, 72 },
    1741             :   { 1409, 440, 128, 75, 385, 72 },
    1742             :   { 1588, 440, 128, 75, 385, 72 },
    1743             :   { 1767, 440, 128, 75, 385, 72 },
    1744             :   { 88, 440, 128, 75, 385, 72 },
    1745             :   { 331, 440, 128, 75, 385, 72 },
    1746             :   { 564, 440, 128, 75, 385, 72 },
    1747             :   { 749, 440, 128, 75, 385, 72 },
    1748             :   { 932, 440, 128, 75, 385, 72 },
    1749             :   { 1115, 440, 128, 75, 385, 72 },
    1750             :   { 1294, 440, 128, 75, 385, 72 },
    1751             :   { 1473, 440, 128, 75, 385, 72 },
    1752             :   { 1652, 440, 128, 75, 385, 72 },
    1753             :   { 1831, 440, 128, 75, 385, 72 },
    1754             :   { 152, 440, 128, 75, 385, 72 },
    1755             :   { 395, 440, 128, 75, 385, 72 },
    1756             :   { 208, 461, 128, 75, 592, 62 },
    1757             :   { 442, 482, 128, 75, 5056, 22 },
    1758             :   { 222, 359, 343, 7, 5520, 32 },
    1759             :   { 2141, 427, 341, 7, 4064, 32 },
    1760             :   { 455, 101, 343, 7, 1521, 32 },
    1761             :   { 638, 101, 343, 7, 1521, 32 },
    1762             :   { 821, 101, 343, 7, 1521, 32 },
    1763             :   { 1004, 101, 343, 7, 1521, 32 },
    1764             :   { 1187, 101, 343, 7, 1521, 32 },
    1765             :   { 1366, 101, 343, 7, 1521, 32 },
    1766             :   { 1545, 101, 343, 7, 1521, 32 },
    1767             :   { 1724, 101, 343, 7, 1521, 32 },
    1768             :   { 1895, 101, 343, 7, 1521, 32 },
    1769             :   { 42, 101, 343, 7, 1521, 32 },
    1770             :   { 283, 101, 343, 7, 1521, 32 },
    1771             :   { 516, 101, 343, 7, 1521, 32 },
    1772             :   { 701, 101, 343, 7, 1521, 32 },
    1773             :   { 884, 101, 343, 7, 1521, 32 },
    1774             :   { 1067, 101, 343, 7, 1521, 32 },
    1775             :   { 1246, 101, 343, 7, 1521, 32 },
    1776             :   { 1425, 101, 343, 7, 1521, 32 },
    1777             :   { 1604, 101, 343, 7, 1521, 32 },
    1778             :   { 1783, 101, 343, 7, 1521, 32 },
    1779             :   { 104, 101, 343, 7, 1521, 32 },
    1780             :   { 347, 101, 343, 7, 1521, 32 },
    1781             :   { 580, 101, 343, 7, 1521, 32 },
    1782             :   { 765, 101, 343, 7, 1521, 32 },
    1783             :   { 948, 101, 343, 7, 1521, 32 },
    1784             :   { 1131, 101, 343, 7, 1521, 32 },
    1785             :   { 1310, 101, 343, 7, 1521, 32 },
    1786             :   { 1489, 101, 343, 7, 1521, 32 },
    1787             :   { 1668, 101, 343, 7, 1521, 32 },
    1788             :   { 1847, 101, 265, 7, 5664, 29 },
    1789             :   { 168, 101, 1, 7, 0, 32 },
    1790             :   { 2135, 389, 2, 128, 0, 76 },
    1791             :   { 2149, 419, 2, 128, 4161, 76 },
    1792             :   { 229, 383, 2, 128, 5571, 76 },
    1793             :   { 2124, 395, 2, 128, 5664, 26 },
    1794             :   { 461, 401, 2, 128, 1473, 76 },
    1795             :   { 644, 401, 2, 128, 1473, 76 },
    1796             :   { 827, 401, 2, 128, 1473, 76 },
    1797             :   { 1010, 401, 2, 128, 1473, 76 },
    1798             :   { 1193, 401, 2, 128, 1473, 76 },
    1799             :   { 1372, 401, 2, 128, 1473, 76 },
    1800             :   { 1551, 401, 2, 128, 1473, 76 },
    1801             :   { 1730, 401, 2, 128, 1473, 76 },
    1802             :   { 1901, 401, 2, 128, 1473, 76 },
    1803             :   { 49, 401, 2, 128, 1473, 76 },
    1804             :   { 291, 401, 2, 128, 1473, 76 },
    1805             :   { 524, 401, 2, 128, 1473, 76 },
    1806             :   { 709, 401, 2, 128, 1473, 76 },
    1807             :   { 892, 401, 2, 128, 1473, 76 },
    1808             :   { 1075, 401, 2, 128, 1473, 76 },
    1809             :   { 1254, 401, 2, 128, 1473, 76 },
    1810             :   { 1433, 401, 2, 128, 1473, 76 },
    1811             :   { 1612, 401, 2, 128, 1473, 76 },
    1812             :   { 1791, 401, 2, 128, 1473, 76 },
    1813             :   { 112, 401, 2, 128, 1473, 76 },
    1814             :   { 355, 401, 2, 128, 1473, 76 },
    1815             :   { 588, 401, 2, 128, 1473, 76 },
    1816             :   { 773, 401, 2, 128, 1473, 76 },
    1817             :   { 956, 401, 2, 128, 1473, 76 },
    1818             :   { 1139, 401, 2, 128, 1473, 76 },
    1819             :   { 1318, 401, 2, 128, 1473, 76 },
    1820             :   { 1497, 401, 2, 128, 1473, 76 },
    1821             :   { 1676, 401, 2, 128, 1473, 76 },
    1822             : };
    1823             : 
    1824             : extern const MCPhysReg AArch64RegUnitRoots[][2] = {
    1825             :   { AArch64::W29 },
    1826             :   { AArch64::W30 },
    1827             :   { AArch64::NZCV },
    1828             :   { AArch64::WSP },
    1829             :   { AArch64::WZR },
    1830             :   { AArch64::B0 },
    1831             :   { AArch64::B1 },
    1832             :   { AArch64::B2 },
    1833             :   { AArch64::B3 },
    1834             :   { AArch64::B4 },
    1835             :   { AArch64::B5 },
    1836             :   { AArch64::B6 },
    1837             :   { AArch64::B7 },
    1838             :   { AArch64::B8 },
    1839             :   { AArch64::B9 },
    1840             :   { AArch64::B10 },
    1841             :   { AArch64::B11 },
    1842             :   { AArch64::B12 },
    1843             :   { AArch64::B13 },
    1844             :   { AArch64::B14 },
    1845             :   { AArch64::B15 },
    1846             :   { AArch64::B16 },
    1847             :   { AArch64::B17 },
    1848             :   { AArch64::B18 },
    1849             :   { AArch64::B19 },
    1850             :   { AArch64::B20 },
    1851             :   { AArch64::B21 },
    1852             :   { AArch64::B22 },
    1853             :   { AArch64::B23 },
    1854             :   { AArch64::B24 },
    1855             :   { AArch64::B25 },
    1856             :   { AArch64::B26 },
    1857             :   { AArch64::B27 },
    1858             :   { AArch64::B28 },
    1859             :   { AArch64::B29 },
    1860             :   { AArch64::B30 },
    1861             :   { AArch64::B31 },
    1862             :   { AArch64::P0 },
    1863             :   { AArch64::P1 },
    1864             :   { AArch64::P2 },
    1865             :   { AArch64::P3 },
    1866             :   { AArch64::P4 },
    1867             :   { AArch64::P5 },
    1868             :   { AArch64::P6 },
    1869             :   { AArch64::P7 },
    1870             :   { AArch64::P8 },
    1871             :   { AArch64::P9 },
    1872             :   { AArch64::P10 },
    1873             :   { AArch64::P11 },
    1874             :   { AArch64::P12 },
    1875             :   { AArch64::P13 },
    1876             :   { AArch64::P14 },
    1877             :   { AArch64::P15 },
    1878             :   { AArch64::W0 },
    1879             :   { AArch64::W1 },
    1880             :   { AArch64::W2 },
    1881             :   { AArch64::W3 },
    1882             :   { AArch64::W4 },
    1883             :   { AArch64::W5 },
    1884             :   { AArch64::W6 },
    1885             :   { AArch64::W7 },
    1886             :   { AArch64::W8 },
    1887             :   { AArch64::W9 },
    1888             :   { AArch64::W10 },
    1889             :   { AArch64::W11 },
    1890             :   { AArch64::W12 },
    1891             :   { AArch64::W13 },
    1892             :   { AArch64::W14 },
    1893             :   { AArch64::W15 },
    1894             :   { AArch64::W16 },
    1895             :   { AArch64::W17 },
    1896             :   { AArch64::W18 },
    1897             :   { AArch64::W19 },
    1898             :   { AArch64::W20 },
    1899             :   { AArch64::W21 },
    1900             :   { AArch64::W22 },
    1901             :   { AArch64::W23 },
    1902             :   { AArch64::W24 },
    1903             :   { AArch64::W25 },
    1904             :   { AArch64::W26 },
    1905             :   { AArch64::W27 },
    1906             :   { AArch64::W28 },
    1907             :   { AArch64::Z0_HI },
    1908             :   { AArch64::Z1_HI },
    1909             :   { AArch64::Z2_HI },
    1910             :   { AArch64::Z3_HI },
    1911             :   { AArch64::Z4_HI },
    1912             :   { AArch64::Z5_HI },
    1913             :   { AArch64::Z6_HI },
    1914             :   { AArch64::Z7_HI },
    1915             :   { AArch64::Z8_HI },
    1916             :   { AArch64::Z9_HI },
    1917             :   { AArch64::Z10_HI },
    1918             :   { AArch64::Z11_HI },
    1919             :   { AArch64::Z12_HI },
    1920             :   { AArch64::Z13_HI },
    1921             :   { AArch64::Z14_HI },
    1922             :   { AArch64::Z15_HI },
    1923             :   { AArch64::Z16_HI },
    1924             :   { AArch64::Z17_HI },
    1925             :   { AArch64::Z18_HI },
    1926             :   { AArch64::Z19_HI },
    1927             :   { AArch64::Z20_HI },
    1928             :   { AArch64::Z21_HI },
    1929             :   { AArch64::Z22_HI },
    1930             :   { AArch64::Z23_HI },
    1931             :   { AArch64::Z24_HI },
    1932             :   { AArch64::Z25_HI },
    1933             :   { AArch64::Z26_HI },
    1934             :   { AArch64::Z27_HI },
    1935             :   { AArch64::Z28_HI },
    1936             :   { AArch64::Z29_HI },
    1937             :   { AArch64::Z30_HI },
    1938             :   { AArch64::Z31_HI },
    1939             : };
    1940             : 
    1941             : namespace {     // Register classes...
    1942             :   // FPR8 Register Class...
    1943             :   const MCPhysReg FPR8[] = {
    1944             :     AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, 
    1945             :   };
    1946             : 
    1947             :   // FPR8 Bit set.
    1948             :   const uint8_t FPR8Bits[] = {
    1949             :     0x00, 0xff, 0xff, 0xff, 0xff, 
    1950             :   };
    1951             : 
    1952             :   // FPR16 Register Class...
    1953             :   const MCPhysReg FPR16[] = {
    1954             :     AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, 
    1955             :   };
    1956             : 
    1957             :   // FPR16 Bit set.
    1958             :   const uint8_t FPR16Bits[] = {
    1959             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
    1960             :   };
    1961             : 
    1962             :   // PPR Register Class...
    1963             :   const MCPhysReg PPR[] = {
    1964             :     AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, 
    1965             :   };
    1966             : 
    1967             :   // PPR Bit set.
    1968             :   const uint8_t PPRBits[] = {
    1969             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
    1970             :   };
    1971             : 
    1972             :   // PPR_3b Register Class...
    1973             :   const MCPhysReg PPR_3b[] = {
    1974             :     AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 
    1975             :   };
    1976             : 
    1977             :   // PPR_3b Bit set.
    1978             :   const uint8_t PPR_3bBits[] = {
    1979             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
    1980             :   };
    1981             : 
    1982             :   // GPR32all Register Class...
    1983             :   const MCPhysReg GPR32all[] = {
    1984             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, 
    1985             :   };
    1986             : 
    1987             :   // GPR32all Bit set.
    1988             :   const uint8_t GPR32allBits[] = {
    1989             :     0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
    1990             :   };
    1991             : 
    1992             :   // FPR32 Register Class...
    1993             :   const MCPhysReg FPR32[] = {
    1994             :     AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, 
    1995             :   };
    1996             : 
    1997             :   // FPR32 Bit set.
    1998             :   const uint8_t FPR32Bits[] = {
    1999             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
    2000             :   };
    2001             : 
    2002             :   // GPR32 Register Class...
    2003             :   const MCPhysReg GPR32[] = {
    2004             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, 
    2005             :   };
    2006             : 
    2007             :   // GPR32 Bit set.
    2008             :   const uint8_t GPR32Bits[] = {
    2009             :     0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
    2010             :   };
    2011             : 
    2012             :   // GPR32sp Register Class...
    2013             :   const MCPhysReg GPR32sp[] = {
    2014             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, 
    2015             :   };
    2016             : 
    2017             :   // GPR32sp Bit set.
    2018             :   const uint8_t GPR32spBits[] = {
    2019             :     0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
    2020             :   };
    2021             : 
    2022             :   // GPR32common Register Class...
    2023             :   const MCPhysReg GPR32common[] = {
    2024             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, 
    2025             :   };
    2026             : 
    2027             :   // GPR32common Bit set.
    2028             :   const uint8_t GPR32commonBits[] = {
    2029             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
    2030             :   };
    2031             : 
    2032             :   // CCR Register Class...
    2033             :   const MCPhysReg CCR[] = {
    2034             :     AArch64::NZCV, 
    2035             :   };
    2036             : 
    2037             :   // CCR Bit set.
    2038             :   const uint8_t CCRBits[] = {
    2039             :     0x08, 
    2040             :   };
    2041             : 
    2042             :   // GPR32sponly Register Class...
    2043             :   const MCPhysReg GPR32sponly[] = {
    2044             :     AArch64::WSP, 
    2045             :   };
    2046             : 
    2047             :   // GPR32sponly Bit set.
    2048             :   const uint8_t GPR32sponlyBits[] = {
    2049             :     0x20, 
    2050             :   };
    2051             : 
    2052             :   // WSeqPairsClass Register Class...
    2053             :   const MCPhysReg WSeqPairsClass[] = {
    2054             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, AArch64::WZR_W0, 
    2055             :   };
    2056             : 
    2057             :   // WSeqPairsClass Bit set.
    2058             :   const uint8_t WSeqPairsClassBits[] = {
    2059             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2060             :   };
    2061             : 
    2062             :   // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
    2063             :   const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
    2064             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, 
    2065             :   };
    2066             : 
    2067             :   // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
    2068             :   const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
    2069             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, 
    2070             :   };
    2071             : 
    2072             :   // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
    2073             :   const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
    2074             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::WZR_W0, 
    2075             :   };
    2076             : 
    2077             :   // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
    2078             :   const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    2079             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff, 0xff, 0xff, 0x0f, 
    2080             :   };
    2081             : 
    2082             :   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
    2083             :   const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
    2084             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, 
    2085             :   };
    2086             : 
    2087             :   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
    2088             :   const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    2089             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, 
    2090             :   };
    2091             : 
    2092             :   // GPR64all Register Class...
    2093             :   const MCPhysReg GPR64all[] = {
    2094             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, 
    2095             :   };
    2096             : 
    2097             :   // GPR64all Bit set.
    2098             :   const uint8_t GPR64allBits[] = {
    2099             :     0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
    2100             :   };
    2101             : 
    2102             :   // FPR64 Register Class...
    2103             :   const MCPhysReg FPR64[] = {
    2104             :     AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 
    2105             :   };
    2106             : 
    2107             :   // FPR64 Bit set.
    2108             :   const uint8_t FPR64Bits[] = {
    2109             :     0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
    2110             :   };
    2111             : 
    2112             :   // GPR64 Register Class...
    2113             :   const MCPhysReg GPR64[] = {
    2114             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, 
    2115             :   };
    2116             : 
    2117             :   // GPR64 Bit set.
    2118             :   const uint8_t GPR64Bits[] = {
    2119             :     0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
    2120             :   };
    2121             : 
    2122             :   // GPR64sp Register Class...
    2123             :   const MCPhysReg GPR64sp[] = {
    2124             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, 
    2125             :   };
    2126             : 
    2127             :   // GPR64sp Bit set.
    2128             :   const uint8_t GPR64spBits[] = {
    2129             :     0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
    2130             :   };
    2131             : 
    2132             :   // GPR64common Register Class...
    2133             :   const MCPhysReg GPR64common[] = {
    2134             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, 
    2135             :   };
    2136             : 
    2137             :   // GPR64common Bit set.
    2138             :   const uint8_t GPR64commonBits[] = {
    2139             :     0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
    2140             :   };
    2141             : 
    2142             :   // tcGPR64 Register Class...
    2143             :   const MCPhysReg tcGPR64[] = {
    2144             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, 
    2145             :   };
    2146             : 
    2147             :   // tcGPR64 Bit set.
    2148             :   const uint8_t tcGPR64Bits[] = {
    2149             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03, 
    2150             :   };
    2151             : 
    2152             :   // GPR64sponly Register Class...
    2153             :   const MCPhysReg GPR64sponly[] = {
    2154             :     AArch64::SP, 
    2155             :   };
    2156             : 
    2157             :   // GPR64sponly Bit set.
    2158             :   const uint8_t GPR64sponlyBits[] = {
    2159             :     0x10, 
    2160             :   };
    2161             : 
    2162             :   // DD Register Class...
    2163             :   const MCPhysReg DD[] = {
    2164             :     AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, 
    2165             :   };
    2166             : 
    2167             :   // DD Bit set.
    2168             :   const uint8_t DDBits[] = {
    2169             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2170             :   };
    2171             : 
    2172             :   // XSeqPairsClass Register Class...
    2173             :   const MCPhysReg XSeqPairsClass[] = {
    2174             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, AArch64::XZR_X0, 
    2175             :   };
    2176             : 
    2177             :   // XSeqPairsClass Bit set.
    2178             :   const uint8_t XSeqPairsClassBits[] = {
    2179             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2180             :   };
    2181             : 
    2182             :   // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
    2183             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
    2184             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, 
    2185             :   };
    2186             : 
    2187             :   // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
    2188             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
    2189             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0xff, 0xff, 0xff, 0x0f, 
    2190             :   };
    2191             : 
    2192             :   // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
    2193             :   const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
    2194             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::XZR_X0, 
    2195             :   };
    2196             : 
    2197             :   // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
    2198             :   const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    2199             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff, 0xff, 0xff, 0x0f, 
    2200             :   };
    2201             : 
    2202             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
    2203             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
    2204             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, 
    2205             :   };
    2206             : 
    2207             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
    2208             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    2209             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0xff, 0xff, 0xff, 0x0f, 
    2210             :   };
    2211             : 
    2212             :   // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
    2213             :   const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
    2214             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, 
    2215             :   };
    2216             : 
    2217             :   // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
    2218             :   const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
    2219             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, 
    2220             :   };
    2221             : 
    2222             :   // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
    2223             :   const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    2224             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::XZR_X0, 
    2225             :   };
    2226             : 
    2227             :   // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
    2228             :   const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    2229             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xff, 0xff, 0x03, 
    2230             :   };
    2231             : 
    2232             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
    2233             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    2234             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, 
    2235             :   };
    2236             : 
    2237             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
    2238             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    2239             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x03, 
    2240             :   };
    2241             : 
    2242             :   // FPR128 Register Class...
    2243             :   const MCPhysReg FPR128[] = {
    2244             :     AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 
    2245             :   };
    2246             : 
    2247             :   // FPR128 Bit set.
    2248             :   const uint8_t FPR128Bits[] = {
    2249             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
    2250             :   };
    2251             : 
    2252             :   // ZPR Register Class...
    2253             :   const MCPhysReg ZPR[] = {
    2254             :     AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31, 
    2255             :   };
    2256             : 
    2257             :   // ZPR Bit set.
    2258             :   const uint8_t ZPRBits[] = {
    2259             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2260             :   };
    2261             : 
    2262             :   // FPR128_lo Register Class...
    2263             :   const MCPhysReg FPR128_lo[] = {
    2264             :     AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, 
    2265             :   };
    2266             : 
    2267             :   // FPR128_lo Bit set.
    2268             :   const uint8_t FPR128_loBits[] = {
    2269             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
    2270             :   };
    2271             : 
    2272             :   // ZPR_with_zsub_in_FPR128_lo Register Class...
    2273             :   const MCPhysReg ZPR_with_zsub_in_FPR128_lo[] = {
    2274             :     AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 
    2275             :   };
    2276             : 
    2277             :   // ZPR_with_zsub_in_FPR128_lo Bit set.
    2278             :   const uint8_t ZPR_with_zsub_in_FPR128_loBits[] = {
    2279             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
    2280             :   };
    2281             : 
    2282             :   // DDD Register Class...
    2283             :   const MCPhysReg DDD[] = {
    2284             :     AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, 
    2285             :   };
    2286             : 
    2287             :   // DDD Bit set.
    2288             :   const uint8_t DDDBits[] = {
    2289             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2290             :   };
    2291             : 
    2292             :   // DDDD Register Class...
    2293             :   const MCPhysReg DDDD[] = {
    2294             :     AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, 
    2295             :   };
    2296             : 
    2297             :   // DDDD Bit set.
    2298             :   const uint8_t DDDDBits[] = {
    2299             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2300             :   };
    2301             : 
    2302             :   // QQ Register Class...
    2303             :   const MCPhysReg QQ[] = {
    2304             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, 
    2305             :   };
    2306             : 
    2307             :   // QQ Bit set.
    2308             :   const uint8_t QQBits[] = {
    2309             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2310             :   };
    2311             : 
    2312             :   // QQ_with_qsub0_in_FPR128_lo Register Class...
    2313             :   const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
    2314             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 
    2315             :   };
    2316             : 
    2317             :   // QQ_with_qsub0_in_FPR128_lo Bit set.
    2318             :   const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
    2319             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
    2320             :   };
    2321             : 
    2322             :   // QQ_with_qsub1_in_FPR128_lo Register Class...
    2323             :   const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
    2324             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, 
    2325             :   };
    2326             : 
    2327             :   // QQ_with_qsub1_in_FPR128_lo Bit set.
    2328             :   const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
    2329             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
    2330             :   };
    2331             : 
    2332             :   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
    2333             :   const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
    2334             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, 
    2335             :   };
    2336             : 
    2337             :   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
    2338             :   const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
    2339             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
    2340             :   };
    2341             : 
    2342             :   // QQQ Register Class...
    2343             :   const MCPhysReg QQQ[] = {
    2344             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
    2345             :   };
    2346             : 
    2347             :   // QQQ Bit set.
    2348             :   const uint8_t QQQBits[] = {
    2349             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2350             :   };
    2351             : 
    2352             :   // QQQ_with_qsub0_in_FPR128_lo Register Class...
    2353             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
    2354             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, 
    2355             :   };
    2356             : 
    2357             :   // QQQ_with_qsub0_in_FPR128_lo Bit set.
    2358             :   const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
    2359             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
    2360             :   };
    2361             : 
    2362             :   // QQQ_with_qsub1_in_FPR128_lo Register Class...
    2363             :   const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
    2364             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, 
    2365             :   };
    2366             : 
    2367             :   // QQQ_with_qsub1_in_FPR128_lo Bit set.
    2368             :   const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
    2369             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
    2370             :   };
    2371             : 
    2372             :   // QQQ_with_qsub2_in_FPR128_lo Register Class...
    2373             :   const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
    2374             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
    2375             :   };
    2376             : 
    2377             :   // QQQ_with_qsub2_in_FPR128_lo Bit set.
    2378             :   const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
    2379             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, 
    2380             :   };
    2381             : 
    2382             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
    2383             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
    2384             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 
    2385             :   };
    2386             : 
    2387             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
    2388             :   const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
    2389             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
    2390             :   };
    2391             : 
    2392             :   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
    2393             :   const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    2394             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, 
    2395             :   };
    2396             : 
    2397             :   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
    2398             :   const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    2399             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, 
    2400             :   };
    2401             : 
    2402             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
    2403             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    2404             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, 
    2405             :   };
    2406             : 
    2407             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
    2408             :   const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    2409             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 
    2410             :   };
    2411             : 
    2412             :   // QQQQ Register Class...
    2413             :   const MCPhysReg QQQQ[] = {
    2414             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2415             :   };
    2416             : 
    2417             :   // QQQQ Bit set.
    2418             :   const uint8_t QQQQBits[] = {
    2419             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
    2420             :   };
    2421             : 
    2422             :   // QQQQ_with_qsub0_in_FPR128_lo Register Class...
    2423             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
    2424             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, 
    2425             :   };
    2426             : 
    2427             :   // QQQQ_with_qsub0_in_FPR128_lo Bit set.
    2428             :   const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
    2429             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
    2430             :   };
    2431             : 
    2432             :   // QQQQ_with_qsub1_in_FPR128_lo Register Class...
    2433             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
    2434             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, 
    2435             :   };
    2436             : 
    2437             :   // QQQQ_with_qsub1_in_FPR128_lo Bit set.
    2438             :   const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
    2439             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
    2440             :   };
    2441             : 
    2442             :   // QQQQ_with_qsub2_in_FPR128_lo Register Class...
    2443             :   const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
    2444             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2445             :   };
    2446             : 
    2447             :   // QQQQ_with_qsub2_in_FPR128_lo Bit set.
    2448             :   const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
    2449             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, 
    2450             :   };
    2451             : 
    2452             :   // QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2453             :   const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
    2454             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2455             :   };
    2456             : 
    2457             :   // QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2458             :   const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2459             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e, 
    2460             :   };
    2461             : 
    2462             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
    2463             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
    2464             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 
    2465             :   };
    2466             : 
    2467             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
    2468             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
    2469             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
    2470             :   };
    2471             : 
    2472             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
    2473             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    2474             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, 
    2475             :   };
    2476             : 
    2477             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
    2478             :   const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    2479             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, 
    2480             :   };
    2481             : 
    2482             :   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2483             :   const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    2484             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2485             :   };
    2486             : 
    2487             :   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2488             :   const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2489             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c, 
    2490             :   };
    2491             : 
    2492             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
    2493             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    2494             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, 
    2495             :   };
    2496             : 
    2497             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
    2498             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    2499             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 
    2500             :   };
    2501             : 
    2502             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2503             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    2504             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, 
    2505             :   };
    2506             : 
    2507             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2508             :   const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2509             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08, 
    2510             :   };
    2511             : 
    2512             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2513             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    2514             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, 
    2515             :   };
    2516             : 
    2517             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2518             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2519             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
    2520             :   };
    2521             : 
    2522             : } // end anonymous namespace
    2523             : 
    2524             : extern const char AArch64RegClassStrings[] = {
    2525             :   /* 0 */ 'F', 'P', 'R', '3', '2', 0,
    2526             :   /* 6 */ 'G', 'P', 'R', '3', '2', 0,
    2527             :   /* 12 */ 'F', 'P', 'R', '6', '4', 0,
    2528             :   /* 18 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
    2529             :   /* 56 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
    2530             :   /* 140 */ 'F', 'P', 'R', '1', '6', 0,
    2531             :   /* 146 */ 'F', 'P', 'R', '1', '2', '8', 0,
    2532             :   /* 153 */ 'F', 'P', 'R', '8', 0,
    2533             :   /* 158 */ 'D', 'D', 'D', 'D', 0,
    2534             :   /* 163 */ 'Q', 'Q', 'Q', 'Q', 0,
    2535             :   /* 168 */ 'C', 'C', 'R', 0,
    2536             :   /* 172 */ 'P', 'P', 'R', 0,
    2537             :   /* 176 */ 'Z', 'P', 'R', 0,
    2538             :   /* 180 */ 'P', 'P', 'R', '_', '3', 'b', 0,
    2539             :   /* 187 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
    2540             :   /* 196 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
    2541             :   /* 205 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    2542             :   /* 247 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    2543             :   /* 289 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    2544             :   /* 377 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    2545             :   /* 465 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2546             :   /* 494 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2547             :   /* 556 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2548             :   /* 616 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2549             :   /* 674 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2550             :   /* 736 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2551             :   /* 798 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2552             :   /* 858 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2553             :   /* 918 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2554             :   /* 980 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2555             :   /* 1042 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2556             :   /* 1104 */ 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    2557             :   /* 1131 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
    2558             :   /* 1139 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
    2559             :   /* 1147 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
    2560             :   /* 1162 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
    2561             :   /* 1177 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
    2562             :   /* 1189 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
    2563             : };
    2564             : 
    2565             : extern const MCRegisterClass AArch64MCRegisterClasses[] = {
    2566             :   { FPR8, FPR8Bits, 153, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, 1, true },
    2567             :   { FPR16, FPR16Bits, 140, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 2, 1, true },
    2568             :   { PPR, PPRBits, 172, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 2, 1, true },
    2569             :   { PPR_3b, PPR_3bBits, 180, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 2, 1, true },
    2570             :   { GPR32all, GPR32allBits, 187, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 4, 1, true },
    2571             :   { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 4, 1, true },
    2572             :   { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 4, 1, true },
    2573             :   { GPR32sp, GPR32spBits, 1131, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 4, 1, true },
    2574             :   { GPR32common, GPR32commonBits, 235, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 4, 1, true },
    2575             :   { CCR, CCRBits, 168, 1, sizeof(CCRBits), AArch64::CCRRegClassID, 4, -1, false },
    2576             :   { GPR32sponly, GPR32sponlyBits, 1177, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 4, 1, true },
    2577             :   { WSeqPairsClass, WSeqPairsClassBits, 1147, 32, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 8, 1, true },
    2578             :   { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, 247, 31, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClassID, 8, 1, true },
    2579             :   { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 335, 31, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 1, true },
    2580             :   { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, 289, 30, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 1, true },
    2581             :   { GPR64all, GPR64allBits, 196, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 8, 1, true },
    2582             :   { FPR64, FPR64Bits, 12, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 8, 1, true },
    2583             :   { GPR64, GPR64Bits, 50, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 8, 1, true },
    2584             :   { GPR64sp, GPR64spBits, 1139, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 8, 1, true },
    2585             :   { GPR64common, GPR64commonBits, 453, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 8, 1, true },
    2586             :   { tcGPR64, tcGPR64Bits, 48, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 8, 1, true },
    2587             :   { GPR64sponly, GPR64sponlyBits, 1189, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 8, 1, true },
    2588             :   { DD, DDBits, 160, 32, sizeof(DDBits), AArch64::DDRegClassID, 16, 1, true },
    2589             :   { XSeqPairsClass, XSeqPairsClassBits, 1162, 32, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 16, 1, true },
    2590             :   { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, 205, 31, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID, 16, 1, true },
    2591             :   { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 423, 31, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 1, true },
    2592             :   { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, 377, 30, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 1, true },
    2593             :   { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 18, 19, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 16, 1, true },
    2594             :   { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 102, 19, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 1, true },
    2595             :   { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, 56, 18, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 1, true },
    2596             :   { FPR128, FPR128Bits, 146, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 16, 1, true },
    2597             :   { ZPR, ZPRBits, 176, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 16, 1, true },
    2598             :   { FPR128_lo, FPR128_loBits, 484, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 16, 1, true },
    2599             :   { ZPR_with_zsub_in_FPR128_lo, ZPR_with_zsub_in_FPR128_loBits, 1104, 16, sizeof(ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR_with_zsub_in_FPR128_loRegClassID, 16, 1, true },
    2600             :   { DDD, DDDBits, 159, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 24, 1, true },
    2601             :   { DDDD, DDDDBits, 158, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 32, 1, true },
    2602             :   { QQ, QQBits, 165, 32, sizeof(QQBits), AArch64::QQRegClassID, 32, 1, true },
    2603             :   { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 467, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 32, 1, true },
    2604             :   { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 529, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 32, 1, true },
    2605             :   { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 616, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 1, true },
    2606             :   { QQQ, QQQBits, 164, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 48, 1, true },
    2607             :   { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 466, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 1, true },
    2608             :   { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 528, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 1, true },
    2609             :   { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 708, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    2610             :   { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 556, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 1, true },
    2611             :   { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 858, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    2612             :   { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 798, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    2613             :   { QQQQ, QQQQBits, 163, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 64, 1, true },
    2614             :   { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 465, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 1, true },
    2615             :   { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 527, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 1, true },
    2616             :   { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 707, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    2617             :   { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 951, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    2618             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 494, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 1, true },
    2619             :   { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 736, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    2620             :   { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 1042, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    2621             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 674, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    2622             :   { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 980, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    2623             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 918, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    2624             : };
    2625             : 
    2626             : // AArch64 Dwarf<->LLVM register mappings.
    2627             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
    2628             :   { 0U, AArch64::W0 },
    2629             :   { 1U, AArch64::W1 },
    2630             :   { 2U, AArch64::W2 },
    2631             :   { 3U, AArch64::W3 },
    2632             :   { 4U, AArch64::W4 },
    2633             :   { 5U, AArch64::W5 },
    2634             :   { 6U, AArch64::W6 },
    2635             :   { 7U, AArch64::W7 },
    2636             :   { 8U, AArch64::W8 },
    2637             :   { 9U, AArch64::W9 },
    2638             :   { 10U, AArch64::W10 },
    2639             :   { 11U, AArch64::W11 },
    2640             :   { 12U, AArch64::W12 },
    2641             :   { 13U, AArch64::W13 },
    2642             :   { 14U, AArch64::W14 },
    2643             :   { 15U, AArch64::W15 },
    2644             :   { 16U, AArch64::W16 },
    2645             :   { 17U, AArch64::W17 },
    2646             :   { 18U, AArch64::W18 },
    2647             :   { 19U, AArch64::W19 },
    2648             :   { 20U, AArch64::W20 },
    2649             :   { 21U, AArch64::W21 },
    2650             :   { 22U, AArch64::W22 },
    2651             :   { 23U, AArch64::W23 },
    2652             :   { 24U, AArch64::W24 },
    2653             :   { 25U, AArch64::W25 },
    2654             :   { 26U, AArch64::W26 },
    2655             :   { 27U, AArch64::W27 },
    2656             :   { 28U, AArch64::W28 },
    2657             :   { 29U, AArch64::W29 },
    2658             :   { 30U, AArch64::W30 },
    2659             :   { 31U, AArch64::WSP },
    2660             :   { 48U, AArch64::P0 },
    2661             :   { 49U, AArch64::P1 },
    2662             :   { 50U, AArch64::P2 },
    2663             :   { 51U, AArch64::P3 },
    2664             :   { 52U, AArch64::P4 },
    2665             :   { 53U, AArch64::P5 },
    2666             :   { 54U, AArch64::P6 },
    2667             :   { 55U, AArch64::P7 },
    2668             :   { 56U, AArch64::P8 },
    2669             :   { 57U, AArch64::P9 },
    2670             :   { 58U, AArch64::P10 },
    2671             :   { 59U, AArch64::P11 },
    2672             :   { 60U, AArch64::P12 },
    2673             :   { 61U, AArch64::P13 },
    2674             :   { 62U, AArch64::P14 },
    2675             :   { 63U, AArch64::P15 },
    2676             :   { 64U, AArch64::B0 },
    2677             :   { 65U, AArch64::B1 },
    2678             :   { 66U, AArch64::B2 },
    2679             :   { 67U, AArch64::B3 },
    2680             :   { 68U, AArch64::B4 },
    2681             :   { 69U, AArch64::B5 },
    2682             :   { 70U, AArch64::B6 },
    2683             :   { 71U, AArch64::B7 },
    2684             :   { 72U, AArch64::B8 },
    2685             :   { 73U, AArch64::B9 },
    2686             :   { 74U, AArch64::B10 },
    2687             :   { 75U, AArch64::B11 },
    2688             :   { 76U, AArch64::B12 },
    2689             :   { 77U, AArch64::B13 },
    2690             :   { 78U, AArch64::B14 },
    2691             :   { 79U, AArch64::B15 },
    2692             :   { 80U, AArch64::B16 },
    2693             :   { 81U, AArch64::B17 },
    2694             :   { 82U, AArch64::B18 },
    2695             :   { 83U, AArch64::B19 },
    2696             :   { 84U, AArch64::B20 },
    2697             :   { 85U, AArch64::B21 },
    2698             :   { 86U, AArch64::B22 },
    2699             :   { 87U, AArch64::B23 },
    2700             :   { 88U, AArch64::B24 },
    2701             :   { 89U, AArch64::B25 },
    2702             :   { 90U, AArch64::B26 },
    2703             :   { 91U, AArch64::B27 },
    2704             :   { 92U, AArch64::B28 },
    2705             :   { 93U, AArch64::B29 },
    2706             :   { 94U, AArch64::B30 },
    2707             :   { 95U, AArch64::B31 },
    2708             :   { 96U, AArch64::Z0 },
    2709             :   { 97U, AArch64::Z1 },
    2710             :   { 98U, AArch64::Z2 },
    2711             :   { 99U, AArch64::Z3 },
    2712             :   { 100U, AArch64::Z4 },
    2713             :   { 101U, AArch64::Z5 },
    2714             :   { 102U, AArch64::Z6 },
    2715             :   { 103U, AArch64::Z7 },
    2716             :   { 104U, AArch64::Z8 },
    2717             :   { 105U, AArch64::Z9 },
    2718             :   { 106U, AArch64::Z10 },
    2719             :   { 107U, AArch64::Z11 },
    2720             :   { 108U, AArch64::Z12 },
    2721             :   { 109U, AArch64::Z13 },
    2722             :   { 110U, AArch64::Z14 },
    2723             :   { 111U, AArch64::Z15 },
    2724             :   { 112U, AArch64::Z16 },
    2725             :   { 113U, AArch64::Z17 },
    2726             :   { 114U, AArch64::Z18 },
    2727             :   { 115U, AArch64::Z19 },
    2728             :   { 116U, AArch64::Z20 },
    2729             :   { 117U, AArch64::Z21 },
    2730             :   { 118U, AArch64::Z22 },
    2731             :   { 119U, AArch64::Z23 },
    2732             :   { 120U, AArch64::Z24 },
    2733             :   { 121U, AArch64::Z25 },
    2734             :   { 122U, AArch64::Z26 },
    2735             :   { 123U, AArch64::Z27 },
    2736             :   { 124U, AArch64::Z28 },
    2737             :   { 125U, AArch64::Z29 },
    2738             :   { 126U, AArch64::Z30 },
    2739             :   { 127U, AArch64::Z31 },
    2740             : };
    2741             : extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
    2742             : 
    2743             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
    2744             :   { 0U, AArch64::W0 },
    2745             :   { 1U, AArch64::W1 },
    2746             :   { 2U, AArch64::W2 },
    2747             :   { 3U, AArch64::W3 },
    2748             :   { 4U, AArch64::W4 },
    2749             :   { 5U, AArch64::W5 },
    2750             :   { 6U, AArch64::W6 },
    2751             :   { 7U, AArch64::W7 },
    2752             :   { 8U, AArch64::W8 },
    2753             :   { 9U, AArch64::W9 },
    2754             :   { 10U, AArch64::W10 },
    2755             :   { 11U, AArch64::W11 },
    2756             :   { 12U, AArch64::W12 },
    2757             :   { 13U, AArch64::W13 },
    2758             :   { 14U, AArch64::W14 },
    2759             :   { 15U, AArch64::W15 },
    2760             :   { 16U, AArch64::W16 },
    2761             :   { 17U, AArch64::W17 },
    2762             :   { 18U, AArch64::W18 },
    2763             :   { 19U, AArch64::W19 },
    2764             :   { 20U, AArch64::W20 },
    2765             :   { 21U, AArch64::W21 },
    2766             :   { 22U, AArch64::W22 },
    2767             :   { 23U, AArch64::W23 },
    2768             :   { 24U, AArch64::W24 },
    2769             :   { 25U, AArch64::W25 },
    2770             :   { 26U, AArch64::W26 },
    2771             :   { 27U, AArch64::W27 },
    2772             :   { 28U, AArch64::W28 },
    2773             :   { 29U, AArch64::W29 },
    2774             :   { 30U, AArch64::W30 },
    2775             :   { 31U, AArch64::WSP },
    2776             :   { 48U, AArch64::P0 },
    2777             :   { 49U, AArch64::P1 },
    2778             :   { 50U, AArch64::P2 },
    2779             :   { 51U, AArch64::P3 },
    2780             :   { 52U, AArch64::P4 },
    2781             :   { 53U, AArch64::P5 },
    2782             :   { 54U, AArch64::P6 },
    2783             :   { 55U, AArch64::P7 },
    2784             :   { 56U, AArch64::P8 },
    2785             :   { 57U, AArch64::P9 },
    2786             :   { 58U, AArch64::P10 },
    2787             :   { 59U, AArch64::P11 },
    2788             :   { 60U, AArch64::P12 },
    2789             :   { 61U, AArch64::P13 },
    2790             :   { 62U, AArch64::P14 },
    2791             :   { 63U, AArch64::P15 },
    2792             :   { 64U, AArch64::B0 },
    2793             :   { 65U, AArch64::B1 },
    2794             :   { 66U, AArch64::B2 },
    2795             :   { 67U, AArch64::B3 },
    2796             :   { 68U, AArch64::B4 },
    2797             :   { 69U, AArch64::B5 },
    2798             :   { 70U, AArch64::B6 },
    2799             :   { 71U, AArch64::B7 },
    2800             :   { 72U, AArch64::B8 },
    2801             :   { 73U, AArch64::B9 },
    2802             :   { 74U, AArch64::B10 },
    2803             :   { 75U, AArch64::B11 },
    2804             :   { 76U, AArch64::B12 },
    2805             :   { 77U, AArch64::B13 },
    2806             :   { 78U, AArch64::B14 },
    2807             :   { 79U, AArch64::B15 },
    2808             :   { 80U, AArch64::B16 },
    2809             :   { 81U, AArch64::B17 },
    2810             :   { 82U, AArch64::B18 },
    2811             :   { 83U, AArch64::B19 },
    2812             :   { 84U, AArch64::B20 },
    2813             :   { 85U, AArch64::B21 },
    2814             :   { 86U, AArch64::B22 },
    2815             :   { 87U, AArch64::B23 },
    2816             :   { 88U, AArch64::B24 },
    2817             :   { 89U, AArch64::B25 },
    2818             :   { 90U, AArch64::B26 },
    2819             :   { 91U, AArch64::B27 },
    2820             :   { 92U, AArch64::B28 },
    2821             :   { 93U, AArch64::B29 },
    2822             :   { 94U, AArch64::B30 },
    2823             :   { 95U, AArch64::B31 },
    2824             :   { 96U, AArch64::Z0 },
    2825             :   { 97U, AArch64::Z1 },
    2826             :   { 98U, AArch64::Z2 },
    2827             :   { 99U, AArch64::Z3 },
    2828             :   { 100U, AArch64::Z4 },
    2829             :   { 101U, AArch64::Z5 },
    2830             :   { 102U, AArch64::Z6 },
    2831             :   { 103U, AArch64::Z7 },
    2832             :   { 104U, AArch64::Z8 },
    2833             :   { 105U, AArch64::Z9 },
    2834             :   { 106U, AArch64::Z10 },
    2835             :   { 107U, AArch64::Z11 },
    2836             :   { 108U, AArch64::Z12 },
    2837             :   { 109U, AArch64::Z13 },
    2838             :   { 110U, AArch64::Z14 },
    2839             :   { 111U, AArch64::Z15 },
    2840             :   { 112U, AArch64::Z16 },
    2841             :   { 113U, AArch64::Z17 },
    2842             :   { 114U, AArch64::Z18 },
    2843             :   { 115U, AArch64::Z19 },
    2844             :   { 116U, AArch64::Z20 },
    2845             :   { 117U, AArch64::Z21 },
    2846             :   { 118U, AArch64::Z22 },
    2847             :   { 119U, AArch64::Z23 },
    2848             :   { 120U, AArch64::Z24 },
    2849             :   { 121U, AArch64::Z25 },
    2850             :   { 122U, AArch64::Z26 },
    2851             :   { 123U, AArch64::Z27 },
    2852             :   { 124U, AArch64::Z28 },
    2853             :   { 125U, AArch64::Z29 },
    2854             :   { 126U, AArch64::Z30 },
    2855             :   { 127U, AArch64::Z31 },
    2856             : };
    2857             : extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
    2858             : 
    2859             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
    2860             :   { AArch64::FP, 29U },
    2861             :   { AArch64::LR, 30U },
    2862             :   { AArch64::SP, 31U },
    2863             :   { AArch64::WSP, 31U },
    2864             :   { AArch64::WZR, 31U },
    2865             :   { AArch64::XZR, 31U },
    2866             :   { AArch64::B0, 64U },
    2867             :   { AArch64::B1, 65U },
    2868             :   { AArch64::B2, 66U },
    2869             :   { AArch64::B3, 67U },
    2870             :   { AArch64::B4, 68U },
    2871             :   { AArch64::B5, 69U },
    2872             :   { AArch64::B6, 70U },
    2873             :   { AArch64::B7, 71U },
    2874             :   { AArch64::B8, 72U },
    2875             :   { AArch64::B9, 73U },
    2876             :   { AArch64::B10, 74U },
    2877             :   { AArch64::B11, 75U },
    2878             :   { AArch64::B12, 76U },
    2879             :   { AArch64::B13, 77U },
    2880             :   { AArch64::B14, 78U },
    2881             :   { AArch64::B15, 79U },
    2882             :   { AArch64::B16, 80U },
    2883             :   { AArch64::B17, 81U },
    2884             :   { AArch64::B18, 82U },
    2885             :   { AArch64::B19, 83U },
    2886             :   { AArch64::B20, 84U },
    2887             :   { AArch64::B21, 85U },
    2888             :   { AArch64::B22, 86U },
    2889             :   { AArch64::B23, 87U },
    2890             :   { AArch64::B24, 88U },
    2891             :   { AArch64::B25, 89U },
    2892             :   { AArch64::B26, 90U },
    2893             :   { AArch64::B27, 91U },
    2894             :   { AArch64::B28, 92U },
    2895             :   { AArch64::B29, 93U },
    2896             :   { AArch64::B30, 94U },
    2897             :   { AArch64::B31, 95U },
    2898             :   { AArch64::D0, 64U },
    2899             :   { AArch64::D1, 65U },
    2900             :   { AArch64::D2, 66U },
    2901             :   { AArch64::D3, 67U },
    2902             :   { AArch64::D4, 68U },
    2903             :   { AArch64::D5, 69U },
    2904             :   { AArch64::D6, 70U },
    2905             :   { AArch64::D7, 71U },
    2906             :   { AArch64::D8, 72U },
    2907             :   { AArch64::D9, 73U },
    2908             :   { AArch64::D10, 74U },
    2909             :   { AArch64::D11, 75U },
    2910             :   { AArch64::D12, 76U },
    2911             :   { AArch64::D13, 77U },
    2912             :   { AArch64::D14, 78U },
    2913             :   { AArch64::D15, 79U },
    2914             :   { AArch64::D16, 80U },
    2915             :   { AArch64::D17, 81U },
    2916             :   { AArch64::D18, 82U },
    2917             :   { AArch64::D19, 83U },
    2918             :   { AArch64::D20, 84U },
    2919             :   { AArch64::D21, 85U },
    2920             :   { AArch64::D22, 86U },
    2921             :   { AArch64::D23, 87U },
    2922             :   { AArch64::D24, 88U },
    2923             :   { AArch64::D25, 89U },
    2924             :   { AArch64::D26, 90U },
    2925             :   { AArch64::D27, 91U },
    2926             :   { AArch64::D28, 92U },
    2927             :   { AArch64::D29, 93U },
    2928             :   { AArch64::D30, 94U },
    2929             :   { AArch64::D31, 95U },
    2930             :   { AArch64::H0, 64U },
    2931             :   { AArch64::H1, 65U },
    2932             :   { AArch64::H2, 66U },
    2933             :   { AArch64::H3, 67U },
    2934             :   { AArch64::H4, 68U },
    2935             :   { AArch64::H5, 69U },
    2936             :   { AArch64::H6, 70U },
    2937             :   { AArch64::H7, 71U },
    2938             :   { AArch64::H8, 72U },
    2939             :   { AArch64::H9, 73U },
    2940             :   { AArch64::H10, 74U },
    2941             :   { AArch64::H11, 75U },
    2942             :   { AArch64::H12, 76U },
    2943             :   { AArch64::H13, 77U },
    2944             :   { AArch64::H14, 78U },
    2945             :   { AArch64::H15, 79U },
    2946             :   { AArch64::H16, 80U },
    2947             :   { AArch64::H17, 81U },
    2948             :   { AArch64::H18, 82U },
    2949             :   { AArch64::H19, 83U },
    2950             :   { AArch64::H20, 84U },
    2951             :   { AArch64::H21, 85U },
    2952             :   { AArch64::H22, 86U },
    2953             :   { AArch64::H23, 87U },
    2954             :   { AArch64::H24, 88U },
    2955             :   { AArch64::H25, 89U },
    2956             :   { AArch64::H26, 90U },
    2957             :   { AArch64::H27, 91U },
    2958             :   { AArch64::H28, 92U },
    2959             :   { AArch64::H29, 93U },
    2960             :   { AArch64::H30, 94U },
    2961             :   { AArch64::H31, 95U },
    2962             :   { AArch64::P0, 48U },
    2963             :   { AArch64::P1, 49U },
    2964             :   { AArch64::P2, 50U },
    2965             :   { AArch64::P3, 51U },
    2966             :   { AArch64::P4, 52U },
    2967             :   { AArch64::P5, 53U },
    2968             :   { AArch64::P6, 54U },
    2969             :   { AArch64::P7, 55U },
    2970             :   { AArch64::P8, 56U },
    2971             :   { AArch64::P9, 57U },
    2972             :   { AArch64::P10, 58U },
    2973             :   { AArch64::P11, 59U },
    2974             :   { AArch64::P12, 60U },
    2975             :   { AArch64::P13, 61U },
    2976             :   { AArch64::P14, 62U },
    2977             :   { AArch64::P15, 63U },
    2978             :   { AArch64::Q0, 64U },
    2979             :   { AArch64::Q1, 65U },
    2980             :   { AArch64::Q2, 66U },
    2981             :   { AArch64::Q3, 67U },
    2982             :   { AArch64::Q4, 68U },
    2983             :   { AArch64::Q5, 69U },
    2984             :   { AArch64::Q6, 70U },
    2985             :   { AArch64::Q7, 71U },
    2986             :   { AArch64::Q8, 72U },
    2987             :   { AArch64::Q9, 73U },
    2988             :   { AArch64::Q10, 74U },
    2989             :   { AArch64::Q11, 75U },
    2990             :   { AArch64::Q12, 76U },
    2991             :   { AArch64::Q13, 77U },
    2992             :   { AArch64::Q14, 78U },
    2993             :   { AArch64::Q15, 79U },
    2994             :   { AArch64::Q16, 80U },
    2995             :   { AArch64::Q17, 81U },
    2996             :   { AArch64::Q18, 82U },
    2997             :   { AArch64::Q19, 83U },
    2998             :   { AArch64::Q20, 84U },
    2999             :   { AArch64::Q21, 85U },
    3000             :   { AArch64::Q22, 86U },
    3001             :   { AArch64::Q23, 87U },
    3002             :   { AArch64::Q24, 88U },
    3003             :   { AArch64::Q25, 89U },
    3004             :   { AArch64::Q26, 90U },
    3005             :   { AArch64::Q27, 91U },
    3006             :   { AArch64::Q28, 92U },
    3007             :   { AArch64::Q29, 93U },
    3008             :   { AArch64::Q30, 94U },
    3009             :   { AArch64::Q31, 95U },
    3010             :   { AArch64::S0, 64U },
    3011             :   { AArch64::S1, 65U },
    3012             :   { AArch64::S2, 66U },
    3013             :   { AArch64::S3, 67U },
    3014             :   { AArch64::S4, 68U },
    3015             :   { AArch64::S5, 69U },
    3016             :   { AArch64::S6, 70U },
    3017             :   { AArch64::S7, 71U },
    3018             :   { AArch64::S8, 72U },
    3019             :   { AArch64::S9, 73U },
    3020             :   { AArch64::S10, 74U },
    3021             :   { AArch64::S11, 75U },
    3022             :   { AArch64::S12, 76U },
    3023             :   { AArch64::S13, 77U },
    3024             :   { AArch64::S14, 78U },
    3025             :   { AArch64::S15, 79U },
    3026             :   { AArch64::S16, 80U },
    3027             :   { AArch64::S17, 81U },
    3028             :   { AArch64::S18, 82U },
    3029             :   { AArch64::S19, 83U },
    3030             :   { AArch64::S20, 84U },
    3031             :   { AArch64::S21, 85U },
    3032             :   { AArch64::S22, 86U },
    3033             :   { AArch64::S23, 87U },
    3034             :   { AArch64::S24, 88U },
    3035             :   { AArch64::S25, 89U },
    3036             :   { AArch64::S26, 90U },
    3037             :   { AArch64::S27, 91U },
    3038             :   { AArch64::S28, 92U },
    3039             :   { AArch64::S29, 93U },
    3040             :   { AArch64::S30, 94U },
    3041             :   { AArch64::S31, 95U },
    3042             :   { AArch64::W0, 0U },
    3043             :   { AArch64::W1, 1U },
    3044             :   { AArch64::W2, 2U },
    3045             :   { AArch64::W3, 3U },
    3046             :   { AArch64::W4, 4U },
    3047             :   { AArch64::W5, 5U },
    3048             :   { AArch64::W6, 6U },
    3049             :   { AArch64::W7, 7U },
    3050             :   { AArch64::W8, 8U },
    3051             :   { AArch64::W9, 9U },
    3052             :   { AArch64::W10, 10U },
    3053             :   { AArch64::W11, 11U },
    3054             :   { AArch64::W12, 12U },
    3055             :   { AArch64::W13, 13U },
    3056             :   { AArch64::W14, 14U },
    3057             :   { AArch64::W15, 15U },
    3058             :   { AArch64::W16, 16U },
    3059             :   { AArch64::W17, 17U },
    3060             :   { AArch64::W18, 18U },
    3061             :   { AArch64::W19, 19U },
    3062             :   { AArch64::W20, 20U },
    3063             :   { AArch64::W21, 21U },
    3064             :   { AArch64::W22, 22U },
    3065             :   { AArch64::W23, 23U },
    3066             :   { AArch64::W24, 24U },
    3067             :   { AArch64::W25, 25U },
    3068             :   { AArch64::W26, 26U },
    3069             :   { AArch64::W27, 27U },
    3070             :   { AArch64::W28, 28U },
    3071             :   { AArch64::W29, 29U },
    3072             :   { AArch64::W30, 30U },
    3073             :   { AArch64::X0, 0U },
    3074             :   { AArch64::X1, 1U },
    3075             :   { AArch64::X2, 2U },
    3076             :   { AArch64::X3, 3U },
    3077             :   { AArch64::X4, 4U },
    3078             :   { AArch64::X5, 5U },
    3079             :   { AArch64::X6, 6U },
    3080             :   { AArch64::X7, 7U },
    3081             :   { AArch64::X8, 8U },
    3082             :   { AArch64::X9, 9U },
    3083             :   { AArch64::X10, 10U },
    3084             :   { AArch64::X11, 11U },
    3085             :   { AArch64::X12, 12U },
    3086             :   { AArch64::X13, 13U },
    3087             :   { AArch64::X14, 14U },
    3088             :   { AArch64::X15, 15U },
    3089             :   { AArch64::X16, 16U },
    3090             :   { AArch64::X17, 17U },
    3091             :   { AArch64::X18, 18U },
    3092             :   { AArch64::X19, 19U },
    3093             :   { AArch64::X20, 20U },
    3094             :   { AArch64::X21, 21U },
    3095             :   { AArch64::X22, 22U },
    3096             :   { AArch64::X23, 23U },
    3097             :   { AArch64::X24, 24U },
    3098             :   { AArch64::X25, 25U },
    3099             :   { AArch64::X26, 26U },
    3100             :   { AArch64::X27, 27U },
    3101             :   { AArch64::X28, 28U },
    3102             :   { AArch64::Z0, 96U },
    3103             :   { AArch64::Z1, 97U },
    3104             :   { AArch64::Z2, 98U },
    3105             :   { AArch64::Z3, 99U },
    3106             :   { AArch64::Z4, 100U },
    3107             :   { AArch64::Z5, 101U },
    3108             :   { AArch64::Z6, 102U },
    3109             :   { AArch64::Z7, 103U },
    3110             :   { AArch64::Z8, 104U },
    3111             :   { AArch64::Z9, 105U },
    3112             :   { AArch64::Z10, 106U },
    3113             :   { AArch64::Z11, 107U },
    3114             :   { AArch64::Z12, 108U },
    3115             :   { AArch64::Z13, 109U },
    3116             :   { AArch64::Z14, 110U },
    3117             :   { AArch64::Z15, 111U },
    3118             :   { AArch64::Z16, 112U },
    3119             :   { AArch64::Z17, 113U },
    3120             :   { AArch64::Z18, 114U },
    3121             :   { AArch64::Z19, 115U },
    3122             :   { AArch64::Z20, 116U },
    3123             :   { AArch64::Z21, 117U },
    3124             :   { AArch64::Z22, 118U },
    3125             :   { AArch64::Z23, 119U },
    3126             :   { AArch64::Z24, 120U },
    3127             :   { AArch64::Z25, 121U },
    3128             :   { AArch64::Z26, 122U },
    3129             :   { AArch64::Z27, 123U },
    3130             :   { AArch64::Z28, 124U },
    3131             :   { AArch64::Z29, 125U },
    3132             :   { AArch64::Z30, 126U },
    3133             :   { AArch64::Z31, 127U },
    3134             : };
    3135             : extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
    3136             : 
    3137             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
    3138             :   { AArch64::FP, 29U },
    3139             :   { AArch64::LR, 30U },
    3140             :   { AArch64::SP, 31U },
    3141             :   { AArch64::WSP, 31U },
    3142             :   { AArch64::WZR, 31U },
    3143             :   { AArch64::XZR, 31U },
    3144             :   { AArch64::B0, 64U },
    3145             :   { AArch64::B1, 65U },
    3146             :   { AArch64::B2, 66U },
    3147             :   { AArch64::B3, 67U },
    3148             :   { AArch64::B4, 68U },
    3149             :   { AArch64::B5, 69U },
    3150             :   { AArch64::B6, 70U },
    3151             :   { AArch64::B7, 71U },
    3152             :   { AArch64::B8, 72U },
    3153             :   { AArch64::B9, 73U },
    3154             :   { AArch64::B10, 74U },
    3155             :   { AArch64::B11, 75U },
    3156             :   { AArch64::B12, 76U },
    3157             :   { AArch64::B13, 77U },
    3158             :   { AArch64::B14, 78U },
    3159             :   { AArch64::B15, 79U },
    3160             :   { AArch64::B16, 80U },
    3161             :   { AArch64::B17, 81U },
    3162             :   { AArch64::B18, 82U },
    3163             :   { AArch64::B19, 83U },
    3164             :   { AArch64::B20, 84U },
    3165             :   { AArch64::B21, 85U },
    3166             :   { AArch64::B22, 86U },
    3167             :   { AArch64::B23, 87U },
    3168             :   { AArch64::B24, 88U },
    3169             :   { AArch64::B25, 89U },
    3170             :   { AArch64::B26, 90U },
    3171             :   { AArch64::B27, 91U },
    3172             :   { AArch64::B28, 92U },
    3173             :   { AArch64::B29, 93U },
    3174             :   { AArch64::B30, 94U },
    3175             :   { AArch64::B31, 95U },
    3176             :   { AArch64::D0, 64U },
    3177             :   { AArch64::D1, 65U },
    3178             :   { AArch64::D2, 66U },
    3179             :   { AArch64::D3, 67U },
    3180             :   { AArch64::D4, 68U },
    3181             :   { AArch64::D5, 69U },
    3182             :   { AArch64::D6, 70U },
    3183             :   { AArch64::D7, 71U },
    3184             :   { AArch64::D8, 72U },
    3185             :   { AArch64::D9, 73U },
    3186             :   { AArch64::D10, 74U },
    3187             :   { AArch64::D11, 75U },
    3188             :   { AArch64::D12, 76U },
    3189             :   { AArch64::D13, 77U },
    3190             :   { AArch64::D14, 78U },
    3191             :   { AArch64::D15, 79U },
    3192             :   { AArch64::D16, 80U },
    3193             :   { AArch64::D17, 81U },
    3194             :   { AArch64::D18, 82U },
    3195             :   { AArch64::D19, 83U },
    3196             :   { AArch64::D20, 84U },
    3197             :   { AArch64::D21, 85U },
    3198             :   { AArch64::D22, 86U },
    3199             :   { AArch64::D23, 87U },
    3200             :   { AArch64::D24, 88U },
    3201             :   { AArch64::D25, 89U },
    3202             :   { AArch64::D26, 90U },
    3203             :   { AArch64::D27, 91U },
    3204             :   { AArch64::D28, 92U },
    3205             :   { AArch64::D29, 93U },
    3206             :   { AArch64::D30, 94U },
    3207             :   { AArch64::D31, 95U },
    3208             :   { AArch64::H0, 64U },
    3209             :   { AArch64::H1, 65U },
    3210             :   { AArch64::H2, 66U },
    3211             :   { AArch64::H3, 67U },
    3212             :   { AArch64::H4, 68U },
    3213             :   { AArch64::H5, 69U },
    3214             :   { AArch64::H6, 70U },
    3215             :   { AArch64::H7, 71U },
    3216             :   { AArch64::H8, 72U },
    3217             :   { AArch64::H9, 73U },
    3218             :   { AArch64::H10, 74U },
    3219             :   { AArch64::H11, 75U },
    3220             :   { AArch64::H12, 76U },
    3221             :   { AArch64::H13, 77U },
    3222             :   { AArch64::H14, 78U },
    3223             :   { AArch64::H15, 79U },
    3224             :   { AArch64::H16, 80U },
    3225             :   { AArch64::H17, 81U },
    3226             :   { AArch64::H18, 82U },
    3227             :   { AArch64::H19, 83U },
    3228             :   { AArch64::H20, 84U },
    3229             :   { AArch64::H21, 85U },
    3230             :   { AArch64::H22, 86U },
    3231             :   { AArch64::H23, 87U },
    3232             :   { AArch64::H24, 88U },
    3233             :   { AArch64::H25, 89U },
    3234             :   { AArch64::H26, 90U },
    3235             :   { AArch64::H27, 91U },
    3236             :   { AArch64::H28, 92U },
    3237             :   { AArch64::H29, 93U },
    3238             :   { AArch64::H30, 94U },
    3239             :   { AArch64::H31, 95U },
    3240             :   { AArch64::P0, 48U },
    3241             :   { AArch64::P1, 49U },
    3242             :   { AArch64::P2, 50U },
    3243             :   { AArch64::P3, 51U },
    3244             :   { AArch64::P4, 52U },
    3245             :   { AArch64::P5, 53U },
    3246             :   { AArch64::P6, 54U },
    3247             :   { AArch64::P7, 55U },
    3248             :   { AArch64::P8, 56U },
    3249             :   { AArch64::P9, 57U },
    3250             :   { AArch64::P10, 58U },
    3251             :   { AArch64::P11, 59U },
    3252             :   { AArch64::P12, 60U },
    3253             :   { AArch64::P13, 61U },
    3254             :   { AArch64::P14, 62U },
    3255             :   { AArch64::P15, 63U },
    3256             :   { AArch64::Q0, 64U },
    3257             :   { AArch64::Q1, 65U },
    3258             :   { AArch64::Q2, 66U },
    3259             :   { AArch64::Q3, 67U },
    3260             :   { AArch64::Q4, 68U },
    3261             :   { AArch64::Q5, 69U },
    3262             :   { AArch64::Q6, 70U },
    3263             :   { AArch64::Q7, 71U },
    3264             :   { AArch64::Q8, 72U },
    3265             :   { AArch64::Q9, 73U },
    3266             :   { AArch64::Q10, 74U },
    3267             :   { AArch64::Q11, 75U },
    3268             :   { AArch64::Q12, 76U },
    3269             :   { AArch64::Q13, 77U },
    3270             :   { AArch64::Q14, 78U },
    3271             :   { AArch64::Q15, 79U },
    3272             :   { AArch64::Q16, 80U },
    3273             :   { AArch64::Q17, 81U },
    3274             :   { AArch64::Q18, 82U },
    3275             :   { AArch64::Q19, 83U },
    3276             :   { AArch64::Q20, 84U },
    3277             :   { AArch64::Q21, 85U },
    3278             :   { AArch64::Q22, 86U },
    3279             :   { AArch64::Q23, 87U },
    3280             :   { AArch64::Q24, 88U },
    3281             :   { AArch64::Q25, 89U },
    3282             :   { AArch64::Q26, 90U },
    3283             :   { AArch64::Q27, 91U },
    3284             :   { AArch64::Q28, 92U },
    3285             :   { AArch64::Q29, 93U },
    3286             :   { AArch64::Q30, 94U },
    3287             :   { AArch64::Q31, 95U },
    3288             :   { AArch64::S0, 64U },
    3289             :   { AArch64::S1, 65U },
    3290             :   { AArch64::S2, 66U },
    3291             :   { AArch64::S3, 67U },
    3292             :   { AArch64::S4, 68U },
    3293             :   { AArch64::S5, 69U },
    3294             :   { AArch64::S6, 70U },
    3295             :   { AArch64::S7, 71U },
    3296             :   { AArch64::S8, 72U },
    3297             :   { AArch64::S9, 73U },
    3298             :   { AArch64::S10, 74U },
    3299             :   { AArch64::S11, 75U },
    3300             :   { AArch64::S12, 76U },
    3301             :   { AArch64::S13, 77U },
    3302             :   { AArch64::S14, 78U },
    3303             :   { AArch64::S15, 79U },
    3304             :   { AArch64::S16, 80U },
    3305             :   { AArch64::S17, 81U },
    3306             :   { AArch64::S18, 82U },
    3307             :   { AArch64::S19, 83U },
    3308             :   { AArch64::S20, 84U },
    3309             :   { AArch64::S21, 85U },
    3310             :   { AArch64::S22, 86U },
    3311             :   { AArch64::S23, 87U },
    3312             :   { AArch64::S24, 88U },
    3313             :   { AArch64::S25, 89U },
    3314             :   { AArch64::S26, 90U },
    3315             :   { AArch64::S27, 91U },
    3316             :   { AArch64::S28, 92U },
    3317             :   { AArch64::S29, 93U },
    3318             :   { AArch64::S30, 94U },
    3319             :   { AArch64::S31, 95U },
    3320             :   { AArch64::W0, 0U },
    3321             :   { AArch64::W1, 1U },
    3322             :   { AArch64::W2, 2U },
    3323             :   { AArch64::W3, 3U },
    3324             :   { AArch64::W4, 4U },
    3325             :   { AArch64::W5, 5U },
    3326             :   { AArch64::W6, 6U },
    3327             :   { AArch64::W7, 7U },
    3328             :   { AArch64::W8, 8U },
    3329             :   { AArch64::W9, 9U },
    3330             :   { AArch64::W10, 10U },
    3331             :   { AArch64::W11, 11U },
    3332             :   { AArch64::W12, 12U },
    3333             :   { AArch64::W13, 13U },
    3334             :   { AArch64::W14, 14U },
    3335             :   { AArch64::W15, 15U },
    3336             :   { AArch64::W16, 16U },
    3337             :   { AArch64::W17, 17U },
    3338             :   { AArch64::W18, 18U },
    3339             :   { AArch64::W19, 19U },
    3340             :   { AArch64::W20, 20U },
    3341             :   { AArch64::W21, 21U },
    3342             :   { AArch64::W22, 22U },
    3343             :   { AArch64::W23, 23U },
    3344             :   { AArch64::W24, 24U },
    3345             :   { AArch64::W25, 25U },
    3346             :   { AArch64::W26, 26U },
    3347             :   { AArch64::W27, 27U },
    3348             :   { AArch64::W28, 28U },
    3349             :   { AArch64::W29, 29U },
    3350             :   { AArch64::W30, 30U },
    3351             :   { AArch64::X0, 0U },
    3352             :   { AArch64::X1, 1U },
    3353             :   { AArch64::X2, 2U },
    3354             :   { AArch64::X3, 3U },
    3355             :   { AArch64::X4, 4U },
    3356             :   { AArch64::X5, 5U },
    3357             :   { AArch64::X6, 6U },
    3358             :   { AArch64::X7, 7U },
    3359             :   { AArch64::X8, 8U },
    3360             :   { AArch64::X9, 9U },
    3361             :   { AArch64::X10, 10U },
    3362             :   { AArch64::X11, 11U },
    3363             :   { AArch64::X12, 12U },
    3364             :   { AArch64::X13, 13U },
    3365             :   { AArch64::X14, 14U },
    3366             :   { AArch64::X15, 15U },
    3367             :   { AArch64::X16, 16U },
    3368             :   { AArch64::X17, 17U },
    3369             :   { AArch64::X18, 18U },
    3370             :   { AArch64::X19, 19U },
    3371             :   { AArch64::X20, 20U },
    3372             :   { AArch64::X21, 21U },
    3373             :   { AArch64::X22, 22U },
    3374             :   { AArch64::X23, 23U },
    3375             :   { AArch64::X24, 24U },
    3376             :   { AArch64::X25, 25U },
    3377             :   { AArch64::X26, 26U },
    3378             :   { AArch64::X27, 27U },
    3379             :   { AArch64::X28, 28U },
    3380             :   { AArch64::Z0, 96U },
    3381             :   { AArch64::Z1, 97U },
    3382             :   { AArch64::Z2, 98U },
    3383             :   { AArch64::Z3, 99U },
    3384             :   { AArch64::Z4, 100U },
    3385             :   { AArch64::Z5, 101U },
    3386             :   { AArch64::Z6, 102U },
    3387             :   { AArch64::Z7, 103U },
    3388             :   { AArch64::Z8, 104U },
    3389             :   { AArch64::Z9, 105U },
    3390             :   { AArch64::Z10, 106U },
    3391             :   { AArch64::Z11, 107U },
    3392             :   { AArch64::Z12, 108U },
    3393             :   { AArch64::Z13, 109U },
    3394             :   { AArch64::Z14, 110U },
    3395             :   { AArch64::Z15, 111U },
    3396             :   { AArch64::Z16, 112U },
    3397             :   { AArch64::Z17, 113U },
    3398             :   { AArch64::Z18, 114U },
    3399             :   { AArch64::Z19, 115U },
    3400             :   { AArch64::Z20, 116U },
    3401             :   { AArch64::Z21, 117U },
    3402             :   { AArch64::Z22, 118U },
    3403             :   { AArch64::Z23, 119U },
    3404             :   { AArch64::Z24, 120U },
    3405             :   { AArch64::Z25, 121U },
    3406             :   { AArch64::Z26, 122U },
    3407             :   { AArch64::Z27, 123U },
    3408             :   { AArch64::Z28, 124U },
    3409             :   { AArch64::Z29, 125U },
    3410             :   { AArch64::Z30, 126U },
    3411             :   { AArch64::Z31, 127U },
    3412             : };
    3413             : extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
    3414             : 
    3415             : extern const uint16_t AArch64RegEncodingTable[] = {
    3416             :   0,
    3417             :   29,
    3418             :   30,
    3419             :   0,
    3420             :   31,
    3421             :   31,
    3422             :   31,
    3423             :   31,
    3424             :   0,
    3425             :   1,
    3426             :   2,
    3427             :   3,
    3428             :   4,
    3429             :   5,
    3430             :   6,
    3431             :   7,
    3432             :   8,
    3433             :   9,
    3434             :   10,
    3435             :   11,
    3436             :   12,
    3437             :   13,
    3438             :   14,
    3439             :   15,
    3440             :   16,
    3441             :   17,
    3442             :   18,
    3443             :   19,
    3444             :   20,
    3445             :   21,
    3446             :   22,
    3447             :   23,
    3448             :   24,
    3449             :   25,
    3450             :   26,
    3451             :   27,
    3452             :   28,
    3453             :   29,
    3454             :   30,
    3455             :   31,
    3456             :   0,
    3457             :   1,
    3458             :   2,
    3459             :   3,
    3460             :   4,
    3461             :   5,
    3462             :   6,
    3463             :   7,
    3464             :   8,
    3465             :   9,
    3466             :   10,
    3467             :   11,
    3468             :   12,
    3469             :   13,
    3470             :   14,
    3471             :   15,
    3472             :   16,
    3473             :   17,
    3474             :   18,
    3475             :   19,
    3476             :   20,
    3477             :   21,
    3478             :   22,
    3479             :   23,
    3480             :   24,
    3481             :   25,
    3482             :   26,
    3483             :   27,
    3484             :   28,
    3485             :   29,
    3486             :   30,
    3487             :   31,
    3488             :   0,
    3489             :   1,
    3490             :   2,
    3491             :   3,
    3492             :   4,
    3493             :   5,
    3494             :   6,
    3495             :   7,
    3496             :   8,
    3497             :   9,
    3498             :   10,
    3499             :   11,
    3500             :   12,
    3501             :   13,
    3502             :   14,
    3503             :   15,
    3504             :   16,
    3505             :   17,
    3506             :   18,
    3507             :   19,
    3508             :   20,
    3509             :   21,
    3510             :   22,
    3511             :   23,
    3512             :   24,
    3513             :   25,
    3514             :   26,
    3515             :   27,
    3516             :   28,
    3517             :   29,
    3518             :   30,
    3519             :   31,
    3520             :   0,
    3521             :   1,
    3522             :   2,
    3523             :   3,
    3524             :   4,
    3525             :   5,
    3526             :   6,
    3527             :   7,
    3528             :   8,
    3529             :   9,
    3530             :   10,
    3531             :   11,
    3532             :   12,
    3533             :   13,
    3534             :   14,
    3535             :   15,
    3536             :   0,
    3537             :   1,
    3538             :   2,
    3539             :   3,
    3540             :   4,
    3541             :   5,
    3542             :   6,
    3543             :   7,
    3544             :   8,
    3545             :   9,
    3546             :   10,
    3547             :   11,
    3548             :   12,
    3549             :   13,
    3550             :   14,
    3551             :   15,
    3552             :   16,
    3553             :   17,
    3554             :   18,
    3555             :   19,
    3556             :   20,
    3557             :   21,
    3558             :   22,
    3559             :   23,
    3560             :   24,
    3561             :   25,
    3562             :   26,
    3563             :   27,
    3564             :   28,
    3565             :   29,
    3566             :   30,
    3567             :   31,
    3568             :   0,
    3569             :   1,
    3570             :   2,
    3571             :   3,
    3572             :   4,
    3573             :   5,
    3574             :   6,
    3575             :   7,
    3576             :   8,
    3577             :   9,
    3578             :   10,
    3579             :   11,
    3580             :   12,
    3581             :   13,
    3582             :   14,
    3583             :   15,
    3584             :   16,
    3585             :   17,
    3586             :   18,
    3587             :   19,
    3588             :   20,
    3589             :   21,
    3590             :   22,
    3591             :   23,
    3592             :   24,
    3593             :   25,
    3594             :   26,
    3595             :   27,
    3596             :   28,
    3597             :   29,
    3598             :   30,
    3599             :   31,
    3600             :   0,
    3601             :   1,
    3602             :   2,
    3603             :   3,
    3604             :   4,
    3605             :   5,
    3606             :   6,
    3607             :   7,
    3608             :   8,
    3609             :   9,
    3610             :   10,
    3611             :   11,
    3612             :   12,
    3613             :   13,
    3614             :   14,
    3615             :   15,
    3616             :   16,
    3617             :   17,
    3618             :   18,
    3619             :   19,
    3620             :   20,
    3621             :   21,
    3622             :   22,
    3623             :   23,
    3624             :   24,
    3625             :   25,
    3626             :   26,
    3627             :   27,
    3628             :   28,
    3629             :   29,
    3630             :   30,
    3631             :   0,
    3632             :   1,
    3633             :   2,
    3634             :   3,
    3635             :   4,
    3636             :   5,
    3637             :   6,
    3638             :   7,
    3639             :   8,
    3640             :   9,
    3641             :   10,
    3642             :   11,
    3643             :   12,
    3644             :   13,
    3645             :   14,
    3646             :   15,
    3647             :   16,
    3648             :   17,
    3649             :   18,
    3650             :   19,
    3651             :   20,
    3652             :   21,
    3653             :   22,
    3654             :   23,
    3655             :   24,
    3656             :   25,
    3657             :   26,
    3658             :   27,
    3659             :   28,
    3660             :   0,
    3661             :   1,
    3662             :   2,
    3663             :   3,
    3664             :   4,
    3665             :   5,
    3666             :   6,
    3667             :   7,
    3668             :   8,
    3669             :   9,
    3670             :   10,
    3671             :   11,
    3672             :   12,
    3673             :   13,
    3674             :   14,
    3675             :   15,
    3676             :   16,
    3677             :   17,
    3678             :   18,
    3679             :   19,
    3680             :   20,
    3681             :   21,
    3682             :   22,
    3683             :   23,
    3684             :   24,
    3685             :   25,
    3686             :   26,
    3687             :   27,
    3688             :   28,
    3689             :   29,
    3690             :   30,
    3691             :   31,
    3692             :   0,
    3693             :   1,
    3694             :   2,
    3695             :   3,
    3696             :   4,
    3697             :   5,
    3698             :   6,
    3699             :   7,
    3700             :   8,
    3701             :   9,
    3702             :   10,
    3703             :   11,
    3704             :   12,
    3705             :   13,
    3706             :   14,
    3707             :   15,
    3708             :   16,
    3709             :   17,
    3710             :   18,
    3711             :   19,
    3712             :   20,
    3713             :   21,
    3714             :   22,
    3715             :   23,
    3716             :   24,
    3717             :   25,
    3718             :   26,
    3719             :   27,
    3720             :   28,
    3721             :   29,
    3722             :   30,
    3723             :   31,
    3724             :   0,
    3725             :   1,
    3726             :   2,
    3727             :   3,
    3728             :   4,
    3729             :   5,
    3730             :   6,
    3731             :   7,
    3732             :   8,
    3733             :   9,
    3734             :   10,
    3735             :   11,
    3736             :   12,
    3737             :   13,
    3738             :   14,
    3739             :   15,
    3740             :   16,
    3741             :   17,
    3742             :   18,
    3743             :   19,
    3744             :   20,
    3745             :   21,
    3746             :   22,
    3747             :   23,
    3748             :   24,
    3749             :   25,
    3750             :   26,
    3751             :   27,
    3752             :   28,
    3753             :   29,
    3754             :   30,
    3755             :   31,
    3756             :   0,
    3757             :   1,
    3758             :   2,
    3759             :   3,
    3760             :   4,
    3761             :   5,
    3762             :   6,
    3763             :   7,
    3764             :   8,
    3765             :   9,
    3766             :   10,
    3767             :   11,
    3768             :   12,
    3769             :   13,
    3770             :   14,
    3771             :   15,
    3772             :   16,
    3773             :   17,
    3774             :   18,
    3775             :   19,
    3776             :   20,
    3777             :   21,
    3778             :   22,
    3779             :   23,
    3780             :   24,
    3781             :   25,
    3782             :   26,
    3783             :   27,
    3784             :   28,
    3785             :   29,
    3786             :   30,
    3787             :   31,
    3788             :   0,
    3789             :   1,
    3790             :   2,
    3791             :   3,
    3792             :   4,
    3793             :   5,
    3794             :   6,
    3795             :   7,
    3796             :   8,
    3797             :   9,
    3798             :   10,
    3799             :   11,
    3800             :   12,
    3801             :   13,
    3802             :   14,
    3803             :   15,
    3804             :   16,
    3805             :   17,
    3806             :   18,
    3807             :   19,
    3808             :   20,
    3809             :   21,
    3810             :   22,
    3811             :   23,
    3812             :   24,
    3813             :   25,
    3814             :   26,
    3815             :   27,
    3816             :   28,
    3817             :   29,
    3818             :   30,
    3819             :   31,
    3820             :   0,
    3821             :   1,
    3822             :   2,
    3823             :   3,
    3824             :   4,
    3825             :   5,
    3826             :   6,
    3827             :   7,
    3828             :   8,
    3829             :   9,
    3830             :   10,
    3831             :   11,
    3832             :   12,
    3833             :   13,
    3834             :   14,
    3835             :   15,
    3836             :   16,
    3837             :   17,
    3838             :   18,
    3839             :   19,
    3840             :   20,
    3841             :   21,
    3842             :   22,
    3843             :   23,
    3844             :   24,
    3845             :   25,
    3846             :   26,
    3847             :   27,
    3848             :   28,
    3849             :   29,
    3850             :   30,
    3851             :   31,
    3852             :   0,
    3853             :   1,
    3854             :   2,
    3855             :   3,
    3856             :   4,
    3857             :   5,
    3858             :   6,
    3859             :   7,
    3860             :   8,
    3861             :   9,
    3862             :   10,
    3863             :   11,
    3864             :   12,
    3865             :   13,
    3866             :   14,
    3867             :   15,
    3868             :   16,
    3869             :   17,
    3870             :   18,
    3871             :   19,
    3872             :   20,
    3873             :   21,
    3874             :   22,
    3875             :   23,
    3876             :   24,
    3877             :   25,
    3878             :   26,
    3879             :   27,
    3880             :   28,
    3881             :   29,
    3882             :   30,
    3883             :   31,
    3884             :   0,
    3885             :   1,
    3886             :   2,
    3887             :   3,
    3888             :   4,
    3889             :   5,
    3890             :   6,
    3891             :   7,
    3892             :   8,
    3893             :   9,
    3894             :   10,
    3895             :   11,
    3896             :   12,
    3897             :   13,
    3898             :   14,
    3899             :   15,
    3900             :   16,
    3901             :   17,
    3902             :   18,
    3903             :   19,
    3904             :   20,
    3905             :   21,
    3906             :   22,
    3907             :   23,
    3908             :   24,
    3909             :   25,
    3910             :   26,
    3911             :   27,
    3912             :   28,
    3913             :   29,
    3914             :   30,
    3915             :   31,
    3916             :   31,
    3917             :   30,
    3918             :   0,
    3919             :   1,
    3920             :   2,
    3921             :   3,
    3922             :   4,
    3923             :   5,
    3924             :   6,
    3925             :   7,
    3926             :   8,
    3927             :   9,
    3928             :   10,
    3929             :   11,
    3930             :   12,
    3931             :   13,
    3932             :   14,
    3933             :   15,
    3934             :   16,
    3935             :   17,
    3936             :   18,
    3937             :   19,
    3938             :   20,
    3939             :   21,
    3940             :   22,
    3941             :   23,
    3942             :   24,
    3943             :   25,
    3944             :   26,
    3945             :   27,
    3946             :   28,
    3947             :   29,
    3948             :   29,
    3949             :   30,
    3950             :   31,
    3951             :   28,
    3952             :   0,
    3953             :   1,
    3954             :   2,
    3955             :   3,
    3956             :   4,
    3957             :   5,
    3958             :   6,
    3959             :   7,
    3960             :   8,
    3961             :   9,
    3962             :   10,
    3963             :   11,
    3964             :   12,
    3965             :   13,
    3966             :   14,
    3967             :   15,
    3968             :   16,
    3969             :   17,
    3970             :   18,
    3971             :   19,
    3972             :   20,
    3973             :   21,
    3974             :   22,
    3975             :   23,
    3976             :   24,
    3977             :   25,
    3978             :   26,
    3979             :   27,
    3980             : };
    3981             : static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
    3982             :   RI->InitMCRegisterInfo(AArch64RegDesc, 564, RA, PC, AArch64MCRegisterClasses, 58, AArch64RegUnitRoots, 114, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 61,
    3983             : AArch64SubRegIdxRanges, AArch64RegEncodingTable);
    3984             : 
    3985             :   switch (DwarfFlavour) {
    3986             :   default:
    3987             :     llvm_unreachable("Unknown DWARF flavour");
    3988             :   case 0:
    3989             :     RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
    3990             :     break;
    3991             :   }
    3992             :   switch (EHFlavour) {
    3993             :   default:
    3994             :     llvm_unreachable("Unknown DWARF flavour");
    3995             :   case 0:
    3996             :     RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
    3997             :     break;
    3998             :   }
    3999             :   switch (DwarfFlavour) {
    4000             :   default:
    4001             :     llvm_unreachable("Unknown DWARF flavour");
    4002             :   case 0:
    4003             :     RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
    4004             :     break;
    4005             :   }
    4006             :   switch (EHFlavour) {
    4007             :   default:
    4008             :     llvm_unreachable("Unknown DWARF flavour");
    4009             :   case 0:
    4010             :     RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
    4011             :     break;
    4012             :   }
    4013             : }
    4014             : 
    4015             : } // end namespace llvm
    4016             : 
    4017             : #endif // GET_REGINFO_MC_DESC
    4018             : 
    4019             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    4020             : |*                                                                            *|
    4021             : |* Register Information Header Fragment                                       *|
    4022             : |*                                                                            *|
    4023             : |* Automatically generated file, do not edit!                                 *|
    4024             : |*                                                                            *|
    4025             : \*===----------------------------------------------------------------------===*/
    4026             : 
    4027             : 
    4028             : #ifdef GET_REGINFO_HEADER
    4029             : #undef GET_REGINFO_HEADER
    4030             : 
    4031             : #include "llvm/CodeGen/TargetRegisterInfo.h"
    4032             : 
    4033             : namespace llvm {
    4034             : 
    4035             : class AArch64FrameLowering;
    4036             : 
    4037        1298 : struct AArch64GenRegisterInfo : public TargetRegisterInfo {
    4038             :   explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
    4039             :       unsigned PC = 0, unsigned HwMode = 0);
    4040             :   unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
    4041             :   LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    4042             :   LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    4043             :   const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
    4044             :   const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
    4045             :   unsigned getRegUnitWeight(unsigned RegUnit) const override;
    4046             :   unsigned getNumRegPressureSets() const override;
    4047             :   const char *getRegPressureSetName(unsigned Idx) const override;
    4048             :   unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
    4049             :   const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
    4050             :   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
    4051             :   ArrayRef<const char *> getRegMaskNames() const override;
    4052             :   ArrayRef<const uint32_t *> getRegMasks() const override;
    4053             :   /// Devirtualized TargetFrameLowering.
    4054             :   static const AArch64FrameLowering *getFrameLowering(
    4055             :       const MachineFunction &MF);
    4056             : };
    4057             : 
    4058             : namespace AArch64 { // Register classes
    4059             :   extern const TargetRegisterClass FPR8RegClass;
    4060             :   extern const TargetRegisterClass FPR16RegClass;
    4061             :   extern const TargetRegisterClass PPRRegClass;
    4062             :   extern const TargetRegisterClass PPR_3bRegClass;
    4063             :   extern const TargetRegisterClass GPR32allRegClass;
    4064             :   extern const TargetRegisterClass FPR32RegClass;
    4065             :   extern const TargetRegisterClass GPR32RegClass;
    4066             :   extern const TargetRegisterClass GPR32spRegClass;
    4067             :   extern const TargetRegisterClass GPR32commonRegClass;
    4068             :   extern const TargetRegisterClass CCRRegClass;
    4069             :   extern const TargetRegisterClass GPR32sponlyRegClass;
    4070             :   extern const TargetRegisterClass WSeqPairsClassRegClass;
    4071             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass;
    4072             :   extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
    4073             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
    4074             :   extern const TargetRegisterClass GPR64allRegClass;
    4075             :   extern const TargetRegisterClass FPR64RegClass;
    4076             :   extern const TargetRegisterClass GPR64RegClass;
    4077             :   extern const TargetRegisterClass GPR64spRegClass;
    4078             :   extern const TargetRegisterClass GPR64commonRegClass;
    4079             :   extern const TargetRegisterClass tcGPR64RegClass;
    4080             :   extern const TargetRegisterClass GPR64sponlyRegClass;
    4081             :   extern const TargetRegisterClass DDRegClass;
    4082             :   extern const TargetRegisterClass XSeqPairsClassRegClass;
    4083             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass;
    4084             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
    4085             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
    4086             :   extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
    4087             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
    4088             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
    4089             :   extern const TargetRegisterClass FPR128RegClass;
    4090             :   extern const TargetRegisterClass ZPRRegClass;
    4091             :   extern const TargetRegisterClass FPR128_loRegClass;
    4092             :   extern const TargetRegisterClass ZPR_with_zsub_in_FPR128_loRegClass;
    4093             :   extern const TargetRegisterClass DDDRegClass;
    4094             :   extern const TargetRegisterClass DDDDRegClass;
    4095             :   extern const TargetRegisterClass QQRegClass;
    4096             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
    4097             :   extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;
    4098             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass;
    4099             :   extern const TargetRegisterClass QQQRegClass;
    4100             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass;
    4101             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass;
    4102             :   extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass;
    4103             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass;
    4104             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
    4105             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
    4106             :   extern const TargetRegisterClass QQQQRegClass;
    4107             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass;
    4108             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass;
    4109             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass;
    4110             :   extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass;
    4111             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass;
    4112             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
    4113             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    4114             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
    4115             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    4116             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    4117             : } // end namespace AArch64
    4118             : 
    4119             : } // end namespace llvm
    4120             : 
    4121             : #endif // GET_REGINFO_HEADER
    4122             : 
    4123             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    4124             : |*                                                                            *|
    4125             : |* Target Register and Register Classes Information                           *|
    4126             : |*                                                                            *|
    4127             : |* Automatically generated file, do not edit!                                 *|
    4128             : |*                                                                            *|
    4129             : \*===----------------------------------------------------------------------===*/
    4130             : 
    4131             : 
    4132             : #ifdef GET_REGINFO_TARGET_DESC
    4133             : #undef GET_REGINFO_TARGET_DESC
    4134             : 
    4135             : namespace llvm {
    4136             : 
    4137             : extern const MCRegisterClass AArch64MCRegisterClasses[];
    4138             : 
    4139             : static const MVT::SimpleValueType VTLists[] = {
    4140             :   /* 0 */ MVT::f32, MVT::i32, MVT::Other,
    4141             :   /* 3 */ MVT::i64, MVT::Other,
    4142             :   /* 5 */ MVT::f16, MVT::Other,
    4143             :   /* 7 */ MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::Other,
    4144             :   /* 12 */ MVT::f64, MVT::i64, MVT::v2f32, MVT::v1f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v4f16, MVT::Other,
    4145             :   /* 22 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::v8f16, MVT::Other,
    4146             :   /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
    4147             :   /* 39 */ MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64, MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv1f32, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv1f64, MVT::nxv2f64, MVT::Other,
    4148             :   /* 52 */ MVT::Untyped, MVT::Other,
    4149             : };
    4150             : 
    4151             : static const char *const SubRegIndexNameTable[] = { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1", "qsub2", "qsub3", "ssub", "sub_32", "sube32", "sube64", "subo32", "subo64", "zsub", "zsub_hi", "dsub1_then_bsub", "dsub1_then_hsub", "dsub1_then_ssub", "dsub3_then_bsub", "dsub3_then_hsub", "dsub3_then_ssub", "dsub2_then_bsub", "dsub2_then_hsub", "dsub2_then_ssub", "qsub1_then_bsub", "qsub1_then_dsub", "qsub1_then_hsub", "qsub1_then_ssub", "qsub3_then_bsub", "qsub3_then_dsub", "qsub3_then_hsub", "qsub3_then_ssub", "qsub2_then_bsub", "qsub2_then_dsub", "qsub2_then_hsub", "qsub2_then_ssub", "subo64_then_sub_32", "dsub0_dsub1", "dsub0_dsub1_dsub2", "dsub1_dsub2", "dsub1_dsub2_dsub3", "dsub2_dsub3", "dsub_qsub1_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub", "qsub0_qsub1", "qsub0_qsub1_qsub2", "qsub1_qsub2", "qsub1_qsub2_qsub3", "qsub2_qsub3", "qsub1_then_dsub_qsub2_then_dsub", "qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "qsub2_then_dsub_qsub3_then_dsub", "sub_32_subo64_then_sub_32", "" };
    4152             : 
    4153             : 
    4154             : static const LaneBitmask SubRegIndexLaneMaskTable[] = {
    4155             :   LaneBitmask::getAll(),
    4156             :   LaneBitmask(0x00000001), // bsub
    4157             :   LaneBitmask(0x00000001), // dsub
    4158             :   LaneBitmask(0x00000001), // dsub0
    4159             :   LaneBitmask(0x00000080), // dsub1
    4160             :   LaneBitmask(0x00000200), // dsub2
    4161             :   LaneBitmask(0x00000100), // dsub3
    4162             :   LaneBitmask(0x00000001), // hsub
    4163             :   LaneBitmask(0x00000002), // qhisub
    4164             :   LaneBitmask(0x00000004), // qsub
    4165             :   LaneBitmask(0x00000001), // qsub0
    4166             :   LaneBitmask(0x00000400), // qsub1
    4167             :   LaneBitmask(0x00001000), // qsub2
    4168             :   LaneBitmask(0x00000800), // qsub3
    4169             :   LaneBitmask(0x00000001), // ssub
    4170             :   LaneBitmask(0x00000008), // sub_32
    4171             :   LaneBitmask(0x00000010), // sube32
    4172             :   LaneBitmask(0x00000008), // sube64
    4173             :   LaneBitmask(0x00000020), // subo32
    4174             :   LaneBitmask(0x00002000), // subo64
    4175             :   LaneBitmask(0x00000001), // zsub
    4176             :   LaneBitmask(0x00000040), // zsub_hi
    4177             :   LaneBitmask(0x00000080), // dsub1_then_bsub
    4178             :   LaneBitmask(0x00000080), // dsub1_then_hsub
    4179             :   LaneBitmask(0x00000080), // dsub1_then_ssub
    4180             :   LaneBitmask(0x00000100), // dsub3_then_bsub
    4181             :   LaneBitmask(0x00000100), // dsub3_then_hsub
    4182             :   LaneBitmask(0x00000100), // dsub3_then_ssub
    4183             :   LaneBitmask(0x00000200), // dsub2_then_bsub
    4184             :   LaneBitmask(0x00000200), // dsub2_then_hsub
    4185             :   LaneBitmask(0x00000200), // dsub2_then_ssub
    4186             :   LaneBitmask(0x00000400), // qsub1_then_bsub
    4187             :   LaneBitmask(0x00000400), // qsub1_then_dsub
    4188             :   LaneBitmask(0x00000400), // qsub1_then_hsub
    4189             :   LaneBitmask(0x00000400), // qsub1_then_ssub
    4190             :   LaneBitmask(0x00000800), // qsub3_then_bsub
    4191             :   LaneBitmask(0x00000800), // qsub3_then_dsub
    4192             :   LaneBitmask(0x00000800), // qsub3_then_hsub
    4193             :   LaneBitmask(0x00000800), // qsub3_then_ssub
    4194             :   LaneBitmask(0x00001000), // qsub2_then_bsub
    4195             :   LaneBitmask(0x00001000), // qsub2_then_dsub
    4196             :   LaneBitmask(0x00001000), // qsub2_then_hsub
    4197             :   LaneBitmask(0x00001000), // qsub2_then_ssub
    4198             :   LaneBitmask(0x00002000), // subo64_then_sub_32
    4199             :   LaneBitmask(0x00000081), // dsub0_dsub1
    4200             :   LaneBitmask(0x00000281), // dsub0_dsub1_dsub2
    4201             :   LaneBitmask(0x00000280), // dsub1_dsub2
    4202             :   LaneBitmask(0x00000380), // dsub1_dsub2_dsub3
    4203             :   LaneBitmask(0x00000300), // dsub2_dsub3
    4204             :   LaneBitmask(0x00000401), // dsub_qsub1_then_dsub
    4205             :   LaneBitmask(0x00001C01), // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    4206             :   LaneBitmask(0x00001401), // dsub_qsub1_then_dsub_qsub2_then_dsub
    4207             :   LaneBitmask(0x00000401), // qsub0_qsub1
    4208             :   LaneBitmask(0x00001401), // qsub0_qsub1_qsub2
    4209             :   LaneBitmask(0x00001400), // qsub1_qsub2
    4210             :   LaneBitmask(0x00001C00), // qsub1_qsub2_qsub3
    4211             :   LaneBitmask(0x00001800), // qsub2_qsub3
    4212             :   LaneBitmask(0x00001400), // qsub1_then_dsub_qsub2_then_dsub
    4213             :   LaneBitmask(0x00001C00), // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    4214             :   LaneBitmask(0x00001800), // qsub2_then_dsub_qsub3_then_dsub
    4215             :   LaneBitmask(0x00002008), // sub_32_subo64_then_sub_32
    4216             :  };
    4217             : 
    4218             : 
    4219             : 
    4220             : static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
    4221             :   // Mode = 0 (Default)
    4222             :   { 8, 8, 8, VTLists+52 },    // FPR8
    4223             :   { 16, 16, 16, VTLists+5 },    // FPR16
    4224             :   { 16, 16, 16, VTLists+7 },    // PPR
    4225             :   { 16, 16, 16, VTLists+7 },    // PPR_3b
    4226             :   { 32, 32, 32, VTLists+1 },    // GPR32all
    4227             :   { 32, 32, 32, VTLists+0 },    // FPR32
    4228             :   { 32, 32, 32, VTLists+1 },    // GPR32
    4229             :   { 32, 32, 32, VTLists+1 },    // GPR32sp
    4230             :   { 32, 32, 32, VTLists+1 },    // GPR32common
    4231             :   { 32, 32, 32, VTLists+1 },    // CCR
    4232             :   { 32, 32, 32, VTLists+1 },    // GPR32sponly
    4233             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass
    4234             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_sube32_in_GPR32common
    4235             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_subo32_in_GPR32common
    4236             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    4237             :   { 64, 64, 64, VTLists+3 },    // GPR64all
    4238             :   { 64, 64, 64, VTLists+12 },    // FPR64
    4239             :   { 64, 64, 64, VTLists+3 },    // GPR64
    4240             :   { 64, 64, 64, VTLists+3 },    // GPR64sp
    4241             :   { 64, 64, 64, VTLists+3 },    // GPR64common
    4242             :   { 64, 64, 64, VTLists+3 },    // tcGPR64
    4243             :   { 64, 64, 64, VTLists+3 },    // GPR64sponly
    4244             :   { 128, 128, 64, VTLists+52 },    // DD
    4245             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass
    4246             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common
    4247             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_GPR64common
    4248             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    4249             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sube64_in_tcGPR64
    4250             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_tcGPR64
    4251             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    4252             :   { 128, 128, 128, VTLists+22 },    // FPR128
    4253             :   { 128, 128, 128, VTLists+39 },    // ZPR
    4254             :   { 128, 128, 128, VTLists+31 },    // FPR128_lo
    4255             :   { 128, 128, 128, VTLists+39 },    // ZPR_with_zsub_in_FPR128_lo
    4256             :   { 192, 192, 64, VTLists+52 },    // DDD
    4257             :   { 256, 256, 64, VTLists+52 },    // DDDD
    4258             :   { 256, 256, 128, VTLists+52 },    // QQ
    4259             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub0_in_FPR128_lo
    4260             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub1_in_FPR128_lo
    4261             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    4262             :   { 384, 384, 128, VTLists+52 },    // QQQ
    4263             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo
    4264             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub1_in_FPR128_lo
    4265             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub2_in_FPR128_lo
    4266             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    4267             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    4268             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    4269             :   { 512, 512, 128, VTLists+52 },    // QQQQ
    4270             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo
    4271             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo
    4272             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub2_in_FPR128_lo
    4273             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub3_in_FPR128_lo
    4274             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    4275             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    4276             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    4277             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    4278             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    4279             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    4280             : };
    4281             : 
    4282             : static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
    4283             : 
    4284             : static const uint32_t FPR8SubClassMask[] = {
    4285             :   0x00000001, 0x00000000, 
    4286             :   0xc0410022, 0x03ffffff, // bsub
    4287             :   0x00400000, 0x0000000c, // dsub1_then_bsub
    4288             :   0x00000000, 0x00000008, // dsub3_then_bsub
    4289             :   0x00000000, 0x0000000c, // dsub2_then_bsub
    4290             :   0x00000000, 0x03fffff0, // qsub1_then_bsub
    4291             :   0x00000000, 0x03ff8000, // qsub3_then_bsub
    4292             :   0x00000000, 0x03ffff00, // qsub2_then_bsub
    4293             : };
    4294             : 
    4295             : static const uint32_t FPR16SubClassMask[] = {
    4296             :   0x00000002, 0x00000000, 
    4297             :   0xc0410020, 0x03ffffff, // hsub
    4298             :   0x00400000, 0x0000000c, // dsub1_then_hsub
    4299             :   0x00000000, 0x00000008, // dsub3_then_hsub
    4300             :   0x00000000, 0x0000000c, // dsub2_then_hsub
    4301             :   0x00000000, 0x03fffff0, // qsub1_then_hsub
    4302             :   0x00000000, 0x03ff8000, // qsub3_then_hsub
    4303             :   0x00000000, 0x03ffff00, // qsub2_then_hsub
    4304             : };
    4305             : 
    4306             : static const uint32_t PPRSubClassMask[] = {
    4307             :   0x0000000c, 0x00000000, 
    4308             : };
    4309             : 
    4310             : static const uint32_t PPR_3bSubClassMask[] = {
    4311             :   0x00000008, 0x00000000, 
    4312             : };
    4313             : 
    4314             : static const uint32_t GPR32allSubClassMask[] = {
    4315             :   0x000005d0, 0x00000000, 
    4316             :   0x3fbe8000, 0x00000000, // sub_32
    4317             :   0x00007800, 0x00000000, // sube32
    4318             :   0x00007800, 0x00000000, // subo32
    4319             :   0x3f800000, 0x00000000, // subo64_then_sub_32
    4320             : };
    4321             : 
    4322             : static const uint32_t FPR32SubClassMask[] = {
    4323             :   0x00000020, 0x00000000, 
    4324             :   0xc0410000, 0x03ffffff, // ssub
    4325             :   0x00400000, 0x0000000c, // dsub1_then_ssub
    4326             :   0x00000000, 0x00000008, // dsub3_then_ssub
    4327             :   0x00000000, 0x0000000c, // dsub2_then_ssub
    4328             :   0x00000000, 0x03fffff0, // qsub1_then_ssub
    4329             :   0x00000000, 0x03ff8000, // qsub3_then_ssub
    4330             :   0x00000000, 0x03ffff00, // qsub2_then_ssub
    4331             : };
    4332             : 
    4333             : static const uint32_t GPR32SubClassMask[] = {
    4334             :   0x00000140, 0x00000000, 
    4335             :   0x3f9a0000, 0x00000000, // sub_32
    4336             :   0x00007800, 0x00000000, // sube32
    4337             :   0x00007800, 0x00000000, // subo32
    4338             :   0x3f800000, 0x00000000, // subo64_then_sub_32
    4339             : };
    4340             : 
    4341             : static const uint32_t GPR32spSubClassMask[] = {
    4342             :   0x00000580, 0x00000000, 
    4343             :   0x2d3c0000, 0x00000000, // sub_32
    4344             :   0x00005000, 0x00000000, // sube32
    4345             :   0x00006000, 0x00000000, // subo32
    4346             :   0x3e000000, 0x00000000, // subo64_then_sub_32
    4347             : };
    4348             : 
    4349             : static const uint32_t GPR32commonSubClassMask[] = {
    4350             :   0x00000100, 0x00000000, 
    4351             :   0x2d180000, 0x00000000, // sub_32
    4352             :   0x00005000, 0x00000000, // sube32
    4353             :   0x00006000, 0x00000000, // subo32
    4354             :   0x3e000000, 0x00000000, // subo64_then_sub_32
    4355             : };
    4356             : 
    4357             : static const uint32_t CCRSubClassMask[] = {
    4358             :   0x00000200, 0x00000000, 
    4359             : };
    4360             : 
    4361             : static const uint32_t GPR32sponlySubClassMask[] = {
    4362             :   0x00000400, 0x00000000, 
    4363             :   0x00200000, 0x00000000, // sub_32
    4364             : };
    4365             : 
    4366             : static const uint32_t WSeqPairsClassSubClassMask[] = {
    4367             :   0x00007800, 0x00000000, 
    4368             :   0x3f800000, 0x00000000, // sub_32_subo64_then_sub_32
    4369             : };
    4370             : 
    4371             : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask[] = {
    4372             :   0x00005000, 0x00000000, 
    4373             :   0x2d000000, 0x00000000, // sub_32_subo64_then_sub_32
    4374             : };
    4375             : 
    4376             : static const uint32_t WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
    4377             :   0x00006000, 0x00000000, 
    4378             :   0x3e000000, 0x00000000, // sub_32_subo64_then_sub_32
    4379             : };
    4380             : 
    4381             : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
    4382             :   0x00004000, 0x00000000, 
    4383             :   0x2c000000, 0x00000000, // sub_32_subo64_then_sub_32
    4384             : };
    4385             : 
    4386             : static const uint32_t GPR64allSubClassMask[] = {
    4387             :   0x003e8000, 0x00000000, 
    4388             :   0x3f800000, 0x00000000, // sube64
    4389             :   0x3f800000, 0x00000000, // subo64
    4390             : };
    4391             : 
    4392             : static const uint32_t FPR64SubClassMask[] = {
    4393             :   0x00010000, 0x00000000, 
    4394             :   0xc0000000, 0x03fffff3, // dsub
    4395             :   0x00400000, 0x0000000c, // dsub0
    4396             :   0x00400000, 0x0000000c, // dsub1
    4397             :   0x00000000, 0x0000000c, // dsub2
    4398             :   0x00000000, 0x00000008, // dsub3
    4399             :   0x00000000, 0x03fffff0, // qsub1_then_dsub
    4400             :   0x00000000, 0x03ff8000, // qsub3_then_dsub
    4401             :   0x00000000, 0x03ffff00, // qsub2_then_dsub
    4402             : };
    4403             : 
    4404             : static const uint32_t GPR64SubClassMask[] = {
    4405             :   0x001a0000, 0x00000000, 
    4406             :   0x3f800000, 0x00000000, // sube64
    4407             :   0x3f800000, 0x00000000, // subo64
    4408             : };
    4409             : 
    4410             : static const uint32_t GPR64spSubClassMask[] = {
    4411             :   0x003c0000, 0x00000000, 
    4412             :   0x2d000000, 0x00000000, // sube64
    4413             :   0x3e000000, 0x00000000, // subo64
    4414             : };
    4415             : 
    4416             : static const uint32_t GPR64commonSubClassMask[] = {
    4417             :   0x00180000, 0x00000000, 
    4418             :   0x2d000000, 0x00000000, // sube64
    4419             :   0x3e000000, 0x00000000, // subo64
    4420             : };
    4421             : 
    4422             : static const uint32_t tcGPR64SubClassMask[] = {
    4423             :   0x00100000, 0x00000000, 
    4424             :   0x28000000, 0x00000000, // sube64
    4425             :   0x30000000, 0x00000000, // subo64
    4426             : };
    4427             : 
    4428             : static const uint32_t GPR64sponlySubClassMask[] = {
    4429             :   0x00200000, 0x00000000, 
    4430             : };
    4431             : 
    4432             : static const uint32_t DDSubClassMask[] = {
    4433             :   0x00400000, 0x00000000, 
    4434             :   0x00000000, 0x0000000c, // dsub0_dsub1
    4435             :   0x00000000, 0x0000000c, // dsub1_dsub2
    4436             :   0x00000000, 0x00000008, // dsub2_dsub3
    4437             :   0x00000000, 0x03fffff0, // dsub_qsub1_then_dsub
    4438             :   0x00000000, 0x03ffff00, // qsub1_then_dsub_qsub2_then_dsub
    4439             :   0x00000000, 0x03ff8000, // qsub2_then_dsub_qsub3_then_dsub
    4440             : };
    4441             : 
    4442             : static const uint32_t XSeqPairsClassSubClassMask[] = {
    4443             :   0x3f800000, 0x00000000, 
    4444             : };
    4445             : 
    4446             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask[] = {
    4447             :   0x2d000000, 0x00000000, 
    4448             : };
    4449             : 
    4450             : static const uint32_t XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
    4451             :   0x3e000000, 0x00000000, 
    4452             : };
    4453             : 
    4454             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
    4455             :   0x2c000000, 0x00000000, 
    4456             : };
    4457             : 
    4458             : static const uint32_t XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask[] = {
    4459             :   0x28000000, 0x00000000, 
    4460             : };
    4461             : 
    4462             : static const uint32_t XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
    4463             :   0x30000000, 0x00000000, 
    4464             : };
    4465             : 
    4466             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
    4467             :   0x20000000, 0x00000000, 
    4468             : };
    4469             : 
    4470             : static const uint32_t FPR128SubClassMask[] = {
    4471             :   0x40000000, 0x00000001, 
    4472             :   0x00000000, 0x03fffff0, // qsub0
    4473             :   0x00000000, 0x03fffff0, // qsub1
    4474             :   0x00000000, 0x03ffff00, // qsub2
    4475             :   0x00000000, 0x03ff8000, // qsub3
    4476             :   0x80000000, 0x00000002, // zsub
    4477             : };
    4478             : 
    4479             : static const uint32_t ZPRSubClassMask[] = {
    4480             :   0x80000000, 0x00000002, 
    4481             : };
    4482             : 
    4483             : static const uint32_t FPR128_loSubClassMask[] = {
    4484             :   0x00000000, 0x00000001, 
    4485             :   0x00000000, 0x029152a0, // qsub0
    4486             :   0x00000000, 0x03b274c0, // qsub1
    4487             :   0x00000000, 0x03e46800, // qsub2
    4488             :   0x00000000, 0x03480000, // qsub3
    4489             :   0x00000000, 0x00000002, // zsub
    4490             : };
    4491             : 
    4492             : static const uint32_t ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    4493             :   0x00000000, 0x00000002, 
    4494             : };
    4495             : 
    4496             : static const uint32_t DDDSubClassMask[] = {
    4497             :   0x00000000, 0x00000004, 
    4498             :   0x00000000, 0x00000008, // dsub0_dsub1_dsub2
    4499             :   0x00000000, 0x00000008, // dsub1_dsub2_dsub3
    4500             :   0x00000000, 0x03ffff00, // dsub_qsub1_then_dsub_qsub2_then_dsub
    4501             :   0x00000000, 0x03ff8000, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    4502             : };
    4503             : 
    4504             : static const uint32_t DDDDSubClassMask[] = {
    4505             :   0x00000000, 0x00000008, 
    4506             :   0x00000000, 0x03ff8000, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    4507             : };
    4508             : 
    4509             : static const uint32_t QQSubClassMask[] = {
    4510             :   0x00000000, 0x000000f0, 
    4511             :   0x00000000, 0x03ffff00, // qsub0_qsub1
    4512             :   0x00000000, 0x03ffff00, // qsub1_qsub2
    4513             :   0x00000000, 0x03ff8000, // qsub2_qsub3
    4514             : };
    4515             : 
    4516             : static const uint32_t QQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    4517             :   0x00000000, 0x000000a0, 
    4518             :   0x00000000, 0x02915200, // qsub0_qsub1
    4519             :   0x00000000, 0x03b27400, // qsub1_qsub2
    4520             :   0x00000000, 0x03e40000, // qsub2_qsub3
    4521             : };
    4522             : 
    4523             : static const uint32_t QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    4524             :   0x00000000, 0x000000c0, 
    4525             :   0x00000000, 0x03b27400, // qsub0_qsub1
    4526             :   0x00000000, 0x03e46800, // qsub1_qsub2
    4527             :   0x00000000, 0x03480000, // qsub2_qsub3
    4528             : };
    4529             : 
    4530             : static const uint32_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    4531             :   0x00000000, 0x00000080, 
    4532             :   0x00000000, 0x02905000, // qsub0_qsub1
    4533             :   0x00000000, 0x03a06000, // qsub1_qsub2
    4534             :   0x00000000, 0x03400000, // qsub2_qsub3
    4535             : };
    4536             : 
    4537             : static const uint32_t QQQSubClassMask[] = {
    4538             :   0x00000000, 0x00007f00, 
    4539             :   0x00000000, 0x03ff8000, // qsub0_qsub1_qsub2
    4540             :   0x00000000, 0x03ff8000, // qsub1_qsub2_qsub3
    4541             : };
    4542             : 
    4543             : static const uint32_t QQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    4544             :   0x00000000, 0x00005200, 
    4545             :   0x00000000, 0x02910000, // qsub0_qsub1_qsub2
    4546             :   0x00000000, 0x03b20000, // qsub1_qsub2_qsub3
    4547             : };
    4548             : 
    4549             : static const uint32_t QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    4550             :   0x00000000, 0x00007400, 
    4551             :   0x00000000, 0x03b20000, // qsub0_qsub1_qsub2
    4552             :   0x00000000, 0x03e40000, // qsub1_qsub2_qsub3
    4553             : };
    4554             : 
    4555             : static const uint32_t QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    4556             :   0x00000000, 0x00006800, 
    4557             :   0x00000000, 0x03e40000, // qsub0_qsub1_qsub2
    4558             :   0x00000000, 0x03480000, // qsub1_qsub2_qsub3
    4559             : };
    4560             : 
    4561             : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    4562             :   0x00000000, 0x00005000, 
    4563             :   0x00000000, 0x02900000, // qsub0_qsub1_qsub2
    4564             :   0x00000000, 0x03a00000, // qsub1_qsub2_qsub3
    4565             : };
    4566             : 
    4567             : static const uint32_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    4568             :   0x00000000, 0x00006000, 
    4569             :   0x00000000, 0x03a00000, // qsub0_qsub1_qsub2
    4570             :   0x00000000, 0x03400000, // qsub1_qsub2_qsub3
    4571             : };
    4572             : 
    4573             : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    4574             :   0x00000000, 0x00004000, 
    4575             :   0x00000000, 0x02800000, // qsub0_qsub1_qsub2
    4576             :   0x00000000, 0x03000000, // qsub1_qsub2_qsub3
    4577             : };
    4578             : 
    4579             : static const uint32_t QQQQSubClassMask[] = {
    4580             :   0x00000000, 0x03ff8000, 
    4581             : };
    4582             : 
    4583             : static const uint32_t QQQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    4584             :   0x00000000, 0x02910000, 
    4585             : };
    4586             : 
    4587             : static const uint32_t QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    4588             :   0x00000000, 0x03b20000, 
    4589             : };
    4590             : 
    4591             : static const uint32_t QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    4592             :   0x00000000, 0x03e40000, 
    4593             : };
    4594             : 
    4595             : static const uint32_t QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    4596             :   0x00000000, 0x03480000, 
    4597             : };
    4598             : 
    4599             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    4600             :   0x00000000, 0x02900000, 
    4601             : };
    4602             : 
    4603             : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    4604             :   0x00000000, 0x03a00000, 
    4605             : };
    4606             : 
    4607             : static const uint32_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    4608             :   0x00000000, 0x03400000, 
    4609             : };
    4610             : 
    4611             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    4612             :   0x00000000, 0x02800000, 
    4613             : };
    4614             : 
    4615             : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    4616             :   0x00000000, 0x03000000, 
    4617             : };
    4618             : 
    4619             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    4620             :   0x00000000, 0x02000000, 
    4621             : };
    4622             : 
    4623             : static const uint16_t SuperRegIdxSeqs[] = {
    4624             :   /* 0 */ 15, 0,
    4625             :   /* 2 */ 17, 19, 0,
    4626             :   /* 5 */ 10, 11, 12, 13, 20, 0,
    4627             :   /* 11 */ 1, 22, 25, 28, 31, 35, 39, 0,
    4628             :   /* 19 */ 2, 3, 4, 5, 6, 32, 36, 40, 0,
    4629             :   /* 28 */ 7, 23, 26, 29, 33, 37, 41, 0,
    4630             :   /* 36 */ 14, 24, 27, 30, 34, 38, 42, 0,
    4631             :   /* 44 */ 15, 16, 18, 43, 0,
    4632             :   /* 49 */ 50, 0,
    4633             :   /* 51 */ 53, 55, 0,
    4634             :   /* 54 */ 52, 54, 56, 0,
    4635             :   /* 58 */ 45, 47, 51, 58, 0,
    4636             :   /* 63 */ 44, 46, 48, 49, 57, 59, 0,
    4637             :   /* 70 */ 60, 0,
    4638             : };
    4639             : 
    4640             : static const TargetRegisterClass *const PPR_3bSuperclasses[] = {
    4641             :   &AArch64::PPRRegClass,
    4642             :   nullptr
    4643             : };
    4644             : 
    4645             : static const TargetRegisterClass *const GPR32Superclasses[] = {
    4646             :   &AArch64::GPR32allRegClass,
    4647             :   nullptr
    4648             : };
    4649             : 
    4650             : static const TargetRegisterClass *const GPR32spSuperclasses[] = {
    4651             :   &AArch64::GPR32allRegClass,
    4652             :   nullptr
    4653             : };
    4654             : 
    4655             : static const TargetRegisterClass *const GPR32commonSuperclasses[] = {
    4656             :   &AArch64::GPR32allRegClass,
    4657             :   &AArch64::GPR32RegClass,
    4658             :   &AArch64::GPR32spRegClass,
    4659             :   nullptr
    4660             : };
    4661             : 
    4662             : static const TargetRegisterClass *const GPR32sponlySuperclasses[] = {
    4663             :   &AArch64::GPR32allRegClass,
    4664             :   &AArch64::GPR32spRegClass,
    4665             :   nullptr
    4666             : };
    4667             : 
    4668             : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses[] = {
    4669             :   &AArch64::WSeqPairsClassRegClass,
    4670             :   nullptr
    4671             : };
    4672             : 
    4673             : static const TargetRegisterClass *const WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
    4674             :   &AArch64::WSeqPairsClassRegClass,
    4675             :   nullptr
    4676             : };
    4677             : 
    4678             : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
    4679             :   &AArch64::WSeqPairsClassRegClass,
    4680             :   &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
    4681             :   &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    4682             :   nullptr
    4683             : };
    4684             : 
    4685             : static const TargetRegisterClass *const GPR64Superclasses[] = {
    4686             :   &AArch64::GPR64allRegClass,
    4687             :   nullptr
    4688             : };
    4689             : 
    4690             : static const TargetRegisterClass *const GPR64spSuperclasses[] = {
    4691             :   &AArch64::GPR64allRegClass,
    4692             :   nullptr
    4693             : };
    4694             : 
    4695             : static const TargetRegisterClass *const GPR64commonSuperclasses[] = {
    4696             :   &AArch64::GPR64allRegClass,
    4697             :   &AArch64::GPR64RegClass,
    4698             :   &AArch64::GPR64spRegClass,
    4699             :   nullptr
    4700             : };
    4701             : 
    4702             : static const TargetRegisterClass *const tcGPR64Superclasses[] = {
    4703             :   &AArch64::GPR64allRegClass,
    4704             :   &AArch64::GPR64RegClass,
    4705             :   &AArch64::GPR64spRegClass,
    4706             :   &AArch64::GPR64commonRegClass,
    4707             :   nullptr
    4708             : };
    4709             : 
    4710             : static const TargetRegisterClass *const GPR64sponlySuperclasses[] = {
    4711             :   &AArch64::GPR64allRegClass,
    4712             :   &AArch64::GPR64spRegClass,
    4713             :   nullptr
    4714             : };
    4715             : 
    4716             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses[] = {
    4717             :   &AArch64::XSeqPairsClassRegClass,
    4718             :   nullptr
    4719             : };
    4720             : 
    4721             : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
    4722             :   &AArch64::XSeqPairsClassRegClass,
    4723             :   nullptr
    4724             : };
    4725             : 
    4726             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
    4727             :   &AArch64::XSeqPairsClassRegClass,
    4728             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    4729             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4730             :   nullptr
    4731             : };
    4732             : 
    4733             : static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_tcGPR64Superclasses[] = {
    4734             :   &AArch64::XSeqPairsClassRegClass,
    4735             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    4736             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4737             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4738             :   nullptr
    4739             : };
    4740             : 
    4741             : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
    4742             :   &AArch64::XSeqPairsClassRegClass,
    4743             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4744             :   nullptr
    4745             : };
    4746             : 
    4747             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
    4748             :   &AArch64::XSeqPairsClassRegClass,
    4749             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    4750             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4751             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    4752             :   &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
    4753             :   &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    4754             :   nullptr
    4755             : };
    4756             : 
    4757             : static const TargetRegisterClass *const FPR128_loSuperclasses[] = {
    4758             :   &AArch64::FPR128RegClass,
    4759             :   nullptr
    4760             : };
    4761             : 
    4762             : static const TargetRegisterClass *const ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    4763             :   &AArch64::ZPRRegClass,
    4764             :   nullptr
    4765             : };
    4766             : 
    4767             : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    4768             :   &AArch64::QQRegClass,
    4769             :   nullptr
    4770             : };
    4771             : 
    4772             : static const TargetRegisterClass *const QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4773             :   &AArch64::QQRegClass,
    4774             :   nullptr
    4775             : };
    4776             : 
    4777             : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4778             :   &AArch64::QQRegClass,
    4779             :   &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
    4780             :   &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
    4781             :   nullptr
    4782             : };
    4783             : 
    4784             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    4785             :   &AArch64::QQQRegClass,
    4786             :   nullptr
    4787             : };
    4788             : 
    4789             : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4790             :   &AArch64::QQQRegClass,
    4791             :   nullptr
    4792             : };
    4793             : 
    4794             : static const TargetRegisterClass *const QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4795             :   &AArch64::QQQRegClass,
    4796             :   nullptr
    4797             : };
    4798             : 
    4799             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4800             :   &AArch64::QQQRegClass,
    4801             :   &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    4802             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    4803             :   nullptr
    4804             : };
    4805             : 
    4806             : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4807             :   &AArch64::QQQRegClass,
    4808             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    4809             :   &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    4810             :   nullptr
    4811             : };
    4812             : 
    4813             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4814             :   &AArch64::QQQRegClass,
    4815             :   &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    4816             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    4817             :   &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    4818             :   &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
    4819             :   &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    4820             :   nullptr
    4821             : };
    4822             : 
    4823             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    4824             :   &AArch64::QQQQRegClass,
    4825             :   nullptr
    4826             : };
    4827             : 
    4828             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4829             :   &AArch64::QQQQRegClass,
    4830             :   nullptr
    4831             : };
    4832             : 
    4833             : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4834             :   &AArch64::QQQQRegClass,
    4835             :   nullptr
    4836             : };
    4837             : 
    4838             : static const TargetRegisterClass *const QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    4839             :   &AArch64::QQQQRegClass,
    4840             :   nullptr
    4841             : };
    4842             : 
    4843             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    4844             :   &AArch64::QQQQRegClass,
    4845             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    4846             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4847             :   nullptr
    4848             : };
    4849             : 
    4850             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4851             :   &AArch64::QQQQRegClass,
    4852             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4853             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4854             :   nullptr
    4855             : };
    4856             : 
    4857             : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    4858             :   &AArch64::QQQQRegClass,
    4859             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4860             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    4861             :   nullptr
    4862             : };
    4863             : 
    4864             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    4865             :   &AArch64::QQQQRegClass,
    4866             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    4867             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4868             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4869             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    4870             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    4871             :   nullptr
    4872             : };
    4873             : 
    4874             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    4875             :   &AArch64::QQQQRegClass,
    4876             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4877             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4878             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    4879             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    4880             :   &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    4881             :   nullptr
    4882             : };
    4883             : 
    4884             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    4885             :   &AArch64::QQQQRegClass,
    4886             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    4887             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    4888             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    4889             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    4890             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    4891             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    4892             :   &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    4893             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    4894             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    4895             :   nullptr
    4896             : };
    4897             : 
    4898             : 
    4899             : static inline unsigned GPR32AltOrderSelect(const MachineFunction &MF) { return 1; }
    4900             : 
    4901         531 : static ArrayRef<MCPhysReg> GPR32GetRawAllocationOrder(const MachineFunction &MF) {
    4902             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    4903             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
    4904             :   const ArrayRef<MCPhysReg> Order[] = {
    4905             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4906             :     makeArrayRef(AltOrder1)
    4907             :   };
    4908             :   const unsigned Select = GPR32AltOrderSelect(MF);
    4909             :   assert(Select < 2);
    4910         531 :   return Order[Select];
    4911             : }
    4912             : 
    4913             : static inline unsigned GPR32spAltOrderSelect(const MachineFunction &MF) { return 1; }
    4914             : 
    4915          86 : static ArrayRef<MCPhysReg> GPR32spGetRawAllocationOrder(const MachineFunction &MF) {
    4916             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    4917             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
    4918             :   const ArrayRef<MCPhysReg> Order[] = {
    4919             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4920             :     makeArrayRef(AltOrder1)
    4921             :   };
    4922             :   const unsigned Select = GPR32spAltOrderSelect(MF);
    4923             :   assert(Select < 2);
    4924          86 :   return Order[Select];
    4925             : }
    4926             : 
    4927             : static inline unsigned GPR32commonAltOrderSelect(const MachineFunction &MF) { return 1; }
    4928             : 
    4929         216 : static ArrayRef<MCPhysReg> GPR32commonGetRawAllocationOrder(const MachineFunction &MF) {
    4930             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    4931             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];
    4932             :   const ArrayRef<MCPhysReg> Order[] = {
    4933             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4934             :     makeArrayRef(AltOrder1)
    4935             :   };
    4936             :   const unsigned Select = GPR32commonAltOrderSelect(MF);
    4937             :   assert(Select < 2);
    4938         216 :   return Order[Select];
    4939             : }
    4940             : 
    4941             : static inline unsigned GPR64AltOrderSelect(const MachineFunction &MF) { return 1; }
    4942             : 
    4943         722 : static ArrayRef<MCPhysReg> GPR64GetRawAllocationOrder(const MachineFunction &MF) {
    4944             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    4945             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
    4946             :   const ArrayRef<MCPhysReg> Order[] = {
    4947             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4948             :     makeArrayRef(AltOrder1)
    4949             :   };
    4950             :   const unsigned Select = GPR64AltOrderSelect(MF);
    4951             :   assert(Select < 2);
    4952         722 :   return Order[Select];
    4953             : }
    4954             : 
    4955             : static inline unsigned GPR64spAltOrderSelect(const MachineFunction &MF) { return 1; }
    4956             : 
    4957         164 : static ArrayRef<MCPhysReg> GPR64spGetRawAllocationOrder(const MachineFunction &MF) {
    4958             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    4959             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];
    4960             :   const ArrayRef<MCPhysReg> Order[] = {
    4961             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4962             :     makeArrayRef(AltOrder1)
    4963             :   };
    4964             :   const unsigned Select = GPR64spAltOrderSelect(MF);
    4965             :   assert(Select < 2);
    4966         164 :   return Order[Select];
    4967             : }
    4968             : 
    4969             : static inline unsigned GPR64commonAltOrderSelect(const MachineFunction &MF) { return 1; }
    4970             : 
    4971         717 : static ArrayRef<MCPhysReg> GPR64commonGetRawAllocationOrder(const MachineFunction &MF) {
    4972             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    4973             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID];
    4974             :   const ArrayRef<MCPhysReg> Order[] = {
    4975             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    4976             :     makeArrayRef(AltOrder1)
    4977             :   };
    4978             :   const unsigned Select = GPR64commonAltOrderSelect(MF);
    4979             :   assert(Select < 2);
    4980         717 :   return Order[Select];
    4981             : }
    4982             : 
    4983             : namespace AArch64 {   // Register class instances
    4984             :   extern const TargetRegisterClass FPR8RegClass = {
    4985             :     &AArch64MCRegisterClasses[FPR8RegClassID],
    4986             :     FPR8SubClassMask,
    4987             :     SuperRegIdxSeqs + 11,
    4988             :     LaneBitmask(0x00000001),
    4989             :     0,
    4990             :     false, /* HasDisjunctSubRegs */
    4991             :     false, /* CoveredBySubRegs */
    4992             :     NullRegClasses,
    4993             :     nullptr
    4994             :   };
    4995             : 
    4996             :   extern const TargetRegisterClass FPR16RegClass = {
    4997             :     &AArch64MCRegisterClasses[FPR16RegClassID],
    4998             :     FPR16SubClassMask,
    4999             :     SuperRegIdxSeqs + 28,
    5000             :     LaneBitmask(0x00000001),
    5001             :     0,
    5002             :     false, /* HasDisjunctSubRegs */
    5003             :     false, /* CoveredBySubRegs */
    5004             :     NullRegClasses,
    5005             :     nullptr
    5006             :   };
    5007             : 
    5008             :   extern const TargetRegisterClass PPRRegClass = {
    5009             :     &AArch64MCRegisterClasses[PPRRegClassID],
    5010             :     PPRSubClassMask,
    5011             :     SuperRegIdxSeqs + 1,
    5012             :     LaneBitmask(0x00000001),
    5013             :     0,
    5014             :     false, /* HasDisjunctSubRegs */
    5015             :     false, /* CoveredBySubRegs */
    5016             :     NullRegClasses,
    5017             :     nullptr
    5018             :   };
    5019             : 
    5020             :   extern const TargetRegisterClass PPR_3bRegClass = {
    5021             :     &AArch64MCRegisterClasses[PPR_3bRegClassID],
    5022             :     PPR_3bSubClassMask,
    5023             :     SuperRegIdxSeqs + 1,
    5024             :     LaneBitmask(0x00000001),
    5025             :     0,
    5026             :     false, /* HasDisjunctSubRegs */
    5027             :     false, /* CoveredBySubRegs */
    5028             :     PPR_3bSuperclasses,
    5029             :     nullptr
    5030             :   };
    5031             : 
    5032             :   extern const TargetRegisterClass GPR32allRegClass = {
    5033             :     &AArch64MCRegisterClasses[GPR32allRegClassID],
    5034             :     GPR32allSubClassMask,
    5035             :     SuperRegIdxSeqs + 44,
    5036             :     LaneBitmask(0x00000001),
    5037             :     0,
    5038             :     false, /* HasDisjunctSubRegs */
    5039             :     false, /* CoveredBySubRegs */
    5040             :     NullRegClasses,
    5041             :     nullptr
    5042             :   };
    5043             : 
    5044             :   extern const TargetRegisterClass FPR32RegClass = {
    5045             :     &AArch64MCRegisterClasses[FPR32RegClassID],
    5046             :     FPR32SubClassMask,
    5047             :     SuperRegIdxSeqs + 36,
    5048             :     LaneBitmask(0x00000001),
    5049             :     0,
    5050             :     false, /* HasDisjunctSubRegs */
    5051             :     false, /* CoveredBySubRegs */
    5052             :     NullRegClasses,
    5053             :     nullptr
    5054             :   };
    5055             : 
    5056             :   extern const TargetRegisterClass GPR32RegClass = {
    5057             :     &AArch64MCRegisterClasses[GPR32RegClassID],
    5058             :     GPR32SubClassMask,
    5059             :     SuperRegIdxSeqs + 44,
    5060             :     LaneBitmask(0x00000001),
    5061             :     0,
    5062             :     false, /* HasDisjunctSubRegs */
    5063             :     false, /* CoveredBySubRegs */
    5064             :     GPR32Superclasses,
    5065             :     GPR32GetRawAllocationOrder
    5066             :   };
    5067             : 
    5068             :   extern const TargetRegisterClass GPR32spRegClass = {
    5069             :     &AArch64MCRegisterClasses[GPR32spRegClassID],
    5070             :     GPR32spSubClassMask,
    5071             :     SuperRegIdxSeqs + 44,
    5072             :     LaneBitmask(0x00000001),
    5073             :     0,
    5074             :     false, /* HasDisjunctSubRegs */
    5075             :     false, /* CoveredBySubRegs */
    5076             :     GPR32spSuperclasses,
    5077             :     GPR32spGetRawAllocationOrder
    5078             :   };
    5079             : 
    5080             :   extern const TargetRegisterClass GPR32commonRegClass = {
    5081             :     &AArch64MCRegisterClasses[GPR32commonRegClassID],
    5082             :     GPR32commonSubClassMask,
    5083             :     SuperRegIdxSeqs + 44,
    5084             :     LaneBitmask(0x00000001),
    5085             :     0,
    5086             :     false, /* HasDisjunctSubRegs */
    5087             :     false, /* CoveredBySubRegs */
    5088             :     GPR32commonSuperclasses,
    5089             :     GPR32commonGetRawAllocationOrder
    5090             :   };
    5091             : 
    5092             :   extern const TargetRegisterClass CCRRegClass = {
    5093             :     &AArch64MCRegisterClasses[CCRRegClassID],
    5094             :     CCRSubClassMask,
    5095             :     SuperRegIdxSeqs + 1,
    5096             :     LaneBitmask(0x00000001),
    5097             :     0,
    5098             :     false, /* HasDisjunctSubRegs */
    5099             :     false, /* CoveredBySubRegs */
    5100             :     NullRegClasses,
    5101             :     nullptr
    5102             :   };
    5103             : 
    5104             :   extern const TargetRegisterClass GPR32sponlyRegClass = {
    5105             :     &AArch64MCRegisterClasses[GPR32sponlyRegClassID],
    5106             :     GPR32sponlySubClassMask,
    5107             :     SuperRegIdxSeqs + 0,
    5108             :     LaneBitmask(0x00000001),
    5109             :     0,
    5110             :     false, /* HasDisjunctSubRegs */
    5111             :     false, /* CoveredBySubRegs */
    5112             :     GPR32sponlySuperclasses,
    5113             :     nullptr
    5114             :   };
    5115             : 
    5116             :   extern const TargetRegisterClass WSeqPairsClassRegClass = {
    5117             :     &AArch64MCRegisterClasses[WSeqPairsClassRegClassID],
    5118             :     WSeqPairsClassSubClassMask,
    5119             :     SuperRegIdxSeqs + 70,
    5120             :     LaneBitmask(0x00000030),
    5121             :     0,
    5122             :     true, /* HasDisjunctSubRegs */
    5123             :     true, /* CoveredBySubRegs */
    5124             :     NullRegClasses,
    5125             :     nullptr
    5126             :   };
    5127             : 
    5128             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass = {
    5129             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32commonRegClassID],
    5130             :     WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask,
    5131             :     SuperRegIdxSeqs + 70,
    5132             :     LaneBitmask(0x00000030),
    5133             :     0,
    5134             :     true, /* HasDisjunctSubRegs */
    5135             :     true, /* CoveredBySubRegs */
    5136             :     WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses,
    5137             :     nullptr
    5138             :   };
    5139             : 
    5140             :   extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
    5141             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
    5142             :     WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
    5143             :     SuperRegIdxSeqs + 70,
    5144             :     LaneBitmask(0x00000030),
    5145             :     0,
    5146             :     true, /* HasDisjunctSubRegs */
    5147             :     true, /* CoveredBySubRegs */
    5148             :     WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
    5149             :     nullptr
    5150             :   };
    5151             : 
    5152             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
    5153             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
    5154             :     WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
    5155             :     SuperRegIdxSeqs + 70,
    5156             :     LaneBitmask(0x00000030),
    5157             :     0,
    5158             :     true, /* HasDisjunctSubRegs */
    5159             :     true, /* CoveredBySubRegs */
    5160             :     WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
    5161             :     nullptr
    5162             :   };
    5163             : 
    5164             :   extern const TargetRegisterClass GPR64allRegClass = {
    5165             :     &AArch64MCRegisterClasses[GPR64allRegClassID],
    5166             :     GPR64allSubClassMask,
    5167             :     SuperRegIdxSeqs + 2,
    5168             :     LaneBitmask(0x00000008),
    5169             :     0,
    5170             :     false, /* HasDisjunctSubRegs */
    5171             :     false, /* CoveredBySubRegs */
    5172             :     NullRegClasses,
    5173             :     nullptr
    5174             :   };
    5175             : 
    5176             :   extern const TargetRegisterClass FPR64RegClass = {
    5177             :     &AArch64MCRegisterClasses[FPR64RegClassID],
    5178             :     FPR64SubClassMask,
    5179             :     SuperRegIdxSeqs + 19,
    5180             :     LaneBitmask(0x00000001),
    5181             :     0,
    5182             :     false, /* HasDisjunctSubRegs */
    5183             :     false, /* CoveredBySubRegs */
    5184             :     NullRegClasses,
    5185             :     nullptr
    5186             :   };
    5187             : 
    5188             :   extern const TargetRegisterClass GPR64RegClass = {
    5189             :     &AArch64MCRegisterClasses[GPR64RegClassID],
    5190             :     GPR64SubClassMask,
    5191             :     SuperRegIdxSeqs + 2,
    5192             :     LaneBitmask(0x00000008),
    5193             :     0,
    5194             :     false, /* HasDisjunctSubRegs */
    5195             :     false, /* CoveredBySubRegs */
    5196             :     GPR64Superclasses,
    5197             :     GPR64GetRawAllocationOrder
    5198             :   };
    5199             : 
    5200             :   extern const TargetRegisterClass GPR64spRegClass = {
    5201             :     &AArch64MCRegisterClasses[GPR64spRegClassID],
    5202             :     GPR64spSubClassMask,
    5203             :     SuperRegIdxSeqs + 2,
    5204             :     LaneBitmask(0x00000008),
    5205             :     0,
    5206             :     false, /* HasDisjunctSubRegs */
    5207             :     false, /* CoveredBySubRegs */
    5208             :     GPR64spSuperclasses,
    5209             :     GPR64spGetRawAllocationOrder
    5210             :   };
    5211             : 
    5212             :   extern const TargetRegisterClass GPR64commonRegClass = {
    5213             :     &AArch64MCRegisterClasses[GPR64commonRegClassID],
    5214             :     GPR64commonSubClassMask,
    5215             :     SuperRegIdxSeqs + 2,
    5216             :     LaneBitmask(0x00000008),
    5217             :     0,
    5218             :     false, /* HasDisjunctSubRegs */
    5219             :     false, /* CoveredBySubRegs */
    5220             :     GPR64commonSuperclasses,
    5221             :     GPR64commonGetRawAllocationOrder
    5222             :   };
    5223             : 
    5224             :   extern const TargetRegisterClass tcGPR64RegClass = {
    5225             :     &AArch64MCRegisterClasses[tcGPR64RegClassID],
    5226             :     tcGPR64SubClassMask,
    5227             :     SuperRegIdxSeqs + 2,
    5228             :     LaneBitmask(0x00000008),
    5229             :     0,
    5230             :     false, /* HasDisjunctSubRegs */
    5231             :     false, /* CoveredBySubRegs */
    5232             :     tcGPR64Superclasses,
    5233             :     nullptr
    5234             :   };
    5235             : 
    5236             :   extern const TargetRegisterClass GPR64sponlyRegClass = {
    5237             :     &AArch64MCRegisterClasses[GPR64sponlyRegClassID],
    5238             :     GPR64sponlySubClassMask,
    5239             :     SuperRegIdxSeqs + 1,
    5240             :     LaneBitmask(0x00000008),
    5241             :     0,
    5242             :     false, /* HasDisjunctSubRegs */
    5243             :     false, /* CoveredBySubRegs */
    5244             :     GPR64sponlySuperclasses,
    5245             :     nullptr
    5246             :   };
    5247             : 
    5248             :   extern const TargetRegisterClass DDRegClass = {
    5249             :     &AArch64MCRegisterClasses[DDRegClassID],
    5250             :     DDSubClassMask,
    5251             :     SuperRegIdxSeqs + 63,
    5252             :     LaneBitmask(0x00000081),
    5253             :     0,
    5254             :     true, /* HasDisjunctSubRegs */
    5255             :     true, /* CoveredBySubRegs */
    5256             :     NullRegClasses,
    5257             :     nullptr
    5258             :   };
    5259             : 
    5260             :   extern const TargetRegisterClass XSeqPairsClassRegClass = {
    5261             :     &AArch64MCRegisterClasses[XSeqPairsClassRegClassID],
    5262             :     XSeqPairsClassSubClassMask,
    5263             :     SuperRegIdxSeqs + 1,
    5264             :     LaneBitmask(0x00002008),
    5265             :     0,
    5266             :     true, /* HasDisjunctSubRegs */
    5267             :     true, /* CoveredBySubRegs */
    5268             :     NullRegClasses,
    5269             :     nullptr
    5270             :   };
    5271             : 
    5272             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass = {
    5273             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID],
    5274             :     XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask,
    5275             :     SuperRegIdxSeqs + 1,
    5276             :     LaneBitmask(0x00002008),
    5277             :     0,
    5278             :     true, /* HasDisjunctSubRegs */
    5279             :     true, /* CoveredBySubRegs */
    5280             :     XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses,
    5281             :     nullptr
    5282             :   };
    5283             : 
    5284             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
    5285             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
    5286             :     XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
    5287             :     SuperRegIdxSeqs + 1,
    5288             :     LaneBitmask(0x00002008),
    5289             :     0,
    5290             :     true, /* HasDisjunctSubRegs */
    5291             :     true, /* CoveredBySubRegs */
    5292             :     XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
    5293             :     nullptr
    5294             :   };
    5295             : 
    5296             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
    5297             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
    5298             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
    5299             :     SuperRegIdxSeqs + 1,
    5300             :     LaneBitmask(0x00002008),
    5301             :     0,
    5302             :     true, /* HasDisjunctSubRegs */
    5303             :     true, /* CoveredBySubRegs */
    5304             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
    5305             :     nullptr
    5306             :   };
    5307             : 
    5308             :   extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass = {
    5309             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_tcGPR64RegClassID],
    5310             :     XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask,
    5311             :     SuperRegIdxSeqs + 1,
    5312             :     LaneBitmask(0x00002008),
    5313             :     0,
    5314             :     true, /* HasDisjunctSubRegs */
    5315             :     true, /* CoveredBySubRegs */
    5316             :     XSeqPairsClass_with_sube64_in_tcGPR64Superclasses,
    5317             :     nullptr
    5318             :   };
    5319             : 
    5320             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
    5321             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
    5322             :     XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
    5323             :     SuperRegIdxSeqs + 1,
    5324             :     LaneBitmask(0x00002008),
    5325             :     0,
    5326             :     true, /* HasDisjunctSubRegs */
    5327             :     true, /* CoveredBySubRegs */
    5328             :     XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
    5329             :     nullptr
    5330             :   };
    5331             : 
    5332             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
    5333             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
    5334             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
    5335             :     SuperRegIdxSeqs + 1,
    5336             :     LaneBitmask(0x00002008),
    5337             :     0,
    5338             :     true, /* HasDisjunctSubRegs */
    5339             :     true, /* CoveredBySubRegs */
    5340             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
    5341             :     nullptr
    5342             :   };
    5343             : 
    5344             :   extern const TargetRegisterClass FPR128RegClass = {
    5345             :     &AArch64MCRegisterClasses[FPR128RegClassID],
    5346             :     FPR128SubClassMask,
    5347             :     SuperRegIdxSeqs + 5,
    5348             :     LaneBitmask(0x00000001),
    5349             :     0,
    5350             :     false, /* HasDisjunctSubRegs */
    5351             :     false, /* CoveredBySubRegs */
    5352             :     NullRegClasses,
    5353             :     nullptr
    5354             :   };
    5355             : 
    5356             :   extern const TargetRegisterClass ZPRRegClass = {
    5357             :     &AArch64MCRegisterClasses[ZPRRegClassID],
    5358             :     ZPRSubClassMask,
    5359             :     SuperRegIdxSeqs + 1,
    5360             :     LaneBitmask(0x00000041),
    5361             :     0,
    5362             :     true, /* HasDisjunctSubRegs */
    5363             :     false, /* CoveredBySubRegs */
    5364             :     NullRegClasses,
    5365             :     nullptr
    5366             :   };
    5367             : 
    5368             :   extern const TargetRegisterClass FPR128_loRegClass = {
    5369             :     &AArch64MCRegisterClasses[FPR128_loRegClassID],
    5370             :     FPR128_loSubClassMask,
    5371             :     SuperRegIdxSeqs + 5,
    5372             :     LaneBitmask(0x00000001),
    5373             :     0,
    5374             :     false, /* HasDisjunctSubRegs */
    5375             :     false, /* CoveredBySubRegs */
    5376             :     FPR128_loSuperclasses,
    5377             :     nullptr
    5378             :   };
    5379             : 
    5380             :   extern const TargetRegisterClass ZPR_with_zsub_in_FPR128_loRegClass = {
    5381             :     &AArch64MCRegisterClasses[ZPR_with_zsub_in_FPR128_loRegClassID],
    5382             :     ZPR_with_zsub_in_FPR128_loSubClassMask,
    5383             :     SuperRegIdxSeqs + 1,
    5384             :     LaneBitmask(0x00000041),
    5385             :     0,
    5386             :     true, /* HasDisjunctSubRegs */
    5387             :     false, /* CoveredBySubRegs */
    5388             :     ZPR_with_zsub_in_FPR128_loSuperclasses,
    5389             :     nullptr
    5390             :   };
    5391             : 
    5392             :   extern const TargetRegisterClass DDDRegClass = {
    5393             :     &AArch64MCRegisterClasses[DDDRegClassID],
    5394             :     DDDSubClassMask,
    5395             :     SuperRegIdxSeqs + 58,
    5396             :     LaneBitmask(0x00000281),
    5397             :     0,
    5398             :     true, /* HasDisjunctSubRegs */
    5399             :     true, /* CoveredBySubRegs */
    5400             :     NullRegClasses,
    5401             :     nullptr
    5402             :   };
    5403             : 
    5404             :   extern const TargetRegisterClass DDDDRegClass = {
    5405             :     &AArch64MCRegisterClasses[DDDDRegClassID],
    5406             :     DDDDSubClassMask,
    5407             :     SuperRegIdxSeqs + 49,
    5408             :     LaneBitmask(0x00000381),
    5409             :     0,
    5410             :     true, /* HasDisjunctSubRegs */
    5411             :     true, /* CoveredBySubRegs */
    5412             :     NullRegClasses,
    5413             :     nullptr
    5414             :   };
    5415             : 
    5416             :   extern const TargetRegisterClass QQRegClass = {
    5417             :     &AArch64MCRegisterClasses[QQRegClassID],
    5418             :     QQSubClassMask,
    5419             :     SuperRegIdxSeqs + 54,
    5420             :     LaneBitmask(0x00000401),
    5421             :     0,
    5422             :     true, /* HasDisjunctSubRegs */
    5423             :     true, /* CoveredBySubRegs */
    5424             :     NullRegClasses,
    5425             :     nullptr
    5426             :   };
    5427             : 
    5428             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass = {
    5429             :     &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_loRegClassID],
    5430             :     QQ_with_qsub0_in_FPR128_loSubClassMask,
    5431             :     SuperRegIdxSeqs + 54,
    5432             :     LaneBitmask(0x00000401),
    5433             :     0,
    5434             :     true, /* HasDisjunctSubRegs */
    5435             :     true, /* CoveredBySubRegs */
    5436             :     QQ_with_qsub0_in_FPR128_loSuperclasses,
    5437             :     nullptr
    5438             :   };
    5439             : 
    5440             :   extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass = {
    5441             :     &AArch64MCRegisterClasses[QQ_with_qsub1_in_FPR128_loRegClassID],
    5442             :     QQ_with_qsub1_in_FPR128_loSubClassMask,
    5443             :     SuperRegIdxSeqs + 54,
    5444             :     LaneBitmask(0x00000401),
    5445             :     0,
    5446             :     true, /* HasDisjunctSubRegs */
    5447             :     true, /* CoveredBySubRegs */
    5448             :     QQ_with_qsub1_in_FPR128_loSuperclasses,
    5449             :     nullptr
    5450             :   };
    5451             : 
    5452             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass = {
    5453             :     &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID],
    5454             :     QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask,
    5455             :     SuperRegIdxSeqs + 54,
    5456             :     LaneBitmask(0x00000401),
    5457             :     0,
    5458             :     true, /* HasDisjunctSubRegs */
    5459             :     true, /* CoveredBySubRegs */
    5460             :     QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses,
    5461             :     nullptr
    5462             :   };
    5463             : 
    5464             :   extern const TargetRegisterClass QQQRegClass = {
    5465             :     &AArch64MCRegisterClasses[QQQRegClassID],
    5466             :     QQQSubClassMask,
    5467             :     SuperRegIdxSeqs + 51,
    5468             :     LaneBitmask(0x00001401),
    5469             :     0,
    5470             :     true, /* HasDisjunctSubRegs */
    5471             :     true, /* CoveredBySubRegs */
    5472             :     NullRegClasses,
    5473             :     nullptr
    5474             :   };
    5475             : 
    5476             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass = {
    5477             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_loRegClassID],
    5478             :     QQQ_with_qsub0_in_FPR128_loSubClassMask,
    5479             :     SuperRegIdxSeqs + 51,
    5480             :     LaneBitmask(0x00001401),
    5481             :     0,
    5482             :     true, /* HasDisjunctSubRegs */
    5483             :     true, /* CoveredBySubRegs */
    5484             :     QQQ_with_qsub0_in_FPR128_loSuperclasses,
    5485             :     nullptr
    5486             :   };
    5487             : 
    5488             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass = {
    5489             :     &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_loRegClassID],
    5490             :     QQQ_with_qsub1_in_FPR128_loSubClassMask,
    5491             :     SuperRegIdxSeqs + 51,
    5492             :     LaneBitmask(0x00001401),
    5493             :     0,
    5494             :     true, /* HasDisjunctSubRegs */
    5495             :     true, /* CoveredBySubRegs */
    5496             :     QQQ_with_qsub1_in_FPR128_loSuperclasses,
    5497             :     nullptr
    5498             :   };
    5499             : 
    5500             :   extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass = {
    5501             :     &AArch64MCRegisterClasses[QQQ_with_qsub2_in_FPR128_loRegClassID],
    5502             :     QQQ_with_qsub2_in_FPR128_loSubClassMask,
    5503             :     SuperRegIdxSeqs + 51,
    5504             :     LaneBitmask(0x00001401),
    5505             :     0,
    5506             :     true, /* HasDisjunctSubRegs */
    5507             :     true, /* CoveredBySubRegs */
    5508             :     QQQ_with_qsub2_in_FPR128_loSuperclasses,
    5509             :     nullptr
    5510             :   };
    5511             : 
    5512             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass = {
    5513             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID],
    5514             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask,
    5515             :     SuperRegIdxSeqs + 51,
    5516             :     LaneBitmask(0x00001401),
    5517             :     0,
    5518             :     true, /* HasDisjunctSubRegs */
    5519             :     true, /* CoveredBySubRegs */
    5520             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses,
    5521             :     nullptr
    5522             :   };
    5523             : 
    5524             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
    5525             :     &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
    5526             :     QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
    5527             :     SuperRegIdxSeqs + 51,
    5528             :     LaneBitmask(0x00001401),
    5529             :     0,
    5530             :     true, /* HasDisjunctSubRegs */
    5531             :     true, /* CoveredBySubRegs */
    5532             :     QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
    5533             :     nullptr
    5534             :   };
    5535             : 
    5536             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
    5537             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
    5538             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
    5539             :     SuperRegIdxSeqs + 51,
    5540             :     LaneBitmask(0x00001401),
    5541             :     0,
    5542             :     true, /* HasDisjunctSubRegs */
    5543             :     true, /* CoveredBySubRegs */
    5544             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
    5545             :     nullptr
    5546             :   };
    5547             : 
    5548             :   extern const TargetRegisterClass QQQQRegClass = {
    5549             :     &AArch64MCRegisterClasses[QQQQRegClassID],
    5550             :     QQQQSubClassMask,
    5551             :     SuperRegIdxSeqs + 1,
    5552             :     LaneBitmask(0x00001C01),
    5553             :     0,
    5554             :     true, /* HasDisjunctSubRegs */
    5555             :     true, /* CoveredBySubRegs */
    5556             :     NullRegClasses,
    5557             :     nullptr
    5558             :   };
    5559             : 
    5560             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass = {
    5561             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_loRegClassID],
    5562             :     QQQQ_with_qsub0_in_FPR128_loSubClassMask,
    5563             :     SuperRegIdxSeqs + 1,
    5564             :     LaneBitmask(0x00001C01),
    5565             :     0,
    5566             :     true, /* HasDisjunctSubRegs */
    5567             :     true, /* CoveredBySubRegs */
    5568             :     QQQQ_with_qsub0_in_FPR128_loSuperclasses,
    5569             :     nullptr
    5570             :   };
    5571             : 
    5572             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass = {
    5573             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_loRegClassID],
    5574             :     QQQQ_with_qsub1_in_FPR128_loSubClassMask,
    5575             :     SuperRegIdxSeqs + 1,
    5576             :     LaneBitmask(0x00001C01),
    5577             :     0,
    5578             :     true, /* HasDisjunctSubRegs */
    5579             :     true, /* CoveredBySubRegs */
    5580             :     QQQQ_with_qsub1_in_FPR128_loSuperclasses,
    5581             :     nullptr
    5582             :   };
    5583             : 
    5584             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass = {
    5585             :     &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_loRegClassID],
    5586             :     QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    5587             :     SuperRegIdxSeqs + 1,
    5588             :     LaneBitmask(0x00001C01),
    5589             :     0,
    5590             :     true, /* HasDisjunctSubRegs */
    5591             :     true, /* CoveredBySubRegs */
    5592             :     QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    5593             :     nullptr
    5594             :   };
    5595             : 
    5596             :   extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass = {
    5597             :     &AArch64MCRegisterClasses[QQQQ_with_qsub3_in_FPR128_loRegClassID],
    5598             :     QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    5599             :     SuperRegIdxSeqs + 1,
    5600             :     LaneBitmask(0x00001C01),
    5601             :     0,
    5602             :     true, /* HasDisjunctSubRegs */
    5603             :     true, /* CoveredBySubRegs */
    5604             :     QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    5605             :     nullptr
    5606             :   };
    5607             : 
    5608             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass = {
    5609             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID],
    5610             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask,
    5611             :     SuperRegIdxSeqs + 1,
    5612             :     LaneBitmask(0x00001C01),
    5613             :     0,
    5614             :     true, /* HasDisjunctSubRegs */
    5615             :     true, /* CoveredBySubRegs */
    5616             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses,
    5617             :     nullptr
    5618             :   };
    5619             : 
    5620             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
    5621             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
    5622             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    5623             :     SuperRegIdxSeqs + 1,
    5624             :     LaneBitmask(0x00001C01),
    5625             :     0,
    5626             :     true, /* HasDisjunctSubRegs */
    5627             :     true, /* CoveredBySubRegs */
    5628             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    5629             :     nullptr
    5630             :   };
    5631             : 
    5632             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    5633             :     &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    5634             :     QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    5635             :     SuperRegIdxSeqs + 1,
    5636             :     LaneBitmask(0x00001C01),
    5637             :     0,
    5638             :     true, /* HasDisjunctSubRegs */
    5639             :     true, /* CoveredBySubRegs */
    5640             :     QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    5641             :     nullptr
    5642             :   };
    5643             : 
    5644             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
    5645             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
    5646             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    5647             :     SuperRegIdxSeqs + 1,
    5648             :     LaneBitmask(0x00001C01),
    5649             :     0,
    5650             :     true, /* HasDisjunctSubRegs */
    5651             :     true, /* CoveredBySubRegs */
    5652             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    5653             :     nullptr
    5654             :   };
    5655             : 
    5656             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    5657             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    5658             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    5659             :     SuperRegIdxSeqs + 1,
    5660             :     LaneBitmask(0x00001C01),
    5661             :     0,
    5662             :     true, /* HasDisjunctSubRegs */
    5663             :     true, /* CoveredBySubRegs */
    5664             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    5665             :     nullptr
    5666             :   };
    5667             : 
    5668             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    5669             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    5670             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    5671             :     SuperRegIdxSeqs + 1,
    5672             :     LaneBitmask(0x00001C01),
    5673             :     0,
    5674             :     true, /* HasDisjunctSubRegs */
    5675             :     true, /* CoveredBySubRegs */
    5676             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    5677             :     nullptr
    5678             :   };
    5679             : 
    5680             : } // end namespace AArch64
    5681             : 
    5682             : namespace {
    5683             :   const TargetRegisterClass* const RegisterClasses[] = {
    5684             :     &AArch64::FPR8RegClass,
    5685             :     &AArch64::FPR16RegClass,
    5686             :     &AArch64::PPRRegClass,
    5687             :     &AArch64::PPR_3bRegClass,
    5688             :     &AArch64::GPR32allRegClass,
    5689             :     &AArch64::FPR32RegClass,
    5690             :     &AArch64::GPR32RegClass,
    5691             :     &AArch64::GPR32spRegClass,
    5692             :     &AArch64::GPR32commonRegClass,
    5693             :     &AArch64::CCRRegClass,
    5694             :     &AArch64::GPR32sponlyRegClass,
    5695             :     &AArch64::WSeqPairsClassRegClass,
    5696             :     &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
    5697             :     &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    5698             :     &AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    5699             :     &AArch64::GPR64allRegClass,
    5700             :     &AArch64::FPR64RegClass,
    5701             :     &AArch64::GPR64RegClass,
    5702             :     &AArch64::GPR64spRegClass,
    5703             :     &AArch64::GPR64commonRegClass,
    5704             :     &AArch64::tcGPR64RegClass,
    5705             :     &AArch64::GPR64sponlyRegClass,
    5706             :     &AArch64::DDRegClass,
    5707             :     &AArch64::XSeqPairsClassRegClass,
    5708             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    5709             :     &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5710             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5711             :     &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
    5712             :     &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    5713             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    5714             :     &AArch64::FPR128RegClass,
    5715             :     &AArch64::ZPRRegClass,
    5716             :     &AArch64::FPR128_loRegClass,
    5717             :     &AArch64::ZPR_with_zsub_in_FPR128_loRegClass,
    5718             :     &AArch64::DDDRegClass,
    5719             :     &AArch64::DDDDRegClass,
    5720             :     &AArch64::QQRegClass,
    5721             :     &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
    5722             :     &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
    5723             :     &AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass,
    5724             :     &AArch64::QQQRegClass,
    5725             :     &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    5726             :     &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    5727             :     &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    5728             :     &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
    5729             :     &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    5730             :     &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    5731             :     &AArch64::QQQQRegClass,
    5732             :     &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    5733             :     &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    5734             :     &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    5735             :     &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    5736             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    5737             :     &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    5738             :     &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5739             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    5740             :     &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5741             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5742             :   };
    5743             : } // end anonymous namespace
    5744             : 
    5745             : static const TargetRegisterInfoDesc AArch64RegInfoDesc[] = { // Extra Descriptors
    5746             :   { 0, false },
    5747             :   { 0, true },
    5748             :   { 0, true },
    5749             :   { 0, false },
    5750             :   { 0, true },
    5751             :   { 0, true },
    5752             :   { 0, true },
    5753             :   { 0, true },
    5754             :   { 0, true },
    5755             :   { 0, true },
    5756             :   { 0, true },
    5757             :   { 0, true },
    5758             :   { 0, true },
    5759             :   { 0, true },
    5760             :   { 0, true },
    5761             :   { 0, true },
    5762             :   { 0, true },
    5763             :   { 0, true },
    5764             :   { 0, true },
    5765             :   { 0, true },
    5766             :   { 0, true },
    5767             :   { 0, true },
    5768             :   { 0, true },
    5769             :   { 0, true },
    5770             :   { 0, true },
    5771             :   { 0, true },
    5772             :   { 0, true },
    5773             :   { 0, true },
    5774             :   { 0, true },
    5775             :   { 0, true },
    5776             :   { 0, true },
    5777             :   { 0, true },
    5778             :   { 0, true },
    5779             :   { 0, true },
    5780             :   { 0, true },
    5781             :   { 0, true },
    5782             :   { 0, true },
    5783             :   { 0, true },
    5784             :   { 0, true },
    5785             :   { 0, true },
    5786             :   { 0, true },
    5787             :   { 0, true },
    5788             :   { 0, true },
    5789             :   { 0, true },
    5790             :   { 0, true },
    5791             :   { 0, true },
    5792             :   { 0, true },
    5793             :   { 0, true },
    5794             :   { 0, true },
    5795             :   { 0, true },
    5796             :   { 0, true },
    5797             :   { 0, true },
    5798             :   { 0, true },
    5799             :   { 0, true },
    5800             :   { 0, true },
    5801             :   { 0, true },
    5802             :   { 0, true },
    5803             :   { 0, true },
    5804             :   { 0, true },
    5805             :   { 0, true },
    5806             :   { 0, true },
    5807             :   { 0, true },
    5808             :   { 0, true },
    5809             :   { 0, true },
    5810             :   { 0, true },
    5811             :   { 0, true },
    5812             :   { 0, true },
    5813             :   { 0, true },
    5814             :   { 0, true },
    5815             :   { 0, true },
    5816             :   { 0, true },
    5817             :   { 0, true },
    5818             :   { 0, true },
    5819             :   { 0, true },
    5820             :   { 0, true },
    5821             :   { 0, true },
    5822             :   { 0, true },
    5823             :   { 0, true },
    5824             :   { 0, true },
    5825             :   { 0, true },
    5826             :   { 0, true },
    5827             :   { 0, true },
    5828             :   { 0, true },
    5829             :   { 0, true },
    5830             :   { 0, true },
    5831             :   { 0, true },
    5832             :   { 0, true },
    5833             :   { 0, true },
    5834             :   { 0, true },
    5835             :   { 0, true },
    5836             :   { 0, true },
    5837             :   { 0, true },
    5838             :   { 0, true },
    5839             :   { 0, true },
    5840             :   { 0, true },
    5841             :   { 0, true },
    5842             :   { 0, true },
    5843             :   { 0, true },
    5844             :   { 0, true },
    5845             :   { 0, true },
    5846             :   { 0, true },
    5847             :   { 0, true },
    5848             :   { 0, true },
    5849             :   { 0, true },
    5850             :   { 0, true },
    5851             :   { 0, true },
    5852             :   { 0, true },
    5853             :   { 0, true },
    5854             :   { 0, true },
    5855             :   { 0, true },
    5856             :   { 0, true },
    5857             :   { 0, true },
    5858             :   { 0, true },
    5859             :   { 0, true },
    5860             :   { 0, true },
    5861             :   { 0, true },
    5862             :   { 0, true },
    5863             :   { 0, true },
    5864             :   { 0, true },
    5865             :   { 0, true },
    5866             :   { 0, true },
    5867             :   { 0, true },
    5868             :   { 0, true },
    5869             :   { 0, true },
    5870             :   { 0, true },
    5871             :   { 0, true },
    5872             :   { 0, true },
    5873             :   { 0, true },
    5874             :   { 0, true },
    5875             :   { 0, true },
    5876             :   { 0, true },
    5877             :   { 0, true },
    5878             :   { 0, true },
    5879             :   { 0, true },
    5880             :   { 0, true },
    5881             :   { 0, true },
    5882             :   { 0, true },
    5883             :   { 0, true },
    5884             :   { 0, true },
    5885             :   { 0, true },
    5886             :   { 0, true },
    5887             :   { 0, true },
    5888             :   { 0, true },
    5889             :   { 0, true },
    5890             :   { 0, true },
    5891             :   { 0, true },
    5892             :   { 0, true },
    5893             :   { 0, true },
    5894             :   { 0, true },
    5895             :   { 0, true },
    5896             :   { 0, true },
    5897             :   { 0, true },
    5898             :   { 0, true },
    5899             :   { 0, true },
    5900             :   { 0, true },
    5901             :   { 0, true },
    5902             :   { 0, true },
    5903             :   { 0, true },
    5904             :   { 0, true },
    5905             :   { 0, true },
    5906             :   { 0, true },
    5907             :   { 0, true },
    5908             :   { 0, true },
    5909             :   { 0, true },
    5910             :   { 0, true },
    5911             :   { 0, true },
    5912             :   { 0, true },
    5913             :   { 0, true },
    5914             :   { 0, true },
    5915             :   { 0, true },
    5916             :   { 0, true },
    5917             :   { 0, true },
    5918             :   { 0, true },
    5919             :   { 0, true },
    5920             :   { 0, true },
    5921             :   { 0, true },
    5922             :   { 0, true },
    5923             :   { 0, true },
    5924             :   { 0, true },
    5925             :   { 0, true },
    5926             :   { 0, true },
    5927             :   { 0, true },
    5928             :   { 0, true },
    5929             :   { 0, true },
    5930             :   { 0, true },
    5931             :   { 0, true },
    5932             :   { 0, true },
    5933             :   { 0, true },
    5934             :   { 0, true },
    5935             :   { 0, true },
    5936             :   { 0, true },
    5937             :   { 0, true },
    5938             :   { 0, true },
    5939             :   { 0, true },
    5940             :   { 0, true },
    5941             :   { 0, true },
    5942             :   { 0, true },
    5943             :   { 0, true },
    5944             :   { 0, true },
    5945             :   { 0, true },
    5946             :   { 0, true },
    5947             :   { 0, true },
    5948             :   { 0, true },
    5949             :   { 0, true },
    5950             :   { 0, true },
    5951             :   { 0, true },
    5952             :   { 0, true },
    5953             :   { 0, true },
    5954             :   { 0, true },
    5955             :   { 0, true },
    5956             :   { 0, true },
    5957             :   { 0, true },
    5958             :   { 0, true },
    5959             :   { 0, true },
    5960             :   { 0, true },
    5961             :   { 0, true },
    5962             :   { 0, true },
    5963             :   { 0, true },
    5964             :   { 0, true },
    5965             :   { 0, true },
    5966             :   { 0, true },
    5967             :   { 0, true },
    5968             :   { 0, true },
    5969             :   { 0, true },
    5970             :   { 0, true },
    5971             :   { 0, true },
    5972             :   { 0, true },
    5973             :   { 0, true },
    5974             :   { 0, true },
    5975             :   { 0, true },
    5976             :   { 0, true },
    5977             :   { 0, true },
    5978             :   { 0, true },
    5979             :   { 0, true },
    5980             :   { 0, true },
    5981             :   { 0, true },
    5982             :   { 0, true },
    5983             :   { 0, true },
    5984             :   { 0, true },
    5985             :   { 0, true },
    5986             :   { 0, true },
    5987             :   { 0, true },
    5988             :   { 0, true },
    5989             :   { 0, true },
    5990             :   { 0, true },
    5991             :   { 0, true },
    5992             :   { 0, true },
    5993             :   { 0, true },
    5994             :   { 0, true },
    5995             :   { 0, true },
    5996             :   { 0, true },
    5997             :   { 0, true },
    5998             :   { 0, true },
    5999             :   { 0, true },
    6000             :   { 0, true },
    6001             :   { 0, true },
    6002             :   { 0, true },
    6003             :   { 0, true },
    6004             :   { 0, true },
    6005             :   { 0, true },
    6006             :   { 0, true },
    6007             :   { 0, true },
    6008             :   { 0, true },
    6009             :   { 0, true },
    6010             :   { 0, true },
    6011             :   { 0, true },
    6012             :   { 0, true },
    6013             :   { 0, true },
    6014             :   { 0, true },
    6015             :   { 0, true },
    6016             :   { 0, true },
    6017             :   { 0, true },
    6018             :   { 0, true },
    6019             :   { 0, true },
    6020             :   { 0, true },
    6021             :   { 0, true },
    6022             :   { 0, false },
    6023             :   { 0, false },
    6024             :   { 0, false },
    6025             :   { 0, false },
    6026             :   { 0, false },
    6027             :   { 0, false },
    6028             :   { 0, false },
    6029             :   { 0, false },
    6030             :   { 0, false },
    6031             :   { 0, false },
    6032             :   { 0, false },
    6033             :   { 0, false },
    6034             :   { 0, false },
    6035             :   { 0, false },
    6036             :   { 0, false },
    6037             :   { 0, false },
    6038             :   { 0, false },
    6039             :   { 0, false },
    6040             :   { 0, false },
    6041             :   { 0, false },
    6042             :   { 0, false },
    6043             :   { 0, false },
    6044             :   { 0, false },
    6045             :   { 0, false },
    6046             :   { 0, false },
    6047             :   { 0, false },
    6048             :   { 0, false },
    6049             :   { 0, false },
    6050             :   { 0, false },
    6051             :   { 0, false },
    6052             :   { 0, false },
    6053             :   { 0, false },
    6054             :   { 0, true },
    6055             :   { 0, true },
    6056             :   { 0, true },
    6057             :   { 0, true },
    6058             :   { 0, true },
    6059             :   { 0, true },
    6060             :   { 0, true },
    6061             :   { 0, true },
    6062             :   { 0, true },
    6063             :   { 0, true },
    6064             :   { 0, true },
    6065             :   { 0, true },
    6066             :   { 0, true },
    6067             :   { 0, true },
    6068             :   { 0, true },
    6069             :   { 0, true },
    6070             :   { 0, true },
    6071             :   { 0, true },
    6072             :   { 0, true },
    6073             :   { 0, true },
    6074             :   { 0, true },
    6075             :   { 0, true },
    6076             :   { 0, true },
    6077             :   { 0, true },
    6078             :   { 0, true },
    6079             :   { 0, true },
    6080             :   { 0, true },
    6081             :   { 0, true },
    6082             :   { 0, true },
    6083             :   { 0, true },
    6084             :   { 0, true },
    6085             :   { 0, true },
    6086             :   { 0, true },
    6087             :   { 0, true },
    6088             :   { 0, true },
    6089             :   { 0, true },
    6090             :   { 0, true },
    6091             :   { 0, true },
    6092             :   { 0, true },
    6093             :   { 0, true },
    6094             :   { 0, true },
    6095             :   { 0, true },
    6096             :   { 0, true },
    6097             :   { 0, true },
    6098             :   { 0, true },
    6099             :   { 0, true },
    6100             :   { 0, true },
    6101             :   { 0, true },
    6102             :   { 0, true },
    6103             :   { 0, true },
    6104             :   { 0, true },
    6105             :   { 0, true },
    6106             :   { 0, true },
    6107             :   { 0, true },
    6108             :   { 0, true },
    6109             :   { 0, true },
    6110             :   { 0, true },
    6111             :   { 0, true },
    6112             :   { 0, true },
    6113             :   { 0, true },
    6114             :   { 0, true },
    6115             :   { 0, true },
    6116             :   { 0, true },
    6117             :   { 0, true },
    6118             :   { 0, true },
    6119             :   { 0, true },
    6120             :   { 0, true },
    6121             :   { 0, true },
    6122             :   { 0, true },
    6123             :   { 0, true },
    6124             :   { 0, true },
    6125             :   { 0, true },
    6126             :   { 0, true },
    6127             :   { 0, true },
    6128             :   { 0, true },
    6129             :   { 0, true },
    6130             :   { 0, true },
    6131             :   { 0, true },
    6132             :   { 0, true },
    6133             :   { 0, true },
    6134             :   { 0, true },
    6135             :   { 0, true },
    6136             :   { 0, true },
    6137             :   { 0, true },
    6138             :   { 0, true },
    6139             :   { 0, true },
    6140             :   { 0, true },
    6141             :   { 0, true },
    6142             :   { 0, true },
    6143             :   { 0, true },
    6144             :   { 0, true },
    6145             :   { 0, true },
    6146             :   { 0, true },
    6147             :   { 0, true },
    6148             :   { 0, true },
    6149             :   { 0, true },
    6150             :   { 0, true },
    6151             :   { 0, true },
    6152             :   { 0, true },
    6153             :   { 0, true },
    6154             :   { 0, true },
    6155             :   { 0, true },
    6156             :   { 0, true },
    6157             :   { 0, true },
    6158             :   { 0, true },
    6159             :   { 0, true },
    6160             :   { 0, true },
    6161             :   { 0, true },
    6162             :   { 0, true },
    6163             :   { 0, true },
    6164             :   { 0, true },
    6165             :   { 0, true },
    6166             :   { 0, true },
    6167             :   { 0, true },
    6168             :   { 0, true },
    6169             :   { 0, true },
    6170             :   { 0, true },
    6171             :   { 0, true },
    6172             :   { 0, true },
    6173             :   { 0, true },
    6174             :   { 0, true },
    6175             :   { 0, true },
    6176             :   { 0, true },
    6177             :   { 0, true },
    6178             :   { 0, true },
    6179             :   { 0, true },
    6180             :   { 0, true },
    6181             :   { 0, true },
    6182             :   { 0, true },
    6183             :   { 0, true },
    6184             :   { 0, true },
    6185             :   { 0, true },
    6186             :   { 0, true },
    6187             :   { 0, true },
    6188             :   { 0, true },
    6189             :   { 0, true },
    6190             :   { 0, true },
    6191             :   { 0, true },
    6192             :   { 0, true },
    6193             :   { 0, true },
    6194             :   { 0, true },
    6195             :   { 0, true },
    6196             :   { 0, true },
    6197             :   { 0, true },
    6198             :   { 0, true },
    6199             :   { 0, true },
    6200             :   { 0, true },
    6201             :   { 0, true },
    6202             :   { 0, true },
    6203             :   { 0, true },
    6204             :   { 0, true },
    6205             :   { 0, true },
    6206             :   { 0, true },
    6207             :   { 0, true },
    6208             :   { 0, true },
    6209             :   { 0, true },
    6210             :   { 0, true },
    6211             :   { 0, true },
    6212             :   { 0, true },
    6213             :   { 0, true },
    6214             :   { 0, true },
    6215             :   { 0, true },
    6216             :   { 0, true },
    6217             :   { 0, true },
    6218             :   { 0, true },
    6219             :   { 0, true },
    6220             :   { 0, true },
    6221             :   { 0, true },
    6222             :   { 0, true },
    6223             :   { 0, true },
    6224             :   { 0, true },
    6225             :   { 0, true },
    6226             :   { 0, true },
    6227             :   { 0, true },
    6228             :   { 0, true },
    6229             :   { 0, true },
    6230             :   { 0, true },
    6231             :   { 0, true },
    6232             :   { 0, true },
    6233             :   { 0, true },
    6234             :   { 0, true },
    6235             :   { 0, true },
    6236             :   { 0, true },
    6237             :   { 0, true },
    6238             :   { 0, true },
    6239             :   { 0, true },
    6240             :   { 0, true },
    6241             :   { 0, true },
    6242             :   { 0, true },
    6243             :   { 0, true },
    6244             :   { 0, true },
    6245             :   { 0, true },
    6246             :   { 0, true },
    6247             :   { 0, true },
    6248             :   { 0, true },
    6249             :   { 0, true },
    6250             :   { 0, true },
    6251             :   { 0, true },
    6252             :   { 0, true },
    6253             :   { 0, true },
    6254             :   { 0, true },
    6255             :   { 0, true },
    6256             :   { 0, true },
    6257             :   { 0, true },
    6258             :   { 0, true },
    6259             :   { 0, true },
    6260             :   { 0, true },
    6261             :   { 0, true },
    6262             :   { 0, true },
    6263             :   { 0, true },
    6264             :   { 0, true },
    6265             :   { 0, true },
    6266             :   { 0, true },
    6267             :   { 0, true },
    6268             :   { 0, true },
    6269             :   { 0, true },
    6270             :   { 0, true },
    6271             :   { 0, true },
    6272             :   { 0, true },
    6273             :   { 0, true },
    6274             :   { 0, true },
    6275             :   { 0, true },
    6276             :   { 0, true },
    6277             :   { 0, true },
    6278             :   { 0, true },
    6279             :   { 0, true },
    6280             :   { 0, true },
    6281             :   { 0, true },
    6282             :   { 0, true },
    6283             :   { 0, true },
    6284             :   { 0, true },
    6285             :   { 0, true },
    6286             :   { 0, true },
    6287             :   { 0, true },
    6288             :   { 0, true },
    6289             :   { 0, true },
    6290             :   { 0, true },
    6291             :   { 0, true },
    6292             :   { 0, true },
    6293             :   { 0, true },
    6294             :   { 0, true },
    6295             :   { 0, true },
    6296             :   { 0, true },
    6297             :   { 0, true },
    6298             :   { 0, true },
    6299             :   { 0, true },
    6300             :   { 0, true },
    6301             :   { 0, true },
    6302             :   { 0, true },
    6303             :   { 0, true },
    6304             :   { 0, true },
    6305             :   { 0, true },
    6306             :   { 0, true },
    6307             :   { 0, true },
    6308             :   { 0, true },
    6309             :   { 0, true },
    6310             : };
    6311        1077 : unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
    6312             :   static const uint8_t RowMap[60] = {
    6313             :     0, 0, 0, 1, 2, 3, 0, 0, 0, 0, 4, 5, 6, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 3, 3, 0, 2, 2, 0, 4, 4, 4, 0, 6, 6, 6, 0, 5, 5, 5, 0, 0, 0, 1, 1, 2, 7, 7, 7, 0, 0, 4, 4, 5, 4, 4, 5, 0, 
    6314             :   };
    6315             :   static const uint8_t Rows[8][60] = {
    6316             :     { 1, 2, 3, 4, 5, 0, 7, 0, 0, 10, 11, 12, 0, 14, 15, 15, 0, 43, 0, 0, 0, 22, 23, 24, 0, 0, 0, 28, 29, 30, 31, 32, 33, 34, 0, 0, 0, 0, 39, 40, 41, 42, 0, 44, 0, 46, 0, 0, 49, 0, 51, 52, 0, 54, 0, 0, 57, 0, 0, 0, },
    6317             :     { 22, 0, 4, 5, 6, 0, 23, 0, 0, 0, 0, 0, 0, 24, 43, 0, 0, 0, 0, 0, 0, 28, 29, 30, 0, 0, 0, 25, 26, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 46, 0, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    6318             :     { 28, 0, 5, 6, 0, 0, 29, 0, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 25, 26, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    6319             :     { 25, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    6320             :     { 31, 32, 32, 40, 36, 0, 33, 0, 0, 11, 12, 13, 0, 34, 0, 0, 0, 0, 0, 0, 0, 39, 41, 42, 0, 0, 0, 35, 37, 38, 39, 40, 41, 42, 0, 0, 0, 0, 35, 36, 37, 38, 0, 57, 0, 59, 0, 0, 57, 0, 58, 54, 0, 56, 0, 0, 59, 0, 0, 0, },
    6321             :     { 39, 40, 40, 36, 0, 0, 41, 0, 0, 12, 13, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 35, 37, 38, 0, 0, 0, 0, 0, 0, 35, 36, 37, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    6322             :     { 35, 36, 0, 0, 0, 0, 37, 0, 0, 0, 0, 0, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    6323             :     { 1, 0, 2, 32, 40, 36, 7, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 0, 0, 31, 33, 34, 35, 37, 38, 39, 41, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 51, 57, 58, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    6324             :   };
    6325             : 
    6326        1077 :   --IdxA; assert(IdxA < 60);
    6327        1077 :   --IdxB; assert(IdxB < 60);
    6328        1077 :   return Rows[RowMap[IdxA]][IdxB];
    6329             : }
    6330             : 
    6331             :   struct MaskRolOp {
    6332             :     LaneBitmask Mask;
    6333             :     uint8_t  RotateLeft;
    6334             :   };
    6335             :   static const MaskRolOp LaneMaskComposeSequences[] = {
    6336             :     { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    6337             :     { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    6338             :     { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    6339             :     { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    6340             :     { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    6341             :     { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    6342             :     { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    6343             :     { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    6344             :     { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
    6345             :     { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
    6346             :     { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
    6347             :     { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
    6348             :     { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
    6349             :     { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 26
    6350             :     { LaneBitmask(0x00000001),  7 }, { LaneBitmask(0x00000080),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 28
    6351             :     { LaneBitmask(0x00000001),  7 }, { LaneBitmask(0x00000080),  2 }, { LaneBitmask(0x00000200), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 31
    6352             :     { LaneBitmask(0x00000001),  9 }, { LaneBitmask(0x00000080),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 35
    6353             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 38
    6354             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000380),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 41
    6355             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000280),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 44
    6356             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 47
    6357             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400),  2 }, { LaneBitmask(0x00001000), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 50
    6358             :     { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000400),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 54
    6359             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 57
    6360             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080),  5 }, { LaneBitmask(0x00000200),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 60
    6361             :     { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000080),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 64
    6362             :     { LaneBitmask(0x00000010), 31 }, { LaneBitmask(0x00000020),  8 }, { LaneBitmask::getNone(), 0 }  // Sequence 67
    6363             :   };
    6364             :   static const MaskRolOp *const CompositeSequences[] = {
    6365             :     &LaneMaskComposeSequences[0], // to bsub
    6366             :     &LaneMaskComposeSequences[0], // to dsub
    6367             :     &LaneMaskComposeSequences[0], // to dsub0
    6368             :     &LaneMaskComposeSequences[2], // to dsub1
    6369             :     &LaneMaskComposeSequences[4], // to dsub2
    6370             :     &LaneMaskComposeSequences[6], // to dsub3
    6371             :     &LaneMaskComposeSequences[0], // to hsub
    6372             :     &LaneMaskComposeSequences[8], // to qhisub
    6373             :     &LaneMaskComposeSequences[10], // to qsub
    6374             :     &LaneMaskComposeSequences[0], // to qsub0
    6375             :     &LaneMaskComposeSequences[12], // to qsub1
    6376             :     &LaneMaskComposeSequences[14], // to qsub2
    6377             :     &LaneMaskComposeSequences[16], // to qsub3
    6378             :     &LaneMaskComposeSequences[0], // to ssub
    6379             :     &LaneMaskComposeSequences[18], // to sub_32
    6380             :     &LaneMaskComposeSequences[20], // to sube32
    6381             :     &LaneMaskComposeSequences[0], // to sube64
    6382             :     &LaneMaskComposeSequences[22], // to subo32
    6383             :     &LaneMaskComposeSequences[12], // to subo64
    6384             :     &LaneMaskComposeSequences[0], // to zsub
    6385             :     &LaneMaskComposeSequences[24], // to zsub_hi
    6386             :     &LaneMaskComposeSequences[2], // to dsub1_then_bsub
    6387             :     &LaneMaskComposeSequences[2], // to dsub1_then_hsub
    6388             :     &LaneMaskComposeSequences[2], // to dsub1_then_ssub
    6389             :     &LaneMaskComposeSequences[6], // to dsub3_then_bsub
    6390             :     &LaneMaskComposeSequences[6], // to dsub3_then_hsub
    6391             :     &LaneMaskComposeSequences[6], // to dsub3_then_ssub
    6392             :     &LaneMaskComposeSequences[4], // to dsub2_then_bsub
    6393             :     &LaneMaskComposeSequences[4], // to dsub2_then_hsub
    6394             :     &LaneMaskComposeSequences[4], // to dsub2_then_ssub
    6395             :     &LaneMaskComposeSequences[12], // to qsub1_then_bsub
    6396             :     &LaneMaskComposeSequences[12], // to qsub1_then_dsub
    6397             :     &LaneMaskComposeSequences[12], // to qsub1_then_hsub
    6398             :     &LaneMaskComposeSequences[12], // to qsub1_then_ssub
    6399             :     &LaneMaskComposeSequences[16], // to qsub3_then_bsub
    6400             :     &LaneMaskComposeSequences[16], // to qsub3_then_dsub
    6401             :     &LaneMaskComposeSequences[16], // to qsub3_then_hsub
    6402             :     &LaneMaskComposeSequences[16], // to qsub3_then_ssub
    6403             :     &LaneMaskComposeSequences[14], // to qsub2_then_bsub
    6404             :     &LaneMaskComposeSequences[14], // to qsub2_then_dsub
    6405             :     &LaneMaskComposeSequences[14], // to qsub2_then_hsub
    6406             :     &LaneMaskComposeSequences[14], // to qsub2_then_ssub
    6407             :     &LaneMaskComposeSequences[26], // to subo64_then_sub_32
    6408             :     &LaneMaskComposeSequences[0], // to dsub0_dsub1
    6409             :     &LaneMaskComposeSequences[0], // to dsub0_dsub1_dsub2
    6410             :     &LaneMaskComposeSequences[28], // to dsub1_dsub2
    6411             :     &LaneMaskComposeSequences[31], // to dsub1_dsub2_dsub3
    6412             :     &LaneMaskComposeSequences[35], // to dsub2_dsub3
    6413             :     &LaneMaskComposeSequences[38], // to dsub_qsub1_then_dsub
    6414             :     &LaneMaskComposeSequences[41], // to dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6415             :     &LaneMaskComposeSequences[44], // to dsub_qsub1_then_dsub_qsub2_then_dsub
    6416             :     &LaneMaskComposeSequences[0], // to qsub0_qsub1
    6417             :     &LaneMaskComposeSequences[0], // to qsub0_qsub1_qsub2
    6418             :     &LaneMaskComposeSequences[47], // to qsub1_qsub2
    6419             :     &LaneMaskComposeSequences[50], // to qsub1_qsub2_qsub3
    6420             :     &LaneMaskComposeSequences[54], // to qsub2_qsub3
    6421             :     &LaneMaskComposeSequences[57], // to qsub1_then_dsub_qsub2_then_dsub
    6422             :     &LaneMaskComposeSequences[60], // to qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6423             :     &LaneMaskComposeSequences[64], // to qsub2_then_dsub_qsub3_then_dsub
    6424             :     &LaneMaskComposeSequences[67] // to sub_32_subo64_then_sub_32
    6425             :   };
    6426             : 
    6427           0 : LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
    6428           0 :   --IdxA; assert(IdxA < 60 && "Subregister index out of bounds");
    6429             :   LaneBitmask Result;
    6430           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    6431           0 :     LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    6432           0 :     if (unsigned S = Ops->RotateLeft)
    6433           0 :       Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    6434             :     else
    6435             :       Result |= LaneBitmask(M);
    6436             :   }
    6437           0 :   return Result;
    6438             : }
    6439             : 
    6440           0 : LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
    6441           0 :   LaneMask &= getSubRegIndexLaneMask(IdxA);
    6442           0 :   --IdxA; assert(IdxA < 60 && "Subregister index out of bounds");
    6443             :   LaneBitmask Result;
    6444           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    6445             :     LaneBitmask::Type M = LaneMask.getAsInteger();
    6446           0 :     if (unsigned S = Ops->RotateLeft)
    6447           0 :       Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    6448             :     else
    6449             :       Result |= LaneBitmask(M);
    6450             :   }
    6451           0 :   return Result;
    6452             : }
    6453             : 
    6454       32153 : const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
    6455             :   static const uint8_t Table[58][60] = {
    6456             :     {   // FPR8
    6457             :       0,        // bsub
    6458             :       0,        // dsub
    6459             :       0,        // dsub0
    6460             :       0,        // dsub1
    6461             :       0,        // dsub2
    6462             :       0,        // dsub3
    6463             :       0,        // hsub
    6464             :       0,        // qhisub
    6465             :       0,        // qsub
    6466             :       0,        // qsub0
    6467             :       0,        // qsub1
    6468             :       0,        // qsub2
    6469             :       0,        // qsub3
    6470             :       0,        // ssub
    6471             :       0,        // sub_32
    6472             :       0,        // sube32
    6473             :       0,        // sube64
    6474             :       0,        // subo32
    6475             :       0,        // subo64
    6476             :       0,        // zsub
    6477             :       0,        // zsub_hi
    6478             :       0,        // dsub1_then_bsub
    6479             :       0,        // dsub1_then_hsub
    6480             :       0,        // dsub1_then_ssub
    6481             :       0,        // dsub3_then_bsub
    6482             :       0,        // dsub3_then_hsub
    6483             :       0,        // dsub3_then_ssub
    6484             :       0,        // dsub2_then_bsub
    6485             :       0,        // dsub2_then_hsub
    6486             :       0,        // dsub2_then_ssub
    6487             :       0,        // qsub1_then_bsub
    6488             :       0,        // qsub1_then_dsub
    6489             :       0,        // qsub1_then_hsub
    6490             :       0,        // qsub1_then_ssub
    6491             :       0,        // qsub3_then_bsub
    6492             :       0,        // qsub3_then_dsub
    6493             :       0,        // qsub3_then_hsub
    6494             :       0,        // qsub3_then_ssub
    6495             :       0,        // qsub2_then_bsub
    6496             :       0,        // qsub2_then_dsub
    6497             :       0,        // qsub2_then_hsub
    6498             :       0,        // qsub2_then_ssub
    6499             :       0,        // subo64_then_sub_32
    6500             :       0,        // dsub0_dsub1
    6501             :       0,        // dsub0_dsub1_dsub2
    6502             :       0,        // dsub1_dsub2
    6503             :       0,        // dsub1_dsub2_dsub3
    6504             :       0,        // dsub2_dsub3
    6505             :       0,        // dsub_qsub1_then_dsub
    6506             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6507             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6508             :       0,        // qsub0_qsub1
    6509             :       0,        // qsub0_qsub1_qsub2
    6510             :       0,        // qsub1_qsub2
    6511             :       0,        // qsub1_qsub2_qsub3
    6512             :       0,        // qsub2_qsub3
    6513             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6514             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6515             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6516             :       0,        // sub_32_subo64_then_sub_32
    6517             :     },
    6518             :     {   // FPR16
    6519             :       2,        // bsub -> FPR16
    6520             :       0,        // dsub
    6521             :       0,        // dsub0
    6522             :       0,        // dsub1
    6523             :       0,        // dsub2
    6524             :       0,        // dsub3
    6525             :       0,        // hsub
    6526             :       0,        // qhisub
    6527             :       0,        // qsub
    6528             :       0,        // qsub0
    6529             :       0,        // qsub1
    6530             :       0,        // qsub2
    6531             :       0,        // qsub3
    6532             :       0,        // ssub
    6533             :       0,        // sub_32
    6534             :       0,        // sube32
    6535             :       0,        // sube64
    6536             :       0,        // subo32
    6537             :       0,        // subo64
    6538             :       0,        // zsub
    6539             :       0,        // zsub_hi
    6540             :       0,        // dsub1_then_bsub
    6541             :       0,        // dsub1_then_hsub
    6542             :       0,        // dsub1_then_ssub
    6543             :       0,        // dsub3_then_bsub
    6544             :       0,        // dsub3_then_hsub
    6545             :       0,        // dsub3_then_ssub
    6546             :       0,        // dsub2_then_bsub
    6547             :       0,        // dsub2_then_hsub
    6548             :       0,        // dsub2_then_ssub
    6549             :       0,        // qsub1_then_bsub
    6550             :       0,        // qsub1_then_dsub
    6551             :       0,        // qsub1_then_hsub
    6552             :       0,        // qsub1_then_ssub
    6553             :       0,        // qsub3_then_bsub
    6554             :       0,        // qsub3_then_dsub
    6555             :       0,        // qsub3_then_hsub
    6556             :       0,        // qsub3_then_ssub
    6557             :       0,        // qsub2_then_bsub
    6558             :       0,        // qsub2_then_dsub
    6559             :       0,        // qsub2_then_hsub
    6560             :       0,        // qsub2_then_ssub
    6561             :       0,        // subo64_then_sub_32
    6562             :       0,        // dsub0_dsub1
    6563             :       0,        // dsub0_dsub1_dsub2
    6564             :       0,        // dsub1_dsub2
    6565             :       0,        // dsub1_dsub2_dsub3
    6566             :       0,        // dsub2_dsub3
    6567             :       0,        // dsub_qsub1_then_dsub
    6568             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6569             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6570             :       0,        // qsub0_qsub1
    6571             :       0,        // qsub0_qsub1_qsub2
    6572             :       0,        // qsub1_qsub2
    6573             :       0,        // qsub1_qsub2_qsub3
    6574             :       0,        // qsub2_qsub3
    6575             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6576             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6577             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6578             :       0,        // sub_32_subo64_then_sub_32
    6579             :     },
    6580             :     {   // PPR
    6581             :       0,        // bsub
    6582             :       0,        // dsub
    6583             :       0,        // dsub0
    6584             :       0,        // dsub1
    6585             :       0,        // dsub2
    6586             :       0,        // dsub3
    6587             :       0,        // hsub
    6588             :       0,        // qhisub
    6589             :       0,        // qsub
    6590             :       0,        // qsub0
    6591             :       0,        // qsub1
    6592             :       0,        // qsub2
    6593             :       0,        // qsub3
    6594             :       0,        // ssub
    6595             :       0,        // sub_32
    6596             :       0,        // sube32
    6597             :       0,        // sube64
    6598             :       0,        // subo32
    6599             :       0,        // subo64
    6600             :       0,        // zsub
    6601             :       0,        // zsub_hi
    6602             :       0,        // dsub1_then_bsub
    6603             :       0,        // dsub1_then_hsub
    6604             :       0,        // dsub1_then_ssub
    6605             :       0,        // dsub3_then_bsub
    6606             :       0,        // dsub3_then_hsub
    6607             :       0,        // dsub3_then_ssub
    6608             :       0,        // dsub2_then_bsub
    6609             :       0,        // dsub2_then_hsub
    6610             :       0,        // dsub2_then_ssub
    6611             :       0,        // qsub1_then_bsub
    6612             :       0,        // qsub1_then_dsub
    6613             :       0,        // qsub1_then_hsub
    6614             :       0,        // qsub1_then_ssub
    6615             :       0,        // qsub3_then_bsub
    6616             :       0,        // qsub3_then_dsub
    6617             :       0,        // qsub3_then_hsub
    6618             :       0,        // qsub3_then_ssub
    6619             :       0,        // qsub2_then_bsub
    6620             :       0,        // qsub2_then_dsub
    6621             :       0,        // qsub2_then_hsub
    6622             :       0,        // qsub2_then_ssub
    6623             :       0,        // subo64_then_sub_32
    6624             :       0,        // dsub0_dsub1
    6625             :       0,        // dsub0_dsub1_dsub2
    6626             :       0,        // dsub1_dsub2
    6627             :       0,        // dsub1_dsub2_dsub3
    6628             :       0,        // dsub2_dsub3
    6629             :       0,        // dsub_qsub1_then_dsub
    6630             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6631             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6632             :       0,        // qsub0_qsub1
    6633             :       0,        // qsub0_qsub1_qsub2
    6634             :       0,        // qsub1_qsub2
    6635             :       0,        // qsub1_qsub2_qsub3
    6636             :       0,        // qsub2_qsub3
    6637             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6638             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6639             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6640             :       0,        // sub_32_subo64_then_sub_32
    6641             :     },
    6642             :     {   // PPR_3b
    6643             :       0,        // bsub
    6644             :       0,        // dsub
    6645             :       0,        // dsub0
    6646             :       0,        // dsub1
    6647             :       0,        // dsub2
    6648             :       0,        // dsub3
    6649             :       0,        // hsub
    6650             :       0,        // qhisub
    6651             :       0,        // qsub
    6652             :       0,        // qsub0
    6653             :       0,        // qsub1
    6654             :       0,        // qsub2
    6655             :       0,        // qsub3
    6656             :       0,        // ssub
    6657             :       0,        // sub_32
    6658             :       0,        // sube32
    6659             :       0,        // sube64
    6660             :       0,        // subo32
    6661             :       0,        // subo64
    6662             :       0,        // zsub
    6663             :       0,        // zsub_hi
    6664             :       0,        // dsub1_then_bsub
    6665             :       0,        // dsub1_then_hsub
    6666             :       0,        // dsub1_then_ssub
    6667             :       0,        // dsub3_then_bsub
    6668             :       0,        // dsub3_then_hsub
    6669             :       0,        // dsub3_then_ssub
    6670             :       0,        // dsub2_then_bsub
    6671             :       0,        // dsub2_then_hsub
    6672             :       0,        // dsub2_then_ssub
    6673             :       0,        // qsub1_then_bsub
    6674             :       0,        // qsub1_then_dsub
    6675             :       0,        // qsub1_then_hsub
    6676             :       0,        // qsub1_then_ssub
    6677             :       0,        // qsub3_then_bsub
    6678             :       0,        // qsub3_then_dsub
    6679             :       0,        // qsub3_then_hsub
    6680             :       0,        // qsub3_then_ssub
    6681             :       0,        // qsub2_then_bsub
    6682             :       0,        // qsub2_then_dsub
    6683             :       0,        // qsub2_then_hsub
    6684             :       0,        // qsub2_then_ssub
    6685             :       0,        // subo64_then_sub_32
    6686             :       0,        // dsub0_dsub1
    6687             :       0,        // dsub0_dsub1_dsub2
    6688             :       0,        // dsub1_dsub2
    6689             :       0,        // dsub1_dsub2_dsub3
    6690             :       0,        // dsub2_dsub3
    6691             :       0,        // dsub_qsub1_then_dsub
    6692             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6693             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6694             :       0,        // qsub0_qsub1
    6695             :       0,        // qsub0_qsub1_qsub2
    6696             :       0,        // qsub1_qsub2
    6697             :       0,        // qsub1_qsub2_qsub3
    6698             :       0,        // qsub2_qsub3
    6699             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6700             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6701             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6702             :       0,        // sub_32_subo64_then_sub_32
    6703             :     },
    6704             :     {   // GPR32all
    6705             :       0,        // bsub
    6706             :       0,        // dsub
    6707             :       0,        // dsub0
    6708             :       0,        // dsub1
    6709             :       0,        // dsub2
    6710             :       0,        // dsub3
    6711             :       0,        // hsub
    6712             :       0,        // qhisub
    6713             :       0,        // qsub
    6714             :       0,        // qsub0
    6715             :       0,        // qsub1
    6716             :       0,        // qsub2
    6717             :       0,        // qsub3
    6718             :       0,        // ssub
    6719             :       0,        // sub_32
    6720             :       0,        // sube32
    6721             :       0,        // sube64
    6722             :       0,        // subo32
    6723             :       0,        // subo64
    6724             :       0,        // zsub
    6725             :       0,        // zsub_hi
    6726             :       0,        // dsub1_then_bsub
    6727             :       0,        // dsub1_then_hsub
    6728             :       0,        // dsub1_then_ssub
    6729             :       0,        // dsub3_then_bsub
    6730             :       0,        // dsub3_then_hsub
    6731             :       0,        // dsub3_then_ssub
    6732             :       0,        // dsub2_then_bsub
    6733             :       0,        // dsub2_then_hsub
    6734             :       0,        // dsub2_then_ssub
    6735             :       0,        // qsub1_then_bsub
    6736             :       0,        // qsub1_then_dsub
    6737             :       0,        // qsub1_then_hsub
    6738             :       0,        // qsub1_then_ssub
    6739             :       0,        // qsub3_then_bsub
    6740             :       0,        // qsub3_then_dsub
    6741             :       0,        // qsub3_then_hsub
    6742             :       0,        // qsub3_then_ssub
    6743             :       0,        // qsub2_then_bsub
    6744             :       0,        // qsub2_then_dsub
    6745             :       0,        // qsub2_then_hsub
    6746             :       0,        // qsub2_then_ssub
    6747             :       0,        // subo64_then_sub_32
    6748             :       0,        // dsub0_dsub1
    6749             :       0,        // dsub0_dsub1_dsub2
    6750             :       0,        // dsub1_dsub2
    6751             :       0,        // dsub1_dsub2_dsub3
    6752             :       0,        // dsub2_dsub3
    6753             :       0,        // dsub_qsub1_then_dsub
    6754             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6755             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6756             :       0,        // qsub0_qsub1
    6757             :       0,        // qsub0_qsub1_qsub2
    6758             :       0,        // qsub1_qsub2
    6759             :       0,        // qsub1_qsub2_qsub3
    6760             :       0,        // qsub2_qsub3
    6761             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6762             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6763             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6764             :       0,        // sub_32_subo64_then_sub_32
    6765             :     },
    6766             :     {   // FPR32
    6767             :       6,        // bsub -> FPR32
    6768             :       0,        // dsub
    6769             :       0,        // dsub0
    6770             :       0,        // dsub1
    6771             :       0,        // dsub2
    6772             :       0,        // dsub3
    6773             :       6,        // hsub -> FPR32
    6774             :       0,        // qhisub
    6775             :       0,        // qsub
    6776             :       0,        // qsub0
    6777             :       0,        // qsub1
    6778             :       0,        // qsub2
    6779             :       0,        // qsub3
    6780             :       0,        // ssub
    6781             :       0,        // sub_32
    6782             :       0,        // sube32
    6783             :       0,        // sube64
    6784             :       0,        // subo32
    6785             :       0,        // subo64
    6786             :       0,        // zsub
    6787             :       0,        // zsub_hi
    6788             :       0,        // dsub1_then_bsub
    6789             :       0,        // dsub1_then_hsub
    6790             :       0,        // dsub1_then_ssub
    6791             :       0,        // dsub3_then_bsub
    6792             :       0,        // dsub3_then_hsub
    6793             :       0,        // dsub3_then_ssub
    6794             :       0,        // dsub2_then_bsub
    6795             :       0,        // dsub2_then_hsub
    6796             :       0,        // dsub2_then_ssub
    6797             :       0,        // qsub1_then_bsub
    6798             :       0,        // qsub1_then_dsub
    6799             :       0,        // qsub1_then_hsub
    6800             :       0,        // qsub1_then_ssub
    6801             :       0,        // qsub3_then_bsub
    6802             :       0,        // qsub3_then_dsub
    6803             :       0,        // qsub3_then_hsub
    6804             :       0,        // qsub3_then_ssub
    6805             :       0,        // qsub2_then_bsub
    6806             :       0,        // qsub2_then_dsub
    6807             :       0,        // qsub2_then_hsub
    6808             :       0,        // qsub2_then_ssub
    6809             :       0,        // subo64_then_sub_32
    6810             :       0,        // dsub0_dsub1
    6811             :       0,        // dsub0_dsub1_dsub2
    6812             :       0,        // dsub1_dsub2
    6813             :       0,        // dsub1_dsub2_dsub3
    6814             :       0,        // dsub2_dsub3
    6815             :       0,        // dsub_qsub1_then_dsub
    6816             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6817             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6818             :       0,        // qsub0_qsub1
    6819             :       0,        // qsub0_qsub1_qsub2
    6820             :       0,        // qsub1_qsub2
    6821             :       0,        // qsub1_qsub2_qsub3
    6822             :       0,        // qsub2_qsub3
    6823             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6824             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6825             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6826             :       0,        // sub_32_subo64_then_sub_32
    6827             :     },
    6828             :     {   // GPR32
    6829             :       0,        // bsub
    6830             :       0,        // dsub
    6831             :       0,        // dsub0
    6832             :       0,        // dsub1
    6833             :       0,        // dsub2
    6834             :       0,        // dsub3
    6835             :       0,        // hsub
    6836             :       0,        // qhisub
    6837             :       0,        // qsub
    6838             :       0,        // qsub0
    6839             :       0,        // qsub1
    6840             :       0,        // qsub2
    6841             :       0,        // qsub3
    6842             :       0,        // ssub
    6843             :       0,        // sub_32
    6844             :       0,        // sube32
    6845             :       0,        // sube64
    6846             :       0,        // subo32
    6847             :       0,        // subo64
    6848             :       0,        // zsub
    6849             :       0,        // zsub_hi
    6850             :       0,        // dsub1_then_bsub
    6851             :       0,        // dsub1_then_hsub
    6852             :       0,        // dsub1_then_ssub
    6853             :       0,        // dsub3_then_bsub
    6854             :       0,        // dsub3_then_hsub
    6855             :       0,        // dsub3_then_ssub
    6856             :       0,        // dsub2_then_bsub
    6857             :       0,        // dsub2_then_hsub
    6858             :       0,        // dsub2_then_ssub
    6859             :       0,        // qsub1_then_bsub
    6860             :       0,        // qsub1_then_dsub
    6861             :       0,        // qsub1_then_hsub
    6862             :       0,        // qsub1_then_ssub
    6863             :       0,        // qsub3_then_bsub
    6864             :       0,        // qsub3_then_dsub
    6865             :       0,        // qsub3_then_hsub
    6866             :       0,        // qsub3_then_ssub
    6867             :       0,        // qsub2_then_bsub
    6868             :       0,        // qsub2_then_dsub
    6869             :       0,        // qsub2_then_hsub
    6870             :       0,        // qsub2_then_ssub
    6871             :       0,        // subo64_then_sub_32
    6872             :       0,        // dsub0_dsub1
    6873             :       0,        // dsub0_dsub1_dsub2
    6874             :       0,        // dsub1_dsub2
    6875             :       0,        // dsub1_dsub2_dsub3
    6876             :       0,        // dsub2_dsub3
    6877             :       0,        // dsub_qsub1_then_dsub
    6878             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6879             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6880             :       0,        // qsub0_qsub1
    6881             :       0,        // qsub0_qsub1_qsub2
    6882             :       0,        // qsub1_qsub2
    6883             :       0,        // qsub1_qsub2_qsub3
    6884             :       0,        // qsub2_qsub3
    6885             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6886             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6887             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6888             :       0,        // sub_32_subo64_then_sub_32
    6889             :     },
    6890             :     {   // GPR32sp
    6891             :       0,        // bsub
    6892             :       0,        // dsub
    6893             :       0,        // dsub0
    6894             :       0,        // dsub1
    6895             :       0,        // dsub2
    6896             :       0,        // dsub3
    6897             :       0,        // hsub
    6898             :       0,        // qhisub
    6899             :       0,        // qsub
    6900             :       0,        // qsub0
    6901             :       0,        // qsub1
    6902             :       0,        // qsub2
    6903             :       0,        // qsub3
    6904             :       0,        // ssub
    6905             :       0,        // sub_32
    6906             :       0,        // sube32
    6907             :       0,        // sube64
    6908             :       0,        // subo32
    6909             :       0,        // subo64
    6910             :       0,        // zsub
    6911             :       0,        // zsub_hi
    6912             :       0,        // dsub1_then_bsub
    6913             :       0,        // dsub1_then_hsub
    6914             :       0,        // dsub1_then_ssub
    6915             :       0,        // dsub3_then_bsub
    6916             :       0,        // dsub3_then_hsub
    6917             :       0,        // dsub3_then_ssub
    6918             :       0,        // dsub2_then_bsub
    6919             :       0,        // dsub2_then_hsub
    6920             :       0,        // dsub2_then_ssub
    6921             :       0,        // qsub1_then_bsub
    6922             :       0,        // qsub1_then_dsub
    6923             :       0,        // qsub1_then_hsub
    6924             :       0,        // qsub1_then_ssub
    6925             :       0,        // qsub3_then_bsub
    6926             :       0,        // qsub3_then_dsub
    6927             :       0,        // qsub3_then_hsub
    6928             :       0,        // qsub3_then_ssub
    6929             :       0,        // qsub2_then_bsub
    6930             :       0,        // qsub2_then_dsub
    6931             :       0,        // qsub2_then_hsub
    6932             :       0,        // qsub2_then_ssub
    6933             :       0,        // subo64_then_sub_32
    6934             :       0,        // dsub0_dsub1
    6935             :       0,        // dsub0_dsub1_dsub2
    6936             :       0,        // dsub1_dsub2
    6937             :       0,        // dsub1_dsub2_dsub3
    6938             :       0,        // dsub2_dsub3
    6939             :       0,        // dsub_qsub1_then_dsub
    6940             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6941             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    6942             :       0,        // qsub0_qsub1
    6943             :       0,        // qsub0_qsub1_qsub2
    6944             :       0,        // qsub1_qsub2
    6945             :       0,        // qsub1_qsub2_qsub3
    6946             :       0,        // qsub2_qsub3
    6947             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    6948             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    6949             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    6950             :       0,        // sub_32_subo64_then_sub_32
    6951             :     },
    6952             :     {   // GPR32common
    6953             :       0,        // bsub
    6954             :       0,        // dsub
    6955             :       0,        // dsub0
    6956             :       0,        // dsub1
    6957             :       0,        // dsub2
    6958             :       0,        // dsub3
    6959             :       0,        // hsub
    6960             :       0,        // qhisub
    6961             :       0,        // qsub
    6962             :       0,        // qsub0
    6963             :       0,        // qsub1
    6964             :       0,        // qsub2
    6965             :       0,        // qsub3
    6966             :       0,        // ssub
    6967             :       0,        // sub_32
    6968             :       0,        // sube32
    6969             :       0,        // sube64
    6970             :       0,        // subo32
    6971             :       0,        // subo64
    6972             :       0,        // zsub
    6973             :       0,        // zsub_hi
    6974             :       0,        // dsub1_then_bsub
    6975             :       0,        // dsub1_then_hsub
    6976             :       0,        // dsub1_then_ssub
    6977             :       0,        // dsub3_then_bsub
    6978             :       0,        // dsub3_then_hsub
    6979             :       0,        // dsub3_then_ssub
    6980             :       0,        // dsub2_then_bsub
    6981             :       0,        // dsub2_then_hsub
    6982             :       0,        // dsub2_then_ssub
    6983             :       0,        // qsub1_then_bsub
    6984             :       0,        // qsub1_then_dsub
    6985             :       0,        // qsub1_then_hsub
    6986             :       0,        // qsub1_then_ssub
    6987             :       0,        // qsub3_then_bsub
    6988             :       0,        // qsub3_then_dsub
    6989             :       0,        // qsub3_then_hsub
    6990             :       0,        // qsub3_then_ssub
    6991             :       0,        // qsub2_then_bsub
    6992             :       0,        // qsub2_then_dsub
    6993             :       0,        // qsub2_then_hsub
    6994             :       0,        // qsub2_then_ssub
    6995             :       0,        // subo64_then_sub_32
    6996             :       0,        // dsub0_dsub1
    6997             :       0,        // dsub0_dsub1_dsub2
    6998             :       0,        // dsub1_dsub2
    6999             :       0,        // dsub1_dsub2_dsub3
    7000             :       0,        // dsub2_dsub3
    7001             :       0,        // dsub_qsub1_then_dsub
    7002             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7003             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7004             :       0,        // qsub0_qsub1
    7005             :       0,        // qsub0_qsub1_qsub2
    7006             :       0,        // qsub1_qsub2
    7007             :       0,        // qsub1_qsub2_qsub3
    7008             :       0,        // qsub2_qsub3
    7009             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7010             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7011             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7012             :       0,        // sub_32_subo64_then_sub_32
    7013             :     },
    7014             :     {   // CCR
    7015             :       0,        // bsub
    7016             :       0,        // dsub
    7017             :       0,        // dsub0
    7018             :       0,        // dsub1
    7019             :       0,        // dsub2
    7020             :       0,        // dsub3
    7021             :       0,        // hsub
    7022             :       0,        // qhisub
    7023             :       0,        // qsub
    7024             :       0,        // qsub0
    7025             :       0,        // qsub1
    7026             :       0,        // qsub2
    7027             :       0,        // qsub3
    7028             :       0,        // ssub
    7029             :       0,        // sub_32
    7030             :       0,        // sube32
    7031             :       0,        // sube64
    7032             :       0,        // subo32
    7033             :       0,        // subo64
    7034             :       0,        // zsub
    7035             :       0,        // zsub_hi
    7036             :       0,        // dsub1_then_bsub
    7037             :       0,        // dsub1_then_hsub
    7038             :       0,        // dsub1_then_ssub
    7039             :       0,        // dsub3_then_bsub
    7040             :       0,        // dsub3_then_hsub
    7041             :       0,        // dsub3_then_ssub
    7042             :       0,        // dsub2_then_bsub
    7043             :       0,        // dsub2_then_hsub
    7044             :       0,        // dsub2_then_ssub
    7045             :       0,        // qsub1_then_bsub
    7046             :       0,        // qsub1_then_dsub
    7047             :       0,        // qsub1_then_hsub
    7048             :       0,        // qsub1_then_ssub
    7049             :       0,        // qsub3_then_bsub
    7050             :       0,        // qsub3_then_dsub
    7051             :       0,        // qsub3_then_hsub
    7052             :       0,        // qsub3_then_ssub
    7053             :       0,        // qsub2_then_bsub
    7054             :       0,        // qsub2_then_dsub
    7055             :       0,        // qsub2_then_hsub
    7056             :       0,        // qsub2_then_ssub
    7057             :       0,        // subo64_then_sub_32
    7058             :       0,        // dsub0_dsub1
    7059             :       0,        // dsub0_dsub1_dsub2
    7060             :       0,        // dsub1_dsub2
    7061             :       0,        // dsub1_dsub2_dsub3
    7062             :       0,        // dsub2_dsub3
    7063             :       0,        // dsub_qsub1_then_dsub
    7064             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7065             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7066             :       0,        // qsub0_qsub1
    7067             :       0,        // qsub0_qsub1_qsub2
    7068             :       0,        // qsub1_qsub2
    7069             :       0,        // qsub1_qsub2_qsub3
    7070             :       0,        // qsub2_qsub3
    7071             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7072             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7073             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7074             :       0,        // sub_32_subo64_then_sub_32
    7075             :     },
    7076             :     {   // GPR32sponly
    7077             :       0,        // bsub
    7078             :       0,        // dsub
    7079             :       0,        // dsub0
    7080             :       0,        // dsub1
    7081             :       0,        // dsub2
    7082             :       0,        // dsub3
    7083             :       0,        // hsub
    7084             :       0,        // qhisub
    7085             :       0,        // qsub
    7086             :       0,        // qsub0
    7087             :       0,        // qsub1
    7088             :       0,        // qsub2
    7089             :       0,        // qsub3
    7090             :       0,        // ssub
    7091             :       0,        // sub_32
    7092             :       0,        // sube32
    7093             :       0,        // sube64
    7094             :       0,        // subo32
    7095             :       0,        // subo64
    7096             :       0,        // zsub
    7097             :       0,        // zsub_hi
    7098             :       0,        // dsub1_then_bsub
    7099             :       0,        // dsub1_then_hsub
    7100             :       0,        // dsub1_then_ssub
    7101             :       0,        // dsub3_then_bsub
    7102             :       0,        // dsub3_then_hsub
    7103             :       0,        // dsub3_then_ssub
    7104             :       0,        // dsub2_then_bsub
    7105             :       0,        // dsub2_then_hsub
    7106             :       0,        // dsub2_then_ssub
    7107             :       0,        // qsub1_then_bsub
    7108             :       0,        // qsub1_then_dsub
    7109             :       0,        // qsub1_then_hsub
    7110             :       0,        // qsub1_then_ssub
    7111             :       0,        // qsub3_then_bsub
    7112             :       0,        // qsub3_then_dsub
    7113             :       0,        // qsub3_then_hsub
    7114             :       0,        // qsub3_then_ssub
    7115             :       0,        // qsub2_then_bsub
    7116             :       0,        // qsub2_then_dsub
    7117             :       0,        // qsub2_then_hsub
    7118             :       0,        // qsub2_then_ssub
    7119             :       0,        // subo64_then_sub_32
    7120             :       0,        // dsub0_dsub1
    7121             :       0,        // dsub0_dsub1_dsub2
    7122             :       0,        // dsub1_dsub2
    7123             :       0,        // dsub1_dsub2_dsub3
    7124             :       0,        // dsub2_dsub3
    7125             :       0,        // dsub_qsub1_then_dsub
    7126             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7127             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7128             :       0,        // qsub0_qsub1
    7129             :       0,        // qsub0_qsub1_qsub2
    7130             :       0,        // qsub1_qsub2
    7131             :       0,        // qsub1_qsub2_qsub3
    7132             :       0,        // qsub2_qsub3
    7133             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7134             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7135             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7136             :       0,        // sub_32_subo64_then_sub_32
    7137             :     },
    7138             :     {   // WSeqPairsClass
    7139             :       0,        // bsub
    7140             :       0,        // dsub
    7141             :       0,        // dsub0
    7142             :       0,        // dsub1
    7143             :       0,        // dsub2
    7144             :       0,        // dsub3
    7145             :       0,        // hsub
    7146             :       0,        // qhisub
    7147             :       0,        // qsub
    7148             :       0,        // qsub0
    7149             :       0,        // qsub1
    7150             :       0,        // qsub2
    7151             :       0,        // qsub3
    7152             :       0,        // ssub
    7153             :       0,        // sub_32
    7154             :       12,       // sube32 -> WSeqPairsClass
    7155             :       0,        // sube64
    7156             :       12,       // subo32 -> WSeqPairsClass
    7157             :       0,        // subo64
    7158             :       0,        // zsub
    7159             :       0,        // zsub_hi
    7160             :       0,        // dsub1_then_bsub
    7161             :       0,        // dsub1_then_hsub
    7162             :       0,        // dsub1_then_ssub
    7163             :       0,        // dsub3_then_bsub
    7164             :       0,        // dsub3_then_hsub
    7165             :       0,        // dsub3_then_ssub
    7166             :       0,        // dsub2_then_bsub
    7167             :       0,        // dsub2_then_hsub
    7168             :       0,        // dsub2_then_ssub
    7169             :       0,        // qsub1_then_bsub
    7170             :       0,        // qsub1_then_dsub
    7171             :       0,        // qsub1_then_hsub
    7172             :       0,        // qsub1_then_ssub
    7173             :       0,        // qsub3_then_bsub
    7174             :       0,        // qsub3_then_dsub
    7175             :       0,        // qsub3_then_hsub
    7176             :       0,        // qsub3_then_ssub
    7177             :       0,        // qsub2_then_bsub
    7178             :       0,        // qsub2_then_dsub
    7179             :       0,        // qsub2_then_hsub
    7180             :       0,        // qsub2_then_ssub
    7181             :       0,        // subo64_then_sub_32
    7182             :       0,        // dsub0_dsub1
    7183             :       0,        // dsub0_dsub1_dsub2
    7184             :       0,        // dsub1_dsub2
    7185             :       0,        // dsub1_dsub2_dsub3
    7186             :       0,        // dsub2_dsub3
    7187             :       0,        // dsub_qsub1_then_dsub
    7188             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7189             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7190             :       0,        // qsub0_qsub1
    7191             :       0,        // qsub0_qsub1_qsub2
    7192             :       0,        // qsub1_qsub2
    7193             :       0,        // qsub1_qsub2_qsub3
    7194             :       0,        // qsub2_qsub3
    7195             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7196             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7197             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7198             :       0,        // sub_32_subo64_then_sub_32
    7199             :     },
    7200             :     {   // WSeqPairsClass_with_sube32_in_GPR32common
    7201             :       0,        // bsub
    7202             :       0,        // dsub
    7203             :       0,        // dsub0
    7204             :       0,        // dsub1
    7205             :       0,        // dsub2
    7206             :       0,        // dsub3
    7207             :       0,        // hsub
    7208             :       0,        // qhisub
    7209             :       0,        // qsub
    7210             :       0,        // qsub0
    7211             :       0,        // qsub1
    7212             :       0,        // qsub2
    7213             :       0,        // qsub3
    7214             :       0,        // ssub
    7215             :       0,        // sub_32
    7216             :       13,       // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common
    7217             :       0,        // sube64
    7218             :       13,       // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common
    7219             :       0,        // subo64
    7220             :       0,        // zsub
    7221             :       0,        // zsub_hi
    7222             :       0,        // dsub1_then_bsub
    7223             :       0,        // dsub1_then_hsub
    7224             :       0,        // dsub1_then_ssub
    7225             :       0,        // dsub3_then_bsub
    7226             :       0,        // dsub3_then_hsub
    7227             :       0,        // dsub3_then_ssub
    7228             :       0,        // dsub2_then_bsub
    7229             :       0,        // dsub2_then_hsub
    7230             :       0,        // dsub2_then_ssub
    7231             :       0,        // qsub1_then_bsub
    7232             :       0,        // qsub1_then_dsub
    7233             :       0,        // qsub1_then_hsub
    7234             :       0,        // qsub1_then_ssub
    7235             :       0,        // qsub3_then_bsub
    7236             :       0,        // qsub3_then_dsub
    7237             :       0,        // qsub3_then_hsub
    7238             :       0,        // qsub3_then_ssub
    7239             :       0,        // qsub2_then_bsub
    7240             :       0,        // qsub2_then_dsub
    7241             :       0,        // qsub2_then_hsub
    7242             :       0,        // qsub2_then_ssub
    7243             :       0,        // subo64_then_sub_32
    7244             :       0,        // dsub0_dsub1
    7245             :       0,        // dsub0_dsub1_dsub2
    7246             :       0,        // dsub1_dsub2
    7247             :       0,        // dsub1_dsub2_dsub3
    7248             :       0,        // dsub2_dsub3
    7249             :       0,        // dsub_qsub1_then_dsub
    7250             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7251             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7252             :       0,        // qsub0_qsub1
    7253             :       0,        // qsub0_qsub1_qsub2
    7254             :       0,        // qsub1_qsub2
    7255             :       0,        // qsub1_qsub2_qsub3
    7256             :       0,        // qsub2_qsub3
    7257             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7258             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7259             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7260             :       0,        // sub_32_subo64_then_sub_32
    7261             :     },
    7262             :     {   // WSeqPairsClass_with_subo32_in_GPR32common
    7263             :       0,        // bsub
    7264             :       0,        // dsub
    7265             :       0,        // dsub0
    7266             :       0,        // dsub1
    7267             :       0,        // dsub2
    7268             :       0,        // dsub3
    7269             :       0,        // hsub
    7270             :       0,        // qhisub
    7271             :       0,        // qsub
    7272             :       0,        // qsub0
    7273             :       0,        // qsub1
    7274             :       0,        // qsub2
    7275             :       0,        // qsub3
    7276             :       0,        // ssub
    7277             :       0,        // sub_32
    7278             :       14,       // sube32 -> WSeqPairsClass_with_subo32_in_GPR32common
    7279             :       0,        // sube64
    7280             :       14,       // subo32 -> WSeqPairsClass_with_subo32_in_GPR32common
    7281             :       0,        // subo64
    7282             :       0,        // zsub
    7283             :       0,        // zsub_hi
    7284             :       0,        // dsub1_then_bsub
    7285             :       0,        // dsub1_then_hsub
    7286             :       0,        // dsub1_then_ssub
    7287             :       0,        // dsub3_then_bsub
    7288             :       0,        // dsub3_then_hsub
    7289             :       0,        // dsub3_then_ssub
    7290             :       0,        // dsub2_then_bsub
    7291             :       0,        // dsub2_then_hsub
    7292             :       0,        // dsub2_then_ssub
    7293             :       0,        // qsub1_then_bsub
    7294             :       0,        // qsub1_then_dsub
    7295             :       0,        // qsub1_then_hsub
    7296             :       0,        // qsub1_then_ssub
    7297             :       0,        // qsub3_then_bsub
    7298             :       0,        // qsub3_then_dsub
    7299             :       0,        // qsub3_then_hsub
    7300             :       0,        // qsub3_then_ssub
    7301             :       0,        // qsub2_then_bsub
    7302             :       0,        // qsub2_then_dsub
    7303             :       0,        // qsub2_then_hsub
    7304             :       0,        // qsub2_then_ssub
    7305             :       0,        // subo64_then_sub_32
    7306             :       0,        // dsub0_dsub1
    7307             :       0,        // dsub0_dsub1_dsub2
    7308             :       0,        // dsub1_dsub2
    7309             :       0,        // dsub1_dsub2_dsub3
    7310             :       0,        // dsub2_dsub3
    7311             :       0,        // dsub_qsub1_then_dsub
    7312             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7313             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7314             :       0,        // qsub0_qsub1
    7315             :       0,        // qsub0_qsub1_qsub2
    7316             :       0,        // qsub1_qsub2
    7317             :       0,        // qsub1_qsub2_qsub3
    7318             :       0,        // qsub2_qsub3
    7319             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7320             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7321             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7322             :       0,        // sub_32_subo64_then_sub_32
    7323             :     },
    7324             :     {   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    7325             :       0,        // bsub
    7326             :       0,        // dsub
    7327             :       0,        // dsub0
    7328             :       0,        // dsub1
    7329             :       0,        // dsub2
    7330             :       0,        // dsub3
    7331             :       0,        // hsub
    7332             :       0,        // qhisub
    7333             :       0,        // qsub
    7334             :       0,        // qsub0
    7335             :       0,        // qsub1
    7336             :       0,        // qsub2
    7337             :       0,        // qsub3
    7338             :       0,        // ssub
    7339             :       0,        // sub_32
    7340             :       15,       // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    7341             :       0,        // sube64
    7342             :       15,       // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    7343             :       0,        // subo64
    7344             :       0,        // zsub
    7345             :       0,        // zsub_hi
    7346             :       0,        // dsub1_then_bsub
    7347             :       0,        // dsub1_then_hsub
    7348             :       0,        // dsub1_then_ssub
    7349             :       0,        // dsub3_then_bsub
    7350             :       0,        // dsub3_then_hsub
    7351             :       0,        // dsub3_then_ssub
    7352             :       0,        // dsub2_then_bsub
    7353             :       0,        // dsub2_then_hsub
    7354             :       0,        // dsub2_then_ssub
    7355             :       0,        // qsub1_then_bsub
    7356             :       0,        // qsub1_then_dsub
    7357             :       0,        // qsub1_then_hsub
    7358             :       0,        // qsub1_then_ssub
    7359             :       0,        // qsub3_then_bsub
    7360             :       0,        // qsub3_then_dsub
    7361             :       0,        // qsub3_then_hsub
    7362             :       0,        // qsub3_then_ssub
    7363             :       0,        // qsub2_then_bsub
    7364             :       0,        // qsub2_then_dsub
    7365             :       0,        // qsub2_then_hsub
    7366             :       0,        // qsub2_then_ssub
    7367             :       0,        // subo64_then_sub_32
    7368             :       0,        // dsub0_dsub1
    7369             :       0,        // dsub0_dsub1_dsub2
    7370             :       0,        // dsub1_dsub2
    7371             :       0,        // dsub1_dsub2_dsub3
    7372             :       0,        // dsub2_dsub3
    7373             :       0,        // dsub_qsub1_then_dsub
    7374             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7375             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7376             :       0,        // qsub0_qsub1
    7377             :       0,        // qsub0_qsub1_qsub2
    7378             :       0,        // qsub1_qsub2
    7379             :       0,        // qsub1_qsub2_qsub3
    7380             :       0,        // qsub2_qsub3
    7381             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7382             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7383             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7384             :       0,        // sub_32_subo64_then_sub_32
    7385             :     },
    7386             :     {   // GPR64all
    7387             :       0,        // bsub
    7388             :       0,        // dsub
    7389             :       0,        // dsub0
    7390             :       0,        // dsub1
    7391             :       0,        // dsub2
    7392             :       0,        // dsub3
    7393             :       0,        // hsub
    7394             :       0,        // qhisub
    7395             :       0,        // qsub
    7396             :       0,        // qsub0
    7397             :       0,        // qsub1
    7398             :       0,        // qsub2
    7399             :       0,        // qsub3
    7400             :       0,        // ssub
    7401             :       16,       // sub_32 -> GPR64all
    7402             :       0,        // sube32
    7403             :       0,        // sube64
    7404             :       0,        // subo32
    7405             :       0,        // subo64
    7406             :       0,        // zsub
    7407             :       0,        // zsub_hi
    7408             :       0,        // dsub1_then_bsub
    7409             :       0,        // dsub1_then_hsub
    7410             :       0,        // dsub1_then_ssub
    7411             :       0,        // dsub3_then_bsub
    7412             :       0,        // dsub3_then_hsub
    7413             :       0,        // dsub3_then_ssub
    7414             :       0,        // dsub2_then_bsub
    7415             :       0,        // dsub2_then_hsub
    7416             :       0,        // dsub2_then_ssub
    7417             :       0,        // qsub1_then_bsub
    7418             :       0,        // qsub1_then_dsub
    7419             :       0,        // qsub1_then_hsub
    7420             :       0,        // qsub1_then_ssub
    7421             :       0,        // qsub3_then_bsub
    7422             :       0,        // qsub3_then_dsub
    7423             :       0,        // qsub3_then_hsub
    7424             :       0,        // qsub3_then_ssub
    7425             :       0,        // qsub2_then_bsub
    7426             :       0,        // qsub2_then_dsub
    7427             :       0,        // qsub2_then_hsub
    7428             :       0,        // qsub2_then_ssub
    7429             :       0,        // subo64_then_sub_32
    7430             :       0,        // dsub0_dsub1
    7431             :       0,        // dsub0_dsub1_dsub2
    7432             :       0,        // dsub1_dsub2
    7433             :       0,        // dsub1_dsub2_dsub3
    7434             :       0,        // dsub2_dsub3
    7435             :       0,        // dsub_qsub1_then_dsub
    7436             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7437             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7438             :       0,        // qsub0_qsub1
    7439             :       0,        // qsub0_qsub1_qsub2
    7440             :       0,        // qsub1_qsub2
    7441             :       0,        // qsub1_qsub2_qsub3
    7442             :       0,        // qsub2_qsub3
    7443             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7444             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7445             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7446             :       0,        // sub_32_subo64_then_sub_32
    7447             :     },
    7448             :     {   // FPR64
    7449             :       17,       // bsub -> FPR64
    7450             :       0,        // dsub
    7451             :       0,        // dsub0
    7452             :       0,        // dsub1
    7453             :       0,        // dsub2
    7454             :       0,        // dsub3
    7455             :       17,       // hsub -> FPR64
    7456             :       0,        // qhisub
    7457             :       0,        // qsub
    7458             :       0,        // qsub0
    7459             :       0,        // qsub1
    7460             :       0,        // qsub2
    7461             :       0,        // qsub3
    7462             :       17,       // ssub -> FPR64
    7463             :       0,        // sub_32
    7464             :       0,        // sube32
    7465             :       0,        // sube64
    7466             :       0,        // subo32
    7467             :       0,        // subo64
    7468             :       0,        // zsub
    7469             :       0,        // zsub_hi
    7470             :       0,        // dsub1_then_bsub
    7471             :       0,        // dsub1_then_hsub
    7472             :       0,        // dsub1_then_ssub
    7473             :       0,        // dsub3_then_bsub
    7474             :       0,        // dsub3_then_hsub
    7475             :       0,        // dsub3_then_ssub
    7476             :       0,        // dsub2_then_bsub
    7477             :       0,        // dsub2_then_hsub
    7478             :       0,        // dsub2_then_ssub
    7479             :       0,        // qsub1_then_bsub
    7480             :       0,        // qsub1_then_dsub
    7481             :       0,        // qsub1_then_hsub
    7482             :       0,        // qsub1_then_ssub
    7483             :       0,        // qsub3_then_bsub
    7484             :       0,        // qsub3_then_dsub
    7485             :       0,        // qsub3_then_hsub
    7486             :       0,        // qsub3_then_ssub
    7487             :       0,        // qsub2_then_bsub
    7488             :       0,        // qsub2_then_dsub
    7489             :       0,        // qsub2_then_hsub
    7490             :       0,        // qsub2_then_ssub
    7491             :       0,        // subo64_then_sub_32
    7492             :       0,        // dsub0_dsub1
    7493             :       0,        // dsub0_dsub1_dsub2
    7494             :       0,        // dsub1_dsub2
    7495             :       0,        // dsub1_dsub2_dsub3
    7496             :       0,        // dsub2_dsub3
    7497             :       0,        // dsub_qsub1_then_dsub
    7498             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7499             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7500             :       0,        // qsub0_qsub1
    7501             :       0,        // qsub0_qsub1_qsub2
    7502             :       0,        // qsub1_qsub2
    7503             :       0,        // qsub1_qsub2_qsub3
    7504             :       0,        // qsub2_qsub3
    7505             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7506             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7507             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7508             :       0,        // sub_32_subo64_then_sub_32
    7509             :     },
    7510             :     {   // GPR64
    7511             :       0,        // bsub
    7512             :       0,        // dsub
    7513             :       0,        // dsub0
    7514             :       0,        // dsub1
    7515             :       0,        // dsub2
    7516             :       0,        // dsub3
    7517             :       0,        // hsub
    7518             :       0,        // qhisub
    7519             :       0,        // qsub
    7520             :       0,        // qsub0
    7521             :       0,        // qsub1
    7522             :       0,        // qsub2
    7523             :       0,        // qsub3
    7524             :       0,        // ssub
    7525             :       18,       // sub_32 -> GPR64
    7526             :       0,        // sube32
    7527             :       0,        // sube64
    7528             :       0,        // subo32
    7529             :       0,        // subo64
    7530             :       0,        // zsub
    7531             :       0,        // zsub_hi
    7532             :       0,        // dsub1_then_bsub
    7533             :       0,        // dsub1_then_hsub
    7534             :       0,        // dsub1_then_ssub
    7535             :       0,        // dsub3_then_bsub
    7536             :       0,        // dsub3_then_hsub
    7537             :       0,        // dsub3_then_ssub
    7538             :       0,        // dsub2_then_bsub
    7539             :       0,        // dsub2_then_hsub
    7540             :       0,        // dsub2_then_ssub
    7541             :       0,        // qsub1_then_bsub
    7542             :       0,        // qsub1_then_dsub
    7543             :       0,        // qsub1_then_hsub
    7544             :       0,        // qsub1_then_ssub
    7545             :       0,        // qsub3_then_bsub
    7546             :       0,        // qsub3_then_dsub
    7547             :       0,        // qsub3_then_hsub
    7548             :       0,        // qsub3_then_ssub
    7549             :       0,        // qsub2_then_bsub
    7550             :       0,        // qsub2_then_dsub
    7551             :       0,        // qsub2_then_hsub
    7552             :       0,        // qsub2_then_ssub
    7553             :       0,        // subo64_then_sub_32
    7554             :       0,        // dsub0_dsub1
    7555             :       0,        // dsub0_dsub1_dsub2
    7556             :       0,        // dsub1_dsub2
    7557             :       0,        // dsub1_dsub2_dsub3
    7558             :       0,        // dsub2_dsub3
    7559             :       0,        // dsub_qsub1_then_dsub
    7560             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7561             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7562             :       0,        // qsub0_qsub1
    7563             :       0,        // qsub0_qsub1_qsub2
    7564             :       0,        // qsub1_qsub2
    7565             :       0,        // qsub1_qsub2_qsub3
    7566             :       0,        // qsub2_qsub3
    7567             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7568             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7569             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7570             :       0,        // sub_32_subo64_then_sub_32
    7571             :     },
    7572             :     {   // GPR64sp
    7573             :       0,        // bsub
    7574             :       0,        // dsub
    7575             :       0,        // dsub0
    7576             :       0,        // dsub1
    7577             :       0,        // dsub2
    7578             :       0,        // dsub3
    7579             :       0,        // hsub
    7580             :       0,        // qhisub
    7581             :       0,        // qsub
    7582             :       0,        // qsub0
    7583             :       0,        // qsub1
    7584             :       0,        // qsub2
    7585             :       0,        // qsub3
    7586             :       0,        // ssub
    7587             :       19,       // sub_32 -> GPR64sp
    7588             :       0,        // sube32
    7589             :       0,        // sube64
    7590             :       0,        // subo32
    7591             :       0,        // subo64
    7592             :       0,        // zsub
    7593             :       0,        // zsub_hi
    7594             :       0,        // dsub1_then_bsub
    7595             :       0,        // dsub1_then_hsub
    7596             :       0,        // dsub1_then_ssub
    7597             :       0,        // dsub3_then_bsub
    7598             :       0,        // dsub3_then_hsub
    7599             :       0,        // dsub3_then_ssub
    7600             :       0,        // dsub2_then_bsub
    7601             :       0,        // dsub2_then_hsub
    7602             :       0,        // dsub2_then_ssub
    7603             :       0,        // qsub1_then_bsub
    7604             :       0,        // qsub1_then_dsub
    7605             :       0,        // qsub1_then_hsub
    7606             :       0,        // qsub1_then_ssub
    7607             :       0,        // qsub3_then_bsub
    7608             :       0,        // qsub3_then_dsub
    7609             :       0,        // qsub3_then_hsub
    7610             :       0,        // qsub3_then_ssub
    7611             :       0,        // qsub2_then_bsub
    7612             :       0,        // qsub2_then_dsub
    7613             :       0,        // qsub2_then_hsub
    7614             :       0,        // qsub2_then_ssub
    7615             :       0,        // subo64_then_sub_32
    7616             :       0,        // dsub0_dsub1
    7617             :       0,        // dsub0_dsub1_dsub2
    7618             :       0,        // dsub1_dsub2
    7619             :       0,        // dsub1_dsub2_dsub3
    7620             :       0,        // dsub2_dsub3
    7621             :       0,        // dsub_qsub1_then_dsub
    7622             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7623             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7624             :       0,        // qsub0_qsub1
    7625             :       0,        // qsub0_qsub1_qsub2
    7626             :       0,        // qsub1_qsub2
    7627             :       0,        // qsub1_qsub2_qsub3
    7628             :       0,        // qsub2_qsub3
    7629             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7630             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7631             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7632             :       0,        // sub_32_subo64_then_sub_32
    7633             :     },
    7634             :     {   // GPR64common
    7635             :       0,        // bsub
    7636             :       0,        // dsub
    7637             :       0,        // dsub0
    7638             :       0,        // dsub1
    7639             :       0,        // dsub2
    7640             :       0,        // dsub3
    7641             :       0,        // hsub
    7642             :       0,        // qhisub
    7643             :       0,        // qsub
    7644             :       0,        // qsub0
    7645             :       0,        // qsub1
    7646             :       0,        // qsub2
    7647             :       0,        // qsub3
    7648             :       0,        // ssub
    7649             :       20,       // sub_32 -> GPR64common
    7650             :       0,        // sube32
    7651             :       0,        // sube64
    7652             :       0,        // subo32
    7653             :       0,        // subo64
    7654             :       0,        // zsub
    7655             :       0,        // zsub_hi
    7656             :       0,        // dsub1_then_bsub
    7657             :       0,        // dsub1_then_hsub
    7658             :       0,        // dsub1_then_ssub
    7659             :       0,        // dsub3_then_bsub
    7660             :       0,        // dsub3_then_hsub
    7661             :       0,        // dsub3_then_ssub
    7662             :       0,        // dsub2_then_bsub
    7663             :       0,        // dsub2_then_hsub
    7664             :       0,        // dsub2_then_ssub
    7665             :       0,        // qsub1_then_bsub
    7666             :       0,        // qsub1_then_dsub
    7667             :       0,        // qsub1_then_hsub
    7668             :       0,        // qsub1_then_ssub
    7669             :       0,        // qsub3_then_bsub
    7670             :       0,        // qsub3_then_dsub
    7671             :       0,        // qsub3_then_hsub
    7672             :       0,        // qsub3_then_ssub
    7673             :       0,        // qsub2_then_bsub
    7674             :       0,        // qsub2_then_dsub
    7675             :       0,        // qsub2_then_hsub
    7676             :       0,        // qsub2_then_ssub
    7677             :       0,        // subo64_then_sub_32
    7678             :       0,        // dsub0_dsub1
    7679             :       0,        // dsub0_dsub1_dsub2
    7680             :       0,        // dsub1_dsub2
    7681             :       0,        // dsub1_dsub2_dsub3
    7682             :       0,        // dsub2_dsub3
    7683             :       0,        // dsub_qsub1_then_dsub
    7684             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7685             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7686             :       0,        // qsub0_qsub1
    7687             :       0,        // qsub0_qsub1_qsub2
    7688             :       0,        // qsub1_qsub2
    7689             :       0,        // qsub1_qsub2_qsub3
    7690             :       0,        // qsub2_qsub3
    7691             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7692             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7693             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7694             :       0,        // sub_32_subo64_then_sub_32
    7695             :     },
    7696             :     {   // tcGPR64
    7697             :       0,        // bsub
    7698             :       0,        // dsub
    7699             :       0,        // dsub0
    7700             :       0,        // dsub1
    7701             :       0,        // dsub2
    7702             :       0,        // dsub3
    7703             :       0,        // hsub
    7704             :       0,        // qhisub
    7705             :       0,        // qsub
    7706             :       0,        // qsub0
    7707             :       0,        // qsub1
    7708             :       0,        // qsub2
    7709             :       0,        // qsub3
    7710             :       0,        // ssub
    7711             :       21,       // sub_32 -> tcGPR64
    7712             :       0,        // sube32
    7713             :       0,        // sube64
    7714             :       0,        // subo32
    7715             :       0,        // subo64
    7716             :       0,        // zsub
    7717             :       0,        // zsub_hi
    7718             :       0,        // dsub1_then_bsub
    7719             :       0,        // dsub1_then_hsub
    7720             :       0,        // dsub1_then_ssub
    7721             :       0,        // dsub3_then_bsub
    7722             :       0,        // dsub3_then_hsub
    7723             :       0,        // dsub3_then_ssub
    7724             :       0,        // dsub2_then_bsub
    7725             :       0,        // dsub2_then_hsub
    7726             :       0,        // dsub2_then_ssub
    7727             :       0,        // qsub1_then_bsub
    7728             :       0,        // qsub1_then_dsub
    7729             :       0,        // qsub1_then_hsub
    7730             :       0,        // qsub1_then_ssub
    7731             :       0,        // qsub3_then_bsub
    7732             :       0,        // qsub3_then_dsub
    7733             :       0,        // qsub3_then_hsub
    7734             :       0,        // qsub3_then_ssub
    7735             :       0,        // qsub2_then_bsub
    7736             :       0,        // qsub2_then_dsub
    7737             :       0,        // qsub2_then_hsub
    7738             :       0,        // qsub2_then_ssub
    7739             :       0,        // subo64_then_sub_32
    7740             :       0,        // dsub0_dsub1
    7741             :       0,        // dsub0_dsub1_dsub2
    7742             :       0,        // dsub1_dsub2
    7743             :       0,        // dsub1_dsub2_dsub3
    7744             :       0,        // dsub2_dsub3
    7745             :       0,        // dsub_qsub1_then_dsub
    7746             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7747             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7748             :       0,        // qsub0_qsub1
    7749             :       0,        // qsub0_qsub1_qsub2
    7750             :       0,        // qsub1_qsub2
    7751             :       0,        // qsub1_qsub2_qsub3
    7752             :       0,        // qsub2_qsub3
    7753             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7754             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7755             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7756             :       0,        // sub_32_subo64_then_sub_32
    7757             :     },
    7758             :     {   // GPR64sponly
    7759             :       0,        // bsub
    7760             :       0,        // dsub
    7761             :       0,        // dsub0
    7762             :       0,        // dsub1
    7763             :       0,        // dsub2
    7764             :       0,        // dsub3
    7765             :       0,        // hsub
    7766             :       0,        // qhisub
    7767             :       0,        // qsub
    7768             :       0,        // qsub0
    7769             :       0,        // qsub1
    7770             :       0,        // qsub2
    7771             :       0,        // qsub3
    7772             :       0,        // ssub
    7773             :       22,       // sub_32 -> GPR64sponly
    7774             :       0,        // sube32
    7775             :       0,        // sube64
    7776             :       0,        // subo32
    7777             :       0,        // subo64
    7778             :       0,        // zsub
    7779             :       0,        // zsub_hi
    7780             :       0,        // dsub1_then_bsub
    7781             :       0,        // dsub1_then_hsub
    7782             :       0,        // dsub1_then_ssub
    7783             :       0,        // dsub3_then_bsub
    7784             :       0,        // dsub3_then_hsub
    7785             :       0,        // dsub3_then_ssub
    7786             :       0,        // dsub2_then_bsub
    7787             :       0,        // dsub2_then_hsub
    7788             :       0,        // dsub2_then_ssub
    7789             :       0,        // qsub1_then_bsub
    7790             :       0,        // qsub1_then_dsub
    7791             :       0,        // qsub1_then_hsub
    7792             :       0,        // qsub1_then_ssub
    7793             :       0,        // qsub3_then_bsub
    7794             :       0,        // qsub3_then_dsub
    7795             :       0,        // qsub3_then_hsub
    7796             :       0,        // qsub3_then_ssub
    7797             :       0,        // qsub2_then_bsub
    7798             :       0,        // qsub2_then_dsub
    7799             :       0,        // qsub2_then_hsub
    7800             :       0,        // qsub2_then_ssub
    7801             :       0,        // subo64_then_sub_32
    7802             :       0,        // dsub0_dsub1
    7803             :       0,        // dsub0_dsub1_dsub2
    7804             :       0,        // dsub1_dsub2
    7805             :       0,        // dsub1_dsub2_dsub3
    7806             :       0,        // dsub2_dsub3
    7807             :       0,        // dsub_qsub1_then_dsub
    7808             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7809             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7810             :       0,        // qsub0_qsub1
    7811             :       0,        // qsub0_qsub1_qsub2
    7812             :       0,        // qsub1_qsub2
    7813             :       0,        // qsub1_qsub2_qsub3
    7814             :       0,        // qsub2_qsub3
    7815             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7816             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7817             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7818             :       0,        // sub_32_subo64_then_sub_32
    7819             :     },
    7820             :     {   // DD
    7821             :       23,       // bsub -> DD
    7822             :       0,        // dsub
    7823             :       23,       // dsub0 -> DD
    7824             :       23,       // dsub1 -> DD
    7825             :       0,        // dsub2
    7826             :       0,        // dsub3
    7827             :       23,       // hsub -> DD
    7828             :       0,        // qhisub
    7829             :       0,        // qsub
    7830             :       0,        // qsub0
    7831             :       0,        // qsub1
    7832             :       0,        // qsub2
    7833             :       0,        // qsub3
    7834             :       23,       // ssub -> DD
    7835             :       0,        // sub_32
    7836             :       0,        // sube32
    7837             :       0,        // sube64
    7838             :       0,        // subo32
    7839             :       0,        // subo64
    7840             :       0,        // zsub
    7841             :       0,        // zsub_hi
    7842             :       23,       // dsub1_then_bsub -> DD
    7843             :       23,       // dsub1_then_hsub -> DD
    7844             :       23,       // dsub1_then_ssub -> DD
    7845             :       0,        // dsub3_then_bsub
    7846             :       0,        // dsub3_then_hsub
    7847             :       0,        // dsub3_then_ssub
    7848             :       0,        // dsub2_then_bsub
    7849             :       0,        // dsub2_then_hsub
    7850             :       0,        // dsub2_then_ssub
    7851             :       0,        // qsub1_then_bsub
    7852             :       0,        // qsub1_then_dsub
    7853             :       0,        // qsub1_then_hsub
    7854             :       0,        // qsub1_then_ssub
    7855             :       0,        // qsub3_then_bsub
    7856             :       0,        // qsub3_then_dsub
    7857             :       0,        // qsub3_then_hsub
    7858             :       0,        // qsub3_then_ssub
    7859             :       0,        // qsub2_then_bsub
    7860             :       0,        // qsub2_then_dsub
    7861             :       0,        // qsub2_then_hsub
    7862             :       0,        // qsub2_then_ssub
    7863             :       0,        // subo64_then_sub_32
    7864             :       0,        // dsub0_dsub1
    7865             :       0,        // dsub0_dsub1_dsub2
    7866             :       0,        // dsub1_dsub2
    7867             :       0,        // dsub1_dsub2_dsub3
    7868             :       0,        // dsub2_dsub3
    7869             :       0,        // dsub_qsub1_then_dsub
    7870             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7871             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7872             :       0,        // qsub0_qsub1
    7873             :       0,        // qsub0_qsub1_qsub2
    7874             :       0,        // qsub1_qsub2
    7875             :       0,        // qsub1_qsub2_qsub3
    7876             :       0,        // qsub2_qsub3
    7877             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7878             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7879             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7880             :       0,        // sub_32_subo64_then_sub_32
    7881             :     },
    7882             :     {   // XSeqPairsClass
    7883             :       0,        // bsub
    7884             :       0,        // dsub
    7885             :       0,        // dsub0
    7886             :       0,        // dsub1
    7887             :       0,        // dsub2
    7888             :       0,        // dsub3
    7889             :       0,        // hsub
    7890             :       0,        // qhisub
    7891             :       0,        // qsub
    7892             :       0,        // qsub0
    7893             :       0,        // qsub1
    7894             :       0,        // qsub2
    7895             :       0,        // qsub3
    7896             :       0,        // ssub
    7897             :       24,       // sub_32 -> XSeqPairsClass
    7898             :       0,        // sube32
    7899             :       24,       // sube64 -> XSeqPairsClass
    7900             :       0,        // subo32
    7901             :       24,       // subo64 -> XSeqPairsClass
    7902             :       0,        // zsub
    7903             :       0,        // zsub_hi
    7904             :       0,        // dsub1_then_bsub
    7905             :       0,        // dsub1_then_hsub
    7906             :       0,        // dsub1_then_ssub
    7907             :       0,        // dsub3_then_bsub
    7908             :       0,        // dsub3_then_hsub
    7909             :       0,        // dsub3_then_ssub
    7910             :       0,        // dsub2_then_bsub
    7911             :       0,        // dsub2_then_hsub
    7912             :       0,        // dsub2_then_ssub
    7913             :       0,        // qsub1_then_bsub
    7914             :       0,        // qsub1_then_dsub
    7915             :       0,        // qsub1_then_hsub
    7916             :       0,        // qsub1_then_ssub
    7917             :       0,        // qsub3_then_bsub
    7918             :       0,        // qsub3_then_dsub
    7919             :       0,        // qsub3_then_hsub
    7920             :       0,        // qsub3_then_ssub
    7921             :       0,        // qsub2_then_bsub
    7922             :       0,        // qsub2_then_dsub
    7923             :       0,        // qsub2_then_hsub
    7924             :       0,        // qsub2_then_ssub
    7925             :       24,       // subo64_then_sub_32 -> XSeqPairsClass
    7926             :       0,        // dsub0_dsub1
    7927             :       0,        // dsub0_dsub1_dsub2
    7928             :       0,        // dsub1_dsub2
    7929             :       0,        // dsub1_dsub2_dsub3
    7930             :       0,        // dsub2_dsub3
    7931             :       0,        // dsub_qsub1_then_dsub
    7932             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7933             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7934             :       0,        // qsub0_qsub1
    7935             :       0,        // qsub0_qsub1_qsub2
    7936             :       0,        // qsub1_qsub2
    7937             :       0,        // qsub1_qsub2_qsub3
    7938             :       0,        // qsub2_qsub3
    7939             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    7940             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7941             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    7942             :       24,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass
    7943             :     },
    7944             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common
    7945             :       0,        // bsub
    7946             :       0,        // dsub
    7947             :       0,        // dsub0
    7948             :       0,        // dsub1
    7949             :       0,        // dsub2
    7950             :       0,        // dsub3
    7951             :       0,        // hsub
    7952             :       0,        // qhisub
    7953             :       0,        // qsub
    7954             :       0,        // qsub0
    7955             :       0,        // qsub1
    7956             :       0,        // qsub2
    7957             :       0,        // qsub3
    7958             :       0,        // ssub
    7959             :       25,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7960             :       0,        // sube32
    7961             :       25,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7962             :       0,        // subo32
    7963             :       25,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7964             :       0,        // zsub
    7965             :       0,        // zsub_hi
    7966             :       0,        // dsub1_then_bsub
    7967             :       0,        // dsub1_then_hsub
    7968             :       0,        // dsub1_then_ssub
    7969             :       0,        // dsub3_then_bsub
    7970             :       0,        // dsub3_then_hsub
    7971             :       0,        // dsub3_then_ssub
    7972             :       0,        // dsub2_then_bsub
    7973             :       0,        // dsub2_then_hsub
    7974             :       0,        // dsub2_then_ssub
    7975             :       0,        // qsub1_then_bsub
    7976             :       0,        // qsub1_then_dsub
    7977             :       0,        // qsub1_then_hsub
    7978             :       0,        // qsub1_then_ssub
    7979             :       0,        // qsub3_then_bsub
    7980             :       0,        // qsub3_then_dsub
    7981             :       0,        // qsub3_then_hsub
    7982             :       0,        // qsub3_then_ssub
    7983             :       0,        // qsub2_then_bsub
    7984             :       0,        // qsub2_then_dsub
    7985             :       0,        // qsub2_then_hsub
    7986             :       0,        // qsub2_then_ssub
    7987             :       25,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
    7988             :       0,        // dsub0_dsub1
    7989             :       0,        // dsub0_dsub1_dsub2
    7990             :       0,        // dsub1_dsub2
    7991             :       0,        // dsub1_dsub2_dsub3
    7992             :       0,        // dsub2_dsub3
    7993             :       0,        // dsub_qsub1_then_dsub
    7994             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7995             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    7996             :       0,        // qsub0_qsub1
    7997             :       0,        // qsub0_qsub1_qsub2
    7998             :       0,        // qsub1_qsub2
    7999             :       0,        // qsub1_qsub2_qsub3
    8000             :       0,        // qsub2_qsub3
    8001             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8002             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8003             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8004             :       25,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
    8005             :     },
    8006             :     {   // XSeqPairsClass_with_subo64_in_GPR64common
    8007             :       0,        // bsub
    8008             :       0,        // dsub
    8009             :       0,        // dsub0
    8010             :       0,        // dsub1
    8011             :       0,        // dsub2
    8012             :       0,        // dsub3
    8013             :       0,        // hsub
    8014             :       0,        // qhisub
    8015             :       0,        // qsub
    8016             :       0,        // qsub0
    8017             :       0,        // qsub1
    8018             :       0,        // qsub2
    8019             :       0,        // qsub3
    8020             :       0,        // ssub
    8021             :       26,       // sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
    8022             :       0,        // sube32
    8023             :       26,       // sube64 -> XSeqPairsClass_with_subo64_in_GPR64common
    8024             :       0,        // subo32
    8025             :       26,       // subo64 -> XSeqPairsClass_with_subo64_in_GPR64common
    8026             :       0,        // zsub
    8027             :       0,        // zsub_hi
    8028             :       0,        // dsub1_then_bsub
    8029             :       0,        // dsub1_then_hsub
    8030             :       0,        // dsub1_then_ssub
    8031             :       0,        // dsub3_then_bsub
    8032             :       0,        // dsub3_then_hsub
    8033             :       0,        // dsub3_then_ssub
    8034             :       0,        // dsub2_then_bsub
    8035             :       0,        // dsub2_then_hsub
    8036             :       0,        // dsub2_then_ssub
    8037             :       0,        // qsub1_then_bsub
    8038             :       0,        // qsub1_then_dsub
    8039             :       0,        // qsub1_then_hsub
    8040             :       0,        // qsub1_then_ssub
    8041             :       0,        // qsub3_then_bsub
    8042             :       0,        // qsub3_then_dsub
    8043             :       0,        // qsub3_then_hsub
    8044             :       0,        // qsub3_then_ssub
    8045             :       0,        // qsub2_then_bsub
    8046             :       0,        // qsub2_then_dsub
    8047             :       0,        // qsub2_then_hsub
    8048             :       0,        // qsub2_then_ssub
    8049             :       26,       // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
    8050             :       0,        // dsub0_dsub1
    8051             :       0,        // dsub0_dsub1_dsub2
    8052             :       0,        // dsub1_dsub2
    8053             :       0,        // dsub1_dsub2_dsub3
    8054             :       0,        // dsub2_dsub3
    8055             :       0,        // dsub_qsub1_then_dsub
    8056             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8057             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8058             :       0,        // qsub0_qsub1
    8059             :       0,        // qsub0_qsub1_qsub2
    8060             :       0,        // qsub1_qsub2
    8061             :       0,        // qsub1_qsub2_qsub3
    8062             :       0,        // qsub2_qsub3
    8063             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8064             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8065             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8066             :       26,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
    8067             :     },
    8068             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    8069             :       0,        // bsub
    8070             :       0,        // dsub
    8071             :       0,        // dsub0
    8072             :       0,        // dsub1
    8073             :       0,        // dsub2
    8074             :       0,        // dsub3
    8075             :       0,        // hsub
    8076             :       0,        // qhisub
    8077             :       0,        // qsub
    8078             :       0,        // qsub0
    8079             :       0,        // qsub1
    8080             :       0,        // qsub2
    8081             :       0,        // qsub3
    8082             :       0,        // ssub
    8083             :       27,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    8084             :       0,        // sube32
    8085             :       27,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    8086             :       0,        // subo32
    8087             :       27,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    8088             :       0,        // zsub
    8089             :       0,        // zsub_hi
    8090             :       0,        // dsub1_then_bsub
    8091             :       0,        // dsub1_then_hsub
    8092             :       0,        // dsub1_then_ssub
    8093             :       0,        // dsub3_then_bsub
    8094             :       0,        // dsub3_then_hsub
    8095             :       0,        // dsub3_then_ssub
    8096             :       0,        // dsub2_then_bsub
    8097             :       0,        // dsub2_then_hsub
    8098             :       0,        // dsub2_then_ssub
    8099             :       0,        // qsub1_then_bsub
    8100             :       0,        // qsub1_then_dsub
    8101             :       0,        // qsub1_then_hsub
    8102             :       0,        // qsub1_then_ssub
    8103             :       0,        // qsub3_then_bsub
    8104             :       0,        // qsub3_then_dsub
    8105             :       0,        // qsub3_then_hsub
    8106             :       0,        // qsub3_then_ssub
    8107             :       0,        // qsub2_then_bsub
    8108             :       0,        // qsub2_then_dsub
    8109             :       0,        // qsub2_then_hsub
    8110             :       0,        // qsub2_then_ssub
    8111             :       27,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    8112             :       0,        // dsub0_dsub1
    8113             :       0,        // dsub0_dsub1_dsub2
    8114             :       0,        // dsub1_dsub2
    8115             :       0,        // dsub1_dsub2_dsub3
    8116             :       0,        // dsub2_dsub3
    8117             :       0,        // dsub_qsub1_then_dsub
    8118             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8119             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8120             :       0,        // qsub0_qsub1
    8121             :       0,        // qsub0_qsub1_qsub2
    8122             :       0,        // qsub1_qsub2
    8123             :       0,        // qsub1_qsub2_qsub3
    8124             :       0,        // qsub2_qsub3
    8125             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8126             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8127             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8128             :       27,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    8129             :     },
    8130             :     {   // XSeqPairsClass_with_sube64_in_tcGPR64
    8131             :       0,        // bsub
    8132             :       0,        // dsub
    8133             :       0,        // dsub0
    8134             :       0,        // dsub1
    8135             :       0,        // dsub2
    8136             :       0,        // dsub3
    8137             :       0,        // hsub
    8138             :       0,        // qhisub
    8139             :       0,        // qsub
    8140             :       0,        // qsub0
    8141             :       0,        // qsub1
    8142             :       0,        // qsub2
    8143             :       0,        // qsub3
    8144             :       0,        // ssub
    8145             :       28,       // sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
    8146             :       0,        // sube32
    8147             :       28,       // sube64 -> XSeqPairsClass_with_sube64_in_tcGPR64
    8148             :       0,        // subo32
    8149             :       28,       // subo64 -> XSeqPairsClass_with_sube64_in_tcGPR64
    8150             :       0,        // zsub
    8151             :       0,        // zsub_hi
    8152             :       0,        // dsub1_then_bsub
    8153             :       0,        // dsub1_then_hsub
    8154             :       0,        // dsub1_then_ssub
    8155             :       0,        // dsub3_then_bsub
    8156             :       0,        // dsub3_then_hsub
    8157             :       0,        // dsub3_then_ssub
    8158             :       0,        // dsub2_then_bsub
    8159             :       0,        // dsub2_then_hsub
    8160             :       0,        // dsub2_then_ssub
    8161             :       0,        // qsub1_then_bsub
    8162             :       0,        // qsub1_then_dsub
    8163             :       0,        // qsub1_then_hsub
    8164             :       0,        // qsub1_then_ssub
    8165             :       0,        // qsub3_then_bsub
    8166             :       0,        // qsub3_then_dsub
    8167             :       0,        // qsub3_then_hsub
    8168             :       0,        // qsub3_then_ssub
    8169             :       0,        // qsub2_then_bsub
    8170             :       0,        // qsub2_then_dsub
    8171             :       0,        // qsub2_then_hsub
    8172             :       0,        // qsub2_then_ssub
    8173             :       28,       // subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
    8174             :       0,        // dsub0_dsub1
    8175             :       0,        // dsub0_dsub1_dsub2
    8176             :       0,        // dsub1_dsub2
    8177             :       0,        // dsub1_dsub2_dsub3
    8178             :       0,        // dsub2_dsub3
    8179             :       0,        // dsub_qsub1_then_dsub
    8180             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8181             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8182             :       0,        // qsub0_qsub1
    8183             :       0,        // qsub0_qsub1_qsub2
    8184             :       0,        // qsub1_qsub2
    8185             :       0,        // qsub1_qsub2_qsub3
    8186             :       0,        // qsub2_qsub3
    8187             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8188             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8189             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8190             :       28,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
    8191             :     },
    8192             :     {   // XSeqPairsClass_with_subo64_in_tcGPR64
    8193             :       0,        // bsub
    8194             :       0,        // dsub
    8195             :       0,        // dsub0
    8196             :       0,        // dsub1
    8197             :       0,        // dsub2
    8198             :       0,        // dsub3
    8199             :       0,        // hsub
    8200             :       0,        // qhisub
    8201             :       0,        // qsub
    8202             :       0,        // qsub0
    8203             :       0,        // qsub1
    8204             :       0,        // qsub2
    8205             :       0,        // qsub3
    8206             :       0,        // ssub
    8207             :       29,       // sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
    8208             :       0,        // sube32
    8209             :       29,       // sube64 -> XSeqPairsClass_with_subo64_in_tcGPR64
    8210             :       0,        // subo32
    8211             :       29,       // subo64 -> XSeqPairsClass_with_subo64_in_tcGPR64
    8212             :       0,        // zsub
    8213             :       0,        // zsub_hi
    8214             :       0,        // dsub1_then_bsub
    8215             :       0,        // dsub1_then_hsub
    8216             :       0,        // dsub1_then_ssub
    8217             :       0,        // dsub3_then_bsub
    8218             :       0,        // dsub3_then_hsub
    8219             :       0,        // dsub3_then_ssub
    8220             :       0,        // dsub2_then_bsub
    8221             :       0,        // dsub2_then_hsub
    8222             :       0,        // dsub2_then_ssub
    8223             :       0,        // qsub1_then_bsub
    8224             :       0,        // qsub1_then_dsub
    8225             :       0,        // qsub1_then_hsub
    8226             :       0,        // qsub1_then_ssub
    8227             :       0,        // qsub3_then_bsub
    8228             :       0,        // qsub3_then_dsub
    8229             :       0,        // qsub3_then_hsub
    8230             :       0,        // qsub3_then_ssub
    8231             :       0,        // qsub2_then_bsub
    8232             :       0,        // qsub2_then_dsub
    8233             :       0,        // qsub2_then_hsub
    8234             :       0,        // qsub2_then_ssub
    8235             :       29,       // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
    8236             :       0,        // dsub0_dsub1
    8237             :       0,        // dsub0_dsub1_dsub2
    8238             :       0,        // dsub1_dsub2
    8239             :       0,        // dsub1_dsub2_dsub3
    8240             :       0,        // dsub2_dsub3
    8241             :       0,        // dsub_qsub1_then_dsub
    8242             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8243             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8244             :       0,        // qsub0_qsub1
    8245             :       0,        // qsub0_qsub1_qsub2
    8246             :       0,        // qsub1_qsub2
    8247             :       0,        // qsub1_qsub2_qsub3
    8248             :       0,        // qsub2_qsub3
    8249             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8250             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8251             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8252             :       29,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
    8253             :     },
    8254             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    8255             :       0,        // bsub
    8256             :       0,        // dsub
    8257             :       0,        // dsub0
    8258             :       0,        // dsub1
    8259             :       0,        // dsub2
    8260             :       0,        // dsub3
    8261             :       0,        // hsub
    8262             :       0,        // qhisub
    8263             :       0,        // qsub
    8264             :       0,        // qsub0
    8265             :       0,        // qsub1
    8266             :       0,        // qsub2
    8267             :       0,        // qsub3
    8268             :       0,        // ssub
    8269             :       30,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    8270             :       0,        // sube32
    8271             :       30,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    8272             :       0,        // subo32
    8273             :       30,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    8274             :       0,        // zsub
    8275             :       0,        // zsub_hi
    8276             :       0,        // dsub1_then_bsub
    8277             :       0,        // dsub1_then_hsub
    8278             :       0,        // dsub1_then_ssub
    8279             :       0,        // dsub3_then_bsub
    8280             :       0,        // dsub3_then_hsub
    8281             :       0,        // dsub3_then_ssub
    8282             :       0,        // dsub2_then_bsub
    8283             :       0,        // dsub2_then_hsub
    8284             :       0,        // dsub2_then_ssub
    8285             :       0,        // qsub1_then_bsub
    8286             :       0,        // qsub1_then_dsub
    8287             :       0,        // qsub1_then_hsub
    8288             :       0,        // qsub1_then_ssub
    8289             :       0,        // qsub3_then_bsub
    8290             :       0,        // qsub3_then_dsub
    8291             :       0,        // qsub3_then_hsub
    8292             :       0,        // qsub3_then_ssub
    8293             :       0,        // qsub2_then_bsub
    8294             :       0,        // qsub2_then_dsub
    8295             :       0,        // qsub2_then_hsub
    8296             :       0,        // qsub2_then_ssub
    8297             :       30,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    8298             :       0,        // dsub0_dsub1
    8299             :       0,        // dsub0_dsub1_dsub2
    8300             :       0,        // dsub1_dsub2
    8301             :       0,        // dsub1_dsub2_dsub3
    8302             :       0,        // dsub2_dsub3
    8303             :       0,        // dsub_qsub1_then_dsub
    8304             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8305             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8306             :       0,        // qsub0_qsub1
    8307             :       0,        // qsub0_qsub1_qsub2
    8308             :       0,        // qsub1_qsub2
    8309             :       0,        // qsub1_qsub2_qsub3
    8310             :       0,        // qsub2_qsub3
    8311             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8312             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8313             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8314             :       30,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    8315             :     },
    8316             :     {   // FPR128
    8317             :       31,       // bsub -> FPR128
    8318             :       31,       // dsub -> FPR128
    8319             :       0,        // dsub0
    8320             :       0,        // dsub1
    8321             :       0,        // dsub2
    8322             :       0,        // dsub3
    8323             :       31,       // hsub -> FPR128
    8324             :       0,        // qhisub
    8325             :       0,        // qsub
    8326             :       0,        // qsub0
    8327             :       0,        // qsub1
    8328             :       0,        // qsub2
    8329             :       0,        // qsub3
    8330             :       31,       // ssub -> FPR128
    8331             :       0,        // sub_32
    8332             :       0,        // sube32
    8333             :       0,        // sube64
    8334             :       0,        // subo32
    8335             :       0,        // subo64
    8336             :       0,        // zsub
    8337             :       0,        // zsub_hi
    8338             :       0,        // dsub1_then_bsub
    8339             :       0,        // dsub1_then_hsub
    8340             :       0,        // dsub1_then_ssub
    8341             :       0,        // dsub3_then_bsub
    8342             :       0,        // dsub3_then_hsub
    8343             :       0,        // dsub3_then_ssub
    8344             :       0,        // dsub2_then_bsub
    8345             :       0,        // dsub2_then_hsub
    8346             :       0,        // dsub2_then_ssub
    8347             :       0,        // qsub1_then_bsub
    8348             :       0,        // qsub1_then_dsub
    8349             :       0,        // qsub1_then_hsub
    8350             :       0,        // qsub1_then_ssub
    8351             :       0,        // qsub3_then_bsub
    8352             :       0,        // qsub3_then_dsub
    8353             :       0,        // qsub3_then_hsub
    8354             :       0,        // qsub3_then_ssub
    8355             :       0,        // qsub2_then_bsub
    8356             :       0,        // qsub2_then_dsub
    8357             :       0,        // qsub2_then_hsub
    8358             :       0,        // qsub2_then_ssub
    8359             :       0,        // subo64_then_sub_32
    8360             :       0,        // dsub0_dsub1
    8361             :       0,        // dsub0_dsub1_dsub2
    8362             :       0,        // dsub1_dsub2
    8363             :       0,        // dsub1_dsub2_dsub3
    8364             :       0,        // dsub2_dsub3
    8365             :       0,        // dsub_qsub1_then_dsub
    8366             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8367             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8368             :       0,        // qsub0_qsub1
    8369             :       0,        // qsub0_qsub1_qsub2
    8370             :       0,        // qsub1_qsub2
    8371             :       0,        // qsub1_qsub2_qsub3
    8372             :       0,        // qsub2_qsub3
    8373             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8374             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8375             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8376             :       0,        // sub_32_subo64_then_sub_32
    8377             :     },
    8378             :     {   // ZPR
    8379             :       32,       // bsub -> ZPR
    8380             :       32,       // dsub -> ZPR
    8381             :       0,        // dsub0
    8382             :       0,        // dsub1
    8383             :       0,        // dsub2
    8384             :       0,        // dsub3
    8385             :       32,       // hsub -> ZPR
    8386             :       0,        // qhisub
    8387             :       0,        // qsub
    8388             :       0,        // qsub0
    8389             :       0,        // qsub1
    8390             :       0,        // qsub2
    8391             :       0,        // qsub3
    8392             :       32,       // ssub -> ZPR
    8393             :       0,        // sub_32
    8394             :       0,        // sube32
    8395             :       0,        // sube64
    8396             :       0,        // subo32
    8397             :       0,        // subo64
    8398             :       32,       // zsub -> ZPR
    8399             :       32,       // zsub_hi -> ZPR
    8400             :       0,        // dsub1_then_bsub
    8401             :       0,        // dsub1_then_hsub
    8402             :       0,        // dsub1_then_ssub
    8403             :       0,        // dsub3_then_bsub
    8404             :       0,        // dsub3_then_hsub
    8405             :       0,        // dsub3_then_ssub
    8406             :       0,        // dsub2_then_bsub
    8407             :       0,        // dsub2_then_hsub
    8408             :       0,        // dsub2_then_ssub
    8409             :       0,        // qsub1_then_bsub
    8410             :       0,        // qsub1_then_dsub
    8411             :       0,        // qsub1_then_hsub
    8412             :       0,        // qsub1_then_ssub
    8413             :       0,        // qsub3_then_bsub
    8414             :       0,        // qsub3_then_dsub
    8415             :       0,        // qsub3_then_hsub
    8416             :       0,        // qsub3_then_ssub
    8417             :       0,        // qsub2_then_bsub
    8418             :       0,        // qsub2_then_dsub
    8419             :       0,        // qsub2_then_hsub
    8420             :       0,        // qsub2_then_ssub
    8421             :       0,        // subo64_then_sub_32
    8422             :       0,        // dsub0_dsub1
    8423             :       0,        // dsub0_dsub1_dsub2
    8424             :       0,        // dsub1_dsub2
    8425             :       0,        // dsub1_dsub2_dsub3
    8426             :       0,        // dsub2_dsub3
    8427             :       0,        // dsub_qsub1_then_dsub
    8428             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8429             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8430             :       0,        // qsub0_qsub1
    8431             :       0,        // qsub0_qsub1_qsub2
    8432             :       0,        // qsub1_qsub2
    8433             :       0,        // qsub1_qsub2_qsub3
    8434             :       0,        // qsub2_qsub3
    8435             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8436             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8437             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8438             :       0,        // sub_32_subo64_then_sub_32
    8439             :     },
    8440             :     {   // FPR128_lo
    8441             :       33,       // bsub -> FPR128_lo
    8442             :       33,       // dsub -> FPR128_lo
    8443             :       0,        // dsub0
    8444             :       0,        // dsub1
    8445             :       0,        // dsub2
    8446             :       0,        // dsub3
    8447             :       33,       // hsub -> FPR128_lo
    8448             :       0,        // qhisub
    8449             :       0,        // qsub
    8450             :       0,        // qsub0
    8451             :       0,        // qsub1
    8452             :       0,        // qsub2
    8453             :       0,        // qsub3
    8454             :       33,       // ssub -> FPR128_lo
    8455             :       0,        // sub_32
    8456             :       0,        // sube32
    8457             :       0,        // sube64
    8458             :       0,        // subo32
    8459             :       0,        // subo64
    8460             :       0,        // zsub
    8461             :       0,        // zsub_hi
    8462             :       0,        // dsub1_then_bsub
    8463             :       0,        // dsub1_then_hsub
    8464             :       0,        // dsub1_then_ssub
    8465             :       0,        // dsub3_then_bsub
    8466             :       0,        // dsub3_then_hsub
    8467             :       0,        // dsub3_then_ssub
    8468             :       0,        // dsub2_then_bsub
    8469             :       0,        // dsub2_then_hsub
    8470             :       0,        // dsub2_then_ssub
    8471             :       0,        // qsub1_then_bsub
    8472             :       0,        // qsub1_then_dsub
    8473             :       0,        // qsub1_then_hsub
    8474             :       0,        // qsub1_then_ssub
    8475             :       0,        // qsub3_then_bsub
    8476             :       0,        // qsub3_then_dsub
    8477             :       0,        // qsub3_then_hsub
    8478             :       0,        // qsub3_then_ssub
    8479             :       0,        // qsub2_then_bsub
    8480             :       0,        // qsub2_then_dsub
    8481             :       0,        // qsub2_then_hsub
    8482             :       0,        // qsub2_then_ssub
    8483             :       0,        // subo64_then_sub_32
    8484             :       0,        // dsub0_dsub1
    8485             :       0,        // dsub0_dsub1_dsub2
    8486             :       0,        // dsub1_dsub2
    8487             :       0,        // dsub1_dsub2_dsub3
    8488             :       0,        // dsub2_dsub3
    8489             :       0,        // dsub_qsub1_then_dsub
    8490             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8491             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8492             :       0,        // qsub0_qsub1
    8493             :       0,        // qsub0_qsub1_qsub2
    8494             :       0,        // qsub1_qsub2
    8495             :       0,        // qsub1_qsub2_qsub3
    8496             :       0,        // qsub2_qsub3
    8497             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8498             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8499             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8500             :       0,        // sub_32_subo64_then_sub_32
    8501             :     },
    8502             :     {   // ZPR_with_zsub_in_FPR128_lo
    8503             :       34,       // bsub -> ZPR_with_zsub_in_FPR128_lo
    8504             :       34,       // dsub -> ZPR_with_zsub_in_FPR128_lo
    8505             :       0,        // dsub0
    8506             :       0,        // dsub1
    8507             :       0,        // dsub2
    8508             :       0,        // dsub3
    8509             :       34,       // hsub -> ZPR_with_zsub_in_FPR128_lo
    8510             :       0,        // qhisub
    8511             :       0,        // qsub
    8512             :       0,        // qsub0
    8513             :       0,        // qsub1
    8514             :       0,        // qsub2
    8515             :       0,        // qsub3
    8516             :       34,       // ssub -> ZPR_with_zsub_in_FPR128_lo
    8517             :       0,        // sub_32
    8518             :       0,        // sube32
    8519             :       0,        // sube64
    8520             :       0,        // subo32
    8521             :       0,        // subo64
    8522             :       34,       // zsub -> ZPR_with_zsub_in_FPR128_lo
    8523             :       34,       // zsub_hi -> ZPR_with_zsub_in_FPR128_lo
    8524             :       0,        // dsub1_then_bsub
    8525             :       0,        // dsub1_then_hsub
    8526             :       0,        // dsub1_then_ssub
    8527             :       0,        // dsub3_then_bsub
    8528             :       0,        // dsub3_then_hsub
    8529             :       0,        // dsub3_then_ssub
    8530             :       0,        // dsub2_then_bsub
    8531             :       0,        // dsub2_then_hsub
    8532             :       0,        // dsub2_then_ssub
    8533             :       0,        // qsub1_then_bsub
    8534             :       0,        // qsub1_then_dsub
    8535             :       0,        // qsub1_then_hsub
    8536             :       0,        // qsub1_then_ssub
    8537             :       0,        // qsub3_then_bsub
    8538             :       0,        // qsub3_then_dsub
    8539             :       0,        // qsub3_then_hsub
    8540             :       0,        // qsub3_then_ssub
    8541             :       0,        // qsub2_then_bsub
    8542             :       0,        // qsub2_then_dsub
    8543             :       0,        // qsub2_then_hsub
    8544             :       0,        // qsub2_then_ssub
    8545             :       0,        // subo64_then_sub_32
    8546             :       0,        // dsub0_dsub1
    8547             :       0,        // dsub0_dsub1_dsub2
    8548             :       0,        // dsub1_dsub2
    8549             :       0,        // dsub1_dsub2_dsub3
    8550             :       0,        // dsub2_dsub3
    8551             :       0,        // dsub_qsub1_then_dsub
    8552             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8553             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8554             :       0,        // qsub0_qsub1
    8555             :       0,        // qsub0_qsub1_qsub2
    8556             :       0,        // qsub1_qsub2
    8557             :       0,        // qsub1_qsub2_qsub3
    8558             :       0,        // qsub2_qsub3
    8559             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8560             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8561             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8562             :       0,        // sub_32_subo64_then_sub_32
    8563             :     },
    8564             :     {   // DDD
    8565             :       35,       // bsub -> DDD
    8566             :       0,        // dsub
    8567             :       35,       // dsub0 -> DDD
    8568             :       35,       // dsub1 -> DDD
    8569             :       35,       // dsub2 -> DDD
    8570             :       0,        // dsub3
    8571             :       35,       // hsub -> DDD
    8572             :       0,        // qhisub
    8573             :       0,        // qsub
    8574             :       0,        // qsub0
    8575             :       0,        // qsub1
    8576             :       0,        // qsub2
    8577             :       0,        // qsub3
    8578             :       35,       // ssub -> DDD
    8579             :       0,        // sub_32
    8580             :       0,        // sube32
    8581             :       0,        // sube64
    8582             :       0,        // subo32
    8583             :       0,        // subo64
    8584             :       0,        // zsub
    8585             :       0,        // zsub_hi
    8586             :       35,       // dsub1_then_bsub -> DDD
    8587             :       35,       // dsub1_then_hsub -> DDD
    8588             :       35,       // dsub1_then_ssub -> DDD
    8589             :       0,        // dsub3_then_bsub
    8590             :       0,        // dsub3_then_hsub
    8591             :       0,        // dsub3_then_ssub
    8592             :       35,       // dsub2_then_bsub -> DDD
    8593             :       35,       // dsub2_then_hsub -> DDD
    8594             :       35,       // dsub2_then_ssub -> DDD
    8595             :       0,        // qsub1_then_bsub
    8596             :       0,        // qsub1_then_dsub
    8597             :       0,        // qsub1_then_hsub
    8598             :       0,        // qsub1_then_ssub
    8599             :       0,        // qsub3_then_bsub
    8600             :       0,        // qsub3_then_dsub
    8601             :       0,        // qsub3_then_hsub
    8602             :       0,        // qsub3_then_ssub
    8603             :       0,        // qsub2_then_bsub
    8604             :       0,        // qsub2_then_dsub
    8605             :       0,        // qsub2_then_hsub
    8606             :       0,        // qsub2_then_ssub
    8607             :       0,        // subo64_then_sub_32
    8608             :       35,       // dsub0_dsub1 -> DDD
    8609             :       0,        // dsub0_dsub1_dsub2
    8610             :       35,       // dsub1_dsub2 -> DDD
    8611             :       0,        // dsub1_dsub2_dsub3
    8612             :       0,        // dsub2_dsub3
    8613             :       0,        // dsub_qsub1_then_dsub
    8614             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8615             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8616             :       0,        // qsub0_qsub1
    8617             :       0,        // qsub0_qsub1_qsub2
    8618             :       0,        // qsub1_qsub2
    8619             :       0,        // qsub1_qsub2_qsub3
    8620             :       0,        // qsub2_qsub3
    8621             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8622             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8623             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8624             :       0,        // sub_32_subo64_then_sub_32
    8625             :     },
    8626             :     {   // DDDD
    8627             :       36,       // bsub -> DDDD
    8628             :       0,        // dsub
    8629             :       36,       // dsub0 -> DDDD
    8630             :       36,       // dsub1 -> DDDD
    8631             :       36,       // dsub2 -> DDDD
    8632             :       36,       // dsub3 -> DDDD
    8633             :       36,       // hsub -> DDDD
    8634             :       0,        // qhisub
    8635             :       0,        // qsub
    8636             :       0,        // qsub0
    8637             :       0,        // qsub1
    8638             :       0,        // qsub2
    8639             :       0,        // qsub3
    8640             :       36,       // ssub -> DDDD
    8641             :       0,        // sub_32
    8642             :       0,        // sube32
    8643             :       0,        // sube64
    8644             :       0,        // subo32
    8645             :       0,        // subo64
    8646             :       0,        // zsub
    8647             :       0,        // zsub_hi
    8648             :       36,       // dsub1_then_bsub -> DDDD
    8649             :       36,       // dsub1_then_hsub -> DDDD
    8650             :       36,       // dsub1_then_ssub -> DDDD
    8651             :       36,       // dsub3_then_bsub -> DDDD
    8652             :       36,       // dsub3_then_hsub -> DDDD
    8653             :       36,       // dsub3_then_ssub -> DDDD
    8654             :       36,       // dsub2_then_bsub -> DDDD
    8655             :       36,       // dsub2_then_hsub -> DDDD
    8656             :       36,       // dsub2_then_ssub -> DDDD
    8657             :       0,        // qsub1_then_bsub
    8658             :       0,        // qsub1_then_dsub
    8659             :       0,        // qsub1_then_hsub
    8660             :       0,        // qsub1_then_ssub
    8661             :       0,        // qsub3_then_bsub
    8662             :       0,        // qsub3_then_dsub
    8663             :       0,        // qsub3_then_hsub
    8664             :       0,        // qsub3_then_ssub
    8665             :       0,        // qsub2_then_bsub
    8666             :       0,        // qsub2_then_dsub
    8667             :       0,        // qsub2_then_hsub
    8668             :       0,        // qsub2_then_ssub
    8669             :       0,        // subo64_then_sub_32
    8670             :       36,       // dsub0_dsub1 -> DDDD
    8671             :       36,       // dsub0_dsub1_dsub2 -> DDDD
    8672             :       36,       // dsub1_dsub2 -> DDDD
    8673             :       36,       // dsub1_dsub2_dsub3 -> DDDD
    8674             :       36,       // dsub2_dsub3 -> DDDD
    8675             :       0,        // dsub_qsub1_then_dsub
    8676             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8677             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8678             :       0,        // qsub0_qsub1
    8679             :       0,        // qsub0_qsub1_qsub2
    8680             :       0,        // qsub1_qsub2
    8681             :       0,        // qsub1_qsub2_qsub3
    8682             :       0,        // qsub2_qsub3
    8683             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8684             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8685             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8686             :       0,        // sub_32_subo64_then_sub_32
    8687             :     },
    8688             :     {   // QQ
    8689             :       37,       // bsub -> QQ
    8690             :       37,       // dsub -> QQ
    8691             :       0,        // dsub0
    8692             :       0,        // dsub1
    8693             :       0,        // dsub2
    8694             :       0,        // dsub3
    8695             :       37,       // hsub -> QQ
    8696             :       0,        // qhisub
    8697             :       0,        // qsub
    8698             :       37,       // qsub0 -> QQ
    8699             :       37,       // qsub1 -> QQ
    8700             :       0,        // qsub2
    8701             :       0,        // qsub3
    8702             :       37,       // ssub -> QQ
    8703             :       0,        // sub_32
    8704             :       0,        // sube32
    8705             :       0,        // sube64
    8706             :       0,        // subo32
    8707             :       0,        // subo64
    8708             :       0,        // zsub
    8709             :       0,        // zsub_hi
    8710             :       0,        // dsub1_then_bsub
    8711             :       0,        // dsub1_then_hsub
    8712             :       0,        // dsub1_then_ssub
    8713             :       0,        // dsub3_then_bsub
    8714             :       0,        // dsub3_then_hsub
    8715             :       0,        // dsub3_then_ssub
    8716             :       0,        // dsub2_then_bsub
    8717             :       0,        // dsub2_then_hsub
    8718             :       0,        // dsub2_then_ssub
    8719             :       37,       // qsub1_then_bsub -> QQ
    8720             :       37,       // qsub1_then_dsub -> QQ
    8721             :       37,       // qsub1_then_hsub -> QQ
    8722             :       37,       // qsub1_then_ssub -> QQ
    8723             :       0,        // qsub3_then_bsub
    8724             :       0,        // qsub3_then_dsub
    8725             :       0,        // qsub3_then_hsub
    8726             :       0,        // qsub3_then_ssub
    8727             :       0,        // qsub2_then_bsub
    8728             :       0,        // qsub2_then_dsub
    8729             :       0,        // qsub2_then_hsub
    8730             :       0,        // qsub2_then_ssub
    8731             :       0,        // subo64_then_sub_32
    8732             :       0,        // dsub0_dsub1
    8733             :       0,        // dsub0_dsub1_dsub2
    8734             :       0,        // dsub1_dsub2
    8735             :       0,        // dsub1_dsub2_dsub3
    8736             :       0,        // dsub2_dsub3
    8737             :       37,       // dsub_qsub1_then_dsub -> QQ
    8738             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8739             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8740             :       0,        // qsub0_qsub1
    8741             :       0,        // qsub0_qsub1_qsub2
    8742             :       0,        // qsub1_qsub2
    8743             :       0,        // qsub1_qsub2_qsub3
    8744             :       0,        // qsub2_qsub3
    8745             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8746             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8747             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8748             :       0,        // sub_32_subo64_then_sub_32
    8749             :     },
    8750             :     {   // QQ_with_qsub0_in_FPR128_lo
    8751             :       38,       // bsub -> QQ_with_qsub0_in_FPR128_lo
    8752             :       38,       // dsub -> QQ_with_qsub0_in_FPR128_lo
    8753             :       0,        // dsub0
    8754             :       0,        // dsub1
    8755             :       0,        // dsub2
    8756             :       0,        // dsub3
    8757             :       38,       // hsub -> QQ_with_qsub0_in_FPR128_lo
    8758             :       0,        // qhisub
    8759             :       0,        // qsub
    8760             :       38,       // qsub0 -> QQ_with_qsub0_in_FPR128_lo
    8761             :       38,       // qsub1 -> QQ_with_qsub0_in_FPR128_lo
    8762             :       0,        // qsub2
    8763             :       0,        // qsub3
    8764             :       38,       // ssub -> QQ_with_qsub0_in_FPR128_lo
    8765             :       0,        // sub_32
    8766             :       0,        // sube32
    8767             :       0,        // sube64
    8768             :       0,        // subo32
    8769             :       0,        // subo64
    8770             :       0,        // zsub
    8771             :       0,        // zsub_hi
    8772             :       0,        // dsub1_then_bsub
    8773             :       0,        // dsub1_then_hsub
    8774             :       0,        // dsub1_then_ssub
    8775             :       0,        // dsub3_then_bsub
    8776             :       0,        // dsub3_then_hsub
    8777             :       0,        // dsub3_then_ssub
    8778             :       0,        // dsub2_then_bsub
    8779             :       0,        // dsub2_then_hsub
    8780             :       0,        // dsub2_then_ssub
    8781             :       38,       // qsub1_then_bsub -> QQ_with_qsub0_in_FPR128_lo
    8782             :       38,       // qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo
    8783             :       38,       // qsub1_then_hsub -> QQ_with_qsub0_in_FPR128_lo
    8784             :       38,       // qsub1_then_ssub -> QQ_with_qsub0_in_FPR128_lo
    8785             :       0,        // qsub3_then_bsub
    8786             :       0,        // qsub3_then_dsub
    8787             :       0,        // qsub3_then_hsub
    8788             :       0,        // qsub3_then_ssub
    8789             :       0,        // qsub2_then_bsub
    8790             :       0,        // qsub2_then_dsub
    8791             :       0,        // qsub2_then_hsub
    8792             :       0,        // qsub2_then_ssub
    8793             :       0,        // subo64_then_sub_32
    8794             :       0,        // dsub0_dsub1
    8795             :       0,        // dsub0_dsub1_dsub2
    8796             :       0,        // dsub1_dsub2
    8797             :       0,        // dsub1_dsub2_dsub3
    8798             :       0,        // dsub2_dsub3
    8799             :       38,       // dsub_qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo
    8800             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8801             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8802             :       0,        // qsub0_qsub1
    8803             :       0,        // qsub0_qsub1_qsub2
    8804             :       0,        // qsub1_qsub2
    8805             :       0,        // qsub1_qsub2_qsub3
    8806             :       0,        // qsub2_qsub3
    8807             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8808             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8809             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8810             :       0,        // sub_32_subo64_then_sub_32
    8811             :     },
    8812             :     {   // QQ_with_qsub1_in_FPR128_lo
    8813             :       39,       // bsub -> QQ_with_qsub1_in_FPR128_lo
    8814             :       39,       // dsub -> QQ_with_qsub1_in_FPR128_lo
    8815             :       0,        // dsub0
    8816             :       0,        // dsub1
    8817             :       0,        // dsub2
    8818             :       0,        // dsub3
    8819             :       39,       // hsub -> QQ_with_qsub1_in_FPR128_lo
    8820             :       0,        // qhisub
    8821             :       0,        // qsub
    8822             :       39,       // qsub0 -> QQ_with_qsub1_in_FPR128_lo
    8823             :       39,       // qsub1 -> QQ_with_qsub1_in_FPR128_lo
    8824             :       0,        // qsub2
    8825             :       0,        // qsub3
    8826             :       39,       // ssub -> QQ_with_qsub1_in_FPR128_lo
    8827             :       0,        // sub_32
    8828             :       0,        // sube32
    8829             :       0,        // sube64
    8830             :       0,        // subo32
    8831             :       0,        // subo64
    8832             :       0,        // zsub
    8833             :       0,        // zsub_hi
    8834             :       0,        // dsub1_then_bsub
    8835             :       0,        // dsub1_then_hsub
    8836             :       0,        // dsub1_then_ssub
    8837             :       0,        // dsub3_then_bsub
    8838             :       0,        // dsub3_then_hsub
    8839             :       0,        // dsub3_then_ssub
    8840             :       0,        // dsub2_then_bsub
    8841             :       0,        // dsub2_then_hsub
    8842             :       0,        // dsub2_then_ssub
    8843             :       39,       // qsub1_then_bsub -> QQ_with_qsub1_in_FPR128_lo
    8844             :       39,       // qsub1_then_dsub -> QQ_with_qsub1_in_FPR128_lo
    8845             :       39,       // qsub1_then_hsub -> QQ_with_qsub1_in_FPR128_lo
    8846             :       39,       // qsub1_then_ssub -> QQ_with_qsub1_in_FPR128_lo
    8847             :       0,        // qsub3_then_bsub
    8848             :       0,        // qsub3_then_dsub
    8849             :       0,        // qsub3_then_hsub
    8850             :       0,        // qsub3_then_ssub
    8851             :       0,        // qsub2_then_bsub
    8852             :       0,        // qsub2_then_dsub
    8853             :       0,        // qsub2_then_hsub
    8854             :       0,        // qsub2_then_ssub
    8855             :       0,        // subo64_then_sub_32
    8856             :       0,        // dsub0_dsub1
    8857             :       0,        // dsub0_dsub1_dsub2
    8858             :       0,        // dsub1_dsub2
    8859             :       0,        // dsub1_dsub2_dsub3
    8860             :       0,        // dsub2_dsub3
    8861             :       39,       // dsub_qsub1_then_dsub -> QQ_with_qsub1_in_FPR128_lo
    8862             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8863             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8864             :       0,        // qsub0_qsub1
    8865             :       0,        // qsub0_qsub1_qsub2
    8866             :       0,        // qsub1_qsub2
    8867             :       0,        // qsub1_qsub2_qsub3
    8868             :       0,        // qsub2_qsub3
    8869             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8870             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8871             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8872             :       0,        // sub_32_subo64_then_sub_32
    8873             :     },
    8874             :     {   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8875             :       40,       // bsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8876             :       40,       // dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8877             :       0,        // dsub0
    8878             :       0,        // dsub1
    8879             :       0,        // dsub2
    8880             :       0,        // dsub3
    8881             :       40,       // hsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8882             :       0,        // qhisub
    8883             :       0,        // qsub
    8884             :       40,       // qsub0 -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8885             :       40,       // qsub1 -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8886             :       0,        // qsub2
    8887             :       0,        // qsub3
    8888             :       40,       // ssub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8889             :       0,        // sub_32
    8890             :       0,        // sube32
    8891             :       0,        // sube64
    8892             :       0,        // subo32
    8893             :       0,        // subo64
    8894             :       0,        // zsub
    8895             :       0,        // zsub_hi
    8896             :       0,        // dsub1_then_bsub
    8897             :       0,        // dsub1_then_hsub
    8898             :       0,        // dsub1_then_ssub
    8899             :       0,        // dsub3_then_bsub
    8900             :       0,        // dsub3_then_hsub
    8901             :       0,        // dsub3_then_ssub
    8902             :       0,        // dsub2_then_bsub
    8903             :       0,        // dsub2_then_hsub
    8904             :       0,        // dsub2_then_ssub
    8905             :       40,       // qsub1_then_bsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8906             :       40,       // qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8907             :       40,       // qsub1_then_hsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8908             :       40,       // qsub1_then_ssub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8909             :       0,        // qsub3_then_bsub
    8910             :       0,        // qsub3_then_dsub
    8911             :       0,        // qsub3_then_hsub
    8912             :       0,        // qsub3_then_ssub
    8913             :       0,        // qsub2_then_bsub
    8914             :       0,        // qsub2_then_dsub
    8915             :       0,        // qsub2_then_hsub
    8916             :       0,        // qsub2_then_ssub
    8917             :       0,        // subo64_then_sub_32
    8918             :       0,        // dsub0_dsub1
    8919             :       0,        // dsub0_dsub1_dsub2
    8920             :       0,        // dsub1_dsub2
    8921             :       0,        // dsub1_dsub2_dsub3
    8922             :       0,        // dsub2_dsub3
    8923             :       40,       // dsub_qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    8924             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8925             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8926             :       0,        // qsub0_qsub1
    8927             :       0,        // qsub0_qsub1_qsub2
    8928             :       0,        // qsub1_qsub2
    8929             :       0,        // qsub1_qsub2_qsub3
    8930             :       0,        // qsub2_qsub3
    8931             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8932             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8933             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8934             :       0,        // sub_32_subo64_then_sub_32
    8935             :     },
    8936             :     {   // QQQ
    8937             :       41,       // bsub -> QQQ
    8938             :       41,       // dsub -> QQQ
    8939             :       0,        // dsub0
    8940             :       0,        // dsub1
    8941             :       0,        // dsub2
    8942             :       0,        // dsub3
    8943             :       41,       // hsub -> QQQ
    8944             :       0,        // qhisub
    8945             :       0,        // qsub
    8946             :       41,       // qsub0 -> QQQ
    8947             :       41,       // qsub1 -> QQQ
    8948             :       41,       // qsub2 -> QQQ
    8949             :       0,        // qsub3
    8950             :       41,       // ssub -> QQQ
    8951             :       0,        // sub_32
    8952             :       0,        // sube32
    8953             :       0,        // sube64
    8954             :       0,        // subo32
    8955             :       0,        // subo64
    8956             :       0,        // zsub
    8957             :       0,        // zsub_hi
    8958             :       0,        // dsub1_then_bsub
    8959             :       0,        // dsub1_then_hsub
    8960             :       0,        // dsub1_then_ssub
    8961             :       0,        // dsub3_then_bsub
    8962             :       0,        // dsub3_then_hsub
    8963             :       0,        // dsub3_then_ssub
    8964             :       0,        // dsub2_then_bsub
    8965             :       0,        // dsub2_then_hsub
    8966             :       0,        // dsub2_then_ssub
    8967             :       41,       // qsub1_then_bsub -> QQQ
    8968             :       41,       // qsub1_then_dsub -> QQQ
    8969             :       41,       // qsub1_then_hsub -> QQQ
    8970             :       41,       // qsub1_then_ssub -> QQQ
    8971             :       0,        // qsub3_then_bsub
    8972             :       0,        // qsub3_then_dsub
    8973             :       0,        // qsub3_then_hsub
    8974             :       0,        // qsub3_then_ssub
    8975             :       41,       // qsub2_then_bsub -> QQQ
    8976             :       41,       // qsub2_then_dsub -> QQQ
    8977             :       41,       // qsub2_then_hsub -> QQQ
    8978             :       41,       // qsub2_then_ssub -> QQQ
    8979             :       0,        // subo64_then_sub_32
    8980             :       0,        // dsub0_dsub1
    8981             :       0,        // dsub0_dsub1_dsub2
    8982             :       0,        // dsub1_dsub2
    8983             :       0,        // dsub1_dsub2_dsub3
    8984             :       0,        // dsub2_dsub3
    8985             :       41,       // dsub_qsub1_then_dsub -> QQQ
    8986             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8987             :       41,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ
    8988             :       41,       // qsub0_qsub1 -> QQQ
    8989             :       0,        // qsub0_qsub1_qsub2
    8990             :       41,       // qsub1_qsub2 -> QQQ
    8991             :       0,        // qsub1_qsub2_qsub3
    8992             :       0,        // qsub2_qsub3
    8993             :       41,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ
    8994             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8995             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8996             :       0,        // sub_32_subo64_then_sub_32
    8997             :     },
    8998             :     {   // QQQ_with_qsub0_in_FPR128_lo
    8999             :       42,       // bsub -> QQQ_with_qsub0_in_FPR128_lo
    9000             :       42,       // dsub -> QQQ_with_qsub0_in_FPR128_lo
    9001             :       0,        // dsub0
    9002             :       0,        // dsub1
    9003             :       0,        // dsub2
    9004             :       0,        // dsub3
    9005             :       42,       // hsub -> QQQ_with_qsub0_in_FPR128_lo
    9006             :       0,        // qhisub
    9007             :       0,        // qsub
    9008             :       42,       // qsub0 -> QQQ_with_qsub0_in_FPR128_lo
    9009             :       42,       // qsub1 -> QQQ_with_qsub0_in_FPR128_lo
    9010             :       42,       // qsub2 -> QQQ_with_qsub0_in_FPR128_lo
    9011             :       0,        // qsub3
    9012             :       42,       // ssub -> QQQ_with_qsub0_in_FPR128_lo
    9013             :       0,        // sub_32
    9014             :       0,        // sube32
    9015             :       0,        // sube64
    9016             :       0,        // subo32
    9017             :       0,        // subo64
    9018             :       0,        // zsub
    9019             :       0,        // zsub_hi
    9020             :       0,        // dsub1_then_bsub
    9021             :       0,        // dsub1_then_hsub
    9022             :       0,        // dsub1_then_ssub
    9023             :       0,        // dsub3_then_bsub
    9024             :       0,        // dsub3_then_hsub
    9025             :       0,        // dsub3_then_ssub
    9026             :       0,        // dsub2_then_bsub
    9027             :       0,        // dsub2_then_hsub
    9028             :       0,        // dsub2_then_ssub
    9029             :       42,       // qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo
    9030             :       42,       // qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    9031             :       42,       // qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo
    9032             :       42,       // qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo
    9033             :       0,        // qsub3_then_bsub
    9034             :       0,        // qsub3_then_dsub
    9035             :       0,        // qsub3_then_hsub
    9036             :       0,        // qsub3_then_ssub
    9037             :       42,       // qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo
    9038             :       42,       // qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    9039             :       42,       // qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo
    9040             :       42,       // qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo
    9041             :       0,        // subo64_then_sub_32
    9042             :       0,        // dsub0_dsub1
    9043             :       0,        // dsub0_dsub1_dsub2
    9044             :       0,        // dsub1_dsub2
    9045             :       0,        // dsub1_dsub2_dsub3
    9046             :       0,        // dsub2_dsub3
    9047             :       42,       // dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    9048             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9049             :       42,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    9050             :       42,       // qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo
    9051             :       0,        // qsub0_qsub1_qsub2
    9052             :       42,       // qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo
    9053             :       0,        // qsub1_qsub2_qsub3
    9054             :       0,        // qsub2_qsub3
    9055             :       42,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
    9056             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9057             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9058             :       0,        // sub_32_subo64_then_sub_32
    9059             :     },
    9060             :     {   // QQQ_with_qsub1_in_FPR128_lo
    9061             :       43,       // bsub -> QQQ_with_qsub1_in_FPR128_lo
    9062             :       43,       // dsub -> QQQ_with_qsub1_in_FPR128_lo
    9063             :       0,        // dsub0
    9064             :       0,        // dsub1
    9065             :       0,        // dsub2
    9066             :       0,        // dsub3
    9067             :       43,       // hsub -> QQQ_with_qsub1_in_FPR128_lo
    9068             :       0,        // qhisub
    9069             :       0,        // qsub
    9070             :       43,       // qsub0 -> QQQ_with_qsub1_in_FPR128_lo
    9071             :       43,       // qsub1 -> QQQ_with_qsub1_in_FPR128_lo
    9072             :       43,       // qsub2 -> QQQ_with_qsub1_in_FPR128_lo
    9073             :       0,        // qsub3
    9074             :       43,       // ssub -> QQQ_with_qsub1_in_FPR128_lo
    9075             :       0,        // sub_32
    9076             :       0,        // sube32
    9077             :       0,        // sube64
    9078             :       0,        // subo32
    9079             :       0,        // subo64
    9080             :       0,        // zsub
    9081             :       0,        // zsub_hi
    9082             :       0,        // dsub1_then_bsub
    9083             :       0,        // dsub1_then_hsub
    9084             :       0,        // dsub1_then_ssub
    9085             :       0,        // dsub3_then_bsub
    9086             :       0,        // dsub3_then_hsub
    9087             :       0,        // dsub3_then_ssub
    9088             :       0,        // dsub2_then_bsub
    9089             :       0,        // dsub2_then_hsub
    9090             :       0,        // dsub2_then_ssub
    9091             :       43,       // qsub1_then_bsub -> QQQ_with_qsub1_in_FPR128_lo
    9092             :       43,       // qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    9093             :       43,       // qsub1_then_hsub -> QQQ_with_qsub1_in_FPR128_lo
    9094             :       43,       // qsub1_then_ssub -> QQQ_with_qsub1_in_FPR128_lo
    9095             :       0,        // qsub3_then_bsub
    9096             :       0,        // qsub3_then_dsub
    9097             :       0,        // qsub3_then_hsub
    9098             :       0,        // qsub3_then_ssub
    9099             :       43,       // qsub2_then_bsub -> QQQ_with_qsub1_in_FPR128_lo
    9100             :       43,       // qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    9101             :       43,       // qsub2_then_hsub -> QQQ_with_qsub1_in_FPR128_lo
    9102             :       43,       // qsub2_then_ssub -> QQQ_with_qsub1_in_FPR128_lo
    9103             :       0,        // subo64_then_sub_32
    9104             :       0,        // dsub0_dsub1
    9105             :       0,        // dsub0_dsub1_dsub2
    9106             :       0,        // dsub1_dsub2
    9107             :       0,        // dsub1_dsub2_dsub3
    9108             :       0,        // dsub2_dsub3
    9109             :       43,       // dsub_qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    9110             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9111             :       43,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    9112             :       43,       // qsub0_qsub1 -> QQQ_with_qsub1_in_FPR128_lo
    9113             :       0,        // qsub0_qsub1_qsub2
    9114             :       43,       // qsub1_qsub2 -> QQQ_with_qsub1_in_FPR128_lo
    9115             :       0,        // qsub1_qsub2_qsub3
    9116             :       0,        // qsub2_qsub3
    9117             :       43,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
    9118             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9119             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9120             :       0,        // sub_32_subo64_then_sub_32
    9121             :     },
    9122             :     {   // QQQ_with_qsub2_in_FPR128_lo
    9123             :       44,       // bsub -> QQQ_with_qsub2_in_FPR128_lo
    9124             :       44,       // dsub -> QQQ_with_qsub2_in_FPR128_lo
    9125             :       0,        // dsub0
    9126             :       0,        // dsub1
    9127             :       0,        // dsub2
    9128             :       0,        // dsub3
    9129             :       44,       // hsub -> QQQ_with_qsub2_in_FPR128_lo
    9130             :       0,        // qhisub
    9131             :       0,        // qsub
    9132             :       44,       // qsub0 -> QQQ_with_qsub2_in_FPR128_lo
    9133             :       44,       // qsub1 -> QQQ_with_qsub2_in_FPR128_lo
    9134             :       44,       // qsub2 -> QQQ_with_qsub2_in_FPR128_lo
    9135             :       0,        // qsub3
    9136             :       44,       // ssub -> QQQ_with_qsub2_in_FPR128_lo
    9137             :       0,        // sub_32
    9138             :       0,        // sube32
    9139             :       0,        // sube64
    9140             :       0,        // subo32
    9141             :       0,        // subo64
    9142             :       0,        // zsub
    9143             :       0,        // zsub_hi
    9144             :       0,        // dsub1_then_bsub
    9145             :       0,        // dsub1_then_hsub
    9146             :       0,        // dsub1_then_ssub
    9147             :       0,        // dsub3_then_bsub
    9148             :       0,        // dsub3_then_hsub
    9149             :       0,        // dsub3_then_ssub
    9150             :       0,        // dsub2_then_bsub
    9151             :       0,        // dsub2_then_hsub
    9152             :       0,        // dsub2_then_ssub
    9153             :       44,       // qsub1_then_bsub -> QQQ_with_qsub2_in_FPR128_lo
    9154             :       44,       // qsub1_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    9155             :       44,       // qsub1_then_hsub -> QQQ_with_qsub2_in_FPR128_lo
    9156             :       44,       // qsub1_then_ssub -> QQQ_with_qsub2_in_FPR128_lo
    9157             :       0,        // qsub3_then_bsub
    9158             :       0,        // qsub3_then_dsub
    9159             :       0,        // qsub3_then_hsub
    9160             :       0,        // qsub3_then_ssub
    9161             :       44,       // qsub2_then_bsub -> QQQ_with_qsub2_in_FPR128_lo
    9162             :       44,       // qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    9163             :       44,       // qsub2_then_hsub -> QQQ_with_qsub2_in_FPR128_lo
    9164             :       44,       // qsub2_then_ssub -> QQQ_with_qsub2_in_FPR128_lo
    9165             :       0,        // subo64_then_sub_32
    9166             :       0,        // dsub0_dsub1
    9167             :       0,        // dsub0_dsub1_dsub2
    9168             :       0,        // dsub1_dsub2
    9169             :       0,        // dsub1_dsub2_dsub3
    9170             :       0,        // dsub2_dsub3
    9171             :       44,       // dsub_qsub1_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    9172             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9173             :       44,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    9174             :       44,       // qsub0_qsub1 -> QQQ_with_qsub2_in_FPR128_lo
    9175             :       0,        // qsub0_qsub1_qsub2
    9176             :       44,       // qsub1_qsub2 -> QQQ_with_qsub2_in_FPR128_lo
    9177             :       0,        // qsub1_qsub2_qsub3
    9178             :       0,        // qsub2_qsub3
    9179             :       44,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
    9180             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9181             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9182             :       0,        // sub_32_subo64_then_sub_32
    9183             :     },
    9184             :     {   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9185             :       45,       // bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9186             :       45,       // dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9187             :       0,        // dsub0
    9188             :       0,        // dsub1
    9189             :       0,        // dsub2
    9190             :       0,        // dsub3
    9191             :       45,       // hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9192             :       0,        // qhisub
    9193             :       0,        // qsub
    9194             :       45,       // qsub0 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9195             :       45,       // qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9196             :       45,       // qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9197             :       0,        // qsub3
    9198             :       45,       // ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9199             :       0,        // sub_32
    9200             :       0,        // sube32
    9201             :       0,        // sube64
    9202             :       0,        // subo32
    9203             :       0,        // subo64
    9204             :       0,        // zsub
    9205             :       0,        // zsub_hi
    9206             :       0,        // dsub1_then_bsub
    9207             :       0,        // dsub1_then_hsub
    9208             :       0,        // dsub1_then_ssub
    9209             :       0,        // dsub3_then_bsub
    9210             :       0,        // dsub3_then_hsub
    9211             :       0,        // dsub3_then_ssub
    9212             :       0,        // dsub2_then_bsub
    9213             :       0,        // dsub2_then_hsub
    9214             :       0,        // dsub2_then_ssub
    9215             :       45,       // qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9216             :       45,       // qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9217             :       45,       // qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9218             :       45,       // qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9219             :       0,        // qsub3_then_bsub
    9220             :       0,        // qsub3_then_dsub
    9221             :       0,        // qsub3_then_hsub
    9222             :       0,        // qsub3_then_ssub
    9223             :       45,       // qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9224             :       45,       // qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9225             :       45,       // qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9226             :       45,       // qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9227             :       0,        // subo64_then_sub_32
    9228             :       0,        // dsub0_dsub1
    9229             :       0,        // dsub0_dsub1_dsub2
    9230             :       0,        // dsub1_dsub2
    9231             :       0,        // dsub1_dsub2_dsub3
    9232             :       0,        // dsub2_dsub3
    9233             :       45,       // dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9234             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9235             :       45,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9236             :       45,       // qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9237             :       0,        // qsub0_qsub1_qsub2
    9238             :       45,       // qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9239             :       0,        // qsub1_qsub2_qsub3
    9240             :       0,        // qsub2_qsub3
    9241             :       45,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    9242             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9243             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9244             :       0,        // sub_32_subo64_then_sub_32
    9245             :     },
    9246             :     {   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9247             :       46,       // bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9248             :       46,       // dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9249             :       0,        // dsub0
    9250             :       0,        // dsub1
    9251             :       0,        // dsub2
    9252             :       0,        // dsub3
    9253             :       46,       // hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9254             :       0,        // qhisub
    9255             :       0,        // qsub
    9256             :       46,       // qsub0 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9257             :       46,       // qsub1 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9258             :       46,       // qsub2 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9259             :       0,        // qsub3
    9260             :       46,       // ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9261             :       0,        // sub_32
    9262             :       0,        // sube32
    9263             :       0,        // sube64
    9264             :       0,        // subo32
    9265             :       0,        // subo64
    9266             :       0,        // zsub
    9267             :       0,        // zsub_hi
    9268             :       0,        // dsub1_then_bsub
    9269             :       0,        // dsub1_then_hsub
    9270             :       0,        // dsub1_then_ssub
    9271             :       0,        // dsub3_then_bsub
    9272             :       0,        // dsub3_then_hsub
    9273             :       0,        // dsub3_then_ssub
    9274             :       0,        // dsub2_then_bsub
    9275             :       0,        // dsub2_then_hsub
    9276             :       0,        // dsub2_then_ssub
    9277             :       46,       // qsub1_then_bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9278             :       46,       // qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9279             :       46,       // qsub1_then_hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9280             :       46,       // qsub1_then_ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9281             :       0,        // qsub3_then_bsub
    9282             :       0,        // qsub3_then_dsub
    9283             :       0,        // qsub3_then_hsub
    9284             :       0,        // qsub3_then_ssub
    9285             :       46,       // qsub2_then_bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9286             :       46,       // qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9287             :       46,       // qsub2_then_hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9288             :       46,       // qsub2_then_ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9289             :       0,        // subo64_then_sub_32
    9290             :       0,        // dsub0_dsub1
    9291             :       0,        // dsub0_dsub1_dsub2
    9292             :       0,        // dsub1_dsub2
    9293             :       0,        // dsub1_dsub2_dsub3
    9294             :       0,        // dsub2_dsub3
    9295             :       46,       // dsub_qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9296             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9297             :       46,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9298             :       46,       // qsub0_qsub1 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9299             :       0,        // qsub0_qsub1_qsub2
    9300             :       46,       // qsub1_qsub2 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9301             :       0,        // qsub1_qsub2_qsub3
    9302             :       0,        // qsub2_qsub3
    9303             :       46,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9304             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9305             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9306             :       0,        // sub_32_subo64_then_sub_32
    9307             :     },
    9308             :     {   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9309             :       47,       // bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9310             :       47,       // dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9311             :       0,        // dsub0
    9312             :       0,        // dsub1
    9313             :       0,        // dsub2
    9314             :       0,        // dsub3
    9315             :       47,       // hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9316             :       0,        // qhisub
    9317             :       0,        // qsub
    9318             :       47,       // qsub0 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9319             :       47,       // qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9320             :       47,       // qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9321             :       0,        // qsub3
    9322             :       47,       // ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9323             :       0,        // sub_32
    9324             :       0,        // sube32
    9325             :       0,        // sube64
    9326             :       0,        // subo32
    9327             :       0,        // subo64
    9328             :       0,        // zsub
    9329             :       0,        // zsub_hi
    9330             :       0,        // dsub1_then_bsub
    9331             :       0,        // dsub1_then_hsub
    9332             :       0,        // dsub1_then_ssub
    9333             :       0,        // dsub3_then_bsub
    9334             :       0,        // dsub3_then_hsub
    9335             :       0,        // dsub3_then_ssub
    9336             :       0,        // dsub2_then_bsub
    9337             :       0,        // dsub2_then_hsub
    9338             :       0,        // dsub2_then_ssub
    9339             :       47,       // qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9340             :       47,       // qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9341             :       47,       // qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9342             :       47,       // qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9343             :       0,        // qsub3_then_bsub
    9344             :       0,        // qsub3_then_dsub
    9345             :       0,        // qsub3_then_hsub
    9346             :       0,        // qsub3_then_ssub
    9347             :       47,       // qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9348             :       47,       // qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9349             :       47,       // qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9350             :       47,       // qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9351             :       0,        // subo64_then_sub_32
    9352             :       0,        // dsub0_dsub1
    9353             :       0,        // dsub0_dsub1_dsub2
    9354             :       0,        // dsub1_dsub2
    9355             :       0,        // dsub1_dsub2_dsub3
    9356             :       0,        // dsub2_dsub3
    9357             :       47,       // dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9358             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9359             :       47,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9360             :       47,       // qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9361             :       0,        // qsub0_qsub1_qsub2
    9362             :       47,       // qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9363             :       0,        // qsub1_qsub2_qsub3
    9364             :       0,        // qsub2_qsub3
    9365             :       47,       // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    9366             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9367             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9368             :       0,        // sub_32_subo64_then_sub_32
    9369             :     },
    9370             :     {   // QQQQ
    9371             :       48,       // bsub -> QQQQ
    9372             :       48,       // dsub -> QQQQ
    9373             :       0,        // dsub0
    9374             :       0,        // dsub1
    9375             :       0,        // dsub2
    9376             :       0,        // dsub3
    9377             :       48,       // hsub -> QQQQ
    9378             :       0,        // qhisub
    9379             :       0,        // qsub
    9380             :       48,       // qsub0 -> QQQQ
    9381             :       48,       // qsub1 -> QQQQ
    9382             :       48,       // qsub2 -> QQQQ
    9383             :       48,       // qsub3 -> QQQQ
    9384             :       48,       // ssub -> QQQQ
    9385             :       0,        // sub_32
    9386             :       0,        // sube32
    9387             :       0,        // sube64
    9388             :       0,        // subo32
    9389             :       0,        // subo64
    9390             :       0,        // zsub
    9391             :       0,        // zsub_hi
    9392             :       0,        // dsub1_then_bsub
    9393             :       0,        // dsub1_then_hsub
    9394             :       0,        // dsub1_then_ssub
    9395             :       0,        // dsub3_then_bsub
    9396             :       0,        // dsub3_then_hsub
    9397             :       0,        // dsub3_then_ssub
    9398             :       0,        // dsub2_then_bsub
    9399             :       0,        // dsub2_then_hsub
    9400             :       0,        // dsub2_then_ssub
    9401             :       48,       // qsub1_then_bsub -> QQQQ
    9402             :       48,       // qsub1_then_dsub -> QQQQ
    9403             :       48,       // qsub1_then_hsub -> QQQQ
    9404             :       48,       // qsub1_then_ssub -> QQQQ
    9405             :       48,       // qsub3_then_bsub -> QQQQ
    9406             :       48,       // qsub3_then_dsub -> QQQQ
    9407             :       48,       // qsub3_then_hsub -> QQQQ
    9408             :       48,       // qsub3_then_ssub -> QQQQ
    9409             :       48,       // qsub2_then_bsub -> QQQQ
    9410             :       48,       // qsub2_then_dsub -> QQQQ
    9411             :       48,       // qsub2_then_hsub -> QQQQ
    9412             :       48,       // qsub2_then_ssub -> QQQQ
    9413             :       0,        // subo64_then_sub_32
    9414             :       0,        // dsub0_dsub1
    9415             :       0,        // dsub0_dsub1_dsub2
    9416             :       0,        // dsub1_dsub2
    9417             :       0,        // dsub1_dsub2_dsub3
    9418             :       0,        // dsub2_dsub3
    9419             :       48,       // dsub_qsub1_then_dsub -> QQQQ
    9420             :       48,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ
    9421             :       48,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ
    9422             :       48,       // qsub0_qsub1 -> QQQQ
    9423             :       48,       // qsub0_qsub1_qsub2 -> QQQQ
    9424             :       48,       // qsub1_qsub2 -> QQQQ
    9425             :       48,       // qsub1_qsub2_qsub3 -> QQQQ
    9426             :       48,       // qsub2_qsub3 -> QQQQ
    9427             :       48,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ
    9428             :       48,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ
    9429             :       48,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ
    9430             :       0,        // sub_32_subo64_then_sub_32
    9431             :     },
    9432             :     {   // QQQQ_with_qsub0_in_FPR128_lo
    9433             :       49,       // bsub -> QQQQ_with_qsub0_in_FPR128_lo
    9434             :       49,       // dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9435             :       0,        // dsub0
    9436             :       0,        // dsub1
    9437             :       0,        // dsub2
    9438             :       0,        // dsub3
    9439             :       49,       // hsub -> QQQQ_with_qsub0_in_FPR128_lo
    9440             :       0,        // qhisub
    9441             :       0,        // qsub
    9442             :       49,       // qsub0 -> QQQQ_with_qsub0_in_FPR128_lo
    9443             :       49,       // qsub1 -> QQQQ_with_qsub0_in_FPR128_lo
    9444             :       49,       // qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
    9445             :       49,       // qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
    9446             :       49,       // ssub -> QQQQ_with_qsub0_in_FPR128_lo
    9447             :       0,        // sub_32
    9448             :       0,        // sube32
    9449             :       0,        // sube64
    9450             :       0,        // subo32
    9451             :       0,        // subo64
    9452             :       0,        // zsub
    9453             :       0,        // zsub_hi
    9454             :       0,        // dsub1_then_bsub
    9455             :       0,        // dsub1_then_hsub
    9456             :       0,        // dsub1_then_ssub
    9457             :       0,        // dsub3_then_bsub
    9458             :       0,        // dsub3_then_hsub
    9459             :       0,        // dsub3_then_ssub
    9460             :       0,        // dsub2_then_bsub
    9461             :       0,        // dsub2_then_hsub
    9462             :       0,        // dsub2_then_ssub
    9463             :       49,       // qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
    9464             :       49,       // qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9465             :       49,       // qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
    9466             :       49,       // qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
    9467             :       49,       // qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
    9468             :       49,       // qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9469             :       49,       // qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
    9470             :       49,       // qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
    9471             :       49,       // qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
    9472             :       49,       // qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9473             :       49,       // qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
    9474             :       49,       // qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
    9475             :       0,        // subo64_then_sub_32
    9476             :       0,        // dsub0_dsub1
    9477             :       0,        // dsub0_dsub1_dsub2
    9478             :       0,        // dsub1_dsub2
    9479             :       0,        // dsub1_dsub2_dsub3
    9480             :       0,        // dsub2_dsub3
    9481             :       49,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9482             :       49,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9483             :       49,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9484             :       49,       // qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo
    9485             :       49,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
    9486             :       49,       // qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
    9487             :       49,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
    9488             :       49,       // qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
    9489             :       49,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9490             :       49,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9491             :       49,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
    9492             :       0,        // sub_32_subo64_then_sub_32
    9493             :     },
    9494             :     {   // QQQQ_with_qsub1_in_FPR128_lo
    9495             :       50,       // bsub -> QQQQ_with_qsub1_in_FPR128_lo
    9496             :       50,       // dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9497             :       0,        // dsub0
    9498             :       0,        // dsub1
    9499             :       0,        // dsub2
    9500             :       0,        // dsub3
    9501             :       50,       // hsub -> QQQQ_with_qsub1_in_FPR128_lo
    9502             :       0,        // qhisub
    9503             :       0,        // qsub
    9504             :       50,       // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo
    9505             :       50,       // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo
    9506             :       50,       // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
    9507             :       50,       // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
    9508             :       50,       // ssub -> QQQQ_with_qsub1_in_FPR128_lo
    9509             :       0,        // sub_32
    9510             :       0,        // sube32
    9511             :       0,        // sube64
    9512             :       0,        // subo32
    9513             :       0,        // subo64
    9514             :       0,        // zsub
    9515             :       0,        // zsub_hi
    9516             :       0,        // dsub1_then_bsub
    9517             :       0,        // dsub1_then_hsub
    9518             :       0,        // dsub1_then_ssub
    9519             :       0,        // dsub3_then_bsub
    9520             :       0,        // dsub3_then_hsub
    9521             :       0,        // dsub3_then_ssub
    9522             :       0,        // dsub2_then_bsub
    9523             :       0,        // dsub2_then_hsub
    9524             :       0,        // dsub2_then_ssub
    9525             :       50,       // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
    9526             :       50,       // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9527             :       50,       // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
    9528             :       50,       // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
    9529             :       50,       // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
    9530             :       50,       // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9531             :       50,       // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
    9532             :       50,       // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
    9533             :       50,       // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
    9534             :       50,       // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9535             :       50,       // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
    9536             :       50,       // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
    9537             :       0,        // subo64_then_sub_32
    9538             :       0,        // dsub0_dsub1
    9539             :       0,        // dsub0_dsub1_dsub2
    9540             :       0,        // dsub1_dsub2
    9541             :       0,        // dsub1_dsub2_dsub3
    9542             :       0,        // dsub2_dsub3
    9543             :       50,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9544             :       50,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9545             :       50,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9546             :       50,       // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo
    9547             :       50,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
    9548             :       50,       // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
    9549             :       50,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
    9550             :       50,       // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
    9551             :       50,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9552             :       50,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9553             :       50,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
    9554             :       0,        // sub_32_subo64_then_sub_32
    9555             :     },
    9556             :     {   // QQQQ_with_qsub2_in_FPR128_lo
    9557             :       51,       // bsub -> QQQQ_with_qsub2_in_FPR128_lo
    9558             :       51,       // dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9559             :       0,        // dsub0
    9560             :       0,        // dsub1
    9561             :       0,        // dsub2
    9562             :       0,        // dsub3
    9563             :       51,       // hsub -> QQQQ_with_qsub2_in_FPR128_lo
    9564             :       0,        // qhisub
    9565             :       0,        // qsub
    9566             :       51,       // qsub0 -> QQQQ_with_qsub2_in_FPR128_lo
    9567             :       51,       // qsub1 -> QQQQ_with_qsub2_in_FPR128_lo
    9568             :       51,       // qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
    9569             :       51,       // qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
    9570             :       51,       // ssub -> QQQQ_with_qsub2_in_FPR128_lo
    9571             :       0,        // sub_32
    9572             :       0,        // sube32
    9573             :       0,        // sube64
    9574             :       0,        // subo32
    9575             :       0,        // subo64
    9576             :       0,        // zsub
    9577             :       0,        // zsub_hi
    9578             :       0,        // dsub1_then_bsub
    9579             :       0,        // dsub1_then_hsub
    9580             :       0,        // dsub1_then_ssub
    9581             :       0,        // dsub3_then_bsub
    9582             :       0,        // dsub3_then_hsub
    9583             :       0,        // dsub3_then_ssub
    9584             :       0,        // dsub2_then_bsub
    9585             :       0,        // dsub2_then_hsub
    9586             :       0,        // dsub2_then_ssub
    9587             :       51,       // qsub1_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
    9588             :       51,       // qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9589             :       51,       // qsub1_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
    9590             :       51,       // qsub1_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
    9591             :       51,       // qsub3_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
    9592             :       51,       // qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9593             :       51,       // qsub3_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
    9594             :       51,       // qsub3_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
    9595             :       51,       // qsub2_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
    9596             :       51,       // qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9597             :       51,       // qsub2_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
    9598             :       51,       // qsub2_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
    9599             :       0,        // subo64_then_sub_32
    9600             :       0,        // dsub0_dsub1
    9601             :       0,        // dsub0_dsub1_dsub2
    9602             :       0,        // dsub1_dsub2
    9603             :       0,        // dsub1_dsub2_dsub3
    9604             :       0,        // dsub2_dsub3
    9605             :       51,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9606             :       51,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9607             :       51,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9608             :       51,       // qsub0_qsub1 -> QQQQ_with_qsub2_in_FPR128_lo
    9609             :       51,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
    9610             :       51,       // qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
    9611             :       51,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
    9612             :       51,       // qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
    9613             :       51,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9614             :       51,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9615             :       51,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
    9616             :       0,        // sub_32_subo64_then_sub_32
    9617             :     },
    9618             :     {   // QQQQ_with_qsub3_in_FPR128_lo
    9619             :       52,       // bsub -> QQQQ_with_qsub3_in_FPR128_lo
    9620             :       52,       // dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9621             :       0,        // dsub0
    9622             :       0,        // dsub1
    9623             :       0,        // dsub2
    9624             :       0,        // dsub3
    9625             :       52,       // hsub -> QQQQ_with_qsub3_in_FPR128_lo
    9626             :       0,        // qhisub
    9627             :       0,        // qsub
    9628             :       52,       // qsub0 -> QQQQ_with_qsub3_in_FPR128_lo
    9629             :       52,       // qsub1 -> QQQQ_with_qsub3_in_FPR128_lo
    9630             :       52,       // qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
    9631             :       52,       // qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
    9632             :       52,       // ssub -> QQQQ_with_qsub3_in_FPR128_lo
    9633             :       0,        // sub_32
    9634             :       0,        // sube32
    9635             :       0,        // sube64
    9636             :       0,        // subo32
    9637             :       0,        // subo64
    9638             :       0,        // zsub
    9639             :       0,        // zsub_hi
    9640             :       0,        // dsub1_then_bsub
    9641             :       0,        // dsub1_then_hsub
    9642             :       0,        // dsub1_then_ssub
    9643             :       0,        // dsub3_then_bsub
    9644             :       0,        // dsub3_then_hsub
    9645             :       0,        // dsub3_then_ssub
    9646             :       0,        // dsub2_then_bsub
    9647             :       0,        // dsub2_then_hsub
    9648             :       0,        // dsub2_then_ssub
    9649             :       52,       // qsub1_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
    9650             :       52,       // qsub1_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9651             :       52,       // qsub1_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
    9652             :       52,       // qsub1_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
    9653             :       52,       // qsub3_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
    9654             :       52,       // qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9655             :       52,       // qsub3_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
    9656             :       52,       // qsub3_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
    9657             :       52,       // qsub2_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
    9658             :       52,       // qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9659             :       52,       // qsub2_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
    9660             :       52,       // qsub2_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
    9661             :       0,        // subo64_then_sub_32
    9662             :       0,        // dsub0_dsub1
    9663             :       0,        // dsub0_dsub1_dsub2
    9664             :       0,        // dsub1_dsub2
    9665             :       0,        // dsub1_dsub2_dsub3
    9666             :       0,        // dsub2_dsub3
    9667             :       52,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9668             :       52,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9669             :       52,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9670             :       52,       // qsub0_qsub1 -> QQQQ_with_qsub3_in_FPR128_lo
    9671             :       52,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
    9672             :       52,       // qsub1_qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
    9673             :       52,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
    9674             :       52,       // qsub2_qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
    9675             :       52,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9676             :       52,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9677             :       52,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
    9678             :       0,        // sub_32_subo64_then_sub_32
    9679             :     },
    9680             :     {   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9681             :       53,       // bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9682             :       53,       // dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9683             :       0,        // dsub0
    9684             :       0,        // dsub1
    9685             :       0,        // dsub2
    9686             :       0,        // dsub3
    9687             :       53,       // hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9688             :       0,        // qhisub
    9689             :       0,        // qsub
    9690             :       53,       // qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9691             :       53,       // qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9692             :       53,       // qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9693             :       53,       // qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9694             :       53,       // ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9695             :       0,        // sub_32
    9696             :       0,        // sube32
    9697             :       0,        // sube64
    9698             :       0,        // subo32
    9699             :       0,        // subo64
    9700             :       0,        // zsub
    9701             :       0,        // zsub_hi
    9702             :       0,        // dsub1_then_bsub
    9703             :       0,        // dsub1_then_hsub
    9704             :       0,        // dsub1_then_ssub
    9705             :       0,        // dsub3_then_bsub
    9706             :       0,        // dsub3_then_hsub
    9707             :       0,        // dsub3_then_ssub
    9708             :       0,        // dsub2_then_bsub
    9709             :       0,        // dsub2_then_hsub
    9710             :       0,        // dsub2_then_ssub
    9711             :       53,       // qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9712             :       53,       // qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9713             :       53,       // qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9714             :       53,       // qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9715             :       53,       // qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9716             :       53,       // qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9717             :       53,       // qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9718             :       53,       // qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9719             :       53,       // qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9720             :       53,       // qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9721             :       53,       // qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9722             :       53,       // qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9723             :       0,        // subo64_then_sub_32
    9724             :       0,        // dsub0_dsub1
    9725             :       0,        // dsub0_dsub1_dsub2
    9726             :       0,        // dsub1_dsub2
    9727             :       0,        // dsub1_dsub2_dsub3
    9728             :       0,        // dsub2_dsub3
    9729             :       53,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9730             :       53,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9731             :       53,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9732             :       53,       // qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9733             :       53,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9734             :       53,       // qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9735             :       53,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9736             :       53,       // qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9737             :       53,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9738             :       53,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9739             :       53,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    9740             :       0,        // sub_32_subo64_then_sub_32
    9741             :     },
    9742             :     {   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9743             :       54,       // bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9744             :       54,       // dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9745             :       0,        // dsub0
    9746             :       0,        // dsub1
    9747             :       0,        // dsub2
    9748             :       0,        // dsub3
    9749             :       54,       // hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9750             :       0,        // qhisub
    9751             :       0,        // qsub
    9752             :       54,       // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9753             :       54,       // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9754             :       54,       // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9755             :       54,       // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9756             :       54,       // ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9757             :       0,        // sub_32
    9758             :       0,        // sube32
    9759             :       0,        // sube64
    9760             :       0,        // subo32
    9761             :       0,        // subo64
    9762             :       0,        // zsub
    9763             :       0,        // zsub_hi
    9764             :       0,        // dsub1_then_bsub
    9765             :       0,        // dsub1_then_hsub
    9766             :       0,        // dsub1_then_ssub
    9767             :       0,        // dsub3_then_bsub
    9768             :       0,        // dsub3_then_hsub
    9769             :       0,        // dsub3_then_ssub
    9770             :       0,        // dsub2_then_bsub
    9771             :       0,        // dsub2_then_hsub
    9772             :       0,        // dsub2_then_ssub
    9773             :       54,       // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9774             :       54,       // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9775             :       54,       // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9776             :       54,       // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9777             :       54,       // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9778             :       54,       // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9779             :       54,       // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9780             :       54,       // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9781             :       54,       // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9782             :       54,       // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9783             :       54,       // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9784             :       54,       // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9785             :       0,        // subo64_then_sub_32
    9786             :       0,        // dsub0_dsub1
    9787             :       0,        // dsub0_dsub1_dsub2
    9788             :       0,        // dsub1_dsub2
    9789             :       0,        // dsub1_dsub2_dsub3
    9790             :       0,        // dsub2_dsub3
    9791             :       54,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9792             :       54,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9793             :       54,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9794             :       54,       // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9795             :       54,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9796             :       54,       // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9797             :       54,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9798             :       54,       // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9799             :       54,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9800             :       54,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9801             :       54,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9802             :       0,        // sub_32_subo64_then_sub_32
    9803             :     },
    9804             :     {   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9805             :       55,       // bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9806             :       55,       // dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9807             :       0,        // dsub0
    9808             :       0,        // dsub1
    9809             :       0,        // dsub2
    9810             :       0,        // dsub3
    9811             :       55,       // hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9812             :       0,        // qhisub
    9813             :       0,        // qsub
    9814             :       55,       // qsub0 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9815             :       55,       // qsub1 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9816             :       55,       // qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9817             :       55,       // qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9818             :       55,       // ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9819             :       0,        // sub_32
    9820             :       0,        // sube32
    9821             :       0,        // sube64
    9822             :       0,        // subo32
    9823             :       0,        // subo64
    9824             :       0,        // zsub
    9825             :       0,        // zsub_hi
    9826             :       0,        // dsub1_then_bsub
    9827             :       0,        // dsub1_then_hsub
    9828             :       0,        // dsub1_then_ssub
    9829             :       0,        // dsub3_then_bsub
    9830             :       0,        // dsub3_then_hsub
    9831             :       0,        // dsub3_then_ssub
    9832             :       0,        // dsub2_then_bsub
    9833             :       0,        // dsub2_then_hsub
    9834             :       0,        // dsub2_then_ssub
    9835             :       55,       // qsub1_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9836             :       55,       // qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9837             :       55,       // qsub1_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9838             :       55,       // qsub1_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9839             :       55,       // qsub3_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9840             :       55,       // qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9841             :       55,       // qsub3_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9842             :       55,       // qsub3_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9843             :       55,       // qsub2_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9844             :       55,       // qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9845             :       55,       // qsub2_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9846             :       55,       // qsub2_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9847             :       0,        // subo64_then_sub_32
    9848             :       0,        // dsub0_dsub1
    9849             :       0,        // dsub0_dsub1_dsub2
    9850             :       0,        // dsub1_dsub2
    9851             :       0,        // dsub1_dsub2_dsub3
    9852             :       0,        // dsub2_dsub3
    9853             :       55,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9854             :       55,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9855             :       55,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9856             :       55,       // qsub0_qsub1 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9857             :       55,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9858             :       55,       // qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9859             :       55,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9860             :       55,       // qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9861             :       55,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9862             :       55,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9863             :       55,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9864             :       0,        // sub_32_subo64_then_sub_32
    9865             :     },
    9866             :     {   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9867             :       56,       // bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9868             :       56,       // dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9869             :       0,        // dsub0
    9870             :       0,        // dsub1
    9871             :       0,        // dsub2
    9872             :       0,        // dsub3
    9873             :       56,       // hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9874             :       0,        // qhisub
    9875             :       0,        // qsub
    9876             :       56,       // qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9877             :       56,       // qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9878             :       56,       // qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9879             :       56,       // qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9880             :       56,       // ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9881             :       0,        // sub_32
    9882             :       0,        // sube32
    9883             :       0,        // sube64
    9884             :       0,        // subo32
    9885             :       0,        // subo64
    9886             :       0,        // zsub
    9887             :       0,        // zsub_hi
    9888             :       0,        // dsub1_then_bsub
    9889             :       0,        // dsub1_then_hsub
    9890             :       0,        // dsub1_then_ssub
    9891             :       0,        // dsub3_then_bsub
    9892             :       0,        // dsub3_then_hsub
    9893             :       0,        // dsub3_then_ssub
    9894             :       0,        // dsub2_then_bsub
    9895             :       0,        // dsub2_then_hsub
    9896             :       0,        // dsub2_then_ssub
    9897             :       56,       // qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9898             :       56,       // qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9899             :       56,       // qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9900             :       56,       // qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9901             :       56,       // qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9902             :       56,       // qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9903             :       56,       // qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9904             :       56,       // qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9905             :       56,       // qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9906             :       56,       // qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9907             :       56,       // qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9908             :       56,       // qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9909             :       0,        // subo64_then_sub_32
    9910             :       0,        // dsub0_dsub1
    9911             :       0,        // dsub0_dsub1_dsub2
    9912             :       0,        // dsub1_dsub2
    9913             :       0,        // dsub1_dsub2_dsub3
    9914             :       0,        // dsub2_dsub3
    9915             :       56,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9916             :       56,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9917             :       56,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9918             :       56,       // qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9919             :       56,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9920             :       56,       // qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9921             :       56,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9922             :       56,       // qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9923             :       56,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9924             :       56,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9925             :       56,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    9926             :       0,        // sub_32_subo64_then_sub_32
    9927             :     },
    9928             :     {   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9929             :       57,       // bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9930             :       57,       // dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9931             :       0,        // dsub0
    9932             :       0,        // dsub1
    9933             :       0,        // dsub2
    9934             :       0,        // dsub3
    9935             :       57,       // hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9936             :       0,        // qhisub
    9937             :       0,        // qsub
    9938             :       57,       // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9939             :       57,       // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9940             :       57,       // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9941             :       57,       // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9942             :       57,       // ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9943             :       0,        // sub_32
    9944             :       0,        // sube32
    9945             :       0,        // sube64
    9946             :       0,        // subo32
    9947             :       0,        // subo64
    9948             :       0,        // zsub
    9949             :       0,        // zsub_hi
    9950             :       0,        // dsub1_then_bsub
    9951             :       0,        // dsub1_then_hsub
    9952             :       0,        // dsub1_then_ssub
    9953             :       0,        // dsub3_then_bsub
    9954             :       0,        // dsub3_then_hsub
    9955             :       0,        // dsub3_then_ssub
    9956             :       0,        // dsub2_then_bsub
    9957             :       0,        // dsub2_then_hsub
    9958             :       0,        // dsub2_then_ssub
    9959             :       57,       // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9960             :       57,       // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9961             :       57,       // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9962             :       57,       // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9963             :       57,       // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9964             :       57,       // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9965             :       57,       // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9966             :       57,       // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9967             :       57,       // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9968             :       57,       // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9969             :       57,       // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9970             :       57,       // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9971             :       0,        // subo64_then_sub_32
    9972             :       0,        // dsub0_dsub1
    9973             :       0,        // dsub0_dsub1_dsub2
    9974             :       0,        // dsub1_dsub2
    9975             :       0,        // dsub1_dsub2_dsub3
    9976             :       0,        // dsub2_dsub3
    9977             :       57,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9978             :       57,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9979             :       57,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9980             :       57,       // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9981             :       57,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9982             :       57,       // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9983             :       57,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9984             :       57,       // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9985             :       57,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9986             :       57,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9987             :       57,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9988             :       0,        // sub_32_subo64_then_sub_32
    9989             :     },
    9990             :     {   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9991             :       58,       // bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9992             :       58,       // dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9993             :       0,        // dsub0
    9994             :       0,        // dsub1
    9995             :       0,        // dsub2
    9996             :       0,        // dsub3
    9997             :       58,       // hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    9998             :       0,        // qhisub
    9999             :       0,        // qsub
   10000             :       58,       // qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10001             :       58,       // qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10002             :       58,       // qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10003             :       58,       // qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10004             :       58,       // ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10005             :       0,        // sub_32
   10006             :       0,        // sube32
   10007             :       0,        // sube64
   10008             :       0,        // subo32
   10009             :       0,        // subo64
   10010             :       0,        // zsub
   10011             :       0,        // zsub_hi
   10012             :       0,        // dsub1_then_bsub
   10013             :       0,        // dsub1_then_hsub
   10014             :       0,        // dsub1_then_ssub
   10015             :       0,        // dsub3_then_bsub
   10016             :       0,        // dsub3_then_hsub
   10017             :       0,        // dsub3_then_ssub
   10018             :       0,        // dsub2_then_bsub
   10019             :       0,        // dsub2_then_hsub
   10020             :       0,        // dsub2_then_ssub
   10021             :       58,       // qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10022             :       58,       // qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10023             :       58,       // qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10024             :       58,       // qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10025             :       58,       // qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10026             :       58,       // qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10027             :       58,       // qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10028             :       58,       // qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10029             :       58,       // qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10030             :       58,       // qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10031             :       58,       // qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10032             :       58,       // qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10033             :       0,        // subo64_then_sub_32
   10034             :       0,        // dsub0_dsub1
   10035             :       0,        // dsub0_dsub1_dsub2
   10036             :       0,        // dsub1_dsub2
   10037             :       0,        // dsub1_dsub2_dsub3
   10038             :       0,        // dsub2_dsub3
   10039             :       58,       // dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10040             :       58,       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10041             :       58,       // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10042             :       58,       // qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10043             :       58,       // qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10044             :       58,       // qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10045             :       58,       // qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10046             :       58,       // qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10047             :       58,       // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10048             :       58,       // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10049             :       58,       // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10050             :       0,        // sub_32_subo64_then_sub_32
   10051             :     },
   10052             :   };
   10053             :   assert(RC && "Missing regclass");
   10054       32153 :   if (!Idx) return RC;
   10055       32153 :   --Idx;
   10056             :   assert(Idx < 60 && "Bad subreg");
   10057       64306 :   unsigned TV = Table[RC->getID()][Idx];
   10058       32153 :   return TV ? getRegClass(TV - 1) : nullptr;
   10059             : }
   10060             : 
   10061             : /// Get the weight in units of pressure for this register class.
   10062      104193 : const RegClassWeight &AArch64GenRegisterInfo::
   10063             : getRegClassWeight(const TargetRegisterClass *RC) const {
   10064             :   static const RegClassWeight RCWeightTable[] = {
   10065             :     {1, 32},    // FPR8
   10066             :     {1, 32},    // FPR16
   10067             :     {1, 16},    // PPR
   10068             :     {1, 8},     // PPR_3b
   10069             :     {1, 33},    // GPR32all
   10070             :     {1, 32},    // FPR32
   10071             :     {1, 32},    // GPR32
   10072             :     {1, 32},    // GPR32sp
   10073             :     {1, 31},    // GPR32common
   10074             :     {0, 0},     // CCR
   10075             :     {1, 1},     // GPR32sponly
   10076             :     {2, 32},    // WSeqPairsClass
   10077             :     {2, 32},    // WSeqPairsClass_with_sube32_in_GPR32common
   10078             :     {2, 32},    // WSeqPairsClass_with_subo32_in_GPR32common
   10079             :     {2, 31},    // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
   10080             :     {1, 33},    // GPR64all
   10081             :     {1, 32},    // FPR64
   10082             :     {1, 32},    // GPR64
   10083             :     {1, 32},    // GPR64sp
   10084             :     {1, 31},    // GPR64common
   10085             :     {1, 19},    // tcGPR64
   10086             :     {1, 1},     // GPR64sponly
   10087             :     {2, 32},    // DD
   10088             :     {2, 32},    // XSeqPairsClass
   10089             :     {2, 32},    // XSeqPairsClass_with_sub_32_in_GPR32common
   10090             :     {2, 32},    // XSeqPairsClass_with_subo64_in_GPR64common
   10091             :     {2, 31},    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
   10092             :     {2, 20},    // XSeqPairsClass_with_sube64_in_tcGPR64
   10093             :     {2, 20},    // XSeqPairsClass_with_subo64_in_tcGPR64
   10094             :     {2, 19},    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
   10095             :     {1, 32},    // FPR128
   10096             :     {2, 64},    // ZPR
   10097             :     {1, 16},    // FPR128_lo
   10098             :     {2, 32},    // ZPR_with_zsub_in_FPR128_lo
   10099             :     {3, 32},    // DDD
   10100             :     {4, 32},    // DDDD
   10101             :     {2, 32},    // QQ
   10102             :     {2, 17},    // QQ_with_qsub0_in_FPR128_lo
   10103             :     {2, 17},    // QQ_with_qsub1_in_FPR128_lo
   10104             :     {2, 16},    // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
   10105             :     {3, 32},    // QQQ
   10106             :     {3, 18},    // QQQ_with_qsub0_in_FPR128_lo
   10107             :     {3, 18},    // QQQ_with_qsub1_in_FPR128_lo
   10108             :     {3, 18},    // QQQ_with_qsub2_in_FPR128_lo
   10109             :     {3, 17},    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
   10110             :     {3, 17},    // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
   10111             :     {3, 16},    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
   10112             :     {4, 32},    // QQQQ
   10113             :     {4, 19},    // QQQQ_with_qsub0_in_FPR128_lo
   10114             :     {4, 19},    // QQQQ_with_qsub1_in_FPR128_lo
   10115             :     {4, 19},    // QQQQ_with_qsub2_in_FPR128_lo
   10116             :     {4, 19},    // QQQQ_with_qsub3_in_FPR128_lo
   10117             :     {4, 18},    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
   10118             :     {4, 18},    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
   10119             :     {4, 18},    // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10120             :     {4, 17},    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
   10121             :     {4, 17},    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10122             :     {4, 16},    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
   10123             :   };
   10124      208386 :   return RCWeightTable[RC->getID()];
   10125             : }
   10126             : 
   10127             : /// Get the weight in units of pressure for this register unit.
   10128       18407 : unsigned AArch64GenRegisterInfo::
   10129             : getRegUnitWeight(unsigned RegUnit) const {
   10130             :   assert(RegUnit < 114 && "invalid register unit");
   10131             :   // All register units have unit weight.
   10132       18407 :   return 1;
   10133             : }
   10134             : 
   10135             : 
   10136             : // Get the number of dimensions of register pressure.
   10137       18883 : unsigned AArch64GenRegisterInfo::getNumRegPressureSets() const {
   10138       18883 :   return 14;
   10139             : }
   10140             : 
   10141             : // Get the name of this register unit pressure set.
   10142           0 : const char *AArch64GenRegisterInfo::
   10143             : getRegPressureSetName(unsigned Idx) const {
   10144             :   static const char *const PressureNameTable[] = {
   10145             :     "GPR32sponly",
   10146             :     "PPR_3b",
   10147             :     "PPR",
   10148             :     "tcGPR64",
   10149             :     "FPR128_lo",
   10150             :     "FPR8",
   10151             :     "ZPR_with_zsub_in_FPR128_lo",
   10152             :     "GPR32",
   10153             :     "ZPR_with_zsub_in_FPR128_lo+FPR128_lo",
   10154             :     "ZPR_with_zsub_in_FPR128_lo+QQ_with_qsub1_in_FPR128_lo",
   10155             :     "ZPR_with_zsub_in_FPR128_lo+QQQ_with_qsub2_in_FPR128_lo",
   10156             :     "ZPR_with_zsub_in_FPR128_lo+QQQQ_with_qsub3_in_FPR128_lo",
   10157             :     "FPR8+ZPR_with_zsub_in_FPR128_lo",
   10158             :     "ZPR",
   10159             :   };
   10160           0 :   return PressureNameTable[Idx];
   10161             : }
   10162             : 
   10163             : // Get the register unit pressure limit for this dimension.
   10164             : // This limit must be adjusted dynamically for reserved registers.
   10165      178798 : unsigned AArch64GenRegisterInfo::
   10166             : getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
   10167             :   static const uint8_t PressureLimitTable[] = {
   10168             :     1,          // 0: GPR32sponly
   10169             :     8,          // 1: PPR_3b
   10170             :     16,         // 2: PPR
   10171             :     21,         // 3: tcGPR64
   10172             :     22,         // 4: FPR128_lo
   10173             :     32,         // 5: FPR8
   10174             :     32,         // 6: ZPR_with_zsub_in_FPR128_lo
   10175             :     33,         // 7: GPR32
   10176             :     35,         // 8: ZPR_with_zsub_in_FPR128_lo+FPR128_lo
   10177             :     35,         // 9: ZPR_with_zsub_in_FPR128_lo+QQ_with_qsub1_in_FPR128_lo
   10178             :     35,         // 10: ZPR_with_zsub_in_FPR128_lo+QQQ_with_qsub2_in_FPR128_lo
   10179             :     35,         // 11: ZPR_with_zsub_in_FPR128_lo+QQQQ_with_qsub3_in_FPR128_lo
   10180             :     48,         // 12: FPR8+ZPR_with_zsub_in_FPR128_lo
   10181             :     64,         // 13: ZPR
   10182             :   };
   10183      178798 :   return PressureLimitTable[Idx];
   10184             : }
   10185             : 
   10186             : /// Table of pressure sets per register class or unit.
   10187             : static const int RCSetsTable[] = {
   10188             :   /* 0 */ 1, 2, -1,
   10189             :   /* 3 */ 0, 7, -1,
   10190             :   /* 6 */ 3, 7, -1,
   10191             :   /* 9 */ 5, 12, 13, -1,
   10192             :   /* 13 */ 4, 5, 8, 12, 13, -1,
   10193             :   /* 19 */ 4, 5, 9, 12, 13, -1,
   10194             :   /* 25 */ 4, 5, 8, 9, 12, 13, -1,
   10195             :   /* 32 */ 4, 5, 10, 12, 13, -1,
   10196             :   /* 38 */ 4, 5, 9, 10, 12, 13, -1,
   10197             :   /* 45 */ 4, 5, 8, 9, 10, 12, 13, -1,
   10198             :   /* 53 */ 4, 5, 11, 12, 13, -1,
   10199             :   /* 59 */ 4, 5, 10, 11, 12, 13, -1,
   10200             :   /* 66 */ 4, 5, 9, 10, 11, 12, 13, -1,
   10201             :   /* 74 */ 4, 5, 6, 8, 9, 10, 11, 12, 13, -1,
   10202             : };
   10203             : 
   10204             : /// Get the dimensions of register pressure impacted by this register class.
   10205             : /// Returns a -1 terminated array of pressure set IDs
   10206      171174 : const int* AArch64GenRegisterInfo::
   10207             : getRegClassPressureSets(const TargetRegisterClass *RC) const {
   10208             :   static const uint8_t RCSetStartTable[] = {
   10209             :     9,9,1,0,4,9,4,4,4,2,3,4,4,4,4,4,9,4,4,4,6,3,9,4,4,4,4,6,6,6,9,11,74,76,9,9,9,45,66,74,9,25,38,59,45,66,74,9,13,19,32,53,25,38,59,45,66,74,};
   10210      342348 :   return &RCSetsTable[RCSetStartTable[RC->getID()]];
   10211             : }
   10212             : 
   10213             : /// Get the dimensions of register pressure impacted by this register unit.
   10214             : /// Returns a -1 terminated array of pressure set IDs
   10215       18407 : const int* AArch64GenRegisterInfo::
   10216             : getRegUnitPressureSets(unsigned RegUnit) const {
   10217             :   assert(RegUnit < 114 && "invalid register unit");
   10218             :   static const uint8_t RUSetStartTable[] = {
   10219             :     4,4,2,3,6,74,74,74,74,74,74,74,74,74,74,74,74,74,74,74,74,45,25,13,9,9,9,9,9,9,9,9,9,9,53,59,66,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,4,4,4,4,4,4,4,4,4,76,76,76,76,76,76,76,76,76,76,76,76,76,76,76,76,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,};
   10220       18407 :   return &RCSetsTable[RUSetStartTable[RegUnit]];
   10221             : }
   10222             : 
   10223             : extern const MCRegisterDesc AArch64RegDesc[];
   10224             : extern const MCPhysReg AArch64RegDiffLists[];
   10225             : extern const LaneBitmask AArch64LaneMaskLists[];
   10226             : extern const char AArch64RegStrings[];
   10227             : extern const char AArch64RegClassStrings[];
   10228             : extern const MCPhysReg AArch64RegUnitRoots[][2];
   10229             : extern const uint16_t AArch64SubRegIdxLists[];
   10230             : extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[];
   10231             : extern const uint16_t AArch64RegEncodingTable[];
   10232             : // AArch64 Dwarf<->LLVM register mappings.
   10233             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[];
   10234             : extern const unsigned AArch64DwarfFlavour0Dwarf2LSize;
   10235             : 
   10236             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[];
   10237             : extern const unsigned AArch64EHFlavour0Dwarf2LSize;
   10238             : 
   10239             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[];
   10240             : extern const unsigned AArch64DwarfFlavour0L2DwarfSize;
   10241             : 
   10242             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[];
   10243             : extern const unsigned AArch64EHFlavour0L2DwarfSize;
   10244             : 
   10245        1326 : AArch64GenRegisterInfo::
   10246             : AArch64GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
   10247        1326 :       unsigned PC, unsigned HwMode)
   10248             :   : TargetRegisterInfo(AArch64RegInfoDesc, RegisterClasses, RegisterClasses+58,
   10249             :              SubRegIndexNameTable, SubRegIndexLaneMaskTable,
   10250        2652 :              LaneBitmask(0xFFFFFFB6), RegClassInfos, HwMode) {
   10251             :   InitMCRegisterInfo(AArch64RegDesc, 564, RA, PC,
   10252             :                      AArch64MCRegisterClasses, 58,
   10253             :                      AArch64RegUnitRoots,
   10254             :                      114,
   10255             :                      AArch64RegDiffLists,
   10256             :                      AArch64LaneMaskLists,
   10257             :                      AArch64RegStrings,
   10258             :                      AArch64RegClassStrings,
   10259             :                      AArch64SubRegIdxLists,
   10260             :                      61,
   10261             :                      AArch64SubRegIdxRanges,
   10262             :                      AArch64RegEncodingTable);
   10263             : 
   10264        1326 :   switch (DwarfFlavour) {
   10265           0 :   default:
   10266           0 :     llvm_unreachable("Unknown DWARF flavour");
   10267        1326 :   case 0:
   10268        1326 :     mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
   10269             :     break;
   10270             :   }
   10271        1326 :   switch (EHFlavour) {
   10272           0 :   default:
   10273           0 :     llvm_unreachable("Unknown DWARF flavour");
   10274        1326 :   case 0:
   10275        1326 :     mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
   10276             :     break;
   10277             :   }
   10278        1326 :   switch (DwarfFlavour) {
   10279           0 :   default:
   10280           0 :     llvm_unreachable("Unknown DWARF flavour");
   10281        1326 :   case 0:
   10282        1326 :     mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
   10283             :     break;
   10284             :   }
   10285        1326 :   switch (EHFlavour) {
   10286           0 :   default:
   10287           0 :     llvm_unreachable("Unknown DWARF flavour");
   10288        1326 :   case 0:
   10289        1326 :     mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
   10290             :     break;
   10291             :   }
   10292        1326 : }
   10293             : 
   10294             : static const MCPhysReg CSR_AArch64_AAPCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
   10295             : static const uint32_t CSR_AArch64_AAPCS_RegMask[] = { 0x00ff0006, 0x00ff0000, 0x00ff0000, 0x00000000, 0x00000000, 0x000000ff, 0x007ff800, 0x000ffc00, 0x00000000, 0xf0000000, 0xf0000007, 0xf0000001, 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x009ffe00, 0x000ff800, };
   10296             : static const MCPhysReg CSR_AArch64_AAPCS_SwiftError_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
   10297             : static const uint32_t CSR_AArch64_AAPCS_SwiftError_RegMask[] = { 0x00ff0006, 0x00ff0000, 0x00ff0000, 0x00000000, 0x00000000, 0x000000ff, 0x007fd800, 0x000fec00, 0x00000000, 0xf0000000, 0xf0000007, 0xf0000001, 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x009ff200, 0x000fc800, };
   10298             : static const MCPhysReg CSR_AArch64_AAPCS_ThisReturn_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, 0 };
   10299             : static const uint32_t CSR_AArch64_AAPCS_ThisReturn_RegMask[] = { 0x00ff0006, 0x00ff0000, 0x00ff0000, 0x00000000, 0x00000000, 0x010000ff, 0x00fff800, 0x000ffc00, 0x00000000, 0xf0000000, 0xf0000007, 0xf0000001, 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x009ffe00, 0x000ff800, };
   10300             : static const MCPhysReg CSR_AArch64_AllRegs_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
   10301             : static const uint32_t CSR_AArch64_AllRegs_RegMask[] = { 0xffffff36, 0xffffffff, 0xffffffff, 0xff0000ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x000fffff, 0x00000000, 0xfff00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffcfffff, 0xff9fffff, 0x000fffff, };
   10302             : static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 };
   10303             : static const uint32_t CSR_AArch64_CXX_TLS_Darwin_RegMask[] = { 0xffffff06, 0xffffffff, 0xffffffff, 0x000000ff, 0xff000000, 0xfeffffff, 0xff7ff87f, 0x000ffc3f, 0x00000000, 0xfff00000, 0xffffffff, 0xffffffff, 0x000fffff, 0x00000000, 0x00000000, 0xff800000, 0xfe9ffe0f, 0x000ff83f, };
   10304             : static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_PE_SaveList[] = { AArch64::LR, AArch64::FP, 0 };
   10305             : static const uint32_t CSR_AArch64_CXX_TLS_Darwin_PE_RegMask[] = { 0x00000006, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00600000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00180000, 0x00000000, };
   10306             : static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 };
   10307             : static const uint32_t CSR_AArch64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0xffffff00, 0xffffffff, 0xffffffff, 0x000000ff, 0xff000000, 0xfeffffff, 0xff1ff87f, 0x000ffc3f, 0x00000000, 0xfff00000, 0xffffffff, 0xffffffff, 0x000fffff, 0x00000000, 0x00000000, 0xff800000, 0xfe03fe0f, 0x000ff83f, };
   10308             : static const MCPhysReg CSR_AArch64_NoRegs_SaveList[] = { 0 };
   10309             : static const uint32_t CSR_AArch64_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
   10310             : static const MCPhysReg CSR_AArch64_RT_MostRegs_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, 0 };
   10311             : static const uint32_t CSR_AArch64_RT_MostRegs_RegMask[] = { 0x00ff0006, 0x00ff0000, 0x00ff0000, 0x00000000, 0x00000000, 0x000000ff, 0x007ff8fe, 0x000ffc7f, 0x00000000, 0xf0000000, 0xf0000007, 0xf0000001, 0x00000003, 0x00000000, 0x00000000, 0x80000000, 0x009ffe1f, 0x000ff87e, };
   10312             : static const MCPhysReg CSR_AArch64_StackProbe_Windows_SaveList[] = { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::SP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
   10313             : static const uint32_t CSR_AArch64_StackProbe_Windows_RegMask[] = { 0xffffff32, 0xffffffff, 0xffffffff, 0xff0000ff, 0xffffffff, 0xffffffff, 0xffbffcff, 0x000ffe7f, 0x00000000, 0xfff00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffcfffff, 0xff87ff1f, 0x000ffc7f, };
   10314             : static const MCPhysReg CSR_AArch64_TLS_Darwin_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
   10315             : static const uint32_t CSR_AArch64_TLS_Darwin_RegMask[] = { 0xffffff02, 0xffffffff, 0xffffffff, 0xff0000ff, 0xffffffff, 0xfeffffff, 0xff3ffcff, 0x000ffe7f, 0x00000000, 0xfff00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xff8fffff, 0xfe87ff1f, 0x000ffc7f, };
   10316             : static const MCPhysReg CSR_AArch64_TLS_ELF_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
   10317             : static const uint32_t CSR_AArch64_TLS_ELF_RegMask[] = { 0xffffff02, 0xffffffff, 0xffffffff, 0xff0000ff, 0xffffffff, 0xfeffffff, 0xff3fffff, 0x000fffff, 0x00000000, 0xfff00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xff8fffff, 0xfe87ffff, 0x000fffff, };
   10318             : 
   10319             : 
   10320         781 : ArrayRef<const uint32_t *> AArch64GenRegisterInfo::getRegMasks() const {
   10321             :   static const uint32_t *const Masks[] = {
   10322             :     CSR_AArch64_AAPCS_RegMask,
   10323             :     CSR_AArch64_AAPCS_SwiftError_RegMask,
   10324             :     CSR_AArch64_AAPCS_ThisReturn_RegMask,
   10325             :     CSR_AArch64_AllRegs_RegMask,
   10326             :     CSR_AArch64_CXX_TLS_Darwin_RegMask,
   10327             :     CSR_AArch64_CXX_TLS_Darwin_PE_RegMask,
   10328             :     CSR_AArch64_CXX_TLS_Darwin_ViaCopy_RegMask,
   10329             :     CSR_AArch64_NoRegs_RegMask,
   10330             :     CSR_AArch64_RT_MostRegs_RegMask,
   10331             :     CSR_AArch64_StackProbe_Windows_RegMask,
   10332             :     CSR_AArch64_TLS_Darwin_RegMask,
   10333             :     CSR_AArch64_TLS_ELF_RegMask,
   10334             :   };
   10335         781 :   return makeArrayRef(Masks);
   10336             : }
   10337             : 
   10338          48 : ArrayRef<const char *> AArch64GenRegisterInfo::getRegMaskNames() const {
   10339             :   static const char *const Names[] = {
   10340             :     "CSR_AArch64_AAPCS",
   10341             :     "CSR_AArch64_AAPCS_SwiftError",
   10342             :     "CSR_AArch64_AAPCS_ThisReturn",
   10343             :     "CSR_AArch64_AllRegs",
   10344             :     "CSR_AArch64_CXX_TLS_Darwin",
   10345             :     "CSR_AArch64_CXX_TLS_Darwin_PE",
   10346             :     "CSR_AArch64_CXX_TLS_Darwin_ViaCopy",
   10347             :     "CSR_AArch64_NoRegs",
   10348             :     "CSR_AArch64_RT_MostRegs",
   10349             :     "CSR_AArch64_StackProbe_Windows",
   10350             :     "CSR_AArch64_TLS_Darwin",
   10351             :     "CSR_AArch64_TLS_ELF",
   10352             :   };
   10353          48 :   return makeArrayRef(Names);
   10354             : }
   10355             : 
   10356             : const AArch64FrameLowering *
   10357      194058 : AArch64GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
   10358             :   return static_cast<const AArch64FrameLowering *>(
   10359      194058 :       MF.getSubtarget().getFrameLowering());
   10360             : }
   10361             : 
   10362             : } // end namespace llvm
   10363             : 
   10364             : #endif // GET_REGINFO_TARGET_DESC
   10365             : 

Generated by: LCOV version 1.13