LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenRegisterInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 56 80 70.0 %
Date: 2018-05-20 00:06:23 Functions: 18 21 85.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Register Enum Values                                                *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_REGINFO_ENUM
      11             : #undef GET_REGINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : 
      15             : class MCRegisterClass;
      16             : extern const MCRegisterClass AArch64MCRegisterClasses[];
      17             : 
      18             : namespace AArch64 {
      19             : enum {
      20             :   NoRegister,
      21             :   FFR = 1,
      22             :   FP = 2,
      23             :   LR = 3,
      24             :   NZCV = 4,
      25             :   SP = 5,
      26             :   WSP = 6,
      27             :   WZR = 7,
      28             :   XZR = 8,
      29             :   B0 = 9,
      30             :   B1 = 10,
      31             :   B2 = 11,
      32             :   B3 = 12,
      33             :   B4 = 13,
      34             :   B5 = 14,
      35             :   B6 = 15,
      36             :   B7 = 16,
      37             :   B8 = 17,
      38             :   B9 = 18,
      39             :   B10 = 19,
      40             :   B11 = 20,
      41             :   B12 = 21,
      42             :   B13 = 22,
      43             :   B14 = 23,
      44             :   B15 = 24,
      45             :   B16 = 25,
      46             :   B17 = 26,
      47             :   B18 = 27,
      48             :   B19 = 28,
      49             :   B20 = 29,
      50             :   B21 = 30,
      51             :   B22 = 31,
      52             :   B23 = 32,
      53             :   B24 = 33,
      54             :   B25 = 34,
      55             :   B26 = 35,
      56             :   B27 = 36,
      57             :   B28 = 37,
      58             :   B29 = 38,
      59             :   B30 = 39,
      60             :   B31 = 40,
      61             :   D0 = 41,
      62             :   D1 = 42,
      63             :   D2 = 43,
      64             :   D3 = 44,
      65             :   D4 = 45,
      66             :   D5 = 46,
      67             :   D6 = 47,
      68             :   D7 = 48,
      69             :   D8 = 49,
      70             :   D9 = 50,
      71             :   D10 = 51,
      72             :   D11 = 52,
      73             :   D12 = 53,
      74             :   D13 = 54,
      75             :   D14 = 55,
      76             :   D15 = 56,
      77             :   D16 = 57,
      78             :   D17 = 58,
      79             :   D18 = 59,
      80             :   D19 = 60,
      81             :   D20 = 61,
      82             :   D21 = 62,
      83             :   D22 = 63,
      84             :   D23 = 64,
      85             :   D24 = 65,
      86             :   D25 = 66,
      87             :   D26 = 67,
      88             :   D27 = 68,
      89             :   D28 = 69,
      90             :   D29 = 70,
      91             :   D30 = 71,
      92             :   D31 = 72,
      93             :   H0 = 73,
      94             :   H1 = 74,
      95             :   H2 = 75,
      96             :   H3 = 76,
      97             :   H4 = 77,
      98             :   H5 = 78,
      99             :   H6 = 79,
     100             :   H7 = 80,
     101             :   H8 = 81,
     102             :   H9 = 82,
     103             :   H10 = 83,
     104             :   H11 = 84,
     105             :   H12 = 85,
     106             :   H13 = 86,
     107             :   H14 = 87,
     108             :   H15 = 88,
     109             :   H16 = 89,
     110             :   H17 = 90,
     111             :   H18 = 91,
     112             :   H19 = 92,
     113             :   H20 = 93,
     114             :   H21 = 94,
     115             :   H22 = 95,
     116             :   H23 = 96,
     117             :   H24 = 97,
     118             :   H25 = 98,
     119             :   H26 = 99,
     120             :   H27 = 100,
     121             :   H28 = 101,
     122             :   H29 = 102,
     123             :   H30 = 103,
     124             :   H31 = 104,
     125             :   P0 = 105,
     126             :   P1 = 106,
     127             :   P2 = 107,
     128             :   P3 = 108,
     129             :   P4 = 109,
     130             :   P5 = 110,
     131             :   P6 = 111,
     132             :   P7 = 112,
     133             :   P8 = 113,
     134             :   P9 = 114,
     135             :   P10 = 115,
     136             :   P11 = 116,
     137             :   P12 = 117,
     138             :   P13 = 118,
     139             :   P14 = 119,
     140             :   P15 = 120,
     141             :   Q0 = 121,
     142             :   Q1 = 122,
     143             :   Q2 = 123,
     144             :   Q3 = 124,
     145             :   Q4 = 125,
     146             :   Q5 = 126,
     147             :   Q6 = 127,
     148             :   Q7 = 128,
     149             :   Q8 = 129,
     150             :   Q9 = 130,
     151             :   Q10 = 131,
     152             :   Q11 = 132,
     153             :   Q12 = 133,
     154             :   Q13 = 134,
     155             :   Q14 = 135,
     156             :   Q15 = 136,
     157             :   Q16 = 137,
     158             :   Q17 = 138,
     159             :   Q18 = 139,
     160             :   Q19 = 140,
     161             :   Q20 = 141,
     162             :   Q21 = 142,
     163             :   Q22 = 143,
     164             :   Q23 = 144,
     165             :   Q24 = 145,
     166             :   Q25 = 146,
     167             :   Q26 = 147,
     168             :   Q27 = 148,
     169             :   Q28 = 149,
     170             :   Q29 = 150,
     171             :   Q30 = 151,
     172             :   Q31 = 152,
     173             :   S0 = 153,
     174             :   S1 = 154,
     175             :   S2 = 155,
     176             :   S3 = 156,
     177             :   S4 = 157,
     178             :   S5 = 158,
     179             :   S6 = 159,
     180             :   S7 = 160,
     181             :   S8 = 161,
     182             :   S9 = 162,
     183             :   S10 = 163,
     184             :   S11 = 164,
     185             :   S12 = 165,
     186             :   S13 = 166,
     187             :   S14 = 167,
     188             :   S15 = 168,
     189             :   S16 = 169,
     190             :   S17 = 170,
     191             :   S18 = 171,
     192             :   S19 = 172,
     193             :   S20 = 173,
     194             :   S21 = 174,
     195             :   S22 = 175,
     196             :   S23 = 176,
     197             :   S24 = 177,
     198             :   S25 = 178,
     199             :   S26 = 179,
     200             :   S27 = 180,
     201             :   S28 = 181,
     202             :   S29 = 182,
     203             :   S30 = 183,
     204             :   S31 = 184,
     205             :   W0 = 185,
     206             :   W1 = 186,
     207             :   W2 = 187,
     208             :   W3 = 188,
     209             :   W4 = 189,
     210             :   W5 = 190,
     211             :   W6 = 191,
     212             :   W7 = 192,
     213             :   W8 = 193,
     214             :   W9 = 194,
     215             :   W10 = 195,
     216             :   W11 = 196,
     217             :   W12 = 197,
     218             :   W13 = 198,
     219             :   W14 = 199,
     220             :   W15 = 200,
     221             :   W16 = 201,
     222             :   W17 = 202,
     223             :   W18 = 203,
     224             :   W19 = 204,
     225             :   W20 = 205,
     226             :   W21 = 206,
     227             :   W22 = 207,
     228             :   W23 = 208,
     229             :   W24 = 209,
     230             :   W25 = 210,
     231             :   W26 = 211,
     232             :   W27 = 212,
     233             :   W28 = 213,
     234             :   W29 = 214,
     235             :   W30 = 215,
     236             :   X0 = 216,
     237             :   X1 = 217,
     238             :   X2 = 218,
     239             :   X3 = 219,
     240             :   X4 = 220,
     241             :   X5 = 221,
     242             :   X6 = 222,
     243             :   X7 = 223,
     244             :   X8 = 224,
     245             :   X9 = 225,
     246             :   X10 = 226,
     247             :   X11 = 227,
     248             :   X12 = 228,
     249             :   X13 = 229,
     250             :   X14 = 230,
     251             :   X15 = 231,
     252             :   X16 = 232,
     253             :   X17 = 233,
     254             :   X18 = 234,
     255             :   X19 = 235,
     256             :   X20 = 236,
     257             :   X21 = 237,
     258             :   X22 = 238,
     259             :   X23 = 239,
     260             :   X24 = 240,
     261             :   X25 = 241,
     262             :   X26 = 242,
     263             :   X27 = 243,
     264             :   X28 = 244,
     265             :   Z0 = 245,
     266             :   Z1 = 246,
     267             :   Z2 = 247,
     268             :   Z3 = 248,
     269             :   Z4 = 249,
     270             :   Z5 = 250,
     271             :   Z6 = 251,
     272             :   Z7 = 252,
     273             :   Z8 = 253,
     274             :   Z9 = 254,
     275             :   Z10 = 255,
     276             :   Z11 = 256,
     277             :   Z12 = 257,
     278             :   Z13 = 258,
     279             :   Z14 = 259,
     280             :   Z15 = 260,
     281             :   Z16 = 261,
     282             :   Z17 = 262,
     283             :   Z18 = 263,
     284             :   Z19 = 264,
     285             :   Z20 = 265,
     286             :   Z21 = 266,
     287             :   Z22 = 267,
     288             :   Z23 = 268,
     289             :   Z24 = 269,
     290             :   Z25 = 270,
     291             :   Z26 = 271,
     292             :   Z27 = 272,
     293             :   Z28 = 273,
     294             :   Z29 = 274,
     295             :   Z30 = 275,
     296             :   Z31 = 276,
     297             :   Z0_HI = 277,
     298             :   Z1_HI = 278,
     299             :   Z2_HI = 279,
     300             :   Z3_HI = 280,
     301             :   Z4_HI = 281,
     302             :   Z5_HI = 282,
     303             :   Z6_HI = 283,
     304             :   Z7_HI = 284,
     305             :   Z8_HI = 285,
     306             :   Z9_HI = 286,
     307             :   Z10_HI = 287,
     308             :   Z11_HI = 288,
     309             :   Z12_HI = 289,
     310             :   Z13_HI = 290,
     311             :   Z14_HI = 291,
     312             :   Z15_HI = 292,
     313             :   Z16_HI = 293,
     314             :   Z17_HI = 294,
     315             :   Z18_HI = 295,
     316             :   Z19_HI = 296,
     317             :   Z20_HI = 297,
     318             :   Z21_HI = 298,
     319             :   Z22_HI = 299,
     320             :   Z23_HI = 300,
     321             :   Z24_HI = 301,
     322             :   Z25_HI = 302,
     323             :   Z26_HI = 303,
     324             :   Z27_HI = 304,
     325             :   Z28_HI = 305,
     326             :   Z29_HI = 306,
     327             :   Z30_HI = 307,
     328             :   Z31_HI = 308,
     329             :   D0_D1 = 309,
     330             :   D1_D2 = 310,
     331             :   D2_D3 = 311,
     332             :   D3_D4 = 312,
     333             :   D4_D5 = 313,
     334             :   D5_D6 = 314,
     335             :   D6_D7 = 315,
     336             :   D7_D8 = 316,
     337             :   D8_D9 = 317,
     338             :   D9_D10 = 318,
     339             :   D10_D11 = 319,
     340             :   D11_D12 = 320,
     341             :   D12_D13 = 321,
     342             :   D13_D14 = 322,
     343             :   D14_D15 = 323,
     344             :   D15_D16 = 324,
     345             :   D16_D17 = 325,
     346             :   D17_D18 = 326,
     347             :   D18_D19 = 327,
     348             :   D19_D20 = 328,
     349             :   D20_D21 = 329,
     350             :   D21_D22 = 330,
     351             :   D22_D23 = 331,
     352             :   D23_D24 = 332,
     353             :   D24_D25 = 333,
     354             :   D25_D26 = 334,
     355             :   D26_D27 = 335,
     356             :   D27_D28 = 336,
     357             :   D28_D29 = 337,
     358             :   D29_D30 = 338,
     359             :   D30_D31 = 339,
     360             :   D31_D0 = 340,
     361             :   D0_D1_D2_D3 = 341,
     362             :   D1_D2_D3_D4 = 342,
     363             :   D2_D3_D4_D5 = 343,
     364             :   D3_D4_D5_D6 = 344,
     365             :   D4_D5_D6_D7 = 345,
     366             :   D5_D6_D7_D8 = 346,
     367             :   D6_D7_D8_D9 = 347,
     368             :   D7_D8_D9_D10 = 348,
     369             :   D8_D9_D10_D11 = 349,
     370             :   D9_D10_D11_D12 = 350,
     371             :   D10_D11_D12_D13 = 351,
     372             :   D11_D12_D13_D14 = 352,
     373             :   D12_D13_D14_D15 = 353,
     374             :   D13_D14_D15_D16 = 354,
     375             :   D14_D15_D16_D17 = 355,
     376             :   D15_D16_D17_D18 = 356,
     377             :   D16_D17_D18_D19 = 357,
     378             :   D17_D18_D19_D20 = 358,
     379             :   D18_D19_D20_D21 = 359,
     380             :   D19_D20_D21_D22 = 360,
     381             :   D20_D21_D22_D23 = 361,
     382             :   D21_D22_D23_D24 = 362,
     383             :   D22_D23_D24_D25 = 363,
     384             :   D23_D24_D25_D26 = 364,
     385             :   D24_D25_D26_D27 = 365,
     386             :   D25_D26_D27_D28 = 366,
     387             :   D26_D27_D28_D29 = 367,
     388             :   D27_D28_D29_D30 = 368,
     389             :   D28_D29_D30_D31 = 369,
     390             :   D29_D30_D31_D0 = 370,
     391             :   D30_D31_D0_D1 = 371,
     392             :   D31_D0_D1_D2 = 372,
     393             :   D0_D1_D2 = 373,
     394             :   D1_D2_D3 = 374,
     395             :   D2_D3_D4 = 375,
     396             :   D3_D4_D5 = 376,
     397             :   D4_D5_D6 = 377,
     398             :   D5_D6_D7 = 378,
     399             :   D6_D7_D8 = 379,
     400             :   D7_D8_D9 = 380,
     401             :   D8_D9_D10 = 381,
     402             :   D9_D10_D11 = 382,
     403             :   D10_D11_D12 = 383,
     404             :   D11_D12_D13 = 384,
     405             :   D12_D13_D14 = 385,
     406             :   D13_D14_D15 = 386,
     407             :   D14_D15_D16 = 387,
     408             :   D15_D16_D17 = 388,
     409             :   D16_D17_D18 = 389,
     410             :   D17_D18_D19 = 390,
     411             :   D18_D19_D20 = 391,
     412             :   D19_D20_D21 = 392,
     413             :   D20_D21_D22 = 393,
     414             :   D21_D22_D23 = 394,
     415             :   D22_D23_D24 = 395,
     416             :   D23_D24_D25 = 396,
     417             :   D24_D25_D26 = 397,
     418             :   D25_D26_D27 = 398,
     419             :   D26_D27_D28 = 399,
     420             :   D27_D28_D29 = 400,
     421             :   D28_D29_D30 = 401,
     422             :   D29_D30_D31 = 402,
     423             :   D30_D31_D0 = 403,
     424             :   D31_D0_D1 = 404,
     425             :   Q0_Q1 = 405,
     426             :   Q1_Q2 = 406,
     427             :   Q2_Q3 = 407,
     428             :   Q3_Q4 = 408,
     429             :   Q4_Q5 = 409,
     430             :   Q5_Q6 = 410,
     431             :   Q6_Q7 = 411,
     432             :   Q7_Q8 = 412,
     433             :   Q8_Q9 = 413,
     434             :   Q9_Q10 = 414,
     435             :   Q10_Q11 = 415,
     436             :   Q11_Q12 = 416,
     437             :   Q12_Q13 = 417,
     438             :   Q13_Q14 = 418,
     439             :   Q14_Q15 = 419,
     440             :   Q15_Q16 = 420,
     441             :   Q16_Q17 = 421,
     442             :   Q17_Q18 = 422,
     443             :   Q18_Q19 = 423,
     444             :   Q19_Q20 = 424,
     445             :   Q20_Q21 = 425,
     446             :   Q21_Q22 = 426,
     447             :   Q22_Q23 = 427,
     448             :   Q23_Q24 = 428,
     449             :   Q24_Q25 = 429,
     450             :   Q25_Q26 = 430,
     451             :   Q26_Q27 = 431,
     452             :   Q27_Q28 = 432,
     453             :   Q28_Q29 = 433,
     454             :   Q29_Q30 = 434,
     455             :   Q30_Q31 = 435,
     456             :   Q31_Q0 = 436,
     457             :   Q0_Q1_Q2_Q3 = 437,
     458             :   Q1_Q2_Q3_Q4 = 438,
     459             :   Q2_Q3_Q4_Q5 = 439,
     460             :   Q3_Q4_Q5_Q6 = 440,
     461             :   Q4_Q5_Q6_Q7 = 441,
     462             :   Q5_Q6_Q7_Q8 = 442,
     463             :   Q6_Q7_Q8_Q9 = 443,
     464             :   Q7_Q8_Q9_Q10 = 444,
     465             :   Q8_Q9_Q10_Q11 = 445,
     466             :   Q9_Q10_Q11_Q12 = 446,
     467             :   Q10_Q11_Q12_Q13 = 447,
     468             :   Q11_Q12_Q13_Q14 = 448,
     469             :   Q12_Q13_Q14_Q15 = 449,
     470             :   Q13_Q14_Q15_Q16 = 450,
     471             :   Q14_Q15_Q16_Q17 = 451,
     472             :   Q15_Q16_Q17_Q18 = 452,
     473             :   Q16_Q17_Q18_Q19 = 453,
     474             :   Q17_Q18_Q19_Q20 = 454,
     475             :   Q18_Q19_Q20_Q21 = 455,
     476             :   Q19_Q20_Q21_Q22 = 456,
     477             :   Q20_Q21_Q22_Q23 = 457,
     478             :   Q21_Q22_Q23_Q24 = 458,
     479             :   Q22_Q23_Q24_Q25 = 459,
     480             :   Q23_Q24_Q25_Q26 = 460,
     481             :   Q24_Q25_Q26_Q27 = 461,
     482             :   Q25_Q26_Q27_Q28 = 462,
     483             :   Q26_Q27_Q28_Q29 = 463,
     484             :   Q27_Q28_Q29_Q30 = 464,
     485             :   Q28_Q29_Q30_Q31 = 465,
     486             :   Q29_Q30_Q31_Q0 = 466,
     487             :   Q30_Q31_Q0_Q1 = 467,
     488             :   Q31_Q0_Q1_Q2 = 468,
     489             :   Q0_Q1_Q2 = 469,
     490             :   Q1_Q2_Q3 = 470,
     491             :   Q2_Q3_Q4 = 471,
     492             :   Q3_Q4_Q5 = 472,
     493             :   Q4_Q5_Q6 = 473,
     494             :   Q5_Q6_Q7 = 474,
     495             :   Q6_Q7_Q8 = 475,
     496             :   Q7_Q8_Q9 = 476,
     497             :   Q8_Q9_Q10 = 477,
     498             :   Q9_Q10_Q11 = 478,
     499             :   Q10_Q11_Q12 = 479,
     500             :   Q11_Q12_Q13 = 480,
     501             :   Q12_Q13_Q14 = 481,
     502             :   Q13_Q14_Q15 = 482,
     503             :   Q14_Q15_Q16 = 483,
     504             :   Q15_Q16_Q17 = 484,
     505             :   Q16_Q17_Q18 = 485,
     506             :   Q17_Q18_Q19 = 486,
     507             :   Q18_Q19_Q20 = 487,
     508             :   Q19_Q20_Q21 = 488,
     509             :   Q20_Q21_Q22 = 489,
     510             :   Q21_Q22_Q23 = 490,
     511             :   Q22_Q23_Q24 = 491,
     512             :   Q23_Q24_Q25 = 492,
     513             :   Q24_Q25_Q26 = 493,
     514             :   Q25_Q26_Q27 = 494,
     515             :   Q26_Q27_Q28 = 495,
     516             :   Q27_Q28_Q29 = 496,
     517             :   Q28_Q29_Q30 = 497,
     518             :   Q29_Q30_Q31 = 498,
     519             :   Q30_Q31_Q0 = 499,
     520             :   Q31_Q0_Q1 = 500,
     521             :   WZR_W0 = 501,
     522             :   W30_WZR = 502,
     523             :   W0_W1 = 503,
     524             :   W1_W2 = 504,
     525             :   W2_W3 = 505,
     526             :   W3_W4 = 506,
     527             :   W4_W5 = 507,
     528             :   W5_W6 = 508,
     529             :   W6_W7 = 509,
     530             :   W7_W8 = 510,
     531             :   W8_W9 = 511,
     532             :   W9_W10 = 512,
     533             :   W10_W11 = 513,
     534             :   W11_W12 = 514,
     535             :   W12_W13 = 515,
     536             :   W13_W14 = 516,
     537             :   W14_W15 = 517,
     538             :   W15_W16 = 518,
     539             :   W16_W17 = 519,
     540             :   W17_W18 = 520,
     541             :   W18_W19 = 521,
     542             :   W19_W20 = 522,
     543             :   W20_W21 = 523,
     544             :   W21_W22 = 524,
     545             :   W22_W23 = 525,
     546             :   W23_W24 = 526,
     547             :   W24_W25 = 527,
     548             :   W25_W26 = 528,
     549             :   W26_W27 = 529,
     550             :   W27_W28 = 530,
     551             :   W28_W29 = 531,
     552             :   W29_W30 = 532,
     553             :   FP_LR = 533,
     554             :   LR_XZR = 534,
     555             :   XZR_X0 = 535,
     556             :   X28_FP = 536,
     557             :   X0_X1 = 537,
     558             :   X1_X2 = 538,
     559             :   X2_X3 = 539,
     560             :   X3_X4 = 540,
     561             :   X4_X5 = 541,
     562             :   X5_X6 = 542,
     563             :   X6_X7 = 543,
     564             :   X7_X8 = 544,
     565             :   X8_X9 = 545,
     566             :   X9_X10 = 546,
     567             :   X10_X11 = 547,
     568             :   X11_X12 = 548,
     569             :   X12_X13 = 549,
     570             :   X13_X14 = 550,
     571             :   X14_X15 = 551,
     572             :   X15_X16 = 552,
     573             :   X16_X17 = 553,
     574             :   X17_X18 = 554,
     575             :   X18_X19 = 555,
     576             :   X19_X20 = 556,
     577             :   X20_X21 = 557,
     578             :   X21_X22 = 558,
     579             :   X22_X23 = 559,
     580             :   X23_X24 = 560,
     581             :   X24_X25 = 561,
     582             :   X25_X26 = 562,
     583             :   X26_X27 = 563,
     584             :   X27_X28 = 564,
     585             :   Z0_Z1 = 565,
     586             :   Z1_Z2 = 566,
     587             :   Z2_Z3 = 567,
     588             :   Z3_Z4 = 568,
     589             :   Z4_Z5 = 569,
     590             :   Z5_Z6 = 570,
     591             :   Z6_Z7 = 571,
     592             :   Z7_Z8 = 572,
     593             :   Z8_Z9 = 573,
     594             :   Z9_Z10 = 574,
     595             :   Z10_Z11 = 575,
     596             :   Z11_Z12 = 576,
     597             :   Z12_Z13 = 577,
     598             :   Z13_Z14 = 578,
     599             :   Z14_Z15 = 579,
     600             :   Z15_Z16 = 580,
     601             :   Z16_Z17 = 581,
     602             :   Z17_Z18 = 582,
     603             :   Z18_Z19 = 583,
     604             :   Z19_Z20 = 584,
     605             :   Z20_Z21 = 585,
     606             :   Z21_Z22 = 586,
     607             :   Z22_Z23 = 587,
     608             :   Z23_Z24 = 588,
     609             :   Z24_Z25 = 589,
     610             :   Z25_Z26 = 590,
     611             :   Z26_Z27 = 591,
     612             :   Z27_Z28 = 592,
     613             :   Z28_Z29 = 593,
     614             :   Z29_Z30 = 594,
     615             :   Z30_Z31 = 595,
     616             :   Z31_Z0 = 596,
     617             :   Z0_Z1_Z2_Z3 = 597,
     618             :   Z1_Z2_Z3_Z4 = 598,
     619             :   Z2_Z3_Z4_Z5 = 599,
     620             :   Z3_Z4_Z5_Z6 = 600,
     621             :   Z4_Z5_Z6_Z7 = 601,
     622             :   Z5_Z6_Z7_Z8 = 602,
     623             :   Z6_Z7_Z8_Z9 = 603,
     624             :   Z7_Z8_Z9_Z10 = 604,
     625             :   Z8_Z9_Z10_Z11 = 605,
     626             :   Z9_Z10_Z11_Z12 = 606,
     627             :   Z10_Z11_Z12_Z13 = 607,
     628             :   Z11_Z12_Z13_Z14 = 608,
     629             :   Z12_Z13_Z14_Z15 = 609,
     630             :   Z13_Z14_Z15_Z16 = 610,
     631             :   Z14_Z15_Z16_Z17 = 611,
     632             :   Z15_Z16_Z17_Z18 = 612,
     633             :   Z16_Z17_Z18_Z19 = 613,
     634             :   Z17_Z18_Z19_Z20 = 614,
     635             :   Z18_Z19_Z20_Z21 = 615,
     636             :   Z19_Z20_Z21_Z22 = 616,
     637             :   Z20_Z21_Z22_Z23 = 617,
     638             :   Z21_Z22_Z23_Z24 = 618,
     639             :   Z22_Z23_Z24_Z25 = 619,
     640             :   Z23_Z24_Z25_Z26 = 620,
     641             :   Z24_Z25_Z26_Z27 = 621,
     642             :   Z25_Z26_Z27_Z28 = 622,
     643             :   Z26_Z27_Z28_Z29 = 623,
     644             :   Z27_Z28_Z29_Z30 = 624,
     645             :   Z28_Z29_Z30_Z31 = 625,
     646             :   Z29_Z30_Z31_Z0 = 626,
     647             :   Z30_Z31_Z0_Z1 = 627,
     648             :   Z31_Z0_Z1_Z2 = 628,
     649             :   Z0_Z1_Z2 = 629,
     650             :   Z1_Z2_Z3 = 630,
     651             :   Z2_Z3_Z4 = 631,
     652             :   Z3_Z4_Z5 = 632,
     653             :   Z4_Z5_Z6 = 633,
     654             :   Z5_Z6_Z7 = 634,
     655             :   Z6_Z7_Z8 = 635,
     656             :   Z7_Z8_Z9 = 636,
     657             :   Z8_Z9_Z10 = 637,
     658             :   Z9_Z10_Z11 = 638,
     659             :   Z10_Z11_Z12 = 639,
     660             :   Z11_Z12_Z13 = 640,
     661             :   Z12_Z13_Z14 = 641,
     662             :   Z13_Z14_Z15 = 642,
     663             :   Z14_Z15_Z16 = 643,
     664             :   Z15_Z16_Z17 = 644,
     665             :   Z16_Z17_Z18 = 645,
     666             :   Z17_Z18_Z19 = 646,
     667             :   Z18_Z19_Z20 = 647,
     668             :   Z19_Z20_Z21 = 648,
     669             :   Z20_Z21_Z22 = 649,
     670             :   Z21_Z22_Z23 = 650,
     671             :   Z22_Z23_Z24 = 651,
     672             :   Z23_Z24_Z25 = 652,
     673             :   Z24_Z25_Z26 = 653,
     674             :   Z25_Z26_Z27 = 654,
     675             :   Z26_Z27_Z28 = 655,
     676             :   Z27_Z28_Z29 = 656,
     677             :   Z28_Z29_Z30 = 657,
     678             :   Z29_Z30_Z31 = 658,
     679             :   Z30_Z31_Z0 = 659,
     680             :   Z31_Z0_Z1 = 660,
     681             :   NUM_TARGET_REGS       // 661
     682             : };
     683             : } // end namespace AArch64
     684             : 
     685             : // Register classes
     686             : 
     687             : namespace AArch64 {
     688             : enum {
     689             :   FPR8RegClassID = 0,
     690             :   FPR16RegClassID = 1,
     691             :   PPRRegClassID = 2,
     692             :   PPR_3bRegClassID = 3,
     693             :   GPR32allRegClassID = 4,
     694             :   FPR32RegClassID = 5,
     695             :   GPR32RegClassID = 6,
     696             :   GPR32spRegClassID = 7,
     697             :   GPR32commonRegClassID = 8,
     698             :   CCRRegClassID = 9,
     699             :   GPR32sponlyRegClassID = 10,
     700             :   WSeqPairsClassRegClassID = 11,
     701             :   WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12,
     702             :   WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
     703             :   WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14,
     704             :   GPR64allRegClassID = 15,
     705             :   FPR64RegClassID = 16,
     706             :   GPR64RegClassID = 17,
     707             :   GPR64spRegClassID = 18,
     708             :   GPR64commonRegClassID = 19,
     709             :   tcGPR64RegClassID = 20,
     710             :   GPR64sponlyRegClassID = 21,
     711             :   DDRegClassID = 22,
     712             :   XSeqPairsClassRegClassID = 23,
     713             :   XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 24,
     714             :   XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 25,
     715             :   XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26,
     716             :   XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 27,
     717             :   XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 28,
     718             :   XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29,
     719             :   FPR128RegClassID = 30,
     720             :   ZPRRegClassID = 31,
     721             :   FPR128_loRegClassID = 32,
     722             :   ZPR_with_zsub_in_FPR128_loRegClassID = 33,
     723             :   DDDRegClassID = 34,
     724             :   DDDDRegClassID = 35,
     725             :   QQRegClassID = 36,
     726             :   ZPR2RegClassID = 37,
     727             :   QQ_with_qsub0_in_FPR128_loRegClassID = 38,
     728             :   QQ_with_qsub1_in_FPR128_loRegClassID = 39,
     729             :   ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID = 40,
     730             :   ZPR2_with_zsub_in_FPR128_loRegClassID = 41,
     731             :   QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 42,
     732             :   ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID = 43,
     733             :   QQQRegClassID = 44,
     734             :   ZPR3RegClassID = 45,
     735             :   QQQ_with_qsub0_in_FPR128_loRegClassID = 46,
     736             :   QQQ_with_qsub1_in_FPR128_loRegClassID = 47,
     737             :   QQQ_with_qsub2_in_FPR128_loRegClassID = 48,
     738             :   ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID = 49,
     739             :   ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID = 50,
     740             :   ZPR3_with_zsub_in_FPR128_loRegClassID = 51,
     741             :   QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 52,
     742             :   QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 53,
     743             :   ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID = 54,
     744             :   ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID = 55,
     745             :   QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 56,
     746             :   ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID = 57,
     747             :   QQQQRegClassID = 58,
     748             :   ZPR4RegClassID = 59,
     749             :   QQQQ_with_qsub0_in_FPR128_loRegClassID = 60,
     750             :   QQQQ_with_qsub1_in_FPR128_loRegClassID = 61,
     751             :   QQQQ_with_qsub2_in_FPR128_loRegClassID = 62,
     752             :   QQQQ_with_qsub3_in_FPR128_loRegClassID = 63,
     753             :   ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID = 64,
     754             :   ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID = 65,
     755             :   ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID = 66,
     756             :   ZPR4_with_zsub_in_FPR128_loRegClassID = 67,
     757             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 68,
     758             :   QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 69,
     759             :   QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 70,
     760             :   ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID = 71,
     761             :   ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID = 72,
     762             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID = 73,
     763             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 74,
     764             :   QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 75,
     765             :   ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID = 76,
     766             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID = 77,
     767             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 78,
     768             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID = 79,
     769             : 
     770             :   };
     771             : } // end namespace AArch64
     772             : 
     773             : 
     774             : // Register alternate name indices
     775             : 
     776             : namespace AArch64 {
     777             : enum {
     778             :   NoRegAltName, // 0
     779             :   vlist1,       // 1
     780             :   vreg, // 2
     781             :   NUM_TARGET_REG_ALT_NAMES = 3
     782             : };
     783             : } // end namespace AArch64
     784             : 
     785             : 
     786             : // Subregister indices
     787             : 
     788             : namespace AArch64 {
     789             : enum {
     790             :   NoSubRegister,
     791             :   bsub, // 1
     792             :   dsub, // 2
     793             :   dsub0,        // 3
     794             :   dsub1,        // 4
     795             :   dsub2,        // 5
     796             :   dsub3,        // 6
     797             :   hsub, // 7
     798             :   qhisub,       // 8
     799             :   qsub, // 9
     800             :   qsub0,        // 10
     801             :   qsub1,        // 11
     802             :   qsub2,        // 12
     803             :   qsub3,        // 13
     804             :   ssub, // 14
     805             :   sub_32,       // 15
     806             :   sube32,       // 16
     807             :   sube64,       // 17
     808             :   subo32,       // 18
     809             :   subo64,       // 19
     810             :   zsub, // 20
     811             :   zsub0,        // 21
     812             :   zsub1,        // 22
     813             :   zsub2,        // 23
     814             :   zsub3,        // 24
     815             :   zsub_hi,      // 25
     816             :   dsub1_then_bsub,      // 26
     817             :   dsub1_then_hsub,      // 27
     818             :   dsub1_then_ssub,      // 28
     819             :   dsub3_then_bsub,      // 29
     820             :   dsub3_then_hsub,      // 30
     821             :   dsub3_then_ssub,      // 31
     822             :   dsub2_then_bsub,      // 32
     823             :   dsub2_then_hsub,      // 33
     824             :   dsub2_then_ssub,      // 34
     825             :   qsub1_then_bsub,      // 35
     826             :   qsub1_then_dsub,      // 36
     827             :   qsub1_then_hsub,      // 37
     828             :   qsub1_then_ssub,      // 38
     829             :   qsub3_then_bsub,      // 39
     830             :   qsub3_then_dsub,      // 40
     831             :   qsub3_then_hsub,      // 41
     832             :   qsub3_then_ssub,      // 42
     833             :   qsub2_then_bsub,      // 43
     834             :   qsub2_then_dsub,      // 44
     835             :   qsub2_then_hsub,      // 45
     836             :   qsub2_then_ssub,      // 46
     837             :   subo64_then_sub_32,   // 47
     838             :   zsub1_then_bsub,      // 48
     839             :   zsub1_then_dsub,      // 49
     840             :   zsub1_then_hsub,      // 50
     841             :   zsub1_then_ssub,      // 51
     842             :   zsub1_then_zsub,      // 52
     843             :   zsub1_then_zsub_hi,   // 53
     844             :   zsub3_then_bsub,      // 54
     845             :   zsub3_then_dsub,      // 55
     846             :   zsub3_then_hsub,      // 56
     847             :   zsub3_then_ssub,      // 57
     848             :   zsub3_then_zsub,      // 58
     849             :   zsub3_then_zsub_hi,   // 59
     850             :   zsub2_then_bsub,      // 60
     851             :   zsub2_then_dsub,      // 61
     852             :   zsub2_then_hsub,      // 62
     853             :   zsub2_then_ssub,      // 63
     854             :   zsub2_then_zsub,      // 64
     855             :   zsub2_then_zsub_hi,   // 65
     856             :   dsub0_dsub1,  // 66
     857             :   dsub0_dsub1_dsub2,    // 67
     858             :   dsub1_dsub2,  // 68
     859             :   dsub1_dsub2_dsub3,    // 69
     860             :   dsub2_dsub3,  // 70
     861             :   dsub_qsub1_then_dsub, // 71
     862             :   dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 72
     863             :   dsub_qsub1_then_dsub_qsub2_then_dsub, // 73
     864             :   qsub0_qsub1,  // 74
     865             :   qsub0_qsub1_qsub2,    // 75
     866             :   qsub1_qsub2,  // 76
     867             :   qsub1_qsub2_qsub3,    // 77
     868             :   qsub2_qsub3,  // 78
     869             :   qsub1_then_dsub_qsub2_then_dsub,      // 79
     870             :   qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,      // 80
     871             :   qsub2_then_dsub_qsub3_then_dsub,      // 81
     872             :   sub_32_subo64_then_sub_32,    // 82
     873             :   dsub_zsub1_then_dsub, // 83
     874             :   zsub_zsub1_then_zsub, // 84
     875             :   dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 85
     876             :   dsub_zsub1_then_dsub_zsub2_then_dsub, // 86
     877             :   zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 87
     878             :   zsub_zsub1_then_zsub_zsub2_then_zsub, // 88
     879             :   zsub0_zsub1,  // 89
     880             :   zsub0_zsub1_zsub2,    // 90
     881             :   zsub1_zsub2,  // 91
     882             :   zsub1_zsub2_zsub3,    // 92
     883             :   zsub2_zsub3,  // 93
     884             :   zsub1_then_dsub_zsub2_then_dsub,      // 94
     885             :   zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,      // 95
     886             :   zsub1_then_zsub_zsub2_then_zsub,      // 96
     887             :   zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,      // 97
     888             :   zsub2_then_dsub_zsub3_then_dsub,      // 98
     889             :   zsub2_then_zsub_zsub3_then_zsub,      // 99
     890             :   NUM_TARGET_SUBREGS
     891             : };
     892             : } // end namespace AArch64
     893             : 
     894             : } // end namespace llvm
     895             : 
     896             : #endif // GET_REGINFO_ENUM
     897             : 
     898             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
     899             : |*                                                                            *|
     900             : |* MC Register Information                                                    *|
     901             : |*                                                                            *|
     902             : |* Automatically generated file, do not edit!                                 *|
     903             : |*                                                                            *|
     904             : \*===----------------------------------------------------------------------===*/
     905             : 
     906             : 
     907             : #ifdef GET_REGINFO_MC_DESC
     908             : #undef GET_REGINFO_MC_DESC
     909             : 
     910             : namespace llvm {
     911             : 
     912             : extern const MCPhysReg AArch64RegDiffLists[] = {
     913             :   /* 0 */ 64945, 1, 1, 1, 74, 1, 1, 1, 0,
     914             :   /* 9 */ 65105, 1, 1, 1, 0,
     915             :   /* 14 */ 65201, 1, 1, 1, 0,
     916             :   /* 19 */ 6, 29, 1, 1, 0,
     917             :   /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0,
     918             :   /* 33 */ 65324, 499, 30, 1, 1, 0,
     919             :   /* 39 */ 64913, 1, 1, 75, 1, 1, 0,
     920             :   /* 46 */ 65073, 1, 1, 0,
     921             :   /* 50 */ 65169, 1, 1, 0,
     922             :   /* 54 */ 6, 1, 29, 1, 0,
     923             :   /* 59 */ 6, 1, 29, 1, 46, 1, 29, 1, 0,
     924             :   /* 68 */ 6, 30, 1, 0,
     925             :   /* 72 */ 6, 30, 1, 46, 30, 1, 0,
     926             :   /* 79 */ 1, 493, 1, 32, 1, 0,
     927             :   /* 85 */ 31, 286, 1, 33, 1, 0,
     928             :   /* 91 */ 64977, 1, 76, 1, 0,
     929             :   /* 96 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
     930             :   /* 111 */ 320, 1, 0,
     931             :   /* 114 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
     932             :   /* 129 */ 526, 1, 0,
     933             :   /* 132 */ 530, 1, 0,
     934             :   /* 135 */ 65053, 1, 0,
     935             :   /* 138 */ 65087, 1, 0,
     936             :   /* 141 */ 65137, 1, 0,
     937             :   /* 144 */ 65218, 1, 0,
     938             :   /* 147 */ 65233, 1, 0,
     939             :   /* 150 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     940             :   /* 183 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     941             :   /* 203 */ 65504, 319, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     942             :   /* 214 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     943             :   /* 247 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     944             :   /* 267 */ 65504, 320, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     945             :   /* 278 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 128, 63, 65503, 34, 65503, 1, 0,
     946             :   /* 296 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     947             :   /* 329 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     948             :   /* 349 */ 65504, 319, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     949             :   /* 360 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 97, 64, 65504, 63, 65503, 1, 0,
     950             :   /* 378 */ 65503, 1, 128, 65503, 1, 192, 65503, 1, 0,
     951             :   /* 387 */ 31, 285, 2, 32, 2, 0,
     952             :   /* 393 */ 319, 2, 0,
     953             :   /* 396 */ 65324, 529, 1, 1, 3, 0,
     954             :   /* 402 */ 2, 3, 0,
     955             :   /* 405 */ 531, 3, 0,
     956             :   /* 408 */ 65004, 3, 0,
     957             :   /* 411 */ 4, 0,
     958             :   /* 413 */ 5, 0,
     959             :   /* 415 */ 31, 286, 1, 5, 28, 0,
     960             :   /* 421 */ 292, 28, 0,
     961             :   /* 424 */ 6, 1, 1, 29, 0,
     962             :   /* 429 */ 6, 1, 1, 29, 46, 1, 1, 29, 0,
     963             :   /* 438 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     964             :   /* 471 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     965             :   /* 491 */ 65504, 319, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     966             :   /* 502 */ 6, 1, 30, 0,
     967             :   /* 506 */ 6, 1, 30, 46, 1, 30, 0,
     968             :   /* 513 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 98, 63, 1, 65503, 1, 30, 0,
     969             :   /* 531 */ 6, 31, 0,
     970             :   /* 534 */ 6, 31, 46, 31, 0,
     971             :   /* 539 */ 65504, 31, 97, 65504, 31, 161, 65504, 31, 0,
     972             :   /* 548 */ 32, 0,
     973             :   /* 550 */ 34, 0,
     974             :   /* 552 */ 5, 49, 0,
     975             :   /* 555 */ 63936, 49, 0,
     976             :   /* 558 */ 65297, 77, 0,
     977             :   /* 561 */ 1, 81, 0,
     978             :   /* 564 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0,
     979             :   /* 581 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0,
     980             :   /* 598 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 96, 1, 65280, 96, 0,
     981             :   /* 628 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 1, 65280, 96, 0,
     982             :   /* 658 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 65505, 65280, 96, 0,
     983             :   /* 688 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65441, 65311, 64, 32, 64, 65345, 96, 0,
     984             :   /* 734 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65441, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
     985             :   /* 780 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
     986             :   /* 826 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
     987             :   /* 872 */ 96, 160, 0,
     988             :   /* 875 */ 65042, 178, 0,
     989             :   /* 878 */ 212, 0,
     990             :   /* 880 */ 65412, 65456, 112, 65456, 65472, 268, 0,
     991             :   /* 887 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
     992             :   /* 899 */ 65009, 65535, 209, 65505, 316, 0,
     993             :   /* 905 */ 65005, 212, 65325, 212, 317, 0,
     994             :   /* 911 */ 65244, 65505, 65325, 212, 317, 0,
     995             :   /* 917 */ 65215, 65505, 32, 65505, 317, 0,
     996             :   /* 923 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
     997             :   /* 935 */ 65005, 212, 65329, 65535, 495, 0,
     998             :   /* 941 */ 65323, 0,
     999             :   /* 943 */ 65249, 65328, 0,
    1000             :   /* 946 */ 65342, 0,
    1001             :   /* 948 */ 65374, 0,
    1002             :   /* 950 */ 65389, 0,
    1003             :   /* 952 */ 65405, 0,
    1004             :   /* 954 */ 65421, 0,
    1005             :   /* 956 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
    1006             :   /* 977 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
    1007             :   /* 998 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
    1008             :   /* 1019 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
    1009             :   /* 1051 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
    1010             :   /* 1073 */ 65469, 0,
    1011             :   /* 1075 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
    1012             :   /* 1084 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
    1013             :   /* 1093 */ 65456, 112, 65456, 65472, 0,
    1014             :   /* 1098 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
    1015             :   /* 1130 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
    1016             :   /* 1162 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
    1017             :   /* 1194 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
    1018             :   /* 1216 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
    1019             :   /* 1238 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
    1020             :   /* 1260 */ 65501, 0,
    1021             :   /* 1262 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
    1022             :   /* 1277 */ 65533, 0,
    1023             :   /* 1279 */ 65535, 0,
    1024             : };
    1025             : 
    1026             : extern const LaneBitmask AArch64LaneMaskLists[] = {
    1027             :   /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
    1028             :   /* 2 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1029             :   /* 5 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1030             :   /* 10 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1031             :   /* 14 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1032             :   /* 17 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1033             :   /* 22 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1034             :   /* 26 */ LaneBitmask(0x00002000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
    1035             :   /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
    1036             :   /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
    1037             :   /* 35 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
    1038             :   /* 38 */ LaneBitmask(0x00004000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
    1039             :   /* 43 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
    1040             :   /* 52 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
    1041             :   /* 59 */ LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
    1042             :   /* 64 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
    1043             :   /* 68 */ LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask::getAll(),
    1044             :   /* 73 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask::getAll(),
    1045             :   /* 78 */ LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
    1046             :   /* 83 */ LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
    1047             :   /* 87 */ LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask::getAll(),
    1048             :   /* 92 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask::getAll(),
    1049             :   /* 97 */ LaneBitmask(0x00000008), LaneBitmask(0x00002000), LaneBitmask::getAll(),
    1050             :   /* 100 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
    1051             :   /* 105 */ LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
    1052             :   /* 114 */ LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
    1053             :   /* 121 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
    1054             :   /* 130 */ LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
    1055             :   /* 139 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
    1056             : };
    1057             : 
    1058             : extern const uint16_t AArch64SubRegIdxLists[] = {
    1059             :   /* 0 */ 2, 14, 7, 1, 0,
    1060             :   /* 5 */ 15, 0,
    1061             :   /* 7 */ 16, 18, 0,
    1062             :   /* 10 */ 20, 2, 14, 7, 1, 25, 0,
    1063             :   /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0,
    1064             :   /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0,
    1065             :   /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0,
    1066             :   /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0,
    1067             :   /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0,
    1068             :   /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0,
    1069             :   /* 128 */ 17, 15, 19, 47, 82, 0,
    1070             :   /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0,
    1071             :   /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0,
    1072             :   /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
    1073             : };
    1074             : 
    1075             : extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
    1076             :   { 65535, 65535 },
    1077             :   { 0, 8 },     // bsub
    1078             :   { 0, 32 },    // dsub
    1079             :   { 0, 64 },    // dsub0
    1080             :   { 0, 64 },    // dsub1
    1081             :   { 0, 64 },    // dsub2
    1082             :   { 0, 64 },    // dsub3
    1083             :   { 0, 16 },    // hsub
    1084             :   { 0, 64 },    // qhisub
    1085             :   { 0, 64 },    // qsub
    1086             :   { 0, 128 },   // qsub0
    1087             :   { 0, 128 },   // qsub1
    1088             :   { 0, 128 },   // qsub2
    1089             :   { 0, 128 },   // qsub3
    1090             :   { 0, 32 },    // ssub
    1091             :   { 0, 32 },    // sub_32
    1092             :   { 0, 32 },    // sube32
    1093             :   { 0, 64 },    // sube64
    1094             :   { 0, 32 },    // subo32
    1095             :   { 0, 64 },    // subo64
    1096             :   { 0, 128 },   // zsub
    1097             :   { 65535, 128 },       // zsub0
    1098             :   { 65535, 128 },       // zsub1
    1099             :   { 65535, 128 },       // zsub2
    1100             :   { 65535, 128 },       // zsub3
    1101             :   { 0, 128 },   // zsub_hi
    1102             :   { 0, 8 },     // dsub1_then_bsub
    1103             :   { 0, 16 },    // dsub1_then_hsub
    1104             :   { 0, 32 },    // dsub1_then_ssub
    1105             :   { 0, 8 },     // dsub3_then_bsub
    1106             :   { 0, 16 },    // dsub3_then_hsub
    1107             :   { 0, 32 },    // dsub3_then_ssub
    1108             :   { 0, 8 },     // dsub2_then_bsub
    1109             :   { 0, 16 },    // dsub2_then_hsub
    1110             :   { 0, 32 },    // dsub2_then_ssub
    1111             :   { 0, 8 },     // qsub1_then_bsub
    1112             :   { 0, 32 },    // qsub1_then_dsub
    1113             :   { 0, 16 },    // qsub1_then_hsub
    1114             :   { 0, 32 },    // qsub1_then_ssub
    1115             :   { 0, 8 },     // qsub3_then_bsub
    1116             :   { 0, 32 },    // qsub3_then_dsub
    1117             :   { 0, 16 },    // qsub3_then_hsub
    1118             :   { 0, 32 },    // qsub3_then_ssub
    1119             :   { 0, 8 },     // qsub2_then_bsub
    1120             :   { 0, 32 },    // qsub2_then_dsub
    1121             :   { 0, 16 },    // qsub2_then_hsub
    1122             :   { 0, 32 },    // qsub2_then_ssub
    1123             :   { 0, 32 },    // subo64_then_sub_32
    1124             :   { 65535, 65535 },     // zsub1_then_bsub
    1125             :   { 65535, 65535 },     // zsub1_then_dsub
    1126             :   { 65535, 65535 },     // zsub1_then_hsub
    1127             :   { 65535, 65535 },     // zsub1_then_ssub
    1128             :   { 65535, 65535 },     // zsub1_then_zsub
    1129             :   { 65535, 65535 },     // zsub1_then_zsub_hi
    1130             :   { 65535, 65535 },     // zsub3_then_bsub
    1131             :   { 65535, 65535 },     // zsub3_then_dsub
    1132             :   { 65535, 65535 },     // zsub3_then_hsub
    1133             :   { 65535, 65535 },     // zsub3_then_ssub
    1134             :   { 65535, 65535 },     // zsub3_then_zsub
    1135             :   { 65535, 65535 },     // zsub3_then_zsub_hi
    1136             :   { 65535, 65535 },     // zsub2_then_bsub
    1137             :   { 65535, 65535 },     // zsub2_then_dsub
    1138             :   { 65535, 65535 },     // zsub2_then_hsub
    1139             :   { 65535, 65535 },     // zsub2_then_ssub
    1140             :   { 65535, 65535 },     // zsub2_then_zsub
    1141             :   { 65535, 65535 },     // zsub2_then_zsub_hi
    1142             :   { 65535, 128 },       // dsub0_dsub1
    1143             :   { 65535, 192 },       // dsub0_dsub1_dsub2
    1144             :   { 65535, 128 },       // dsub1_dsub2
    1145             :   { 65535, 192 },       // dsub1_dsub2_dsub3
    1146             :   { 65535, 128 },       // dsub2_dsub3
    1147             :   { 65535, 64 },        // dsub_qsub1_then_dsub
    1148             :   { 65535, 128 },       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    1149             :   { 65535, 96 },        // dsub_qsub1_then_dsub_qsub2_then_dsub
    1150             :   { 65535, 256 },       // qsub0_qsub1
    1151             :   { 65535, 384 },       // qsub0_qsub1_qsub2
    1152             :   { 65535, 256 },       // qsub1_qsub2
    1153             :   { 65535, 384 },       // qsub1_qsub2_qsub3
    1154             :   { 65535, 256 },       // qsub2_qsub3
    1155             :   { 65535, 64 },        // qsub1_then_dsub_qsub2_then_dsub
    1156             :   { 65535, 96 },        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    1157             :   { 65535, 64 },        // qsub2_then_dsub_qsub3_then_dsub
    1158             :   { 65535, 64 },        // sub_32_subo64_then_sub_32
    1159             :   { 65535, 31 },        // dsub_zsub1_then_dsub
    1160             :   { 65535, 127 },       // zsub_zsub1_then_zsub
    1161             :   { 65535, 29 },        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    1162             :   { 65535, 30 },        // dsub_zsub1_then_dsub_zsub2_then_dsub
    1163             :   { 65535, 125 },       // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    1164             :   { 65535, 126 },       // zsub_zsub1_then_zsub_zsub2_then_zsub
    1165             :   { 65535, 256 },       // zsub0_zsub1
    1166             :   { 65535, 384 },       // zsub0_zsub1_zsub2
    1167             :   { 65535, 256 },       // zsub1_zsub2
    1168             :   { 65535, 384 },       // zsub1_zsub2_zsub3
    1169             :   { 65535, 256 },       // zsub2_zsub3
    1170             :   { 65535, 65534 },     // zsub1_then_dsub_zsub2_then_dsub
    1171             :   { 65535, 65533 },     // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    1172             :   { 65535, 65534 },     // zsub1_then_zsub_zsub2_then_zsub
    1173             :   { 65535, 65533 },     // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    1174             :   { 65535, 65534 },     // zsub2_then_dsub_zsub3_then_dsub
    1175             :   { 65535, 65534 },     // zsub2_then_zsub_zsub3_then_zsub
    1176             : };
    1177             : 
    1178             : extern const char AArch64RegStrings[] = {
    1179             :   /* 0 */ 'B', '1', '0', 0,
    1180             :   /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
    1181             :   /* 17 */ 'H', '1', '0', 0,
    1182             :   /* 21 */ 'P', '1', '0', 0,
    1183             :   /* 25 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
    1184             :   /* 38 */ 'S', '1', '0', 0,
    1185             :   /* 42 */ 'W', '9', '_', 'W', '1', '0', 0,
    1186             :   /* 49 */ 'X', '9', '_', 'X', '1', '0', 0,
    1187             :   /* 56 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0,
    1188             :   /* 69 */ 'B', '2', '0', 0,
    1189             :   /* 73 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
    1190             :   /* 89 */ 'H', '2', '0', 0,
    1191             :   /* 93 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
    1192             :   /* 109 */ 'S', '2', '0', 0,
    1193             :   /* 113 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
    1194             :   /* 121 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
    1195             :   /* 129 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0,
    1196             :   /* 145 */ 'B', '3', '0', 0,
    1197             :   /* 149 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
    1198             :   /* 165 */ 'H', '3', '0', 0,
    1199             :   /* 169 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
    1200             :   /* 185 */ 'S', '3', '0', 0,
    1201             :   /* 189 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
    1202             :   /* 197 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0,
    1203             :   /* 213 */ 'B', '0', 0,
    1204             :   /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
    1205             :   /* 231 */ 'H', '0', 0,
    1206             :   /* 234 */ 'P', '0', 0,
    1207             :   /* 237 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
    1208             :   /* 252 */ 'S', '0', 0,
    1209             :   /* 255 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
    1210             :   /* 262 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
    1211             :   /* 269 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0,
    1212             :   /* 284 */ 'B', '1', '1', 0,
    1213             :   /* 288 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
    1214             :   /* 302 */ 'H', '1', '1', 0,
    1215             :   /* 306 */ 'P', '1', '1', 0,
    1216             :   /* 310 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
    1217             :   /* 324 */ 'S', '1', '1', 0,
    1218             :   /* 328 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
    1219             :   /* 336 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
    1220             :   /* 344 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0,
    1221             :   /* 358 */ 'B', '2', '1', 0,
    1222             :   /* 362 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
    1223             :   /* 378 */ 'H', '2', '1', 0,
    1224             :   /* 382 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
    1225             :   /* 398 */ 'S', '2', '1', 0,
    1226             :   /* 402 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
    1227             :   /* 410 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
    1228             :   /* 418 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0,
    1229             :   /* 434 */ 'B', '3', '1', 0,
    1230             :   /* 438 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
    1231             :   /* 454 */ 'H', '3', '1', 0,
    1232             :   /* 458 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
    1233             :   /* 474 */ 'S', '3', '1', 0,
    1234             :   /* 478 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0,
    1235             :   /* 494 */ 'B', '1', 0,
    1236             :   /* 497 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
    1237             :   /* 511 */ 'H', '1', 0,
    1238             :   /* 514 */ 'P', '1', 0,
    1239             :   /* 517 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
    1240             :   /* 531 */ 'S', '1', 0,
    1241             :   /* 534 */ 'W', '0', '_', 'W', '1', 0,
    1242             :   /* 540 */ 'X', '0', '_', 'X', '1', 0,
    1243             :   /* 546 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0,
    1244             :   /* 560 */ 'B', '1', '2', 0,
    1245             :   /* 564 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
    1246             :   /* 579 */ 'H', '1', '2', 0,
    1247             :   /* 583 */ 'P', '1', '2', 0,
    1248             :   /* 587 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
    1249             :   /* 602 */ 'S', '1', '2', 0,
    1250             :   /* 606 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
    1251             :   /* 614 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
    1252             :   /* 622 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0,
    1253             :   /* 637 */ 'B', '2', '2', 0,
    1254             :   /* 641 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
    1255             :   /* 657 */ 'H', '2', '2', 0,
    1256             :   /* 661 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
    1257             :   /* 677 */ 'S', '2', '2', 0,
    1258             :   /* 681 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
    1259             :   /* 689 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
    1260             :   /* 697 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0,
    1261             :   /* 713 */ 'B', '2', 0,
    1262             :   /* 716 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
    1263             :   /* 729 */ 'H', '2', 0,
    1264             :   /* 732 */ 'P', '2', 0,
    1265             :   /* 735 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
    1266             :   /* 748 */ 'S', '2', 0,
    1267             :   /* 751 */ 'W', '1', '_', 'W', '2', 0,
    1268             :   /* 757 */ 'X', '1', '_', 'X', '2', 0,
    1269             :   /* 763 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0,
    1270             :   /* 776 */ 'B', '1', '3', 0,
    1271             :   /* 780 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
    1272             :   /* 796 */ 'H', '1', '3', 0,
    1273             :   /* 800 */ 'P', '1', '3', 0,
    1274             :   /* 804 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
    1275             :   /* 820 */ 'S', '1', '3', 0,
    1276             :   /* 824 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
    1277             :   /* 832 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
    1278             :   /* 840 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0,
    1279             :   /* 856 */ 'B', '2', '3', 0,
    1280             :   /* 860 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
    1281             :   /* 876 */ 'H', '2', '3', 0,
    1282             :   /* 880 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
    1283             :   /* 896 */ 'S', '2', '3', 0,
    1284             :   /* 900 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
    1285             :   /* 908 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
    1286             :   /* 916 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0,
    1287             :   /* 932 */ 'B', '3', 0,
    1288             :   /* 935 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
    1289             :   /* 947 */ 'H', '3', 0,
    1290             :   /* 950 */ 'P', '3', 0,
    1291             :   /* 953 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
    1292             :   /* 965 */ 'S', '3', 0,
    1293             :   /* 968 */ 'W', '2', '_', 'W', '3', 0,
    1294             :   /* 974 */ 'X', '2', '_', 'X', '3', 0,
    1295             :   /* 980 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0,
    1296             :   /* 992 */ 'B', '1', '4', 0,
    1297             :   /* 996 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
    1298             :   /* 1012 */ 'H', '1', '4', 0,
    1299             :   /* 1016 */ 'P', '1', '4', 0,
    1300             :   /* 1020 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
    1301             :   /* 1036 */ 'S', '1', '4', 0,
    1302             :   /* 1040 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
    1303             :   /* 1048 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
    1304             :   /* 1056 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0,
    1305             :   /* 1072 */ 'B', '2', '4', 0,
    1306             :   /* 1076 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
    1307             :   /* 1092 */ 'H', '2', '4', 0,
    1308             :   /* 1096 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
    1309             :   /* 1112 */ 'S', '2', '4', 0,
    1310             :   /* 1116 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
    1311             :   /* 1124 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
    1312             :   /* 1132 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0,
    1313             :   /* 1148 */ 'B', '4', 0,
    1314             :   /* 1151 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
    1315             :   /* 1163 */ 'H', '4', 0,
    1316             :   /* 1166 */ 'P', '4', 0,
    1317             :   /* 1169 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
    1318             :   /* 1181 */ 'S', '4', 0,
    1319             :   /* 1184 */ 'W', '3', '_', 'W', '4', 0,
    1320             :   /* 1190 */ 'X', '3', '_', 'X', '4', 0,
    1321             :   /* 1196 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0,
    1322             :   /* 1208 */ 'B', '1', '5', 0,
    1323             :   /* 1212 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
    1324             :   /* 1228 */ 'H', '1', '5', 0,
    1325             :   /* 1232 */ 'P', '1', '5', 0,
    1326             :   /* 1236 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
    1327             :   /* 1252 */ 'S', '1', '5', 0,
    1328             :   /* 1256 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
    1329             :   /* 1264 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
    1330             :   /* 1272 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0,
    1331             :   /* 1288 */ 'B', '2', '5', 0,
    1332             :   /* 1292 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
    1333             :   /* 1308 */ 'H', '2', '5', 0,
    1334             :   /* 1312 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
    1335             :   /* 1328 */ 'S', '2', '5', 0,
    1336             :   /* 1332 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
    1337             :   /* 1340 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
    1338             :   /* 1348 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0,
    1339             :   /* 1364 */ 'B', '5', 0,
    1340             :   /* 1367 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
    1341             :   /* 1379 */ 'H', '5', 0,
    1342             :   /* 1382 */ 'P', '5', 0,
    1343             :   /* 1385 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
    1344             :   /* 1397 */ 'S', '5', 0,
    1345             :   /* 1400 */ 'W', '4', '_', 'W', '5', 0,
    1346             :   /* 1406 */ 'X', '4', '_', 'X', '5', 0,
    1347             :   /* 1412 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0,
    1348             :   /* 1424 */ 'B', '1', '6', 0,
    1349             :   /* 1428 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
    1350             :   /* 1444 */ 'H', '1', '6', 0,
    1351             :   /* 1448 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
    1352             :   /* 1464 */ 'S', '1', '6', 0,
    1353             :   /* 1468 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
    1354             :   /* 1476 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
    1355             :   /* 1484 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0,
    1356             :   /* 1500 */ 'B', '2', '6', 0,
    1357             :   /* 1504 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
    1358             :   /* 1520 */ 'H', '2', '6', 0,
    1359             :   /* 1524 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
    1360             :   /* 1540 */ 'S', '2', '6', 0,
    1361             :   /* 1544 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
    1362             :   /* 1552 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
    1363             :   /* 1560 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0,
    1364             :   /* 1576 */ 'B', '6', 0,
    1365             :   /* 1579 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
    1366             :   /* 1591 */ 'H', '6', 0,
    1367             :   /* 1594 */ 'P', '6', 0,
    1368             :   /* 1597 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
    1369             :   /* 1609 */ 'S', '6', 0,
    1370             :   /* 1612 */ 'W', '5', '_', 'W', '6', 0,
    1371             :   /* 1618 */ 'X', '5', '_', 'X', '6', 0,
    1372             :   /* 1624 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0,
    1373             :   /* 1636 */ 'B', '1', '7', 0,
    1374             :   /* 1640 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
    1375             :   /* 1656 */ 'H', '1', '7', 0,
    1376             :   /* 1660 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
    1377             :   /* 1676 */ 'S', '1', '7', 0,
    1378             :   /* 1680 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
    1379             :   /* 1688 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
    1380             :   /* 1696 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0,
    1381             :   /* 1712 */ 'B', '2', '7', 0,
    1382             :   /* 1716 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
    1383             :   /* 1732 */ 'H', '2', '7', 0,
    1384             :   /* 1736 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
    1385             :   /* 1752 */ 'S', '2', '7', 0,
    1386             :   /* 1756 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
    1387             :   /* 1764 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
    1388             :   /* 1772 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0,
    1389             :   /* 1788 */ 'B', '7', 0,
    1390             :   /* 1791 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
    1391             :   /* 1803 */ 'H', '7', 0,
    1392             :   /* 1806 */ 'P', '7', 0,
    1393             :   /* 1809 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
    1394             :   /* 1821 */ 'S', '7', 0,
    1395             :   /* 1824 */ 'W', '6', '_', 'W', '7', 0,
    1396             :   /* 1830 */ 'X', '6', '_', 'X', '7', 0,
    1397             :   /* 1836 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0,
    1398             :   /* 1848 */ 'B', '1', '8', 0,
    1399             :   /* 1852 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
    1400             :   /* 1868 */ 'H', '1', '8', 0,
    1401             :   /* 1872 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
    1402             :   /* 1888 */ 'S', '1', '8', 0,
    1403             :   /* 1892 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
    1404             :   /* 1900 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
    1405             :   /* 1908 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0,
    1406             :   /* 1924 */ 'B', '2', '8', 0,
    1407             :   /* 1928 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
    1408             :   /* 1944 */ 'H', '2', '8', 0,
    1409             :   /* 1948 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
    1410             :   /* 1964 */ 'S', '2', '8', 0,
    1411             :   /* 1968 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
    1412             :   /* 1976 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
    1413             :   /* 1984 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0,
    1414             :   /* 2000 */ 'B', '8', 0,
    1415             :   /* 2003 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
    1416             :   /* 2015 */ 'H', '8', 0,
    1417             :   /* 2018 */ 'P', '8', 0,
    1418             :   /* 2021 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
    1419             :   /* 2033 */ 'S', '8', 0,
    1420             :   /* 2036 */ 'W', '7', '_', 'W', '8', 0,
    1421             :   /* 2042 */ 'X', '7', '_', 'X', '8', 0,
    1422             :   /* 2048 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0,
    1423             :   /* 2060 */ 'B', '1', '9', 0,
    1424             :   /* 2064 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
    1425             :   /* 2080 */ 'H', '1', '9', 0,
    1426             :   /* 2084 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
    1427             :   /* 2100 */ 'S', '1', '9', 0,
    1428             :   /* 2104 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
    1429             :   /* 2112 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
    1430             :   /* 2120 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0,
    1431             :   /* 2136 */ 'B', '2', '9', 0,
    1432             :   /* 2140 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
    1433             :   /* 2156 */ 'H', '2', '9', 0,
    1434             :   /* 2160 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
    1435             :   /* 2176 */ 'S', '2', '9', 0,
    1436             :   /* 2180 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
    1437             :   /* 2188 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0,
    1438             :   /* 2204 */ 'B', '9', 0,
    1439             :   /* 2207 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
    1440             :   /* 2219 */ 'H', '9', 0,
    1441             :   /* 2222 */ 'P', '9', 0,
    1442             :   /* 2225 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
    1443             :   /* 2237 */ 'S', '9', 0,
    1444             :   /* 2240 */ 'W', '8', '_', 'W', '9', 0,
    1445             :   /* 2246 */ 'X', '8', '_', 'X', '9', 0,
    1446             :   /* 2252 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0,
    1447             :   /* 2264 */ 'Z', '1', '0', '_', 'H', 'I', 0,
    1448             :   /* 2271 */ 'Z', '2', '0', '_', 'H', 'I', 0,
    1449             :   /* 2278 */ 'Z', '3', '0', '_', 'H', 'I', 0,
    1450             :   /* 2285 */ 'Z', '0', '_', 'H', 'I', 0,
    1451             :   /* 2291 */ 'Z', '1', '1', '_', 'H', 'I', 0,
    1452             :   /* 2298 */ 'Z', '2', '1', '_', 'H', 'I', 0,
    1453             :   /* 2305 */ 'Z', '3', '1', '_', 'H', 'I', 0,
    1454             :   /* 2312 */ 'Z', '1', '_', 'H', 'I', 0,
    1455             :   /* 2318 */ 'Z', '1', '2', '_', 'H', 'I', 0,
    1456             :   /* 2325 */ 'Z', '2', '2', '_', 'H', 'I', 0,
    1457             :   /* 2332 */ 'Z', '2', '_', 'H', 'I', 0,
    1458             :   /* 2338 */ 'Z', '1', '3', '_', 'H', 'I', 0,
    1459             :   /* 2345 */ 'Z', '2', '3', '_', 'H', 'I', 0,
    1460             :   /* 2352 */ 'Z', '3', '_', 'H', 'I', 0,
    1461             :   /* 2358 */ 'Z', '1', '4', '_', 'H', 'I', 0,
    1462             :   /* 2365 */ 'Z', '2', '4', '_', 'H', 'I', 0,
    1463             :   /* 2372 */ 'Z', '4', '_', 'H', 'I', 0,
    1464             :   /* 2378 */ 'Z', '1', '5', '_', 'H', 'I', 0,
    1465             :   /* 2385 */ 'Z', '2', '5', '_', 'H', 'I', 0,
    1466             :   /* 2392 */ 'Z', '5', '_', 'H', 'I', 0,
    1467             :   /* 2398 */ 'Z', '1', '6', '_', 'H', 'I', 0,
    1468             :   /* 2405 */ 'Z', '2', '6', '_', 'H', 'I', 0,
    1469             :   /* 2412 */ 'Z', '6', '_', 'H', 'I', 0,
    1470             :   /* 2418 */ 'Z', '1', '7', '_', 'H', 'I', 0,
    1471             :   /* 2425 */ 'Z', '2', '7', '_', 'H', 'I', 0,
    1472             :   /* 2432 */ 'Z', '7', '_', 'H', 'I', 0,
    1473             :   /* 2438 */ 'Z', '1', '8', '_', 'H', 'I', 0,
    1474             :   /* 2445 */ 'Z', '2', '8', '_', 'H', 'I', 0,
    1475             :   /* 2452 */ 'Z', '8', '_', 'H', 'I', 0,
    1476             :   /* 2458 */ 'Z', '1', '9', '_', 'H', 'I', 0,
    1477             :   /* 2465 */ 'Z', '2', '9', '_', 'H', 'I', 0,
    1478             :   /* 2472 */ 'Z', '9', '_', 'H', 'I', 0,
    1479             :   /* 2478 */ 'X', '2', '8', '_', 'F', 'P', 0,
    1480             :   /* 2485 */ 'W', 'S', 'P', 0,
    1481             :   /* 2489 */ 'F', 'F', 'R', 0,
    1482             :   /* 2493 */ 'F', 'P', '_', 'L', 'R', 0,
    1483             :   /* 2499 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
    1484             :   /* 2507 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
    1485             :   /* 2514 */ 'N', 'Z', 'C', 'V', 0,
    1486             : };
    1487             : 
    1488             : extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
    1489             :   { 3, 0, 0, 0, 0, 0 },
    1490             :   { 2489, 8, 8, 4, 20465, 0 },
    1491             :   { 2482, 878, 405, 5, 20465, 27 },
    1492             :   { 2496, 878, 132, 5, 20465, 27 },
    1493             :   { 2514, 8, 8, 4, 20465, 0 },
    1494             :   { 2486, 7, 8, 5, 6576, 27 },
    1495             :   { 2485, 8, 1279, 4, 6576, 0 },
    1496             :   { 2503, 8, 79, 4, 6608, 0 },
    1497             :   { 2510, 1279, 129, 5, 6608, 27 },
    1498             :   { 213, 8, 214, 4, 20433, 0 },
    1499             :   { 494, 8, 296, 4, 20433, 0 },
    1500             :   { 713, 8, 438, 4, 20433, 0 },
    1501             :   { 932, 8, 150, 4, 20433, 0 },
    1502             :   { 1148, 8, 150, 4, 20433, 0 },
    1503             :   { 1364, 8, 150, 4, 20433, 0 },
    1504             :   { 1576, 8, 150, 4, 20433, 0 },
    1505             :   { 1788, 8, 150, 4, 20433, 0 },
    1506             :   { 2000, 8, 150, 4, 20433, 0 },
    1507             :   { 2204, 8, 150, 4, 20433, 0 },
    1508             :   { 0, 8, 150, 4, 20433, 0 },
    1509             :   { 284, 8, 150, 4, 20433, 0 },
    1510             :   { 560, 8, 150, 4, 20433, 0 },
    1511             :   { 776, 8, 150, 4, 20433, 0 },
    1512             :   { 992, 8, 150, 4, 20433, 0 },
    1513             :   { 1208, 8, 150, 4, 20433, 0 },
    1514             :   { 1424, 8, 150, 4, 20433, 0 },
    1515             :   { 1636, 8, 150, 4, 20433, 0 },
    1516             :   { 1848, 8, 150, 4, 20433, 0 },
    1517             :   { 2060, 8, 150, 4, 20433, 0 },
    1518             :   { 69, 8, 150, 4, 20433, 0 },
    1519             :   { 358, 8, 150, 4, 20433, 0 },
    1520             :   { 637, 8, 150, 4, 20433, 0 },
    1521             :   { 856, 8, 150, 4, 20433, 0 },
    1522             :   { 1072, 8, 150, 4, 20433, 0 },
    1523             :   { 1288, 8, 150, 4, 20433, 0 },
    1524             :   { 1500, 8, 150, 4, 20433, 0 },
    1525             :   { 1712, 8, 150, 4, 20433, 0 },
    1526             :   { 1924, 8, 150, 4, 20433, 0 },
    1527             :   { 2136, 8, 150, 4, 20433, 0 },
    1528             :   { 145, 8, 150, 4, 20433, 0 },
    1529             :   { 434, 8, 150, 4, 20433, 0 },
    1530             :   { 228, 1080, 217, 1, 20161, 3 },
    1531             :   { 508, 1080, 299, 1, 20161, 3 },
    1532             :   { 726, 1080, 441, 1, 20161, 3 },
    1533             :   { 944, 1080, 153, 1, 20161, 3 },
    1534             :   { 1160, 1080, 153, 1, 20161, 3 },
    1535             :   { 1376, 1080, 153, 1, 20161, 3 },
    1536             :   { 1588, 1080, 153, 1, 20161, 3 },
    1537             :   { 1800, 1080, 153, 1, 20161, 3 },
    1538             :   { 2012, 1080, 153, 1, 20161, 3 },
    1539             :   { 2216, 1080, 153, 1, 20161, 3 },
    1540             :   { 13, 1080, 153, 1, 20161, 3 },
    1541             :   { 298, 1080, 153, 1, 20161, 3 },
    1542             :   { 575, 1080, 153, 1, 20161, 3 },
    1543             :   { 792, 1080, 153, 1, 20161, 3 },
    1544             :   { 1008, 1080, 153, 1, 20161, 3 },
    1545             :   { 1224, 1080, 153, 1, 20161, 3 },
    1546             :   { 1440, 1080, 153, 1, 20161, 3 },
    1547             :   { 1652, 1080, 153, 1, 20161, 3 },
    1548             :   { 1864, 1080, 153, 1, 20161, 3 },
    1549             :   { 2076, 1080, 153, 1, 20161, 3 },
    1550             :   { 85, 1080, 153, 1, 20161, 3 },
    1551             :   { 374, 1080, 153, 1, 20161, 3 },
    1552             :   { 653, 1080, 153, 1, 20161, 3 },
    1553             :   { 872, 1080, 153, 1, 20161, 3 },
    1554             :   { 1088, 1080, 153, 1, 20161, 3 },
    1555             :   { 1304, 1080, 153, 1, 20161, 3 },
    1556             :   { 1516, 1080, 153, 1, 20161, 3 },
    1557             :   { 1728, 1080, 153, 1, 20161, 3 },
    1558             :   { 1940, 1080, 153, 1, 20161, 3 },
    1559             :   { 2152, 1080, 153, 1, 20161, 3 },
    1560             :   { 161, 1080, 153, 1, 20161, 3 },
    1561             :   { 450, 1080, 153, 1, 20161, 3 },
    1562             :   { 231, 1082, 215, 3, 17169, 3 },
    1563             :   { 511, 1082, 297, 3, 17169, 3 },
    1564             :   { 729, 1082, 439, 3, 17169, 3 },
    1565             :   { 947, 1082, 151, 3, 17169, 3 },
    1566             :   { 1163, 1082, 151, 3, 17169, 3 },
    1567             :   { 1379, 1082, 151, 3, 17169, 3 },
    1568             :   { 1591, 1082, 151, 3, 17169, 3 },
    1569             :   { 1803, 1082, 151, 3, 17169, 3 },
    1570             :   { 2015, 1082, 151, 3, 17169, 3 },
    1571             :   { 2219, 1082, 151, 3, 17169, 3 },
    1572             :   { 17, 1082, 151, 3, 17169, 3 },
    1573             :   { 302, 1082, 151, 3, 17169, 3 },
    1574             :   { 579, 1082, 151, 3, 17169, 3 },
    1575             :   { 796, 1082, 151, 3, 17169, 3 },
    1576             :   { 1012, 1082, 151, 3, 17169, 3 },
    1577             :   { 1228, 1082, 151, 3, 17169, 3 },
    1578             :   { 1444, 1082, 151, 3, 17169, 3 },
    1579             :   { 1656, 1082, 151, 3, 17169, 3 },
    1580             :   { 1868, 1082, 151, 3, 17169, 3 },
    1581             :   { 2080, 1082, 151, 3, 17169, 3 },
    1582             :   { 89, 1082, 151, 3, 17169, 3 },
    1583             :   { 378, 1082, 151, 3, 17169, 3 },
    1584             :   { 657, 1082, 151, 3, 17169, 3 },
    1585             :   { 876, 1082, 151, 3, 17169, 3 },
    1586             :   { 1092, 1082, 151, 3, 17169, 3 },
    1587             :   { 1308, 1082, 151, 3, 17169, 3 },
    1588             :   { 1520, 1082, 151, 3, 17169, 3 },
    1589             :   { 1732, 1082, 151, 3, 17169, 3 },
    1590             :   { 1944, 1082, 151, 3, 17169, 3 },
    1591             :   { 2156, 1082, 151, 3, 17169, 3 },
    1592             :   { 165, 1082, 151, 3, 17169, 3 },
    1593             :   { 454, 1082, 151, 3, 17169, 3 },
    1594             :   { 234, 8, 8, 4, 17169, 0 },
    1595             :   { 514, 8, 8, 4, 17169, 0 },
    1596             :   { 732, 8, 8, 4, 17169, 0 },
    1597             :   { 950, 8, 8, 4, 17169, 0 },
    1598             :   { 1166, 8, 8, 4, 17169, 0 },
    1599             :   { 1382, 8, 8, 4, 17169, 0 },
    1600             :   { 1594, 8, 8, 4, 17169, 0 },
    1601             :   { 1806, 8, 8, 4, 17169, 0 },
    1602             :   { 2018, 8, 8, 4, 17169, 0 },
    1603             :   { 2222, 8, 8, 4, 17169, 0 },
    1604             :   { 21, 8, 8, 4, 17169, 0 },
    1605             :   { 306, 8, 8, 4, 17169, 0 },
    1606             :   { 583, 8, 8, 4, 17169, 0 },
    1607             :   { 800, 8, 8, 4, 17169, 0 },
    1608             :   { 1016, 8, 8, 4, 17169, 0 },
    1609             :   { 1232, 8, 8, 4, 17169, 0 },
    1610             :   { 249, 1093, 247, 0, 15265, 3 },
    1611             :   { 528, 1093, 329, 0, 15265, 3 },
    1612             :   { 745, 1093, 471, 0, 15265, 3 },
    1613             :   { 962, 1093, 183, 0, 15265, 3 },
    1614             :   { 1178, 1093, 183, 0, 15265, 3 },
    1615             :   { 1394, 1093, 183, 0, 15265, 3 },
    1616             :   { 1606, 1093, 183, 0, 15265, 3 },
    1617             :   { 1818, 1093, 183, 0, 15265, 3 },
    1618             :   { 2030, 1093, 183, 0, 15265, 3 },
    1619             :   { 2234, 1093, 183, 0, 15265, 3 },
    1620             :   { 34, 1093, 183, 0, 15265, 3 },
    1621             :   { 320, 1093, 183, 0, 15265, 3 },
    1622             :   { 598, 1093, 183, 0, 15265, 3 },
    1623             :   { 816, 1093, 183, 0, 15265, 3 },
    1624             :   { 1032, 1093, 183, 0, 15265, 3 },
    1625             :   { 1248, 1093, 183, 0, 15265, 3 },
    1626             :   { 1460, 1093, 183, 0, 15265, 3 },
    1627             :   { 1672, 1093, 183, 0, 15265, 3 },
    1628             :   { 1884, 1093, 183, 0, 15265, 3 },
    1629             :   { 2096, 1093, 183, 0, 15265, 3 },
    1630             :   { 105, 1093, 183, 0, 15265, 3 },
    1631             :   { 394, 1093, 183, 0, 15265, 3 },
    1632             :   { 673, 1093, 183, 0, 15265, 3 },
    1633             :   { 892, 1093, 183, 0, 15265, 3 },
    1634             :   { 1108, 1093, 183, 0, 15265, 3 },
    1635             :   { 1324, 1093, 183, 0, 15265, 3 },
    1636             :   { 1536, 1093, 183, 0, 15265, 3 },
    1637             :   { 1748, 1093, 183, 0, 15265, 3 },
    1638             :   { 1960, 1093, 183, 0, 15265, 3 },
    1639             :   { 2172, 1093, 183, 0, 15265, 3 },
    1640             :   { 181, 1093, 183, 0, 15265, 3 },
    1641             :   { 470, 1093, 183, 0, 15265, 3 },
    1642             :   { 252, 1081, 216, 2, 15201, 3 },
    1643             :   { 531, 1081, 298, 2, 15201, 3 },
    1644             :   { 748, 1081, 440, 2, 15201, 3 },
    1645             :   { 965, 1081, 152, 2, 15201, 3 },
    1646             :   { 1181, 1081, 152, 2, 15201, 3 },
    1647             :   { 1397, 1081, 152, 2, 15201, 3 },
    1648             :   { 1609, 1081, 152, 2, 15201, 3 },
    1649             :   { 1821, 1081, 152, 2, 15201, 3 },
    1650             :   { 2033, 1081, 152, 2, 15201, 3 },
    1651             :   { 2237, 1081, 152, 2, 15201, 3 },
    1652             :   { 38, 1081, 152, 2, 15201, 3 },
    1653             :   { 324, 1081, 152, 2, 15201, 3 },
    1654             :   { 602, 1081, 152, 2, 15201, 3 },
    1655             :   { 820, 1081, 152, 2, 15201, 3 },
    1656             :   { 1036, 1081, 152, 2, 15201, 3 },
    1657             :   { 1252, 1081, 152, 2, 15201, 3 },
    1658             :   { 1464, 1081, 152, 2, 15201, 3 },
    1659             :   { 1676, 1081, 152, 2, 15201, 3 },
    1660             :   { 1888, 1081, 152, 2, 15201, 3 },
    1661             :   { 2100, 1081, 152, 2, 15201, 3 },
    1662             :   { 109, 1081, 152, 2, 15201, 3 },
    1663             :   { 398, 1081, 152, 2, 15201, 3 },
    1664             :   { 677, 1081, 152, 2, 15201, 3 },
    1665             :   { 896, 1081, 152, 2, 15201, 3 },
    1666             :   { 1112, 1081, 152, 2, 15201, 3 },
    1667             :   { 1328, 1081, 152, 2, 15201, 3 },
    1668             :   { 1540, 1081, 152, 2, 15201, 3 },
    1669             :   { 1752, 1081, 152, 2, 15201, 3 },
    1670             :   { 1964, 1081, 152, 2, 15201, 3 },
    1671             :   { 2176, 1081, 152, 2, 15201, 3 },
    1672             :   { 185, 1081, 152, 2, 15201, 3 },
    1673             :   { 474, 1081, 152, 2, 15201, 3 },
    1674             :   { 259, 8, 387, 4, 15233, 0 },
    1675             :   { 537, 8, 85, 4, 15233, 0 },
    1676             :   { 754, 8, 85, 4, 15233, 0 },
    1677             :   { 971, 8, 85, 4, 15233, 0 },
    1678             :   { 1187, 8, 85, 4, 15233, 0 },
    1679             :   { 1403, 8, 85, 4, 15233, 0 },
    1680             :   { 1615, 8, 85, 4, 15233, 0 },
    1681             :   { 1827, 8, 85, 4, 15233, 0 },
    1682             :   { 2039, 8, 85, 4, 15233, 0 },
    1683             :   { 2243, 8, 85, 4, 15233, 0 },
    1684             :   { 45, 8, 85, 4, 15233, 0 },
    1685             :   { 332, 8, 85, 4, 15233, 0 },
    1686             :   { 610, 8, 85, 4, 15233, 0 },
    1687             :   { 828, 8, 85, 4, 15233, 0 },
    1688             :   { 1044, 8, 85, 4, 15233, 0 },
    1689             :   { 1260, 8, 85, 4, 15233, 0 },
    1690             :   { 1472, 8, 85, 4, 15233, 0 },
    1691             :   { 1684, 8, 85, 4, 15233, 0 },
    1692             :   { 1896, 8, 85, 4, 15233, 0 },
    1693             :   { 2108, 8, 85, 4, 15233, 0 },
    1694             :   { 117, 8, 85, 4, 15233, 0 },
    1695             :   { 406, 8, 85, 4, 15233, 0 },
    1696             :   { 685, 8, 85, 4, 15233, 0 },
    1697             :   { 904, 8, 85, 4, 15233, 0 },
    1698             :   { 1120, 8, 85, 4, 15233, 0 },
    1699             :   { 1336, 8, 85, 4, 15233, 0 },
    1700             :   { 1548, 8, 85, 4, 15233, 0 },
    1701             :   { 1760, 8, 85, 4, 15233, 0 },
    1702             :   { 1972, 8, 415, 4, 15233, 0 },
    1703             :   { 2184, 8, 396, 4, 15057, 0 },
    1704             :   { 193, 8, 33, 4, 15057, 0 },
    1705             :   { 266, 1275, 393, 5, 15169, 27 },
    1706             :   { 543, 1275, 111, 5, 15169, 27 },
    1707             :   { 760, 1275, 111, 5, 15169, 27 },
    1708             :   { 977, 1275, 111, 5, 15169, 27 },
    1709             :   { 1193, 1275, 111, 5, 15169, 27 },
    1710             :   { 1409, 1275, 111, 5, 15169, 27 },
    1711             :   { 1621, 1275, 111, 5, 15169, 27 },
    1712             :   { 1833, 1275, 111, 5, 15169, 27 },
    1713             :   { 2045, 1275, 111, 5, 15169, 27 },
    1714             :   { 2249, 1275, 111, 5, 15169, 27 },
    1715             :   { 52, 1275, 111, 5, 15169, 27 },
    1716             :   { 340, 1275, 111, 5, 15169, 27 },
    1717             :   { 618, 1275, 111, 5, 15169, 27 },
    1718             :   { 836, 1275, 111, 5, 15169, 27 },
    1719             :   { 1052, 1275, 111, 5, 15169, 27 },
    1720             :   { 1268, 1275, 111, 5, 15169, 27 },
    1721             :   { 1480, 1275, 111, 5, 15169, 27 },
    1722             :   { 1692, 1275, 111, 5, 15169, 27 },
    1723             :   { 1904, 1275, 111, 5, 15169, 27 },
    1724             :   { 2116, 1275, 111, 5, 15169, 27 },
    1725             :   { 125, 1275, 111, 5, 15169, 27 },
    1726             :   { 414, 1275, 111, 5, 15169, 27 },
    1727             :   { 693, 1275, 111, 5, 15169, 27 },
    1728             :   { 912, 1275, 111, 5, 15169, 27 },
    1729             :   { 1128, 1275, 111, 5, 15169, 27 },
    1730             :   { 1344, 1275, 111, 5, 15169, 27 },
    1731             :   { 1556, 1275, 111, 5, 15169, 27 },
    1732             :   { 1768, 1275, 111, 5, 15169, 27 },
    1733             :   { 1980, 1275, 421, 5, 15169, 27 },
    1734             :   { 281, 880, 268, 10, 8929, 35 },
    1735             :   { 557, 880, 350, 10, 8929, 35 },
    1736             :   { 773, 880, 492, 10, 8929, 35 },
    1737             :   { 989, 880, 204, 10, 8929, 35 },
    1738             :   { 1205, 880, 204, 10, 8929, 35 },
    1739             :   { 1421, 880, 204, 10, 8929, 35 },
    1740             :   { 1633, 880, 204, 10, 8929, 35 },
    1741             :   { 1845, 880, 204, 10, 8929, 35 },
    1742             :   { 2057, 880, 204, 10, 8929, 35 },
    1743             :   { 2261, 880, 204, 10, 8929, 35 },
    1744             :   { 65, 880, 204, 10, 8929, 35 },
    1745             :   { 354, 880, 204, 10, 8929, 35 },
    1746             :   { 633, 880, 204, 10, 8929, 35 },
    1747             :   { 852, 880, 204, 10, 8929, 35 },
    1748             :   { 1068, 880, 204, 10, 8929, 35 },
    1749             :   { 1284, 880, 204, 10, 8929, 35 },
    1750             :   { 1496, 880, 204, 10, 8929, 35 },
    1751             :   { 1708, 880, 204, 10, 8929, 35 },
    1752             :   { 1920, 880, 204, 10, 8929, 35 },
    1753             :   { 2132, 880, 204, 10, 8929, 35 },
    1754             :   { 141, 880, 204, 10, 8929, 35 },
    1755             :   { 430, 880, 204, 10, 8929, 35 },
    1756             :   { 709, 880, 204, 10, 8929, 35 },
    1757             :   { 928, 880, 204, 10, 8929, 35 },
    1758             :   { 1144, 880, 204, 10, 8929, 35 },
    1759             :   { 1360, 880, 204, 10, 8929, 35 },
    1760             :   { 1572, 880, 204, 10, 8929, 35 },
    1761             :   { 1784, 880, 204, 10, 8929, 35 },
    1762             :   { 1996, 880, 204, 10, 8929, 35 },
    1763             :   { 2200, 880, 204, 10, 8929, 35 },
    1764             :   { 209, 880, 204, 10, 8929, 35 },
    1765             :   { 490, 880, 204, 10, 8929, 35 },
    1766             :   { 2285, 8, 267, 4, 15137, 0 },
    1767             :   { 2312, 8, 349, 4, 15137, 0 },
    1768             :   { 2332, 8, 491, 4, 15137, 0 },
    1769             :   { 2352, 8, 203, 4, 15137, 0 },
    1770             :   { 2372, 8, 203, 4, 15137, 0 },
    1771             :   { 2392, 8, 203, 4, 15137, 0 },
    1772             :   { 2412, 8, 203, 4, 15137, 0 },
    1773             :   { 2432, 8, 203, 4, 15137, 0 },
    1774             :   { 2452, 8, 203, 4, 15137, 0 },
    1775             :   { 2472, 8, 203, 4, 15137, 0 },
    1776             :   { 2264, 8, 203, 4, 15137, 0 },
    1777             :   { 2291, 8, 203, 4, 15137, 0 },
    1778             :   { 2318, 8, 203, 4, 15137, 0 },
    1779             :   { 2338, 8, 203, 4, 15137, 0 },
    1780             :   { 2358, 8, 203, 4, 15137, 0 },
    1781             :   { 2378, 8, 203, 4, 15137, 0 },
    1782             :   { 2398, 8, 203, 4, 15137, 0 },
    1783             :   { 2418, 8, 203, 4, 15137, 0 },
    1784             :   { 2438, 8, 203, 4, 15137, 0 },
    1785             :   { 2458, 8, 203, 4, 15137, 0 },
    1786             :   { 2271, 8, 203, 4, 15137, 0 },
    1787             :   { 2298, 8, 203, 4, 15137, 0 },
    1788             :   { 2325, 8, 203, 4, 15137, 0 },
    1789             :   { 2345, 8, 203, 4, 15137, 0 },
    1790             :   { 2365, 8, 203, 4, 15137, 0 },
    1791             :   { 2385, 8, 203, 4, 15137, 0 },
    1792             :   { 2405, 8, 203, 4, 15137, 0 },
    1793             :   { 2425, 8, 203, 4, 15137, 0 },
    1794             :   { 2445, 8, 203, 4, 15137, 0 },
    1795             :   { 2465, 8, 203, 4, 15137, 0 },
    1796             :   { 2278, 8, 203, 4, 15137, 0 },
    1797             :   { 2305, 8, 203, 4, 15137, 0 },
    1798             :   { 505, 1084, 360, 17, 2353, 61 },
    1799             :   { 723, 1084, 513, 17, 2353, 61 },
    1800             :   { 941, 1084, 278, 17, 2353, 61 },
    1801             :   { 1157, 1084, 278, 17, 2353, 61 },
    1802             :   { 1373, 1084, 278, 17, 2353, 61 },
    1803             :   { 1585, 1084, 278, 17, 2353, 61 },
    1804             :   { 1797, 1084, 278, 17, 2353, 61 },
    1805             :   { 2009, 1084, 278, 17, 2353, 61 },
    1806             :   { 2213, 1084, 278, 17, 2353, 61 },
    1807             :   { 10, 1084, 278, 17, 2353, 61 },
    1808             :   { 294, 1084, 278, 17, 2353, 61 },
    1809             :   { 571, 1084, 278, 17, 2353, 61 },
    1810             :   { 788, 1084, 278, 17, 2353, 61 },
    1811             :   { 1004, 1084, 278, 17, 2353, 61 },
    1812             :   { 1220, 1084, 278, 17, 2353, 61 },
    1813             :   { 1436, 1084, 278, 17, 2353, 61 },
    1814             :   { 1648, 1084, 278, 17, 2353, 61 },
    1815             :   { 1860, 1084, 278, 17, 2353, 61 },
    1816             :   { 2072, 1084, 278, 17, 2353, 61 },
    1817             :   { 81, 1084, 278, 17, 2353, 61 },
    1818             :   { 370, 1084, 278, 17, 2353, 61 },
    1819             :   { 649, 1084, 278, 17, 2353, 61 },
    1820             :   { 868, 1084, 278, 17, 2353, 61 },
    1821             :   { 1084, 1084, 278, 17, 2353, 61 },
    1822             :   { 1300, 1084, 278, 17, 2353, 61 },
    1823             :   { 1512, 1084, 278, 17, 2353, 61 },
    1824             :   { 1724, 1084, 278, 17, 2353, 61 },
    1825             :   { 1936, 1084, 278, 17, 2353, 61 },
    1826             :   { 2148, 1084, 278, 17, 2353, 61 },
    1827             :   { 157, 1084, 278, 17, 2353, 61 },
    1828             :   { 446, 1084, 278, 17, 2353, 61 },
    1829             :   { 224, 1075, 278, 17, 8496, 2 },
    1830             :   { 935, 1216, 872, 41, 225, 68 },
    1831             :   { 1151, 1216, 872, 41, 225, 68 },
    1832             :   { 1367, 1216, 872, 41, 225, 68 },
    1833             :   { 1579, 1216, 872, 41, 225, 68 },
    1834             :   { 1791, 1216, 872, 41, 225, 68 },
    1835             :   { 2003, 1216, 872, 41, 225, 68 },
    1836             :   { 2207, 1216, 872, 41, 225, 68 },
    1837             :   { 4, 1216, 872, 41, 225, 68 },
    1838             :   { 288, 1216, 872, 41, 225, 68 },
    1839             :   { 564, 1216, 872, 41, 225, 68 },
    1840             :   { 780, 1216, 872, 41, 225, 68 },
    1841             :   { 996, 1216, 872, 41, 225, 68 },
    1842             :   { 1212, 1216, 872, 41, 225, 68 },
    1843             :   { 1428, 1216, 872, 41, 225, 68 },
    1844             :   { 1640, 1216, 872, 41, 225, 68 },
    1845             :   { 1852, 1216, 872, 41, 225, 68 },
    1846             :   { 2064, 1216, 872, 41, 225, 68 },
    1847             :   { 73, 1216, 872, 41, 225, 68 },
    1848             :   { 362, 1216, 872, 41, 225, 68 },
    1849             :   { 641, 1216, 872, 41, 225, 68 },
    1850             :   { 860, 1216, 872, 41, 225, 68 },
    1851             :   { 1076, 1216, 872, 41, 225, 68 },
    1852             :   { 1292, 1216, 872, 41, 225, 68 },
    1853             :   { 1504, 1216, 872, 41, 225, 68 },
    1854             :   { 1716, 1216, 872, 41, 225, 68 },
    1855             :   { 1928, 1216, 872, 41, 225, 68 },
    1856             :   { 2140, 1216, 872, 41, 225, 68 },
    1857             :   { 149, 1216, 872, 41, 225, 68 },
    1858             :   { 438, 1216, 872, 41, 225, 68 },
    1859             :   { 216, 1238, 872, 41, 304, 73 },
    1860             :   { 497, 1051, 872, 41, 864, 59 },
    1861             :   { 716, 1194, 872, 41, 6784, 5 },
    1862             :   { 720, 96, 539, 26, 801, 74 },
    1863             :   { 938, 96, 378, 26, 801, 74 },
    1864             :   { 1154, 96, 378, 26, 801, 74 },
    1865             :   { 1370, 96, 378, 26, 801, 74 },
    1866             :   { 1582, 96, 378, 26, 801, 74 },
    1867             :   { 1794, 96, 378, 26, 801, 74 },
    1868             :   { 2006, 96, 378, 26, 801, 74 },
    1869             :   { 2210, 96, 378, 26, 801, 74 },
    1870             :   { 7, 96, 378, 26, 801, 74 },
    1871             :   { 291, 96, 378, 26, 801, 74 },
    1872             :   { 567, 96, 378, 26, 801, 74 },
    1873             :   { 784, 96, 378, 26, 801, 74 },
    1874             :   { 1000, 96, 378, 26, 801, 74 },
    1875             :   { 1216, 96, 378, 26, 801, 74 },
    1876             :   { 1432, 96, 378, 26, 801, 74 },
    1877             :   { 1644, 96, 378, 26, 801, 74 },
    1878             :   { 1856, 96, 378, 26, 801, 74 },
    1879             :   { 2068, 96, 378, 26, 801, 74 },
    1880             :   { 77, 96, 378, 26, 801, 74 },
    1881             :   { 366, 96, 378, 26, 801, 74 },
    1882             :   { 645, 96, 378, 26, 801, 74 },
    1883             :   { 864, 96, 378, 26, 801, 74 },
    1884             :   { 1080, 96, 378, 26, 801, 74 },
    1885             :   { 1296, 96, 378, 26, 801, 74 },
    1886             :   { 1508, 96, 378, 26, 801, 74 },
    1887             :   { 1720, 96, 378, 26, 801, 74 },
    1888             :   { 1932, 96, 378, 26, 801, 74 },
    1889             :   { 2144, 96, 378, 26, 801, 74 },
    1890             :   { 153, 96, 378, 26, 801, 74 },
    1891             :   { 442, 96, 378, 26, 801, 74 },
    1892             :   { 220, 114, 378, 26, 1088, 64 },
    1893             :   { 501, 1262, 378, 26, 8032, 10 },
    1894             :   { 525, 887, 366, 63, 2257, 80 },
    1895             :   { 742, 887, 519, 63, 2257, 80 },
    1896             :   { 959, 887, 284, 63, 2257, 80 },
    1897             :   { 1175, 887, 284, 63, 2257, 80 },
    1898             :   { 1391, 887, 284, 63, 2257, 80 },
    1899             :   { 1603, 887, 284, 63, 2257, 80 },
    1900             :   { 1815, 887, 284, 63, 2257, 80 },
    1901             :   { 2027, 887, 284, 63, 2257, 80 },
    1902             :   { 2231, 887, 284, 63, 2257, 80 },
    1903             :   { 31, 887, 284, 63, 2257, 80 },
    1904             :   { 316, 887, 284, 63, 2257, 80 },
    1905             :   { 594, 887, 284, 63, 2257, 80 },
    1906             :   { 812, 887, 284, 63, 2257, 80 },
    1907             :   { 1028, 887, 284, 63, 2257, 80 },
    1908             :   { 1244, 887, 284, 63, 2257, 80 },
    1909             :   { 1456, 887, 284, 63, 2257, 80 },
    1910             :   { 1668, 887, 284, 63, 2257, 80 },
    1911             :   { 1880, 887, 284, 63, 2257, 80 },
    1912             :   { 2092, 887, 284, 63, 2257, 80 },
    1913             :   { 101, 887, 284, 63, 2257, 80 },
    1914             :   { 390, 887, 284, 63, 2257, 80 },
    1915             :   { 669, 887, 284, 63, 2257, 80 },
    1916             :   { 888, 887, 284, 63, 2257, 80 },
    1917             :   { 1104, 887, 284, 63, 2257, 80 },
    1918             :   { 1320, 887, 284, 63, 2257, 80 },
    1919             :   { 1532, 887, 284, 63, 2257, 80 },
    1920             :   { 1744, 887, 284, 63, 2257, 80 },
    1921             :   { 1956, 887, 284, 63, 2257, 80 },
    1922             :   { 2168, 887, 284, 63, 2257, 80 },
    1923             :   { 177, 887, 284, 63, 2257, 80 },
    1924             :   { 466, 887, 284, 63, 2257, 80 },
    1925             :   { 245, 923, 284, 63, 8496, 14 },
    1926             :   { 953, 1130, 873, 96, 145, 87 },
    1927             :   { 1169, 1130, 873, 96, 145, 87 },
    1928             :   { 1385, 1130, 873, 96, 145, 87 },
    1929             :   { 1597, 1130, 873, 96, 145, 87 },
    1930             :   { 1809, 1130, 873, 96, 145, 87 },
    1931             :   { 2021, 1130, 873, 96, 145, 87 },
    1932             :   { 2225, 1130, 873, 96, 145, 87 },
    1933             :   { 25, 1130, 873, 96, 145, 87 },
    1934             :   { 310, 1130, 873, 96, 145, 87 },
    1935             :   { 587, 1130, 873, 96, 145, 87 },
    1936             :   { 804, 1130, 873, 96, 145, 87 },
    1937             :   { 1020, 1130, 873, 96, 145, 87 },
    1938             :   { 1236, 1130, 873, 96, 145, 87 },
    1939             :   { 1448, 1130, 873, 96, 145, 87 },
    1940             :   { 1660, 1130, 873, 96, 145, 87 },
    1941             :   { 1872, 1130, 873, 96, 145, 87 },
    1942             :   { 2084, 1130, 873, 96, 145, 87 },
    1943             :   { 93, 1130, 873, 96, 145, 87 },
    1944             :   { 382, 1130, 873, 96, 145, 87 },
    1945             :   { 661, 1130, 873, 96, 145, 87 },
    1946             :   { 880, 1130, 873, 96, 145, 87 },
    1947             :   { 1096, 1130, 873, 96, 145, 87 },
    1948             :   { 1312, 1130, 873, 96, 145, 87 },
    1949             :   { 1524, 1130, 873, 96, 145, 87 },
    1950             :   { 1736, 1130, 873, 96, 145, 87 },
    1951             :   { 1948, 1130, 873, 96, 145, 87 },
    1952             :   { 2160, 1130, 873, 96, 145, 87 },
    1953             :   { 169, 1130, 873, 96, 145, 87 },
    1954             :   { 458, 1130, 873, 96, 145, 87 },
    1955             :   { 237, 1162, 873, 96, 304, 92 },
    1956             :   { 517, 1019, 873, 96, 864, 78 },
    1957             :   { 735, 1098, 873, 96, 6784, 17 },
    1958             :   { 739, 956, 542, 75, 737, 93 },
    1959             :   { 956, 956, 381, 75, 737, 93 },
    1960             :   { 1172, 956, 381, 75, 737, 93 },
    1961             :   { 1388, 956, 381, 75, 737, 93 },
    1962             :   { 1600, 956, 381, 75, 737, 93 },
    1963             :   { 1812, 956, 381, 75, 737, 93 },
    1964             :   { 2024, 956, 381, 75, 737, 93 },
    1965             :   { 2228, 956, 381, 75, 737, 93 },
    1966             :   { 28, 956, 381, 75, 737, 93 },
    1967             :   { 313, 956, 381, 75, 737, 93 },
    1968             :   { 590, 956, 381, 75, 737, 93 },
    1969             :   { 808, 956, 381, 75, 737, 93 },
    1970             :   { 1024, 956, 381, 75, 737, 93 },
    1971             :   { 1240, 956, 381, 75, 737, 93 },
    1972             :   { 1452, 956, 381, 75, 737, 93 },
    1973             :   { 1664, 956, 381, 75, 737, 93 },
    1974             :   { 1876, 956, 381, 75, 737, 93 },
    1975             :   { 2088, 956, 381, 75, 737, 93 },
    1976             :   { 97, 956, 381, 75, 737, 93 },
    1977             :   { 386, 956, 381, 75, 737, 93 },
    1978             :   { 665, 956, 381, 75, 737, 93 },
    1979             :   { 884, 956, 381, 75, 737, 93 },
    1980             :   { 1100, 956, 381, 75, 737, 93 },
    1981             :   { 1316, 956, 381, 75, 737, 93 },
    1982             :   { 1528, 956, 381, 75, 737, 93 },
    1983             :   { 1740, 956, 381, 75, 737, 93 },
    1984             :   { 1952, 956, 381, 75, 737, 93 },
    1985             :   { 2164, 956, 381, 75, 737, 93 },
    1986             :   { 173, 956, 381, 75, 737, 93 },
    1987             :   { 462, 956, 381, 75, 737, 93 },
    1988             :   { 241, 977, 381, 75, 1088, 83 },
    1989             :   { 521, 998, 381, 75, 8032, 22 },
    1990             :   { 255, 875, 550, 7, 8832, 32 },
    1991             :   { 2499, 943, 548, 7, 6432, 32 },
    1992             :   { 534, 144, 550, 7, 2209, 32 },
    1993             :   { 751, 144, 550, 7, 2209, 32 },
    1994             :   { 968, 144, 550, 7, 2209, 32 },
    1995             :   { 1184, 144, 550, 7, 2209, 32 },
    1996             :   { 1400, 144, 550, 7, 2209, 32 },
    1997             :   { 1612, 144, 550, 7, 2209, 32 },
    1998             :   { 1824, 144, 550, 7, 2209, 32 },
    1999             :   { 2036, 144, 550, 7, 2209, 32 },
    2000             :   { 2240, 144, 550, 7, 2209, 32 },
    2001             :   { 42, 144, 550, 7, 2209, 32 },
    2002             :   { 328, 144, 550, 7, 2209, 32 },
    2003             :   { 606, 144, 550, 7, 2209, 32 },
    2004             :   { 824, 144, 550, 7, 2209, 32 },
    2005             :   { 1040, 144, 550, 7, 2209, 32 },
    2006             :   { 1256, 144, 550, 7, 2209, 32 },
    2007             :   { 1468, 144, 550, 7, 2209, 32 },
    2008             :   { 1680, 144, 550, 7, 2209, 32 },
    2009             :   { 1892, 144, 550, 7, 2209, 32 },
    2010             :   { 2104, 144, 550, 7, 2209, 32 },
    2011             :   { 113, 144, 550, 7, 2209, 32 },
    2012             :   { 402, 144, 550, 7, 2209, 32 },
    2013             :   { 681, 144, 550, 7, 2209, 32 },
    2014             :   { 900, 144, 550, 7, 2209, 32 },
    2015             :   { 1116, 144, 550, 7, 2209, 32 },
    2016             :   { 1332, 144, 550, 7, 2209, 32 },
    2017             :   { 1544, 144, 550, 7, 2209, 32 },
    2018             :   { 1756, 144, 550, 7, 2209, 32 },
    2019             :   { 1968, 144, 550, 7, 2209, 32 },
    2020             :   { 2180, 144, 413, 7, 8976, 29 },
    2021             :   { 189, 144, 7, 7, 96, 32 },
    2022             :   { 2493, 905, 8, 128, 96, 97 },
    2023             :   { 2507, 935, 8, 128, 6529, 97 },
    2024             :   { 262, 899, 8, 128, 8883, 97 },
    2025             :   { 2478, 911, 8, 128, 8976, 26 },
    2026             :   { 540, 917, 8, 128, 2161, 97 },
    2027             :   { 757, 917, 8, 128, 2161, 97 },
    2028             :   { 974, 917, 8, 128, 2161, 97 },
    2029             :   { 1190, 917, 8, 128, 2161, 97 },
    2030             :   { 1406, 917, 8, 128, 2161, 97 },
    2031             :   { 1618, 917, 8, 128, 2161, 97 },
    2032             :   { 1830, 917, 8, 128, 2161, 97 },
    2033             :   { 2042, 917, 8, 128, 2161, 97 },
    2034             :   { 2246, 917, 8, 128, 2161, 97 },
    2035             :   { 49, 917, 8, 128, 2161, 97 },
    2036             :   { 336, 917, 8, 128, 2161, 97 },
    2037             :   { 614, 917, 8, 128, 2161, 97 },
    2038             :   { 832, 917, 8, 128, 2161, 97 },
    2039             :   { 1048, 917, 8, 128, 2161, 97 },
    2040             :   { 1264, 917, 8, 128, 2161, 97 },
    2041             :   { 1476, 917, 8, 128, 2161, 97 },
    2042             :   { 1688, 917, 8, 128, 2161, 97 },
    2043             :   { 1900, 917, 8, 128, 2161, 97 },
    2044             :   { 2112, 917, 8, 128, 2161, 97 },
    2045             :   { 121, 917, 8, 128, 2161, 97 },
    2046             :   { 410, 917, 8, 128, 2161, 97 },
    2047             :   { 689, 917, 8, 128, 2161, 97 },
    2048             :   { 908, 917, 8, 128, 2161, 97 },
    2049             :   { 1124, 917, 8, 128, 2161, 97 },
    2050             :   { 1340, 917, 8, 128, 2161, 97 },
    2051             :   { 1552, 917, 8, 128, 2161, 97 },
    2052             :   { 1764, 917, 8, 128, 2161, 97 },
    2053             :   { 1976, 917, 8, 128, 2161, 97 },
    2054             :   { 554, 564, 372, 134, 1457, 100 },
    2055             :   { 770, 564, 525, 134, 1457, 100 },
    2056             :   { 986, 564, 290, 134, 1457, 100 },
    2057             :   { 1202, 564, 290, 134, 1457, 100 },
    2058             :   { 1418, 564, 290, 134, 1457, 100 },
    2059             :   { 1630, 564, 290, 134, 1457, 100 },
    2060             :   { 1842, 564, 290, 134, 1457, 100 },
    2061             :   { 2054, 564, 290, 134, 1457, 100 },
    2062             :   { 2258, 564, 290, 134, 1457, 100 },
    2063             :   { 62, 564, 290, 134, 1457, 100 },
    2064             :   { 350, 564, 290, 134, 1457, 100 },
    2065             :   { 629, 564, 290, 134, 1457, 100 },
    2066             :   { 848, 564, 290, 134, 1457, 100 },
    2067             :   { 1064, 564, 290, 134, 1457, 100 },
    2068             :   { 1280, 564, 290, 134, 1457, 100 },
    2069             :   { 1492, 564, 290, 134, 1457, 100 },
    2070             :   { 1704, 564, 290, 134, 1457, 100 },
    2071             :   { 1916, 564, 290, 134, 1457, 100 },
    2072             :   { 2128, 564, 290, 134, 1457, 100 },
    2073             :   { 137, 564, 290, 134, 1457, 100 },
    2074             :   { 426, 564, 290, 134, 1457, 100 },
    2075             :   { 705, 564, 290, 134, 1457, 100 },
    2076             :   { 924, 564, 290, 134, 1457, 100 },
    2077             :   { 1140, 564, 290, 134, 1457, 100 },
    2078             :   { 1356, 564, 290, 134, 1457, 100 },
    2079             :   { 1568, 564, 290, 134, 1457, 100 },
    2080             :   { 1780, 564, 290, 134, 1457, 100 },
    2081             :   { 1992, 564, 290, 134, 1457, 100 },
    2082             :   { 2196, 564, 290, 134, 1457, 100 },
    2083             :   { 205, 564, 290, 134, 1457, 100 },
    2084             :   { 486, 564, 290, 134, 1457, 100 },
    2085             :   { 277, 581, 290, 134, 8544, 38 },
    2086             :   { 980, 780, 8, 181, 1, 121 },
    2087             :   { 1196, 780, 8, 181, 1, 121 },
    2088             :   { 1412, 780, 8, 181, 1, 121 },
    2089             :   { 1624, 780, 8, 181, 1, 121 },
    2090             :   { 1836, 780, 8, 181, 1, 121 },
    2091             :   { 2048, 780, 8, 181, 1, 121 },
    2092             :   { 2252, 780, 8, 181, 1, 121 },
    2093             :   { 56, 780, 8, 181, 1, 121 },
    2094             :   { 344, 780, 8, 181, 1, 121 },
    2095             :   { 622, 780, 8, 181, 1, 121 },
    2096             :   { 840, 780, 8, 181, 1, 121 },
    2097             :   { 1056, 780, 8, 181, 1, 121 },
    2098             :   { 1272, 780, 8, 181, 1, 121 },
    2099             :   { 1484, 780, 8, 181, 1, 121 },
    2100             :   { 1696, 780, 8, 181, 1, 121 },
    2101             :   { 1908, 780, 8, 181, 1, 121 },
    2102             :   { 2120, 780, 8, 181, 1, 121 },
    2103             :   { 129, 780, 8, 181, 1, 121 },
    2104             :   { 418, 780, 8, 181, 1, 121 },
    2105             :   { 697, 780, 8, 181, 1, 121 },
    2106             :   { 916, 780, 8, 181, 1, 121 },
    2107             :   { 1132, 780, 8, 181, 1, 121 },
    2108             :   { 1348, 780, 8, 181, 1, 121 },
    2109             :   { 1560, 780, 8, 181, 1, 121 },
    2110             :   { 1772, 780, 8, 181, 1, 121 },
    2111             :   { 1984, 780, 8, 181, 1, 121 },
    2112             :   { 2188, 780, 8, 181, 1, 121 },
    2113             :   { 197, 780, 8, 181, 1, 121 },
    2114             :   { 478, 780, 8, 181, 1, 121 },
    2115             :   { 269, 826, 8, 181, 384, 130 },
    2116             :   { 546, 688, 8, 181, 944, 105 },
    2117             :   { 763, 734, 8, 181, 6864, 43 },
    2118             :   { 767, 598, 545, 151, 625, 139 },
    2119             :   { 983, 598, 180, 151, 625, 139 },
    2120             :   { 1199, 598, 180, 151, 625, 139 },
    2121             :   { 1415, 598, 180, 151, 625, 139 },
    2122             :   { 1627, 598, 180, 151, 625, 139 },
    2123             :   { 1839, 598, 180, 151, 625, 139 },
    2124             :   { 2051, 598, 180, 151, 625, 139 },
    2125             :   { 2255, 598, 180, 151, 625, 139 },
    2126             :   { 59, 598, 180, 151, 625, 139 },
    2127             :   { 347, 598, 180, 151, 625, 139 },
    2128             :   { 625, 598, 180, 151, 625, 139 },
    2129             :   { 844, 598, 180, 151, 625, 139 },
    2130             :   { 1060, 598, 180, 151, 625, 139 },
    2131             :   { 1276, 598, 180, 151, 625, 139 },
    2132             :   { 1488, 598, 180, 151, 625, 139 },
    2133             :   { 1700, 598, 180, 151, 625, 139 },
    2134             :   { 1912, 598, 180, 151, 625, 139 },
    2135             :   { 2124, 598, 180, 151, 625, 139 },
    2136             :   { 133, 598, 180, 151, 625, 139 },
    2137             :   { 422, 598, 180, 151, 625, 139 },
    2138             :   { 701, 598, 180, 151, 625, 139 },
    2139             :   { 920, 598, 180, 151, 625, 139 },
    2140             :   { 1136, 598, 180, 151, 625, 139 },
    2141             :   { 1352, 598, 180, 151, 625, 139 },
    2142             :   { 1564, 598, 180, 151, 625, 139 },
    2143             :   { 1776, 598, 180, 151, 625, 139 },
    2144             :   { 1988, 598, 180, 151, 625, 139 },
    2145             :   { 2192, 598, 180, 151, 625, 139 },
    2146             :   { 201, 598, 180, 151, 625, 139 },
    2147             :   { 482, 598, 180, 151, 625, 139 },
    2148             :   { 273, 628, 180, 151, 1152, 114 },
    2149             :   { 550, 658, 180, 151, 8096, 52 },
    2150             : };
    2151             : 
    2152             : extern const MCPhysReg AArch64RegUnitRoots[][2] = {
    2153             :   { AArch64::FFR },
    2154             :   { AArch64::W29 },
    2155             :   { AArch64::W30 },
    2156             :   { AArch64::NZCV },
    2157             :   { AArch64::WSP },
    2158             :   { AArch64::WZR },
    2159             :   { AArch64::B0 },
    2160             :   { AArch64::B1 },
    2161             :   { AArch64::B2 },
    2162             :   { AArch64::B3 },
    2163             :   { AArch64::B4 },
    2164             :   { AArch64::B5 },
    2165             :   { AArch64::B6 },
    2166             :   { AArch64::B7 },
    2167             :   { AArch64::B8 },
    2168             :   { AArch64::B9 },
    2169             :   { AArch64::B10 },
    2170             :   { AArch64::B11 },
    2171             :   { AArch64::B12 },
    2172             :   { AArch64::B13 },
    2173             :   { AArch64::B14 },
    2174             :   { AArch64::B15 },
    2175             :   { AArch64::B16 },
    2176             :   { AArch64::B17 },
    2177             :   { AArch64::B18 },
    2178             :   { AArch64::B19 },
    2179             :   { AArch64::B20 },
    2180             :   { AArch64::B21 },
    2181             :   { AArch64::B22 },
    2182             :   { AArch64::B23 },
    2183             :   { AArch64::B24 },
    2184             :   { AArch64::B25 },
    2185             :   { AArch64::B26 },
    2186             :   { AArch64::B27 },
    2187             :   { AArch64::B28 },
    2188             :   { AArch64::B29 },
    2189             :   { AArch64::B30 },
    2190             :   { AArch64::B31 },
    2191             :   { AArch64::P0 },
    2192             :   { AArch64::P1 },
    2193             :   { AArch64::P2 },
    2194             :   { AArch64::P3 },
    2195             :   { AArch64::P4 },
    2196             :   { AArch64::P5 },
    2197             :   { AArch64::P6 },
    2198             :   { AArch64::P7 },
    2199             :   { AArch64::P8 },
    2200             :   { AArch64::P9 },
    2201             :   { AArch64::P10 },
    2202             :   { AArch64::P11 },
    2203             :   { AArch64::P12 },
    2204             :   { AArch64::P13 },
    2205             :   { AArch64::P14 },
    2206             :   { AArch64::P15 },
    2207             :   { AArch64::W0 },
    2208             :   { AArch64::W1 },
    2209             :   { AArch64::W2 },
    2210             :   { AArch64::W3 },
    2211             :   { AArch64::W4 },
    2212             :   { AArch64::W5 },
    2213             :   { AArch64::W6 },
    2214             :   { AArch64::W7 },
    2215             :   { AArch64::W8 },
    2216             :   { AArch64::W9 },
    2217             :   { AArch64::W10 },
    2218             :   { AArch64::W11 },
    2219             :   { AArch64::W12 },
    2220             :   { AArch64::W13 },
    2221             :   { AArch64::W14 },
    2222             :   { AArch64::W15 },
    2223             :   { AArch64::W16 },
    2224             :   { AArch64::W17 },
    2225             :   { AArch64::W18 },
    2226             :   { AArch64::W19 },
    2227             :   { AArch64::W20 },
    2228             :   { AArch64::W21 },
    2229             :   { AArch64::W22 },
    2230             :   { AArch64::W23 },
    2231             :   { AArch64::W24 },
    2232             :   { AArch64::W25 },
    2233             :   { AArch64::W26 },
    2234             :   { AArch64::W27 },
    2235             :   { AArch64::W28 },
    2236             :   { AArch64::Z0_HI },
    2237             :   { AArch64::Z1_HI },
    2238             :   { AArch64::Z2_HI },
    2239             :   { AArch64::Z3_HI },
    2240             :   { AArch64::Z4_HI },
    2241             :   { AArch64::Z5_HI },
    2242             :   { AArch64::Z6_HI },
    2243             :   { AArch64::Z7_HI },
    2244             :   { AArch64::Z8_HI },
    2245             :   { AArch64::Z9_HI },
    2246             :   { AArch64::Z10_HI },
    2247             :   { AArch64::Z11_HI },
    2248             :   { AArch64::Z12_HI },
    2249             :   { AArch64::Z13_HI },
    2250             :   { AArch64::Z14_HI },
    2251             :   { AArch64::Z15_HI },
    2252             :   { AArch64::Z16_HI },
    2253             :   { AArch64::Z17_HI },
    2254             :   { AArch64::Z18_HI },
    2255             :   { AArch64::Z19_HI },
    2256             :   { AArch64::Z20_HI },
    2257             :   { AArch64::Z21_HI },
    2258             :   { AArch64::Z22_HI },
    2259             :   { AArch64::Z23_HI },
    2260             :   { AArch64::Z24_HI },
    2261             :   { AArch64::Z25_HI },
    2262             :   { AArch64::Z26_HI },
    2263             :   { AArch64::Z27_HI },
    2264             :   { AArch64::Z28_HI },
    2265             :   { AArch64::Z29_HI },
    2266             :   { AArch64::Z30_HI },
    2267             :   { AArch64::Z31_HI },
    2268             : };
    2269             : 
    2270             : namespace {     // Register classes...
    2271             :   // FPR8 Register Class...
    2272             :   const MCPhysReg FPR8[] = {
    2273             :     AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, 
    2274             :   };
    2275             : 
    2276             :   // FPR8 Bit set.
    2277             :   const uint8_t FPR8Bits[] = {
    2278             :     0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2279             :   };
    2280             : 
    2281             :   // FPR16 Register Class...
    2282             :   const MCPhysReg FPR16[] = {
    2283             :     AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, 
    2284             :   };
    2285             : 
    2286             :   // FPR16 Bit set.
    2287             :   const uint8_t FPR16Bits[] = {
    2288             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2289             :   };
    2290             : 
    2291             :   // PPR Register Class...
    2292             :   const MCPhysReg PPR[] = {
    2293             :     AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, 
    2294             :   };
    2295             : 
    2296             :   // PPR Bit set.
    2297             :   const uint8_t PPRBits[] = {
    2298             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
    2299             :   };
    2300             : 
    2301             :   // PPR_3b Register Class...
    2302             :   const MCPhysReg PPR_3b[] = {
    2303             :     AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 
    2304             :   };
    2305             : 
    2306             :   // PPR_3b Bit set.
    2307             :   const uint8_t PPR_3bBits[] = {
    2308             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
    2309             :   };
    2310             : 
    2311             :   // GPR32all Register Class...
    2312             :   const MCPhysReg GPR32all[] = {
    2313             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, 
    2314             :   };
    2315             : 
    2316             :   // GPR32all Bit set.
    2317             :   const uint8_t GPR32allBits[] = {
    2318             :     0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
    2319             :   };
    2320             : 
    2321             :   // FPR32 Register Class...
    2322             :   const MCPhysReg FPR32[] = {
    2323             :     AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, 
    2324             :   };
    2325             : 
    2326             :   // FPR32 Bit set.
    2327             :   const uint8_t FPR32Bits[] = {
    2328             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2329             :   };
    2330             : 
    2331             :   // GPR32 Register Class...
    2332             :   const MCPhysReg GPR32[] = {
    2333             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, 
    2334             :   };
    2335             : 
    2336             :   // GPR32 Bit set.
    2337             :   const uint8_t GPR32Bits[] = {
    2338             :     0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
    2339             :   };
    2340             : 
    2341             :   // GPR32sp Register Class...
    2342             :   const MCPhysReg GPR32sp[] = {
    2343             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, 
    2344             :   };
    2345             : 
    2346             :   // GPR32sp Bit set.
    2347             :   const uint8_t GPR32spBits[] = {
    2348             :     0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
    2349             :   };
    2350             : 
    2351             :   // GPR32common Register Class...
    2352             :   const MCPhysReg GPR32common[] = {
    2353             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, 
    2354             :   };
    2355             : 
    2356             :   // GPR32common Bit set.
    2357             :   const uint8_t GPR32commonBits[] = {
    2358             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
    2359             :   };
    2360             : 
    2361             :   // CCR Register Class...
    2362             :   const MCPhysReg CCR[] = {
    2363             :     AArch64::NZCV, 
    2364             :   };
    2365             : 
    2366             :   // CCR Bit set.
    2367             :   const uint8_t CCRBits[] = {
    2368             :     0x10, 
    2369             :   };
    2370             : 
    2371             :   // GPR32sponly Register Class...
    2372             :   const MCPhysReg GPR32sponly[] = {
    2373             :     AArch64::WSP, 
    2374             :   };
    2375             : 
    2376             :   // GPR32sponly Bit set.
    2377             :   const uint8_t GPR32sponlyBits[] = {
    2378             :     0x40, 
    2379             :   };
    2380             : 
    2381             :   // WSeqPairsClass Register Class...
    2382             :   const MCPhysReg WSeqPairsClass[] = {
    2383             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, AArch64::WZR_W0, 
    2384             :   };
    2385             : 
    2386             :   // WSeqPairsClass Bit set.
    2387             :   const uint8_t WSeqPairsClassBits[] = {
    2388             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2389             :   };
    2390             : 
    2391             :   // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
    2392             :   const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
    2393             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, 
    2394             :   };
    2395             : 
    2396             :   // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
    2397             :   const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
    2398             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 
    2399             :   };
    2400             : 
    2401             :   // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
    2402             :   const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
    2403             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::WZR_W0, 
    2404             :   };
    2405             : 
    2406             :   // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
    2407             :   const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    2408             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, 
    2409             :   };
    2410             : 
    2411             :   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
    2412             :   const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
    2413             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, 
    2414             :   };
    2415             : 
    2416             :   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
    2417             :   const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    2418             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
    2419             :   };
    2420             : 
    2421             :   // GPR64all Register Class...
    2422             :   const MCPhysReg GPR64all[] = {
    2423             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, 
    2424             :   };
    2425             : 
    2426             :   // GPR64all Bit set.
    2427             :   const uint8_t GPR64allBits[] = {
    2428             :     0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
    2429             :   };
    2430             : 
    2431             :   // FPR64 Register Class...
    2432             :   const MCPhysReg FPR64[] = {
    2433             :     AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 
    2434             :   };
    2435             : 
    2436             :   // FPR64 Bit set.
    2437             :   const uint8_t FPR64Bits[] = {
    2438             :     0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2439             :   };
    2440             : 
    2441             :   // GPR64 Register Class...
    2442             :   const MCPhysReg GPR64[] = {
    2443             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, 
    2444             :   };
    2445             : 
    2446             :   // GPR64 Bit set.
    2447             :   const uint8_t GPR64Bits[] = {
    2448             :     0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
    2449             :   };
    2450             : 
    2451             :   // GPR64sp Register Class...
    2452             :   const MCPhysReg GPR64sp[] = {
    2453             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, 
    2454             :   };
    2455             : 
    2456             :   // GPR64sp Bit set.
    2457             :   const uint8_t GPR64spBits[] = {
    2458             :     0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
    2459             :   };
    2460             : 
    2461             :   // GPR64common Register Class...
    2462             :   const MCPhysReg GPR64common[] = {
    2463             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, 
    2464             :   };
    2465             : 
    2466             :   // GPR64common Bit set.
    2467             :   const uint8_t GPR64commonBits[] = {
    2468             :     0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
    2469             :   };
    2470             : 
    2471             :   // tcGPR64 Register Class...
    2472             :   const MCPhysReg tcGPR64[] = {
    2473             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, 
    2474             :   };
    2475             : 
    2476             :   // tcGPR64 Bit set.
    2477             :   const uint8_t tcGPR64Bits[] = {
    2478             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, 
    2479             :   };
    2480             : 
    2481             :   // GPR64sponly Register Class...
    2482             :   const MCPhysReg GPR64sponly[] = {
    2483             :     AArch64::SP, 
    2484             :   };
    2485             : 
    2486             :   // GPR64sponly Bit set.
    2487             :   const uint8_t GPR64sponlyBits[] = {
    2488             :     0x20, 
    2489             :   };
    2490             : 
    2491             :   // DD Register Class...
    2492             :   const MCPhysReg DD[] = {
    2493             :     AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, 
    2494             :   };
    2495             : 
    2496             :   // DD Bit set.
    2497             :   const uint8_t DDBits[] = {
    2498             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2499             :   };
    2500             : 
    2501             :   // XSeqPairsClass Register Class...
    2502             :   const MCPhysReg XSeqPairsClass[] = {
    2503             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, AArch64::XZR_X0, 
    2504             :   };
    2505             : 
    2506             :   // XSeqPairsClass Bit set.
    2507             :   const uint8_t XSeqPairsClassBits[] = {
    2508             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2509             :   };
    2510             : 
    2511             :   // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
    2512             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
    2513             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, 
    2514             :   };
    2515             : 
    2516             :   // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
    2517             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
    2518             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f, 
    2519             :   };
    2520             : 
    2521             :   // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
    2522             :   const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
    2523             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::XZR_X0, 
    2524             :   };
    2525             : 
    2526             :   // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
    2527             :   const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    2528             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, 
    2529             :   };
    2530             : 
    2531             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
    2532             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
    2533             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, 
    2534             :   };
    2535             : 
    2536             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
    2537             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    2538             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xff, 0x1f, 
    2539             :   };
    2540             : 
    2541             :   // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
    2542             :   const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
    2543             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, 
    2544             :   };
    2545             : 
    2546             :   // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
    2547             :   const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
    2548             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f, 
    2549             :   };
    2550             : 
    2551             :   // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
    2552             :   const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    2553             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::XZR_X0, 
    2554             :   };
    2555             : 
    2556             :   // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
    2557             :   const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    2558             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xfe, 0xff, 0x07, 
    2559             :   };
    2560             : 
    2561             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
    2562             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    2563             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, 
    2564             :   };
    2565             : 
    2566             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
    2567             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    2568             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, 
    2569             :   };
    2570             : 
    2571             :   // FPR128 Register Class...
    2572             :   const MCPhysReg FPR128[] = {
    2573             :     AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 
    2574             :   };
    2575             : 
    2576             :   // FPR128 Bit set.
    2577             :   const uint8_t FPR128Bits[] = {
    2578             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2579             :   };
    2580             : 
    2581             :   // ZPR Register Class...
    2582             :   const MCPhysReg ZPR[] = {
    2583             :     AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31, 
    2584             :   };
    2585             : 
    2586             :   // ZPR Bit set.
    2587             :   const uint8_t ZPRBits[] = {
    2588             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2589             :   };
    2590             : 
    2591             :   // FPR128_lo Register Class...
    2592             :   const MCPhysReg FPR128_lo[] = {
    2593             :     AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, 
    2594             :   };
    2595             : 
    2596             :   // FPR128_lo Bit set.
    2597             :   const uint8_t FPR128_loBits[] = {
    2598             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
    2599             :   };
    2600             : 
    2601             :   // ZPR_with_zsub_in_FPR128_lo Register Class...
    2602             :   const MCPhysReg ZPR_with_zsub_in_FPR128_lo[] = {
    2603             :     AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 
    2604             :   };
    2605             : 
    2606             :   // ZPR_with_zsub_in_FPR128_lo Bit set.
    2607             :   const uint8_t ZPR_with_zsub_in_FPR128_loBits[] = {
    2608             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2609             :   };
    2610             : 
    2611             :   // DDD Register Class...
    2612             :   const MCPhysReg DDD[] = {
    2613             :     AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, 
    2614             :   };
    2615             : 
    2616             :   // DDD Bit set.
    2617             :   const uint8_t DDDBits[] = {
    2618             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2619             :   };
    2620             : 
    2621             :   // DDDD Register Class...
    2622             :   const MCPhysReg DDDD[] = {
    2623             :     AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, 
    2624             :   };
    2625             : 
    2626             :   // DDDD Bit set.
    2627             :   const uint8_t DDDDBits[] = {
    2628             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2629             :   };
    2630             : 
    2631             :   // QQ Register Class...
    2632             :   const MCPhysReg QQ[] = {
    2633             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, 
    2634             :   };
    2635             : 
    2636             :   // QQ Bit set.
    2637             :   const uint8_t QQBits[] = {
    2638             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2639             :   };
    2640             : 
    2641             :   // ZPR2 Register Class...
    2642             :   const MCPhysReg ZPR2[] = {
    2643             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0, 
    2644             :   };
    2645             : 
    2646             :   // ZPR2 Bit set.
    2647             :   const uint8_t ZPR2Bits[] = {
    2648             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2649             :   };
    2650             : 
    2651             :   // QQ_with_qsub0_in_FPR128_lo Register Class...
    2652             :   const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
    2653             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 
    2654             :   };
    2655             : 
    2656             :   // QQ_with_qsub0_in_FPR128_lo Bit set.
    2657             :   const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
    2658             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2659             :   };
    2660             : 
    2661             :   // QQ_with_qsub1_in_FPR128_lo Register Class...
    2662             :   const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
    2663             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, 
    2664             :   };
    2665             : 
    2666             :   // QQ_with_qsub1_in_FPR128_lo Bit set.
    2667             :   const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
    2668             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2669             :   };
    2670             : 
    2671             :   // ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2672             :   const MCPhysReg ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2673             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0, 
    2674             :   };
    2675             : 
    2676             :   // ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2677             :   const uint8_t ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2678             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2679             :   };
    2680             : 
    2681             :   // ZPR2_with_zsub_in_FPR128_lo Register Class...
    2682             :   const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
    2683             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 
    2684             :   };
    2685             : 
    2686             :   // ZPR2_with_zsub_in_FPR128_lo Bit set.
    2687             :   const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
    2688             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2689             :   };
    2690             : 
    2691             :   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
    2692             :   const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
    2693             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, 
    2694             :   };
    2695             : 
    2696             :   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
    2697             :   const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
    2698             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2699             :   };
    2700             : 
    2701             :   // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2702             :   const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2703             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, 
    2704             :   };
    2705             : 
    2706             :   // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2707             :   const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2708             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2709             :   };
    2710             : 
    2711             :   // QQQ Register Class...
    2712             :   const MCPhysReg QQQ[] = {
    2713             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
    2714             :   };
    2715             : 
    2716             :   // QQQ Bit set.
    2717             :   const uint8_t QQQBits[] = {
    2718             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2719             :   };
    2720             : 
    2721             :   // ZPR3 Register Class...
    2722             :   const MCPhysReg ZPR3[] = {
    2723             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
    2724             :   };
    2725             : 
    2726             :   // ZPR3 Bit set.
    2727             :   const uint8_t ZPR3Bits[] = {
    2728             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2729             :   };
    2730             : 
    2731             :   // QQQ_with_qsub0_in_FPR128_lo Register Class...
    2732             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
    2733             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, 
    2734             :   };
    2735             : 
    2736             :   // QQQ_with_qsub0_in_FPR128_lo Bit set.
    2737             :   const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
    2738             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2739             :   };
    2740             : 
    2741             :   // QQQ_with_qsub1_in_FPR128_lo Register Class...
    2742             :   const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
    2743             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, 
    2744             :   };
    2745             : 
    2746             :   // QQQ_with_qsub1_in_FPR128_lo Bit set.
    2747             :   const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
    2748             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2749             :   };
    2750             : 
    2751             :   // QQQ_with_qsub2_in_FPR128_lo Register Class...
    2752             :   const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
    2753             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
    2754             :   };
    2755             : 
    2756             :   // QQQ_with_qsub2_in_FPR128_lo Bit set.
    2757             :   const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
    2758             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
    2759             :   };
    2760             : 
    2761             :   // ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2762             :   const MCPhysReg ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2763             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1, 
    2764             :   };
    2765             : 
    2766             :   // ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2767             :   const uint8_t ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2768             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2769             :   };
    2770             : 
    2771             :   // ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2772             :   const MCPhysReg ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2773             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
    2774             :   };
    2775             : 
    2776             :   // ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2777             :   const uint8_t ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2778             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
    2779             :   };
    2780             : 
    2781             :   // ZPR3_with_zsub_in_FPR128_lo Register Class...
    2782             :   const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
    2783             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, 
    2784             :   };
    2785             : 
    2786             :   // ZPR3_with_zsub_in_FPR128_lo Bit set.
    2787             :   const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
    2788             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2789             :   };
    2790             : 
    2791             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
    2792             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
    2793             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 
    2794             :   };
    2795             : 
    2796             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
    2797             :   const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
    2798             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2799             :   };
    2800             : 
    2801             :   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
    2802             :   const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    2803             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, 
    2804             :   };
    2805             : 
    2806             :   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
    2807             :   const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    2808             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
    2809             :   };
    2810             : 
    2811             :   // ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2812             :   const MCPhysReg ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2813             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1, 
    2814             :   };
    2815             : 
    2816             :   // ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2817             :   const uint8_t ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2818             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
    2819             :   };
    2820             : 
    2821             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2822             :   const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2823             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 
    2824             :   };
    2825             : 
    2826             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2827             :   const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2828             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2829             :   };
    2830             : 
    2831             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
    2832             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    2833             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, 
    2834             :   };
    2835             : 
    2836             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
    2837             :   const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    2838             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
    2839             :   };
    2840             : 
    2841             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2842             :   const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2843             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, 
    2844             :   };
    2845             : 
    2846             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2847             :   const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2848             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
    2849             :   };
    2850             : 
    2851             :   // QQQQ Register Class...
    2852             :   const MCPhysReg QQQQ[] = {
    2853             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2854             :   };
    2855             : 
    2856             :   // QQQQ Bit set.
    2857             :   const uint8_t QQQQBits[] = {
    2858             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2859             :   };
    2860             : 
    2861             :   // ZPR4 Register Class...
    2862             :   const MCPhysReg ZPR4[] = {
    2863             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    2864             :   };
    2865             : 
    2866             :   // ZPR4 Bit set.
    2867             :   const uint8_t ZPR4Bits[] = {
    2868             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2869             :   };
    2870             : 
    2871             :   // QQQQ_with_qsub0_in_FPR128_lo Register Class...
    2872             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
    2873             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, 
    2874             :   };
    2875             : 
    2876             :   // QQQQ_with_qsub0_in_FPR128_lo Bit set.
    2877             :   const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
    2878             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2879             :   };
    2880             : 
    2881             :   // QQQQ_with_qsub1_in_FPR128_lo Register Class...
    2882             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
    2883             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, 
    2884             :   };
    2885             : 
    2886             :   // QQQQ_with_qsub1_in_FPR128_lo Bit set.
    2887             :   const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
    2888             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2889             :   };
    2890             : 
    2891             :   // QQQQ_with_qsub2_in_FPR128_lo Register Class...
    2892             :   const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
    2893             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2894             :   };
    2895             : 
    2896             :   // QQQQ_with_qsub2_in_FPR128_lo Bit set.
    2897             :   const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
    2898             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
    2899             :   };
    2900             : 
    2901             :   // QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2902             :   const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
    2903             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2904             :   };
    2905             : 
    2906             :   // QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2907             :   const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2908             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
    2909             :   };
    2910             : 
    2911             :   // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2912             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2913             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2, 
    2914             :   };
    2915             : 
    2916             :   // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2917             :   const uint8_t ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2918             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2919             :   };
    2920             : 
    2921             :   // ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2922             :   const MCPhysReg ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2923             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    2924             :   };
    2925             : 
    2926             :   // ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2927             :   const uint8_t ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2928             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
    2929             :   };
    2930             : 
    2931             :   // ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2932             :   const MCPhysReg ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2933             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    2934             :   };
    2935             : 
    2936             :   // ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2937             :   const uint8_t ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2938             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
    2939             :   };
    2940             : 
    2941             :   // ZPR4_with_zsub_in_FPR128_lo Register Class...
    2942             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
    2943             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, 
    2944             :   };
    2945             : 
    2946             :   // ZPR4_with_zsub_in_FPR128_lo Bit set.
    2947             :   const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
    2948             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2949             :   };
    2950             : 
    2951             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
    2952             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
    2953             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 
    2954             :   };
    2955             : 
    2956             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
    2957             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
    2958             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2959             :   };
    2960             : 
    2961             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
    2962             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    2963             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, 
    2964             :   };
    2965             : 
    2966             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
    2967             :   const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    2968             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
    2969             :   };
    2970             : 
    2971             :   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    2972             :   const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    2973             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2974             :   };
    2975             : 
    2976             :   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    2977             :   const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    2978             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
    2979             :   };
    2980             : 
    2981             :   // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2982             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2983             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2, 
    2984             :   };
    2985             : 
    2986             :   // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2987             :   const uint8_t ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2988             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
    2989             :   };
    2990             : 
    2991             :   // ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    2992             :   const MCPhysReg ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo[] = {
    2993             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    2994             :   };
    2995             : 
    2996             :   // ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    2997             :   const uint8_t ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    2998             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
    2999             :   };
    3000             : 
    3001             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    3002             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo[] = {
    3003             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 
    3004             :   };
    3005             : 
    3006             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    3007             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    3008             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    3009             :   };
    3010             : 
    3011             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
    3012             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    3013             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, 
    3014             :   };
    3015             : 
    3016             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
    3017             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    3018             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
    3019             :   };
    3020             : 
    3021             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    3022             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    3023             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, 
    3024             :   };
    3025             : 
    3026             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    3027             :   const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    3028             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
    3029             :   };
    3030             : 
    3031             :   // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    3032             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo[] = {
    3033             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2, 
    3034             :   };
    3035             : 
    3036             :   // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    3037             :   const uint8_t ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    3038             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
    3039             :   };
    3040             : 
    3041             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    3042             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo[] = {
    3043             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, 
    3044             :   };
    3045             : 
    3046             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    3047             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    3048             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
    3049             :   };
    3050             : 
    3051             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    3052             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    3053             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, 
    3054             :   };
    3055             : 
    3056             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    3057             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    3058             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
    3059             :   };
    3060             : 
    3061             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo Register Class...
    3062             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo[] = {
    3063             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, 
    3064             :   };
    3065             : 
    3066             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo Bit set.
    3067             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits[] = {
    3068             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
    3069             :   };
    3070             : 
    3071             : } // end anonymous namespace
    3072             : 
    3073             : extern const char AArch64RegClassStrings[] = {
    3074             :   /* 0 */ 'F', 'P', 'R', '3', '2', 0,
    3075             :   /* 6 */ 'G', 'P', 'R', '3', '2', 0,
    3076             :   /* 12 */ 'Z', 'P', 'R', '2', 0,
    3077             :   /* 17 */ 'Z', 'P', 'R', '3', 0,
    3078             :   /* 22 */ 'F', 'P', 'R', '6', '4', 0,
    3079             :   /* 28 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
    3080             :   /* 66 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
    3081             :   /* 150 */ 'Z', 'P', 'R', '4', 0,
    3082             :   /* 155 */ 'F', 'P', 'R', '1', '6', 0,
    3083             :   /* 161 */ 'F', 'P', 'R', '1', '2', '8', 0,
    3084             :   /* 168 */ 'F', 'P', 'R', '8', 0,
    3085             :   /* 173 */ 'D', 'D', 'D', 'D', 0,
    3086             :   /* 178 */ 'Q', 'Q', 'Q', 'Q', 0,
    3087             :   /* 183 */ 'C', 'C', 'R', 0,
    3088             :   /* 187 */ 'P', 'P', 'R', 0,
    3089             :   /* 191 */ 'Z', 'P', 'R', 0,
    3090             :   /* 195 */ 'P', 'P', 'R', '_', '3', 'b', 0,
    3091             :   /* 202 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
    3092             :   /* 211 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
    3093             :   /* 220 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    3094             :   /* 262 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    3095             :   /* 304 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    3096             :   /* 392 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    3097             :   /* 480 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3098             :   /* 509 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3099             :   /* 571 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3100             :   /* 631 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3101             :   /* 689 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3102             :   /* 751 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3103             :   /* 813 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3104             :   /* 873 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3105             :   /* 933 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3106             :   /* 995 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3107             :   /* 1057 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3108             :   /* 1119 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3109             :   /* 1147 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3110             :   /* 1175 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3111             :   /* 1203 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3112             :   /* 1281 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3113             :   /* 1359 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3114             :   /* 1437 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3115             :   /* 1515 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3116             :   /* 1611 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3117             :   /* 1689 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3118             :   /* 1785 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3119             :   /* 1863 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3120             :   /* 1959 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3121             :   /* 2055 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
    3122             :   /* 2063 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
    3123             :   /* 2071 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
    3124             :   /* 2086 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
    3125             :   /* 2101 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
    3126             :   /* 2113 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
    3127             : };
    3128             : 
    3129             : extern const MCRegisterClass AArch64MCRegisterClasses[] = {
    3130             :   { FPR8, FPR8Bits, 168, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, 1, true },
    3131             :   { FPR16, FPR16Bits, 155, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 2, 1, true },
    3132             :   { PPR, PPRBits, 187, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 2, 1, true },
    3133             :   { PPR_3b, PPR_3bBits, 195, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 2, 1, true },
    3134             :   { GPR32all, GPR32allBits, 202, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 4, 1, true },
    3135             :   { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 4, 1, true },
    3136             :   { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 4, 1, true },
    3137             :   { GPR32sp, GPR32spBits, 2055, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 4, 1, true },
    3138             :   { GPR32common, GPR32commonBits, 250, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 4, 1, true },
    3139             :   { CCR, CCRBits, 183, 1, sizeof(CCRBits), AArch64::CCRRegClassID, 4, -1, false },
    3140             :   { GPR32sponly, GPR32sponlyBits, 2101, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 4, 1, true },
    3141             :   { WSeqPairsClass, WSeqPairsClassBits, 2071, 32, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 8, 1, true },
    3142             :   { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, 262, 31, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClassID, 8, 1, true },
    3143             :   { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 350, 31, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 1, true },
    3144             :   { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, 304, 30, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 1, true },
    3145             :   { GPR64all, GPR64allBits, 211, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 8, 1, true },
    3146             :   { FPR64, FPR64Bits, 22, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 8, 1, true },
    3147             :   { GPR64, GPR64Bits, 60, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 8, 1, true },
    3148             :   { GPR64sp, GPR64spBits, 2063, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 8, 1, true },
    3149             :   { GPR64common, GPR64commonBits, 468, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 8, 1, true },
    3150             :   { tcGPR64, tcGPR64Bits, 58, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 8, 1, true },
    3151             :   { GPR64sponly, GPR64sponlyBits, 2113, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 8, 1, true },
    3152             :   { DD, DDBits, 175, 32, sizeof(DDBits), AArch64::DDRegClassID, 16, 1, true },
    3153             :   { XSeqPairsClass, XSeqPairsClassBits, 2086, 32, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 16, 1, true },
    3154             :   { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, 220, 31, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID, 16, 1, true },
    3155             :   { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 438, 31, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 1, true },
    3156             :   { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, 392, 30, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 1, true },
    3157             :   { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 28, 19, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 16, 1, true },
    3158             :   { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 112, 19, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 1, true },
    3159             :   { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, 66, 18, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 1, true },
    3160             :   { FPR128, FPR128Bits, 161, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 16, 1, true },
    3161             :   { ZPR, ZPRBits, 191, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 16, 1, true },
    3162             :   { FPR128_lo, FPR128_loBits, 499, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 16, 1, true },
    3163             :   { ZPR_with_zsub_in_FPR128_lo, ZPR_with_zsub_in_FPR128_loBits, 1254, 16, sizeof(ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR_with_zsub_in_FPR128_loRegClassID, 16, 1, true },
    3164             :   { DDD, DDDBits, 174, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 24, 1, true },
    3165             :   { DDDD, DDDDBits, 173, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 32, 1, true },
    3166             :   { QQ, QQBits, 180, 32, sizeof(QQBits), AArch64::QQRegClassID, 32, 1, true },
    3167             :   { ZPR2, ZPR2Bits, 12, 32, sizeof(ZPR2Bits), AArch64::ZPR2RegClassID, 32, 1, true },
    3168             :   { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 482, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 32, 1, true },
    3169             :   { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 544, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 32, 1, true },
    3170             :   { ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo, ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits, 1235, 16, sizeof(ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID, 32, 1, true },
    3171             :   { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, 1119, 16, sizeof(ZPR2_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub_in_FPR128_loRegClassID, 32, 1, true },
    3172             :   { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 631, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 1, true },
    3173             :   { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits, 1203, 15, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID, 32, 1, true },
    3174             :   { QQQ, QQQBits, 179, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 48, 1, true },
    3175             :   { ZPR3, ZPR3Bits, 17, 32, sizeof(ZPR3Bits), AArch64::ZPR3RegClassID, 48, 1, true },
    3176             :   { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 481, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 1, true },
    3177             :   { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 543, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 1, true },
    3178             :   { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 723, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    3179             :   { ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo, ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits, 1313, 16, sizeof(ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID, 48, 1, true },
    3180             :   { ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo, ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits, 1469, 16, sizeof(ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID, 48, 1, true },
    3181             :   { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, 1147, 16, sizeof(ZPR3_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_loRegClassID, 48, 1, true },
    3182             :   { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 571, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 1, true },
    3183             :   { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 873, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    3184             :   { ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo, ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits, 1515, 15, sizeof(ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID, 48, 1, true },
    3185             :   { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits, 1281, 15, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID, 48, 1, true },
    3186             :   { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 813, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    3187             :   { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits, 1437, 14, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID, 48, 1, true },
    3188             :   { QQQQ, QQQQBits, 178, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 64, 1, true },
    3189             :   { ZPR4, ZPR4Bits, 150, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 64, 1, true },
    3190             :   { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 480, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 1, true },
    3191             :   { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 542, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 1, true },
    3192             :   { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 722, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    3193             :   { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 966, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    3194             :   { ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits, 1391, 16, sizeof(ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3195             :   { ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits, 1643, 16, sizeof(ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3196             :   { ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits, 1817, 16, sizeof(ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3197             :   { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, 1175, 16, sizeof(ZPR4_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3198             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 509, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 1, true },
    3199             :   { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 751, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    3200             :   { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 1057, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    3201             :   { ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits, 1689, 15, sizeof(ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3202             :   { ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits, 1959, 15, sizeof(ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3203             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits, 1359, 15, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3204             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 689, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    3205             :   { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 995, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    3206             :   { ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits, 1863, 14, sizeof(ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3207             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits, 1611, 14, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3208             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 933, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    3209             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits, 1785, 13, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3210             : };
    3211             : 
    3212             : // AArch64 Dwarf<->LLVM register mappings.
    3213             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
    3214             :   { 0U, AArch64::W0 },
    3215             :   { 1U, AArch64::W1 },
    3216             :   { 2U, AArch64::W2 },
    3217             :   { 3U, AArch64::W3 },
    3218             :   { 4U, AArch64::W4 },
    3219             :   { 5U, AArch64::W5 },
    3220             :   { 6U, AArch64::W6 },
    3221             :   { 7U, AArch64::W7 },
    3222             :   { 8U, AArch64::W8 },
    3223             :   { 9U, AArch64::W9 },
    3224             :   { 10U, AArch64::W10 },
    3225             :   { 11U, AArch64::W11 },
    3226             :   { 12U, AArch64::W12 },
    3227             :   { 13U, AArch64::W13 },
    3228             :   { 14U, AArch64::W14 },
    3229             :   { 15U, AArch64::W15 },
    3230             :   { 16U, AArch64::W16 },
    3231             :   { 17U, AArch64::W17 },
    3232             :   { 18U, AArch64::W18 },
    3233             :   { 19U, AArch64::W19 },
    3234             :   { 20U, AArch64::W20 },
    3235             :   { 21U, AArch64::W21 },
    3236             :   { 22U, AArch64::W22 },
    3237             :   { 23U, AArch64::W23 },
    3238             :   { 24U, AArch64::W24 },
    3239             :   { 25U, AArch64::W25 },
    3240             :   { 26U, AArch64::W26 },
    3241             :   { 27U, AArch64::W27 },
    3242             :   { 28U, AArch64::W28 },
    3243             :   { 29U, AArch64::W29 },
    3244             :   { 30U, AArch64::W30 },
    3245             :   { 31U, AArch64::WSP },
    3246             :   { 47U, AArch64::FFR },
    3247             :   { 48U, AArch64::P0 },
    3248             :   { 49U, AArch64::P1 },
    3249             :   { 50U, AArch64::P2 },
    3250             :   { 51U, AArch64::P3 },
    3251             :   { 52U, AArch64::P4 },
    3252             :   { 53U, AArch64::P5 },
    3253             :   { 54U, AArch64::P6 },
    3254             :   { 55U, AArch64::P7 },
    3255             :   { 56U, AArch64::P8 },
    3256             :   { 57U, AArch64::P9 },
    3257             :   { 58U, AArch64::P10 },
    3258             :   { 59U, AArch64::P11 },
    3259             :   { 60U, AArch64::P12 },
    3260             :   { 61U, AArch64::P13 },
    3261             :   { 62U, AArch64::P14 },
    3262             :   { 63U, AArch64::P15 },
    3263             :   { 64U, AArch64::B0 },
    3264             :   { 65U, AArch64::B1 },
    3265             :   { 66U, AArch64::B2 },
    3266             :   { 67U, AArch64::B3 },
    3267             :   { 68U, AArch64::B4 },
    3268             :   { 69U, AArch64::B5 },
    3269             :   { 70U, AArch64::B6 },
    3270             :   { 71U, AArch64::B7 },
    3271             :   { 72U, AArch64::B8 },
    3272             :   { 73U, AArch64::B9 },
    3273             :   { 74U, AArch64::B10 },
    3274             :   { 75U, AArch64::B11 },
    3275             :   { 76U, AArch64::B12 },
    3276             :   { 77U, AArch64::B13 },
    3277             :   { 78U, AArch64::B14 },
    3278             :   { 79U, AArch64::B15 },
    3279             :   { 80U, AArch64::B16 },
    3280             :   { 81U, AArch64::B17 },
    3281             :   { 82U, AArch64::B18 },
    3282             :   { 83U, AArch64::B19 },
    3283             :   { 84U, AArch64::B20 },
    3284             :   { 85U, AArch64::B21 },
    3285             :   { 86U, AArch64::B22 },
    3286             :   { 87U, AArch64::B23 },
    3287             :   { 88U, AArch64::B24 },
    3288             :   { 89U, AArch64::B25 },
    3289             :   { 90U, AArch64::B26 },
    3290             :   { 91U, AArch64::B27 },
    3291             :   { 92U, AArch64::B28 },
    3292             :   { 93U, AArch64::B29 },
    3293             :   { 94U, AArch64::B30 },
    3294             :   { 95U, AArch64::B31 },
    3295             :   { 96U, AArch64::Z0 },
    3296             :   { 97U, AArch64::Z1 },
    3297             :   { 98U, AArch64::Z2 },
    3298             :   { 99U, AArch64::Z3 },
    3299             :   { 100U, AArch64::Z4 },
    3300             :   { 101U, AArch64::Z5 },
    3301             :   { 102U, AArch64::Z6 },
    3302             :   { 103U, AArch64::Z7 },
    3303             :   { 104U, AArch64::Z8 },
    3304             :   { 105U, AArch64::Z9 },
    3305             :   { 106U, AArch64::Z10 },
    3306             :   { 107U, AArch64::Z11 },
    3307             :   { 108U, AArch64::Z12 },
    3308             :   { 109U, AArch64::Z13 },
    3309             :   { 110U, AArch64::Z14 },
    3310             :   { 111U, AArch64::Z15 },
    3311             :   { 112U, AArch64::Z16 },
    3312             :   { 113U, AArch64::Z17 },
    3313             :   { 114U, AArch64::Z18 },
    3314             :   { 115U, AArch64::Z19 },
    3315             :   { 116U, AArch64::Z20 },
    3316             :   { 117U, AArch64::Z21 },
    3317             :   { 118U, AArch64::Z22 },
    3318             :   { 119U, AArch64::Z23 },
    3319             :   { 120U, AArch64::Z24 },
    3320             :   { 121U, AArch64::Z25 },
    3321             :   { 122U, AArch64::Z26 },
    3322             :   { 123U, AArch64::Z27 },
    3323             :   { 124U, AArch64::Z28 },
    3324             :   { 125U, AArch64::Z29 },
    3325             :   { 126U, AArch64::Z30 },
    3326             :   { 127U, AArch64::Z31 },
    3327             : };
    3328             : extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
    3329             : 
    3330             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
    3331             :   { 0U, AArch64::W0 },
    3332             :   { 1U, AArch64::W1 },
    3333             :   { 2U, AArch64::W2 },
    3334             :   { 3U, AArch64::W3 },
    3335             :   { 4U, AArch64::W4 },
    3336             :   { 5U, AArch64::W5 },
    3337             :   { 6U, AArch64::W6 },
    3338             :   { 7U, AArch64::W7 },
    3339             :   { 8U, AArch64::W8 },
    3340             :   { 9U, AArch64::W9 },
    3341             :   { 10U, AArch64::W10 },
    3342             :   { 11U, AArch64::W11 },
    3343             :   { 12U, AArch64::W12 },
    3344             :   { 13U, AArch64::W13 },
    3345             :   { 14U, AArch64::W14 },
    3346             :   { 15U, AArch64::W15 },
    3347             :   { 16U, AArch64::W16 },
    3348             :   { 17U, AArch64::W17 },
    3349             :   { 18U, AArch64::W18 },
    3350             :   { 19U, AArch64::W19 },
    3351             :   { 20U, AArch64::W20 },
    3352             :   { 21U, AArch64::W21 },
    3353             :   { 22U, AArch64::W22 },
    3354             :   { 23U, AArch64::W23 },
    3355             :   { 24U, AArch64::W24 },
    3356             :   { 25U, AArch64::W25 },
    3357             :   { 26U, AArch64::W26 },
    3358             :   { 27U, AArch64::W27 },
    3359             :   { 28U, AArch64::W28 },
    3360             :   { 29U, AArch64::W29 },
    3361             :   { 30U, AArch64::W30 },
    3362             :   { 31U, AArch64::WSP },
    3363             :   { 47U, AArch64::FFR },
    3364             :   { 48U, AArch64::P0 },
    3365             :   { 49U, AArch64::P1 },
    3366             :   { 50U, AArch64::P2 },
    3367             :   { 51U, AArch64::P3 },
    3368             :   { 52U, AArch64::P4 },
    3369             :   { 53U, AArch64::P5 },
    3370             :   { 54U, AArch64::P6 },
    3371             :   { 55U, AArch64::P7 },
    3372             :   { 56U, AArch64::P8 },
    3373             :   { 57U, AArch64::P9 },
    3374             :   { 58U, AArch64::P10 },
    3375             :   { 59U, AArch64::P11 },
    3376             :   { 60U, AArch64::P12 },
    3377             :   { 61U, AArch64::P13 },
    3378             :   { 62U, AArch64::P14 },
    3379             :   { 63U, AArch64::P15 },
    3380             :   { 64U, AArch64::B0 },
    3381             :   { 65U, AArch64::B1 },
    3382             :   { 66U, AArch64::B2 },
    3383             :   { 67U, AArch64::B3 },
    3384             :   { 68U, AArch64::B4 },
    3385             :   { 69U, AArch64::B5 },
    3386             :   { 70U, AArch64::B6 },
    3387             :   { 71U, AArch64::B7 },
    3388             :   { 72U, AArch64::B8 },
    3389             :   { 73U, AArch64::B9 },
    3390             :   { 74U, AArch64::B10 },
    3391             :   { 75U, AArch64::B11 },
    3392             :   { 76U, AArch64::B12 },
    3393             :   { 77U, AArch64::B13 },
    3394             :   { 78U, AArch64::B14 },
    3395             :   { 79U, AArch64::B15 },
    3396             :   { 80U, AArch64::B16 },
    3397             :   { 81U, AArch64::B17 },
    3398             :   { 82U, AArch64::B18 },
    3399             :   { 83U, AArch64::B19 },
    3400             :   { 84U, AArch64::B20 },
    3401             :   { 85U, AArch64::B21 },
    3402             :   { 86U, AArch64::B22 },
    3403             :   { 87U, AArch64::B23 },
    3404             :   { 88U, AArch64::B24 },
    3405             :   { 89U, AArch64::B25 },
    3406             :   { 90U, AArch64::B26 },
    3407             :   { 91U, AArch64::B27 },
    3408             :   { 92U, AArch64::B28 },
    3409             :   { 93U, AArch64::B29 },
    3410             :   { 94U, AArch64::B30 },
    3411             :   { 95U, AArch64::B31 },
    3412             :   { 96U, AArch64::Z0 },
    3413             :   { 97U, AArch64::Z1 },
    3414             :   { 98U, AArch64::Z2 },
    3415             :   { 99U, AArch64::Z3 },
    3416             :   { 100U, AArch64::Z4 },
    3417             :   { 101U, AArch64::Z5 },
    3418             :   { 102U, AArch64::Z6 },
    3419             :   { 103U, AArch64::Z7 },
    3420             :   { 104U, AArch64::Z8 },
    3421             :   { 105U, AArch64::Z9 },
    3422             :   { 106U, AArch64::Z10 },
    3423             :   { 107U, AArch64::Z11 },
    3424             :   { 108U, AArch64::Z12 },
    3425             :   { 109U, AArch64::Z13 },
    3426             :   { 110U, AArch64::Z14 },
    3427             :   { 111U, AArch64::Z15 },
    3428             :   { 112U, AArch64::Z16 },
    3429             :   { 113U, AArch64::Z17 },
    3430             :   { 114U, AArch64::Z18 },
    3431             :   { 115U, AArch64::Z19 },
    3432             :   { 116U, AArch64::Z20 },
    3433             :   { 117U, AArch64::Z21 },
    3434             :   { 118U, AArch64::Z22 },
    3435             :   { 119U, AArch64::Z23 },
    3436             :   { 120U, AArch64::Z24 },
    3437             :   { 121U, AArch64::Z25 },
    3438             :   { 122U, AArch64::Z26 },
    3439             :   { 123U, AArch64::Z27 },
    3440             :   { 124U, AArch64::Z28 },
    3441             :   { 125U, AArch64::Z29 },
    3442             :   { 126U, AArch64::Z30 },
    3443             :   { 127U, AArch64::Z31 },
    3444             : };
    3445             : extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
    3446             : 
    3447             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
    3448             :   { AArch64::FFR, 47U },
    3449             :   { AArch64::FP, 29U },
    3450             :   { AArch64::LR, 30U },
    3451             :   { AArch64::SP, 31U },
    3452             :   { AArch64::WSP, 31U },
    3453             :   { AArch64::WZR, 31U },
    3454             :   { AArch64::XZR, 31U },
    3455             :   { AArch64::B0, 64U },
    3456             :   { AArch64::B1, 65U },
    3457             :   { AArch64::B2, 66U },
    3458             :   { AArch64::B3, 67U },
    3459             :   { AArch64::B4, 68U },
    3460             :   { AArch64::B5, 69U },
    3461             :   { AArch64::B6, 70U },
    3462             :   { AArch64::B7, 71U },
    3463             :   { AArch64::B8, 72U },
    3464             :   { AArch64::B9, 73U },
    3465             :   { AArch64::B10, 74U },
    3466             :   { AArch64::B11, 75U },
    3467             :   { AArch64::B12, 76U },
    3468             :   { AArch64::B13, 77U },
    3469             :   { AArch64::B14, 78U },
    3470             :   { AArch64::B15, 79U },
    3471             :   { AArch64::B16, 80U },
    3472             :   { AArch64::B17, 81U },
    3473             :   { AArch64::B18, 82U },
    3474             :   { AArch64::B19, 83U },
    3475             :   { AArch64::B20, 84U },
    3476             :   { AArch64::B21, 85U },
    3477             :   { AArch64::B22, 86U },
    3478             :   { AArch64::B23, 87U },
    3479             :   { AArch64::B24, 88U },
    3480             :   { AArch64::B25, 89U },
    3481             :   { AArch64::B26, 90U },
    3482             :   { AArch64::B27, 91U },
    3483             :   { AArch64::B28, 92U },
    3484             :   { AArch64::B29, 93U },
    3485             :   { AArch64::B30, 94U },
    3486             :   { AArch64::B31, 95U },
    3487             :   { AArch64::D0, 64U },
    3488             :   { AArch64::D1, 65U },
    3489             :   { AArch64::D2, 66U },
    3490             :   { AArch64::D3, 67U },
    3491             :   { AArch64::D4, 68U },
    3492             :   { AArch64::D5, 69U },
    3493             :   { AArch64::D6, 70U },
    3494             :   { AArch64::D7, 71U },
    3495             :   { AArch64::D8, 72U },
    3496             :   { AArch64::D9, 73U },
    3497             :   { AArch64::D10, 74U },
    3498             :   { AArch64::D11, 75U },
    3499             :   { AArch64::D12, 76U },
    3500             :   { AArch64::D13, 77U },
    3501             :   { AArch64::D14, 78U },
    3502             :   { AArch64::D15, 79U },
    3503             :   { AArch64::D16, 80U },
    3504             :   { AArch64::D17, 81U },
    3505             :   { AArch64::D18, 82U },
    3506             :   { AArch64::D19, 83U },
    3507             :   { AArch64::D20, 84U },
    3508             :   { AArch64::D21, 85U },
    3509             :   { AArch64::D22, 86U },
    3510             :   { AArch64::D23, 87U },
    3511             :   { AArch64::D24, 88U },
    3512             :   { AArch64::D25, 89U },
    3513             :   { AArch64::D26, 90U },
    3514             :   { AArch64::D27, 91U },
    3515             :   { AArch64::D28, 92U },
    3516             :   { AArch64::D29, 93U },
    3517             :   { AArch64::D30, 94U },
    3518             :   { AArch64::D31, 95U },
    3519             :   { AArch64::H0, 64U },
    3520             :   { AArch64::H1, 65U },
    3521             :   { AArch64::H2, 66U },
    3522             :   { AArch64::H3, 67U },
    3523             :   { AArch64::H4, 68U },
    3524             :   { AArch64::H5, 69U },
    3525             :   { AArch64::H6, 70U },
    3526             :   { AArch64::H7, 71U },
    3527             :   { AArch64::H8, 72U },
    3528             :   { AArch64::H9, 73U },
    3529             :   { AArch64::H10, 74U },
    3530             :   { AArch64::H11, 75U },
    3531             :   { AArch64::H12, 76U },
    3532             :   { AArch64::H13, 77U },
    3533             :   { AArch64::H14, 78U },
    3534             :   { AArch64::H15, 79U },
    3535             :   { AArch64::H16, 80U },
    3536             :   { AArch64::H17, 81U },
    3537             :   { AArch64::H18, 82U },
    3538             :   { AArch64::H19, 83U },
    3539             :   { AArch64::H20, 84U },
    3540             :   { AArch64::H21, 85U },
    3541             :   { AArch64::H22, 86U },
    3542             :   { AArch64::H23, 87U },
    3543             :   { AArch64::H24, 88U },
    3544             :   { AArch64::H25, 89U },
    3545             :   { AArch64::H26, 90U },
    3546             :   { AArch64::H27, 91U },
    3547             :   { AArch64::H28, 92U },
    3548             :   { AArch64::H29, 93U },
    3549             :   { AArch64::H30, 94U },
    3550             :   { AArch64::H31, 95U },
    3551             :   { AArch64::P0, 48U },
    3552             :   { AArch64::P1, 49U },
    3553             :   { AArch64::P2, 50U },
    3554             :   { AArch64::P3, 51U },
    3555             :   { AArch64::P4, 52U },
    3556             :   { AArch64::P5, 53U },
    3557             :   { AArch64::P6, 54U },
    3558             :   { AArch64::P7, 55U },
    3559             :   { AArch64::P8, 56U },
    3560             :   { AArch64::P9, 57U },
    3561             :   { AArch64::P10, 58U },
    3562             :   { AArch64::P11, 59U },
    3563             :   { AArch64::P12, 60U },
    3564             :   { AArch64::P13, 61U },
    3565             :   { AArch64::P14, 62U },
    3566             :   { AArch64::P15, 63U },
    3567             :   { AArch64::Q0, 64U },
    3568             :   { AArch64::Q1, 65U },
    3569             :   { AArch64::Q2, 66U },
    3570             :   { AArch64::Q3, 67U },
    3571             :   { AArch64::Q4, 68U },
    3572             :   { AArch64::Q5, 69U },
    3573             :   { AArch64::Q6, 70U },
    3574             :   { AArch64::Q7, 71U },
    3575             :   { AArch64::Q8, 72U },
    3576             :   { AArch64::Q9, 73U },
    3577             :   { AArch64::Q10, 74U },
    3578             :   { AArch64::Q11, 75U },
    3579             :   { AArch64::Q12, 76U },
    3580             :   { AArch64::Q13, 77U },
    3581             :   { AArch64::Q14, 78U },
    3582             :   { AArch64::Q15, 79U },
    3583             :   { AArch64::Q16, 80U },
    3584             :   { AArch64::Q17, 81U },
    3585             :   { AArch64::Q18, 82U },
    3586             :   { AArch64::Q19, 83U },
    3587             :   { AArch64::Q20, 84U },
    3588             :   { AArch64::Q21, 85U },
    3589             :   { AArch64::Q22, 86U },
    3590             :   { AArch64::Q23, 87U },
    3591             :   { AArch64::Q24, 88U },
    3592             :   { AArch64::Q25, 89U },
    3593             :   { AArch64::Q26, 90U },
    3594             :   { AArch64::Q27, 91U },
    3595             :   { AArch64::Q28, 92U },
    3596             :   { AArch64::Q29, 93U },
    3597             :   { AArch64::Q30, 94U },
    3598             :   { AArch64::Q31, 95U },
    3599             :   { AArch64::S0, 64U },
    3600             :   { AArch64::S1, 65U },
    3601             :   { AArch64::S2, 66U },
    3602             :   { AArch64::S3, 67U },
    3603             :   { AArch64::S4, 68U },
    3604             :   { AArch64::S5, 69U },
    3605             :   { AArch64::S6, 70U },
    3606             :   { AArch64::S7, 71U },
    3607             :   { AArch64::S8, 72U },
    3608             :   { AArch64::S9, 73U },
    3609             :   { AArch64::S10, 74U },
    3610             :   { AArch64::S11, 75U },
    3611             :   { AArch64::S12, 76U },
    3612             :   { AArch64::S13, 77U },
    3613             :   { AArch64::S14, 78U },
    3614             :   { AArch64::S15, 79U },
    3615             :   { AArch64::S16, 80U },
    3616             :   { AArch64::S17, 81U },
    3617             :   { AArch64::S18, 82U },
    3618             :   { AArch64::S19, 83U },
    3619             :   { AArch64::S20, 84U },
    3620             :   { AArch64::S21, 85U },
    3621             :   { AArch64::S22, 86U },
    3622             :   { AArch64::S23, 87U },
    3623             :   { AArch64::S24, 88U },
    3624             :   { AArch64::S25, 89U },
    3625             :   { AArch64::S26, 90U },
    3626             :   { AArch64::S27, 91U },
    3627             :   { AArch64::S28, 92U },
    3628             :   { AArch64::S29, 93U },
    3629             :   { AArch64::S30, 94U },
    3630             :   { AArch64::S31, 95U },
    3631             :   { AArch64::W0, 0U },
    3632             :   { AArch64::W1, 1U },
    3633             :   { AArch64::W2, 2U },
    3634             :   { AArch64::W3, 3U },
    3635             :   { AArch64::W4, 4U },
    3636             :   { AArch64::W5, 5U },
    3637             :   { AArch64::W6, 6U },
    3638             :   { AArch64::W7, 7U },
    3639             :   { AArch64::W8, 8U },
    3640             :   { AArch64::W9, 9U },
    3641             :   { AArch64::W10, 10U },
    3642             :   { AArch64::W11, 11U },
    3643             :   { AArch64::W12, 12U },
    3644             :   { AArch64::W13, 13U },
    3645             :   { AArch64::W14, 14U },
    3646             :   { AArch64::W15, 15U },
    3647             :   { AArch64::W16, 16U },
    3648             :   { AArch64::W17, 17U },
    3649             :   { AArch64::W18, 18U },
    3650             :   { AArch64::W19, 19U },
    3651             :   { AArch64::W20, 20U },
    3652             :   { AArch64::W21, 21U },
    3653             :   { AArch64::W22, 22U },
    3654             :   { AArch64::W23, 23U },
    3655             :   { AArch64::W24, 24U },
    3656             :   { AArch64::W25, 25U },
    3657             :   { AArch64::W26, 26U },
    3658             :   { AArch64::W27, 27U },
    3659             :   { AArch64::W28, 28U },
    3660             :   { AArch64::W29, 29U },
    3661             :   { AArch64::W30, 30U },
    3662             :   { AArch64::X0, 0U },
    3663             :   { AArch64::X1, 1U },
    3664             :   { AArch64::X2, 2U },
    3665             :   { AArch64::X3, 3U },
    3666             :   { AArch64::X4, 4U },
    3667             :   { AArch64::X5, 5U },
    3668             :   { AArch64::X6, 6U },
    3669             :   { AArch64::X7, 7U },
    3670             :   { AArch64::X8, 8U },
    3671             :   { AArch64::X9, 9U },
    3672             :   { AArch64::X10, 10U },
    3673             :   { AArch64::X11, 11U },
    3674             :   { AArch64::X12, 12U },
    3675             :   { AArch64::X13, 13U },
    3676             :   { AArch64::X14, 14U },
    3677             :   { AArch64::X15, 15U },
    3678             :   { AArch64::X16, 16U },
    3679             :   { AArch64::X17, 17U },
    3680             :   { AArch64::X18, 18U },
    3681             :   { AArch64::X19, 19U },
    3682             :   { AArch64::X20, 20U },
    3683             :   { AArch64::X21, 21U },
    3684             :   { AArch64::X22, 22U },
    3685             :   { AArch64::X23, 23U },
    3686             :   { AArch64::X24, 24U },
    3687             :   { AArch64::X25, 25U },
    3688             :   { AArch64::X26, 26U },
    3689             :   { AArch64::X27, 27U },
    3690             :   { AArch64::X28, 28U },
    3691             :   { AArch64::Z0, 96U },
    3692             :   { AArch64::Z1, 97U },
    3693             :   { AArch64::Z2, 98U },
    3694             :   { AArch64::Z3, 99U },
    3695             :   { AArch64::Z4, 100U },
    3696             :   { AArch64::Z5, 101U },
    3697             :   { AArch64::Z6, 102U },
    3698             :   { AArch64::Z7, 103U },
    3699             :   { AArch64::Z8, 104U },
    3700             :   { AArch64::Z9, 105U },
    3701             :   { AArch64::Z10, 106U },
    3702             :   { AArch64::Z11, 107U },
    3703             :   { AArch64::Z12, 108U },
    3704             :   { AArch64::Z13, 109U },
    3705             :   { AArch64::Z14, 110U },
    3706             :   { AArch64::Z15, 111U },
    3707             :   { AArch64::Z16, 112U },
    3708             :   { AArch64::Z17, 113U },
    3709             :   { AArch64::Z18, 114U },
    3710             :   { AArch64::Z19, 115U },
    3711             :   { AArch64::Z20, 116U },
    3712             :   { AArch64::Z21, 117U },
    3713             :   { AArch64::Z22, 118U },
    3714             :   { AArch64::Z23, 119U },
    3715             :   { AArch64::Z24, 120U },
    3716             :   { AArch64::Z25, 121U },
    3717             :   { AArch64::Z26, 122U },
    3718             :   { AArch64::Z27, 123U },
    3719             :   { AArch64::Z28, 124U },
    3720             :   { AArch64::Z29, 125U },
    3721             :   { AArch64::Z30, 126U },
    3722             :   { AArch64::Z31, 127U },
    3723             : };
    3724             : extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
    3725             : 
    3726             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
    3727             :   { AArch64::FFR, 47U },
    3728             :   { AArch64::FP, 29U },
    3729             :   { AArch64::LR, 30U },
    3730             :   { AArch64::SP, 31U },
    3731             :   { AArch64::WSP, 31U },
    3732             :   { AArch64::WZR, 31U },
    3733             :   { AArch64::XZR, 31U },
    3734             :   { AArch64::B0, 64U },
    3735             :   { AArch64::B1, 65U },
    3736             :   { AArch64::B2, 66U },
    3737             :   { AArch64::B3, 67U },
    3738             :   { AArch64::B4, 68U },
    3739             :   { AArch64::B5, 69U },
    3740             :   { AArch64::B6, 70U },
    3741             :   { AArch64::B7, 71U },
    3742             :   { AArch64::B8, 72U },
    3743             :   { AArch64::B9, 73U },
    3744             :   { AArch64::B10, 74U },
    3745             :   { AArch64::B11, 75U },
    3746             :   { AArch64::B12, 76U },
    3747             :   { AArch64::B13, 77U },
    3748             :   { AArch64::B14, 78U },
    3749             :   { AArch64::B15, 79U },
    3750             :   { AArch64::B16, 80U },
    3751             :   { AArch64::B17, 81U },
    3752             :   { AArch64::B18, 82U },
    3753             :   { AArch64::B19, 83U },
    3754             :   { AArch64::B20, 84U },
    3755             :   { AArch64::B21, 85U },
    3756             :   { AArch64::B22, 86U },
    3757             :   { AArch64::B23, 87U },
    3758             :   { AArch64::B24, 88U },
    3759             :   { AArch64::B25, 89U },
    3760             :   { AArch64::B26, 90U },
    3761             :   { AArch64::B27, 91U },
    3762             :   { AArch64::B28, 92U },
    3763             :   { AArch64::B29, 93U },
    3764             :   { AArch64::B30, 94U },
    3765             :   { AArch64::B31, 95U },
    3766             :   { AArch64::D0, 64U },
    3767             :   { AArch64::D1, 65U },
    3768             :   { AArch64::D2, 66U },
    3769             :   { AArch64::D3, 67U },
    3770             :   { AArch64::D4, 68U },
    3771             :   { AArch64::D5, 69U },
    3772             :   { AArch64::D6, 70U },
    3773             :   { AArch64::D7, 71U },
    3774             :   { AArch64::D8, 72U },
    3775             :   { AArch64::D9, 73U },
    3776             :   { AArch64::D10, 74U },
    3777             :   { AArch64::D11, 75U },
    3778             :   { AArch64::D12, 76U },
    3779             :   { AArch64::D13, 77U },
    3780             :   { AArch64::D14, 78U },
    3781             :   { AArch64::D15, 79U },
    3782             :   { AArch64::D16, 80U },
    3783             :   { AArch64::D17, 81U },
    3784             :   { AArch64::D18, 82U },
    3785             :   { AArch64::D19, 83U },
    3786             :   { AArch64::D20, 84U },
    3787             :   { AArch64::D21, 85U },
    3788             :   { AArch64::D22, 86U },
    3789             :   { AArch64::D23, 87U },
    3790             :   { AArch64::D24, 88U },
    3791             :   { AArch64::D25, 89U },
    3792             :   { AArch64::D26, 90U },
    3793             :   { AArch64::D27, 91U },
    3794             :   { AArch64::D28, 92U },
    3795             :   { AArch64::D29, 93U },
    3796             :   { AArch64::D30, 94U },
    3797             :   { AArch64::D31, 95U },
    3798             :   { AArch64::H0, 64U },
    3799             :   { AArch64::H1, 65U },
    3800             :   { AArch64::H2, 66U },
    3801             :   { AArch64::H3, 67U },
    3802             :   { AArch64::H4, 68U },
    3803             :   { AArch64::H5, 69U },
    3804             :   { AArch64::H6, 70U },
    3805             :   { AArch64::H7, 71U },
    3806             :   { AArch64::H8, 72U },
    3807             :   { AArch64::H9, 73U },
    3808             :   { AArch64::H10, 74U },
    3809             :   { AArch64::H11, 75U },
    3810             :   { AArch64::H12, 76U },
    3811             :   { AArch64::H13, 77U },
    3812             :   { AArch64::H14, 78U },
    3813             :   { AArch64::H15, 79U },
    3814             :   { AArch64::H16, 80U },
    3815             :   { AArch64::H17, 81U },
    3816             :   { AArch64::H18, 82U },
    3817             :   { AArch64::H19, 83U },
    3818             :   { AArch64::H20, 84U },
    3819             :   { AArch64::H21, 85U },
    3820             :   { AArch64::H22, 86U },
    3821             :   { AArch64::H23, 87U },
    3822             :   { AArch64::H24, 88U },
    3823             :   { AArch64::H25, 89U },
    3824             :   { AArch64::H26, 90U },
    3825             :   { AArch64::H27, 91U },
    3826             :   { AArch64::H28, 92U },
    3827             :   { AArch64::H29, 93U },
    3828             :   { AArch64::H30, 94U },
    3829             :   { AArch64::H31, 95U },
    3830             :   { AArch64::P0, 48U },
    3831             :   { AArch64::P1, 49U },
    3832             :   { AArch64::P2, 50U },
    3833             :   { AArch64::P3, 51U },
    3834             :   { AArch64::P4, 52U },
    3835             :   { AArch64::P5, 53U },
    3836             :   { AArch64::P6, 54U },
    3837             :   { AArch64::P7, 55U },
    3838             :   { AArch64::P8, 56U },
    3839             :   { AArch64::P9, 57U },
    3840             :   { AArch64::P10, 58U },
    3841             :   { AArch64::P11, 59U },
    3842             :   { AArch64::P12, 60U },
    3843             :   { AArch64::P13, 61U },
    3844             :   { AArch64::P14, 62U },
    3845             :   { AArch64::P15, 63U },
    3846             :   { AArch64::Q0, 64U },
    3847             :   { AArch64::Q1, 65U },
    3848             :   { AArch64::Q2, 66U },
    3849             :   { AArch64::Q3, 67U },
    3850             :   { AArch64::Q4, 68U },
    3851             :   { AArch64::Q5, 69U },
    3852             :   { AArch64::Q6, 70U },
    3853             :   { AArch64::Q7, 71U },
    3854             :   { AArch64::Q8, 72U },
    3855             :   { AArch64::Q9, 73U },
    3856             :   { AArch64::Q10, 74U },
    3857             :   { AArch64::Q11, 75U },
    3858             :   { AArch64::Q12, 76U },
    3859             :   { AArch64::Q13, 77U },
    3860             :   { AArch64::Q14, 78U },
    3861             :   { AArch64::Q15, 79U },
    3862             :   { AArch64::Q16, 80U },
    3863             :   { AArch64::Q17, 81U },
    3864             :   { AArch64::Q18, 82U },
    3865             :   { AArch64::Q19, 83U },
    3866             :   { AArch64::Q20, 84U },
    3867             :   { AArch64::Q21, 85U },
    3868             :   { AArch64::Q22, 86U },
    3869             :   { AArch64::Q23, 87U },
    3870             :   { AArch64::Q24, 88U },
    3871             :   { AArch64::Q25, 89U },
    3872             :   { AArch64::Q26, 90U },
    3873             :   { AArch64::Q27, 91U },
    3874             :   { AArch64::Q28, 92U },
    3875             :   { AArch64::Q29, 93U },
    3876             :   { AArch64::Q30, 94U },
    3877             :   { AArch64::Q31, 95U },
    3878             :   { AArch64::S0, 64U },
    3879             :   { AArch64::S1, 65U },
    3880             :   { AArch64::S2, 66U },
    3881             :   { AArch64::S3, 67U },
    3882             :   { AArch64::S4, 68U },
    3883             :   { AArch64::S5, 69U },
    3884             :   { AArch64::S6, 70U },
    3885             :   { AArch64::S7, 71U },
    3886             :   { AArch64::S8, 72U },
    3887             :   { AArch64::S9, 73U },
    3888             :   { AArch64::S10, 74U },
    3889             :   { AArch64::S11, 75U },
    3890             :   { AArch64::S12, 76U },
    3891             :   { AArch64::S13, 77U },
    3892             :   { AArch64::S14, 78U },
    3893             :   { AArch64::S15, 79U },
    3894             :   { AArch64::S16, 80U },
    3895             :   { AArch64::S17, 81U },
    3896             :   { AArch64::S18, 82U },
    3897             :   { AArch64::S19, 83U },
    3898             :   { AArch64::S20, 84U },
    3899             :   { AArch64::S21, 85U },
    3900             :   { AArch64::S22, 86U },
    3901             :   { AArch64::S23, 87U },
    3902             :   { AArch64::S24, 88U },
    3903             :   { AArch64::S25, 89U },
    3904             :   { AArch64::S26, 90U },
    3905             :   { AArch64::S27, 91U },
    3906             :   { AArch64::S28, 92U },
    3907             :   { AArch64::S29, 93U },
    3908             :   { AArch64::S30, 94U },
    3909             :   { AArch64::S31, 95U },
    3910             :   { AArch64::W0, 0U },
    3911             :   { AArch64::W1, 1U },
    3912             :   { AArch64::W2, 2U },
    3913             :   { AArch64::W3, 3U },
    3914             :   { AArch64::W4, 4U },
    3915             :   { AArch64::W5, 5U },
    3916             :   { AArch64::W6, 6U },
    3917             :   { AArch64::W7, 7U },
    3918             :   { AArch64::W8, 8U },
    3919             :   { AArch64::W9, 9U },
    3920             :   { AArch64::W10, 10U },
    3921             :   { AArch64::W11, 11U },
    3922             :   { AArch64::W12, 12U },
    3923             :   { AArch64::W13, 13U },
    3924             :   { AArch64::W14, 14U },
    3925             :   { AArch64::W15, 15U },
    3926             :   { AArch64::W16, 16U },
    3927             :   { AArch64::W17, 17U },
    3928             :   { AArch64::W18, 18U },
    3929             :   { AArch64::W19, 19U },
    3930             :   { AArch64::W20, 20U },
    3931             :   { AArch64::W21, 21U },
    3932             :   { AArch64::W22, 22U },
    3933             :   { AArch64::W23, 23U },
    3934             :   { AArch64::W24, 24U },
    3935             :   { AArch64::W25, 25U },
    3936             :   { AArch64::W26, 26U },
    3937             :   { AArch64::W27, 27U },
    3938             :   { AArch64::W28, 28U },
    3939             :   { AArch64::W29, 29U },
    3940             :   { AArch64::W30, 30U },
    3941             :   { AArch64::X0, 0U },
    3942             :   { AArch64::X1, 1U },
    3943             :   { AArch64::X2, 2U },
    3944             :   { AArch64::X3, 3U },
    3945             :   { AArch64::X4, 4U },
    3946             :   { AArch64::X5, 5U },
    3947             :   { AArch64::X6, 6U },
    3948             :   { AArch64::X7, 7U },
    3949             :   { AArch64::X8, 8U },
    3950             :   { AArch64::X9, 9U },
    3951             :   { AArch64::X10, 10U },
    3952             :   { AArch64::X11, 11U },
    3953             :   { AArch64::X12, 12U },
    3954             :   { AArch64::X13, 13U },
    3955             :   { AArch64::X14, 14U },
    3956             :   { AArch64::X15, 15U },
    3957             :   { AArch64::X16, 16U },
    3958             :   { AArch64::X17, 17U },
    3959             :   { AArch64::X18, 18U },
    3960             :   { AArch64::X19, 19U },
    3961             :   { AArch64::X20, 20U },
    3962             :   { AArch64::X21, 21U },
    3963             :   { AArch64::X22, 22U },
    3964             :   { AArch64::X23, 23U },
    3965             :   { AArch64::X24, 24U },
    3966             :   { AArch64::X25, 25U },
    3967             :   { AArch64::X26, 26U },
    3968             :   { AArch64::X27, 27U },
    3969             :   { AArch64::X28, 28U },
    3970             :   { AArch64::Z0, 96U },
    3971             :   { AArch64::Z1, 97U },
    3972             :   { AArch64::Z2, 98U },
    3973             :   { AArch64::Z3, 99U },
    3974             :   { AArch64::Z4, 100U },
    3975             :   { AArch64::Z5, 101U },
    3976             :   { AArch64::Z6, 102U },
    3977             :   { AArch64::Z7, 103U },
    3978             :   { AArch64::Z8, 104U },
    3979             :   { AArch64::Z9, 105U },
    3980             :   { AArch64::Z10, 106U },
    3981             :   { AArch64::Z11, 107U },
    3982             :   { AArch64::Z12, 108U },
    3983             :   { AArch64::Z13, 109U },
    3984             :   { AArch64::Z14, 110U },
    3985             :   { AArch64::Z15, 111U },
    3986             :   { AArch64::Z16, 112U },
    3987             :   { AArch64::Z17, 113U },
    3988             :   { AArch64::Z18, 114U },
    3989             :   { AArch64::Z19, 115U },
    3990             :   { AArch64::Z20, 116U },
    3991             :   { AArch64::Z21, 117U },
    3992             :   { AArch64::Z22, 118U },
    3993             :   { AArch64::Z23, 119U },
    3994             :   { AArch64::Z24, 120U },
    3995             :   { AArch64::Z25, 121U },
    3996             :   { AArch64::Z26, 122U },
    3997             :   { AArch64::Z27, 123U },
    3998             :   { AArch64::Z28, 124U },
    3999             :   { AArch64::Z29, 125U },
    4000             :   { AArch64::Z30, 126U },
    4001             :   { AArch64::Z31, 127U },
    4002             : };
    4003             : extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
    4004             : 
    4005             : extern const uint16_t AArch64RegEncodingTable[] = {
    4006             :   0,
    4007             :   0,
    4008             :   29,
    4009             :   30,
    4010             :   0,
    4011             :   31,
    4012             :   31,
    4013             :   31,
    4014             :   31,
    4015             :   0,
    4016             :   1,
    4017             :   2,
    4018             :   3,
    4019             :   4,
    4020             :   5,
    4021             :   6,
    4022             :   7,
    4023             :   8,
    4024             :   9,
    4025             :   10,
    4026             :   11,
    4027             :   12,
    4028             :   13,
    4029             :   14,
    4030             :   15,
    4031             :   16,
    4032             :   17,
    4033             :   18,
    4034             :   19,
    4035             :   20,
    4036             :   21,
    4037             :   22,
    4038             :   23,
    4039             :   24,
    4040             :   25,
    4041             :   26,
    4042             :   27,
    4043             :   28,
    4044             :   29,
    4045             :   30,
    4046             :   31,
    4047             :   0,
    4048             :   1,
    4049             :   2,
    4050             :   3,
    4051             :   4,
    4052             :   5,
    4053             :   6,
    4054             :   7,
    4055             :   8,
    4056             :   9,
    4057             :   10,
    4058             :   11,
    4059             :   12,
    4060             :   13,
    4061             :   14,
    4062             :   15,
    4063             :   16,
    4064             :   17,
    4065             :   18,
    4066             :   19,
    4067             :   20,
    4068             :   21,
    4069             :   22,
    4070             :   23,
    4071             :   24,
    4072             :   25,
    4073             :   26,
    4074             :   27,
    4075             :   28,
    4076             :   29,
    4077             :   30,
    4078             :   31,
    4079             :   0,
    4080             :   1,
    4081             :   2,
    4082             :   3,
    4083             :   4,
    4084             :   5,
    4085             :   6,
    4086             :   7,
    4087             :   8,
    4088             :   9,
    4089             :   10,
    4090             :   11,
    4091             :   12,
    4092             :   13,
    4093             :   14,
    4094             :   15,
    4095             :   16,
    4096             :   17,
    4097             :   18,
    4098             :   19,
    4099             :   20,
    4100             :   21,
    4101             :   22,
    4102             :   23,
    4103             :   24,
    4104             :   25,
    4105             :   26,
    4106             :   27,
    4107             :   28,
    4108             :   29,
    4109             :   30,
    4110             :   31,
    4111             :   0,
    4112             :   1,
    4113             :   2,
    4114             :   3,
    4115             :   4,
    4116             :   5,
    4117             :   6,
    4118             :   7,
    4119             :   8,
    4120             :   9,
    4121             :   10,
    4122             :   11,
    4123             :   12,
    4124             :   13,
    4125             :   14,
    4126             :   15,
    4127             :   0,
    4128             :   1,
    4129             :   2,
    4130             :   3,
    4131             :   4,
    4132             :   5,
    4133             :   6,
    4134             :   7,
    4135             :   8,
    4136             :   9,
    4137             :   10,
    4138             :   11,
    4139             :   12,
    4140             :   13,
    4141             :   14,
    4142             :   15,
    4143             :   16,
    4144             :   17,
    4145             :   18,
    4146             :   19,
    4147             :   20,
    4148             :   21,
    4149             :   22,
    4150             :   23,
    4151             :   24,
    4152             :   25,
    4153             :   26,
    4154             :   27,
    4155             :   28,
    4156             :   29,
    4157             :   30,
    4158             :   31,
    4159             :   0,
    4160             :   1,
    4161             :   2,
    4162             :   3,
    4163             :   4,
    4164             :   5,
    4165             :   6,
    4166             :   7,
    4167             :   8,
    4168             :   9,
    4169             :   10,
    4170             :   11,
    4171             :   12,
    4172             :   13,
    4173             :   14,
    4174             :   15,
    4175             :   16,
    4176             :   17,
    4177             :   18,
    4178             :   19,
    4179             :   20,
    4180             :   21,
    4181             :   22,
    4182             :   23,
    4183             :   24,
    4184             :   25,
    4185             :   26,
    4186             :   27,
    4187             :   28,
    4188             :   29,
    4189             :   30,
    4190             :   31,
    4191             :   0,
    4192             :   1,
    4193             :   2,
    4194             :   3,
    4195             :   4,
    4196             :   5,
    4197             :   6,
    4198             :   7,
    4199             :   8,
    4200             :   9,
    4201             :   10,
    4202             :   11,
    4203             :   12,
    4204             :   13,
    4205             :   14,
    4206             :   15,
    4207             :   16,
    4208             :   17,
    4209             :   18,
    4210             :   19,
    4211             :   20,
    4212             :   21,
    4213             :   22,
    4214             :   23,
    4215             :   24,
    4216             :   25,
    4217             :   26,
    4218             :   27,
    4219             :   28,
    4220             :   29,
    4221             :   30,
    4222             :   0,
    4223             :   1,
    4224             :   2,
    4225             :   3,
    4226             :   4,
    4227             :   5,
    4228             :   6,
    4229             :   7,
    4230             :   8,
    4231             :   9,
    4232             :   10,
    4233             :   11,
    4234             :   12,
    4235             :   13,
    4236             :   14,
    4237             :   15,
    4238             :   16,
    4239             :   17,
    4240             :   18,
    4241             :   19,
    4242             :   20,
    4243             :   21,
    4244             :   22,
    4245             :   23,
    4246             :   24,
    4247             :   25,
    4248             :   26,
    4249             :   27,
    4250             :   28,
    4251             :   0,
    4252             :   1,
    4253             :   2,
    4254             :   3,
    4255             :   4,
    4256             :   5,
    4257             :   6,
    4258             :   7,
    4259             :   8,
    4260             :   9,
    4261             :   10,
    4262             :   11,
    4263             :   12,
    4264             :   13,
    4265             :   14,
    4266             :   15,
    4267             :   16,
    4268             :   17,
    4269             :   18,
    4270             :   19,
    4271             :   20,
    4272             :   21,
    4273             :   22,
    4274             :   23,
    4275             :   24,
    4276             :   25,
    4277             :   26,
    4278             :   27,
    4279             :   28,
    4280             :   29,
    4281             :   30,
    4282             :   31,
    4283             :   0,
    4284             :   1,
    4285             :   2,
    4286             :   3,
    4287             :   4,
    4288             :   5,
    4289             :   6,
    4290             :   7,
    4291             :   8,
    4292             :   9,
    4293             :   10,
    4294             :   11,
    4295             :   12,
    4296             :   13,
    4297             :   14,
    4298             :   15,
    4299             :   16,
    4300             :   17,
    4301             :   18,
    4302             :   19,
    4303             :   20,
    4304             :   21,
    4305             :   22,
    4306             :   23,
    4307             :   24,
    4308             :   25,
    4309             :   26,
    4310             :   27,
    4311             :   28,
    4312             :   29,
    4313             :   30,
    4314             :   31,
    4315             :   0,
    4316             :   1,
    4317             :   2,
    4318             :   3,
    4319             :   4,
    4320             :   5,
    4321             :   6,
    4322             :   7,
    4323             :   8,
    4324             :   9,
    4325             :   10,
    4326             :   11,
    4327             :   12,
    4328             :   13,
    4329             :   14,
    4330             :   15,
    4331             :   16,
    4332             :   17,
    4333             :   18,
    4334             :   19,
    4335             :   20,
    4336             :   21,
    4337             :   22,
    4338             :   23,
    4339             :   24,
    4340             :   25,
    4341             :   26,
    4342             :   27,
    4343             :   28,
    4344             :   29,
    4345             :   30,
    4346             :   31,
    4347             :   0,
    4348             :   1,
    4349             :   2,
    4350             :   3,
    4351             :   4,
    4352             :   5,
    4353             :   6,
    4354             :   7,
    4355             :   8,
    4356             :   9,
    4357             :   10,
    4358             :   11,
    4359             :   12,
    4360             :   13,
    4361             :   14,
    4362             :   15,
    4363             :   16,
    4364             :   17,
    4365             :   18,
    4366             :   19,
    4367             :   20,
    4368             :   21,
    4369             :   22,
    4370             :   23,
    4371             :   24,
    4372             :   25,
    4373             :   26,
    4374             :   27,
    4375             :   28,
    4376             :   29,
    4377             :   30,
    4378             :   31,
    4379             :   0,
    4380             :   1,
    4381             :   2,
    4382             :   3,
    4383             :   4,
    4384             :   5,
    4385             :   6,
    4386             :   7,
    4387             :   8,
    4388             :   9,
    4389             :   10,
    4390             :   11,
    4391             :   12,
    4392             :   13,
    4393             :   14,
    4394             :   15,
    4395             :   16,
    4396             :   17,
    4397             :   18,
    4398             :   19,
    4399             :   20,
    4400             :   21,
    4401             :   22,
    4402             :   23,
    4403             :   24,
    4404             :   25,
    4405             :   26,
    4406             :   27,
    4407             :   28,
    4408             :   29,
    4409             :   30,
    4410             :   31,
    4411             :   0,
    4412             :   1,
    4413             :   2,
    4414             :   3,
    4415             :   4,
    4416             :   5,
    4417             :   6,
    4418             :   7,
    4419             :   8,
    4420             :   9,
    4421             :   10,
    4422             :   11,
    4423             :   12,
    4424             :   13,
    4425             :   14,
    4426             :   15,
    4427             :   16,
    4428             :   17,
    4429             :   18,
    4430             :   19,
    4431             :   20,
    4432             :   21,
    4433             :   22,
    4434             :   23,
    4435             :   24,
    4436             :   25,
    4437             :   26,
    4438             :   27,
    4439             :   28,
    4440             :   29,
    4441             :   30,
    4442             :   31,
    4443             :   0,
    4444             :   1,
    4445             :   2,
    4446             :   3,
    4447             :   4,
    4448             :   5,
    4449             :   6,
    4450             :   7,
    4451             :   8,
    4452             :   9,
    4453             :   10,
    4454             :   11,
    4455             :   12,
    4456             :   13,
    4457             :   14,
    4458             :   15,
    4459             :   16,
    4460             :   17,
    4461             :   18,
    4462             :   19,
    4463             :   20,
    4464             :   21,
    4465             :   22,
    4466             :   23,
    4467             :   24,
    4468             :   25,
    4469             :   26,
    4470             :   27,
    4471             :   28,
    4472             :   29,
    4473             :   30,
    4474             :   31,
    4475             :   0,
    4476             :   1,
    4477             :   2,
    4478             :   3,
    4479             :   4,
    4480             :   5,
    4481             :   6,
    4482             :   7,
    4483             :   8,
    4484             :   9,
    4485             :   10,
    4486             :   11,
    4487             :   12,
    4488             :   13,
    4489             :   14,
    4490             :   15,
    4491             :   16,
    4492             :   17,
    4493             :   18,
    4494             :   19,
    4495             :   20,
    4496             :   21,
    4497             :   22,
    4498             :   23,
    4499             :   24,
    4500             :   25,
    4501             :   26,
    4502             :   27,
    4503             :   28,
    4504             :   29,
    4505             :   30,
    4506             :   31,
    4507             :   31,
    4508             :   30,
    4509             :   0,
    4510             :   1,
    4511             :   2,
    4512             :   3,
    4513             :   4,
    4514             :   5,
    4515             :   6,
    4516             :   7,
    4517             :   8,
    4518             :   9,
    4519             :   10,
    4520             :   11,
    4521             :   12,
    4522             :   13,
    4523             :   14,
    4524             :   15,
    4525             :   16,
    4526             :   17,
    4527             :   18,
    4528             :   19,
    4529             :   20,
    4530             :   21,
    4531             :   22,
    4532             :   23,
    4533             :   24,
    4534             :   25,
    4535             :   26,
    4536             :   27,
    4537             :   28,
    4538             :   29,
    4539             :   29,
    4540             :   30,
    4541             :   31,
    4542             :   28,
    4543             :   0,
    4544             :   1,
    4545             :   2,
    4546             :   3,
    4547             :   4,
    4548             :   5,
    4549             :   6,
    4550             :   7,
    4551             :   8,
    4552             :   9,
    4553             :   10,
    4554             :   11,
    4555             :   12,
    4556             :   13,
    4557             :   14,
    4558             :   15,
    4559             :   16,
    4560             :   17,
    4561             :   18,
    4562             :   19,
    4563             :   20,
    4564             :   21,
    4565             :   22,
    4566             :   23,
    4567             :   24,
    4568             :   25,
    4569             :   26,
    4570             :   27,
    4571             :   0,
    4572             :   1,
    4573             :   2,
    4574             :   3,
    4575             :   4,
    4576             :   5,
    4577             :   6,
    4578             :   7,
    4579             :   8,
    4580             :   9,
    4581             :   10,
    4582             :   11,
    4583             :   12,
    4584             :   13,
    4585             :   14,
    4586             :   15,
    4587             :   16,
    4588             :   17,
    4589             :   18,
    4590             :   19,
    4591             :   20,
    4592             :   21,
    4593             :   22,
    4594             :   23,
    4595             :   24,
    4596             :   25,
    4597             :   26,
    4598             :   27,
    4599             :   28,
    4600             :   29,
    4601             :   30,
    4602             :   31,
    4603             :   0,
    4604             :   1,
    4605             :   2,
    4606             :   3,
    4607             :   4,
    4608             :   5,
    4609             :   6,
    4610             :   7,
    4611             :   8,
    4612             :   9,
    4613             :   10,
    4614             :   11,
    4615             :   12,
    4616             :   13,
    4617             :   14,
    4618             :   15,
    4619             :   16,
    4620             :   17,
    4621             :   18,
    4622             :   19,
    4623             :   20,
    4624             :   21,
    4625             :   22,
    4626             :   23,
    4627             :   24,
    4628             :   25,
    4629             :   26,
    4630             :   27,
    4631             :   28,
    4632             :   29,
    4633             :   30,
    4634             :   31,
    4635             :   0,
    4636             :   1,
    4637             :   2,
    4638             :   3,
    4639             :   4,
    4640             :   5,
    4641             :   6,
    4642             :   7,
    4643             :   8,
    4644             :   9,
    4645             :   10,
    4646             :   11,
    4647             :   12,
    4648             :   13,
    4649             :   14,
    4650             :   15,
    4651             :   16,
    4652             :   17,
    4653             :   18,
    4654             :   19,
    4655             :   20,
    4656             :   21,
    4657             :   22,
    4658             :   23,
    4659             :   24,
    4660             :   25,
    4661             :   26,
    4662             :   27,
    4663             :   28,
    4664             :   29,
    4665             :   30,
    4666             :   31,
    4667             : };
    4668             : static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
    4669             :   RI->InitMCRegisterInfo(AArch64RegDesc, 661, RA, PC, AArch64MCRegisterClasses, 80, AArch64RegUnitRoots, 115, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 100,
    4670             : AArch64SubRegIdxRanges, AArch64RegEncodingTable);
    4671             : 
    4672             :   switch (DwarfFlavour) {
    4673             :   default:
    4674             :     llvm_unreachable("Unknown DWARF flavour");
    4675             :   case 0:
    4676             :     RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
    4677             :     break;
    4678             :   }
    4679             :   switch (EHFlavour) {
    4680             :   default:
    4681             :     llvm_unreachable("Unknown DWARF flavour");
    4682             :   case 0:
    4683             :     RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
    4684             :     break;
    4685             :   }
    4686             :   switch (DwarfFlavour) {
    4687             :   default:
    4688             :     llvm_unreachable("Unknown DWARF flavour");
    4689             :   case 0:
    4690             :     RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
    4691             :     break;
    4692             :   }
    4693             :   switch (EHFlavour) {
    4694             :   default:
    4695             :     llvm_unreachable("Unknown DWARF flavour");
    4696             :   case 0:
    4697             :     RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
    4698             :     break;
    4699             :   }
    4700             : }
    4701             : 
    4702             : } // end namespace llvm
    4703             : 
    4704             : #endif // GET_REGINFO_MC_DESC
    4705             : 
    4706             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    4707             : |*                                                                            *|
    4708             : |* Register Information Header Fragment                                       *|
    4709             : |*                                                                            *|
    4710             : |* Automatically generated file, do not edit!                                 *|
    4711             : |*                                                                            *|
    4712             : \*===----------------------------------------------------------------------===*/
    4713             : 
    4714             : 
    4715             : #ifdef GET_REGINFO_HEADER
    4716             : #undef GET_REGINFO_HEADER
    4717             : 
    4718             : #include "llvm/CodeGen/TargetRegisterInfo.h"
    4719             : 
    4720             : namespace llvm {
    4721             : 
    4722             : class AArch64FrameLowering;
    4723             : 
    4724        1391 : struct AArch64GenRegisterInfo : public TargetRegisterInfo {
    4725             :   explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
    4726             :       unsigned PC = 0, unsigned HwMode = 0);
    4727             :   unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
    4728             :   LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    4729             :   LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    4730             :   const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
    4731             :   const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
    4732             :   unsigned getRegUnitWeight(unsigned RegUnit) const override;
    4733             :   unsigned getNumRegPressureSets() const override;
    4734             :   const char *getRegPressureSetName(unsigned Idx) const override;
    4735             :   unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
    4736             :   const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
    4737             :   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
    4738             :   ArrayRef<const char *> getRegMaskNames() const override;
    4739             :   ArrayRef<const uint32_t *> getRegMasks() const override;
    4740             :   /// Devirtualized TargetFrameLowering.
    4741             :   static const AArch64FrameLowering *getFrameLowering(
    4742             :       const MachineFunction &MF);
    4743             : };
    4744             : 
    4745             : namespace AArch64 { // Register classes
    4746             :   extern const TargetRegisterClass FPR8RegClass;
    4747             :   extern const TargetRegisterClass FPR16RegClass;
    4748             :   extern const TargetRegisterClass PPRRegClass;
    4749             :   extern const TargetRegisterClass PPR_3bRegClass;
    4750             :   extern const TargetRegisterClass GPR32allRegClass;
    4751             :   extern const TargetRegisterClass FPR32RegClass;
    4752             :   extern const TargetRegisterClass GPR32RegClass;
    4753             :   extern const TargetRegisterClass GPR32spRegClass;
    4754             :   extern const TargetRegisterClass GPR32commonRegClass;
    4755             :   extern const TargetRegisterClass CCRRegClass;
    4756             :   extern const TargetRegisterClass GPR32sponlyRegClass;
    4757             :   extern const TargetRegisterClass WSeqPairsClassRegClass;
    4758             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass;
    4759             :   extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
    4760             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
    4761             :   extern const TargetRegisterClass GPR64allRegClass;
    4762             :   extern const TargetRegisterClass FPR64RegClass;
    4763             :   extern const TargetRegisterClass GPR64RegClass;
    4764             :   extern const TargetRegisterClass GPR64spRegClass;
    4765             :   extern const TargetRegisterClass GPR64commonRegClass;
    4766             :   extern const TargetRegisterClass tcGPR64RegClass;
    4767             :   extern const TargetRegisterClass GPR64sponlyRegClass;
    4768             :   extern const TargetRegisterClass DDRegClass;
    4769             :   extern const TargetRegisterClass XSeqPairsClassRegClass;
    4770             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass;
    4771             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
    4772             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
    4773             :   extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
    4774             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
    4775             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
    4776             :   extern const TargetRegisterClass FPR128RegClass;
    4777             :   extern const TargetRegisterClass ZPRRegClass;
    4778             :   extern const TargetRegisterClass FPR128_loRegClass;
    4779             :   extern const TargetRegisterClass ZPR_with_zsub_in_FPR128_loRegClass;
    4780             :   extern const TargetRegisterClass DDDRegClass;
    4781             :   extern const TargetRegisterClass DDDDRegClass;
    4782             :   extern const TargetRegisterClass QQRegClass;
    4783             :   extern const TargetRegisterClass ZPR2RegClass;
    4784             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
    4785             :   extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;
    4786             :   extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4787             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass;
    4788             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass;
    4789             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4790             :   extern const TargetRegisterClass QQQRegClass;
    4791             :   extern const TargetRegisterClass ZPR3RegClass;
    4792             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass;
    4793             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass;
    4794             :   extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass;
    4795             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4796             :   extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4797             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass;
    4798             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass;
    4799             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
    4800             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4801             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4802             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
    4803             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4804             :   extern const TargetRegisterClass QQQQRegClass;
    4805             :   extern const TargetRegisterClass ZPR4RegClass;
    4806             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass;
    4807             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass;
    4808             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass;
    4809             :   extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass;
    4810             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4811             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4812             :   extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4813             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass;
    4814             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass;
    4815             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
    4816             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    4817             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4818             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4819             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4820             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
    4821             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    4822             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4823             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4824             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    4825             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass;
    4826             : } // end namespace AArch64
    4827             : 
    4828             : } // end namespace llvm
    4829             : 
    4830             : #endif // GET_REGINFO_HEADER
    4831             : 
    4832             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    4833             : |*                                                                            *|
    4834             : |* Target Register and Register Classes Information                           *|
    4835             : |*                                                                            *|
    4836             : |* Automatically generated file, do not edit!                                 *|
    4837             : |*                                                                            *|
    4838             : \*===----------------------------------------------------------------------===*/
    4839             : 
    4840             : 
    4841             : #ifdef GET_REGINFO_TARGET_DESC
    4842             : #undef GET_REGINFO_TARGET_DESC
    4843             : 
    4844             : namespace llvm {
    4845             : 
    4846             : extern const MCRegisterClass AArch64MCRegisterClasses[];
    4847             : 
    4848             : static const MVT::SimpleValueType VTLists[] = {
    4849             :   /* 0 */ MVT::f32, MVT::i32, MVT::Other,
    4850             :   /* 3 */ MVT::i64, MVT::Other,
    4851             :   /* 5 */ MVT::f16, MVT::Other,
    4852             :   /* 7 */ MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::Other,
    4853             :   /* 12 */ MVT::f64, MVT::i64, MVT::v2f32, MVT::v1f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v4f16, MVT::Other,
    4854             :   /* 22 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::v8f16, MVT::Other,
    4855             :   /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
    4856             :   /* 39 */ MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64, MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv1f32, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv1f64, MVT::nxv2f64, MVT::Other,
    4857             :   /* 52 */ MVT::Untyped, MVT::Other,
    4858             : };
    4859             : 
    4860             : static const char *const SubRegIndexNameTable[] = { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1", "qsub2", "qsub3", "ssub", "sub_32", "sube32", "sube64", "subo32", "subo64", "zsub", "zsub0", "zsub1", "zsub2", "zsub3", "zsub_hi", "dsub1_then_bsub", "dsub1_then_hsub", "dsub1_then_ssub", "dsub3_then_bsub", "dsub3_then_hsub", "dsub3_then_ssub", "dsub2_then_bsub", "dsub2_then_hsub", "dsub2_then_ssub", "qsub1_then_bsub", "qsub1_then_dsub", "qsub1_then_hsub", "qsub1_then_ssub", "qsub3_then_bsub", "qsub3_then_dsub", "qsub3_then_hsub", "qsub3_then_ssub", "qsub2_then_bsub", "qsub2_then_dsub", "qsub2_then_hsub", "qsub2_then_ssub", "subo64_then_sub_32", "zsub1_then_bsub", "zsub1_then_dsub", "zsub1_then_hsub", "zsub1_then_ssub", "zsub1_then_zsub", "zsub1_then_zsub_hi", "zsub3_then_bsub", "zsub3_then_dsub", "zsub3_then_hsub", "zsub3_then_ssub", "zsub3_then_zsub", "zsub3_then_zsub_hi", "zsub2_then_bsub", "zsub2_then_dsub", "zsub2_then_hsub", "zsub2_then_ssub", "zsub2_then_zsub", "zsub2_then_zsub_hi", "dsub0_dsub1", "dsub0_dsub1_dsub2", "dsub1_dsub2", "dsub1_dsub2_dsub3", "dsub2_dsub3", "dsub_qsub1_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub", "qsub0_qsub1", "qsub0_qsub1_qsub2", "qsub1_qsub2", "qsub1_qsub2_qsub3", "qsub2_qsub3", "qsub1_then_dsub_qsub2_then_dsub", "qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "qsub2_then_dsub_qsub3_then_dsub", "sub_32_subo64_then_sub_32", "dsub_zsub1_then_dsub", "zsub_zsub1_then_zsub", "dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub", "dsub_zsub1_then_dsub_zsub2_then_dsub", "zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub", "zsub_zsub1_then_zsub_zsub2_then_zsub", "zsub0_zsub1", "zsub0_zsub1_zsub2", "zsub1_zsub2", "zsub1_zsub2_zsub3", "zsub2_zsub3", "zsub1_then_dsub_zsub2_then_dsub", "zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub", "zsub1_then_zsub_zsub2_then_zsub", "zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub", "zsub2_then_dsub_zsub3_then_dsub", "zsub2_then_zsub_zsub3_then_zsub", "" };
    4861             : 
    4862             : 
    4863             : static const LaneBitmask SubRegIndexLaneMaskTable[] = {
    4864             :   LaneBitmask::getAll(),
    4865             :   LaneBitmask(0x00000001), // bsub
    4866             :   LaneBitmask(0x00000001), // dsub
    4867             :   LaneBitmask(0x00000001), // dsub0
    4868             :   LaneBitmask(0x00000080), // dsub1
    4869             :   LaneBitmask(0x00000200), // dsub2
    4870             :   LaneBitmask(0x00000100), // dsub3
    4871             :   LaneBitmask(0x00000001), // hsub
    4872             :   LaneBitmask(0x00000002), // qhisub
    4873             :   LaneBitmask(0x00000004), // qsub
    4874             :   LaneBitmask(0x00000001), // qsub0
    4875             :   LaneBitmask(0x00000400), // qsub1
    4876             :   LaneBitmask(0x00001000), // qsub2
    4877             :   LaneBitmask(0x00000800), // qsub3
    4878             :   LaneBitmask(0x00000001), // ssub
    4879             :   LaneBitmask(0x00000008), // sub_32
    4880             :   LaneBitmask(0x00000010), // sube32
    4881             :   LaneBitmask(0x00000008), // sube64
    4882             :   LaneBitmask(0x00000020), // subo32
    4883             :   LaneBitmask(0x00002000), // subo64
    4884             :   LaneBitmask(0x00000001), // zsub
    4885             :   LaneBitmask(0x00000041), // zsub0
    4886             :   LaneBitmask(0x0000C000), // zsub1
    4887             :   LaneBitmask(0x000C0000), // zsub2
    4888             :   LaneBitmask(0x00030000), // zsub3
    4889             :   LaneBitmask(0x00000040), // zsub_hi
    4890             :   LaneBitmask(0x00000080), // dsub1_then_bsub
    4891             :   LaneBitmask(0x00000080), // dsub1_then_hsub
    4892             :   LaneBitmask(0x00000080), // dsub1_then_ssub
    4893             :   LaneBitmask(0x00000100), // dsub3_then_bsub
    4894             :   LaneBitmask(0x00000100), // dsub3_then_hsub
    4895             :   LaneBitmask(0x00000100), // dsub3_then_ssub
    4896             :   LaneBitmask(0x00000200), // dsub2_then_bsub
    4897             :   LaneBitmask(0x00000200), // dsub2_then_hsub
    4898             :   LaneBitmask(0x00000200), // dsub2_then_ssub
    4899             :   LaneBitmask(0x00000400), // qsub1_then_bsub
    4900             :   LaneBitmask(0x00000400), // qsub1_then_dsub
    4901             :   LaneBitmask(0x00000400), // qsub1_then_hsub
    4902             :   LaneBitmask(0x00000400), // qsub1_then_ssub
    4903             :   LaneBitmask(0x00000800), // qsub3_then_bsub
    4904             :   LaneBitmask(0x00000800), // qsub3_then_dsub
    4905             :   LaneBitmask(0x00000800), // qsub3_then_hsub
    4906             :   LaneBitmask(0x00000800), // qsub3_then_ssub
    4907             :   LaneBitmask(0x00001000), // qsub2_then_bsub
    4908             :   LaneBitmask(0x00001000), // qsub2_then_dsub
    4909             :   LaneBitmask(0x00001000), // qsub2_then_hsub
    4910             :   LaneBitmask(0x00001000), // qsub2_then_ssub
    4911             :   LaneBitmask(0x00002000), // subo64_then_sub_32
    4912             :   LaneBitmask(0x00004000), // zsub1_then_bsub
    4913             :   LaneBitmask(0x00004000), // zsub1_then_dsub
    4914             :   LaneBitmask(0x00004000), // zsub1_then_hsub
    4915             :   LaneBitmask(0x00004000), // zsub1_then_ssub
    4916             :   LaneBitmask(0x00004000), // zsub1_then_zsub
    4917             :   LaneBitmask(0x00008000), // zsub1_then_zsub_hi
    4918             :   LaneBitmask(0x00010000), // zsub3_then_bsub
    4919             :   LaneBitmask(0x00010000), // zsub3_then_dsub
    4920             :   LaneBitmask(0x00010000), // zsub3_then_hsub
    4921             :   LaneBitmask(0x00010000), // zsub3_then_ssub
    4922             :   LaneBitmask(0x00010000), // zsub3_then_zsub
    4923             :   LaneBitmask(0x00020000), // zsub3_then_zsub_hi
    4924             :   LaneBitmask(0x00040000), // zsub2_then_bsub
    4925             :   LaneBitmask(0x00040000), // zsub2_then_dsub
    4926             :   LaneBitmask(0x00040000), // zsub2_then_hsub
    4927             :   LaneBitmask(0x00040000), // zsub2_then_ssub
    4928             :   LaneBitmask(0x00040000), // zsub2_then_zsub
    4929             :   LaneBitmask(0x00080000), // zsub2_then_zsub_hi
    4930             :   LaneBitmask(0x00000081), // dsub0_dsub1
    4931             :   LaneBitmask(0x00000281), // dsub0_dsub1_dsub2
    4932             :   LaneBitmask(0x00000280), // dsub1_dsub2
    4933             :   LaneBitmask(0x00000380), // dsub1_dsub2_dsub3
    4934             :   LaneBitmask(0x00000300), // dsub2_dsub3
    4935             :   LaneBitmask(0x00000401), // dsub_qsub1_then_dsub
    4936             :   LaneBitmask(0x00001C01), // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    4937             :   LaneBitmask(0x00001401), // dsub_qsub1_then_dsub_qsub2_then_dsub
    4938             :   LaneBitmask(0x00000401), // qsub0_qsub1
    4939             :   LaneBitmask(0x00001401), // qsub0_qsub1_qsub2
    4940             :   LaneBitmask(0x00001400), // qsub1_qsub2
    4941             :   LaneBitmask(0x00001C00), // qsub1_qsub2_qsub3
    4942             :   LaneBitmask(0x00001800), // qsub2_qsub3
    4943             :   LaneBitmask(0x00001400), // qsub1_then_dsub_qsub2_then_dsub
    4944             :   LaneBitmask(0x00001C00), // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    4945             :   LaneBitmask(0x00001800), // qsub2_then_dsub_qsub3_then_dsub
    4946             :   LaneBitmask(0x00002008), // sub_32_subo64_then_sub_32
    4947             :   LaneBitmask(0x00004001), // dsub_zsub1_then_dsub
    4948             :   LaneBitmask(0x00004001), // zsub_zsub1_then_zsub
    4949             :   LaneBitmask(0x00054001), // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    4950             :   LaneBitmask(0x00044001), // dsub_zsub1_then_dsub_zsub2_then_dsub
    4951             :   LaneBitmask(0x00054001), // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    4952             :   LaneBitmask(0x00044001), // zsub_zsub1_then_zsub_zsub2_then_zsub
    4953             :   LaneBitmask(0x0000C041), // zsub0_zsub1
    4954             :   LaneBitmask(0x000CC041), // zsub0_zsub1_zsub2
    4955             :   LaneBitmask(0x000CC000), // zsub1_zsub2
    4956             :   LaneBitmask(0x000FC000), // zsub1_zsub2_zsub3
    4957             :   LaneBitmask(0x000F0000), // zsub2_zsub3
    4958             :   LaneBitmask(0x00044000), // zsub1_then_dsub_zsub2_then_dsub
    4959             :   LaneBitmask(0x00054000), // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    4960             :   LaneBitmask(0x00044000), // zsub1_then_zsub_zsub2_then_zsub
    4961             :   LaneBitmask(0x00054000), // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    4962             :   LaneBitmask(0x00050000), // zsub2_then_dsub_zsub3_then_dsub
    4963             :   LaneBitmask(0x00050000), // zsub2_then_zsub_zsub3_then_zsub
    4964             :  };
    4965             : 
    4966             : 
    4967             : 
    4968             : static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
    4969             :   // Mode = 0 (Default)
    4970             :   { 8, 8, 8, VTLists+52 },    // FPR8
    4971             :   { 16, 16, 16, VTLists+5 },    // FPR16
    4972             :   { 16, 16, 16, VTLists+7 },    // PPR
    4973             :   { 16, 16, 16, VTLists+7 },    // PPR_3b
    4974             :   { 32, 32, 32, VTLists+1 },    // GPR32all
    4975             :   { 32, 32, 32, VTLists+0 },    // FPR32
    4976             :   { 32, 32, 32, VTLists+1 },    // GPR32
    4977             :   { 32, 32, 32, VTLists+1 },    // GPR32sp
    4978             :   { 32, 32, 32, VTLists+1 },    // GPR32common
    4979             :   { 32, 32, 32, VTLists+1 },    // CCR
    4980             :   { 32, 32, 32, VTLists+1 },    // GPR32sponly
    4981             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass
    4982             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_sube32_in_GPR32common
    4983             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_subo32_in_GPR32common
    4984             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    4985             :   { 64, 64, 64, VTLists+3 },    // GPR64all
    4986             :   { 64, 64, 64, VTLists+12 },    // FPR64
    4987             :   { 64, 64, 64, VTLists+3 },    // GPR64
    4988             :   { 64, 64, 64, VTLists+3 },    // GPR64sp
    4989             :   { 64, 64, 64, VTLists+3 },    // GPR64common
    4990             :   { 64, 64, 64, VTLists+3 },    // tcGPR64
    4991             :   { 64, 64, 64, VTLists+3 },    // GPR64sponly
    4992             :   { 128, 128, 64, VTLists+52 },    // DD
    4993             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass
    4994             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common
    4995             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_GPR64common
    4996             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    4997             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sube64_in_tcGPR64
    4998             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_tcGPR64
    4999             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    5000             :   { 128, 128, 128, VTLists+22 },    // FPR128
    5001             :   { 128, 128, 128, VTLists+39 },    // ZPR
    5002             :   { 128, 128, 128, VTLists+31 },    // FPR128_lo
    5003             :   { 128, 128, 128, VTLists+39 },    // ZPR_with_zsub_in_FPR128_lo
    5004             :   { 192, 192, 64, VTLists+52 },    // DDD
    5005             :   { 256, 256, 64, VTLists+52 },    // DDDD
    5006             :   { 256, 256, 128, VTLists+52 },    // QQ
    5007             :   { 256, 256, 128, VTLists+52 },    // ZPR2
    5008             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub0_in_FPR128_lo
    5009             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub1_in_FPR128_lo
    5010             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo
    5011             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub_in_FPR128_lo
    5012             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    5013             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo
    5014             :   { 384, 384, 128, VTLists+52 },    // QQQ
    5015             :   { 384, 384, 128, VTLists+52 },    // ZPR3
    5016             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo
    5017             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub1_in_FPR128_lo
    5018             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub2_in_FPR128_lo
    5019             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo
    5020             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo
    5021             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo
    5022             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    5023             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    5024             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo
    5025             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo
    5026             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    5027             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo
    5028             :   { 512, 512, 128, VTLists+52 },    // QQQQ
    5029             :   { 512, 512, 128, VTLists+52 },    // ZPR4
    5030             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo
    5031             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo
    5032             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub2_in_FPR128_lo
    5033             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub3_in_FPR128_lo
    5034             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo
    5035             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo
    5036             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo
    5037             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo
    5038             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    5039             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    5040             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    5041             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo
    5042             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo
    5043             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo
    5044             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    5045             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    5046             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo
    5047             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo
    5048             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    5049             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_lo
    5050             : };
    5051             : 
    5052             : static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
    5053             : 
    5054             : static const uint32_t FPR8SubClassMask[] = {
    5055             :   0x00000001, 0x00000000, 0x00000000, 
    5056             :   0xc0410022, 0xffffffff, 0x0000ffff, // bsub
    5057             :   0x00400000, 0x0000000c, 0x00000000, // dsub1_then_bsub
    5058             :   0x00000000, 0x00000008, 0x00000000, // dsub3_then_bsub
    5059             :   0x00000000, 0x0000000c, 0x00000000, // dsub2_then_bsub
    5060             :   0x00000000, 0xf531d4d0, 0x00004c70, // qsub1_then_bsub
    5061             :   0x00000000, 0xf4000000, 0x00004c70, // qsub3_then_bsub
    5062             :   0x00000000, 0xf531d000, 0x00004c70, // qsub2_then_bsub
    5063             :   0x00000000, 0x0ace2b20, 0x0000b38f, // zsub1_then_bsub
    5064             :   0x00000000, 0x08000000, 0x0000b38f, // zsub3_then_bsub
    5065             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub2_then_bsub
    5066             : };
    5067             : 
    5068             : static const uint32_t FPR16SubClassMask[] = {
    5069             :   0x00000002, 0x00000000, 0x00000000, 
    5070             :   0xc0410020, 0xffffffff, 0x0000ffff, // hsub
    5071             :   0x00400000, 0x0000000c, 0x00000000, // dsub1_then_hsub
    5072             :   0x00000000, 0x00000008, 0x00000000, // dsub3_then_hsub
    5073             :   0x00000000, 0x0000000c, 0x00000000, // dsub2_then_hsub
    5074             :   0x00000000, 0xf531d4d0, 0x00004c70, // qsub1_then_hsub
    5075             :   0x00000000, 0xf4000000, 0x00004c70, // qsub3_then_hsub
    5076             :   0x00000000, 0xf531d000, 0x00004c70, // qsub2_then_hsub
    5077             :   0x00000000, 0x0ace2b20, 0x0000b38f, // zsub1_then_hsub
    5078             :   0x00000000, 0x08000000, 0x0000b38f, // zsub3_then_hsub
    5079             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub2_then_hsub
    5080             : };
    5081             : 
    5082             : static const uint32_t PPRSubClassMask[] = {
    5083             :   0x0000000c, 0x00000000, 0x00000000, 
    5084             : };
    5085             : 
    5086             : static const uint32_t PPR_3bSubClassMask[] = {
    5087             :   0x00000008, 0x00000000, 0x00000000, 
    5088             : };
    5089             : 
    5090             : static const uint32_t GPR32allSubClassMask[] = {
    5091             :   0x000005d0, 0x00000000, 0x00000000, 
    5092             :   0x3fbe8000, 0x00000000, 0x00000000, // sub_32
    5093             :   0x00007800, 0x00000000, 0x00000000, // sube32
    5094             :   0x00007800, 0x00000000, 0x00000000, // subo32
    5095             :   0x3f800000, 0x00000000, 0x00000000, // subo64_then_sub_32
    5096             : };
    5097             : 
    5098             : static const uint32_t FPR32SubClassMask[] = {
    5099             :   0x00000020, 0x00000000, 0x00000000, 
    5100             :   0xc0410000, 0xffffffff, 0x0000ffff, // ssub
    5101             :   0x00400000, 0x0000000c, 0x00000000, // dsub1_then_ssub
    5102             :   0x00000000, 0x00000008, 0x00000000, // dsub3_then_ssub
    5103             :   0x00000000, 0x0000000c, 0x00000000, // dsub2_then_ssub
    5104             :   0x00000000, 0xf531d4d0, 0x00004c70, // qsub1_then_ssub
    5105             :   0x00000000, 0xf4000000, 0x00004c70, // qsub3_then_ssub
    5106             :   0x00000000, 0xf531d000, 0x00004c70, // qsub2_then_ssub
    5107             :   0x00000000, 0x0ace2b20, 0x0000b38f, // zsub1_then_ssub
    5108             :   0x00000000, 0x08000000, 0x0000b38f, // zsub3_then_ssub
    5109             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub2_then_ssub
    5110             : };
    5111             : 
    5112             : static const uint32_t GPR32SubClassMask[] = {
    5113             :   0x00000140, 0x00000000, 0x00000000, 
    5114             :   0x3f9a0000, 0x00000000, 0x00000000, // sub_32
    5115             :   0x00007800, 0x00000000, 0x00000000, // sube32
    5116             :   0x00007800, 0x00000000, 0x00000000, // subo32
    5117             :   0x3f800000, 0x00000000, 0x00000000, // subo64_then_sub_32
    5118             : };
    5119             : 
    5120             : static const uint32_t GPR32spSubClassMask[] = {
    5121             :   0x00000580, 0x00000000, 0x00000000, 
    5122             :   0x2d3c0000, 0x00000000, 0x00000000, // sub_32
    5123             :   0x00005000, 0x00000000, 0x00000000, // sube32
    5124             :   0x00006000, 0x00000000, 0x00000000, // subo32
    5125             :   0x3e000000, 0x00000000, 0x00000000, // subo64_then_sub_32
    5126             : };
    5127             : 
    5128             : static const uint32_t GPR32commonSubClassMask[] = {
    5129             :   0x00000100, 0x00000000, 0x00000000, 
    5130             :   0x2d180000, 0x00000000, 0x00000000, // sub_32
    5131             :   0x00005000, 0x00000000, 0x00000000, // sube32
    5132             :   0x00006000, 0x00000000, 0x00000000, // subo32
    5133             :   0x3e000000, 0x00000000, 0x00000000, // subo64_then_sub_32
    5134             : };
    5135             : 
    5136             : static const uint32_t CCRSubClassMask[] = {
    5137             :   0x00000200, 0x00000000, 0x00000000, 
    5138             : };
    5139             : 
    5140             : static const uint32_t GPR32sponlySubClassMask[] = {
    5141             :   0x00000400, 0x00000000, 0x00000000, 
    5142             :   0x00200000, 0x00000000, 0x00000000, // sub_32
    5143             : };
    5144             : 
    5145             : static const uint32_t WSeqPairsClassSubClassMask[] = {
    5146             :   0x00007800, 0x00000000, 0x00000000, 
    5147             :   0x3f800000, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
    5148             : };
    5149             : 
    5150             : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask[] = {
    5151             :   0x00005000, 0x00000000, 0x00000000, 
    5152             :   0x2d000000, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
    5153             : };
    5154             : 
    5155             : static const uint32_t WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
    5156             :   0x00006000, 0x00000000, 0x00000000, 
    5157             :   0x3e000000, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
    5158             : };
    5159             : 
    5160             : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
    5161             :   0x00004000, 0x00000000, 0x00000000, 
    5162             :   0x2c000000, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
    5163             : };
    5164             : 
    5165             : static const uint32_t GPR64allSubClassMask[] = {
    5166             :   0x003e8000, 0x00000000, 0x00000000, 
    5167             :   0x3f800000, 0x00000000, 0x00000000, // sube64
    5168             :   0x3f800000, 0x00000000, 0x00000000, // subo64
    5169             : };
    5170             : 
    5171             : static const uint32_t FPR64SubClassMask[] = {
    5172             :   0x00010000, 0x00000000, 0x00000000, 
    5173             :   0xc0000000, 0xfffffff3, 0x0000ffff, // dsub
    5174             :   0x00400000, 0x0000000c, 0x00000000, // dsub0
    5175             :   0x00400000, 0x0000000c, 0x00000000, // dsub1
    5176             :   0x00000000, 0x0000000c, 0x00000000, // dsub2
    5177             :   0x00000000, 0x00000008, 0x00000000, // dsub3
    5178             :   0x00000000, 0xf531d4d0, 0x00004c70, // qsub1_then_dsub
    5179             :   0x00000000, 0xf4000000, 0x00004c70, // qsub3_then_dsub
    5180             :   0x00000000, 0xf531d000, 0x00004c70, // qsub2_then_dsub
    5181             :   0x00000000, 0x0ace2b20, 0x0000b38f, // zsub1_then_dsub
    5182             :   0x00000000, 0x08000000, 0x0000b38f, // zsub3_then_dsub
    5183             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub2_then_dsub
    5184             : };
    5185             : 
    5186             : static const uint32_t GPR64SubClassMask[] = {
    5187             :   0x001a0000, 0x00000000, 0x00000000, 
    5188             :   0x3f800000, 0x00000000, 0x00000000, // sube64
    5189             :   0x3f800000, 0x00000000, 0x00000000, // subo64
    5190             : };
    5191             : 
    5192             : static const uint32_t GPR64spSubClassMask[] = {
    5193             :   0x003c0000, 0x00000000, 0x00000000, 
    5194             :   0x2d000000, 0x00000000, 0x00000000, // sube64
    5195             :   0x3e000000, 0x00000000, 0x00000000, // subo64
    5196             : };
    5197             : 
    5198             : static const uint32_t GPR64commonSubClassMask[] = {
    5199             :   0x00180000, 0x00000000, 0x00000000, 
    5200             :   0x2d000000, 0x00000000, 0x00000000, // sube64
    5201             :   0x3e000000, 0x00000000, 0x00000000, // subo64
    5202             : };
    5203             : 
    5204             : static const uint32_t tcGPR64SubClassMask[] = {
    5205             :   0x00100000, 0x00000000, 0x00000000, 
    5206             :   0x28000000, 0x00000000, 0x00000000, // sube64
    5207             :   0x30000000, 0x00000000, 0x00000000, // subo64
    5208             : };
    5209             : 
    5210             : static const uint32_t GPR64sponlySubClassMask[] = {
    5211             :   0x00200000, 0x00000000, 0x00000000, 
    5212             : };
    5213             : 
    5214             : static const uint32_t DDSubClassMask[] = {
    5215             :   0x00400000, 0x00000000, 0x00000000, 
    5216             :   0x00000000, 0x0000000c, 0x00000000, // dsub0_dsub1
    5217             :   0x00000000, 0x0000000c, 0x00000000, // dsub1_dsub2
    5218             :   0x00000000, 0x00000008, 0x00000000, // dsub2_dsub3
    5219             :   0x00000000, 0xf531d4d0, 0x00004c70, // dsub_qsub1_then_dsub
    5220             :   0x00000000, 0xf531d000, 0x00004c70, // qsub1_then_dsub_qsub2_then_dsub
    5221             :   0x00000000, 0xf4000000, 0x00004c70, // qsub2_then_dsub_qsub3_then_dsub
    5222             :   0x00000000, 0x0ace2b20, 0x0000b38f, // dsub_zsub1_then_dsub
    5223             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub1_then_dsub_zsub2_then_dsub
    5224             :   0x00000000, 0x08000000, 0x0000b38f, // zsub2_then_dsub_zsub3_then_dsub
    5225             : };
    5226             : 
    5227             : static const uint32_t XSeqPairsClassSubClassMask[] = {
    5228             :   0x3f800000, 0x00000000, 0x00000000, 
    5229             : };
    5230             : 
    5231             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask[] = {
    5232             :   0x2d000000, 0x00000000, 0x00000000, 
    5233             : };
    5234             : 
    5235             : static const uint32_t XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
    5236             :   0x3e000000, 0x00000000, 0x00000000, 
    5237             : };
    5238             : 
    5239             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
    5240             :   0x2c000000, 0x00000000, 0x00000000, 
    5241             : };
    5242             : 
    5243             : static const uint32_t XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask[] = {
    5244             :   0x28000000, 0x00000000, 0x00000000, 
    5245             : };
    5246             : 
    5247             : static const uint32_t XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
    5248             :   0x30000000, 0x00000000, 0x00000000, 
    5249             : };
    5250             : 
    5251             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
    5252             :   0x20000000, 0x00000000, 0x00000000, 
    5253             : };
    5254             : 
    5255             : static const uint32_t FPR128SubClassMask[] = {
    5256             :   0x40000000, 0x00000001, 0x00000000, 
    5257             :   0x00000000, 0xf531d4d0, 0x00004c70, // qsub0
    5258             :   0x00000000, 0xf531d4d0, 0x00004c70, // qsub1
    5259             :   0x00000000, 0xf531d000, 0x00004c70, // qsub2
    5260             :   0x00000000, 0xf4000000, 0x00004c70, // qsub3
    5261             :   0x80000000, 0x0ace2b22, 0x0000b38f, // zsub
    5262             :   0x00000000, 0x0ace2b20, 0x0000b38f, // zsub1_then_zsub
    5263             :   0x00000000, 0x08000000, 0x0000b38f, // zsub3_then_zsub
    5264             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub2_then_zsub
    5265             : };
    5266             : 
    5267             : static const uint32_t ZPRSubClassMask[] = {
    5268             :   0x80000000, 0x00000002, 0x00000000, 
    5269             :   0x00000000, 0x0ace2b20, 0x0000b38f, // zsub0
    5270             :   0x00000000, 0x0ace2b20, 0x0000b38f, // zsub1
    5271             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub2
    5272             :   0x00000000, 0x08000000, 0x0000b38f, // zsub3
    5273             : };
    5274             : 
    5275             : static const uint32_t FPR128_loSubClassMask[] = {
    5276             :   0x00000000, 0x00000001, 0x00000000, 
    5277             :   0x00000000, 0x11104440, 0x00004410, // qsub0
    5278             :   0x00000000, 0x21308480, 0x00004c30, // qsub1
    5279             :   0x00000000, 0x41210000, 0x00004c60, // qsub2
    5280             :   0x00000000, 0x80000000, 0x00004840, // qsub3
    5281             :   0x00000000, 0x02880a02, 0x0000a208, // zsub
    5282             :   0x00000000, 0x02c20900, 0x0000b281, // zsub1_then_zsub
    5283             :   0x00000000, 0x00000000, 0x00009104, // zsub3_then_zsub
    5284             :   0x00000000, 0x02440000, 0x0000b182, // zsub2_then_zsub
    5285             : };
    5286             : 
    5287             : static const uint32_t ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5288             :   0x00000000, 0x00000002, 0x00000000, 
    5289             :   0x00000000, 0x02880a00, 0x0000a208, // zsub0
    5290             :   0x00000000, 0x02c20900, 0x0000b281, // zsub1
    5291             :   0x00000000, 0x02440000, 0x0000b182, // zsub2
    5292             :   0x00000000, 0x00000000, 0x00009104, // zsub3
    5293             : };
    5294             : 
    5295             : static const uint32_t DDDSubClassMask[] = {
    5296             :   0x00000000, 0x00000004, 0x00000000, 
    5297             :   0x00000000, 0x00000008, 0x00000000, // dsub0_dsub1_dsub2
    5298             :   0x00000000, 0x00000008, 0x00000000, // dsub1_dsub2_dsub3
    5299             :   0x00000000, 0xf531d000, 0x00004c70, // dsub_qsub1_then_dsub_qsub2_then_dsub
    5300             :   0x00000000, 0xf4000000, 0x00004c70, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5301             :   0x00000000, 0x0ace2000, 0x0000b38f, // dsub_zsub1_then_dsub_zsub2_then_dsub
    5302             :   0x00000000, 0x08000000, 0x0000b38f, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    5303             : };
    5304             : 
    5305             : static const uint32_t DDDDSubClassMask[] = {
    5306             :   0x00000000, 0x00000008, 0x00000000, 
    5307             :   0x00000000, 0xf4000000, 0x00004c70, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5308             :   0x00000000, 0x08000000, 0x0000b38f, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    5309             : };
    5310             : 
    5311             : static const uint32_t QQSubClassMask[] = {
    5312             :   0x00000000, 0x000004d0, 0x00000000, 
    5313             :   0x00000000, 0xf531d000, 0x00004c70, // qsub0_qsub1
    5314             :   0x00000000, 0xf531d000, 0x00004c70, // qsub1_qsub2
    5315             :   0x00000000, 0xf4000000, 0x00004c70, // qsub2_qsub3
    5316             :   0x00000000, 0x0ace2b20, 0x0000b38f, // zsub_zsub1_then_zsub
    5317             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub1_then_zsub_zsub2_then_zsub
    5318             :   0x00000000, 0x08000000, 0x0000b38f, // zsub2_then_zsub_zsub3_then_zsub
    5319             : };
    5320             : 
    5321             : static const uint32_t ZPR2SubClassMask[] = {
    5322             :   0x00000000, 0x00000b20, 0x00000000, 
    5323             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub0_zsub1
    5324             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub1_zsub2
    5325             :   0x00000000, 0x08000000, 0x0000b38f, // zsub2_zsub3
    5326             : };
    5327             : 
    5328             : static const uint32_t QQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    5329             :   0x00000000, 0x00000440, 0x00000000, 
    5330             :   0x00000000, 0x11104000, 0x00004410, // qsub0_qsub1
    5331             :   0x00000000, 0x21308000, 0x00004c30, // qsub1_qsub2
    5332             :   0x00000000, 0x40000000, 0x00004c60, // qsub2_qsub3
    5333             :   0x00000000, 0x02880a00, 0x0000a208, // zsub_zsub1_then_zsub
    5334             :   0x00000000, 0x02c20000, 0x0000b281, // zsub1_then_zsub_zsub2_then_zsub
    5335             :   0x00000000, 0x00000000, 0x0000b182, // zsub2_then_zsub_zsub3_then_zsub
    5336             : };
    5337             : 
    5338             : static const uint32_t QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5339             :   0x00000000, 0x00000480, 0x00000000, 
    5340             :   0x00000000, 0x21308000, 0x00004c30, // qsub0_qsub1
    5341             :   0x00000000, 0x41210000, 0x00004c60, // qsub1_qsub2
    5342             :   0x00000000, 0x80000000, 0x00004840, // qsub2_qsub3
    5343             :   0x00000000, 0x02c20900, 0x0000b281, // zsub_zsub1_then_zsub
    5344             :   0x00000000, 0x02440000, 0x0000b182, // zsub1_then_zsub_zsub2_then_zsub
    5345             :   0x00000000, 0x00000000, 0x00009104, // zsub2_then_zsub_zsub3_then_zsub
    5346             : };
    5347             : 
    5348             : static const uint32_t ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5349             :   0x00000000, 0x00000900, 0x00000000, 
    5350             :   0x00000000, 0x02c20000, 0x0000b281, // zsub0_zsub1
    5351             :   0x00000000, 0x02440000, 0x0000b182, // zsub1_zsub2
    5352             :   0x00000000, 0x00000000, 0x00009104, // zsub2_zsub3
    5353             : };
    5354             : 
    5355             : static const uint32_t ZPR2_with_zsub_in_FPR128_loSubClassMask[] = {
    5356             :   0x00000000, 0x00000a00, 0x00000000, 
    5357             :   0x00000000, 0x02880000, 0x0000a208, // zsub0_zsub1
    5358             :   0x00000000, 0x02c20000, 0x0000b281, // zsub1_zsub2
    5359             :   0x00000000, 0x00000000, 0x0000b182, // zsub2_zsub3
    5360             : };
    5361             : 
    5362             : static const uint32_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5363             :   0x00000000, 0x00000400, 0x00000000, 
    5364             :   0x00000000, 0x01100000, 0x00004410, // qsub0_qsub1
    5365             :   0x00000000, 0x01200000, 0x00004c20, // qsub1_qsub2
    5366             :   0x00000000, 0x00000000, 0x00004840, // qsub2_qsub3
    5367             :   0x00000000, 0x02800800, 0x0000a200, // zsub_zsub1_then_zsub
    5368             :   0x00000000, 0x02400000, 0x0000b080, // zsub1_then_zsub_zsub2_then_zsub
    5369             :   0x00000000, 0x00000000, 0x00009100, // zsub2_then_zsub_zsub3_then_zsub
    5370             : };
    5371             : 
    5372             : static const uint32_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5373             :   0x00000000, 0x00000800, 0x00000000, 
    5374             :   0x00000000, 0x02800000, 0x0000a200, // zsub0_zsub1
    5375             :   0x00000000, 0x02400000, 0x0000b080, // zsub1_zsub2
    5376             :   0x00000000, 0x00000000, 0x00009100, // zsub2_zsub3
    5377             : };
    5378             : 
    5379             : static const uint32_t QQQSubClassMask[] = {
    5380             :   0x00000000, 0x0131d000, 0x00000000, 
    5381             :   0x00000000, 0xf4000000, 0x00004c70, // qsub0_qsub1_qsub2
    5382             :   0x00000000, 0xf4000000, 0x00004c70, // qsub1_qsub2_qsub3
    5383             :   0x00000000, 0x0ace2000, 0x0000b38f, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5384             :   0x00000000, 0x08000000, 0x0000b38f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5385             : };
    5386             : 
    5387             : static const uint32_t ZPR3SubClassMask[] = {
    5388             :   0x00000000, 0x02ce2000, 0x00000000, 
    5389             :   0x00000000, 0x08000000, 0x0000b38f, // zsub0_zsub1_zsub2
    5390             :   0x00000000, 0x08000000, 0x0000b38f, // zsub1_zsub2_zsub3
    5391             : };
    5392             : 
    5393             : static const uint32_t QQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    5394             :   0x00000000, 0x01104000, 0x00000000, 
    5395             :   0x00000000, 0x10000000, 0x00004410, // qsub0_qsub1_qsub2
    5396             :   0x00000000, 0x20000000, 0x00004c30, // qsub1_qsub2_qsub3
    5397             :   0x00000000, 0x02880000, 0x0000a208, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5398             :   0x00000000, 0x00000000, 0x0000b281, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5399             : };
    5400             : 
    5401             : static const uint32_t QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5402             :   0x00000000, 0x01308000, 0x00000000, 
    5403             :   0x00000000, 0x20000000, 0x00004c30, // qsub0_qsub1_qsub2
    5404             :   0x00000000, 0x40000000, 0x00004c60, // qsub1_qsub2_qsub3
    5405             :   0x00000000, 0x02c20000, 0x0000b281, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5406             :   0x00000000, 0x00000000, 0x0000b182, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5407             : };
    5408             : 
    5409             : static const uint32_t QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5410             :   0x00000000, 0x01210000, 0x00000000, 
    5411             :   0x00000000, 0x40000000, 0x00004c60, // qsub0_qsub1_qsub2
    5412             :   0x00000000, 0x80000000, 0x00004840, // qsub1_qsub2_qsub3
    5413             :   0x00000000, 0x02440000, 0x0000b182, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5414             :   0x00000000, 0x00000000, 0x00009104, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5415             : };
    5416             : 
    5417             : static const uint32_t ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5418             :   0x00000000, 0x02c20000, 0x00000000, 
    5419             :   0x00000000, 0x00000000, 0x0000b281, // zsub0_zsub1_zsub2
    5420             :   0x00000000, 0x00000000, 0x0000b182, // zsub1_zsub2_zsub3
    5421             : };
    5422             : 
    5423             : static const uint32_t ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5424             :   0x00000000, 0x02440000, 0x00000000, 
    5425             :   0x00000000, 0x00000000, 0x0000b182, // zsub0_zsub1_zsub2
    5426             :   0x00000000, 0x00000000, 0x00009104, // zsub1_zsub2_zsub3
    5427             : };
    5428             : 
    5429             : static const uint32_t ZPR3_with_zsub_in_FPR128_loSubClassMask[] = {
    5430             :   0x00000000, 0x02880000, 0x00000000, 
    5431             :   0x00000000, 0x00000000, 0x0000a208, // zsub0_zsub1_zsub2
    5432             :   0x00000000, 0x00000000, 0x0000b281, // zsub1_zsub2_zsub3
    5433             : };
    5434             : 
    5435             : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5436             :   0x00000000, 0x01100000, 0x00000000, 
    5437             :   0x00000000, 0x00000000, 0x00004410, // qsub0_qsub1_qsub2
    5438             :   0x00000000, 0x00000000, 0x00004c20, // qsub1_qsub2_qsub3
    5439             :   0x00000000, 0x02800000, 0x0000a200, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5440             :   0x00000000, 0x00000000, 0x0000b080, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5441             : };
    5442             : 
    5443             : static const uint32_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5444             :   0x00000000, 0x01200000, 0x00000000, 
    5445             :   0x00000000, 0x00000000, 0x00004c20, // qsub0_qsub1_qsub2
    5446             :   0x00000000, 0x00000000, 0x00004840, // qsub1_qsub2_qsub3
    5447             :   0x00000000, 0x02400000, 0x0000b080, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5448             :   0x00000000, 0x00000000, 0x00009100, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5449             : };
    5450             : 
    5451             : static const uint32_t ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5452             :   0x00000000, 0x02400000, 0x00000000, 
    5453             :   0x00000000, 0x00000000, 0x0000b080, // zsub0_zsub1_zsub2
    5454             :   0x00000000, 0x00000000, 0x00009100, // zsub1_zsub2_zsub3
    5455             : };
    5456             : 
    5457             : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5458             :   0x00000000, 0x02800000, 0x00000000, 
    5459             :   0x00000000, 0x00000000, 0x0000a200, // zsub0_zsub1_zsub2
    5460             :   0x00000000, 0x00000000, 0x0000b080, // zsub1_zsub2_zsub3
    5461             : };
    5462             : 
    5463             : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5464             :   0x00000000, 0x01000000, 0x00000000, 
    5465             :   0x00000000, 0x00000000, 0x00004400, // qsub0_qsub1_qsub2
    5466             :   0x00000000, 0x00000000, 0x00004800, // qsub1_qsub2_qsub3
    5467             :   0x00000000, 0x02000000, 0x0000a000, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5468             :   0x00000000, 0x00000000, 0x00009000, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5469             : };
    5470             : 
    5471             : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5472             :   0x00000000, 0x02000000, 0x00000000, 
    5473             :   0x00000000, 0x00000000, 0x0000a000, // zsub0_zsub1_zsub2
    5474             :   0x00000000, 0x00000000, 0x00009000, // zsub1_zsub2_zsub3
    5475             : };
    5476             : 
    5477             : static const uint32_t QQQQSubClassMask[] = {
    5478             :   0x00000000, 0xf4000000, 0x00004c70, 
    5479             :   0x00000000, 0x08000000, 0x0000b38f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5480             : };
    5481             : 
    5482             : static const uint32_t ZPR4SubClassMask[] = {
    5483             :   0x00000000, 0x08000000, 0x0000b38f, 
    5484             : };
    5485             : 
    5486             : static const uint32_t QQQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    5487             :   0x00000000, 0x10000000, 0x00004410, 
    5488             :   0x00000000, 0x00000000, 0x0000a208, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5489             : };
    5490             : 
    5491             : static const uint32_t QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5492             :   0x00000000, 0x20000000, 0x00004c30, 
    5493             :   0x00000000, 0x00000000, 0x0000b281, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5494             : };
    5495             : 
    5496             : static const uint32_t QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5497             :   0x00000000, 0x40000000, 0x00004c60, 
    5498             :   0x00000000, 0x00000000, 0x0000b182, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5499             : };
    5500             : 
    5501             : static const uint32_t QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    5502             :   0x00000000, 0x80000000, 0x00004840, 
    5503             :   0x00000000, 0x00000000, 0x00009104, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5504             : };
    5505             : 
    5506             : static const uint32_t ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5507             :   0x00000000, 0x00000000, 0x0000b281, 
    5508             : };
    5509             : 
    5510             : static const uint32_t ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5511             :   0x00000000, 0x00000000, 0x0000b182, 
    5512             : };
    5513             : 
    5514             : static const uint32_t ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5515             :   0x00000000, 0x00000000, 0x00009104, 
    5516             : };
    5517             : 
    5518             : static const uint32_t ZPR4_with_zsub_in_FPR128_loSubClassMask[] = {
    5519             :   0x00000000, 0x00000000, 0x0000a208, 
    5520             : };
    5521             : 
    5522             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5523             :   0x00000000, 0x00000000, 0x00004410, 
    5524             :   0x00000000, 0x00000000, 0x0000a200, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5525             : };
    5526             : 
    5527             : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5528             :   0x00000000, 0x00000000, 0x00004c20, 
    5529             :   0x00000000, 0x00000000, 0x0000b080, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5530             : };
    5531             : 
    5532             : static const uint32_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    5533             :   0x00000000, 0x00000000, 0x00004840, 
    5534             :   0x00000000, 0x00000000, 0x00009100, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5535             : };
    5536             : 
    5537             : static const uint32_t ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5538             :   0x00000000, 0x00000000, 0x0000b080, 
    5539             : };
    5540             : 
    5541             : static const uint32_t ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5542             :   0x00000000, 0x00000000, 0x00009100, 
    5543             : };
    5544             : 
    5545             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5546             :   0x00000000, 0x00000000, 0x0000a200, 
    5547             : };
    5548             : 
    5549             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5550             :   0x00000000, 0x00000000, 0x00004400, 
    5551             :   0x00000000, 0x00000000, 0x0000a000, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5552             : };
    5553             : 
    5554             : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    5555             :   0x00000000, 0x00000000, 0x00004800, 
    5556             :   0x00000000, 0x00000000, 0x00009000, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5557             : };
    5558             : 
    5559             : static const uint32_t ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5560             :   0x00000000, 0x00000000, 0x00009000, 
    5561             : };
    5562             : 
    5563             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5564             :   0x00000000, 0x00000000, 0x0000a000, 
    5565             : };
    5566             : 
    5567             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    5568             :   0x00000000, 0x00000000, 0x00004000, 
    5569             :   0x00000000, 0x00000000, 0x00008000, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5570             : };
    5571             : 
    5572             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSubClassMask[] = {
    5573             :   0x00000000, 0x00000000, 0x00008000, 
    5574             : };
    5575             : 
    5576             : static const uint16_t SuperRegIdxSeqs[] = {
    5577             :   /* 0 */ 15, 0,
    5578             :   /* 2 */ 17, 19, 0,
    5579             :   /* 5 */ 21, 22, 23, 24, 0,
    5580             :   /* 10 */ 15, 16, 18, 47, 0,
    5581             :   /* 15 */ 1, 26, 29, 32, 35, 39, 43, 48, 54, 60, 0,
    5582             :   /* 26 */ 2, 3, 4, 5, 6, 36, 40, 44, 49, 55, 61, 0,
    5583             :   /* 38 */ 7, 27, 30, 33, 37, 41, 45, 50, 56, 62, 0,
    5584             :   /* 49 */ 14, 28, 31, 34, 38, 42, 46, 51, 57, 63, 0,
    5585             :   /* 60 */ 10, 11, 12, 13, 20, 52, 58, 64, 0,
    5586             :   /* 69 */ 82, 0,
    5587             :   /* 71 */ 72, 85, 0,
    5588             :   /* 74 */ 87, 0,
    5589             :   /* 76 */ 90, 92, 0,
    5590             :   /* 79 */ 89, 91, 93, 0,
    5591             :   /* 83 */ 67, 69, 73, 80, 86, 95, 0,
    5592             :   /* 90 */ 75, 77, 88, 97, 0,
    5593             :   /* 95 */ 66, 68, 70, 71, 79, 81, 83, 94, 98, 0,
    5594             :   /* 105 */ 74, 76, 78, 84, 96, 99, 0,
    5595             : };
    5596             : 
    5597             : static const TargetRegisterClass *const PPR_3bSuperclasses[] = {
    5598             :   &AArch64::PPRRegClass,
    5599             :   nullptr
    5600             : };
    5601             : 
    5602             : static const TargetRegisterClass *const GPR32Superclasses[] = {
    5603             :   &AArch64::GPR32allRegClass,
    5604             :   nullptr
    5605             : };
    5606             : 
    5607             : static const TargetRegisterClass *const GPR32spSuperclasses[] = {
    5608             :   &AArch64::GPR32allRegClass,
    5609             :   nullptr
    5610             : };
    5611             : 
    5612             : static const TargetRegisterClass *const GPR32commonSuperclasses[] = {
    5613             :   &AArch64::GPR32allRegClass,
    5614             :   &AArch64::GPR32RegClass,
    5615             :   &AArch64::GPR32spRegClass,
    5616             :   nullptr
    5617             : };
    5618             : 
    5619             : static const TargetRegisterClass *const GPR32sponlySuperclasses[] = {
    5620             :   &AArch64::GPR32allRegClass,
    5621             :   &AArch64::GPR32spRegClass,
    5622             :   nullptr
    5623             : };
    5624             : 
    5625             : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses[] = {
    5626             :   &AArch64::WSeqPairsClassRegClass,
    5627             :   nullptr
    5628             : };
    5629             : 
    5630             : static const TargetRegisterClass *const WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
    5631             :   &AArch64::WSeqPairsClassRegClass,
    5632             :   nullptr
    5633             : };
    5634             : 
    5635             : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
    5636             :   &AArch64::WSeqPairsClassRegClass,
    5637             :   &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
    5638             :   &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    5639             :   nullptr
    5640             : };
    5641             : 
    5642             : static const TargetRegisterClass *const GPR64Superclasses[] = {
    5643             :   &AArch64::GPR64allRegClass,
    5644             :   nullptr
    5645             : };
    5646             : 
    5647             : static const TargetRegisterClass *const GPR64spSuperclasses[] = {
    5648             :   &AArch64::GPR64allRegClass,
    5649             :   nullptr
    5650             : };
    5651             : 
    5652             : static const TargetRegisterClass *const GPR64commonSuperclasses[] = {
    5653             :   &AArch64::GPR64allRegClass,
    5654             :   &AArch64::GPR64RegClass,
    5655             :   &AArch64::GPR64spRegClass,
    5656             :   nullptr
    5657             : };
    5658             : 
    5659             : static const TargetRegisterClass *const tcGPR64Superclasses[] = {
    5660             :   &AArch64::GPR64allRegClass,
    5661             :   &AArch64::GPR64RegClass,
    5662             :   &AArch64::GPR64spRegClass,
    5663             :   &AArch64::GPR64commonRegClass,
    5664             :   nullptr
    5665             : };
    5666             : 
    5667             : static const TargetRegisterClass *const GPR64sponlySuperclasses[] = {
    5668             :   &AArch64::GPR64allRegClass,
    5669             :   &AArch64::GPR64spRegClass,
    5670             :   nullptr
    5671             : };
    5672             : 
    5673             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses[] = {
    5674             :   &AArch64::XSeqPairsClassRegClass,
    5675             :   nullptr
    5676             : };
    5677             : 
    5678             : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
    5679             :   &AArch64::XSeqPairsClassRegClass,
    5680             :   nullptr
    5681             : };
    5682             : 
    5683             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
    5684             :   &AArch64::XSeqPairsClassRegClass,
    5685             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    5686             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5687             :   nullptr
    5688             : };
    5689             : 
    5690             : static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_tcGPR64Superclasses[] = {
    5691             :   &AArch64::XSeqPairsClassRegClass,
    5692             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    5693             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5694             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5695             :   nullptr
    5696             : };
    5697             : 
    5698             : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
    5699             :   &AArch64::XSeqPairsClassRegClass,
    5700             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5701             :   nullptr
    5702             : };
    5703             : 
    5704             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
    5705             :   &AArch64::XSeqPairsClassRegClass,
    5706             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    5707             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5708             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    5709             :   &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
    5710             :   &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    5711             :   nullptr
    5712             : };
    5713             : 
    5714             : static const TargetRegisterClass *const FPR128_loSuperclasses[] = {
    5715             :   &AArch64::FPR128RegClass,
    5716             :   nullptr
    5717             : };
    5718             : 
    5719             : static const TargetRegisterClass *const ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5720             :   &AArch64::ZPRRegClass,
    5721             :   nullptr
    5722             : };
    5723             : 
    5724             : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    5725             :   &AArch64::QQRegClass,
    5726             :   nullptr
    5727             : };
    5728             : 
    5729             : static const TargetRegisterClass *const QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    5730             :   &AArch64::QQRegClass,
    5731             :   nullptr
    5732             : };
    5733             : 
    5734             : static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5735             :   &AArch64::ZPR2RegClass,
    5736             :   nullptr
    5737             : };
    5738             : 
    5739             : static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_loSuperclasses[] = {
    5740             :   &AArch64::ZPR2RegClass,
    5741             :   nullptr
    5742             : };
    5743             : 
    5744             : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    5745             :   &AArch64::QQRegClass,
    5746             :   &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
    5747             :   &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
    5748             :   nullptr
    5749             : };
    5750             : 
    5751             : static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5752             :   &AArch64::ZPR2RegClass,
    5753             :   &AArch64::ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5754             :   &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
    5755             :   nullptr
    5756             : };
    5757             : 
    5758             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    5759             :   &AArch64::QQQRegClass,
    5760             :   nullptr
    5761             : };
    5762             : 
    5763             : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    5764             :   &AArch64::QQQRegClass,
    5765             :   nullptr
    5766             : };
    5767             : 
    5768             : static const TargetRegisterClass *const QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    5769             :   &AArch64::QQQRegClass,
    5770             :   nullptr
    5771             : };
    5772             : 
    5773             : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5774             :   &AArch64::ZPR3RegClass,
    5775             :   nullptr
    5776             : };
    5777             : 
    5778             : static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5779             :   &AArch64::ZPR3RegClass,
    5780             :   nullptr
    5781             : };
    5782             : 
    5783             : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_loSuperclasses[] = {
    5784             :   &AArch64::ZPR3RegClass,
    5785             :   nullptr
    5786             : };
    5787             : 
    5788             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    5789             :   &AArch64::QQQRegClass,
    5790             :   &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    5791             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    5792             :   nullptr
    5793             : };
    5794             : 
    5795             : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    5796             :   &AArch64::QQQRegClass,
    5797             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    5798             :   &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    5799             :   nullptr
    5800             : };
    5801             : 
    5802             : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5803             :   &AArch64::ZPR3RegClass,
    5804             :   &AArch64::ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5805             :   &AArch64::ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5806             :   nullptr
    5807             : };
    5808             : 
    5809             : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5810             :   &AArch64::ZPR3RegClass,
    5811             :   &AArch64::ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5812             :   &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    5813             :   nullptr
    5814             : };
    5815             : 
    5816             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    5817             :   &AArch64::QQQRegClass,
    5818             :   &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    5819             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    5820             :   &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    5821             :   &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
    5822             :   &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    5823             :   nullptr
    5824             : };
    5825             : 
    5826             : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5827             :   &AArch64::ZPR3RegClass,
    5828             :   &AArch64::ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5829             :   &AArch64::ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5830             :   &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    5831             :   &AArch64::ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5832             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5833             :   nullptr
    5834             : };
    5835             : 
    5836             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    5837             :   &AArch64::QQQQRegClass,
    5838             :   nullptr
    5839             : };
    5840             : 
    5841             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    5842             :   &AArch64::QQQQRegClass,
    5843             :   nullptr
    5844             : };
    5845             : 
    5846             : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    5847             :   &AArch64::QQQQRegClass,
    5848             :   nullptr
    5849             : };
    5850             : 
    5851             : static const TargetRegisterClass *const QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    5852             :   &AArch64::QQQQRegClass,
    5853             :   nullptr
    5854             : };
    5855             : 
    5856             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5857             :   &AArch64::ZPR4RegClass,
    5858             :   nullptr
    5859             : };
    5860             : 
    5861             : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5862             :   &AArch64::ZPR4RegClass,
    5863             :   nullptr
    5864             : };
    5865             : 
    5866             : static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5867             :   &AArch64::ZPR4RegClass,
    5868             :   nullptr
    5869             : };
    5870             : 
    5871             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_loSuperclasses[] = {
    5872             :   &AArch64::ZPR4RegClass,
    5873             :   nullptr
    5874             : };
    5875             : 
    5876             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    5877             :   &AArch64::QQQQRegClass,
    5878             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    5879             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    5880             :   nullptr
    5881             : };
    5882             : 
    5883             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    5884             :   &AArch64::QQQQRegClass,
    5885             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    5886             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    5887             :   nullptr
    5888             : };
    5889             : 
    5890             : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    5891             :   &AArch64::QQQQRegClass,
    5892             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    5893             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    5894             :   nullptr
    5895             : };
    5896             : 
    5897             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5898             :   &AArch64::ZPR4RegClass,
    5899             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5900             :   &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5901             :   nullptr
    5902             : };
    5903             : 
    5904             : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5905             :   &AArch64::ZPR4RegClass,
    5906             :   &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5907             :   &AArch64::ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5908             :   nullptr
    5909             : };
    5910             : 
    5911             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5912             :   &AArch64::ZPR4RegClass,
    5913             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5914             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    5915             :   nullptr
    5916             : };
    5917             : 
    5918             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    5919             :   &AArch64::QQQQRegClass,
    5920             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    5921             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    5922             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    5923             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    5924             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    5925             :   nullptr
    5926             : };
    5927             : 
    5928             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    5929             :   &AArch64::QQQQRegClass,
    5930             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    5931             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    5932             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    5933             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    5934             :   &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5935             :   nullptr
    5936             : };
    5937             : 
    5938             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5939             :   &AArch64::ZPR4RegClass,
    5940             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5941             :   &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5942             :   &AArch64::ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5943             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5944             :   &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5945             :   nullptr
    5946             : };
    5947             : 
    5948             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5949             :   &AArch64::ZPR4RegClass,
    5950             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5951             :   &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5952             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    5953             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5954             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5955             :   nullptr
    5956             : };
    5957             : 
    5958             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    5959             :   &AArch64::QQQQRegClass,
    5960             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    5961             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    5962             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    5963             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    5964             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    5965             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    5966             :   &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5967             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    5968             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    5969             :   nullptr
    5970             : };
    5971             : 
    5972             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSuperclasses[] = {
    5973             :   &AArch64::ZPR4RegClass,
    5974             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5975             :   &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5976             :   &AArch64::ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5977             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    5978             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5979             :   &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5980             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5981             :   &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5982             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    5983             :   nullptr
    5984             : };
    5985             : 
    5986             : 
    5987             : static inline unsigned GPR32AltOrderSelect(const MachineFunction &MF) { return 1; }
    5988             : 
    5989         561 : static ArrayRef<MCPhysReg> GPR32GetRawAllocationOrder(const MachineFunction &MF) {
    5990             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    5991             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
    5992             :   const ArrayRef<MCPhysReg> Order[] = {
    5993             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5994             :     makeArrayRef(AltOrder1)
    5995             :   };
    5996             :   const unsigned Select = GPR32AltOrderSelect(MF);
    5997             :   assert(Select < 2);
    5998         561 :   return Order[Select];
    5999             : }
    6000             : 
    6001             : static inline unsigned GPR32spAltOrderSelect(const MachineFunction &MF) { return 1; }
    6002             : 
    6003          87 : static ArrayRef<MCPhysReg> GPR32spGetRawAllocationOrder(const MachineFunction &MF) {
    6004             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    6005             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
    6006             :   const ArrayRef<MCPhysReg> Order[] = {
    6007             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6008             :     makeArrayRef(AltOrder1)
    6009             :   };
    6010             :   const unsigned Select = GPR32spAltOrderSelect(MF);
    6011             :   assert(Select < 2);
    6012          87 :   return Order[Select];
    6013             : }
    6014             : 
    6015             : static inline unsigned GPR32commonAltOrderSelect(const MachineFunction &MF) { return 1; }
    6016             : 
    6017         234 : static ArrayRef<MCPhysReg> GPR32commonGetRawAllocationOrder(const MachineFunction &MF) {
    6018             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    6019             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];
    6020             :   const ArrayRef<MCPhysReg> Order[] = {
    6021             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6022             :     makeArrayRef(AltOrder1)
    6023             :   };
    6024             :   const unsigned Select = GPR32commonAltOrderSelect(MF);
    6025             :   assert(Select < 2);
    6026         234 :   return Order[Select];
    6027             : }
    6028             : 
    6029             : static inline unsigned GPR64AltOrderSelect(const MachineFunction &MF) { return 1; }
    6030             : 
    6031         743 : static ArrayRef<MCPhysReg> GPR64GetRawAllocationOrder(const MachineFunction &MF) {
    6032             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    6033             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
    6034             :   const ArrayRef<MCPhysReg> Order[] = {
    6035             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6036             :     makeArrayRef(AltOrder1)
    6037             :   };
    6038             :   const unsigned Select = GPR64AltOrderSelect(MF);
    6039             :   assert(Select < 2);
    6040         743 :   return Order[Select];
    6041             : }
    6042             : 
    6043             : static inline unsigned GPR64spAltOrderSelect(const MachineFunction &MF) { return 1; }
    6044             : 
    6045         173 : static ArrayRef<MCPhysReg> GPR64spGetRawAllocationOrder(const MachineFunction &MF) {
    6046             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    6047             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];
    6048             :   const ArrayRef<MCPhysReg> Order[] = {
    6049             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6050             :     makeArrayRef(AltOrder1)
    6051             :   };
    6052             :   const unsigned Select = GPR64spAltOrderSelect(MF);
    6053             :   assert(Select < 2);
    6054         173 :   return Order[Select];
    6055             : }
    6056             : 
    6057             : static inline unsigned GPR64commonAltOrderSelect(const MachineFunction &MF) { return 1; }
    6058             : 
    6059         734 : static ArrayRef<MCPhysReg> GPR64commonGetRawAllocationOrder(const MachineFunction &MF) {
    6060             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    6061             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID];
    6062             :   const ArrayRef<MCPhysReg> Order[] = {
    6063             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6064             :     makeArrayRef(AltOrder1)
    6065             :   };
    6066             :   const unsigned Select = GPR64commonAltOrderSelect(MF);
    6067             :   assert(Select < 2);
    6068         734 :   return Order[Select];
    6069             : }
    6070             : 
    6071             : namespace AArch64 {   // Register class instances
    6072             :   extern const TargetRegisterClass FPR8RegClass = {
    6073             :     &AArch64MCRegisterClasses[FPR8RegClassID],
    6074             :     FPR8SubClassMask,
    6075             :     SuperRegIdxSeqs + 15,
    6076             :     LaneBitmask(0x00000001),
    6077             :     0,
    6078             :     false, /* HasDisjunctSubRegs */
    6079             :     false, /* CoveredBySubRegs */
    6080             :     NullRegClasses,
    6081             :     nullptr
    6082             :   };
    6083             : 
    6084             :   extern const TargetRegisterClass FPR16RegClass = {
    6085             :     &AArch64MCRegisterClasses[FPR16RegClassID],
    6086             :     FPR16SubClassMask,
    6087             :     SuperRegIdxSeqs + 38,
    6088             :     LaneBitmask(0x00000001),
    6089             :     0,
    6090             :     false, /* HasDisjunctSubRegs */
    6091             :     false, /* CoveredBySubRegs */
    6092             :     NullRegClasses,
    6093             :     nullptr
    6094             :   };
    6095             : 
    6096             :   extern const TargetRegisterClass PPRRegClass = {
    6097             :     &AArch64MCRegisterClasses[PPRRegClassID],
    6098             :     PPRSubClassMask,
    6099             :     SuperRegIdxSeqs + 1,
    6100             :     LaneBitmask(0x00000001),
    6101             :     0,
    6102             :     false, /* HasDisjunctSubRegs */
    6103             :     false, /* CoveredBySubRegs */
    6104             :     NullRegClasses,
    6105             :     nullptr
    6106             :   };
    6107             : 
    6108             :   extern const TargetRegisterClass PPR_3bRegClass = {
    6109             :     &AArch64MCRegisterClasses[PPR_3bRegClassID],
    6110             :     PPR_3bSubClassMask,
    6111             :     SuperRegIdxSeqs + 1,
    6112             :     LaneBitmask(0x00000001),
    6113             :     0,
    6114             :     false, /* HasDisjunctSubRegs */
    6115             :     false, /* CoveredBySubRegs */
    6116             :     PPR_3bSuperclasses,
    6117             :     nullptr
    6118             :   };
    6119             : 
    6120             :   extern const TargetRegisterClass GPR32allRegClass = {
    6121             :     &AArch64MCRegisterClasses[GPR32allRegClassID],
    6122             :     GPR32allSubClassMask,
    6123             :     SuperRegIdxSeqs + 10,
    6124             :     LaneBitmask(0x00000001),
    6125             :     0,
    6126             :     false, /* HasDisjunctSubRegs */
    6127             :     false, /* CoveredBySubRegs */
    6128             :     NullRegClasses,
    6129             :     nullptr
    6130             :   };
    6131             : 
    6132             :   extern const TargetRegisterClass FPR32RegClass = {
    6133             :     &AArch64MCRegisterClasses[FPR32RegClassID],
    6134             :     FPR32SubClassMask,
    6135             :     SuperRegIdxSeqs + 49,
    6136             :     LaneBitmask(0x00000001),
    6137             :     0,
    6138             :     false, /* HasDisjunctSubRegs */
    6139             :     false, /* CoveredBySubRegs */
    6140             :     NullRegClasses,
    6141             :     nullptr
    6142             :   };
    6143             : 
    6144             :   extern const TargetRegisterClass GPR32RegClass = {
    6145             :     &AArch64MCRegisterClasses[GPR32RegClassID],
    6146             :     GPR32SubClassMask,
    6147             :     SuperRegIdxSeqs + 10,
    6148             :     LaneBitmask(0x00000001),
    6149             :     0,
    6150             :     false, /* HasDisjunctSubRegs */
    6151             :     false, /* CoveredBySubRegs */
    6152             :     GPR32Superclasses,
    6153             :     GPR32GetRawAllocationOrder
    6154             :   };
    6155             : 
    6156             :   extern const TargetRegisterClass GPR32spRegClass = {
    6157             :     &AArch64MCRegisterClasses[GPR32spRegClassID],
    6158             :     GPR32spSubClassMask,
    6159             :     SuperRegIdxSeqs + 10,
    6160             :     LaneBitmask(0x00000001),
    6161             :     0,
    6162             :     false, /* HasDisjunctSubRegs */
    6163             :     false, /* CoveredBySubRegs */
    6164             :     GPR32spSuperclasses,
    6165             :     GPR32spGetRawAllocationOrder
    6166             :   };
    6167             : 
    6168             :   extern const TargetRegisterClass GPR32commonRegClass = {
    6169             :     &AArch64MCRegisterClasses[GPR32commonRegClassID],
    6170             :     GPR32commonSubClassMask,
    6171             :     SuperRegIdxSeqs + 10,
    6172             :     LaneBitmask(0x00000001),
    6173             :     0,
    6174             :     false, /* HasDisjunctSubRegs */
    6175             :     false, /* CoveredBySubRegs */
    6176             :     GPR32commonSuperclasses,
    6177             :     GPR32commonGetRawAllocationOrder
    6178             :   };
    6179             : 
    6180             :   extern const TargetRegisterClass CCRRegClass = {
    6181             :     &AArch64MCRegisterClasses[CCRRegClassID],
    6182             :     CCRSubClassMask,
    6183             :     SuperRegIdxSeqs + 1,
    6184             :     LaneBitmask(0x00000001),
    6185             :     0,
    6186             :     false, /* HasDisjunctSubRegs */
    6187             :     false, /* CoveredBySubRegs */
    6188             :     NullRegClasses,
    6189             :     nullptr
    6190             :   };
    6191             : 
    6192             :   extern const TargetRegisterClass GPR32sponlyRegClass = {
    6193             :     &AArch64MCRegisterClasses[GPR32sponlyRegClassID],
    6194             :     GPR32sponlySubClassMask,
    6195             :     SuperRegIdxSeqs + 0,
    6196             :     LaneBitmask(0x00000001),
    6197             :     0,
    6198             :     false, /* HasDisjunctSubRegs */
    6199             :     false, /* CoveredBySubRegs */
    6200             :     GPR32sponlySuperclasses,
    6201             :     nullptr
    6202             :   };
    6203             : 
    6204             :   extern const TargetRegisterClass WSeqPairsClassRegClass = {
    6205             :     &AArch64MCRegisterClasses[WSeqPairsClassRegClassID],
    6206             :     WSeqPairsClassSubClassMask,
    6207             :     SuperRegIdxSeqs + 69,
    6208             :     LaneBitmask(0x00000030),
    6209             :     0,
    6210             :     true, /* HasDisjunctSubRegs */
    6211             :     true, /* CoveredBySubRegs */
    6212             :     NullRegClasses,
    6213             :     nullptr
    6214             :   };
    6215             : 
    6216             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass = {
    6217             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32commonRegClassID],
    6218             :     WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask,
    6219             :     SuperRegIdxSeqs + 69,
    6220             :     LaneBitmask(0x00000030),
    6221             :     0,
    6222             :     true, /* HasDisjunctSubRegs */
    6223             :     true, /* CoveredBySubRegs */
    6224             :     WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses,
    6225             :     nullptr
    6226             :   };
    6227             : 
    6228             :   extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
    6229             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
    6230             :     WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
    6231             :     SuperRegIdxSeqs + 69,
    6232             :     LaneBitmask(0x00000030),
    6233             :     0,
    6234             :     true, /* HasDisjunctSubRegs */
    6235             :     true, /* CoveredBySubRegs */
    6236             :     WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
    6237             :     nullptr
    6238             :   };
    6239             : 
    6240             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
    6241             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
    6242             :     WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
    6243             :     SuperRegIdxSeqs + 69,
    6244             :     LaneBitmask(0x00000030),
    6245             :     0,
    6246             :     true, /* HasDisjunctSubRegs */
    6247             :     true, /* CoveredBySubRegs */
    6248             :     WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
    6249             :     nullptr
    6250             :   };
    6251             : 
    6252             :   extern const TargetRegisterClass GPR64allRegClass = {
    6253             :     &AArch64MCRegisterClasses[GPR64allRegClassID],
    6254             :     GPR64allSubClassMask,
    6255             :     SuperRegIdxSeqs + 2,
    6256             :     LaneBitmask(0x00000008),
    6257             :     0,
    6258             :     false, /* HasDisjunctSubRegs */
    6259             :     false, /* CoveredBySubRegs */
    6260             :     NullRegClasses,
    6261             :     nullptr
    6262             :   };
    6263             : 
    6264             :   extern const TargetRegisterClass FPR64RegClass = {
    6265             :     &AArch64MCRegisterClasses[FPR64RegClassID],
    6266             :     FPR64SubClassMask,
    6267             :     SuperRegIdxSeqs + 26,
    6268             :     LaneBitmask(0x00000001),
    6269             :     0,
    6270             :     false, /* HasDisjunctSubRegs */
    6271             :     false, /* CoveredBySubRegs */
    6272             :     NullRegClasses,
    6273             :     nullptr
    6274             :   };
    6275             : 
    6276             :   extern const TargetRegisterClass GPR64RegClass = {
    6277             :     &AArch64MCRegisterClasses[GPR64RegClassID],
    6278             :     GPR64SubClassMask,
    6279             :     SuperRegIdxSeqs + 2,
    6280             :     LaneBitmask(0x00000008),
    6281             :     0,
    6282             :     false, /* HasDisjunctSubRegs */
    6283             :     false, /* CoveredBySubRegs */
    6284             :     GPR64Superclasses,
    6285             :     GPR64GetRawAllocationOrder
    6286             :   };
    6287             : 
    6288             :   extern const TargetRegisterClass GPR64spRegClass = {
    6289             :     &AArch64MCRegisterClasses[GPR64spRegClassID],
    6290             :     GPR64spSubClassMask,
    6291             :     SuperRegIdxSeqs + 2,
    6292             :     LaneBitmask(0x00000008),
    6293             :     0,
    6294             :     false, /* HasDisjunctSubRegs */
    6295             :     false, /* CoveredBySubRegs */
    6296             :     GPR64spSuperclasses,
    6297             :     GPR64spGetRawAllocationOrder
    6298             :   };
    6299             : 
    6300             :   extern const TargetRegisterClass GPR64commonRegClass = {
    6301             :     &AArch64MCRegisterClasses[GPR64commonRegClassID],
    6302             :     GPR64commonSubClassMask,
    6303             :     SuperRegIdxSeqs + 2,
    6304             :     LaneBitmask(0x00000008),
    6305             :     0,
    6306             :     false, /* HasDisjunctSubRegs */
    6307             :     false, /* CoveredBySubRegs */
    6308             :     GPR64commonSuperclasses,
    6309             :     GPR64commonGetRawAllocationOrder
    6310             :   };
    6311             : 
    6312             :   extern const TargetRegisterClass tcGPR64RegClass = {
    6313             :     &AArch64MCRegisterClasses[tcGPR64RegClassID],
    6314             :     tcGPR64SubClassMask,
    6315             :     SuperRegIdxSeqs + 2,
    6316             :     LaneBitmask(0x00000008),
    6317             :     0,
    6318             :     false, /* HasDisjunctSubRegs */
    6319             :     false, /* CoveredBySubRegs */
    6320             :     tcGPR64Superclasses,
    6321             :     nullptr
    6322             :   };
    6323             : 
    6324             :   extern const TargetRegisterClass GPR64sponlyRegClass = {
    6325             :     &AArch64MCRegisterClasses[GPR64sponlyRegClassID],
    6326             :     GPR64sponlySubClassMask,
    6327             :     SuperRegIdxSeqs + 1,
    6328             :     LaneBitmask(0x00000008),
    6329             :     0,
    6330             :     false, /* HasDisjunctSubRegs */
    6331             :     false, /* CoveredBySubRegs */
    6332             :     GPR64sponlySuperclasses,
    6333             :     nullptr
    6334             :   };
    6335             : 
    6336             :   extern const TargetRegisterClass DDRegClass = {
    6337             :     &AArch64MCRegisterClasses[DDRegClassID],
    6338             :     DDSubClassMask,
    6339             :     SuperRegIdxSeqs + 95,
    6340             :     LaneBitmask(0x00000081),
    6341             :     0,
    6342             :     true, /* HasDisjunctSubRegs */
    6343             :     true, /* CoveredBySubRegs */
    6344             :     NullRegClasses,
    6345             :     nullptr
    6346             :   };
    6347             : 
    6348             :   extern const TargetRegisterClass XSeqPairsClassRegClass = {
    6349             :     &AArch64MCRegisterClasses[XSeqPairsClassRegClassID],
    6350             :     XSeqPairsClassSubClassMask,
    6351             :     SuperRegIdxSeqs + 1,
    6352             :     LaneBitmask(0x00002008),
    6353             :     0,
    6354             :     true, /* HasDisjunctSubRegs */
    6355             :     true, /* CoveredBySubRegs */
    6356             :     NullRegClasses,
    6357             :     nullptr
    6358             :   };
    6359             : 
    6360             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass = {
    6361             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID],
    6362             :     XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask,
    6363             :     SuperRegIdxSeqs + 1,
    6364             :     LaneBitmask(0x00002008),
    6365             :     0,
    6366             :     true, /* HasDisjunctSubRegs */
    6367             :     true, /* CoveredBySubRegs */
    6368             :     XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses,
    6369             :     nullptr
    6370             :   };
    6371             : 
    6372             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
    6373             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
    6374             :     XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
    6375             :     SuperRegIdxSeqs + 1,
    6376             :     LaneBitmask(0x00002008),
    6377             :     0,
    6378             :     true, /* HasDisjunctSubRegs */
    6379             :     true, /* CoveredBySubRegs */
    6380             :     XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
    6381             :     nullptr
    6382             :   };
    6383             : 
    6384             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
    6385             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
    6386             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
    6387             :     SuperRegIdxSeqs + 1,
    6388             :     LaneBitmask(0x00002008),
    6389             :     0,
    6390             :     true, /* HasDisjunctSubRegs */
    6391             :     true, /* CoveredBySubRegs */
    6392             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
    6393             :     nullptr
    6394             :   };
    6395             : 
    6396             :   extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass = {
    6397             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_tcGPR64RegClassID],
    6398             :     XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask,
    6399             :     SuperRegIdxSeqs + 1,
    6400             :     LaneBitmask(0x00002008),
    6401             :     0,
    6402             :     true, /* HasDisjunctSubRegs */
    6403             :     true, /* CoveredBySubRegs */
    6404             :     XSeqPairsClass_with_sube64_in_tcGPR64Superclasses,
    6405             :     nullptr
    6406             :   };
    6407             : 
    6408             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
    6409             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
    6410             :     XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
    6411             :     SuperRegIdxSeqs + 1,
    6412             :     LaneBitmask(0x00002008),
    6413             :     0,
    6414             :     true, /* HasDisjunctSubRegs */
    6415             :     true, /* CoveredBySubRegs */
    6416             :     XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
    6417             :     nullptr
    6418             :   };
    6419             : 
    6420             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
    6421             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
    6422             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
    6423             :     SuperRegIdxSeqs + 1,
    6424             :     LaneBitmask(0x00002008),
    6425             :     0,
    6426             :     true, /* HasDisjunctSubRegs */
    6427             :     true, /* CoveredBySubRegs */
    6428             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
    6429             :     nullptr
    6430             :   };
    6431             : 
    6432             :   extern const TargetRegisterClass FPR128RegClass = {
    6433             :     &AArch64MCRegisterClasses[FPR128RegClassID],
    6434             :     FPR128SubClassMask,
    6435             :     SuperRegIdxSeqs + 60,
    6436             :     LaneBitmask(0x00000001),
    6437             :     0,
    6438             :     false, /* HasDisjunctSubRegs */
    6439             :     false, /* CoveredBySubRegs */
    6440             :     NullRegClasses,
    6441             :     nullptr
    6442             :   };
    6443             : 
    6444             :   extern const TargetRegisterClass ZPRRegClass = {
    6445             :     &AArch64MCRegisterClasses[ZPRRegClassID],
    6446             :     ZPRSubClassMask,
    6447             :     SuperRegIdxSeqs + 5,
    6448             :     LaneBitmask(0x00000041),
    6449             :     0,
    6450             :     true, /* HasDisjunctSubRegs */
    6451             :     false, /* CoveredBySubRegs */
    6452             :     NullRegClasses,
    6453             :     nullptr
    6454             :   };
    6455             : 
    6456             :   extern const TargetRegisterClass FPR128_loRegClass = {
    6457             :     &AArch64MCRegisterClasses[FPR128_loRegClassID],
    6458             :     FPR128_loSubClassMask,
    6459             :     SuperRegIdxSeqs + 60,
    6460             :     LaneBitmask(0x00000001),
    6461             :     0,
    6462             :     false, /* HasDisjunctSubRegs */
    6463             :     false, /* CoveredBySubRegs */
    6464             :     FPR128_loSuperclasses,
    6465             :     nullptr
    6466             :   };
    6467             : 
    6468             :   extern const TargetRegisterClass ZPR_with_zsub_in_FPR128_loRegClass = {
    6469             :     &AArch64MCRegisterClasses[ZPR_with_zsub_in_FPR128_loRegClassID],
    6470             :     ZPR_with_zsub_in_FPR128_loSubClassMask,
    6471             :     SuperRegIdxSeqs + 5,
    6472             :     LaneBitmask(0x00000041),
    6473             :     0,
    6474             :     true, /* HasDisjunctSubRegs */
    6475             :     false, /* CoveredBySubRegs */
    6476             :     ZPR_with_zsub_in_FPR128_loSuperclasses,
    6477             :     nullptr
    6478             :   };
    6479             : 
    6480             :   extern const TargetRegisterClass DDDRegClass = {
    6481             :     &AArch64MCRegisterClasses[DDDRegClassID],
    6482             :     DDDSubClassMask,
    6483             :     SuperRegIdxSeqs + 83,
    6484             :     LaneBitmask(0x00000281),
    6485             :     0,
    6486             :     true, /* HasDisjunctSubRegs */
    6487             :     true, /* CoveredBySubRegs */
    6488             :     NullRegClasses,
    6489             :     nullptr
    6490             :   };
    6491             : 
    6492             :   extern const TargetRegisterClass DDDDRegClass = {
    6493             :     &AArch64MCRegisterClasses[DDDDRegClassID],
    6494             :     DDDDSubClassMask,
    6495             :     SuperRegIdxSeqs + 71,
    6496             :     LaneBitmask(0x00000381),
    6497             :     0,
    6498             :     true, /* HasDisjunctSubRegs */
    6499             :     true, /* CoveredBySubRegs */
    6500             :     NullRegClasses,
    6501             :     nullptr
    6502             :   };
    6503             : 
    6504             :   extern const TargetRegisterClass QQRegClass = {
    6505             :     &AArch64MCRegisterClasses[QQRegClassID],
    6506             :     QQSubClassMask,
    6507             :     SuperRegIdxSeqs + 105,
    6508             :     LaneBitmask(0x00000401),
    6509             :     0,
    6510             :     true, /* HasDisjunctSubRegs */
    6511             :     true, /* CoveredBySubRegs */
    6512             :     NullRegClasses,
    6513             :     nullptr
    6514             :   };
    6515             : 
    6516             :   extern const TargetRegisterClass ZPR2RegClass = {
    6517             :     &AArch64MCRegisterClasses[ZPR2RegClassID],
    6518             :     ZPR2SubClassMask,
    6519             :     SuperRegIdxSeqs + 79,
    6520             :     LaneBitmask(0x0000C041),
    6521             :     0,
    6522             :     true, /* HasDisjunctSubRegs */
    6523             :     true, /* CoveredBySubRegs */
    6524             :     NullRegClasses,
    6525             :     nullptr
    6526             :   };
    6527             : 
    6528             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass = {
    6529             :     &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_loRegClassID],
    6530             :     QQ_with_qsub0_in_FPR128_loSubClassMask,
    6531             :     SuperRegIdxSeqs + 105,
    6532             :     LaneBitmask(0x00000401),
    6533             :     0,
    6534             :     true, /* HasDisjunctSubRegs */
    6535             :     true, /* CoveredBySubRegs */
    6536             :     QQ_with_qsub0_in_FPR128_loSuperclasses,
    6537             :     nullptr
    6538             :   };
    6539             : 
    6540             :   extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass = {
    6541             :     &AArch64MCRegisterClasses[QQ_with_qsub1_in_FPR128_loRegClassID],
    6542             :     QQ_with_qsub1_in_FPR128_loSubClassMask,
    6543             :     SuperRegIdxSeqs + 105,
    6544             :     LaneBitmask(0x00000401),
    6545             :     0,
    6546             :     true, /* HasDisjunctSubRegs */
    6547             :     true, /* CoveredBySubRegs */
    6548             :     QQ_with_qsub1_in_FPR128_loSuperclasses,
    6549             :     nullptr
    6550             :   };
    6551             : 
    6552             :   extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6553             :     &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6554             :     ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6555             :     SuperRegIdxSeqs + 79,
    6556             :     LaneBitmask(0x0000C041),
    6557             :     0,
    6558             :     true, /* HasDisjunctSubRegs */
    6559             :     true, /* CoveredBySubRegs */
    6560             :     ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6561             :     nullptr
    6562             :   };
    6563             : 
    6564             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass = {
    6565             :     &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_loRegClassID],
    6566             :     ZPR2_with_zsub_in_FPR128_loSubClassMask,
    6567             :     SuperRegIdxSeqs + 79,
    6568             :     LaneBitmask(0x0000C041),
    6569             :     0,
    6570             :     true, /* HasDisjunctSubRegs */
    6571             :     true, /* CoveredBySubRegs */
    6572             :     ZPR2_with_zsub_in_FPR128_loSuperclasses,
    6573             :     nullptr
    6574             :   };
    6575             : 
    6576             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass = {
    6577             :     &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID],
    6578             :     QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask,
    6579             :     SuperRegIdxSeqs + 105,
    6580             :     LaneBitmask(0x00000401),
    6581             :     0,
    6582             :     true, /* HasDisjunctSubRegs */
    6583             :     true, /* CoveredBySubRegs */
    6584             :     QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses,
    6585             :     nullptr
    6586             :   };
    6587             : 
    6588             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6589             :     &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6590             :     ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6591             :     SuperRegIdxSeqs + 79,
    6592             :     LaneBitmask(0x0000C041),
    6593             :     0,
    6594             :     true, /* HasDisjunctSubRegs */
    6595             :     true, /* CoveredBySubRegs */
    6596             :     ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6597             :     nullptr
    6598             :   };
    6599             : 
    6600             :   extern const TargetRegisterClass QQQRegClass = {
    6601             :     &AArch64MCRegisterClasses[QQQRegClassID],
    6602             :     QQQSubClassMask,
    6603             :     SuperRegIdxSeqs + 90,
    6604             :     LaneBitmask(0x00001401),
    6605             :     0,
    6606             :     true, /* HasDisjunctSubRegs */
    6607             :     true, /* CoveredBySubRegs */
    6608             :     NullRegClasses,
    6609             :     nullptr
    6610             :   };
    6611             : 
    6612             :   extern const TargetRegisterClass ZPR3RegClass = {
    6613             :     &AArch64MCRegisterClasses[ZPR3RegClassID],
    6614             :     ZPR3SubClassMask,
    6615             :     SuperRegIdxSeqs + 76,
    6616             :     LaneBitmask(0x000CC041),
    6617             :     0,
    6618             :     true, /* HasDisjunctSubRegs */
    6619             :     true, /* CoveredBySubRegs */
    6620             :     NullRegClasses,
    6621             :     nullptr
    6622             :   };
    6623             : 
    6624             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass = {
    6625             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_loRegClassID],
    6626             :     QQQ_with_qsub0_in_FPR128_loSubClassMask,
    6627             :     SuperRegIdxSeqs + 90,
    6628             :     LaneBitmask(0x00001401),
    6629             :     0,
    6630             :     true, /* HasDisjunctSubRegs */
    6631             :     true, /* CoveredBySubRegs */
    6632             :     QQQ_with_qsub0_in_FPR128_loSuperclasses,
    6633             :     nullptr
    6634             :   };
    6635             : 
    6636             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass = {
    6637             :     &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_loRegClassID],
    6638             :     QQQ_with_qsub1_in_FPR128_loSubClassMask,
    6639             :     SuperRegIdxSeqs + 90,
    6640             :     LaneBitmask(0x00001401),
    6641             :     0,
    6642             :     true, /* HasDisjunctSubRegs */
    6643             :     true, /* CoveredBySubRegs */
    6644             :     QQQ_with_qsub1_in_FPR128_loSuperclasses,
    6645             :     nullptr
    6646             :   };
    6647             : 
    6648             :   extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass = {
    6649             :     &AArch64MCRegisterClasses[QQQ_with_qsub2_in_FPR128_loRegClassID],
    6650             :     QQQ_with_qsub2_in_FPR128_loSubClassMask,
    6651             :     SuperRegIdxSeqs + 90,
    6652             :     LaneBitmask(0x00001401),
    6653             :     0,
    6654             :     true, /* HasDisjunctSubRegs */
    6655             :     true, /* CoveredBySubRegs */
    6656             :     QQQ_with_qsub2_in_FPR128_loSuperclasses,
    6657             :     nullptr
    6658             :   };
    6659             : 
    6660             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6661             :     &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6662             :     ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6663             :     SuperRegIdxSeqs + 76,
    6664             :     LaneBitmask(0x000CC041),
    6665             :     0,
    6666             :     true, /* HasDisjunctSubRegs */
    6667             :     true, /* CoveredBySubRegs */
    6668             :     ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6669             :     nullptr
    6670             :   };
    6671             : 
    6672             :   extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6673             :     &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6674             :     ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6675             :     SuperRegIdxSeqs + 76,
    6676             :     LaneBitmask(0x000CC041),
    6677             :     0,
    6678             :     true, /* HasDisjunctSubRegs */
    6679             :     true, /* CoveredBySubRegs */
    6680             :     ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6681             :     nullptr
    6682             :   };
    6683             : 
    6684             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass = {
    6685             :     &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_loRegClassID],
    6686             :     ZPR3_with_zsub_in_FPR128_loSubClassMask,
    6687             :     SuperRegIdxSeqs + 76,
    6688             :     LaneBitmask(0x000CC041),
    6689             :     0,
    6690             :     true, /* HasDisjunctSubRegs */
    6691             :     true, /* CoveredBySubRegs */
    6692             :     ZPR3_with_zsub_in_FPR128_loSuperclasses,
    6693             :     nullptr
    6694             :   };
    6695             : 
    6696             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass = {
    6697             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID],
    6698             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask,
    6699             :     SuperRegIdxSeqs + 90,
    6700             :     LaneBitmask(0x00001401),
    6701             :     0,
    6702             :     true, /* HasDisjunctSubRegs */
    6703             :     true, /* CoveredBySubRegs */
    6704             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses,
    6705             :     nullptr
    6706             :   };
    6707             : 
    6708             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
    6709             :     &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
    6710             :     QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
    6711             :     SuperRegIdxSeqs + 90,
    6712             :     LaneBitmask(0x00001401),
    6713             :     0,
    6714             :     true, /* HasDisjunctSubRegs */
    6715             :     true, /* CoveredBySubRegs */
    6716             :     QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
    6717             :     nullptr
    6718             :   };
    6719             : 
    6720             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6721             :     &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6722             :     ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6723             :     SuperRegIdxSeqs + 76,
    6724             :     LaneBitmask(0x000CC041),
    6725             :     0,
    6726             :     true, /* HasDisjunctSubRegs */
    6727             :     true, /* CoveredBySubRegs */
    6728             :     ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6729             :     nullptr
    6730             :   };
    6731             : 
    6732             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6733             :     &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6734             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6735             :     SuperRegIdxSeqs + 76,
    6736             :     LaneBitmask(0x000CC041),
    6737             :     0,
    6738             :     true, /* HasDisjunctSubRegs */
    6739             :     true, /* CoveredBySubRegs */
    6740             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6741             :     nullptr
    6742             :   };
    6743             : 
    6744             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
    6745             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
    6746             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
    6747             :     SuperRegIdxSeqs + 90,
    6748             :     LaneBitmask(0x00001401),
    6749             :     0,
    6750             :     true, /* HasDisjunctSubRegs */
    6751             :     true, /* CoveredBySubRegs */
    6752             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
    6753             :     nullptr
    6754             :   };
    6755             : 
    6756             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6757             :     &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6758             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6759             :     SuperRegIdxSeqs + 76,
    6760             :     LaneBitmask(0x000CC041),
    6761             :     0,
    6762             :     true, /* HasDisjunctSubRegs */
    6763             :     true, /* CoveredBySubRegs */
    6764             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6765             :     nullptr
    6766             :   };
    6767             : 
    6768             :   extern const TargetRegisterClass QQQQRegClass = {
    6769             :     &AArch64MCRegisterClasses[QQQQRegClassID],
    6770             :     QQQQSubClassMask,
    6771             :     SuperRegIdxSeqs + 74,
    6772             :     LaneBitmask(0x00001C01),
    6773             :     0,
    6774             :     true, /* HasDisjunctSubRegs */
    6775             :     true, /* CoveredBySubRegs */
    6776             :     NullRegClasses,
    6777             :     nullptr
    6778             :   };
    6779             : 
    6780             :   extern const TargetRegisterClass ZPR4RegClass = {
    6781             :     &AArch64MCRegisterClasses[ZPR4RegClassID],
    6782             :     ZPR4SubClassMask,
    6783             :     SuperRegIdxSeqs + 1,
    6784             :     LaneBitmask(0x000FC041),
    6785             :     0,
    6786             :     true, /* HasDisjunctSubRegs */
    6787             :     true, /* CoveredBySubRegs */
    6788             :     NullRegClasses,
    6789             :     nullptr
    6790             :   };
    6791             : 
    6792             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass = {
    6793             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_loRegClassID],
    6794             :     QQQQ_with_qsub0_in_FPR128_loSubClassMask,
    6795             :     SuperRegIdxSeqs + 74,
    6796             :     LaneBitmask(0x00001C01),
    6797             :     0,
    6798             :     true, /* HasDisjunctSubRegs */
    6799             :     true, /* CoveredBySubRegs */
    6800             :     QQQQ_with_qsub0_in_FPR128_loSuperclasses,
    6801             :     nullptr
    6802             :   };
    6803             : 
    6804             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass = {
    6805             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_loRegClassID],
    6806             :     QQQQ_with_qsub1_in_FPR128_loSubClassMask,
    6807             :     SuperRegIdxSeqs + 74,
    6808             :     LaneBitmask(0x00001C01),
    6809             :     0,
    6810             :     true, /* HasDisjunctSubRegs */
    6811             :     true, /* CoveredBySubRegs */
    6812             :     QQQQ_with_qsub1_in_FPR128_loSuperclasses,
    6813             :     nullptr
    6814             :   };
    6815             : 
    6816             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass = {
    6817             :     &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_loRegClassID],
    6818             :     QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    6819             :     SuperRegIdxSeqs + 74,
    6820             :     LaneBitmask(0x00001C01),
    6821             :     0,
    6822             :     true, /* HasDisjunctSubRegs */
    6823             :     true, /* CoveredBySubRegs */
    6824             :     QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    6825             :     nullptr
    6826             :   };
    6827             : 
    6828             :   extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass = {
    6829             :     &AArch64MCRegisterClasses[QQQQ_with_qsub3_in_FPR128_loRegClassID],
    6830             :     QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    6831             :     SuperRegIdxSeqs + 74,
    6832             :     LaneBitmask(0x00001C01),
    6833             :     0,
    6834             :     true, /* HasDisjunctSubRegs */
    6835             :     true, /* CoveredBySubRegs */
    6836             :     QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    6837             :     nullptr
    6838             :   };
    6839             : 
    6840             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6841             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6842             :     ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6843             :     SuperRegIdxSeqs + 1,
    6844             :     LaneBitmask(0x000FC041),
    6845             :     0,
    6846             :     true, /* HasDisjunctSubRegs */
    6847             :     true, /* CoveredBySubRegs */
    6848             :     ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6849             :     nullptr
    6850             :   };
    6851             : 
    6852             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6853             :     &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6854             :     ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6855             :     SuperRegIdxSeqs + 1,
    6856             :     LaneBitmask(0x000FC041),
    6857             :     0,
    6858             :     true, /* HasDisjunctSubRegs */
    6859             :     true, /* CoveredBySubRegs */
    6860             :     ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6861             :     nullptr
    6862             :   };
    6863             : 
    6864             :   extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6865             :     &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6866             :     ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6867             :     SuperRegIdxSeqs + 1,
    6868             :     LaneBitmask(0x000FC041),
    6869             :     0,
    6870             :     true, /* HasDisjunctSubRegs */
    6871             :     true, /* CoveredBySubRegs */
    6872             :     ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6873             :     nullptr
    6874             :   };
    6875             : 
    6876             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass = {
    6877             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_loRegClassID],
    6878             :     ZPR4_with_zsub_in_FPR128_loSubClassMask,
    6879             :     SuperRegIdxSeqs + 1,
    6880             :     LaneBitmask(0x000FC041),
    6881             :     0,
    6882             :     true, /* HasDisjunctSubRegs */
    6883             :     true, /* CoveredBySubRegs */
    6884             :     ZPR4_with_zsub_in_FPR128_loSuperclasses,
    6885             :     nullptr
    6886             :   };
    6887             : 
    6888             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass = {
    6889             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID],
    6890             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask,
    6891             :     SuperRegIdxSeqs + 74,
    6892             :     LaneBitmask(0x00001C01),
    6893             :     0,
    6894             :     true, /* HasDisjunctSubRegs */
    6895             :     true, /* CoveredBySubRegs */
    6896             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses,
    6897             :     nullptr
    6898             :   };
    6899             : 
    6900             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
    6901             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
    6902             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    6903             :     SuperRegIdxSeqs + 74,
    6904             :     LaneBitmask(0x00001C01),
    6905             :     0,
    6906             :     true, /* HasDisjunctSubRegs */
    6907             :     true, /* CoveredBySubRegs */
    6908             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    6909             :     nullptr
    6910             :   };
    6911             : 
    6912             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    6913             :     &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    6914             :     QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    6915             :     SuperRegIdxSeqs + 74,
    6916             :     LaneBitmask(0x00001C01),
    6917             :     0,
    6918             :     true, /* HasDisjunctSubRegs */
    6919             :     true, /* CoveredBySubRegs */
    6920             :     QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    6921             :     nullptr
    6922             :   };
    6923             : 
    6924             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6925             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6926             :     ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6927             :     SuperRegIdxSeqs + 1,
    6928             :     LaneBitmask(0x000FC041),
    6929             :     0,
    6930             :     true, /* HasDisjunctSubRegs */
    6931             :     true, /* CoveredBySubRegs */
    6932             :     ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6933             :     nullptr
    6934             :   };
    6935             : 
    6936             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6937             :     &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6938             :     ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6939             :     SuperRegIdxSeqs + 1,
    6940             :     LaneBitmask(0x000FC041),
    6941             :     0,
    6942             :     true, /* HasDisjunctSubRegs */
    6943             :     true, /* CoveredBySubRegs */
    6944             :     ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6945             :     nullptr
    6946             :   };
    6947             : 
    6948             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6949             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6950             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6951             :     SuperRegIdxSeqs + 1,
    6952             :     LaneBitmask(0x000FC041),
    6953             :     0,
    6954             :     true, /* HasDisjunctSubRegs */
    6955             :     true, /* CoveredBySubRegs */
    6956             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6957             :     nullptr
    6958             :   };
    6959             : 
    6960             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
    6961             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
    6962             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    6963             :     SuperRegIdxSeqs + 74,
    6964             :     LaneBitmask(0x00001C01),
    6965             :     0,
    6966             :     true, /* HasDisjunctSubRegs */
    6967             :     true, /* CoveredBySubRegs */
    6968             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    6969             :     nullptr
    6970             :   };
    6971             : 
    6972             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    6973             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    6974             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    6975             :     SuperRegIdxSeqs + 74,
    6976             :     LaneBitmask(0x00001C01),
    6977             :     0,
    6978             :     true, /* HasDisjunctSubRegs */
    6979             :     true, /* CoveredBySubRegs */
    6980             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    6981             :     nullptr
    6982             :   };
    6983             : 
    6984             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6985             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6986             :     ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6987             :     SuperRegIdxSeqs + 1,
    6988             :     LaneBitmask(0x000FC041),
    6989             :     0,
    6990             :     true, /* HasDisjunctSubRegs */
    6991             :     true, /* CoveredBySubRegs */
    6992             :     ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    6993             :     nullptr
    6994             :   };
    6995             : 
    6996             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    6997             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    6998             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    6999             :     SuperRegIdxSeqs + 1,
    7000             :     LaneBitmask(0x000FC041),
    7001             :     0,
    7002             :     true, /* HasDisjunctSubRegs */
    7003             :     true, /* CoveredBySubRegs */
    7004             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    7005             :     nullptr
    7006             :   };
    7007             : 
    7008             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    7009             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    7010             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    7011             :     SuperRegIdxSeqs + 74,
    7012             :     LaneBitmask(0x00001C01),
    7013             :     0,
    7014             :     true, /* HasDisjunctSubRegs */
    7015             :     true, /* CoveredBySubRegs */
    7016             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    7017             :     nullptr
    7018             :   };
    7019             : 
    7020             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass = {
    7021             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClassID],
    7022             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSubClassMask,
    7023             :     SuperRegIdxSeqs + 1,
    7024             :     LaneBitmask(0x000FC041),
    7025             :     0,
    7026             :     true, /* HasDisjunctSubRegs */
    7027             :     true, /* CoveredBySubRegs */
    7028             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loSuperclasses,
    7029             :     nullptr
    7030             :   };
    7031             : 
    7032             : } // end namespace AArch64
    7033             : 
    7034             : namespace {
    7035             :   const TargetRegisterClass* const RegisterClasses[] = {
    7036             :     &AArch64::FPR8RegClass,
    7037             :     &AArch64::FPR16RegClass,
    7038             :     &AArch64::PPRRegClass,
    7039             :     &AArch64::PPR_3bRegClass,
    7040             :     &AArch64::GPR32allRegClass,
    7041             :     &AArch64::FPR32RegClass,
    7042             :     &AArch64::GPR32RegClass,
    7043             :     &AArch64::GPR32spRegClass,
    7044             :     &AArch64::GPR32commonRegClass,
    7045             :     &AArch64::CCRRegClass,
    7046             :     &AArch64::GPR32sponlyRegClass,
    7047             :     &AArch64::WSeqPairsClassRegClass,
    7048             :     &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
    7049             :     &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    7050             :     &AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    7051             :     &AArch64::GPR64allRegClass,
    7052             :     &AArch64::FPR64RegClass,
    7053             :     &AArch64::GPR64RegClass,
    7054             :     &AArch64::GPR64spRegClass,
    7055             :     &AArch64::GPR64commonRegClass,
    7056             :     &AArch64::tcGPR64RegClass,
    7057             :     &AArch64::GPR64sponlyRegClass,
    7058             :     &AArch64::DDRegClass,
    7059             :     &AArch64::XSeqPairsClassRegClass,
    7060             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    7061             :     &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    7062             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    7063             :     &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
    7064             :     &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    7065             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    7066             :     &AArch64::FPR128RegClass,
    7067             :     &AArch64::ZPRRegClass,
    7068             :     &AArch64::FPR128_loRegClass,
    7069             :     &AArch64::ZPR_with_zsub_in_FPR128_loRegClass,
    7070             :     &AArch64::DDDRegClass,
    7071             :     &AArch64::DDDDRegClass,
    7072             :     &AArch64::QQRegClass,
    7073             :     &AArch64::ZPR2RegClass,
    7074             :     &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
    7075             :     &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
    7076             :     &AArch64::ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7077             :     &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
    7078             :     &AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass,
    7079             :     &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7080             :     &AArch64::QQQRegClass,
    7081             :     &AArch64::ZPR3RegClass,
    7082             :     &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    7083             :     &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    7084             :     &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    7085             :     &AArch64::ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7086             :     &AArch64::ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7087             :     &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    7088             :     &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
    7089             :     &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    7090             :     &AArch64::ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7091             :     &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7092             :     &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    7093             :     &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7094             :     &AArch64::QQQQRegClass,
    7095             :     &AArch64::ZPR4RegClass,
    7096             :     &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    7097             :     &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    7098             :     &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    7099             :     &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    7100             :     &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7101             :     &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7102             :     &AArch64::ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7103             :     &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    7104             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    7105             :     &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    7106             :     &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    7107             :     &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7108             :     &AArch64::ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7109             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7110             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    7111             :     &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    7112             :     &AArch64::ZPR4_with_zsub1_in_ZPR_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7113             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7114             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    7115             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_with_zsub_in_FPR128_loRegClass,
    7116             :   };
    7117             : } // end anonymous namespace
    7118             : 
    7119             : static const TargetRegisterInfoDesc AArch64RegInfoDesc[] = { // Extra Descriptors
    7120             :   { 0, false },
    7121             :   { 0, false },
    7122             :   { 0, true },
    7123             :   { 0, true },
    7124             :   { 0, false },
    7125             :   { 0, true },
    7126             :   { 0, true },
    7127             :   { 0, true },
    7128             :   { 0, true },
    7129             :   { 0, true },
    7130             :   { 0, true },
    7131             :   { 0, true },
    7132             :   { 0, true },
    7133             :   { 0, true },
    7134             :   { 0, true },
    7135             :   { 0, true },
    7136             :   { 0, true },
    7137             :   { 0, true },
    7138             :   { 0, true },
    7139             :   { 0, true },
    7140             :   { 0, true },
    7141             :   { 0, true },
    7142             :   { 0, true },
    7143             :   { 0, true },
    7144             :   { 0, true },
    7145             :   { 0, true },
    7146             :   { 0, true },
    7147             :   { 0, true },
    7148             :   { 0, true },
    7149             :   { 0, true },
    7150             :   { 0, true },
    7151             :   { 0, true },
    7152             :   { 0, true },
    7153             :   { 0, true },
    7154             :   { 0, true },
    7155             :   { 0, true },
    7156             :   { 0, true },
    7157             :   { 0, true },
    7158             :   { 0, true },
    7159             :   { 0, true },
    7160             :   { 0, true },
    7161             :   { 0, true },
    7162             :   { 0, true },
    7163             :   { 0, true },
    7164             :   { 0, true },
    7165             :   { 0, true },
    7166             :   { 0, true },
    7167             :   { 0, true },
    7168             :   { 0, true },
    7169             :   { 0, true },
    7170             :   { 0, true },
    7171             :   { 0, true },
    7172             :   { 0, true },
    7173             :   { 0, true },
    7174             :   { 0, true },
    7175             :   { 0, true },
    7176             :   { 0, true },
    7177             :   { 0, true },
    7178             :   { 0, true },
    7179             :   { 0, true },
    7180             :   { 0, true },
    7181             :   { 0, true },
    7182             :   { 0, true },
    7183             :   { 0, true },
    7184             :   { 0, true },
    7185             :   { 0, true },
    7186             :   { 0, true },
    7187             :   { 0, true },
    7188             :   { 0, true },
    7189             :   { 0, true },
    7190             :   { 0, true },
    7191             :   { 0, true },
    7192             :   { 0, true },
    7193             :   { 0, true },
    7194             :   { 0, true },
    7195             :   { 0, true },
    7196             :   { 0, true },
    7197             :   { 0, true },
    7198             :   { 0, true },
    7199             :   { 0, true },
    7200             :   { 0, true },
    7201             :   { 0, true },
    7202             :   { 0, true },
    7203             :   { 0, true },
    7204             :   { 0, true },
    7205             :   { 0, true },
    7206             :   { 0, true },
    7207             :   { 0, true },
    7208             :   { 0, true },
    7209             :   { 0, true },
    7210             :   { 0, true },
    7211             :   { 0, true },
    7212             :   { 0, true },
    7213             :   { 0, true },
    7214             :   { 0, true },
    7215             :   { 0, true },
    7216             :   { 0, true },
    7217             :   { 0, true },
    7218             :   { 0, true },
    7219             :   { 0, true },
    7220             :   { 0, true },
    7221             :   { 0, true },
    7222             :   { 0, true },
    7223             :   { 0, true },
    7224             :   { 0, true },
    7225             :   { 0, true },
    7226             :   { 0, true },
    7227             :   { 0, true },
    7228             :   { 0, true },
    7229             :   { 0, true },
    7230             :   { 0, true },
    7231             :   { 0, true },
    7232             :   { 0, true },
    7233             :   { 0, true },
    7234             :   { 0, true },
    7235             :   { 0, true },
    7236             :   { 0, true },
    7237             :   { 0, true },
    7238             :   { 0, true },
    7239             :   { 0, true },
    7240             :   { 0, true },
    7241             :   { 0, true },
    7242             :   { 0, true },
    7243             :   { 0, true },
    7244             :   { 0, true },
    7245             :   { 0, true },
    7246             :   { 0, true },
    7247             :   { 0, true },
    7248             :   { 0, true },
    7249             :   { 0, true },
    7250             :   { 0, true },
    7251             :   { 0, true },
    7252             :   { 0, true },
    7253             :   { 0, true },
    7254             :   { 0, true },
    7255             :   { 0, true },
    7256             :   { 0, true },
    7257             :   { 0, true },
    7258             :   { 0, true },
    7259             :   { 0, true },
    7260             :   { 0, true },
    7261             :   { 0, true },
    7262             :   { 0, true },
    7263             :   { 0, true },
    7264             :   { 0, true },
    7265             :   { 0, true },
    7266             :   { 0, true },
    7267             :   { 0, true },
    7268             :   { 0, true },
    7269             :   { 0, true },
    7270             :   { 0, true },
    7271             :   { 0, true },
    7272             :   { 0, true },
    7273             :   { 0, true },
    7274             :   { 0, true },
    7275             :   { 0, true },
    7276             :   { 0, true },
    7277             :   { 0, true },
    7278             :   { 0, true },
    7279             :   { 0, true },
    7280             :   { 0, true },
    7281             :   { 0, true },
    7282             :   { 0, true },
    7283             :   { 0, true },
    7284             :   { 0, true },
    7285             :   { 0, true },
    7286             :   { 0, true },
    7287             :   { 0, true },
    7288             :   { 0, true },
    7289             :   { 0, true },
    7290             :   { 0, true },
    7291             :   { 0, true },
    7292             :   { 0, true },
    7293             :   { 0, true },
    7294             :   { 0, true },
    7295             :   { 0, true },
    7296             :   { 0, true },
    7297             :   { 0, true },
    7298             :   { 0, true },
    7299             :   { 0, true },
    7300             :   { 0, true },
    7301             :   { 0, true },
    7302             :   { 0, true },
    7303             :   { 0, true },
    7304             :   { 0, true },
    7305             :   { 0, true },
    7306             :   { 0, true },
    7307             :   { 0, true },
    7308             :   { 0, true },
    7309             :   { 0, true },
    7310             :   { 0, true },
    7311             :   { 0, true },
    7312             :   { 0, true },
    7313             :   { 0, true },
    7314             :   { 0, true },
    7315             :   { 0, true },
    7316             :   { 0, true },
    7317             :   { 0, true },
    7318             :   { 0, true },
    7319             :   { 0, true },
    7320             :   { 0, true },
    7321             :   { 0, true },
    7322             :   { 0, true },
    7323             :   { 0, true },
    7324             :   { 0, true },
    7325             :   { 0, true },
    7326             :   { 0, true },
    7327             :   { 0, true },
    7328             :   { 0, true },
    7329             :   { 0, true },
    7330             :   { 0, true },
    7331             :   { 0, true },
    7332             :   { 0, true },
    7333             :   { 0, true },
    7334             :   { 0, true },
    7335             :   { 0, true },
    7336             :   { 0, true },
    7337             :   { 0, true },
    7338             :   { 0, true },
    7339             :   { 0, true },
    7340             :   { 0, true },
    7341             :   { 0, true },
    7342             :   { 0, true },
    7343             :   { 0, true },
    7344             :   { 0, true },
    7345             :   { 0, true },
    7346             :   { 0, true },
    7347             :   { 0, true },
    7348             :   { 0, true },
    7349             :   { 0, true },
    7350             :   { 0, true },
    7351             :   { 0, true },
    7352             :   { 0, true },
    7353             :   { 0, true },
    7354             :   { 0, true },
    7355             :   { 0, true },
    7356             :   { 0, true },
    7357             :   { 0, true },
    7358             :   { 0, true },
    7359             :   { 0, true },
    7360             :   { 0, true },
    7361             :   { 0, true },
    7362             :   { 0, true },
    7363             :   { 0, true },
    7364             :   { 0, true },
    7365             :   { 0, true },
    7366             :   { 0, true },
    7367             :   { 0, true },
    7368             :   { 0, true },
    7369             :   { 0, true },
    7370             :   { 0, true },
    7371             :   { 0, true },
    7372             :   { 0, true },
    7373             :   { 0, true },
    7374             :   { 0, true },
    7375             :   { 0, true },
    7376             :   { 0, true },
    7377             :   { 0, true },
    7378             :   { 0, true },
    7379             :   { 0, true },
    7380             :   { 0, true },
    7381             :   { 0, true },
    7382             :   { 0, true },
    7383             :   { 0, true },
    7384             :   { 0, true },
    7385             :   { 0, true },
    7386             :   { 0, true },
    7387             :   { 0, true },
    7388             :   { 0, true },
    7389             :   { 0, true },
    7390             :   { 0, true },
    7391             :   { 0, true },
    7392             :   { 0, true },
    7393             :   { 0, true },
    7394             :   { 0, true },
    7395             :   { 0, true },
    7396             :   { 0, true },
    7397             :   { 0, false },
    7398             :   { 0, false },
    7399             :   { 0, false },
    7400             :   { 0, false },
    7401             :   { 0, false },
    7402             :   { 0, false },
    7403             :   { 0, false },
    7404             :   { 0, false },
    7405             :   { 0, false },
    7406             :   { 0, false },
    7407             :   { 0, false },
    7408             :   { 0, false },
    7409             :   { 0, false },
    7410             :   { 0, false },
    7411             :   { 0, false },
    7412             :   { 0, false },
    7413             :   { 0, false },
    7414             :   { 0, false },
    7415             :   { 0, false },
    7416             :   { 0, false },
    7417             :   { 0, false },
    7418             :   { 0, false },
    7419             :   { 0, false },
    7420             :   { 0, false },
    7421             :   { 0, false },
    7422             :   { 0, false },
    7423             :   { 0, false },
    7424             :   { 0, false },
    7425             :   { 0, false },
    7426             :   { 0, false },
    7427             :   { 0, false },
    7428             :   { 0, false },
    7429             :   { 0, true },
    7430             :   { 0, true },
    7431             :   { 0, true },
    7432             :   { 0, true },
    7433             :   { 0, true },
    7434             :   { 0, true },
    7435             :   { 0, true },
    7436             :   { 0, true },
    7437             :   { 0, true },
    7438             :   { 0, true },
    7439             :   { 0, true },
    7440             :   { 0, true },
    7441             :   { 0, true },
    7442             :   { 0, true },
    7443             :   { 0, true },
    7444             :   { 0, true },
    7445             :   { 0, true },
    7446             :   { 0, true },
    7447             :   { 0, true },
    7448             :   { 0, true },
    7449             :   { 0, true },
    7450             :   { 0, true },
    7451             :   { 0, true },
    7452             :   { 0, true },
    7453             :   { 0, true },
    7454             :   { 0, true },
    7455             :   { 0, true },
    7456             :   { 0, true },
    7457             :   { 0, true },
    7458             :   { 0, true },
    7459             :   { 0, true },
    7460             :   { 0, true },
    7461             :   { 0, true },
    7462             :   { 0, true },
    7463             :   { 0, true },
    7464             :   { 0, true },
    7465             :   { 0, true },
    7466             :   { 0, true },
    7467             :   { 0, true },
    7468             :   { 0, true },
    7469             :   { 0, true },
    7470             :   { 0, true },
    7471             :   { 0, true },
    7472             :   { 0, true },
    7473             :   { 0, true },
    7474             :   { 0, true },
    7475             :   { 0, true },
    7476             :   { 0, true },
    7477             :   { 0, true },
    7478             :   { 0, true },
    7479             :   { 0, true },
    7480             :   { 0, true },
    7481             :   { 0, true },
    7482             :   { 0, true },
    7483             :   { 0, true },
    7484             :   { 0, true },
    7485             :   { 0, true },
    7486             :   { 0, true },
    7487             :   { 0, true },
    7488             :   { 0, true },
    7489             :   { 0, true },
    7490             :   { 0, true },
    7491             :   { 0, true },
    7492             :   { 0, true },
    7493             :   { 0, true },
    7494             :   { 0, true },
    7495             :   { 0, true },
    7496             :   { 0, true },
    7497             :   { 0, true },
    7498             :   { 0, true },
    7499             :   { 0, true },
    7500             :   { 0, true },
    7501             :   { 0, true },
    7502             :   { 0, true },
    7503             :   { 0, true },
    7504             :   { 0, true },
    7505             :   { 0, true },
    7506             :   { 0, true },
    7507             :   { 0, true },
    7508             :   { 0, true },
    7509             :   { 0, true },
    7510             :   { 0, true },
    7511             :   { 0, true },
    7512             :   { 0, true },
    7513             :   { 0, true },
    7514             :   { 0, true },
    7515             :   { 0, true },
    7516             :   { 0, true },
    7517             :   { 0, true },
    7518             :   { 0, true },
    7519             :   { 0, true },
    7520             :   { 0, true },
    7521             :   { 0, true },
    7522             :   { 0, true },
    7523             :   { 0, true },
    7524             :   { 0, true },
    7525             :   { 0, true },
    7526             :   { 0, true },
    7527             :   { 0, true },
    7528             :   { 0, true },
    7529             :   { 0, true },
    7530             :   { 0, true },
    7531             :   { 0, true },
    7532             :   { 0, true },
    7533             :   { 0, true },
    7534             :   { 0, true },
    7535             :   { 0, true },
    7536             :   { 0, true },
    7537             :   { 0, true },
    7538             :   { 0, true },
    7539             :   { 0, true },
    7540             :   { 0, true },
    7541             :   { 0, true },
    7542             :   { 0, true },
    7543             :   { 0, true },
    7544             :   { 0, true },
    7545             :   { 0, true },
    7546             :   { 0, true },
    7547             :   { 0, true },
    7548             :   { 0, true },
    7549             :   { 0, true },
    7550             :   { 0, true },
    7551             :   { 0, true },
    7552             :   { 0, true },
    7553             :   { 0, true },
    7554             :   { 0, true },
    7555             :   { 0, true },
    7556             :   { 0, true },
    7557             :   { 0, true },
    7558             :   { 0, true },
    7559             :   { 0, true },
    7560             :   { 0, true },
    7561             :   { 0, true },
    7562             :   { 0, true },
    7563             :   { 0, true },
    7564             :   { 0, true },
    7565             :   { 0, true },
    7566             :   { 0, true },
    7567             :   { 0, true },
    7568             :   { 0, true },
    7569             :   { 0, true },
    7570             :   { 0, true },
    7571             :   { 0, true },
    7572             :   { 0, true },
    7573             :   { 0, true },
    7574             :   { 0, true },
    7575             :   { 0, true },
    7576             :   { 0, true },
    7577             :   { 0, true },
    7578             :   { 0, true },
    7579             :   { 0, true },
    7580             :   { 0, true },
    7581             :   { 0, true },
    7582             :   { 0, true },
    7583             :   { 0, true },
    7584             :   { 0, true },
    7585             :   { 0, true },
    7586             :   { 0, true },
    7587             :   { 0, true },
    7588             :   { 0, true },
    7589             :   { 0, true },
    7590             :   { 0, true },
    7591             :   { 0, true },
    7592             :   { 0, true },
    7593             :   { 0, true },
    7594             :   { 0, true },
    7595             :   { 0, true },
    7596             :   { 0, true },
    7597             :   { 0, true },
    7598             :   { 0, true },
    7599             :   { 0, true },
    7600             :   { 0, true },
    7601             :   { 0, true },
    7602             :   { 0, true },
    7603             :   { 0, true },
    7604             :   { 0, true },
    7605             :   { 0, true },
    7606             :   { 0, true },
    7607             :   { 0, true },
    7608             :   { 0, true },
    7609             :   { 0, true },
    7610             :   { 0, true },
    7611             :   { 0, true },
    7612             :   { 0, true },
    7613             :   { 0, true },
    7614             :   { 0, true },
    7615             :   { 0, true },
    7616             :   { 0, true },
    7617             :   { 0, true },
    7618             :   { 0, true },
    7619             :   { 0, true },
    7620             :   { 0, true },
    7621             :   { 0, true },
    7622             :   { 0, true },
    7623             :   { 0, true },
    7624             :   { 0, true },
    7625             :   { 0, true },
    7626             :   { 0, true },
    7627             :   { 0, true },
    7628             :   { 0, true },
    7629             :   { 0, true },
    7630             :   { 0, true },
    7631             :   { 0, true },
    7632             :   { 0, true },
    7633             :   { 0, true },
    7634             :   { 0, true },
    7635             :   { 0, true },
    7636             :   { 0, true },
    7637             :   { 0, true },
    7638             :   { 0, true },
    7639             :   { 0, true },
    7640             :   { 0, true },
    7641             :   { 0, true },
    7642             :   { 0, true },
    7643             :   { 0, true },
    7644             :   { 0, true },
    7645             :   { 0, true },
    7646             :   { 0, true },
    7647             :   { 0, true },
    7648             :   { 0, true },
    7649             :   { 0, true },
    7650             :   { 0, true },
    7651             :   { 0, true },
    7652             :   { 0, true },
    7653             :   { 0, true },
    7654             :   { 0, true },
    7655             :   { 0, true },
    7656             :   { 0, true },
    7657             :   { 0, true },
    7658             :   { 0, true },
    7659             :   { 0, true },
    7660             :   { 0, true },
    7661             :   { 0, true },
    7662             :   { 0, true },
    7663             :   { 0, true },
    7664             :   { 0, true },
    7665             :   { 0, true },
    7666             :   { 0, true },
    7667             :   { 0, true },
    7668             :   { 0, true },
    7669             :   { 0, true },
    7670             :   { 0, true },
    7671             :   { 0, true },
    7672             :   { 0, true },
    7673             :   { 0, true },
    7674             :   { 0, true },
    7675             :   { 0, true },
    7676             :   { 0, true },
    7677             :   { 0, true },
    7678             :   { 0, true },
    7679             :   { 0, true },
    7680             :   { 0, true },
    7681             :   { 0, true },
    7682             :   { 0, true },
    7683             :   { 0, true },
    7684             :   { 0, true },
    7685             :   { 0, true },
    7686             :   { 0, true },
    7687             :   { 0, true },
    7688             :   { 0, true },
    7689             :   { 0, true },
    7690             :   { 0, true },
    7691             :   { 0, true },
    7692             :   { 0, true },
    7693             :   { 0, true },
    7694             :   { 0, true },
    7695             :   { 0, true },
    7696             :   { 0, true },
    7697             :   { 0, true },
    7698             :   { 0, true },
    7699             :   { 0, true },
    7700             :   { 0, true },
    7701             :   { 0, true },
    7702             :   { 0, true },
    7703             :   { 0, true },
    7704             :   { 0, true },
    7705             :   { 0, true },
    7706             :   { 0, true },
    7707             :   { 0, true },
    7708             :   { 0, true },
    7709             :   { 0, true },
    7710             :   { 0, true },
    7711             :   { 0, true },
    7712             :   { 0, true },
    7713             :   { 0, true },
    7714             :   { 0, true },
    7715             :   { 0, true },
    7716             :   { 0, true },
    7717             :   { 0, true },
    7718             :   { 0, true },
    7719             :   { 0, true },
    7720             :   { 0, true },
    7721             :   { 0, true },
    7722             :   { 0, true },
    7723             :   { 0, true },
    7724             :   { 0, true },
    7725             :   { 0, true },
    7726             :   { 0, true },
    7727             :   { 0, true },
    7728             :   { 0, true },
    7729             :   { 0, true },
    7730             :   { 0, true },
    7731             :   { 0, true },
    7732             :   { 0, true },
    7733             :   { 0, true },
    7734             :   { 0, true },
    7735             :   { 0, true },
    7736             :   { 0, true },
    7737             :   { 0, true },
    7738             :   { 0, true },
    7739             :   { 0, true },
    7740             :   { 0, true },
    7741             :   { 0, true },
    7742             :   { 0, true },
    7743             :   { 0, true },
    7744             :   { 0, true },
    7745             :   { 0, true },
    7746             :   { 0, true },
    7747             :   { 0, true },
    7748             :   { 0, true },
    7749             :   { 0, true },
    7750             :   { 0, true },
    7751             :   { 0, true },
    7752             :   { 0, true },
    7753             :   { 0, true },
    7754             :   { 0, true },
    7755             :   { 0, true },
    7756             :   { 0, true },
    7757             :   { 0, true },
    7758             :   { 0, true },
    7759             :   { 0, true },
    7760             :   { 0, true },
    7761             :   { 0, true },
    7762             :   { 0, true },
    7763             :   { 0, true },
    7764             :   { 0, true },
    7765             :   { 0, true },
    7766             :   { 0, true },
    7767             :   { 0, true },
    7768             :   { 0, true },
    7769             :   { 0, true },
    7770             :   { 0, true },
    7771             :   { 0, true },
    7772             :   { 0, true },
    7773             :   { 0, true },
    7774             :   { 0, true },
    7775             :   { 0, true },
    7776             :   { 0, true },
    7777             :   { 0, true },
    7778             :   { 0, true },
    7779             :   { 0, true },
    7780             :   { 0, true },
    7781             : };
    7782        1171 : unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
    7783             :   static const uint8_t RowMap[99] = {
    7784             :     0, 0, 0, 1, 2, 3, 0, 0, 0, 0, 4, 5, 6, 0, 0, 0, 0, 0, 1, 0, 0, 7, 8, 9, 0, 0, 1, 1, 0, 3, 3, 0, 2, 2, 0, 4, 4, 4, 0, 6, 6, 6, 0, 5, 5, 5, 0, 0, 7, 7, 7, 7, 0, 0, 9, 9, 9, 9, 0, 0, 8, 8, 8, 8, 0, 0, 0, 1, 1, 2, 10, 10, 10, 0, 0, 4, 4, 5, 4, 4, 5, 0, 11, 10, 11, 11, 10, 10, 0, 0, 7, 7, 8, 7, 7, 7, 7, 8, 8, 
    7785             :   };
    7786             :   static const uint8_t Rows[12][99] = {
    7787             :     { 1, 2, 3, 4, 5, 0, 7, 0, 0, 10, 11, 12, 0, 14, 15, 15, 0, 47, 0, 20, 21, 22, 23, 0, 25, 26, 27, 28, 0, 0, 0, 32, 33, 34, 35, 36, 37, 38, 0, 0, 0, 0, 43, 44, 45, 46, 0, 48, 49, 50, 51, 52, 53, 0, 0, 0, 0, 0, 0, 60, 61, 62, 63, 64, 65, 66, 0, 68, 0, 0, 71, 0, 73, 74, 0, 76, 0, 0, 79, 0, 0, 0, 83, 84, 0, 86, 0, 88, 89, 0, 91, 0, 0, 94, 0, 96, 0, 0, 0, },
    7788             :     { 26, 0, 4, 5, 6, 0, 27, 0, 0, 0, 0, 0, 0, 28, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 33, 34, 0, 0, 0, 29, 30, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 68, 0, 70, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7789             :     { 32, 0, 5, 6, 0, 0, 33, 0, 0, 0, 0, 0, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 30, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7790             :     { 29, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7791             :     { 35, 36, 36, 44, 40, 0, 37, 0, 0, 11, 12, 13, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 43, 45, 46, 0, 0, 0, 39, 41, 42, 43, 44, 45, 46, 0, 0, 0, 0, 39, 40, 41, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 79, 0, 81, 0, 0, 79, 0, 80, 76, 0, 78, 0, 0, 81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7792             :     { 43, 44, 44, 40, 0, 0, 45, 0, 0, 12, 13, 0, 0, 46, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 41, 42, 0, 0, 0, 0, 0, 0, 39, 40, 41, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7793             :     { 39, 40, 0, 0, 0, 0, 41, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7794             :     { 48, 49, 49, 61, 55, 0, 50, 0, 0, 52, 64, 58, 0, 51, 0, 0, 0, 0, 0, 52, 22, 23, 24, 0, 53, 60, 62, 63, 0, 0, 0, 54, 56, 57, 60, 61, 62, 63, 0, 0, 0, 0, 54, 55, 56, 57, 0, 60, 61, 62, 63, 64, 65, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 58, 59, 94, 0, 98, 0, 0, 94, 0, 95, 96, 0, 99, 0, 0, 98, 0, 0, 0, 94, 96, 0, 95, 0, 97, 91, 0, 93, 0, 0, 98, 0, 99, 0, 0, 0, },
    7795             :     { 60, 61, 61, 55, 0, 0, 62, 0, 0, 64, 58, 0, 0, 63, 0, 0, 0, 0, 0, 64, 23, 24, 0, 0, 65, 54, 56, 57, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 58, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7796             :     { 54, 55, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 57, 0, 0, 0, 0, 0, 58, 0, 0, 0, 0, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7797             :     { 1, 2, 2, 36, 44, 40, 7, 0, 0, 20, 52, 64, 58, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 35, 37, 38, 39, 41, 42, 43, 45, 46, 48, 49, 50, 51, 54, 55, 56, 57, 60, 61, 62, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 71, 73, 79, 80, 81, 83, 85, 86, 84, 88, 96, 97, 99, 94, 95, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7798             :     { 1, 0, 2, 49, 61, 55, 7, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 48, 50, 51, 54, 56, 57, 60, 62, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 83, 86, 94, 95, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7799             :   };
    7800             : 
    7801        1171 :   --IdxA; assert(IdxA < 99);
    7802        1171 :   --IdxB; assert(IdxB < 99);
    7803        1171 :   return Rows[RowMap[IdxA]][IdxB];
    7804             : }
    7805             : 
    7806             :   struct MaskRolOp {
    7807             :     LaneBitmask Mask;
    7808             :     uint8_t  RotateLeft;
    7809             :   };
    7810             :   static const MaskRolOp LaneMaskComposeSequences[] = {
    7811             :     { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    7812             :     { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    7813             :     { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    7814             :     { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    7815             :     { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    7816             :     { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    7817             :     { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    7818             :     { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    7819             :     { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
    7820             :     { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
    7821             :     { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
    7822             :     { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
    7823             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
    7824             :     { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000040), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 27
    7825             :     { LaneBitmask(0x00000001), 16 }, { LaneBitmask(0x00000040), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 30
    7826             :     { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 33
    7827             :     { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 35
    7828             :     { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 37
    7829             :     { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 39
    7830             :     { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 41
    7831             :     { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 },   // Sequence 43
    7832             :     { LaneBitmask(0xFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 },   // Sequence 45
    7833             :     { LaneBitmask(0xFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 },   // Sequence 47
    7834             :     { LaneBitmask(0x00000001),  7 }, { LaneBitmask(0x00000080),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 49
    7835             :     { LaneBitmask(0x00000001),  7 }, { LaneBitmask(0x00000080),  2 }, { LaneBitmask(0x00000200), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 52
    7836             :     { LaneBitmask(0x00000001),  9 }, { LaneBitmask(0x00000080),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 56
    7837             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 59
    7838             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000380),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 62
    7839             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000280),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 65
    7840             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 68
    7841             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400),  2 }, { LaneBitmask(0x00001000), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 71
    7842             :     { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000400),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 75
    7843             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 78
    7844             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080),  5 }, { LaneBitmask(0x00000200),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 81
    7845             :     { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000080),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 85
    7846             :     { LaneBitmask(0x00000010), 31 }, { LaneBitmask(0x00000020),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 88
    7847             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 91
    7848             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 94
    7849             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask(0x00000100),  8 }, { LaneBitmask(0x00000200),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 97
    7850             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask(0x00000200),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 102
    7851             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask(0x00000800),  5 }, { LaneBitmask(0x00001000),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 106
    7852             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask(0x00001000),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 111
    7853             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask(0x0000C000),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 115
    7854             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask(0x0000C000),  4 }, { LaneBitmask(0x000C0000), 30 }, { LaneBitmask::getNone(), 0 },   // Sequence 119
    7855             :     { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000040), 13 }, { LaneBitmask(0x0000C000),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 124
    7856             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000080), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 128
    7857             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000080), 11 }, { LaneBitmask(0x00000200),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 131
    7858             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000400),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 135
    7859             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000400),  8 }, { LaneBitmask(0x00001000),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 138
    7860             :     { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000080),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 142
    7861             :     { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000400),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 145
    7862             :   };
    7863             :   static const MaskRolOp *const CompositeSequences[] = {
    7864             :     &LaneMaskComposeSequences[0], // to bsub
    7865             :     &LaneMaskComposeSequences[0], // to dsub
    7866             :     &LaneMaskComposeSequences[0], // to dsub0
    7867             :     &LaneMaskComposeSequences[2], // to dsub1
    7868             :     &LaneMaskComposeSequences[4], // to dsub2
    7869             :     &LaneMaskComposeSequences[6], // to dsub3
    7870             :     &LaneMaskComposeSequences[0], // to hsub
    7871             :     &LaneMaskComposeSequences[8], // to qhisub
    7872             :     &LaneMaskComposeSequences[10], // to qsub
    7873             :     &LaneMaskComposeSequences[0], // to qsub0
    7874             :     &LaneMaskComposeSequences[12], // to qsub1
    7875             :     &LaneMaskComposeSequences[14], // to qsub2
    7876             :     &LaneMaskComposeSequences[16], // to qsub3
    7877             :     &LaneMaskComposeSequences[0], // to ssub
    7878             :     &LaneMaskComposeSequences[18], // to sub_32
    7879             :     &LaneMaskComposeSequences[20], // to sube32
    7880             :     &LaneMaskComposeSequences[0], // to sube64
    7881             :     &LaneMaskComposeSequences[22], // to subo32
    7882             :     &LaneMaskComposeSequences[12], // to subo64
    7883             :     &LaneMaskComposeSequences[0], // to zsub
    7884             :     &LaneMaskComposeSequences[0], // to zsub0
    7885             :     &LaneMaskComposeSequences[24], // to zsub1
    7886             :     &LaneMaskComposeSequences[27], // to zsub2
    7887             :     &LaneMaskComposeSequences[30], // to zsub3
    7888             :     &LaneMaskComposeSequences[33], // to zsub_hi
    7889             :     &LaneMaskComposeSequences[2], // to dsub1_then_bsub
    7890             :     &LaneMaskComposeSequences[2], // to dsub1_then_hsub
    7891             :     &LaneMaskComposeSequences[2], // to dsub1_then_ssub
    7892             :     &LaneMaskComposeSequences[6], // to dsub3_then_bsub
    7893             :     &LaneMaskComposeSequences[6], // to dsub3_then_hsub
    7894             :     &LaneMaskComposeSequences[6], // to dsub3_then_ssub
    7895             :     &LaneMaskComposeSequences[4], // to dsub2_then_bsub
    7896             :     &LaneMaskComposeSequences[4], // to dsub2_then_hsub
    7897             :     &LaneMaskComposeSequences[4], // to dsub2_then_ssub
    7898             :     &LaneMaskComposeSequences[12], // to qsub1_then_bsub
    7899             :     &LaneMaskComposeSequences[12], // to qsub1_then_dsub
    7900             :     &LaneMaskComposeSequences[12], // to qsub1_then_hsub
    7901             :     &LaneMaskComposeSequences[12], // to qsub1_then_ssub
    7902             :     &LaneMaskComposeSequences[16], // to qsub3_then_bsub
    7903             :     &LaneMaskComposeSequences[16], // to qsub3_then_dsub
    7904             :     &LaneMaskComposeSequences[16], // to qsub3_then_hsub
    7905             :     &LaneMaskComposeSequences[16], // to qsub3_then_ssub
    7906             :     &LaneMaskComposeSequences[14], // to qsub2_then_bsub
    7907             :     &LaneMaskComposeSequences[14], // to qsub2_then_dsub
    7908             :     &LaneMaskComposeSequences[14], // to qsub2_then_hsub
    7909             :     &LaneMaskComposeSequences[14], // to qsub2_then_ssub
    7910             :     &LaneMaskComposeSequences[35], // to subo64_then_sub_32
    7911             :     &LaneMaskComposeSequences[37], // to zsub1_then_bsub
    7912             :     &LaneMaskComposeSequences[37], // to zsub1_then_dsub
    7913             :     &LaneMaskComposeSequences[37], // to zsub1_then_hsub
    7914             :     &LaneMaskComposeSequences[37], // to zsub1_then_ssub
    7915             :     &LaneMaskComposeSequences[37], // to zsub1_then_zsub
    7916             :     &LaneMaskComposeSequences[39], // to zsub1_then_zsub_hi
    7917             :     &LaneMaskComposeSequences[41], // to zsub3_then_bsub
    7918             :     &LaneMaskComposeSequences[41], // to zsub3_then_dsub
    7919             :     &LaneMaskComposeSequences[41], // to zsub3_then_hsub
    7920             :     &LaneMaskComposeSequences[41], // to zsub3_then_ssub
    7921             :     &LaneMaskComposeSequences[41], // to zsub3_then_zsub
    7922             :     &LaneMaskComposeSequences[43], // to zsub3_then_zsub_hi
    7923             :     &LaneMaskComposeSequences[45], // to zsub2_then_bsub
    7924             :     &LaneMaskComposeSequences[45], // to zsub2_then_dsub
    7925             :     &LaneMaskComposeSequences[45], // to zsub2_then_hsub
    7926             :     &LaneMaskComposeSequences[45], // to zsub2_then_ssub
    7927             :     &LaneMaskComposeSequences[45], // to zsub2_then_zsub
    7928             :     &LaneMaskComposeSequences[47], // to zsub2_then_zsub_hi
    7929             :     &LaneMaskComposeSequences[0], // to dsub0_dsub1
    7930             :     &LaneMaskComposeSequences[0], // to dsub0_dsub1_dsub2
    7931             :     &LaneMaskComposeSequences[49], // to dsub1_dsub2
    7932             :     &LaneMaskComposeSequences[52], // to dsub1_dsub2_dsub3
    7933             :     &LaneMaskComposeSequences[56], // to dsub2_dsub3
    7934             :     &LaneMaskComposeSequences[59], // to dsub_qsub1_then_dsub
    7935             :     &LaneMaskComposeSequences[62], // to dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7936             :     &LaneMaskComposeSequences[65], // to dsub_qsub1_then_dsub_qsub2_then_dsub
    7937             :     &LaneMaskComposeSequences[0], // to qsub0_qsub1
    7938             :     &LaneMaskComposeSequences[0], // to qsub0_qsub1_qsub2
    7939             :     &LaneMaskComposeSequences[68], // to qsub1_qsub2
    7940             :     &LaneMaskComposeSequences[71], // to qsub1_qsub2_qsub3
    7941             :     &LaneMaskComposeSequences[75], // to qsub2_qsub3
    7942             :     &LaneMaskComposeSequences[78], // to qsub1_then_dsub_qsub2_then_dsub
    7943             :     &LaneMaskComposeSequences[81], // to qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    7944             :     &LaneMaskComposeSequences[85], // to qsub2_then_dsub_qsub3_then_dsub
    7945             :     &LaneMaskComposeSequences[88], // to sub_32_subo64_then_sub_32
    7946             :     &LaneMaskComposeSequences[91], // to dsub_zsub1_then_dsub
    7947             :     &LaneMaskComposeSequences[94], // to zsub_zsub1_then_zsub
    7948             :     &LaneMaskComposeSequences[97], // to dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    7949             :     &LaneMaskComposeSequences[102], // to dsub_zsub1_then_dsub_zsub2_then_dsub
    7950             :     &LaneMaskComposeSequences[106], // to zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    7951             :     &LaneMaskComposeSequences[111], // to zsub_zsub1_then_zsub_zsub2_then_zsub
    7952             :     &LaneMaskComposeSequences[0], // to zsub0_zsub1
    7953             :     &LaneMaskComposeSequences[0], // to zsub0_zsub1_zsub2
    7954             :     &LaneMaskComposeSequences[115], // to zsub1_zsub2
    7955             :     &LaneMaskComposeSequences[119], // to zsub1_zsub2_zsub3
    7956             :     &LaneMaskComposeSequences[124], // to zsub2_zsub3
    7957             :     &LaneMaskComposeSequences[128], // to zsub1_then_dsub_zsub2_then_dsub
    7958             :     &LaneMaskComposeSequences[131], // to zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    7959             :     &LaneMaskComposeSequences[135], // to zsub1_then_zsub_zsub2_then_zsub
    7960             :     &LaneMaskComposeSequences[138], // to zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    7961             :     &LaneMaskComposeSequences[142], // to zsub2_then_dsub_zsub3_then_dsub
    7962             :     &LaneMaskComposeSequences[145] // to zsub2_then_zsub_zsub3_then_zsub
    7963             :   };
    7964             : 
    7965           0 : LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
    7966           0 :   --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
    7967             :   LaneBitmask Result;
    7968           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    7969           0 :     LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    7970           0 :     if (unsigned S = Ops->RotateLeft)
    7971           0 :       Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    7972             :     else
    7973             :       Result |= LaneBitmask(M);
    7974             :   }
    7975           0 :   return Result;
    7976             : }
    7977             : 
    7978           0 : LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
    7979           0 :   LaneMask &= getSubRegIndexLaneMask(IdxA);
    7980           0 :   --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
    7981             :   LaneBitmask Result;
    7982           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    7983             :     LaneBitmask::Type M = LaneMask.getAsInteger();
    7984           0 :     if (unsigned S = Ops->RotateLeft)
    7985           0 :       Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    7986             :     else
    7987             :       Result |= LaneBitmask(M);
    7988             :   }
    7989           0 :   return Result;
    7990             : }
    7991             : 
    7992       33553 : const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
    7993             :   static const uint8_t Table[80][99] = {
    7994             :     {   // FPR8
    7995             :       0,        // bsub
    7996             :       0,        // dsub
    7997             :       0,        // dsub0
    7998             :       0,        // dsub1
    7999             :       0,        // dsub2
    8000             :       0,        // dsub3
    8001             :       0,        // hsub
    8002             :       0,        // qhisub
    8003             :       0,        // qsub
    8004             :       0,        // qsub0
    8005             :       0,        // qsub1
    8006             :       0,        // qsub2
    8007             :       0,        // qsub3
    8008             :       0,        // ssub
    8009             :       0,        // sub_32
    8010             :       0,        // sube32
    8011             :       0,        // sube64
    8012             :       0,        // subo32
    8013             :       0,        // subo64
    8014             :       0,        // zsub
    8015             :       0,        // zsub0
    8016             :       0,        // zsub1
    8017             :       0,        // zsub2
    8018             :       0,        // zsub3
    8019             :       0,        // zsub_hi
    8020             :       0,        // dsub1_then_bsub
    8021             :       0,        // dsub1_then_hsub
    8022             :       0,        // dsub1_then_ssub
    8023             :       0,        // dsub3_then_bsub
    8024             :       0,        // dsub3_then_hsub
    8025             :       0,        // dsub3_then_ssub
    8026             :       0,        // dsub2_then_bsub
    8027             :       0,        // dsub2_then_hsub
    8028             :       0,        // dsub2_then_ssub
    8029             :       0,        // qsub1_then_bsub
    8030             :       0,        // qsub1_then_dsub
    8031             :       0,        // qsub1_then_hsub
    8032             :       0,        // qsub1_then_ssub
    8033             :       0,        // qsub3_then_bsub
    8034             :       0,        // qsub3_then_dsub
    8035             :       0,        // qsub3_then_hsub
    8036             :       0,        // qsub3_then_ssub
    8037             :       0,        // qsub2_then_bsub
    8038             :       0,        // qsub2_then_dsub
    8039             :       0,        // qsub2_then_hsub
    8040             :       0,        // qsub2_then_ssub
    8041             :       0,        // subo64_then_sub_32
    8042             :       0,        // zsub1_then_bsub
    8043             :       0,        // zsub1_then_dsub
    8044             :       0,        // zsub1_then_hsub
    8045             :       0,        // zsub1_then_ssub
    8046             :       0,        // zsub1_then_zsub
    8047             :       0,        // zsub1_then_zsub_hi
    8048             :       0,        // zsub3_then_bsub
    8049             :       0,        // zsub3_then_dsub
    8050             :       0,        // zsub3_then_hsub
    8051             :       0,        // zsub3_then_ssub
    8052             :       0,        // zsub3_then_zsub
    8053             :       0,        // zsub3_then_zsub_hi
    8054             :       0,        // zsub2_then_bsub
    8055             :       0,        // zsub2_then_dsub
    8056             :       0,        // zsub2_then_hsub
    8057             :       0,        // zsub2_then_ssub
    8058             :       0,        // zsub2_then_zsub
    8059             :       0,        // zsub2_then_zsub_hi
    8060             :       0,        // dsub0_dsub1
    8061             :       0,        // dsub0_dsub1_dsub2
    8062             :       0,        // dsub1_dsub2
    8063             :       0,        // dsub1_dsub2_dsub3
    8064             :       0,        // dsub2_dsub3
    8065             :       0,        // dsub_qsub1_then_dsub
    8066             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8067             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8068             :       0,        // qsub0_qsub1
    8069             :       0,        // qsub0_qsub1_qsub2
    8070             :       0,        // qsub1_qsub2
    8071             :       0,        // qsub1_qsub2_qsub3
    8072             :       0,        // qsub2_qsub3
    8073             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8074             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8075             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8076             :       0,        // sub_32_subo64_then_sub_32
    8077             :       0,        // dsub_zsub1_then_dsub
    8078             :       0,        // zsub_zsub1_then_zsub
    8079             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8080             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8081             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8082             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8083             :       0,        // zsub0_zsub1
    8084             :       0,        // zsub0_zsub1_zsub2
    8085             :       0,        // zsub1_zsub2
    8086             :       0,        // zsub1_zsub2_zsub3
    8087             :       0,        // zsub2_zsub3
    8088             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8089             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8090             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8091             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8092             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8093             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8094             :     },
    8095             :     {   // FPR16
    8096             :       2,        // bsub -> FPR16
    8097             :       0,        // dsub
    8098             :       0,        // dsub0
    8099             :       0,        // dsub1
    8100             :       0,        // dsub2
    8101             :       0,        // dsub3
    8102             :       0,        // hsub
    8103             :       0,        // qhisub
    8104             :       0,        // qsub
    8105             :       0,        // qsub0
    8106             :       0,        // qsub1
    8107             :       0,        // qsub2
    8108             :       0,        // qsub3
    8109             :       0,        // ssub
    8110             :       0,        // sub_32
    8111             :       0,        // sube32
    8112             :       0,        // sube64
    8113             :       0,        // subo32
    8114             :       0,        // subo64
    8115             :       0,        // zsub
    8116             :       0,        // zsub0
    8117             :       0,        // zsub1
    8118             :       0,        // zsub2
    8119             :       0,        // zsub3
    8120             :       0,        // zsub_hi
    8121             :       0,        // dsub1_then_bsub
    8122             :       0,        // dsub1_then_hsub
    8123             :       0,        // dsub1_then_ssub
    8124             :       0,        // dsub3_then_bsub
    8125             :       0,        // dsub3_then_hsub
    8126             :       0,        // dsub3_then_ssub
    8127             :       0,        // dsub2_then_bsub
    8128             :       0,        // dsub2_then_hsub
    8129             :       0,        // dsub2_then_ssub
    8130             :       0,        // qsub1_then_bsub
    8131             :       0,        // qsub1_then_dsub
    8132             :       0,        // qsub1_then_hsub
    8133             :       0,        // qsub1_then_ssub
    8134             :       0,        // qsub3_then_bsub
    8135             :       0,        // qsub3_then_dsub
    8136             :       0,        // qsub3_then_hsub
    8137             :       0,        // qsub3_then_ssub
    8138             :       0,        // qsub2_then_bsub
    8139             :       0,        // qsub2_then_dsub
    8140             :       0,        // qsub2_then_hsub
    8141             :       0,        // qsub2_then_ssub
    8142             :       0,        // subo64_then_sub_32
    8143             :       0,        // zsub1_then_bsub
    8144             :       0,        // zsub1_then_dsub
    8145             :       0,        // zsub1_then_hsub
    8146             :       0,        // zsub1_then_ssub
    8147             :       0,        // zsub1_then_zsub
    8148             :       0,        // zsub1_then_zsub_hi
    8149             :       0,        // zsub3_then_bsub
    8150             :       0,        // zsub3_then_dsub
    8151             :       0,        // zsub3_then_hsub
    8152             :       0,        // zsub3_then_ssub
    8153             :       0,        // zsub3_then_zsub
    8154             :       0,        // zsub3_then_zsub_hi
    8155             :       0,        // zsub2_then_bsub
    8156             :       0,        // zsub2_then_dsub
    8157             :       0,        // zsub2_then_hsub
    8158             :       0,        // zsub2_then_ssub
    8159             :       0,        // zsub2_then_zsub
    8160             :       0,        // zsub2_then_zsub_hi
    8161             :       0,        // dsub0_dsub1
    8162             :       0,        // dsub0_dsub1_dsub2
    8163             :       0,        // dsub1_dsub2
    8164             :       0,        // dsub1_dsub2_dsub3
    8165             :       0,        // dsub2_dsub3
    8166             :       0,        // dsub_qsub1_then_dsub
    8167             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8168             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8169             :       0,        // qsub0_qsub1
    8170             :       0,        // qsub0_qsub1_qsub2
    8171             :       0,        // qsub1_qsub2
    8172             :       0,        // qsub1_qsub2_qsub3
    8173             :       0,        // qsub2_qsub3
    8174             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8175             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8176             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8177             :       0,        // sub_32_subo64_then_sub_32
    8178             :       0,        // dsub_zsub1_then_dsub
    8179             :       0,        // zsub_zsub1_then_zsub
    8180             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8181             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8182             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8183             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8184             :       0,        // zsub0_zsub1
    8185             :       0,        // zsub0_zsub1_zsub2
    8186             :       0,        // zsub1_zsub2
    8187             :       0,        // zsub1_zsub2_zsub3
    8188             :       0,        // zsub2_zsub3
    8189             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8190             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8191             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8192             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8193             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8194             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8195             :     },
    8196             :     {   // PPR
    8197             :       0,        // bsub
    8198             :       0,        // dsub
    8199             :       0,        // dsub0
    8200             :       0,        // dsub1
    8201             :       0,        // dsub2
    8202             :       0,        // dsub3
    8203             :       0,        // hsub
    8204             :       0,        // qhisub
    8205             :       0,        // qsub
    8206             :       0,        // qsub0
    8207             :       0,        // qsub1
    8208             :       0,        // qsub2
    8209             :       0,        // qsub3
    8210             :       0,        // ssub
    8211             :       0,        // sub_32
    8212             :       0,        // sube32
    8213             :       0,        // sube64
    8214             :       0,        // subo32
    8215             :       0,        // subo64
    8216             :       0,        // zsub
    8217             :       0,        // zsub0
    8218             :       0,        // zsub1
    8219             :       0,        // zsub2
    8220             :       0,        // zsub3
    8221             :       0,        // zsub_hi
    8222             :       0,        // dsub1_then_bsub
    8223             :       0,        // dsub1_then_hsub
    8224             :       0,        // dsub1_then_ssub
    8225             :       0,        // dsub3_then_bsub
    8226             :       0,        // dsub3_then_hsub
    8227             :       0,        // dsub3_then_ssub
    8228             :       0,        // dsub2_then_bsub
    8229             :       0,        // dsub2_then_hsub
    8230             :       0,        // dsub2_then_ssub
    8231             :       0,        // qsub1_then_bsub
    8232             :       0,        // qsub1_then_dsub
    8233             :       0,        // qsub1_then_hsub
    8234             :       0,        // qsub1_then_ssub
    8235             :       0,        // qsub3_then_bsub
    8236             :       0,        // qsub3_then_dsub
    8237             :       0,        // qsub3_then_hsub
    8238             :       0,        // qsub3_then_ssub
    8239             :       0,        // qsub2_then_bsub
    8240             :       0,        // qsub2_then_dsub
    8241             :       0,        // qsub2_then_hsub
    8242             :       0,        // qsub2_then_ssub
    8243             :       0,        // subo64_then_sub_32
    8244             :       0,        // zsub1_then_bsub
    8245             :       0,        // zsub1_then_dsub
    8246             :       0,        // zsub1_then_hsub
    8247             :       0,        // zsub1_then_ssub
    8248             :       0,        // zsub1_then_zsub
    8249             :       0,        // zsub1_then_zsub_hi
    8250             :       0,        // zsub3_then_bsub
    8251             :       0,        // zsub3_then_dsub
    8252             :       0,        // zsub3_then_hsub
    8253             :       0,        // zsub3_then_ssub
    8254             :       0,        // zsub3_then_zsub
    8255             :       0,        // zsub3_then_zsub_hi
    8256             :       0,        // zsub2_then_bsub
    8257             :       0,        // zsub2_then_dsub
    8258             :       0,        // zsub2_then_hsub
    8259             :       0,        // zsub2_then_ssub
    8260             :       0,        // zsub2_then_zsub
    8261             :       0,        // zsub2_then_zsub_hi
    8262             :       0,        // dsub0_dsub1
    8263             :       0,        // dsub0_dsub1_dsub2
    8264             :       0,        // dsub1_dsub2
    8265             :       0,        // dsub1_dsub2_dsub3
    8266             :       0,        // dsub2_dsub3
    8267             :       0,        // dsub_qsub1_then_dsub
    8268             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8269             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8270             :       0,        // qsub0_qsub1
    8271             :       0,        // qsub0_qsub1_qsub2
    8272             :       0,        // qsub1_qsub2
    8273             :       0,        // qsub1_qsub2_qsub3
    8274             :       0,        // qsub2_qsub3
    8275             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8276             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8277             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8278             :       0,        // sub_32_subo64_then_sub_32
    8279             :       0,        // dsub_zsub1_then_dsub
    8280             :       0,        // zsub_zsub1_then_zsub
    8281             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8282             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8283             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8284             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8285             :       0,        // zsub0_zsub1
    8286             :       0,        // zsub0_zsub1_zsub2
    8287             :       0,        // zsub1_zsub2
    8288             :       0,        // zsub1_zsub2_zsub3
    8289             :       0,        // zsub2_zsub3
    8290             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8291             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8292             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8293             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8294             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8295             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8296             :     },
    8297             :     {   // PPR_3b
    8298             :       0,        // bsub
    8299             :       0,        // dsub
    8300             :       0,        // dsub0
    8301             :       0,        // dsub1
    8302             :       0,        // dsub2
    8303             :       0,        // dsub3
    8304             :       0,        // hsub
    8305             :       0,        // qhisub
    8306             :       0,        // qsub
    8307             :       0,        // qsub0
    8308             :       0,        // qsub1
    8309             :       0,        // qsub2
    8310             :       0,        // qsub3
    8311             :       0,        // ssub
    8312             :       0,        // sub_32
    8313             :       0,        // sube32
    8314             :       0,        // sube64
    8315             :       0,        // subo32
    8316             :       0,        // subo64
    8317             :       0,        // zsub
    8318             :       0,        // zsub0
    8319             :       0,        // zsub1
    8320             :       0,        // zsub2
    8321             :       0,        // zsub3
    8322             :       0,        // zsub_hi
    8323             :       0,        // dsub1_then_bsub
    8324             :       0,        // dsub1_then_hsub
    8325             :       0,        // dsub1_then_ssub
    8326             :       0,        // dsub3_then_bsub
    8327             :       0,        // dsub3_then_hsub
    8328             :       0,        // dsub3_then_ssub
    8329             :       0,        // dsub2_then_bsub
    8330             :       0,        // dsub2_then_hsub
    8331             :       0,        // dsub2_then_ssub
    8332             :       0,        // qsub1_then_bsub
    8333             :       0,        // qsub1_then_dsub
    8334             :       0,        // qsub1_then_hsub
    8335             :       0,        // qsub1_then_ssub
    8336             :       0,        // qsub3_then_bsub
    8337             :       0,        // qsub3_then_dsub
    8338             :       0,        // qsub3_then_hsub
    8339             :       0,        // qsub3_then_ssub
    8340             :       0,        // qsub2_then_bsub
    8341             :       0,        // qsub2_then_dsub
    8342             :       0,        // qsub2_then_hsub
    8343             :       0,        // qsub2_then_ssub
    8344             :       0,        // subo64_then_sub_32
    8345             :       0,        // zsub1_then_bsub
    8346             :       0,        // zsub1_then_dsub
    8347             :       0,        // zsub1_then_hsub
    8348             :       0,        // zsub1_then_ssub
    8349             :       0,        // zsub1_then_zsub
    8350             :       0,        // zsub1_then_zsub_hi
    8351             :       0,        // zsub3_then_bsub
    8352             :       0,        // zsub3_then_dsub
    8353             :       0,        // zsub3_then_hsub
    8354             :       0,        // zsub3_then_ssub
    8355             :       0,        // zsub3_then_zsub
    8356             :       0,        // zsub3_then_zsub_hi
    8357             :       0,        // zsub2_then_bsub
    8358             :       0,        // zsub2_then_dsub
    8359             :       0,        // zsub2_then_hsub
    8360             :       0,        // zsub2_then_ssub
    8361             :       0,        // zsub2_then_zsub
    8362             :       0,        // zsub2_then_zsub_hi
    8363             :       0,        // dsub0_dsub1
    8364             :       0,        // dsub0_dsub1_dsub2
    8365             :       0,        // dsub1_dsub2
    8366             :       0,        // dsub1_dsub2_dsub3
    8367             :       0,        // dsub2_dsub3
    8368             :       0,        // dsub_qsub1_then_dsub
    8369             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8370             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8371             :       0,        // qsub0_qsub1
    8372             :       0,        // qsub0_qsub1_qsub2
    8373             :       0,        // qsub1_qsub2
    8374             :       0,        // qsub1_qsub2_qsub3
    8375             :       0,        // qsub2_qsub3
    8376             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8377             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8378             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8379             :       0,        // sub_32_subo64_then_sub_32
    8380             :       0,        // dsub_zsub1_then_dsub
    8381             :       0,        // zsub_zsub1_then_zsub
    8382             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8383             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8384             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8385             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8386             :       0,        // zsub0_zsub1
    8387             :       0,        // zsub0_zsub1_zsub2
    8388             :       0,        // zsub1_zsub2
    8389             :       0,        // zsub1_zsub2_zsub3
    8390             :       0,        // zsub2_zsub3
    8391             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8392             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8393             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8394             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8395             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8396             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8397             :     },
    8398             :     {   // GPR32all
    8399             :       0,        // bsub
    8400             :       0,        // dsub
    8401             :       0,        // dsub0
    8402             :       0,        // dsub1
    8403             :       0,        // dsub2
    8404             :       0,        // dsub3
    8405             :       0,        // hsub
    8406             :       0,        // qhisub
    8407             :       0,        // qsub
    8408             :       0,        // qsub0
    8409             :       0,        // qsub1
    8410             :       0,        // qsub2
    8411             :       0,        // qsub3
    8412             :       0,        // ssub
    8413             :       0,        // sub_32
    8414             :       0,        // sube32
    8415             :       0,        // sube64
    8416             :       0,        // subo32
    8417             :       0,        // subo64
    8418             :       0,        // zsub
    8419             :       0,        // zsub0
    8420             :       0,        // zsub1
    8421             :       0,        // zsub2
    8422             :       0,        // zsub3
    8423             :       0,        // zsub_hi
    8424             :       0,        // dsub1_then_bsub
    8425             :       0,        // dsub1_then_hsub
    8426             :       0,        // dsub1_then_ssub
    8427             :       0,        // dsub3_then_bsub
    8428             :       0,        // dsub3_then_hsub
    8429             :       0,        // dsub3_then_ssub
    8430             :       0,        // dsub2_then_bsub
    8431             :       0,        // dsub2_then_hsub
    8432             :       0,        // dsub2_then_ssub
    8433             :       0,        // qsub1_then_bsub
    8434             :       0,        // qsub1_then_dsub
    8435             :       0,        // qsub1_then_hsub
    8436             :       0,        // qsub1_then_ssub
    8437             :       0,        // qsub3_then_bsub
    8438             :       0,        // qsub3_then_dsub
    8439             :       0,        // qsub3_then_hsub
    8440             :       0,        // qsub3_then_ssub
    8441             :       0,        // qsub2_then_bsub
    8442             :       0,        // qsub2_then_dsub
    8443             :       0,        // qsub2_then_hsub
    8444             :       0,        // qsub2_then_ssub
    8445             :       0,        // subo64_then_sub_32
    8446             :       0,        // zsub1_then_bsub
    8447             :       0,        // zsub1_then_dsub
    8448             :       0,        // zsub1_then_hsub
    8449             :       0,        // zsub1_then_ssub
    8450             :       0,        // zsub1_then_zsub
    8451             :       0,        // zsub1_then_zsub_hi
    8452             :       0,        // zsub3_then_bsub
    8453             :       0,        // zsub3_then_dsub
    8454             :       0,        // zsub3_then_hsub
    8455             :       0,        // zsub3_then_ssub
    8456             :       0,        // zsub3_then_zsub
    8457             :       0,        // zsub3_then_zsub_hi
    8458             :       0,        // zsub2_then_bsub
    8459             :       0,        // zsub2_then_dsub
    8460             :       0,        // zsub2_then_hsub
    8461             :       0,        // zsub2_then_ssub
    8462             :       0,        // zsub2_then_zsub
    8463             :       0,        // zsub2_then_zsub_hi
    8464             :       0,        // dsub0_dsub1
    8465             :       0,        // dsub0_dsub1_dsub2
    8466             :       0,        // dsub1_dsub2
    8467             :       0,        // dsub1_dsub2_dsub3
    8468             :       0,        // dsub2_dsub3
    8469             :       0,        // dsub_qsub1_then_dsub
    8470             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8471             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8472             :       0,        // qsub0_qsub1
    8473             :       0,        // qsub0_qsub1_qsub2
    8474             :       0,        // qsub1_qsub2
    8475             :       0,        // qsub1_qsub2_qsub3
    8476             :       0,        // qsub2_qsub3
    8477             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8478             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8479             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8480             :       0,        // sub_32_subo64_then_sub_32
    8481             :       0,        // dsub_zsub1_then_dsub
    8482             :       0,        // zsub_zsub1_then_zsub
    8483             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8484             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8485             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8486             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8487             :       0,        // zsub0_zsub1
    8488             :       0,        // zsub0_zsub1_zsub2
    8489             :       0,        // zsub1_zsub2
    8490             :       0,        // zsub1_zsub2_zsub3
    8491             :       0,        // zsub2_zsub3
    8492             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8493             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8494             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8495             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8496             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8497             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8498             :     },
    8499             :     {   // FPR32
    8500             :       6,        // bsub -> FPR32
    8501             :       0,        // dsub
    8502             :       0,        // dsub0
    8503             :       0,        // dsub1
    8504             :       0,        // dsub2
    8505             :       0,        // dsub3
    8506             :       6,        // hsub -> FPR32
    8507             :       0,        // qhisub
    8508             :       0,        // qsub
    8509             :       0,        // qsub0
    8510             :       0,        // qsub1
    8511             :       0,        // qsub2
    8512             :       0,        // qsub3
    8513             :       0,        // ssub
    8514             :       0,        // sub_32
    8515             :       0,        // sube32
    8516             :       0,        // sube64
    8517             :       0,        // subo32
    8518             :       0,        // subo64
    8519             :       0,        // zsub
    8520             :       0,        // zsub0
    8521             :       0,        // zsub1
    8522             :       0,        // zsub2
    8523             :       0,        // zsub3
    8524             :       0,        // zsub_hi
    8525             :       0,        // dsub1_then_bsub
    8526             :       0,        // dsub1_then_hsub
    8527             :       0,        // dsub1_then_ssub
    8528             :       0,        // dsub3_then_bsub
    8529             :       0,        // dsub3_then_hsub
    8530             :       0,        // dsub3_then_ssub
    8531             :       0,        // dsub2_then_bsub
    8532             :       0,        // dsub2_then_hsub
    8533             :       0,        // dsub2_then_ssub
    8534             :       0,        // qsub1_then_bsub
    8535             :       0,        // qsub1_then_dsub
    8536             :       0,        // qsub1_then_hsub
    8537             :       0,        // qsub1_then_ssub
    8538             :       0,        // qsub3_then_bsub
    8539             :       0,        // qsub3_then_dsub
    8540             :       0,        // qsub3_then_hsub
    8541             :       0,        // qsub3_then_ssub
    8542             :       0,        // qsub2_then_bsub
    8543             :       0,        // qsub2_then_dsub
    8544             :       0,        // qsub2_then_hsub
    8545             :       0,        // qsub2_then_ssub
    8546             :       0,        // subo64_then_sub_32
    8547             :       0,        // zsub1_then_bsub
    8548             :       0,        // zsub1_then_dsub
    8549             :       0,        // zsub1_then_hsub
    8550             :       0,        // zsub1_then_ssub
    8551             :       0,        // zsub1_then_zsub
    8552             :       0,        // zsub1_then_zsub_hi
    8553             :       0,        // zsub3_then_bsub
    8554             :       0,        // zsub3_then_dsub
    8555             :       0,        // zsub3_then_hsub
    8556             :       0,        // zsub3_then_ssub
    8557             :       0,        // zsub3_then_zsub
    8558             :       0,        // zsub3_then_zsub_hi
    8559             :       0,        // zsub2_then_bsub
    8560             :       0,        // zsub2_then_dsub
    8561             :       0,        // zsub2_then_hsub
    8562             :       0,        // zsub2_then_ssub
    8563             :       0,        // zsub2_then_zsub
    8564             :       0,        // zsub2_then_zsub_hi
    8565             :       0,        // dsub0_dsub1
    8566             :       0,        // dsub0_dsub1_dsub2
    8567             :       0,        // dsub1_dsub2
    8568             :       0,        // dsub1_dsub2_dsub3
    8569             :       0,        // dsub2_dsub3
    8570             :       0,        // dsub_qsub1_then_dsub
    8571             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8572             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8573             :       0,        // qsub0_qsub1
    8574             :       0,        // qsub0_qsub1_qsub2
    8575             :       0,        // qsub1_qsub2
    8576             :       0,        // qsub1_qsub2_qsub3
    8577             :       0,        // qsub2_qsub3
    8578             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8579             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8580             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8581             :       0,        // sub_32_subo64_then_sub_32
    8582             :       0,        // dsub_zsub1_then_dsub
    8583             :       0,        // zsub_zsub1_then_zsub
    8584             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8585             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8586             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8587             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8588             :       0,        // zsub0_zsub1
    8589             :       0,        // zsub0_zsub1_zsub2
    8590             :       0,        // zsub1_zsub2
    8591             :       0,        // zsub1_zsub2_zsub3
    8592             :       0,        // zsub2_zsub3
    8593             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8594             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8595             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8596             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8597             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8598             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8599             :     },
    8600             :     {   // GPR32
    8601             :       0,        // bsub
    8602             :       0,        // dsub
    8603             :       0,        // dsub0
    8604             :       0,        // dsub1
    8605             :       0,        // dsub2
    8606             :       0,        // dsub3
    8607             :       0,        // hsub
    8608             :       0,        // qhisub
    8609             :       0,        // qsub
    8610             :       0,        // qsub0
    8611             :       0,        // qsub1
    8612             :       0,        // qsub2
    8613             :       0,        // qsub3
    8614             :       0,        // ssub
    8615             :       0,        // sub_32
    8616             :       0,        // sube32
    8617             :       0,        // sube64
    8618             :       0,        // subo32
    8619             :       0,        // subo64
    8620             :       0,        // zsub
    8621             :       0,        // zsub0
    8622             :       0,        // zsub1
    8623             :       0,        // zsub2
    8624             :       0,        // zsub3
    8625             :       0,        // zsub_hi
    8626             :       0,        // dsub1_then_bsub
    8627             :       0,        // dsub1_then_hsub
    8628             :       0,        // dsub1_then_ssub
    8629             :       0,        // dsub3_then_bsub
    8630             :       0,        // dsub3_then_hsub
    8631             :       0,        // dsub3_then_ssub
    8632             :       0,        // dsub2_then_bsub
    8633             :       0,        // dsub2_then_hsub
    8634             :       0,        // dsub2_then_ssub
    8635             :       0,        // qsub1_then_bsub
    8636             :       0,        // qsub1_then_dsub
    8637             :       0,        // qsub1_then_hsub
    8638             :       0,        // qsub1_then_ssub
    8639             :       0,        // qsub3_then_bsub
    8640             :       0,        // qsub3_then_dsub
    8641             :       0,        // qsub3_then_hsub
    8642             :       0,        // qsub3_then_ssub
    8643             :       0,        // qsub2_then_bsub
    8644             :       0,        // qsub2_then_dsub
    8645             :       0,        // qsub2_then_hsub
    8646             :       0,        // qsub2_then_ssub
    8647             :       0,        // subo64_then_sub_32
    8648             :       0,        // zsub1_then_bsub
    8649             :       0,        // zsub1_then_dsub
    8650             :       0,        // zsub1_then_hsub
    8651             :       0,        // zsub1_then_ssub
    8652             :       0,        // zsub1_then_zsub
    8653             :       0,        // zsub1_then_zsub_hi
    8654             :       0,        // zsub3_then_bsub
    8655             :       0,        // zsub3_then_dsub
    8656             :       0,        // zsub3_then_hsub
    8657             :       0,        // zsub3_then_ssub
    8658             :       0,        // zsub3_then_zsub
    8659             :       0,        // zsub3_then_zsub_hi
    8660             :       0,        // zsub2_then_bsub
    8661             :       0,        // zsub2_then_dsub
    8662             :       0,        // zsub2_then_hsub
    8663             :       0,        // zsub2_then_ssub
    8664             :       0,        // zsub2_then_zsub
    8665             :       0,        // zsub2_then_zsub_hi
    8666             :       0,        // dsub0_dsub1
    8667             :       0,        // dsub0_dsub1_dsub2
    8668             :       0,        // dsub1_dsub2
    8669             :       0,        // dsub1_dsub2_dsub3
    8670             :       0,        // dsub2_dsub3
    8671             :       0,        // dsub_qsub1_then_dsub
    8672             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8673             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8674             :       0,        // qsub0_qsub1
    8675             :       0,        // qsub0_qsub1_qsub2
    8676             :       0,        // qsub1_qsub2
    8677             :       0,        // qsub1_qsub2_qsub3
    8678             :       0,        // qsub2_qsub3
    8679             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8680             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8681             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8682             :       0,        // sub_32_subo64_then_sub_32
    8683             :       0,        // dsub_zsub1_then_dsub
    8684             :       0,        // zsub_zsub1_then_zsub
    8685             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8686             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8687             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8688             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8689             :       0,        // zsub0_zsub1
    8690             :       0,        // zsub0_zsub1_zsub2
    8691             :       0,        // zsub1_zsub2
    8692             :       0,        // zsub1_zsub2_zsub3
    8693             :       0,        // zsub2_zsub3
    8694             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8695             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8696             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8697             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8698             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8699             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8700             :     },
    8701             :     {   // GPR32sp
    8702             :       0,        // bsub
    8703             :       0,        // dsub
    8704             :       0,        // dsub0
    8705             :       0,        // dsub1
    8706             :       0,        // dsub2
    8707             :       0,        // dsub3
    8708             :       0,        // hsub
    8709             :       0,        // qhisub
    8710             :       0,        // qsub
    8711             :       0,        // qsub0
    8712             :       0,        // qsub1
    8713             :       0,        // qsub2
    8714             :       0,        // qsub3
    8715             :       0,        // ssub
    8716             :       0,        // sub_32
    8717             :       0,        // sube32
    8718             :       0,        // sube64
    8719             :       0,        // subo32
    8720             :       0,        // subo64
    8721             :       0,        // zsub
    8722             :       0,        // zsub0
    8723             :       0,        // zsub1
    8724             :       0,        // zsub2
    8725             :       0,        // zsub3
    8726             :       0,        // zsub_hi
    8727             :       0,        // dsub1_then_bsub
    8728             :       0,        // dsub1_then_hsub
    8729             :       0,        // dsub1_then_ssub
    8730             :       0,        // dsub3_then_bsub
    8731             :       0,        // dsub3_then_hsub
    8732             :       0,        // dsub3_then_ssub
    8733             :       0,        // dsub2_then_bsub
    8734             :       0,        // dsub2_then_hsub
    8735             :       0,        // dsub2_then_ssub
    8736             :       0,        // qsub1_then_bsub
    8737             :       0,        // qsub1_then_dsub
    8738             :       0,        // qsub1_then_hsub
    8739             :       0,        // qsub1_then_ssub
    8740             :       0,        // qsub3_then_bsub
    8741             :       0,        // qsub3_then_dsub
    8742             :       0,        // qsub3_then_hsub
    8743             :       0,        // qsub3_then_ssub
    8744             :       0,        // qsub2_then_bsub
    8745             :       0,        // qsub2_then_dsub
    8746             :       0,        // qsub2_then_hsub
    8747             :       0,        // qsub2_then_ssub
    8748             :       0,        // subo64_then_sub_32
    8749             :       0,        // zsub1_then_bsub
    8750             :       0,        // zsub1_then_dsub
    8751             :       0,        // zsub1_then_hsub
    8752             :       0,        // zsub1_then_ssub
    8753             :       0,        // zsub1_then_zsub
    8754             :       0,        // zsub1_then_zsub_hi
    8755             :       0,        // zsub3_then_bsub
    8756             :       0,        // zsub3_then_dsub
    8757             :       0,        // zsub3_then_hsub
    8758             :       0,        // zsub3_then_ssub
    8759             :       0,        // zsub3_then_zsub
    8760             :       0,        // zsub3_then_zsub_hi
    8761             :       0,        // zsub2_then_bsub
    8762             :       0,        // zsub2_then_dsub
    8763             :       0,        // zsub2_then_hsub
    8764             :       0,        // zsub2_then_ssub
    8765             :       0,        // zsub2_then_zsub
    8766             :       0,        // zsub2_then_zsub_hi
    8767             :       0,        // dsub0_dsub1
    8768             :       0,        // dsub0_dsub1_dsub2
    8769             :       0,        // dsub1_dsub2
    8770             :       0,        // dsub1_dsub2_dsub3
    8771             :       0,        // dsub2_dsub3
    8772             :       0,        // dsub_qsub1_then_dsub
    8773             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8774             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8775             :       0,        // qsub0_qsub1
    8776             :       0,        // qsub0_qsub1_qsub2
    8777             :       0,        // qsub1_qsub2
    8778             :       0,        // qsub1_qsub2_qsub3
    8779             :       0,        // qsub2_qsub3
    8780             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8781             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8782             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8783             :       0,        // sub_32_subo64_then_sub_32
    8784             :       0,        // dsub_zsub1_then_dsub
    8785             :       0,        // zsub_zsub1_then_zsub
    8786             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8787             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8788             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8789             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8790             :       0,        // zsub0_zsub1
    8791             :       0,        // zsub0_zsub1_zsub2
    8792             :       0,        // zsub1_zsub2
    8793             :       0,        // zsub1_zsub2_zsub3
    8794             :       0,        // zsub2_zsub3
    8795             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8796             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8797             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8798             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8799             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8800             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8801             :     },
    8802             :     {   // GPR32common
    8803             :       0,        // bsub
    8804             :       0,        // dsub
    8805             :       0,        // dsub0
    8806             :       0,        // dsub1
    8807             :       0,        // dsub2
    8808             :       0,        // dsub3
    8809             :       0,        // hsub
    8810             :       0,        // qhisub
    8811             :       0,        // qsub
    8812             :       0,        // qsub0
    8813             :       0,        // qsub1
    8814             :       0,        // qsub2
    8815             :       0,        // qsub3
    8816             :       0,        // ssub
    8817             :       0,        // sub_32
    8818             :       0,        // sube32
    8819             :       0,        // sube64
    8820             :       0,        // subo32
    8821             :       0,        // subo64
    8822             :       0,        // zsub
    8823             :       0,        // zsub0
    8824             :       0,        // zsub1
    8825             :       0,        // zsub2
    8826             :       0,        // zsub3
    8827             :       0,        // zsub_hi
    8828             :       0,        // dsub1_then_bsub
    8829             :       0,        // dsub1_then_hsub
    8830             :       0,        // dsub1_then_ssub
    8831             :       0,        // dsub3_then_bsub
    8832             :       0,        // dsub3_then_hsub
    8833             :       0,        // dsub3_then_ssub
    8834             :       0,        // dsub2_then_bsub
    8835             :       0,        // dsub2_then_hsub
    8836             :       0,        // dsub2_then_ssub
    8837             :       0,        // qsub1_then_bsub
    8838             :       0,        // qsub1_then_dsub
    8839             :       0,        // qsub1_then_hsub
    8840             :       0,        // qsub1_then_ssub
    8841             :       0,        // qsub3_then_bsub
    8842             :       0,        // qsub3_then_dsub
    8843             :       0,        // qsub3_then_hsub
    8844             :       0,        // qsub3_then_ssub
    8845             :       0,        // qsub2_then_bsub
    8846             :       0,        // qsub2_then_dsub
    8847             :       0,        // qsub2_then_hsub
    8848             :       0,        // qsub2_then_ssub
    8849             :       0,        // subo64_then_sub_32
    8850             :       0,        // zsub1_then_bsub
    8851             :       0,        // zsub1_then_dsub
    8852             :       0,        // zsub1_then_hsub
    8853             :       0,        // zsub1_then_ssub
    8854             :       0,        // zsub1_then_zsub
    8855             :       0,        // zsub1_then_zsub_hi
    8856             :       0,        // zsub3_then_bsub
    8857             :       0,        // zsub3_then_dsub
    8858             :       0,        // zsub3_then_hsub
    8859             :       0,        // zsub3_then_ssub
    8860             :       0,        // zsub3_then_zsub
    8861             :       0,        // zsub3_then_zsub_hi
    8862             :       0,        // zsub2_then_bsub
    8863             :       0,        // zsub2_then_dsub
    8864             :       0,        // zsub2_then_hsub
    8865             :       0,        // zsub2_then_ssub
    8866             :       0,        // zsub2_then_zsub
    8867             :       0,        // zsub2_then_zsub_hi
    8868             :       0,        // dsub0_dsub1
    8869             :       0,        // dsub0_dsub1_dsub2
    8870             :       0,        // dsub1_dsub2
    8871             :       0,        // dsub1_dsub2_dsub3
    8872             :       0,        // dsub2_dsub3
    8873             :       0,        // dsub_qsub1_then_dsub
    8874             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8875             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8876             :       0,        // qsub0_qsub1
    8877             :       0,        // qsub0_qsub1_qsub2
    8878             :       0,        // qsub1_qsub2
    8879             :       0,        // qsub1_qsub2_qsub3
    8880             :       0,        // qsub2_qsub3
    8881             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8882             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8883             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8884             :       0,        // sub_32_subo64_then_sub_32
    8885             :       0,        // dsub_zsub1_then_dsub
    8886             :       0,        // zsub_zsub1_then_zsub
    8887             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8888             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8889             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8890             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8891             :       0,        // zsub0_zsub1
    8892             :       0,        // zsub0_zsub1_zsub2
    8893             :       0,        // zsub1_zsub2
    8894             :       0,        // zsub1_zsub2_zsub3
    8895             :       0,        // zsub2_zsub3
    8896             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8897             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8898             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8899             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8900             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8901             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8902             :     },
    8903             :     {   // CCR
    8904             :       0,        // bsub
    8905             :       0,        // dsub
    8906             :       0,        // dsub0
    8907             :       0,        // dsub1
    8908             :       0,        // dsub2
    8909             :       0,        // dsub3
    8910             :       0,        // hsub
    8911             :       0,        // qhisub
    8912             :       0,        // qsub
    8913             :       0,        // qsub0
    8914             :       0,        // qsub1
    8915             :       0,        // qsub2
    8916             :       0,        // qsub3
    8917             :       0,        // ssub
    8918             :       0,        // sub_32
    8919             :       0,        // sube32
    8920             :       0,        // sube64
    8921             :       0,        // subo32
    8922             :       0,        // subo64
    8923             :       0,        // zsub
    8924             :       0,        // zsub0
    8925             :       0,        // zsub1
    8926             :       0,        // zsub2
    8927             :       0,        // zsub3
    8928             :       0,        // zsub_hi
    8929             :       0,        // dsub1_then_bsub
    8930             :       0,        // dsub1_then_hsub
    8931             :       0,        // dsub1_then_ssub
    8932             :       0,        // dsub3_then_bsub
    8933             :       0,        // dsub3_then_hsub
    8934             :       0,        // dsub3_then_ssub
    8935             :       0,        // dsub2_then_bsub
    8936             :       0,        // dsub2_then_hsub
    8937             :       0,        // dsub2_then_ssub
    8938             :       0,        // qsub1_then_bsub
    8939             :       0,        // qsub1_then_dsub
    8940             :       0,        // qsub1_then_hsub
    8941             :       0,        // qsub1_then_ssub
    8942             :       0,        // qsub3_then_bsub
    8943             :       0,        // qsub3_then_dsub
    8944             :       0,        // qsub3_then_hsub
    8945             :       0,        // qsub3_then_ssub
    8946             :       0,        // qsub2_then_bsub
    8947             :       0,        // qsub2_then_dsub
    8948             :       0,        // qsub2_then_hsub
    8949             :       0,        // qsub2_then_ssub
    8950             :       0,        // subo64_then_sub_32
    8951             :       0,        // zsub1_then_bsub
    8952             :       0,        // zsub1_then_dsub
    8953             :       0,        // zsub1_then_hsub
    8954             :       0,        // zsub1_then_ssub
    8955             :       0,        // zsub1_then_zsub
    8956             :       0,        // zsub1_then_zsub_hi
    8957             :       0,        // zsub3_then_bsub
    8958             :       0,        // zsub3_then_dsub
    8959             :       0,        // zsub3_then_hsub
    8960             :       0,        // zsub3_then_ssub
    8961             :       0,        // zsub3_then_zsub
    8962             :       0,        // zsub3_then_zsub_hi
    8963             :       0,        // zsub2_then_bsub
    8964             :       0,        // zsub2_then_dsub
    8965             :       0,        // zsub2_then_hsub
    8966             :       0,        // zsub2_then_ssub
    8967             :       0,        // zsub2_then_zsub
    8968             :       0,        // zsub2_then_zsub_hi
    8969             :       0,        // dsub0_dsub1
    8970             :       0,        // dsub0_dsub1_dsub2
    8971             :       0,        // dsub1_dsub2
    8972             :       0,        // dsub1_dsub2_dsub3
    8973             :       0,        // dsub2_dsub3
    8974             :       0,        // dsub_qsub1_then_dsub
    8975             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8976             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8977             :       0,        // qsub0_qsub1
    8978             :       0,        // qsub0_qsub1_qsub2
    8979             :       0,        // qsub1_qsub2
    8980             :       0,        // qsub1_qsub2_qsub3
    8981             :       0,        // qsub2_qsub3
    8982             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8983             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8984             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8985             :       0,        // sub_32_subo64_then_sub_32
    8986             :       0,        // dsub_zsub1_then_dsub
    8987             :       0,        // zsub_zsub1_then_zsub
    8988             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8989             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8990             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8991             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8992             :       0,        // zsub0_zsub1
    8993             :       0,        // zsub0_zsub1_zsub2
    8994             :       0,        // zsub1_zsub2
    8995             :       0,        // zsub1_zsub2_zsub3
    8996             :       0,        // zsub2_zsub3
    8997             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8998             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8999             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9000             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9001             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9002             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9003             :     },
    9004             :     {   // GPR32sponly
    9005             :       0,        // bsub
    9006             :       0,        // dsub
    9007             :       0,        // dsub0
    9008             :       0,        // dsub1
    9009             :       0,        // dsub2
    9010             :       0,        // dsub3
    9011             :       0,        // hsub
    9012             :       0,        // qhisub
    9013             :       0,        // qsub
    9014             :       0,        // qsub0
    9015             :       0,        // qsub1
    9016             :       0,        // qsub2
    9017             :       0,        // qsub3
    9018             :       0,        // ssub
    9019             :       0,        // sub_32
    9020             :       0,        // sube32
    9021             :       0,        // sube64
    9022             :       0,        // subo32
    9023             :       0,        // subo64
    9024             :       0,        // zsub
    9025             :       0,        // zsub0
    9026             :       0,        // zsub1
    9027             :       0,        // zsub2
    9028             :       0,        // zsub3
    9029             :       0,        // zsub_hi
    9030             :       0,        // dsub1_then_bsub
    9031             :       0,        // dsub1_then_hsub
    9032             :       0,        // dsub1_then_ssub
    9033             :       0,        // dsub3_then_bsub
    9034             :       0,        // dsub3_then_hsub
    9035             :       0,        // dsub3_then_ssub
    9036             :       0,        // dsub2_then_bsub
    9037             :       0,        // dsub2_then_hsub
    9038             :       0,        // dsub2_then_ssub
    9039             :       0,        // qsub1_then_bsub
    9040             :       0,        // qsub1_then_dsub
    9041             :       0,        // qsub1_then_hsub
    9042             :       0,        // qsub1_then_ssub
    9043             :       0,        // qsub3_then_bsub
    9044             :       0,        // qsub3_then_dsub
    9045             :       0,        // qsub3_then_hsub
    9046             :       0,        // qsub3_then_ssub
    9047             :       0,        // qsub2_then_bsub
    9048             :       0,        // qsub2_then_dsub
    9049             :       0,        // qsub2_then_hsub
    9050             :       0,        // qsub2_then_ssub
    9051             :       0,        // subo64_then_sub_32
    9052             :       0,        // zsub1_then_bsub
    9053             :       0,        // zsub1_then_dsub
    9054             :       0,        // zsub1_then_hsub
    9055             :       0,        // zsub1_then_ssub
    9056             :       0,        // zsub1_then_zsub
    9057             :       0,        // zsub1_then_zsub_hi
    9058             :       0,        // zsub3_then_bsub
    9059             :       0,        // zsub3_then_dsub
    9060             :       0,        // zsub3_then_hsub
    9061             :       0,        // zsub3_then_ssub
    9062             :       0,        // zsub3_then_zsub
    9063             :       0,        // zsub3_then_zsub_hi
    9064             :       0,        // zsub2_then_bsub
    9065             :       0,        // zsub2_then_dsub
    9066             :       0,        // zsub2_then_hsub
    9067             :       0,        // zsub2_then_ssub
    9068             :       0,        // zsub2_then_zsub
    9069             :       0,        // zsub2_then_zsub_hi
    9070             :       0,        // dsub0_dsub1
    9071             :       0,        // dsub0_dsub1_dsub2
    9072             :       0,        // dsub1_dsub2
    9073             :       0,        // dsub1_dsub2_dsub3
    9074             :       0,        // dsub2_dsub3
    9075             :       0,        // dsub_qsub1_then_dsub
    9076             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9077             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9078             :       0,        // qsub0_qsub1
    9079             :       0,        // qsub0_qsub1_qsub2
    9080             :       0,        // qsub1_qsub2
    9081             :       0,        // qsub1_qsub2_qsub3
    9082             :       0,        // qsub2_qsub3
    9083             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9084             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9085             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9086             :       0,        // sub_32_subo64_then_sub_32
    9087             :       0,        // dsub_zsub1_then_dsub
    9088             :       0,        // zsub_zsub1_then_zsub
    9089             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9090             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9091             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9092             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9093             :       0,        // zsub0_zsub1
    9094             :       0,        // zsub0_zsub1_zsub2
    9095             :       0,        // zsub1_zsub2
    9096             :       0,        // zsub1_zsub2_zsub3
    9097             :       0,        // zsub2_zsub3
    9098             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9099             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9100             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9101             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9102             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9103             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9104             :     },
    9105             :     {   // WSeqPairsClass
    9106             :       0,        // bsub
    9107             :       0,        // dsub
    9108             :       0,        // dsub0
    9109             :       0,        // dsub1
    9110             :       0,        // dsub2
    9111             :       0,        // dsub3
    9112             :       0,        // hsub
    9113             :       0,        // qhisub
    9114             :       0,        // qsub
    9115             :       0,        // qsub0
    9116             :       0,        // qsub1
    9117             :       0,        // qsub2
    9118             :       0,        // qsub3
    9119             :       0,        // ssub
    9120             :       0,        // sub_32
    9121             :       12,       // sube32 -> WSeqPairsClass
    9122             :       0,        // sube64
    9123             :       12,       // subo32 -> WSeqPairsClass
    9124             :       0,        // subo64
    9125             :       0,        // zsub
    9126             :       0,        // zsub0
    9127             :       0,        // zsub1
    9128             :       0,        // zsub2
    9129             :       0,        // zsub3
    9130             :       0,        // zsub_hi
    9131             :       0,        // dsub1_then_bsub
    9132             :       0,        // dsub1_then_hsub
    9133             :       0,        // dsub1_then_ssub
    9134             :       0,        // dsub3_then_bsub
    9135             :       0,        // dsub3_then_hsub
    9136             :       0,        // dsub3_then_ssub
    9137             :       0,        // dsub2_then_bsub
    9138             :       0,        // dsub2_then_hsub
    9139             :       0,        // dsub2_then_ssub
    9140             :       0,        // qsub1_then_bsub
    9141             :       0,        // qsub1_then_dsub
    9142             :       0,        // qsub1_then_hsub
    9143             :       0,        // qsub1_then_ssub
    9144             :       0,        // qsub3_then_bsub
    9145             :       0,        // qsub3_then_dsub
    9146             :       0,        // qsub3_then_hsub
    9147             :       0,        // qsub3_then_ssub
    9148             :       0,        // qsub2_then_bsub
    9149             :       0,        // qsub2_then_dsub
    9150             :       0,        // qsub2_then_hsub
    9151             :       0,        // qsub2_then_ssub
    9152             :       0,        // subo64_then_sub_32
    9153             :       0,        // zsub1_then_bsub
    9154             :       0,        // zsub1_then_dsub
    9155             :       0,        // zsub1_then_hsub
    9156             :       0,        // zsub1_then_ssub
    9157             :       0,        // zsub1_then_zsub
    9158             :       0,        // zsub1_then_zsub_hi
    9159             :       0,        // zsub3_then_bsub
    9160             :       0,        // zsub3_then_dsub
    9161             :       0,        // zsub3_then_hsub
    9162             :       0,        // zsub3_then_ssub
    9163             :       0,        // zsub3_then_zsub
    9164             :       0,        // zsub3_then_zsub_hi
    9165             :       0,        // zsub2_then_bsub
    9166             :       0,        // zsub2_then_dsub
    9167             :       0,        // zsub2_then_hsub
    9168             :       0,        // zsub2_then_ssub
    9169             :       0,        // zsub2_then_zsub
    9170             :       0,        // zsub2_then_zsub_hi
    9171             :       0,        // dsub0_dsub1
    9172             :       0,        // dsub0_dsub1_dsub2
    9173             :       0,        // dsub1_dsub2
    9174             :       0,        // dsub1_dsub2_dsub3
    9175             :       0,        // dsub2_dsub3
    9176             :       0,        // dsub_qsub1_then_dsub
    9177             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9178             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9179             :       0,        // qsub0_qsub1
    9180             :       0,        // qsub0_qsub1_qsub2
    9181             :       0,        // qsub1_qsub2
    9182             :       0,        // qsub1_qsub2_qsub3
    9183             :       0,        // qsub2_qsub3
    9184             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9185             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9186             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9187             :       0,        // sub_32_subo64_then_sub_32
    9188             :       0,        // dsub_zsub1_then_dsub
    9189             :       0,        // zsub_zsub1_then_zsub
    9190             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9191             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9192             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9193             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9194             :       0,        // zsub0_zsub1
    9195             :       0,        // zsub0_zsub1_zsub2
    9196             :       0,        // zsub1_zsub2
    9197             :       0,        // zsub1_zsub2_zsub3
    9198             :       0,        // zsub2_zsub3
    9199             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9200             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9201             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9202             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9203             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9204             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9205             :     },
    9206             :     {   // WSeqPairsClass_with_sube32_in_GPR32common
    9207             :       0,        // bsub
    9208             :       0,        // dsub
    9209             :       0,        // dsub0
    9210             :       0,        // dsub1
    9211             :       0,        // dsub2
    9212             :       0,        // dsub3
    9213             :       0,        // hsub
    9214             :       0,        // qhisub
    9215             :       0,        // qsub
    9216             :       0,        // qsub0
    9217             :       0,        // qsub1
    9218             :       0,        // qsub2
    9219             :       0,        // qsub3
    9220             :       0,        // ssub
    9221             :       0,        // sub_32
    9222             :       13,       // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common
    9223             :       0,        // sube64
    9224             :       13,       // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common
    9225             :       0,        // subo64
    9226             :       0,        // zsub
    9227             :       0,        // zsub0
    9228             :       0,        // zsub1
    9229             :       0,        // zsub2
    9230             :       0,        // zsub3
    9231             :       0,        // zsub_hi
    9232             :       0,        // dsub1_then_bsub
    9233             :       0,        // dsub1_then_hsub
    9234             :       0,        // dsub1_then_ssub
    9235             :       0,        // dsub3_then_bsub
    9236             :       0,        // dsub3_then_hsub
    9237             :       0,        // dsub3_then_ssub
    9238             :       0,        // dsub2_then_bsub
    9239             :       0,        // dsub2_then_hsub
    9240             :       0,        // dsub2_then_ssub
    9241             :       0,        // qsub1_then_bsub
    9242             :       0,        // qsub1_then_dsub
    9243             :       0,        // qsub1_then_hsub
    9244             :       0,        // qsub1_then_ssub
    9245             :       0,        // qsub3_then_bsub
    9246             :       0,        // qsub3_then_dsub
    9247             :       0,        // qsub3_then_hsub
    9248             :       0,        // qsub3_then_ssub
    9249             :       0,        // qsub2_then_bsub
    9250             :       0,        // qsub2_then_dsub
    9251             :       0,        // qsub2_then_hsub
    9252             :       0,        // qsub2_then_ssub
    9253             :       0,        // subo64_then_sub_32
    9254             :       0,        // zsub1_then_bsub
    9255             :       0,        // zsub1_then_dsub
    9256             :       0,        // zsub1_then_hsub
    9257             :       0,        // zsub1_then_ssub
    9258             :       0,        // zsub1_then_zsub
    9259             :       0,        // zsub1_then_zsub_hi
    9260             :       0,        // zsub3_then_bsub
    9261             :       0,        // zsub3_then_dsub
    9262             :       0,        // zsub3_then_hsub
    9263             :       0,        // zsub3_then_ssub
    9264             :       0,        // zsub3_then_zsub
    9265             :       0,        // zsub3_then_zsub_hi
    9266             :       0,        // zsub2_then_bsub
    9267             :       0,        // zsub2_then_dsub
    9268             :       0,        // zsub2_then_hsub
    9269             :       0,        // zsub2_then_ssub
    9270             :       0,        // zsub2_then_zsub
    9271             :       0,        // zsub2_then_zsub_hi
    9272             :       0,        // dsub0_dsub1
    9273             :       0,        // dsub0_dsub1_dsub2
    9274             :       0,        // dsub1_dsub2
    9275             :       0,        // dsub1_dsub2_dsub3
    9276             :       0,        // dsub2_dsub3
    9277             :       0,        // dsub_qsub1_then_dsub
    9278             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9279             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9280             :       0,        // qsub0_qsub1
    9281             :       0,        // qsub0_qsub1_qsub2
    9282             :       0,        // qsub1_qsub2
    9283             :       0,        // qsub1_qsub2_qsub3
    9284             :       0,        // qsub2_qsub3
    9285             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9286             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9287             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9288             :       0,        // sub_32_subo64_then_sub_32
    9289             :       0,        // dsub_zsub1_then_dsub
    9290             :       0,        // zsub_zsub1_then_zsub
    9291             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9292             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9293             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9294             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9295             :       0,        // zsub0_zsub1
    9296             :       0,        // zsub0_zsub1_zsub2
    9297             :       0,        // zsub1_zsub2
    9298             :       0,        // zsub1_zsub2_zsub3
    9299             :       0,        // zsub2_zsub3
    9300             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9301             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9302             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9303             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9304             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9305             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9306             :     },
    9307             :     {   // WSeqPairsClass_with_subo32_in_GPR32common
    9308             :       0,        // bsub
    9309             :       0,        // dsub
    9310             :       0,        // dsub0
    9311             :       0,        // dsub1
    9312             :       0,        // dsub2
    9313             :       0,        // dsub3
    9314             :       0,        // hsub
    9315             :       0,        // qhisub
    9316             :       0,        // qsub
    9317             :       0,        // qsub0
    9318             :       0,        // qsub1
    9319             :       0,        // qsub2
    9320             :       0,        // qsub3
    9321             :       0,        // ssub
    9322             :       0,        // sub_32
    9323             :       14,       // sube32 -> WSeqPairsClass_with_subo32_in_GPR32common
    9324             :       0,        // sube64
    9325             :       14,       // subo32 -> WSeqPairsClass_with_subo32_in_GPR32common
    9326             :       0,        // subo64
    9327             :       0,        // zsub
    9328             :       0,        // zsub0
    9329             :       0,        // zsub1
    9330             :       0,        // zsub2
    9331             :       0,        // zsub3
    9332             :       0,        // zsub_hi
    9333             :       0,        // dsub1_then_bsub
    9334             :       0,        // dsub1_then_hsub
    9335             :       0,        // dsub1_then_ssub
    9336             :       0,        // dsub3_then_bsub
    9337             :       0,        // dsub3_then_hsub
    9338             :       0,        // dsub3_then_ssub
    9339             :       0,        // dsub2_then_bsub
    9340             :       0,        // dsub2_then_hsub
    9341             :       0,        // dsub2_then_ssub
    9342             :       0,        // qsub1_then_bsub
    9343             :       0,        // qsub1_then_dsub
    9344             :       0,        // qsub1_then_hsub
    9345             :       0,        // qsub1_then_ssub
    9346             :       0,        // qsub3_then_bsub
    9347             :       0,        // qsub3_then_dsub
    9348             :       0,        // qsub3_then_hsub
    9349             :       0,        // qsub3_then_ssub
    9350             :       0,        // qsub2_then_bsub
    9351             :       0,        // qsub2_then_dsub
    9352             :       0,        // qsub2_then_hsub
    9353             :       0,        // qsub2_then_ssub
    9354             :       0,        // subo64_then_sub_32
    9355             :       0,        // zsub1_then_bsub
    9356             :       0,        // zsub1_then_dsub
    9357             :       0,        // zsub1_then_hsub
    9358             :       0,        // zsub1_then_ssub
    9359             :       0,        // zsub1_then_zsub
    9360             :       0,        // zsub1_then_zsub_hi
    9361             :       0,        // zsub3_then_bsub
    9362             :       0,        // zsub3_then_dsub
    9363             :       0,        // zsub3_then_hsub
    9364             :       0,        // zsub3_then_ssub
    9365             :       0,        // zsub3_then_zsub
    9366             :       0,        // zsub3_then_zsub_hi
    9367             :       0,        // zsub2_then_bsub
    9368             :       0,        // zsub2_then_dsub
    9369             :       0,        // zsub2_then_hsub
    9370             :       0,        // zsub2_then_ssub
    9371             :       0,        // zsub2_then_zsub
    9372             :       0,        // zsub2_then_zsub_hi
    9373             :       0,        // dsub0_dsub1
    9374             :       0,        // dsub0_dsub1_dsub2
    9375             :       0,        // dsub1_dsub2
    9376             :       0,        // dsub1_dsub2_dsub3
    9377             :       0,        // dsub2_dsub3
    9378             :       0,        // dsub_qsub1_then_dsub
    9379             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9380             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9381             :       0,        // qsub0_qsub1
    9382             :       0,        // qsub0_qsub1_qsub2
    9383             :       0,        // qsub1_qsub2
    9384             :       0,        // qsub1_qsub2_qsub3
    9385             :       0,        // qsub2_qsub3
    9386             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9387             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9388             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9389             :       0,        // sub_32_subo64_then_sub_32
    9390             :       0,        // dsub_zsub1_then_dsub
    9391             :       0,        // zsub_zsub1_then_zsub
    9392             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9393             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9394             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9395             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9396             :       0,        // zsub0_zsub1
    9397             :       0,        // zsub0_zsub1_zsub2
    9398             :       0,        // zsub1_zsub2
    9399             :       0,        // zsub1_zsub2_zsub3
    9400             :       0,        // zsub2_zsub3
    9401             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9402             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9403             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9404             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9405             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9406             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9407             :     },
    9408             :     {   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    9409             :       0,        // bsub
    9410             :       0,        // dsub
    9411             :       0,        // dsub0
    9412             :       0,        // dsub1
    9413             :       0,        // dsub2
    9414             :       0,        // dsub3
    9415             :       0,        // hsub
    9416             :       0,        // qhisub
    9417             :       0,        // qsub
    9418             :       0,        // qsub0
    9419             :       0,        // qsub1
    9420             :       0,        // qsub2
    9421             :       0,        // qsub3
    9422             :       0,        // ssub
    9423             :       0,        // sub_32
    9424             :       15,       // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    9425             :       0,        // sube64
    9426             :       15,       // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    9427             :       0,        // subo64
    9428             :       0,        // zsub
    9429             :       0,        // zsub0
    9430             :       0,        // zsub1
    9431             :       0,        // zsub2
    9432             :       0,        // zsub3
    9433             :       0,        // zsub_hi
    9434             :       0,        // dsub1_then_bsub
    9435             :       0,        // dsub1_then_hsub
    9436             :       0,        // dsub1_then_ssub
    9437             :       0,        // dsub3_then_bsub
    9438             :       0,        // dsub3_then_hsub
    9439             :       0,        // dsub3_then_ssub
    9440             :       0,        // dsub2_then_bsub
    9441             :       0,        // dsub2_then_hsub
    9442             :       0,        // dsub2_then_ssub
    9443             :       0,        // qsub1_then_bsub
    9444             :       0,        // qsub1_then_dsub
    9445             :       0,        // qsub1_then_hsub
    9446             :       0,        // qsub1_then_ssub
    9447             :       0,        // qsub3_then_bsub
    9448             :       0,        // qsub3_then_dsub
    9449             :       0,        // qsub3_then_hsub
    9450             :       0,        // qsub3_then_ssub
    9451             :       0,        // qsub2_then_bsub
    9452             :       0,        // qsub2_then_dsub
    9453             :       0,        // qsub2_then_hsub
    9454             :       0,        // qsub2_then_ssub
    9455             :       0,        // subo64_then_sub_32
    9456             :       0,        // zsub1_then_bsub
    9457             :       0,        // zsub1_then_dsub
    9458             :       0,        // zsub1_then_hsub
    9459             :       0,        // zsub1_then_ssub
    9460             :       0,        // zsub1_then_zsub
    9461             :       0,        // zsub1_then_zsub_hi
    9462             :       0,        // zsub3_then_bsub
    9463             :       0,        // zsub3_then_dsub
    9464             :       0,        // zsub3_then_hsub
    9465             :       0,        // zsub3_then_ssub
    9466             :       0,        // zsub3_then_zsub
    9467             :       0,        // zsub3_then_zsub_hi
    9468             :       0,        // zsub2_then_bsub
    9469             :       0,        // zsub2_then_dsub
    9470             :       0,        // zsub2_then_hsub
    9471             :       0,        // zsub2_then_ssub
    9472             :       0,        // zsub2_then_zsub
    9473             :       0,        // zsub2_then_zsub_hi
    9474             :       0,        // dsub0_dsub1
    9475             :       0,        // dsub0_dsub1_dsub2
    9476             :       0,        // dsub1_dsub2
    9477             :       0,        // dsub1_dsub2_dsub3
    9478             :       0,        // dsub2_dsub3
    9479             :       0,        // dsub_qsub1_then_dsub
    9480             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9481             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9482             :       0,        // qsub0_qsub1
    9483             :       0,        // qsub0_qsub1_qsub2
    9484             :       0,        // qsub1_qsub2
    9485             :       0,        // qsub1_qsub2_qsub3
    9486             :       0,        // qsub2_qsub3
    9487             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9488             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9489             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9490             :       0,        // sub_32_subo64_then_sub_32
    9491             :       0,        // dsub_zsub1_then_dsub
    9492             :       0,        // zsub_zsub1_then_zsub
    9493             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9494             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9495             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9496             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9497             :       0,        // zsub0_zsub1
    9498             :       0,        // zsub0_zsub1_zsub2
    9499             :       0,        // zsub1_zsub2
    9500             :       0,        // zsub1_zsub2_zsub3
    9501             :       0,        // zsub2_zsub3
    9502             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9503             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9504             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9505             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9506             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9507             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9508             :     },
    9509             :     {   // GPR64all
    9510             :       0,        // bsub
    9511             :       0,        // dsub
    9512             :       0,        // dsub0
    9513             :       0,        // dsub1
    9514             :       0,        // dsub2
    9515             :       0,        // dsub3
    9516             :       0,        // hsub
    9517             :       0,        // qhisub
    9518             :       0,        // qsub
    9519             :       0,        // qsub0
    9520             :       0,        // qsub1
    9521             :       0,        // qsub2
    9522             :       0,        // qsub3
    9523             :       0,        // ssub
    9524             :       16,       // sub_32 -> GPR64all
    9525             :       0,        // sube32
    9526             :       0,        // sube64
    9527             :       0,        // subo32
    9528             :       0,        // subo64
    9529             :       0,        // zsub
    9530             :       0,        // zsub0
    9531             :       0,        // zsub1
    9532             :       0,        // zsub2
    9533             :       0,        // zsub3
    9534             :       0,        // zsub_hi
    9535             :       0,        // dsub1_then_bsub
    9536             :       0,        // dsub1_then_hsub
    9537             :       0,        // dsub1_then_ssub
    9538             :       0,        // dsub3_then_bsub
    9539             :       0,        // dsub3_then_hsub
    9540             :       0,        // dsub3_then_ssub
    9541             :       0,        // dsub2_then_bsub
    9542             :       0,        // dsub2_then_hsub
    9543             :       0,        // dsub2_then_ssub
    9544             :       0,        // qsub1_then_bsub
    9545             :       0,        // qsub1_then_dsub
    9546             :       0,        // qsub1_then_hsub
    9547             :       0,        // qsub1_then_ssub
    9548             :       0,        // qsub3_then_bsub
    9549             :       0,        // qsub3_then_dsub
    9550             :       0,        // qsub3_then_hsub
    9551             :       0,        // qsub3_then_ssub
    9552             :       0,        // qsub2_then_bsub
    9553             :       0,        // qsub2_then_dsub
    9554             :       0,        // qsub2_then_hsub
    9555             :       0,        // qsub2_then_ssub
    9556             :       0,        // subo64_then_sub_32
    9557             :       0,        // zsub1_then_bsub
    9558             :       0,        // zsub1_then_dsub
    9559             :       0,        // zsub1_then_hsub
    9560             :       0,        // zsub1_then_ssub
    9561             :       0,        // zsub1_then_zsub
    9562             :       0,        // zsub1_then_zsub_hi
    9563             :       0,        // zsub3_then_bsub
    9564             :       0,        // zsub3_then_dsub
    9565             :       0,        // zsub3_then_hsub
    9566             :       0,        // zsub3_then_ssub
    9567             :       0,        // zsub3_then_zsub
    9568             :       0,        // zsub3_then_zsub_hi
    9569             :       0,        // zsub2_then_bsub
    9570             :       0,        // zsub2_then_dsub
    9571             :       0,        // zsub2_then_hsub
    9572             :       0,        // zsub2_then_ssub
    9573             :       0,        // zsub2_then_zsub
    9574             :       0,        // zsub2_then_zsub_hi
    9575             :       0,        // dsub0_dsub1
    9576             :       0,        // dsub0_dsub1_dsub2
    9577             :       0,        // dsub1_dsub2
    9578             :       0,        // dsub1_dsub2_dsub3
    9579             :       0,        // dsub2_dsub3
    9580             :       0,        // dsub_qsub1_then_dsub
    9581             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9582             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9583             :       0,        // qsub0_qsub1
    9584             :       0,        // qsub0_qsub1_qsub2
    9585             :       0,        // qsub1_qsub2
    9586             :       0,        // qsub1_qsub2_qsub3
    9587             :       0,        // qsub2_qsub3
    9588             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9589             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9590             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9591             :       0,        // sub_32_subo64_then_sub_32
    9592             :       0,        // dsub_zsub1_then_dsub
    9593             :       0,        // zsub_zsub1_then_zsub
    9594             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9595             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9596             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9597             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9598             :       0,        // zsub0_zsub1
    9599             :       0,        // zsub0_zsub1_zsub2
    9600             :       0,        // zsub1_zsub2
    9601             :       0,        // zsub1_zsub2_zsub3
    9602             :       0,        // zsub2_zsub3
    9603             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9604             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9605             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9606             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9607             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9608             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9609             :     },
    9610             :     {   // FPR64
    9611             :       17,       // bsub -> FPR64
    9612             :       0,        // dsub
    9613             :       0,        // dsub0
    9614             :       0,        // dsub1
    9615             :       0,        // dsub2
    9616             :       0,        // dsub3
    9617             :       17,       // hsub -> FPR64
    9618             :       0,        // qhisub
    9619             :       0,        // qsub
    9620             :       0,        // qsub0
    9621             :       0,        // qsub1
    9622             :       0,        // qsub2
    9623             :       0,        // qsub3
    9624             :       17,       // ssub -> FPR64
    9625             :       0,        // sub_32
    9626             :       0,        // sube32
    9627             :       0,        // sube64
    9628             :       0,        // subo32
    9629             :       0,        // subo64
    9630             :       0,        // zsub
    9631             :       0,        // zsub0
    9632             :       0,        // zsub1
    9633             :       0,        // zsub2
    9634             :       0,        // zsub3
    9635             :       0,        // zsub_hi
    9636             :       0,        // dsub1_then_bsub
    9637             :       0,        // dsub1_then_hsub
    9638             :       0,        // dsub1_then_ssub
    9639             :       0,        // dsub3_then_bsub
    9640             :       0,        // dsub3_then_hsub
    9641             :       0,        // dsub3_then_ssub
    9642             :       0,        // dsub2_then_bsub
    9643             :       0,        // dsub2_then_hsub
    9644             :       0,        // dsub2_then_ssub
    9645             :       0,        // qsub1_then_bsub
    9646             :       0,        // qsub1_then_dsub
    9647             :       0,        // qsub1_then_hsub
    9648             :       0,        // qsub1_then_ssub
    9649             :       0,        // qsub3_then_bsub
    9650             :       0,        // qsub3_then_dsub
    9651             :       0,        // qsub3_then_hsub
    9652             :       0,        // qsub3_then_ssub
    9653             :       0,        // qsub2_then_bsub
    9654             :       0,        // qsub2_then_dsub
    9655             :       0,        // qsub2_then_hsub
    9656             :       0,        // qsub2_then_ssub
    9657             :       0,        // subo64_then_sub_32
    9658             :       0,        // zsub1_then_bsub
    9659             :       0,        // zsub1_then_dsub
    9660             :       0,        // zsub1_then_hsub
    9661             :       0,        // zsub1_then_ssub
    9662             :       0,        // zsub1_then_zsub
    9663             :       0,        // zsub1_then_zsub_hi
    9664             :       0,        // zsub3_then_bsub
    9665             :       0,        // zsub3_then_dsub
    9666             :       0,        // zsub3_then_hsub
    9667             :       0,        // zsub3_then_ssub
    9668             :       0,        // zsub3_then_zsub
    9669             :       0,        // zsub3_then_zsub_hi
    9670             :       0,        // zsub2_then_bsub
    9671             :       0,        // zsub2_then_dsub
    9672             :       0,        // zsub2_then_hsub
    9673             :       0,        // zsub2_then_ssub
    9674             :       0,        // zsub2_then_zsub
    9675             :       0,        // zsub2_then_zsub_hi
    9676             :       0,        // dsub0_dsub1
    9677             :       0,        // dsub0_dsub1_dsub2
    9678             :       0,        // dsub1_dsub2
    9679             :       0,        // dsub1_dsub2_dsub3
    9680             :       0,        // dsub2_dsub3
    9681             :       0,        // dsub_qsub1_then_dsub
    9682             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9683             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9684             :       0,        // qsub0_qsub1
    9685             :       0,        // qsub0_qsub1_qsub2
    9686             :       0,        // qsub1_qsub2
    9687             :       0,        // qsub1_qsub2_qsub3
    9688             :       0,        // qsub2_qsub3
    9689             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9690             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9691             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9692             :       0,        // sub_32_subo64_then_sub_32
    9693             :       0,        // dsub_zsub1_then_dsub
    9694             :       0,        // zsub_zsub1_then_zsub
    9695             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9696             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9697             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9698             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9699             :       0,        // zsub0_zsub1
    9700             :       0,        // zsub0_zsub1_zsub2
    9701             :       0,        // zsub1_zsub2
    9702             :       0,        // zsub1_zsub2_zsub3
    9703             :       0,        // zsub2_zsub3
    9704             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9705             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9706             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9707             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9708             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9709             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9710             :     },
    9711             :     {   // GPR64
    9712             :       0,        // bsub
    9713             :       0,        // dsub
    9714             :       0,        // dsub0
    9715             :       0,        // dsub1
    9716             :       0,        // dsub2
    9717             :       0,        // dsub3
    9718             :       0,        // hsub
    9719             :       0,        // qhisub
    9720             :       0,        // qsub
    9721             :       0,        // qsub0
    9722             :       0,        // qsub1
    9723             :       0,        // qsub2
    9724             :       0,        // qsub3
    9725             :       0,        // ssub
    9726             :       18,       // sub_32 -> GPR64
    9727             :       0,        // sube32
    9728             :       0,        // sube64
    9729             :       0,        // subo32
    9730             :       0,        // subo64
    9731             :       0,        // zsub
    9732             :       0,        // zsub0
    9733             :       0,        // zsub1
    9734             :       0,        // zsub2
    9735             :       0,        // zsub3
    9736             :       0,        // zsub_hi
    9737             :       0,        // dsub1_then_bsub
    9738             :       0,        // dsub1_then_hsub
    9739             :       0,        // dsub1_then_ssub
    9740             :       0,        // dsub3_then_bsub
    9741             :       0,        // dsub3_then_hsub
    9742             :       0,        // dsub3_then_ssub
    9743             :       0,        // dsub2_then_bsub
    9744             :       0,        // dsub2_then_hsub
    9745             :       0,        // dsub2_then_ssub
    9746             :       0,        // qsub1_then_bsub
    9747             :       0,        // qsub1_then_dsub
    9748             :       0,        // qsub1_then_hsub
    9749             :       0,        // qsub1_then_ssub
    9750             :       0,        // qsub3_then_bsub
    9751             :       0,        // qsub3_then_dsub
    9752             :       0,        // qsub3_then_hsub
    9753             :       0,        // qsub3_then_ssub
    9754             :       0,        // qsub2_then_bsub
    9755             :       0,        // qsub2_then_dsub
    9756             :       0,        // qsub2_then_hsub
    9757             :       0,        // qsub2_then_ssub
    9758             :       0,        // subo64_then_sub_32
    9759             :       0,        // zsub1_then_bsub
    9760             :       0,        // zsub1_then_dsub
    9761             :       0,        // zsub1_then_hsub
    9762             :       0,        // zsub1_then_ssub
    9763             :       0,        // zsub1_then_zsub
    9764             :       0,        // zsub1_then_zsub_hi
    9765             :       0,        // zsub3_then_bsub
    9766             :       0,        // zsub3_then_dsub
    9767             :       0,        // zsub3_then_hsub
    9768             :       0,        // zsub3_then_ssub
    9769             :       0,        // zsub3_then_zsub
    9770             :       0,        // zsub3_then_zsub_hi
    9771             :       0,        // zsub2_then_bsub
    9772             :       0,        // zsub2_then_dsub
    9773             :       0,        // zsub2_then_hsub
    9774             :       0,        // zsub2_then_ssub
    9775             :       0,        // zsub2_then_zsub
    9776             :       0,        // zsub2_then_zsub_hi
    9777             :       0,        // dsub0_dsub1
    9778             :       0,        // dsub0_dsub1_dsub2
    9779             :       0,        // dsub1_dsub2
    9780             :       0,        // dsub1_dsub2_dsub3
    9781             :       0,        // dsub2_dsub3
    9782             :       0,        // dsub_qsub1_then_dsub
    9783             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9784             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9785             :       0,        // qsub0_qsub1
    9786             :       0,        // qsub0_qsub1_qsub2
    9787             :       0,        // qsub1_qsub2
    9788             :       0,        // qsub1_qsub2_qsub3
    9789             :       0,        // qsub2_qsub3
    9790             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9791             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9792             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9793             :       0,        // sub_32_subo64_then_sub_32
    9794             :       0,        // dsub_zsub1_then_dsub
    9795             :       0,        // zsub_zsub1_then_zsub
    9796             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9797             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9798             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9799             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9800             :       0,        // zsub0_zsub1
    9801             :       0,        // zsub0_zsub1_zsub2
    9802             :       0,        // zsub1_zsub2
    9803             :       0,        // zsub1_zsub2_zsub3
    9804             :       0,        // zsub2_zsub3
    9805             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9806             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9807             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9808             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9809             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9810             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9811             :     },
    9812             :     {   // GPR64sp
    9813             :       0,        // bsub
    9814             :       0,        // dsub
    9815             :       0,        // dsub0
    9816             :       0,        // dsub1
    9817             :       0,        // dsub2
    9818             :       0,        // dsub3
    9819             :       0,        // hsub
    9820             :       0,        // qhisub
    9821             :       0,        // qsub
    9822             :       0,        // qsub0
    9823             :       0,        // qsub1
    9824             :       0,        // qsub2
    9825             :       0,        // qsub3
    9826             :       0,        // ssub
    9827             :       19,       // sub_32 -> GPR64sp
    9828             :       0,        // sube32
    9829             :       0,        // sube64
    9830             :       0,        // subo32
    9831             :       0,        // subo64
    9832             :       0,        // zsub
    9833             :       0,        // zsub0
    9834             :       0,        // zsub1
    9835             :       0,        // zsub2
    9836             :       0,        // zsub3
    9837             :       0,        // zsub_hi
    9838             :       0,        // dsub1_then_bsub
    9839             :       0,        // dsub1_then_hsub
    9840             :       0,        // dsub1_then_ssub
    9841             :       0,        // dsub3_then_bsub
    9842             :       0,        // dsub3_then_hsub
    9843             :       0,        // dsub3_then_ssub
    9844             :       0,        // dsub2_then_bsub
    9845             :       0,        // dsub2_then_hsub
    9846             :       0,        // dsub2_then_ssub
    9847             :       0,        // qsub1_then_bsub
    9848             :       0,        // qsub1_then_dsub
    9849             :       0,        // qsub1_then_hsub
    9850             :       0,        // qsub1_then_ssub
    9851             :       0,        // qsub3_then_bsub
    9852             :       0,        // qsub3_then_dsub
    9853             :       0,        // qsub3_then_hsub
    9854             :       0,        // qsub3_then_ssub
    9855             :       0,        // qsub2_then_bsub
    9856             :       0,        // qsub2_then_dsub
    9857             :       0,        // qsub2_then_hsub
    9858             :       0,        // qsub2_then_ssub
    9859             :       0,        // subo64_then_sub_32
    9860             :       0,        // zsub1_then_bsub
    9861             :       0,        // zsub1_then_dsub
    9862             :       0,        // zsub1_then_hsub
    9863             :       0,        // zsub1_then_ssub
    9864             :       0,        // zsub1_then_zsub
    9865             :       0,        // zsub1_then_zsub_hi
    9866             :       0,        // zsub3_then_bsub
    9867             :       0,        // zsub3_then_dsub
    9868             :       0,        // zsub3_then_hsub
    9869             :       0,        // zsub3_then_ssub
    9870             :       0,        // zsub3_then_zsub
    9871             :       0,        // zsub3_then_zsub_hi
    9872             :       0,        // zsub2_then_bsub
    9873             :       0,        // zsub2_then_dsub
    9874             :       0,        // zsub2_then_hsub
    9875             :       0,        // zsub2_then_ssub
    9876             :       0,        // zsub2_then_zsub
    9877             :       0,        // zsub2_then_zsub_hi
    9878             :       0,        // dsub0_dsub1
    9879             :       0,        // dsub0_dsub1_dsub2
    9880             :       0,        // dsub1_dsub2
    9881             :       0,        // dsub1_dsub2_dsub3
    9882             :       0,        // dsub2_dsub3
    9883             :       0,        // dsub_qsub1_then_dsub
    9884             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9885             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9886             :       0,        // qsub0_qsub1
    9887             :       0,        // qsub0_qsub1_qsub2
    9888             :       0,        // qsub1_qsub2
    9889             :       0,        // qsub1_qsub2_qsub3
    9890             :       0,        // qsub2_qsub3
    9891             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9892             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9893             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9894             :       0,        // sub_32_subo64_then_sub_32
    9895             :       0,        // dsub_zsub1_then_dsub
    9896             :       0,        // zsub_zsub1_then_zsub
    9897             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9898             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9899             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9900             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9901             :       0,        // zsub0_zsub1
    9902             :       0,        // zsub0_zsub1_zsub2
    9903             :       0,        // zsub1_zsub2
    9904             :       0,        // zsub1_zsub2_zsub3
    9905             :       0,        // zsub2_zsub3
    9906             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9907             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9908             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9909             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9910             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9911             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9912             :     },
    9913             :     {   // GPR64common
    9914             :       0,        // bsub
    9915             :       0,        // dsub
    9916             :       0,        // dsub0
    9917             :       0,        // dsub1
    9918             :       0,        // dsub2
    9919             :       0,        // dsub3
    9920             :       0,        // hsub
    9921             :       0,        // qhisub
    9922             :       0,        // qsub
    9923             :       0,        // qsub0
    9924             :       0,        // qsub1
    9925             :       0,        // qsub2
    9926             :       0,        // qsub3
    9927             :       0,        // ssub
    9928             :       20,       // sub_32 -> GPR64common
    9929             :       0,        // sube32
    9930             :       0,        // sube64
    9931             :       0,        // subo32
    9932             :       0,        // subo64
    9933             :       0,        // zsub
    9934             :       0,        // zsub0
    9935             :       0,        // zsub1
    9936             :       0,        // zsub2
    9937             :       0,        // zsub3
    9938             :       0,        // zsub_hi
    9939             :       0,        // dsub1_then_bsub
    9940             :       0,        // dsub1_then_hsub
    9941             :       0,        // dsub1_then_ssub
    9942             :       0,        // dsub3_then_bsub
    9943             :       0,        // dsub3_then_hsub
    9944             :       0,        // dsub3_then_ssub
    9945             :       0,        // dsub2_then_bsub
    9946             :       0,        // dsub2_then_hsub
    9947             :       0,        // dsub2_then_ssub
    9948             :       0,        // qsub1_then_bsub
    9949             :       0,        // qsub1_then_dsub
    9950             :       0,        // qsub1_then_hsub
    9951             :       0,        // qsub1_then_ssub
    9952             :       0,        // qsub3_then_bsub
    9953             :       0,        // qsub3_then_dsub
    9954             :       0,        // qsub3_then_hsub
    9955             :       0,        // qsub3_then_ssub
    9956             :       0,        // qsub2_then_bsub
    9957             :       0,        // qsub2_then_dsub
    9958             :       0,        // qsub2_then_hsub
    9959             :       0,        // qsub2_then_ssub
    9960             :       0,        // subo64_then_sub_32
    9961             :       0,        // zsub1_then_bsub
    9962             :       0,        // zsub1_then_dsub
    9963             :       0,        // zsub1_then_hsub
    9964             :       0,        // zsub1_then_ssub
    9965             :       0,        // zsub1_then_zsub
    9966             :       0,        // zsub1_then_zsub_hi
    9967             :       0,        // zsub3_then_bsub
    9968             :       0,        // zsub3_then_dsub
    9969             :       0,        // zsub3_then_hsub
    9970             :       0,        // zsub3_then_ssub
    9971             :       0,        // zsub3_then_zsub
    9972             :       0,        // zsub3_then_zsub_hi
    9973             :       0,        // zsub2_then_bsub
    9974             :       0,        // zsub2_then_dsub
    9975             :       0,        // zsub2_then_hsub
    9976             :       0,        // zsub2_then_ssub
    9977             :       0,        // zsub2_then_zsub
    9978             :       0,        // zsub2_then_zsub_hi
    9979             :       0,        // dsub0_dsub1
    9980             :       0,        // dsub0_dsub1_dsub2
    9981             :       0,        // dsub1_dsub2
    9982             :       0,        // dsub1_dsub2_dsub3
    9983             :       0,        // dsub2_dsub3
    9984             :       0,        // dsub_qsub1_then_dsub
    9985             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9986             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9987             :       0,        // qsub0_qsub1
    9988             :       0,        // qsub0_qsub1_qsub2
    9989             :       0,        // qsub1_qsub2
    9990             :       0,        // qsub1_qsub2_qsub3
    9991             :       0,        // qsub2_qsub3
    9992             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9993             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9994             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9995             :       0,        // sub_32_subo64_then_sub_32
    9996             :       0,        // dsub_zsub1_then_dsub
    9997             :       0,        // zsub_zsub1_then_zsub
    9998             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9999             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10000             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10001             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10002             :       0,        // zsub0_zsub1
   10003             :       0,        // zsub0_zsub1_zsub2
   10004             :       0,        // zsub1_zsub2
   10005             :       0,        // zsub1_zsub2_zsub3
   10006             :       0,        // zsub2_zsub3
   10007             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10008             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10009             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10010             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10011             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10012             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10013             :     },
   10014             :     {   // tcGPR64
   10015             :       0,        // bsub
   10016             :       0,        // dsub
   10017             :       0,        // dsub0
   10018             :       0,        // dsub1
   10019             :       0,        // dsub2
   10020             :       0,        // dsub3
   10021             :       0,        // hsub
   10022             :       0,        // qhisub
   10023             :       0,        // qsub
   10024             :       0,        // qsub0
   10025             :       0,        // qsub1
   10026             :       0,        // qsub2
   10027             :       0,        // qsub3
   10028             :       0,        // ssub
   10029             :       21,       // sub_32 -> tcGPR64
   10030             :       0,        // sube32
   10031             :       0,        // sube64
   10032             :       0,        // subo32
   10033             :       0,        // subo64
   10034             :       0,        // zsub
   10035             :       0,        // zsub0
   10036             :       0,        // zsub1
   10037             :       0,        // zsub2
   10038             :       0,        // zsub3
   10039             :       0,        // zsub_hi
   10040             :       0,        // dsub1_then_bsub
   10041             :       0,        // dsub1_then_hsub
   10042             :       0,        // dsub1_then_ssub
   10043             :       0,        // dsub3_then_bsub
   10044             :       0,        // dsub3_then_hsub
   10045             :       0,        // dsub3_then_ssub
   10046             :       0,        // dsub2_then_bsub
   10047             :       0,        // dsub2_then_hsub
   10048             :       0,        // dsub2_then_ssub
   10049             :       0,        // qsub1_then_bsub
   10050             :       0,        // qsub1_then_dsub
   10051             :       0,        // qsub1_then_hsub
   10052             :       0,        // qsub1_then_ssub
   10053             :       0,        // qsub3_then_bsub
   10054             :       0,        // qsub3_then_dsub
   10055             :       0,        // qsub3_then_hsub
   10056             :       0,        // qsub3_then_ssub
   10057             :       0,        // qsub2_then_bsub
   10058             :       0,        // qsub2_then_dsub
   10059             :       0,        // qsub2_then_hsub
   10060             :       0,        // qsub2_then_ssub
   10061             :       0,        // subo64_then_sub_32
   10062             :       0,        // zsub1_then_bsub
   10063             :       0,        // zsub1_then_dsub
   10064             :       0,        // zsub1_then_hsub
   10065             :       0,        // zsub1_then_ssub
   10066             :       0,        // zsub1_then_zsub
   10067             :       0,        // zsub1_then_zsub_hi
   10068             :       0,        // zsub3_then_bsub
   10069             :       0,        // zsub3_then_dsub
   10070             :       0,        // zsub3_then_hsub
   10071             :       0,        // zsub3_then_ssub
   10072             :       0,        // zsub3_then_zsub
   10073             :       0,        // zsub3_then_zsub_hi
   10074             :       0,        // zsub2_then_bsub
   10075             :       0,        // zsub2_then_dsub
   10076             :       0,        // zsub2_then_hsub
   10077             :       0,        // zsub2_then_ssub
   10078             :       0,        // zsub2_then_zsub
   10079             :       0,        // zsub2_then_zsub_hi
   10080             :       0,        // dsub0_dsub1
   10081             :       0,        // dsub0_dsub1_dsub2
   10082             :       0,        // dsub1_dsub2
   10083             :       0,        // dsub1_dsub2_dsub3
   10084             :       0,        // dsub2_dsub3
   10085             :       0,        // dsub_qsub1_then_dsub
   10086             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10087             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10088             :       0,        // qsub0_qsub1
   10089             :       0,        // qsub0_qsub1_qsub2
   10090             :       0,        // qsub1_qsub2
   10091             :       0,        // qsub1_qsub2_qsub3
   10092             :       0,        // qsub2_qsub3
   10093             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10094             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10095             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10096             :       0,        // sub_32_subo64_then_sub_32
   10097             :       0,        // dsub_zsub1_then_dsub
   10098             :       0,        // zsub_zsub1_then_zsub
   10099             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10100             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10101             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10102             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10103             :       0,        // zsub0_zsub1
   10104             :       0,        // zsub0_zsub1_zsub2
   10105             :       0,        // zsub1_zsub2
   10106             :       0,        // zsub1_zsub2_zsub3
   10107             :       0,        // zsub2_zsub3
   10108             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10109             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10110             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10111             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10112             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10113             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10114             :     },
   10115             :     {   // GPR64sponly
   10116             :       0,        // bsub
   10117             :       0,        // dsub
   10118             :       0,        // dsub0
   10119             :       0,        // dsub1
   10120             :       0,        // dsub2
   10121             :       0,        // dsub3
   10122             :       0,        // hsub
   10123             :       0,        // qhisub
   10124             :       0,        // qsub
   10125             :       0,        // qsub0
   10126             :       0,        // qsub1
   10127             :       0,        // qsub2
   10128             :       0,        // qsub3
   10129             :       0,        // ssub
   10130             :       22,       // sub_32 -> GPR64sponly
   10131             :       0,        // sube32
   10132             :       0,        // sube64
   10133             :       0,        // subo32
   10134             :       0,        // subo64
   10135             :       0,        // zsub
   10136             :       0,        // zsub0
   10137             :       0,        // zsub1
   10138             :       0,        // zsub2
   10139             :       0,        // zsub3
   10140             :       0,        // zsub_hi
   10141             :       0,        // dsub1_then_bsub
   10142             :       0,        // dsub1_then_hsub
   10143             :       0,        // dsub1_then_ssub
   10144             :       0,        // dsub3_then_bsub
   10145             :       0,        // dsub3_then_hsub
   10146             :       0,        // dsub3_then_ssub
   10147             :       0,        // dsub2_then_bsub
   10148             :       0,        // dsub2_then_hsub
   10149             :       0,        // dsub2_then_ssub
   10150             :       0,        // qsub1_then_bsub
   10151             :       0,        // qsub1_then_dsub
   10152             :       0,        // qsub1_then_hsub
   10153             :       0,        // qsub1_then_ssub
   10154             :       0,        // qsub3_then_bsub
   10155             :       0,        // qsub3_then_dsub
   10156             :       0,        // qsub3_then_hsub
   10157             :       0,        // qsub3_then_ssub
   10158             :       0,        // qsub2_then_bsub
   10159             :       0,        // qsub2_then_dsub
   10160             :       0,        // qsub2_then_hsub
   10161             :       0,        // qsub2_then_ssub
   10162             :       0,        // subo64_then_sub_32
   10163             :       0,        // zsub1_then_bsub
   10164             :       0,        // zsub1_then_dsub
   10165             :       0,        // zsub1_then_hsub
   10166             :       0,        // zsub1_then_ssub
   10167             :       0,        // zsub1_then_zsub
   10168             :       0,        // zsub1_then_zsub_hi
   10169             :       0,        // zsub3_then_bsub
   10170             :       0,        // zsub3_then_dsub
   10171             :       0,        // zsub3_then_hsub
   10172             :       0,        // zsub3_then_ssub
   10173             :       0,        // zsub3_then_zsub
   10174             :       0,        // zsub3_then_zsub_hi
   10175             :       0,        // zsub2_then_bsub
   10176             :       0,        // zsub2_then_dsub
   10177             :       0,        // zsub2_then_hsub
   10178             :       0,        // zsub2_then_ssub
   10179             :       0,        // zsub2_then_zsub
   10180             :       0,        // zsub2_then_zsub_hi
   10181             :       0,        // dsub0_dsub1
   10182             :       0,        // dsub0_dsub1_dsub2
   10183             :       0,        // dsub1_dsub2
   10184             :       0,        // dsub1_dsub2_dsub3
   10185             :       0,        // dsub2_dsub3
   10186             :       0,        // dsub_qsub1_then_dsub
   10187             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10188             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10189             :       0,        // qsub0_qsub1
   10190             :       0,        // qsub0_qsub1_qsub2
   10191             :       0,        // qsub1_qsub2
   10192             :       0,        // qsub1_qsub2_qsub3
   10193             :       0,        // qsub2_qsub3
   10194             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10195             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10196             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10197             :       0,        // sub_32_subo64_then_sub_32
   10198             :       0,        // dsub_zsub1_then_dsub
   10199             :       0,        // zsub_zsub1_then_zsub
   10200             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10201             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10202             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10203             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10204             :       0,        // zsub0_zsub1
   10205             :       0,        // zsub0_zsub1_zsub2
   10206             :       0,        // zsub1_zsub2
   10207             :       0,        // zsub1_zsub2_zsub3
   10208             :       0,        // zsub2_zsub3
   10209             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10210             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10211             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10212             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10213             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10214             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10215             :     },
   10216             :     {   // DD
   10217             :       23,       // bsub -> DD
   10218             :       0,        // dsub
   10219             :       23,       // dsub0 -> DD
   10220             :       23,       // dsub1 -> DD
   10221             :       0,        // dsub2
   10222             :       0,        // dsub3
   10223             :       23,       // hsub -> DD
   10224             :       0,        // qhisub
   10225             :       0,        // qsub
   10226             :       0,        // qsub0
   10227             :       0,        // qsub1
   10228             :       0,        // qsub2
   10229             :       0,        // qsub3
   10230             :       23,       // ssub -> DD
   10231             :       0,        // sub_32
   10232             :       0,        // sube32
   10233             :       0,        // sube64
   10234             :       0,        // subo32
   10235             :       0,        // subo64
   10236             :       0,        // zsub
   10237             :       0,        // zsub0
   10238             :       0,        // zsub1
   10239             :       0,        // zsub2
   10240             :       0,        // zsub3
   10241             :       0,        // zsub_hi
   10242             :       23,       // dsub1_then_bsub -> DD
   10243             :       23,       // dsub1_then_hsub -> DD
   10244             :       23,       // dsub1_then_ssub -> DD
   10245             :       0,        // dsub3_then_bsub
   10246             :       0,        // dsub3_then_hsub
   10247             :       0,        // dsub3_then_ssub
   10248             :       0,        // dsub2_then_bsub
   10249             :       0,        // dsub2_then_hsub
   10250             :       0,        // dsub2_then_ssub
   10251             :       0,        // qsub1_then_bsub
   10252             :       0,        // qsub1_then_dsub
   10253             :       0,        // qsub1_then_hsub
   10254             :       0,        // qsub1_then_ssub
   10255             :       0,        // qsub3_then_bsub
   10256             :       0,        // qsub3_then_dsub
   10257             :       0,        // qsub3_then_hsub
   10258             :       0,        // qsub3_then_ssub
   10259             :       0,        // qsub2_then_bsub
   10260             :       0,        // qsub2_then_dsub
   10261             :       0,        // qsub2_then_hsub
   10262             :       0,        // qsub2_then_ssub
   10263             :       0,        // subo64_then_sub_32
   10264             :       0,        // zsub1_then_bsub
   10265             :       0,        // zsub1_then_dsub
   10266             :       0,        // zsub1_then_hsub
   10267             :       0,        // zsub1_then_ssub
   10268             :       0,        // zsub1_then_zsub
   10269             :       0,        // zsub1_then_zsub_hi
   10270             :       0,        // zsub3_then_bsub
   10271             :       0,        // zsub3_then_dsub
   10272             :       0,        // zsub3_then_hsub
   10273             :       0,        // zsub3_then_ssub
   10274             :       0,        // zsub3_then_zsub
   10275             :       0,        // zsub3_then_zsub_hi
   10276             :       0,        // zsub2_then_bsub
   10277             :       0,        // zsub2_then_dsub
   10278             :       0,        // zsub2_then_hsub
   10279             :       0,        // zsub2_then_ssub
   10280             :       0,        // zsub2_then_zsub
   10281             :       0,        // zsub2_then_zsub_hi
   10282             :       0,        // dsub0_dsub1
   10283             :       0,        // dsub0_dsub1_dsub2
   10284             :       0,        // dsub1_dsub2
   10285             :       0,        // dsub1_dsub2_dsub3
   10286             :       0,        // dsub2_dsub3
   10287             :       0,        // dsub_qsub1_then_dsub
   10288             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10289             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10290             :       0,        // qsub0_qsub1
   10291             :       0,        // qsub0_qsub1_qsub2
   10292             :       0,        // qsub1_qsub2
   10293             :       0,        // qsub1_qsub2_qsub3
   10294             :       0,        // qsub2_qsub3
   10295             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10296             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10297             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10298             :       0,        // sub_32_subo64_then_sub_32
   10299             :       0,        // dsub_zsub1_then_dsub
   10300             :       0,        // zsub_zsub1_then_zsub
   10301             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10302             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10303             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10304             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10305             :       0,        // zsub0_zsub1
   10306             :       0,        // zsub0_zsub1_zsub2
   10307             :       0,        // zsub1_zsub2
   10308             :       0,        // zsub1_zsub2_zsub3
   10309             :       0,        // zsub2_zsub3
   10310             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10311             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10312             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10313             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10314             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10315             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10316             :     },
   10317             :     {   // XSeqPairsClass
   10318             :       0,        // bsub
   10319             :       0,        // dsub
   10320             :       0,        // dsub0
   10321             :       0,        // dsub1
   10322             :       0,        // dsub2
   10323             :       0,        // dsub3
   10324             :       0,        // hsub
   10325             :       0,        // qhisub
   10326             :       0,        // qsub
   10327             :       0,        // qsub0
   10328             :       0,        // qsub1
   10329             :       0,        // qsub2
   10330             :       0,        // qsub3
   10331             :       0,        // ssub
   10332             :       24,       // sub_32 -> XSeqPairsClass
   10333             :       0,        // sube32
   10334             :       24,       // sube64 -> XSeqPairsClass
   10335             :       0,        // subo32
   10336             :       24,       // subo64 -> XSeqPairsClass
   10337             :       0,        // zsub
   10338             :       0,        // zsub0
   10339             :       0,        // zsub1
   10340             :       0,        // zsub2
   10341             :       0,        // zsub3
   10342             :       0,        // zsub_hi
   10343             :       0,        // dsub1_then_bsub
   10344             :       0,        // dsub1_then_hsub
   10345             :       0,        // dsub1_then_ssub
   10346             :       0,        // dsub3_then_bsub
   10347             :       0,        // dsub3_then_hsub
   10348             :       0,        // dsub3_then_ssub
   10349             :       0,        // dsub2_then_bsub
   10350             :       0,        // dsub2_then_hsub
   10351             :       0,        // dsub2_then_ssub
   10352             :       0,        // qsub1_then_bsub
   10353             :       0,        // qsub1_then_dsub
   10354             :       0,        // qsub1_then_hsub
   10355             :       0,        // qsub1_then_ssub
   10356             :       0,        // qsub3_then_bsub
   10357             :       0,        // qsub3_then_dsub
   10358             :       0,        // qsub3_then_hsub
   10359             :       0,        // qsub3_then_ssub
   10360             :       0,        // qsub2_then_bsub
   10361             :       0,        // qsub2_then_dsub
   10362             :       0,        // qsub2_then_hsub
   10363             :       0,        // qsub2_then_ssub
   10364             :       24,       // subo64_then_sub_32 -> XSeqPairsClass
   10365             :       0,        // zsub1_then_bsub
   10366             :       0,        // zsub1_then_dsub
   10367             :       0,        // zsub1_then_hsub
   10368             :       0,        // zsub1_then_ssub
   10369             :       0,        // zsub1_then_zsub
   10370             :       0,        // zsub1_then_zsub_hi
   10371             :       0,        // zsub3_then_bsub
   10372             :       0,        // zsub3_then_dsub
   10373             :       0,        // zsub3_then_hsub
   10374             :       0,        // zsub3_then_ssub
   10375             :       0,        // zsub3_then_zsub
   10376             :       0,        // zsub3_then_zsub_hi
   10377             :       0,        // zsub2_then_bsub
   10378             :       0,        // zsub2_then_dsub
   10379             :       0,        // zsub2_then_hsub
   10380             :       0,        // zsub2_then_ssub
   10381             :       0,        // zsub2_then_zsub
   10382             :       0,        // zsub2_then_zsub_hi
   10383             :       0,        // dsub0_dsub1
   10384             :       0,        // dsub0_dsub1_dsub2
   10385             :       0,        // dsub1_dsub2
   10386             :       0,        // dsub1_dsub2_dsub3
   10387             :       0,        // dsub2_dsub3
   10388             :       0,        // dsub_qsub1_then_dsub
   10389             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10390             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10391             :       0,        // qsub0_qsub1
   10392             :       0,        // qsub0_qsub1_qsub2
   10393             :       0,        // qsub1_qsub2
   10394             :       0,        // qsub1_qsub2_qsub3
   10395             :       0,        // qsub2_qsub3
   10396             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10397             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10398             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10399             :       24,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass
   10400             :       0,        // dsub_zsub1_then_dsub
   10401             :       0,        // zsub_zsub1_then_zsub
   10402             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10403             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10404             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10405             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10406             :       0,        // zsub0_zsub1
   10407             :       0,        // zsub0_zsub1_zsub2
   10408             :       0,        // zsub1_zsub2
   10409             :       0,        // zsub1_zsub2_zsub3
   10410             :       0,        // zsub2_zsub3
   10411             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10412             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10413             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10414             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10415             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10416             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10417             :     },
   10418             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common
   10419             :       0,        // bsub
   10420             :       0,        // dsub
   10421             :       0,        // dsub0
   10422             :       0,        // dsub1
   10423             :       0,        // dsub2
   10424             :       0,        // dsub3
   10425             :       0,        // hsub
   10426             :       0,        // qhisub
   10427             :       0,        // qsub
   10428             :       0,        // qsub0
   10429             :       0,        // qsub1
   10430             :       0,        // qsub2
   10431             :       0,        // qsub3
   10432             :       0,        // ssub
   10433             :       25,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
   10434             :       0,        // sube32
   10435             :       25,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common
   10436             :       0,        // subo32
   10437             :       25,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common
   10438             :       0,        // zsub
   10439             :       0,        // zsub0
   10440             :       0,        // zsub1
   10441             :       0,        // zsub2
   10442             :       0,        // zsub3
   10443             :       0,        // zsub_hi
   10444             :       0,        // dsub1_then_bsub
   10445             :       0,        // dsub1_then_hsub
   10446             :       0,        // dsub1_then_ssub
   10447             :       0,        // dsub3_then_bsub
   10448             :       0,        // dsub3_then_hsub
   10449             :       0,        // dsub3_then_ssub
   10450             :       0,        // dsub2_then_bsub
   10451             :       0,        // dsub2_then_hsub
   10452             :       0,        // dsub2_then_ssub
   10453             :       0,        // qsub1_then_bsub
   10454             :       0,        // qsub1_then_dsub
   10455             :       0,        // qsub1_then_hsub
   10456             :       0,        // qsub1_then_ssub
   10457             :       0,        // qsub3_then_bsub
   10458             :       0,        // qsub3_then_dsub
   10459             :       0,        // qsub3_then_hsub
   10460             :       0,        // qsub3_then_ssub
   10461             :       0,        // qsub2_then_bsub
   10462             :       0,        // qsub2_then_dsub
   10463             :       0,        // qsub2_then_hsub
   10464             :       0,        // qsub2_then_ssub
   10465             :       25,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
   10466             :       0,        // zsub1_then_bsub
   10467             :       0,        // zsub1_then_dsub
   10468             :       0,        // zsub1_then_hsub
   10469             :       0,        // zsub1_then_ssub
   10470             :       0,        // zsub1_then_zsub
   10471             :       0,        // zsub1_then_zsub_hi
   10472             :       0,        // zsub3_then_bsub
   10473             :       0,        // zsub3_then_dsub
   10474             :       0,        // zsub3_then_hsub
   10475             :       0,        // zsub3_then_ssub
   10476             :       0,        // zsub3_then_zsub
   10477             :       0,        // zsub3_then_zsub_hi
   10478             :       0,        // zsub2_then_bsub
   10479             :       0,        // zsub2_then_dsub
   10480             :       0,        // zsub2_then_hsub
   10481             :       0,        // zsub2_then_ssub
   10482             :       0,        // zsub2_then_zsub
   10483             :       0,        // zsub2_then_zsub_hi
   10484             :       0,        // dsub0_dsub1
   10485             :       0,        // dsub0_dsub1_dsub2
   10486             :       0,        // dsub1_dsub2
   10487             :       0,        // dsub1_dsub2_dsub3
   10488             :       0,        // dsub2_dsub3
   10489             :       0,        // dsub_qsub1_then_dsub
   10490             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10491             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10492             :       0,        // qsub0_qsub1
   10493             :       0,        // qsub0_qsub1_qsub2
   10494             :       0,        // qsub1_qsub2
   10495             :       0,        // qsub1_qsub2_qsub3
   10496             :       0,        // qsub2_qsub3
   10497             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10498             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10499             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10500             :       25,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common
   10501             :       0,        // dsub_zsub1_then_dsub
   10502             :       0,        // zsub_zsub1_then_zsub
   10503             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10504             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10505             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10506             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10507             :       0,        // zsub0_zsub1
   10508             :       0,        // zsub0_zsub1_zsub2
   10509             :       0,        // zsub1_zsub2
   10510             :       0,        // zsub1_zsub2_zsub3
   10511             :       0,        // zsub2_zsub3
   10512             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10513             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10514             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10515             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10516             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10517             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10518             :     },
   10519             :     {   // XSeqPairsClass_with_subo64_in_GPR64common
   10520             :       0,        // bsub
   10521             :       0,        // dsub
   10522             :       0,        // dsub0
   10523             :       0,        // dsub1
   10524             :       0,        // dsub2
   10525             :       0,        // dsub3
   10526             :       0,        // hsub
   10527             :       0,        // qhisub
   10528             :       0,        // qsub
   10529             :       0,        // qsub0
   10530             :       0,        // qsub1
   10531             :       0,        // qsub2
   10532             :       0,        // qsub3
   10533             :       0,        // ssub
   10534             :       26,       // sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
   10535             :       0,        // sube32
   10536             :       26,       // sube64 -> XSeqPairsClass_with_subo64_in_GPR64common
   10537             :       0,        // subo32
   10538             :       26,       // subo64 -> XSeqPairsClass_with_subo64_in_GPR64common
   10539             :       0,        // zsub
   10540             :       0,        // zsub0
   10541             :       0,        // zsub1
   10542             :       0,        // zsub2
   10543             :       0,        // zsub3
   10544             :       0,        // zsub_hi
   10545             :       0,        // dsub1_then_bsub
   10546             :       0,        // dsub1_then_hsub
   10547             :       0,        // dsub1_then_ssub
   10548             :       0,        // dsub3_then_bsub
   10549             :       0,        // dsub3_then_hsub
   10550             :       0,        // dsub3_then_ssub
   10551             :       0,        // dsub2_then_bsub
   10552             :       0,        // dsub2_then_hsub
   10553             :       0,        // dsub2_then_ssub
   10554             :       0,        // qsub1_then_bsub
   10555             :       0,        // qsub1_then_dsub
   10556             :       0,        // qsub1_then_hsub
   10557             :       0,        // qsub1_then_ssub
   10558             :       0,        // qsub3_then_bsub
   10559             :       0,        // qsub3_then_dsub
   10560             :       0,        // qsub3_then_hsub
   10561             :       0,        // qsub3_then_ssub
   10562             :       0,        // qsub2_then_bsub
   10563             :       0,        // qsub2_then_dsub
   10564             :       0,        // qsub2_then_hsub
   10565             :       0,        // qsub2_then_ssub
   10566             :       26,       // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
   10567             :       0,        // zsub1_then_bsub
   10568             :       0,        // zsub1_then_dsub
   10569             :       0,        // zsub1_then_hsub
   10570             :       0,        // zsub1_then_ssub
   10571             :       0,        // zsub1_then_zsub
   10572             :       0,        // zsub1_then_zsub_hi
   10573             :       0,        // zsub3_then_bsub
   10574             :       0,        // zsub3_then_dsub
   10575             :       0,        // zsub3_then_hsub
   10576             :       0,        // zsub3_then_ssub
   10577             :       0,        // zsub3_then_zsub
   10578             :       0,        // zsub3_then_zsub_hi
   10579             :       0,        // zsub2_then_bsub
   10580             :       0,        // zsub2_then_dsub
   10581             :       0,        // zsub2_then_hsub
   10582             :       0,        // zsub2_then_ssub
   10583             :       0,        // zsub2_then_zsub
   10584             :       0,        // zsub2_then_zsub_hi
   10585             :       0,        // dsub0_dsub1
   10586             :       0,        // dsub0_dsub1_dsub2
   10587             :       0,        // dsub1_dsub2
   10588             :       0,        // dsub1_dsub2_dsub3
   10589             :       0,        // dsub2_dsub3
   10590             :       0,        // dsub_qsub1_then_dsub
   10591             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10592             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10593             :       0,        // qsub0_qsub1
   10594             :       0,        // qsub0_qsub1_qsub2
   10595             :       0,        // qsub1_qsub2
   10596             :       0,        // qsub1_qsub2_qsub3
   10597             :       0,        // qsub2_qsub3
   10598             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10599             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10600             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10601             :       26,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
   10602             :       0,        // dsub_zsub1_then_dsub
   10603             :       0,        // zsub_zsub1_then_zsub
   10604             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10605             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10606             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10607             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10608             :       0,        // zsub0_zsub1
   10609             :       0,        // zsub0_zsub1_zsub2
   10610             :       0,        // zsub1_zsub2
   10611             :       0,        // zsub1_zsub2_zsub3
   10612             :       0,        // zsub2_zsub3
   10613             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10614             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10615             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10616             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10617             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10618             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10619             :     },
   10620             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
   10621             :       0,        // bsub
   10622             :       0,        // dsub
   10623             :       0,        // dsub0
   10624             :       0,        // dsub1
   10625             :       0,        // dsub2
   10626             :       0,        // dsub3
   10627             :       0,        // hsub
   10628             :       0,        // qhisub
   10629             :       0,        // qsub
   10630             :       0,        // qsub0
   10631             :       0,        // qsub1
   10632             :       0,        // qsub2
   10633             :       0,        // qsub3
   10634             :       0,        // ssub
   10635             :       27,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
   10636             :       0,        // sube32
   10637             :       27,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
   10638             :       0,        // subo32
   10639             :       27,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
   10640             :       0,        // zsub
   10641             :       0,        // zsub0
   10642             :       0,        // zsub1
   10643             :       0,        // zsub2
   10644             :       0,        // zsub3
   10645             :       0,        // zsub_hi
   10646             :       0,        // dsub1_then_bsub
   10647             :       0,        // dsub1_then_hsub
   10648             :       0,        // dsub1_then_ssub
   10649             :       0,        // dsub3_then_bsub
   10650             :       0,        // dsub3_then_hsub
   10651             :       0,        // dsub3_then_ssub
   10652             :       0,        // dsub2_then_bsub
   10653             :       0,        // dsub2_then_hsub
   10654             :       0,        // dsub2_then_ssub
   10655             :       0,        // qsub1_then_bsub
   10656             :       0,        // qsub1_then_dsub
   10657             :       0,        // qsub1_then_hsub
   10658             :       0,        // qsub1_then_ssub
   10659             :       0,        // qsub3_then_bsub
   10660             :       0,        // qsub3_then_dsub
   10661             :       0,        // qsub3_then_hsub
   10662             :       0,        // qsub3_then_ssub
   10663             :       0,        // qsub2_then_bsub
   10664             :       0,        // qsub2_then_dsub
   10665             :       0,        // qsub2_then_hsub
   10666             :       0,        // qsub2_then_ssub
   10667             :       27,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
   10668             :       0,        // zsub1_then_bsub
   10669             :       0,        // zsub1_then_dsub
   10670             :       0,        // zsub1_then_hsub
   10671             :       0,        // zsub1_then_ssub
   10672             :       0,        // zsub1_then_zsub
   10673             :       0,        // zsub1_then_zsub_hi
   10674             :       0,        // zsub3_then_bsub
   10675             :       0,        // zsub3_then_dsub
   10676             :       0,        // zsub3_then_hsub
   10677             :       0,        // zsub3_then_ssub
   10678             :       0,        // zsub3_then_zsub
   10679             :       0,        // zsub3_then_zsub_hi
   10680             :       0,        // zsub2_then_bsub
   10681             :       0,        // zsub2_then_dsub
   10682             :       0,        // zsub2_then_hsub
   10683             :       0,        // zsub2_then_ssub
   10684             :       0,        // zsub2_then_zsub
   10685             :       0,        // zsub2_then_zsub_hi
   10686             :       0,        // dsub0_dsub1
   10687             :       0,        // dsub0_dsub1_dsub2
   10688             :       0,        // dsub1_dsub2
   10689             :       0,        // dsub1_dsub2_dsub3
   10690             :       0,        // dsub2_dsub3
   10691             :       0,        // dsub_qsub1_then_dsub
   10692             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10693             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10694             :       0,        // qsub0_qsub1
   10695             :       0,        // qsub0_qsub1_qsub2
   10696             :       0,        // qsub1_qsub2
   10697             :       0,        // qsub1_qsub2_qsub3
   10698             :       0,        // qsub2_qsub3
   10699             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10700             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10701             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10702             :       27,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
   10703             :       0,        // dsub_zsub1_then_dsub
   10704             :       0,        // zsub_zsub1_then_zsub
   10705             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10706             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10707             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10708             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10709             :       0,        // zsub0_zsub1
   10710             :       0,        // zsub0_zsub1_zsub2
   10711             :       0,        // zsub1_zsub2
   10712             :       0,        // zsub1_zsub2_zsub3
   10713             :       0,        // zsub2_zsub3
   10714             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10715             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10716             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10717             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10718             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10719             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10720             :     },
   10721             :     {   // XSeqPairsClass_with_sube64_in_tcGPR64
   10722             :       0,        // bsub
   10723             :       0,        // dsub
   10724             :       0,        // dsub0
   10725             :       0,        // dsub1
   10726             :       0,        // dsub2
   10727             :       0,        // dsub3
   10728             :       0,        // hsub
   10729             :       0,        // qhisub
   10730             :       0,        // qsub
   10731             :       0,        // qsub0
   10732             :       0,        // qsub1
   10733             :       0,        // qsub2
   10734             :       0,        // qsub3
   10735             :       0,        // ssub
   10736             :       28,       // sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
   10737             :       0,        // sube32
   10738             :       28,       // sube64 -> XSeqPairsClass_with_sube64_in_tcGPR64
   10739             :       0,        // subo32
   10740             :       28,       // subo64 -> XSeqPairsClass_with_sube64_in_tcGPR64
   10741             :       0,        // zsub
   10742             :       0,        // zsub0
   10743             :       0,        // zsub1
   10744             :       0,        // zsub2
   10745             :       0,        // zsub3
   10746             :       0,        // zsub_hi
   10747             :       0,        // dsub1_then_bsub
   10748             :       0,        // dsub1_then_hsub
   10749             :       0,        // dsub1_then_ssub
   10750             :       0,        // dsub3_then_bsub
   10751             :       0,        // dsub3_then_hsub
   10752             :       0,        // dsub3_then_ssub
   10753             :       0,        // dsub2_then_bsub
   10754             :       0,        // dsub2_then_hsub
   10755             :       0,        // dsub2_then_ssub
   10756             :       0,        // qsub1_then_bsub
   10757             :       0,        // qsub1_then_dsub
   10758             :       0,        // qsub1_then_hsub
   10759             :       0,        // qsub1_then_ssub
   10760             :       0,        // qsub3_then_bsub
   10761             :       0,        // qsub3_then_dsub
   10762             :       0,        // qsub3_then_hsub
   10763             :       0,        // qsub3_then_ssub
   10764             :       0,        // qsub2_then_bsub
   10765             :       0,        // qsub2_then_dsub
   10766             :       0,        // qsub2_then_hsub
   10767             :       0,        // qsub2_then_ssub
   10768             :       28,       // subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
   10769             :       0,        // zsub1_then_bsub
   10770             :       0,        // zsub1_then_dsub
   10771             :       0,        // zsub1_then_hsub
   10772             :       0,        // zsub1_then_ssub
   10773             :       0,        // zsub1_then_zsub
   10774             :       0,        // zsub1_then_zsub_hi
   10775             :       0,        // zsub3_then_bsub
   10776             :       0,        // zsub3_then_dsub
   10777             :       0,        // zsub3_then_hsub
   10778             :       0,        // zsub3_then_ssub
   10779             :       0,        // zsub3_then_zsub
   10780             :       0,        // zsub3_then_zsub_hi
   10781             :       0,        // zsub2_then_bsub
   10782             :       0,        // zsub2_then_dsub
   10783             :       0,        // zsub2_then_hsub
   10784             :       0,        // zsub2_then_ssub
   10785             :       0,        // zsub2_then_zsub
   10786             :       0,        // zsub2_then_zsub_hi
   10787             :       0,        // dsub0_dsub1
   10788             :       0,        // dsub0_dsub1_dsub2
   10789             :       0,        // dsub1_dsub2
   10790             :       0,        // dsub1_dsub2_dsub3
   10791             :       0,        // dsub2_dsub3
   10792             :       0,        // dsub_qsub1_then_dsub
   10793             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10794             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10795             :       0,        // qsub0_qsub1
   10796             :       0,        // qsub0_qsub1_qsub2
   10797             :       0,        // qsub1_qsub2
   10798             :       0,        // qsub1_qsub2_qsub3
   10799             :       0,        // qsub2_qsub3
   10800             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10801             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10802             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10803             :       28,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
   10804             :       0,        // dsub_zsub1_then_dsub
   10805             :       0,        // zsub_zsub1_then_zsub
   10806             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10807             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10808             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10809             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10810             :       0,        // zsub0_zsub1
   10811             :       0,        // zsub0_zsub1_zsub2
   10812             :       0,        // zsub1_zsub2
   10813             :       0,        // zsub1_zsub2_zsub3
   10814             :       0,        // zsub2_zsub3
   10815             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10816             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10817             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10818             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10819             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10820             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10821             :     },
   10822             :     {   // XSeqPairsClass_with_subo64_in_tcGPR64
   10823             :       0,        // bsub
   10824             :       0,        // dsub
   10825             :       0,        // dsub0
   10826             :       0,        // dsub1
   10827             :       0,        // dsub2
   10828             :       0,        // dsub3
   10829             :       0,        // hsub
   10830             :       0,        // qhisub
   10831             :       0,        // qsub
   10832             :       0,        // qsub0
   10833             :       0,        // qsub1
   10834             :       0,        // qsub2
   10835             :       0,        // qsub3
   10836             :       0,        // ssub
   10837             :       29,       // sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
   10838             :       0,        // sube32
   10839             :       29,       // sube64 -> XSeqPairsClass_with_subo64_in_tcGPR64
   10840             :       0,        // subo32
   10841             :       29,       // subo64 -> XSeqPairsClass_with_subo64_in_tcGPR64
   10842             :       0,        // zsub
   10843             :       0,        // zsub0
   10844             :       0,        // zsub1
   10845             :       0,        // zsub2
   10846             :       0,        // zsub3
   10847             :       0,        // zsub_hi
   10848             :       0,        // dsub1_then_bsub
   10849             :       0,        // dsub1_then_hsub
   10850             :       0,        // dsub1_then_ssub
   10851             :       0,        // dsub3_then_bsub
   10852             :       0,        // dsub3_then_hsub
   10853             :       0,        // dsub3_then_ssub
   10854             :       0,        // dsub2_then_bsub
   10855             :       0,        // dsub2_then_hsub
   10856             :       0,        // dsub2_then_ssub
   10857             :       0,        // qsub1_then_bsub
   10858             :       0,        // qsub1_then_dsub
   10859             :       0,        // qsub1_then_hsub
   10860             :       0,        // qsub1_then_ssub
   10861             :       0,        // qsub3_then_bsub
   10862             :       0,        // qsub3_then_dsub
   10863             :       0,        // qsub3_then_hsub
   10864             :       0,        // qsub3_then_ssub
   10865             :       0,        // qsub2_then_bsub
   10866             :       0,        // qsub2_then_dsub
   10867             :       0,        // qsub2_then_hsub
   10868             :       0,        // qsub2_then_ssub
   10869             :       29,       // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
   10870             :       0,        // zsub1_then_bsub
   10871             :       0,        // zsub1_then_dsub
   10872             :       0,        // zsub1_then_hsub
   10873             :       0,        // zsub1_then_ssub
   10874             :       0,        // zsub1_then_zsub
   10875             :       0,        // zsub1_then_zsub_hi
   10876             :       0,        // zsub3_then_bsub
   10877             :       0,        // zsub3_then_dsub
   10878             :       0,        // zsub3_then_hsub
   10879             :       0,        // zsub3_then_ssub
   10880             :       0,        // zsub3_then_zsub
   10881             :       0,        // zsub3_then_zsub_hi
   10882             :       0,        // zsub2_then_bsub
   10883             :       0,        // zsub2_then_dsub
   10884             :       0,        // zsub2_then_hsub
   10885             :       0,        // zsub2_then_ssub
   10886             :       0,        // zsub2_then_zsub
   10887             :       0,        // zsub2_then_zsub_hi
   10888             :       0,        // dsub0_dsub1
   10889             :       0,        // dsub0_dsub1_dsub2
   10890             :       0,        // dsub1_dsub2
   10891             :       0,        // dsub1_dsub2_dsub3
   10892             :       0,        // dsub2_dsub3
   10893             :       0,        // dsub_qsub1_then_dsub
   10894             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10895             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10896             :       0,        // qsub0_qsub1
   10897             :       0,        // qsub0_qsub1_qsub2
   10898             :       0,        // qsub1_qsub2
   10899             :       0,        // qsub1_qsub2_qsub3
   10900             :       0,        // qsub2_qsub3
   10901             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10902             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10903             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10904             :       29,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
   10905             :       0,        // dsub_zsub1_then_dsub
   10906             :       0,        // zsub_zsub1_then_zsub
   10907             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10908             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10909             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10910             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10911             :       0,        // zsub0_zsub1
   10912             :       0,        // zsub0_zsub1_zsub2
   10913             :       0,        // zsub1_zsub2
   10914             :       0,        // zsub1_zsub2_zsub3
   10915             :       0,        // zsub2_zsub3
   10916             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10917             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10918             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10919             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10920             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10921             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10922             :     },
   10923             :     {   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
   10924             :       0,        // bsub
   10925             :       0,        // dsub
   10926             :       0,        // dsub0
   10927             :       0,        // dsub1
   10928             :       0,        // dsub2
   10929             :       0,        // dsub3
   10930             :       0,        // hsub
   10931             :       0,        // qhisub
   10932             :       0,        // qsub
   10933             :       0,        // qsub0
   10934             :       0,        // qsub1
   10935             :       0,        // qsub2
   10936             :       0,        // qsub3
   10937             :       0,        // ssub
   10938             :       30,       // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
   10939             :       0,        // sube32
   10940             :       30,       // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
   10941             :       0,        // subo32
   10942             :       30,       // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
   10943             :       0,        // zsub
   10944             :       0,        // zsub0
   10945             :       0,        // zsub1
   10946             :       0,        // zsub2
   10947             :       0,        // zsub3
   10948             :       0,        // zsub_hi
   10949             :       0,        // dsub1_then_bsub
   10950             :       0,        // dsub1_then_hsub
   10951             :       0,        // dsub1_then_ssub
   10952             :       0,        // dsub3_then_bsub
   10953             :       0,        // dsub3_then_hsub
   10954             :       0,        // dsub3_then_ssub
   10955             :       0,        // dsub2_then_bsub
   10956             :       0,        // dsub2_then_hsub
   10957             :       0,        // dsub2_then_ssub
   10958             :       0,        // qsub1_then_bsub
   10959             :       0,        // qsub1_then_dsub
   10960             :       0,        // qsub1_then_hsub
   10961             :       0,        // qsub1_then_ssub
   10962             :       0,        // qsub3_then_bsub
   10963             :       0,        // qsub3_then_dsub
   10964             :       0,        // qsub3_then_hsub
   10965             :       0,        // qsub3_then_ssub
   10966             :       0,        // qsub2_then_bsub
   10967             :       0,        // qsub2_then_dsub
   10968             :       0,        // qsub2_then_hsub
   10969             :       0,        // qsub2_then_ssub
   10970             :       30,       // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
   10971             :       0,        // zsub1_then_bsub
   10972             :       0,        // zsub1_then_dsub
   10973             :       0,        // zsub1_then_hsub
   10974             :       0,        // zsub1_then_ssub
   10975             :       0,        // zsub1_then_zsub
   10976             :       0,        // zsub1_then_zsub_hi
   10977             :       0,        // zsub3_then_bsub
   10978             :       0,        // zsub3_then_dsub
   10979             :       0,        // zsub3_then_hsub
   10980             :       0,        // zsub3_then_ssub
   10981             :       0,        // zsub3_then_zsub
   10982             :       0,        // zsub3_then_zsub_hi
   10983             :       0,        // zsub2_then_bsub
   10984             :       0,        // zsub2_then_dsub
   10985             :       0,        // zsub2_then_hsub
   10986             :       0,        // zsub2_then_ssub
   10987             :       0,        // zsub2_then_zsub
   10988             :       0,        // zsub2_then_zsub_hi
   10989             :       0,        // dsub0_dsub1
   10990             :       0,        // dsub0_dsub1_dsub2
   10991             :       0,        // dsub1_dsub2
   10992             :       0,        // dsub1_dsub2_dsub3
   10993             :       0,        // dsub2_dsub3
   10994             :       0,        // dsub_qsub1_then_dsub
   10995             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10996             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10997             :       0,        // qsub0_qsub1
   10998             :       0,        // qsub0_qsub1_qsub2
   10999             :       0,        // qsub1_qsub2
   11000             :       0,        // qsub1_qsub2_qsub3
   11001             :       0,        // qsub2_qsub3
   11002             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   11003             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   11004             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   11005             :       30,       // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
   11006             :       0,        // dsub_zsub1_then_dsub
   11007             :       0,        // zsub_zsub1_then_zsub
   11008             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   11009             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   11010             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   11011             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   11012             :       0,        // zsub0_zsub1
   11013             :       0,        // zsub0_zsub1_zsub2
   11014             :       0,        // zsub1_zsub2
   11015             :       0,        // zsub1_zsub2_zsub3
   11016             :       0,        // zsub2_zsub3
   11017             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   11018             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   11019             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   11020             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   11021             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   11022             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   11023             :     },
   11024             :     {   // FPR128
   11025             :       31,       // bsub -> FPR128
   11026             :       31,       // dsub -> FPR128
   11027             :       0,        // dsub0
   11028             :       0,        // dsub1
   11029             :       0,        // dsub2
   11030             :       0,        // dsub3
   11031             :       31,       // hsub -> FPR128
   11032             :       0,        // qhisub
   11033             :       0,        // qsub
   11034             :       0,        // qsub0
   11035             :       0,        // qsub1
   11036             :       0,        // qsub2
   11037             :       0,        // qsub3
   11038             :       31,       // ssub -> FPR128
   11039             :       0,        // sub_32
   11040             :       0,        // sube32
   11041             :       0,        // sube64
   11042             :       0,        // subo32
   11043             :       0,        // subo64
   11044             :       0,        // zsub
   11045             :       0,        // zsub0
   11046             :       0,        // zsub1
   11047             :       0,        // zsub2
   11048             :       0,        // zsub3
   11049             :       0,        // zsub_hi
   11050             :       0,        // dsub1_then_bsub
   11051             :       0,        // dsub1_then_hsub
   11052             :       0,        // dsub1_then_ssub
   11053             :       0,        // dsub3_then_bsub
   11054             :       0,        // dsub3_then_hsub
   11055             :       0,        // dsub3_then_ssub
   11056             :       0,        // dsub2_then_bsub
   11057             :       0,        // dsub2_then_hsub
   11058             :       0,        // dsub2_then_ssub
   11059             :       0,        // qsub1_then_bsub
   11060             :       0,        // qsub1_then_dsub
   11061             :       0,        // qsub1_then_hsub
   11062             :       0,        // qsub1_then_ssub
   11063             :       0,        // qsub3_then_bsub
   11064             :       0,        // qsub3_then_dsub
   11065             :       0,        // qsub3_then_hsub
   11066             :       0,        // qsub3_then_ssub
   11067             :       0,        // qsub2_then_bsub
   11068             :       0,        // qsub2_then_dsub
   11069             :       0,        // qsub2_then_hsub
   11070             :       0,        // qsub2_then_ssub
   11071             :       0,        // subo64_then_sub_32
   11072             :       0,        // zsub1_then_bsub
   11073             :       0,        // zsub1_then_dsub
   11074             :       0,        // zsub1_then_hsub
   11075             :       0,        // zsub1_then_ssub
   11076             :       0,        // zsub1_then_zsub
   11077             :       0,        // zsub1_then_zsub_hi
   11078             :       0,        // zsub3_then_bsub
   11079             :       0,        // zsub3_then_dsub
   11080             :       0,        // zsub3_then_hsub
   11081             :       0,        // zsub3_then_ssub
   11082             :       0,        // zsub3_then_zsub
   11083             :       0,        // zsub3_then_zsub_hi
   11084             :       0,        // zsub2_then_bsub
   11085             :       0,        // zsub2_then_dsub
   11086             :       0,        // zsub2_then_hsub
   11087             :       0,        // zsub2_then_ssub
   11088             :       0,        // zsub2_then_zsub
   11089             :       0,        // zsub2_then_zsub_hi
   11090             :       0,        // dsub0_dsub1
   11091             :       0,        // dsub0_dsub1_dsub2
   11092             :       0,        // dsub1_dsub2
   11093             :       0,        // dsub1_dsub2_dsub3
   11094             :       0,        // dsub2_dsub3
   11095             :       0,        // dsub_qsub1_then_dsub
   11096             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   11097             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   11098             :       0,        // qsub0_qsub1
   11099             :       0,        // qsub0_qsub1_qsub2
   11100             :       0,        // qsub1_qsub2
   11101             :       0,        // qsub1_qsub2_qsub3
   11102             :       0,        // qsub2_qsub3
   11103             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   11104             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   11105             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   11106             :       0,        // sub_32_subo64_then_sub_32
   11107             :       0,        // dsub_zsub1_then_dsub
   11108             :       0,        // zsub_zsub1_then_zsub
   11109             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   11110             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   11111             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   11112             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   11113             :       0,        // zsub0_zsub1
   11114             :       0,        // zsub0_zsub1_zsub2
   11115             :       0,        // zsub1_zsub2
   11116             :       0,        // zsub1_zsub2_zsub3
   11117             :       0,        // zsub2_zsub3
   11118             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   11119             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   11120             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   11121             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   11122             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   11123             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   11124             :     },
   11125             :     {   // ZPR
   11126             :       32,       // bsub -> ZPR
   11127             :       32,       // dsub -> ZPR
   11128             :       0,        // dsub0
   11129             :       0,        // dsub1
   11130             :       0,        // dsub2
   11131             :       0,        // dsub3
   11132             :       32,       // hsub -> ZPR
   11133             :       0,        // qhisub
   11134             :       0,        // qsub
   11135             :       0,        // qsub0
   11136             :       0,        // qsub1
   11137             :       0,        // qsub2
   11138             :       0,        // qsub3
   11139             :       32,       // ssub -> ZPR
   11140             :       0,        // sub_32
   11141             :       0,        // sube32
   11142             :       0,        // sube64
   11143             :       0,        // subo32
   11144             :       0,        // subo64
   11145             :       32,       // zsub -> ZPR
   11146             :       0,        // zsub0
   11147             :       0,        // zsub1
   11148             :       0,        // zsub2
   11149             :       0,        // zsub3
   11150             :       32,       // zsub_hi -> ZPR
   11151             :       0,        // dsub1_then_bsub
   11152             :       0,        // dsub1_then_hsub
   11153             :       0,        // dsub1_then_ssub
   11154             :       0,        // dsub3_then_bsub
   11155             :       0,        // dsub3_then_hsub
   11156             :       0,        // dsub3_then_ssub
   11157             :       0,        // dsub2_then_bsub
   11158             :       0,        // dsub2_then_hsub
   11159             :       0,        // dsub2_then_ssub
   11160             :       0,        // qsub1_then_bsub
   11161             :       0,        // qsub1_then_dsub
   11162             :       0,        // qsub1_then_hsub
   11163             :       0,        // qsub1_then_ssub
   11164             :       0,        // qsub3_then_bsub
   11165             :       0,        // qsub3_then_dsub
   11166             :       0,        // qsub3_then_hsub
   11167             :       0,        // qsub3_then_ssub
   11168             :       0,        // qsub2_then_bsub
   11169             :       0,        // qsub2_then_dsub
   11170             :       0,        // qsub2_then_hsub
   11171             :       0,        // qsub2_then_ssub
   11172             :       0,        // subo64_then_sub_32
   11173             :       0,        // zsub1_then_bsub
   11174             :       0,        // zsub1_then_dsub
   11175             :       0,        // zsub1_then_hsub
   11176             :       0,        // zsub1_then_ssub
   11177             :       0,        // zsub1_then_zsub
   11178             :       0,        // zsub1_then_zsub_hi
   11179             :       0,        // zsub3_then_bsub
   11180             :       0,        // zsub3_then_dsub
   11181             :       0,        // zsub3_then_hsub
   11182             :       0,        // zsub3_then_ssub
   11183             :       0,        // zsub3_then_zsub
   11184             :       0,        // zsub3_then_zsub_hi
   11185             :       0,        // zsub2_then_bsub
   11186             :       0,        // zsub2_then_dsub
   11187             :       0,        // zsub2_then_hsub
   11188             :       0,        // zsub2_then_ssub
   11189             :       0,        // zsub2_then_zsub
   11190             :       0,        // zsub2_then_zsub_hi
   11191             :       0,        // dsub0_dsub1
   11192             :       0,        // dsub0_dsub1_dsub2
   11193             :       0,        // dsub1_dsub2
   11194             :       0,        // dsub1_dsub2_dsub3
   11195             :       0,        // dsub2_dsub3
   11196             :       0,        // dsub_qsub1_then_dsub
   11197             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   11198             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   11199             :       0,        // qsub0_qsub1
   11200             :       0,        // qsub0_qsub1_qsub2
   11201             :       0,        // qsub1_qsub2
   11202             :       0,        // qsub1_qsub2_qsub3
   11203             :       0,        // qsub2_qsub3
   11204             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   11205             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   11206             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   11207             :       0,        // sub_32_subo64_then_sub_32
   11208             :       0,        // dsub_zsub1_then_dsub
   11209             :       0,        // zsub_zsub1_then_zsub
   11210             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   11211             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   11212             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   11213             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   11214             :       0,        // zsub0_zsub1
   11215