LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AArch64 - AArch64GenRegisterInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 56 80 70.0 %
Date: 2018-07-13 00:08:38 Functions: 18 21 85.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Register Enum Values                                                *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_REGINFO_ENUM
      11             : #undef GET_REGINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : 
      15             : class MCRegisterClass;
      16             : extern const MCRegisterClass AArch64MCRegisterClasses[];
      17             : 
      18             : namespace AArch64 {
      19             : enum {
      20             :   NoRegister,
      21             :   FFR = 1,
      22             :   FP = 2,
      23             :   LR = 3,
      24             :   NZCV = 4,
      25             :   SP = 5,
      26             :   WSP = 6,
      27             :   WZR = 7,
      28             :   XZR = 8,
      29             :   B0 = 9,
      30             :   B1 = 10,
      31             :   B2 = 11,
      32             :   B3 = 12,
      33             :   B4 = 13,
      34             :   B5 = 14,
      35             :   B6 = 15,
      36             :   B7 = 16,
      37             :   B8 = 17,
      38             :   B9 = 18,
      39             :   B10 = 19,
      40             :   B11 = 20,
      41             :   B12 = 21,
      42             :   B13 = 22,
      43             :   B14 = 23,
      44             :   B15 = 24,
      45             :   B16 = 25,
      46             :   B17 = 26,
      47             :   B18 = 27,
      48             :   B19 = 28,
      49             :   B20 = 29,
      50             :   B21 = 30,
      51             :   B22 = 31,
      52             :   B23 = 32,
      53             :   B24 = 33,
      54             :   B25 = 34,
      55             :   B26 = 35,
      56             :   B27 = 36,
      57             :   B28 = 37,
      58             :   B29 = 38,
      59             :   B30 = 39,
      60             :   B31 = 40,
      61             :   D0 = 41,
      62             :   D1 = 42,
      63             :   D2 = 43,
      64             :   D3 = 44,
      65             :   D4 = 45,
      66             :   D5 = 46,
      67             :   D6 = 47,
      68             :   D7 = 48,
      69             :   D8 = 49,
      70             :   D9 = 50,
      71             :   D10 = 51,
      72             :   D11 = 52,
      73             :   D12 = 53,
      74             :   D13 = 54,
      75             :   D14 = 55,
      76             :   D15 = 56,
      77             :   D16 = 57,
      78             :   D17 = 58,
      79             :   D18 = 59,
      80             :   D19 = 60,
      81             :   D20 = 61,
      82             :   D21 = 62,
      83             :   D22 = 63,
      84             :   D23 = 64,
      85             :   D24 = 65,
      86             :   D25 = 66,
      87             :   D26 = 67,
      88             :   D27 = 68,
      89             :   D28 = 69,
      90             :   D29 = 70,
      91             :   D30 = 71,
      92             :   D31 = 72,
      93             :   H0 = 73,
      94             :   H1 = 74,
      95             :   H2 = 75,
      96             :   H3 = 76,
      97             :   H4 = 77,
      98             :   H5 = 78,
      99             :   H6 = 79,
     100             :   H7 = 80,
     101             :   H8 = 81,
     102             :   H9 = 82,
     103             :   H10 = 83,
     104             :   H11 = 84,
     105             :   H12 = 85,
     106             :   H13 = 86,
     107             :   H14 = 87,
     108             :   H15 = 88,
     109             :   H16 = 89,
     110             :   H17 = 90,
     111             :   H18 = 91,
     112             :   H19 = 92,
     113             :   H20 = 93,
     114             :   H21 = 94,
     115             :   H22 = 95,
     116             :   H23 = 96,
     117             :   H24 = 97,
     118             :   H25 = 98,
     119             :   H26 = 99,
     120             :   H27 = 100,
     121             :   H28 = 101,
     122             :   H29 = 102,
     123             :   H30 = 103,
     124             :   H31 = 104,
     125             :   P0 = 105,
     126             :   P1 = 106,
     127             :   P2 = 107,
     128             :   P3 = 108,
     129             :   P4 = 109,
     130             :   P5 = 110,
     131             :   P6 = 111,
     132             :   P7 = 112,
     133             :   P8 = 113,
     134             :   P9 = 114,
     135             :   P10 = 115,
     136             :   P11 = 116,
     137             :   P12 = 117,
     138             :   P13 = 118,
     139             :   P14 = 119,
     140             :   P15 = 120,
     141             :   Q0 = 121,
     142             :   Q1 = 122,
     143             :   Q2 = 123,
     144             :   Q3 = 124,
     145             :   Q4 = 125,
     146             :   Q5 = 126,
     147             :   Q6 = 127,
     148             :   Q7 = 128,
     149             :   Q8 = 129,
     150             :   Q9 = 130,
     151             :   Q10 = 131,
     152             :   Q11 = 132,
     153             :   Q12 = 133,
     154             :   Q13 = 134,
     155             :   Q14 = 135,
     156             :   Q15 = 136,
     157             :   Q16 = 137,
     158             :   Q17 = 138,
     159             :   Q18 = 139,
     160             :   Q19 = 140,
     161             :   Q20 = 141,
     162             :   Q21 = 142,
     163             :   Q22 = 143,
     164             :   Q23 = 144,
     165             :   Q24 = 145,
     166             :   Q25 = 146,
     167             :   Q26 = 147,
     168             :   Q27 = 148,
     169             :   Q28 = 149,
     170             :   Q29 = 150,
     171             :   Q30 = 151,
     172             :   Q31 = 152,
     173             :   S0 = 153,
     174             :   S1 = 154,
     175             :   S2 = 155,
     176             :   S3 = 156,
     177             :   S4 = 157,
     178             :   S5 = 158,
     179             :   S6 = 159,
     180             :   S7 = 160,
     181             :   S8 = 161,
     182             :   S9 = 162,
     183             :   S10 = 163,
     184             :   S11 = 164,
     185             :   S12 = 165,
     186             :   S13 = 166,
     187             :   S14 = 167,
     188             :   S15 = 168,
     189             :   S16 = 169,
     190             :   S17 = 170,
     191             :   S18 = 171,
     192             :   S19 = 172,
     193             :   S20 = 173,
     194             :   S21 = 174,
     195             :   S22 = 175,
     196             :   S23 = 176,
     197             :   S24 = 177,
     198             :   S25 = 178,
     199             :   S26 = 179,
     200             :   S27 = 180,
     201             :   S28 = 181,
     202             :   S29 = 182,
     203             :   S30 = 183,
     204             :   S31 = 184,
     205             :   W0 = 185,
     206             :   W1 = 186,
     207             :   W2 = 187,
     208             :   W3 = 188,
     209             :   W4 = 189,
     210             :   W5 = 190,
     211             :   W6 = 191,
     212             :   W7 = 192,
     213             :   W8 = 193,
     214             :   W9 = 194,
     215             :   W10 = 195,
     216             :   W11 = 196,
     217             :   W12 = 197,
     218             :   W13 = 198,
     219             :   W14 = 199,
     220             :   W15 = 200,
     221             :   W16 = 201,
     222             :   W17 = 202,
     223             :   W18 = 203,
     224             :   W19 = 204,
     225             :   W20 = 205,
     226             :   W21 = 206,
     227             :   W22 = 207,
     228             :   W23 = 208,
     229             :   W24 = 209,
     230             :   W25 = 210,
     231             :   W26 = 211,
     232             :   W27 = 212,
     233             :   W28 = 213,
     234             :   W29 = 214,
     235             :   W30 = 215,
     236             :   X0 = 216,
     237             :   X1 = 217,
     238             :   X2 = 218,
     239             :   X3 = 219,
     240             :   X4 = 220,
     241             :   X5 = 221,
     242             :   X6 = 222,
     243             :   X7 = 223,
     244             :   X8 = 224,
     245             :   X9 = 225,
     246             :   X10 = 226,
     247             :   X11 = 227,
     248             :   X12 = 228,
     249             :   X13 = 229,
     250             :   X14 = 230,
     251             :   X15 = 231,
     252             :   X16 = 232,
     253             :   X17 = 233,
     254             :   X18 = 234,
     255             :   X19 = 235,
     256             :   X20 = 236,
     257             :   X21 = 237,
     258             :   X22 = 238,
     259             :   X23 = 239,
     260             :   X24 = 240,
     261             :   X25 = 241,
     262             :   X26 = 242,
     263             :   X27 = 243,
     264             :   X28 = 244,
     265             :   Z0 = 245,
     266             :   Z1 = 246,
     267             :   Z2 = 247,
     268             :   Z3 = 248,
     269             :   Z4 = 249,
     270             :   Z5 = 250,
     271             :   Z6 = 251,
     272             :   Z7 = 252,
     273             :   Z8 = 253,
     274             :   Z9 = 254,
     275             :   Z10 = 255,
     276             :   Z11 = 256,
     277             :   Z12 = 257,
     278             :   Z13 = 258,
     279             :   Z14 = 259,
     280             :   Z15 = 260,
     281             :   Z16 = 261,
     282             :   Z17 = 262,
     283             :   Z18 = 263,
     284             :   Z19 = 264,
     285             :   Z20 = 265,
     286             :   Z21 = 266,
     287             :   Z22 = 267,
     288             :   Z23 = 268,
     289             :   Z24 = 269,
     290             :   Z25 = 270,
     291             :   Z26 = 271,
     292             :   Z27 = 272,
     293             :   Z28 = 273,
     294             :   Z29 = 274,
     295             :   Z30 = 275,
     296             :   Z31 = 276,
     297             :   Z0_HI = 277,
     298             :   Z1_HI = 278,
     299             :   Z2_HI = 279,
     300             :   Z3_HI = 280,
     301             :   Z4_HI = 281,
     302             :   Z5_HI = 282,
     303             :   Z6_HI = 283,
     304             :   Z7_HI = 284,
     305             :   Z8_HI = 285,
     306             :   Z9_HI = 286,
     307             :   Z10_HI = 287,
     308             :   Z11_HI = 288,
     309             :   Z12_HI = 289,
     310             :   Z13_HI = 290,
     311             :   Z14_HI = 291,
     312             :   Z15_HI = 292,
     313             :   Z16_HI = 293,
     314             :   Z17_HI = 294,
     315             :   Z18_HI = 295,
     316             :   Z19_HI = 296,
     317             :   Z20_HI = 297,
     318             :   Z21_HI = 298,
     319             :   Z22_HI = 299,
     320             :   Z23_HI = 300,
     321             :   Z24_HI = 301,
     322             :   Z25_HI = 302,
     323             :   Z26_HI = 303,
     324             :   Z27_HI = 304,
     325             :   Z28_HI = 305,
     326             :   Z29_HI = 306,
     327             :   Z30_HI = 307,
     328             :   Z31_HI = 308,
     329             :   D0_D1 = 309,
     330             :   D1_D2 = 310,
     331             :   D2_D3 = 311,
     332             :   D3_D4 = 312,
     333             :   D4_D5 = 313,
     334             :   D5_D6 = 314,
     335             :   D6_D7 = 315,
     336             :   D7_D8 = 316,
     337             :   D8_D9 = 317,
     338             :   D9_D10 = 318,
     339             :   D10_D11 = 319,
     340             :   D11_D12 = 320,
     341             :   D12_D13 = 321,
     342             :   D13_D14 = 322,
     343             :   D14_D15 = 323,
     344             :   D15_D16 = 324,
     345             :   D16_D17 = 325,
     346             :   D17_D18 = 326,
     347             :   D18_D19 = 327,
     348             :   D19_D20 = 328,
     349             :   D20_D21 = 329,
     350             :   D21_D22 = 330,
     351             :   D22_D23 = 331,
     352             :   D23_D24 = 332,
     353             :   D24_D25 = 333,
     354             :   D25_D26 = 334,
     355             :   D26_D27 = 335,
     356             :   D27_D28 = 336,
     357             :   D28_D29 = 337,
     358             :   D29_D30 = 338,
     359             :   D30_D31 = 339,
     360             :   D31_D0 = 340,
     361             :   D0_D1_D2_D3 = 341,
     362             :   D1_D2_D3_D4 = 342,
     363             :   D2_D3_D4_D5 = 343,
     364             :   D3_D4_D5_D6 = 344,
     365             :   D4_D5_D6_D7 = 345,
     366             :   D5_D6_D7_D8 = 346,
     367             :   D6_D7_D8_D9 = 347,
     368             :   D7_D8_D9_D10 = 348,
     369             :   D8_D9_D10_D11 = 349,
     370             :   D9_D10_D11_D12 = 350,
     371             :   D10_D11_D12_D13 = 351,
     372             :   D11_D12_D13_D14 = 352,
     373             :   D12_D13_D14_D15 = 353,
     374             :   D13_D14_D15_D16 = 354,
     375             :   D14_D15_D16_D17 = 355,
     376             :   D15_D16_D17_D18 = 356,
     377             :   D16_D17_D18_D19 = 357,
     378             :   D17_D18_D19_D20 = 358,
     379             :   D18_D19_D20_D21 = 359,
     380             :   D19_D20_D21_D22 = 360,
     381             :   D20_D21_D22_D23 = 361,
     382             :   D21_D22_D23_D24 = 362,
     383             :   D22_D23_D24_D25 = 363,
     384             :   D23_D24_D25_D26 = 364,
     385             :   D24_D25_D26_D27 = 365,
     386             :   D25_D26_D27_D28 = 366,
     387             :   D26_D27_D28_D29 = 367,
     388             :   D27_D28_D29_D30 = 368,
     389             :   D28_D29_D30_D31 = 369,
     390             :   D29_D30_D31_D0 = 370,
     391             :   D30_D31_D0_D1 = 371,
     392             :   D31_D0_D1_D2 = 372,
     393             :   D0_D1_D2 = 373,
     394             :   D1_D2_D3 = 374,
     395             :   D2_D3_D4 = 375,
     396             :   D3_D4_D5 = 376,
     397             :   D4_D5_D6 = 377,
     398             :   D5_D6_D7 = 378,
     399             :   D6_D7_D8 = 379,
     400             :   D7_D8_D9 = 380,
     401             :   D8_D9_D10 = 381,
     402             :   D9_D10_D11 = 382,
     403             :   D10_D11_D12 = 383,
     404             :   D11_D12_D13 = 384,
     405             :   D12_D13_D14 = 385,
     406             :   D13_D14_D15 = 386,
     407             :   D14_D15_D16 = 387,
     408             :   D15_D16_D17 = 388,
     409             :   D16_D17_D18 = 389,
     410             :   D17_D18_D19 = 390,
     411             :   D18_D19_D20 = 391,
     412             :   D19_D20_D21 = 392,
     413             :   D20_D21_D22 = 393,
     414             :   D21_D22_D23 = 394,
     415             :   D22_D23_D24 = 395,
     416             :   D23_D24_D25 = 396,
     417             :   D24_D25_D26 = 397,
     418             :   D25_D26_D27 = 398,
     419             :   D26_D27_D28 = 399,
     420             :   D27_D28_D29 = 400,
     421             :   D28_D29_D30 = 401,
     422             :   D29_D30_D31 = 402,
     423             :   D30_D31_D0 = 403,
     424             :   D31_D0_D1 = 404,
     425             :   Q0_Q1 = 405,
     426             :   Q1_Q2 = 406,
     427             :   Q2_Q3 = 407,
     428             :   Q3_Q4 = 408,
     429             :   Q4_Q5 = 409,
     430             :   Q5_Q6 = 410,
     431             :   Q6_Q7 = 411,
     432             :   Q7_Q8 = 412,
     433             :   Q8_Q9 = 413,
     434             :   Q9_Q10 = 414,
     435             :   Q10_Q11 = 415,
     436             :   Q11_Q12 = 416,
     437             :   Q12_Q13 = 417,
     438             :   Q13_Q14 = 418,
     439             :   Q14_Q15 = 419,
     440             :   Q15_Q16 = 420,
     441             :   Q16_Q17 = 421,
     442             :   Q17_Q18 = 422,
     443             :   Q18_Q19 = 423,
     444             :   Q19_Q20 = 424,
     445             :   Q20_Q21 = 425,
     446             :   Q21_Q22 = 426,
     447             :   Q22_Q23 = 427,
     448             :   Q23_Q24 = 428,
     449             :   Q24_Q25 = 429,
     450             :   Q25_Q26 = 430,
     451             :   Q26_Q27 = 431,
     452             :   Q27_Q28 = 432,
     453             :   Q28_Q29 = 433,
     454             :   Q29_Q30 = 434,
     455             :   Q30_Q31 = 435,
     456             :   Q31_Q0 = 436,
     457             :   Q0_Q1_Q2_Q3 = 437,
     458             :   Q1_Q2_Q3_Q4 = 438,
     459             :   Q2_Q3_Q4_Q5 = 439,
     460             :   Q3_Q4_Q5_Q6 = 440,
     461             :   Q4_Q5_Q6_Q7 = 441,
     462             :   Q5_Q6_Q7_Q8 = 442,
     463             :   Q6_Q7_Q8_Q9 = 443,
     464             :   Q7_Q8_Q9_Q10 = 444,
     465             :   Q8_Q9_Q10_Q11 = 445,
     466             :   Q9_Q10_Q11_Q12 = 446,
     467             :   Q10_Q11_Q12_Q13 = 447,
     468             :   Q11_Q12_Q13_Q14 = 448,
     469             :   Q12_Q13_Q14_Q15 = 449,
     470             :   Q13_Q14_Q15_Q16 = 450,
     471             :   Q14_Q15_Q16_Q17 = 451,
     472             :   Q15_Q16_Q17_Q18 = 452,
     473             :   Q16_Q17_Q18_Q19 = 453,
     474             :   Q17_Q18_Q19_Q20 = 454,
     475             :   Q18_Q19_Q20_Q21 = 455,
     476             :   Q19_Q20_Q21_Q22 = 456,
     477             :   Q20_Q21_Q22_Q23 = 457,
     478             :   Q21_Q22_Q23_Q24 = 458,
     479             :   Q22_Q23_Q24_Q25 = 459,
     480             :   Q23_Q24_Q25_Q26 = 460,
     481             :   Q24_Q25_Q26_Q27 = 461,
     482             :   Q25_Q26_Q27_Q28 = 462,
     483             :   Q26_Q27_Q28_Q29 = 463,
     484             :   Q27_Q28_Q29_Q30 = 464,
     485             :   Q28_Q29_Q30_Q31 = 465,
     486             :   Q29_Q30_Q31_Q0 = 466,
     487             :   Q30_Q31_Q0_Q1 = 467,
     488             :   Q31_Q0_Q1_Q2 = 468,
     489             :   Q0_Q1_Q2 = 469,
     490             :   Q1_Q2_Q3 = 470,
     491             :   Q2_Q3_Q4 = 471,
     492             :   Q3_Q4_Q5 = 472,
     493             :   Q4_Q5_Q6 = 473,
     494             :   Q5_Q6_Q7 = 474,
     495             :   Q6_Q7_Q8 = 475,
     496             :   Q7_Q8_Q9 = 476,
     497             :   Q8_Q9_Q10 = 477,
     498             :   Q9_Q10_Q11 = 478,
     499             :   Q10_Q11_Q12 = 479,
     500             :   Q11_Q12_Q13 = 480,
     501             :   Q12_Q13_Q14 = 481,
     502             :   Q13_Q14_Q15 = 482,
     503             :   Q14_Q15_Q16 = 483,
     504             :   Q15_Q16_Q17 = 484,
     505             :   Q16_Q17_Q18 = 485,
     506             :   Q17_Q18_Q19 = 486,
     507             :   Q18_Q19_Q20 = 487,
     508             :   Q19_Q20_Q21 = 488,
     509             :   Q20_Q21_Q22 = 489,
     510             :   Q21_Q22_Q23 = 490,
     511             :   Q22_Q23_Q24 = 491,
     512             :   Q23_Q24_Q25 = 492,
     513             :   Q24_Q25_Q26 = 493,
     514             :   Q25_Q26_Q27 = 494,
     515             :   Q26_Q27_Q28 = 495,
     516             :   Q27_Q28_Q29 = 496,
     517             :   Q28_Q29_Q30 = 497,
     518             :   Q29_Q30_Q31 = 498,
     519             :   Q30_Q31_Q0 = 499,
     520             :   Q31_Q0_Q1 = 500,
     521             :   WZR_W0 = 501,
     522             :   W30_WZR = 502,
     523             :   W0_W1 = 503,
     524             :   W1_W2 = 504,
     525             :   W2_W3 = 505,
     526             :   W3_W4 = 506,
     527             :   W4_W5 = 507,
     528             :   W5_W6 = 508,
     529             :   W6_W7 = 509,
     530             :   W7_W8 = 510,
     531             :   W8_W9 = 511,
     532             :   W9_W10 = 512,
     533             :   W10_W11 = 513,
     534             :   W11_W12 = 514,
     535             :   W12_W13 = 515,
     536             :   W13_W14 = 516,
     537             :   W14_W15 = 517,
     538             :   W15_W16 = 518,
     539             :   W16_W17 = 519,
     540             :   W17_W18 = 520,
     541             :   W18_W19 = 521,
     542             :   W19_W20 = 522,
     543             :   W20_W21 = 523,
     544             :   W21_W22 = 524,
     545             :   W22_W23 = 525,
     546             :   W23_W24 = 526,
     547             :   W24_W25 = 527,
     548             :   W25_W26 = 528,
     549             :   W26_W27 = 529,
     550             :   W27_W28 = 530,
     551             :   W28_W29 = 531,
     552             :   W29_W30 = 532,
     553             :   FP_LR = 533,
     554             :   LR_XZR = 534,
     555             :   XZR_X0 = 535,
     556             :   X28_FP = 536,
     557             :   X0_X1 = 537,
     558             :   X1_X2 = 538,
     559             :   X2_X3 = 539,
     560             :   X3_X4 = 540,
     561             :   X4_X5 = 541,
     562             :   X5_X6 = 542,
     563             :   X6_X7 = 543,
     564             :   X7_X8 = 544,
     565             :   X8_X9 = 545,
     566             :   X9_X10 = 546,
     567             :   X10_X11 = 547,
     568             :   X11_X12 = 548,
     569             :   X12_X13 = 549,
     570             :   X13_X14 = 550,
     571             :   X14_X15 = 551,
     572             :   X15_X16 = 552,
     573             :   X16_X17 = 553,
     574             :   X17_X18 = 554,
     575             :   X18_X19 = 555,
     576             :   X19_X20 = 556,
     577             :   X20_X21 = 557,
     578             :   X21_X22 = 558,
     579             :   X22_X23 = 559,
     580             :   X23_X24 = 560,
     581             :   X24_X25 = 561,
     582             :   X25_X26 = 562,
     583             :   X26_X27 = 563,
     584             :   X27_X28 = 564,
     585             :   Z0_Z1 = 565,
     586             :   Z1_Z2 = 566,
     587             :   Z2_Z3 = 567,
     588             :   Z3_Z4 = 568,
     589             :   Z4_Z5 = 569,
     590             :   Z5_Z6 = 570,
     591             :   Z6_Z7 = 571,
     592             :   Z7_Z8 = 572,
     593             :   Z8_Z9 = 573,
     594             :   Z9_Z10 = 574,
     595             :   Z10_Z11 = 575,
     596             :   Z11_Z12 = 576,
     597             :   Z12_Z13 = 577,
     598             :   Z13_Z14 = 578,
     599             :   Z14_Z15 = 579,
     600             :   Z15_Z16 = 580,
     601             :   Z16_Z17 = 581,
     602             :   Z17_Z18 = 582,
     603             :   Z18_Z19 = 583,
     604             :   Z19_Z20 = 584,
     605             :   Z20_Z21 = 585,
     606             :   Z21_Z22 = 586,
     607             :   Z22_Z23 = 587,
     608             :   Z23_Z24 = 588,
     609             :   Z24_Z25 = 589,
     610             :   Z25_Z26 = 590,
     611             :   Z26_Z27 = 591,
     612             :   Z27_Z28 = 592,
     613             :   Z28_Z29 = 593,
     614             :   Z29_Z30 = 594,
     615             :   Z30_Z31 = 595,
     616             :   Z31_Z0 = 596,
     617             :   Z0_Z1_Z2_Z3 = 597,
     618             :   Z1_Z2_Z3_Z4 = 598,
     619             :   Z2_Z3_Z4_Z5 = 599,
     620             :   Z3_Z4_Z5_Z6 = 600,
     621             :   Z4_Z5_Z6_Z7 = 601,
     622             :   Z5_Z6_Z7_Z8 = 602,
     623             :   Z6_Z7_Z8_Z9 = 603,
     624             :   Z7_Z8_Z9_Z10 = 604,
     625             :   Z8_Z9_Z10_Z11 = 605,
     626             :   Z9_Z10_Z11_Z12 = 606,
     627             :   Z10_Z11_Z12_Z13 = 607,
     628             :   Z11_Z12_Z13_Z14 = 608,
     629             :   Z12_Z13_Z14_Z15 = 609,
     630             :   Z13_Z14_Z15_Z16 = 610,
     631             :   Z14_Z15_Z16_Z17 = 611,
     632             :   Z15_Z16_Z17_Z18 = 612,
     633             :   Z16_Z17_Z18_Z19 = 613,
     634             :   Z17_Z18_Z19_Z20 = 614,
     635             :   Z18_Z19_Z20_Z21 = 615,
     636             :   Z19_Z20_Z21_Z22 = 616,
     637             :   Z20_Z21_Z22_Z23 = 617,
     638             :   Z21_Z22_Z23_Z24 = 618,
     639             :   Z22_Z23_Z24_Z25 = 619,
     640             :   Z23_Z24_Z25_Z26 = 620,
     641             :   Z24_Z25_Z26_Z27 = 621,
     642             :   Z25_Z26_Z27_Z28 = 622,
     643             :   Z26_Z27_Z28_Z29 = 623,
     644             :   Z27_Z28_Z29_Z30 = 624,
     645             :   Z28_Z29_Z30_Z31 = 625,
     646             :   Z29_Z30_Z31_Z0 = 626,
     647             :   Z30_Z31_Z0_Z1 = 627,
     648             :   Z31_Z0_Z1_Z2 = 628,
     649             :   Z0_Z1_Z2 = 629,
     650             :   Z1_Z2_Z3 = 630,
     651             :   Z2_Z3_Z4 = 631,
     652             :   Z3_Z4_Z5 = 632,
     653             :   Z4_Z5_Z6 = 633,
     654             :   Z5_Z6_Z7 = 634,
     655             :   Z6_Z7_Z8 = 635,
     656             :   Z7_Z8_Z9 = 636,
     657             :   Z8_Z9_Z10 = 637,
     658             :   Z9_Z10_Z11 = 638,
     659             :   Z10_Z11_Z12 = 639,
     660             :   Z11_Z12_Z13 = 640,
     661             :   Z12_Z13_Z14 = 641,
     662             :   Z13_Z14_Z15 = 642,
     663             :   Z14_Z15_Z16 = 643,
     664             :   Z15_Z16_Z17 = 644,
     665             :   Z16_Z17_Z18 = 645,
     666             :   Z17_Z18_Z19 = 646,
     667             :   Z18_Z19_Z20 = 647,
     668             :   Z19_Z20_Z21 = 648,
     669             :   Z20_Z21_Z22 = 649,
     670             :   Z21_Z22_Z23 = 650,
     671             :   Z22_Z23_Z24 = 651,
     672             :   Z23_Z24_Z25 = 652,
     673             :   Z24_Z25_Z26 = 653,
     674             :   Z25_Z26_Z27 = 654,
     675             :   Z26_Z27_Z28 = 655,
     676             :   Z27_Z28_Z29 = 656,
     677             :   Z28_Z29_Z30 = 657,
     678             :   Z29_Z30_Z31 = 658,
     679             :   Z30_Z31_Z0 = 659,
     680             :   Z31_Z0_Z1 = 660,
     681             :   NUM_TARGET_REGS       // 661
     682             : };
     683             : } // end namespace AArch64
     684             : 
     685             : // Register classes
     686             : 
     687             : namespace AArch64 {
     688             : enum {
     689             :   FPR8RegClassID = 0,
     690             :   FPR16RegClassID = 1,
     691             :   PPRRegClassID = 2,
     692             :   PPR_3bRegClassID = 3,
     693             :   GPR32allRegClassID = 4,
     694             :   FPR32RegClassID = 5,
     695             :   GPR32RegClassID = 6,
     696             :   GPR32spRegClassID = 7,
     697             :   GPR32commonRegClassID = 8,
     698             :   CCRRegClassID = 9,
     699             :   GPR32sponlyRegClassID = 10,
     700             :   WSeqPairsClassRegClassID = 11,
     701             :   WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12,
     702             :   WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
     703             :   WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14,
     704             :   GPR64allRegClassID = 15,
     705             :   FPR64RegClassID = 16,
     706             :   GPR64RegClassID = 17,
     707             :   GPR64spRegClassID = 18,
     708             :   GPR64commonRegClassID = 19,
     709             :   tcGPR64RegClassID = 20,
     710             :   GPR64sponlyRegClassID = 21,
     711             :   DDRegClassID = 22,
     712             :   XSeqPairsClassRegClassID = 23,
     713             :   XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 24,
     714             :   XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 25,
     715             :   XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26,
     716             :   XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 27,
     717             :   XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 28,
     718             :   XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29,
     719             :   FPR128RegClassID = 30,
     720             :   ZPRRegClassID = 31,
     721             :   FPR128_loRegClassID = 32,
     722             :   ZPR_4bRegClassID = 33,
     723             :   ZPR_3bRegClassID = 34,
     724             :   DDDRegClassID = 35,
     725             :   DDDDRegClassID = 36,
     726             :   QQRegClassID = 37,
     727             :   ZPR2RegClassID = 38,
     728             :   QQ_with_qsub0_in_FPR128_loRegClassID = 39,
     729             :   QQ_with_qsub1_in_FPR128_loRegClassID = 40,
     730             :   ZPR2_with_zsub1_in_ZPR_4bRegClassID = 41,
     731             :   ZPR2_with_zsub_in_FPR128_loRegClassID = 42,
     732             :   QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 43,
     733             :   ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 44,
     734             :   ZPR2_with_zsub0_in_ZPR_3bRegClassID = 45,
     735             :   ZPR2_with_zsub1_in_ZPR_3bRegClassID = 46,
     736             :   ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 47,
     737             :   QQQRegClassID = 48,
     738             :   ZPR3RegClassID = 49,
     739             :   QQQ_with_qsub0_in_FPR128_loRegClassID = 50,
     740             :   QQQ_with_qsub1_in_FPR128_loRegClassID = 51,
     741             :   QQQ_with_qsub2_in_FPR128_loRegClassID = 52,
     742             :   ZPR3_with_zsub1_in_ZPR_4bRegClassID = 53,
     743             :   ZPR3_with_zsub2_in_ZPR_4bRegClassID = 54,
     744             :   ZPR3_with_zsub_in_FPR128_loRegClassID = 55,
     745             :   QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 56,
     746             :   QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 57,
     747             :   ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 58,
     748             :   ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 59,
     749             :   QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 60,
     750             :   ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 61,
     751             :   ZPR3_with_zsub0_in_ZPR_3bRegClassID = 62,
     752             :   ZPR3_with_zsub1_in_ZPR_3bRegClassID = 63,
     753             :   ZPR3_with_zsub2_in_ZPR_3bRegClassID = 64,
     754             :   ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 65,
     755             :   ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 66,
     756             :   ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 67,
     757             :   QQQQRegClassID = 68,
     758             :   ZPR4RegClassID = 69,
     759             :   QQQQ_with_qsub0_in_FPR128_loRegClassID = 70,
     760             :   QQQQ_with_qsub1_in_FPR128_loRegClassID = 71,
     761             :   QQQQ_with_qsub2_in_FPR128_loRegClassID = 72,
     762             :   QQQQ_with_qsub3_in_FPR128_loRegClassID = 73,
     763             :   ZPR4_with_zsub1_in_ZPR_4bRegClassID = 74,
     764             :   ZPR4_with_zsub2_in_ZPR_4bRegClassID = 75,
     765             :   ZPR4_with_zsub3_in_ZPR_4bRegClassID = 76,
     766             :   ZPR4_with_zsub_in_FPR128_loRegClassID = 77,
     767             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 78,
     768             :   QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 79,
     769             :   QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 80,
     770             :   ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 81,
     771             :   ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 82,
     772             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 83,
     773             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 84,
     774             :   QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 85,
     775             :   ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 86,
     776             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 87,
     777             :   QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 88,
     778             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 89,
     779             :   ZPR4_with_zsub0_in_ZPR_3bRegClassID = 90,
     780             :   ZPR4_with_zsub1_in_ZPR_3bRegClassID = 91,
     781             :   ZPR4_with_zsub2_in_ZPR_3bRegClassID = 92,
     782             :   ZPR4_with_zsub3_in_ZPR_3bRegClassID = 93,
     783             :   ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 94,
     784             :   ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 95,
     785             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 96,
     786             :   ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 97,
     787             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 98,
     788             :   ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 99,
     789             : 
     790             :   };
     791             : } // end namespace AArch64
     792             : 
     793             : 
     794             : // Register alternate name indices
     795             : 
     796             : namespace AArch64 {
     797             : enum {
     798             :   NoRegAltName, // 0
     799             :   vlist1,       // 1
     800             :   vreg, // 2
     801             :   NUM_TARGET_REG_ALT_NAMES = 3
     802             : };
     803             : } // end namespace AArch64
     804             : 
     805             : 
     806             : // Subregister indices
     807             : 
     808             : namespace AArch64 {
     809             : enum {
     810             :   NoSubRegister,
     811             :   bsub, // 1
     812             :   dsub, // 2
     813             :   dsub0,        // 3
     814             :   dsub1,        // 4
     815             :   dsub2,        // 5
     816             :   dsub3,        // 6
     817             :   hsub, // 7
     818             :   qhisub,       // 8
     819             :   qsub, // 9
     820             :   qsub0,        // 10
     821             :   qsub1,        // 11
     822             :   qsub2,        // 12
     823             :   qsub3,        // 13
     824             :   ssub, // 14
     825             :   sub_32,       // 15
     826             :   sube32,       // 16
     827             :   sube64,       // 17
     828             :   subo32,       // 18
     829             :   subo64,       // 19
     830             :   zsub, // 20
     831             :   zsub0,        // 21
     832             :   zsub1,        // 22
     833             :   zsub2,        // 23
     834             :   zsub3,        // 24
     835             :   zsub_hi,      // 25
     836             :   dsub1_then_bsub,      // 26
     837             :   dsub1_then_hsub,      // 27
     838             :   dsub1_then_ssub,      // 28
     839             :   dsub3_then_bsub,      // 29
     840             :   dsub3_then_hsub,      // 30
     841             :   dsub3_then_ssub,      // 31
     842             :   dsub2_then_bsub,      // 32
     843             :   dsub2_then_hsub,      // 33
     844             :   dsub2_then_ssub,      // 34
     845             :   qsub1_then_bsub,      // 35
     846             :   qsub1_then_dsub,      // 36
     847             :   qsub1_then_hsub,      // 37
     848             :   qsub1_then_ssub,      // 38
     849             :   qsub3_then_bsub,      // 39
     850             :   qsub3_then_dsub,      // 40
     851             :   qsub3_then_hsub,      // 41
     852             :   qsub3_then_ssub,      // 42
     853             :   qsub2_then_bsub,      // 43
     854             :   qsub2_then_dsub,      // 44
     855             :   qsub2_then_hsub,      // 45
     856             :   qsub2_then_ssub,      // 46
     857             :   subo64_then_sub_32,   // 47
     858             :   zsub1_then_bsub,      // 48
     859             :   zsub1_then_dsub,      // 49
     860             :   zsub1_then_hsub,      // 50
     861             :   zsub1_then_ssub,      // 51
     862             :   zsub1_then_zsub,      // 52
     863             :   zsub1_then_zsub_hi,   // 53
     864             :   zsub3_then_bsub,      // 54
     865             :   zsub3_then_dsub,      // 55
     866             :   zsub3_then_hsub,      // 56
     867             :   zsub3_then_ssub,      // 57
     868             :   zsub3_then_zsub,      // 58
     869             :   zsub3_then_zsub_hi,   // 59
     870             :   zsub2_then_bsub,      // 60
     871             :   zsub2_then_dsub,      // 61
     872             :   zsub2_then_hsub,      // 62
     873             :   zsub2_then_ssub,      // 63
     874             :   zsub2_then_zsub,      // 64
     875             :   zsub2_then_zsub_hi,   // 65
     876             :   dsub0_dsub1,  // 66
     877             :   dsub0_dsub1_dsub2,    // 67
     878             :   dsub1_dsub2,  // 68
     879             :   dsub1_dsub2_dsub3,    // 69
     880             :   dsub2_dsub3,  // 70
     881             :   dsub_qsub1_then_dsub, // 71
     882             :   dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 72
     883             :   dsub_qsub1_then_dsub_qsub2_then_dsub, // 73
     884             :   qsub0_qsub1,  // 74
     885             :   qsub0_qsub1_qsub2,    // 75
     886             :   qsub1_qsub2,  // 76
     887             :   qsub1_qsub2_qsub3,    // 77
     888             :   qsub2_qsub3,  // 78
     889             :   qsub1_then_dsub_qsub2_then_dsub,      // 79
     890             :   qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,      // 80
     891             :   qsub2_then_dsub_qsub3_then_dsub,      // 81
     892             :   sub_32_subo64_then_sub_32,    // 82
     893             :   dsub_zsub1_then_dsub, // 83
     894             :   zsub_zsub1_then_zsub, // 84
     895             :   dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 85
     896             :   dsub_zsub1_then_dsub_zsub2_then_dsub, // 86
     897             :   zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 87
     898             :   zsub_zsub1_then_zsub_zsub2_then_zsub, // 88
     899             :   zsub0_zsub1,  // 89
     900             :   zsub0_zsub1_zsub2,    // 90
     901             :   zsub1_zsub2,  // 91
     902             :   zsub1_zsub2_zsub3,    // 92
     903             :   zsub2_zsub3,  // 93
     904             :   zsub1_then_dsub_zsub2_then_dsub,      // 94
     905             :   zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,      // 95
     906             :   zsub1_then_zsub_zsub2_then_zsub,      // 96
     907             :   zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,      // 97
     908             :   zsub2_then_dsub_zsub3_then_dsub,      // 98
     909             :   zsub2_then_zsub_zsub3_then_zsub,      // 99
     910             :   NUM_TARGET_SUBREGS
     911             : };
     912             : } // end namespace AArch64
     913             : 
     914             : } // end namespace llvm
     915             : 
     916             : #endif // GET_REGINFO_ENUM
     917             : 
     918             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
     919             : |*                                                                            *|
     920             : |* MC Register Information                                                    *|
     921             : |*                                                                            *|
     922             : |* Automatically generated file, do not edit!                                 *|
     923             : |*                                                                            *|
     924             : \*===----------------------------------------------------------------------===*/
     925             : 
     926             : 
     927             : #ifdef GET_REGINFO_MC_DESC
     928             : #undef GET_REGINFO_MC_DESC
     929             : 
     930             : namespace llvm {
     931             : 
     932             : extern const MCPhysReg AArch64RegDiffLists[] = {
     933             :   /* 0 */ 64945, 1, 1, 1, 74, 1, 1, 1, 0,
     934             :   /* 9 */ 65105, 1, 1, 1, 0,
     935             :   /* 14 */ 65201, 1, 1, 1, 0,
     936             :   /* 19 */ 6, 29, 1, 1, 0,
     937             :   /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0,
     938             :   /* 33 */ 65324, 499, 30, 1, 1, 0,
     939             :   /* 39 */ 64913, 1, 1, 75, 1, 1, 0,
     940             :   /* 46 */ 65073, 1, 1, 0,
     941             :   /* 50 */ 65169, 1, 1, 0,
     942             :   /* 54 */ 6, 1, 29, 1, 0,
     943             :   /* 59 */ 6, 1, 29, 1, 46, 1, 29, 1, 0,
     944             :   /* 68 */ 6, 30, 1, 0,
     945             :   /* 72 */ 6, 30, 1, 46, 30, 1, 0,
     946             :   /* 79 */ 1, 493, 1, 32, 1, 0,
     947             :   /* 85 */ 31, 286, 1, 33, 1, 0,
     948             :   /* 91 */ 64977, 1, 76, 1, 0,
     949             :   /* 96 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
     950             :   /* 111 */ 320, 1, 0,
     951             :   /* 114 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
     952             :   /* 129 */ 526, 1, 0,
     953             :   /* 132 */ 530, 1, 0,
     954             :   /* 135 */ 65053, 1, 0,
     955             :   /* 138 */ 65087, 1, 0,
     956             :   /* 141 */ 65137, 1, 0,
     957             :   /* 144 */ 65218, 1, 0,
     958             :   /* 147 */ 65233, 1, 0,
     959             :   /* 150 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     960             :   /* 183 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     961             :   /* 203 */ 65504, 319, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
     962             :   /* 214 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     963             :   /* 247 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     964             :   /* 267 */ 65504, 320, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
     965             :   /* 278 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 128, 63, 65503, 34, 65503, 1, 0,
     966             :   /* 296 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     967             :   /* 329 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     968             :   /* 349 */ 65504, 319, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
     969             :   /* 360 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 97, 64, 65504, 63, 65503, 1, 0,
     970             :   /* 378 */ 65503, 1, 128, 65503, 1, 192, 65503, 1, 0,
     971             :   /* 387 */ 31, 285, 2, 32, 2, 0,
     972             :   /* 393 */ 319, 2, 0,
     973             :   /* 396 */ 65324, 529, 1, 1, 3, 0,
     974             :   /* 402 */ 2, 3, 0,
     975             :   /* 405 */ 531, 3, 0,
     976             :   /* 408 */ 65004, 3, 0,
     977             :   /* 411 */ 4, 0,
     978             :   /* 413 */ 5, 0,
     979             :   /* 415 */ 31, 286, 1, 5, 28, 0,
     980             :   /* 421 */ 292, 28, 0,
     981             :   /* 424 */ 6, 1, 1, 29, 0,
     982             :   /* 429 */ 6, 1, 1, 29, 46, 1, 1, 29, 0,
     983             :   /* 438 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     984             :   /* 471 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     985             :   /* 491 */ 65504, 319, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
     986             :   /* 502 */ 6, 1, 30, 0,
     987             :   /* 506 */ 6, 1, 30, 46, 1, 30, 0,
     988             :   /* 513 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 98, 63, 1, 65503, 1, 30, 0,
     989             :   /* 531 */ 6, 31, 0,
     990             :   /* 534 */ 6, 31, 46, 31, 0,
     991             :   /* 539 */ 65504, 31, 97, 65504, 31, 161, 65504, 31, 0,
     992             :   /* 548 */ 32, 0,
     993             :   /* 550 */ 34, 0,
     994             :   /* 552 */ 5, 49, 0,
     995             :   /* 555 */ 63936, 49, 0,
     996             :   /* 558 */ 65297, 77, 0,
     997             :   /* 561 */ 1, 81, 0,
     998             :   /* 564 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0,
     999             :   /* 581 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0,
    1000             :   /* 598 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 96, 1, 65280, 96, 0,
    1001             :   /* 628 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 1, 65280, 96, 0,
    1002             :   /* 658 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 65505, 65280, 96, 0,
    1003             :   /* 688 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65441, 65311, 64, 32, 64, 65345, 96, 0,
    1004             :   /* 734 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65441, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
    1005             :   /* 780 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
    1006             :   /* 826 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
    1007             :   /* 872 */ 96, 160, 0,
    1008             :   /* 875 */ 65042, 178, 0,
    1009             :   /* 878 */ 212, 0,
    1010             :   /* 880 */ 65412, 65456, 112, 65456, 65472, 268, 0,
    1011             :   /* 887 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
    1012             :   /* 899 */ 65009, 65535, 209, 65505, 316, 0,
    1013             :   /* 905 */ 65005, 212, 65325, 212, 317, 0,
    1014             :   /* 911 */ 65244, 65505, 65325, 212, 317, 0,
    1015             :   /* 917 */ 65215, 65505, 32, 65505, 317, 0,
    1016             :   /* 923 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
    1017             :   /* 935 */ 65005, 212, 65329, 65535, 495, 0,
    1018             :   /* 941 */ 65323, 0,
    1019             :   /* 943 */ 65249, 65328, 0,
    1020             :   /* 946 */ 65342, 0,
    1021             :   /* 948 */ 65374, 0,
    1022             :   /* 950 */ 65389, 0,
    1023             :   /* 952 */ 65405, 0,
    1024             :   /* 954 */ 65421, 0,
    1025             :   /* 956 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
    1026             :   /* 977 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
    1027             :   /* 998 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
    1028             :   /* 1019 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
    1029             :   /* 1051 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
    1030             :   /* 1073 */ 65469, 0,
    1031             :   /* 1075 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
    1032             :   /* 1084 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
    1033             :   /* 1093 */ 65456, 112, 65456, 65472, 0,
    1034             :   /* 1098 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
    1035             :   /* 1130 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
    1036             :   /* 1162 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
    1037             :   /* 1194 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
    1038             :   /* 1216 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
    1039             :   /* 1238 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
    1040             :   /* 1260 */ 65501, 0,
    1041             :   /* 1262 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
    1042             :   /* 1277 */ 65533, 0,
    1043             :   /* 1279 */ 65535, 0,
    1044             : };
    1045             : 
    1046             : extern const LaneBitmask AArch64LaneMaskLists[] = {
    1047             :   /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
    1048             :   /* 2 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1049             :   /* 5 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1050             :   /* 10 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1051             :   /* 14 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1052             :   /* 17 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1053             :   /* 22 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask::getAll(),
    1054             :   /* 26 */ LaneBitmask(0x00002000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
    1055             :   /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
    1056             :   /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
    1057             :   /* 35 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
    1058             :   /* 38 */ LaneBitmask(0x00004000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
    1059             :   /* 43 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
    1060             :   /* 52 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
    1061             :   /* 59 */ LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
    1062             :   /* 64 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
    1063             :   /* 68 */ LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask::getAll(),
    1064             :   /* 73 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask::getAll(),
    1065             :   /* 78 */ LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
    1066             :   /* 83 */ LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
    1067             :   /* 87 */ LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask::getAll(),
    1068             :   /* 92 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask::getAll(),
    1069             :   /* 97 */ LaneBitmask(0x00000008), LaneBitmask(0x00002000), LaneBitmask::getAll(),
    1070             :   /* 100 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
    1071             :   /* 105 */ LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
    1072             :   /* 114 */ LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
    1073             :   /* 121 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
    1074             :   /* 130 */ LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
    1075             :   /* 139 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
    1076             : };
    1077             : 
    1078             : extern const uint16_t AArch64SubRegIdxLists[] = {
    1079             :   /* 0 */ 2, 14, 7, 1, 0,
    1080             :   /* 5 */ 15, 0,
    1081             :   /* 7 */ 16, 18, 0,
    1082             :   /* 10 */ 20, 2, 14, 7, 1, 25, 0,
    1083             :   /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0,
    1084             :   /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0,
    1085             :   /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0,
    1086             :   /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0,
    1087             :   /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0,
    1088             :   /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0,
    1089             :   /* 128 */ 17, 15, 19, 47, 82, 0,
    1090             :   /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0,
    1091             :   /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0,
    1092             :   /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
    1093             : };
    1094             : 
    1095             : extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
    1096             :   { 65535, 65535 },
    1097             :   { 0, 8 },     // bsub
    1098             :   { 0, 32 },    // dsub
    1099             :   { 0, 64 },    // dsub0
    1100             :   { 0, 64 },    // dsub1
    1101             :   { 0, 64 },    // dsub2
    1102             :   { 0, 64 },    // dsub3
    1103             :   { 0, 16 },    // hsub
    1104             :   { 0, 64 },    // qhisub
    1105             :   { 0, 64 },    // qsub
    1106             :   { 0, 128 },   // qsub0
    1107             :   { 0, 128 },   // qsub1
    1108             :   { 0, 128 },   // qsub2
    1109             :   { 0, 128 },   // qsub3
    1110             :   { 0, 32 },    // ssub
    1111             :   { 0, 32 },    // sub_32
    1112             :   { 0, 32 },    // sube32
    1113             :   { 0, 64 },    // sube64
    1114             :   { 0, 32 },    // subo32
    1115             :   { 0, 64 },    // subo64
    1116             :   { 0, 128 },   // zsub
    1117             :   { 65535, 128 },       // zsub0
    1118             :   { 65535, 128 },       // zsub1
    1119             :   { 65535, 128 },       // zsub2
    1120             :   { 65535, 128 },       // zsub3
    1121             :   { 0, 128 },   // zsub_hi
    1122             :   { 0, 8 },     // dsub1_then_bsub
    1123             :   { 0, 16 },    // dsub1_then_hsub
    1124             :   { 0, 32 },    // dsub1_then_ssub
    1125             :   { 0, 8 },     // dsub3_then_bsub
    1126             :   { 0, 16 },    // dsub3_then_hsub
    1127             :   { 0, 32 },    // dsub3_then_ssub
    1128             :   { 0, 8 },     // dsub2_then_bsub
    1129             :   { 0, 16 },    // dsub2_then_hsub
    1130             :   { 0, 32 },    // dsub2_then_ssub
    1131             :   { 0, 8 },     // qsub1_then_bsub
    1132             :   { 0, 32 },    // qsub1_then_dsub
    1133             :   { 0, 16 },    // qsub1_then_hsub
    1134             :   { 0, 32 },    // qsub1_then_ssub
    1135             :   { 0, 8 },     // qsub3_then_bsub
    1136             :   { 0, 32 },    // qsub3_then_dsub
    1137             :   { 0, 16 },    // qsub3_then_hsub
    1138             :   { 0, 32 },    // qsub3_then_ssub
    1139             :   { 0, 8 },     // qsub2_then_bsub
    1140             :   { 0, 32 },    // qsub2_then_dsub
    1141             :   { 0, 16 },    // qsub2_then_hsub
    1142             :   { 0, 32 },    // qsub2_then_ssub
    1143             :   { 0, 32 },    // subo64_then_sub_32
    1144             :   { 65535, 65535 },     // zsub1_then_bsub
    1145             :   { 65535, 65535 },     // zsub1_then_dsub
    1146             :   { 65535, 65535 },     // zsub1_then_hsub
    1147             :   { 65535, 65535 },     // zsub1_then_ssub
    1148             :   { 65535, 65535 },     // zsub1_then_zsub
    1149             :   { 65535, 65535 },     // zsub1_then_zsub_hi
    1150             :   { 65535, 65535 },     // zsub3_then_bsub
    1151             :   { 65535, 65535 },     // zsub3_then_dsub
    1152             :   { 65535, 65535 },     // zsub3_then_hsub
    1153             :   { 65535, 65535 },     // zsub3_then_ssub
    1154             :   { 65535, 65535 },     // zsub3_then_zsub
    1155             :   { 65535, 65535 },     // zsub3_then_zsub_hi
    1156             :   { 65535, 65535 },     // zsub2_then_bsub
    1157             :   { 65535, 65535 },     // zsub2_then_dsub
    1158             :   { 65535, 65535 },     // zsub2_then_hsub
    1159             :   { 65535, 65535 },     // zsub2_then_ssub
    1160             :   { 65535, 65535 },     // zsub2_then_zsub
    1161             :   { 65535, 65535 },     // zsub2_then_zsub_hi
    1162             :   { 65535, 128 },       // dsub0_dsub1
    1163             :   { 65535, 192 },       // dsub0_dsub1_dsub2
    1164             :   { 65535, 128 },       // dsub1_dsub2
    1165             :   { 65535, 192 },       // dsub1_dsub2_dsub3
    1166             :   { 65535, 128 },       // dsub2_dsub3
    1167             :   { 65535, 64 },        // dsub_qsub1_then_dsub
    1168             :   { 65535, 128 },       // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    1169             :   { 65535, 96 },        // dsub_qsub1_then_dsub_qsub2_then_dsub
    1170             :   { 65535, 256 },       // qsub0_qsub1
    1171             :   { 65535, 384 },       // qsub0_qsub1_qsub2
    1172             :   { 65535, 256 },       // qsub1_qsub2
    1173             :   { 65535, 384 },       // qsub1_qsub2_qsub3
    1174             :   { 65535, 256 },       // qsub2_qsub3
    1175             :   { 65535, 64 },        // qsub1_then_dsub_qsub2_then_dsub
    1176             :   { 65535, 96 },        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    1177             :   { 65535, 64 },        // qsub2_then_dsub_qsub3_then_dsub
    1178             :   { 65535, 64 },        // sub_32_subo64_then_sub_32
    1179             :   { 65535, 31 },        // dsub_zsub1_then_dsub
    1180             :   { 65535, 127 },       // zsub_zsub1_then_zsub
    1181             :   { 65535, 29 },        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    1182             :   { 65535, 30 },        // dsub_zsub1_then_dsub_zsub2_then_dsub
    1183             :   { 65535, 125 },       // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    1184             :   { 65535, 126 },       // zsub_zsub1_then_zsub_zsub2_then_zsub
    1185             :   { 65535, 256 },       // zsub0_zsub1
    1186             :   { 65535, 384 },       // zsub0_zsub1_zsub2
    1187             :   { 65535, 256 },       // zsub1_zsub2
    1188             :   { 65535, 384 },       // zsub1_zsub2_zsub3
    1189             :   { 65535, 256 },       // zsub2_zsub3
    1190             :   { 65535, 65534 },     // zsub1_then_dsub_zsub2_then_dsub
    1191             :   { 65535, 65533 },     // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    1192             :   { 65535, 65534 },     // zsub1_then_zsub_zsub2_then_zsub
    1193             :   { 65535, 65533 },     // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    1194             :   { 65535, 65534 },     // zsub2_then_dsub_zsub3_then_dsub
    1195             :   { 65535, 65534 },     // zsub2_then_zsub_zsub3_then_zsub
    1196             : };
    1197             : 
    1198             : extern const char AArch64RegStrings[] = {
    1199             :   /* 0 */ 'B', '1', '0', 0,
    1200             :   /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
    1201             :   /* 17 */ 'H', '1', '0', 0,
    1202             :   /* 21 */ 'P', '1', '0', 0,
    1203             :   /* 25 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
    1204             :   /* 38 */ 'S', '1', '0', 0,
    1205             :   /* 42 */ 'W', '9', '_', 'W', '1', '0', 0,
    1206             :   /* 49 */ 'X', '9', '_', 'X', '1', '0', 0,
    1207             :   /* 56 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0,
    1208             :   /* 69 */ 'B', '2', '0', 0,
    1209             :   /* 73 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
    1210             :   /* 89 */ 'H', '2', '0', 0,
    1211             :   /* 93 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
    1212             :   /* 109 */ 'S', '2', '0', 0,
    1213             :   /* 113 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
    1214             :   /* 121 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
    1215             :   /* 129 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0,
    1216             :   /* 145 */ 'B', '3', '0', 0,
    1217             :   /* 149 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
    1218             :   /* 165 */ 'H', '3', '0', 0,
    1219             :   /* 169 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
    1220             :   /* 185 */ 'S', '3', '0', 0,
    1221             :   /* 189 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
    1222             :   /* 197 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0,
    1223             :   /* 213 */ 'B', '0', 0,
    1224             :   /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
    1225             :   /* 231 */ 'H', '0', 0,
    1226             :   /* 234 */ 'P', '0', 0,
    1227             :   /* 237 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
    1228             :   /* 252 */ 'S', '0', 0,
    1229             :   /* 255 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
    1230             :   /* 262 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
    1231             :   /* 269 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0,
    1232             :   /* 284 */ 'B', '1', '1', 0,
    1233             :   /* 288 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
    1234             :   /* 302 */ 'H', '1', '1', 0,
    1235             :   /* 306 */ 'P', '1', '1', 0,
    1236             :   /* 310 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
    1237             :   /* 324 */ 'S', '1', '1', 0,
    1238             :   /* 328 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
    1239             :   /* 336 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
    1240             :   /* 344 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0,
    1241             :   /* 358 */ 'B', '2', '1', 0,
    1242             :   /* 362 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
    1243             :   /* 378 */ 'H', '2', '1', 0,
    1244             :   /* 382 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
    1245             :   /* 398 */ 'S', '2', '1', 0,
    1246             :   /* 402 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
    1247             :   /* 410 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
    1248             :   /* 418 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0,
    1249             :   /* 434 */ 'B', '3', '1', 0,
    1250             :   /* 438 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
    1251             :   /* 454 */ 'H', '3', '1', 0,
    1252             :   /* 458 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
    1253             :   /* 474 */ 'S', '3', '1', 0,
    1254             :   /* 478 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0,
    1255             :   /* 494 */ 'B', '1', 0,
    1256             :   /* 497 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
    1257             :   /* 511 */ 'H', '1', 0,
    1258             :   /* 514 */ 'P', '1', 0,
    1259             :   /* 517 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
    1260             :   /* 531 */ 'S', '1', 0,
    1261             :   /* 534 */ 'W', '0', '_', 'W', '1', 0,
    1262             :   /* 540 */ 'X', '0', '_', 'X', '1', 0,
    1263             :   /* 546 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0,
    1264             :   /* 560 */ 'B', '1', '2', 0,
    1265             :   /* 564 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
    1266             :   /* 579 */ 'H', '1', '2', 0,
    1267             :   /* 583 */ 'P', '1', '2', 0,
    1268             :   /* 587 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
    1269             :   /* 602 */ 'S', '1', '2', 0,
    1270             :   /* 606 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
    1271             :   /* 614 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
    1272             :   /* 622 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0,
    1273             :   /* 637 */ 'B', '2', '2', 0,
    1274             :   /* 641 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
    1275             :   /* 657 */ 'H', '2', '2', 0,
    1276             :   /* 661 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
    1277             :   /* 677 */ 'S', '2', '2', 0,
    1278             :   /* 681 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
    1279             :   /* 689 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
    1280             :   /* 697 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0,
    1281             :   /* 713 */ 'B', '2', 0,
    1282             :   /* 716 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
    1283             :   /* 729 */ 'H', '2', 0,
    1284             :   /* 732 */ 'P', '2', 0,
    1285             :   /* 735 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
    1286             :   /* 748 */ 'S', '2', 0,
    1287             :   /* 751 */ 'W', '1', '_', 'W', '2', 0,
    1288             :   /* 757 */ 'X', '1', '_', 'X', '2', 0,
    1289             :   /* 763 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0,
    1290             :   /* 776 */ 'B', '1', '3', 0,
    1291             :   /* 780 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
    1292             :   /* 796 */ 'H', '1', '3', 0,
    1293             :   /* 800 */ 'P', '1', '3', 0,
    1294             :   /* 804 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
    1295             :   /* 820 */ 'S', '1', '3', 0,
    1296             :   /* 824 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
    1297             :   /* 832 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
    1298             :   /* 840 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0,
    1299             :   /* 856 */ 'B', '2', '3', 0,
    1300             :   /* 860 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
    1301             :   /* 876 */ 'H', '2', '3', 0,
    1302             :   /* 880 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
    1303             :   /* 896 */ 'S', '2', '3', 0,
    1304             :   /* 900 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
    1305             :   /* 908 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
    1306             :   /* 916 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0,
    1307             :   /* 932 */ 'B', '3', 0,
    1308             :   /* 935 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
    1309             :   /* 947 */ 'H', '3', 0,
    1310             :   /* 950 */ 'P', '3', 0,
    1311             :   /* 953 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
    1312             :   /* 965 */ 'S', '3', 0,
    1313             :   /* 968 */ 'W', '2', '_', 'W', '3', 0,
    1314             :   /* 974 */ 'X', '2', '_', 'X', '3', 0,
    1315             :   /* 980 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0,
    1316             :   /* 992 */ 'B', '1', '4', 0,
    1317             :   /* 996 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
    1318             :   /* 1012 */ 'H', '1', '4', 0,
    1319             :   /* 1016 */ 'P', '1', '4', 0,
    1320             :   /* 1020 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
    1321             :   /* 1036 */ 'S', '1', '4', 0,
    1322             :   /* 1040 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
    1323             :   /* 1048 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
    1324             :   /* 1056 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0,
    1325             :   /* 1072 */ 'B', '2', '4', 0,
    1326             :   /* 1076 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
    1327             :   /* 1092 */ 'H', '2', '4', 0,
    1328             :   /* 1096 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
    1329             :   /* 1112 */ 'S', '2', '4', 0,
    1330             :   /* 1116 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
    1331             :   /* 1124 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
    1332             :   /* 1132 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0,
    1333             :   /* 1148 */ 'B', '4', 0,
    1334             :   /* 1151 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
    1335             :   /* 1163 */ 'H', '4', 0,
    1336             :   /* 1166 */ 'P', '4', 0,
    1337             :   /* 1169 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
    1338             :   /* 1181 */ 'S', '4', 0,
    1339             :   /* 1184 */ 'W', '3', '_', 'W', '4', 0,
    1340             :   /* 1190 */ 'X', '3', '_', 'X', '4', 0,
    1341             :   /* 1196 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0,
    1342             :   /* 1208 */ 'B', '1', '5', 0,
    1343             :   /* 1212 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
    1344             :   /* 1228 */ 'H', '1', '5', 0,
    1345             :   /* 1232 */ 'P', '1', '5', 0,
    1346             :   /* 1236 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
    1347             :   /* 1252 */ 'S', '1', '5', 0,
    1348             :   /* 1256 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
    1349             :   /* 1264 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
    1350             :   /* 1272 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0,
    1351             :   /* 1288 */ 'B', '2', '5', 0,
    1352             :   /* 1292 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
    1353             :   /* 1308 */ 'H', '2', '5', 0,
    1354             :   /* 1312 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
    1355             :   /* 1328 */ 'S', '2', '5', 0,
    1356             :   /* 1332 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
    1357             :   /* 1340 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
    1358             :   /* 1348 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0,
    1359             :   /* 1364 */ 'B', '5', 0,
    1360             :   /* 1367 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
    1361             :   /* 1379 */ 'H', '5', 0,
    1362             :   /* 1382 */ 'P', '5', 0,
    1363             :   /* 1385 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
    1364             :   /* 1397 */ 'S', '5', 0,
    1365             :   /* 1400 */ 'W', '4', '_', 'W', '5', 0,
    1366             :   /* 1406 */ 'X', '4', '_', 'X', '5', 0,
    1367             :   /* 1412 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0,
    1368             :   /* 1424 */ 'B', '1', '6', 0,
    1369             :   /* 1428 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
    1370             :   /* 1444 */ 'H', '1', '6', 0,
    1371             :   /* 1448 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
    1372             :   /* 1464 */ 'S', '1', '6', 0,
    1373             :   /* 1468 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
    1374             :   /* 1476 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
    1375             :   /* 1484 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0,
    1376             :   /* 1500 */ 'B', '2', '6', 0,
    1377             :   /* 1504 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
    1378             :   /* 1520 */ 'H', '2', '6', 0,
    1379             :   /* 1524 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
    1380             :   /* 1540 */ 'S', '2', '6', 0,
    1381             :   /* 1544 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
    1382             :   /* 1552 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
    1383             :   /* 1560 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0,
    1384             :   /* 1576 */ 'B', '6', 0,
    1385             :   /* 1579 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
    1386             :   /* 1591 */ 'H', '6', 0,
    1387             :   /* 1594 */ 'P', '6', 0,
    1388             :   /* 1597 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
    1389             :   /* 1609 */ 'S', '6', 0,
    1390             :   /* 1612 */ 'W', '5', '_', 'W', '6', 0,
    1391             :   /* 1618 */ 'X', '5', '_', 'X', '6', 0,
    1392             :   /* 1624 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0,
    1393             :   /* 1636 */ 'B', '1', '7', 0,
    1394             :   /* 1640 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
    1395             :   /* 1656 */ 'H', '1', '7', 0,
    1396             :   /* 1660 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
    1397             :   /* 1676 */ 'S', '1', '7', 0,
    1398             :   /* 1680 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
    1399             :   /* 1688 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
    1400             :   /* 1696 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0,
    1401             :   /* 1712 */ 'B', '2', '7', 0,
    1402             :   /* 1716 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
    1403             :   /* 1732 */ 'H', '2', '7', 0,
    1404             :   /* 1736 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
    1405             :   /* 1752 */ 'S', '2', '7', 0,
    1406             :   /* 1756 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
    1407             :   /* 1764 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
    1408             :   /* 1772 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0,
    1409             :   /* 1788 */ 'B', '7', 0,
    1410             :   /* 1791 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
    1411             :   /* 1803 */ 'H', '7', 0,
    1412             :   /* 1806 */ 'P', '7', 0,
    1413             :   /* 1809 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
    1414             :   /* 1821 */ 'S', '7', 0,
    1415             :   /* 1824 */ 'W', '6', '_', 'W', '7', 0,
    1416             :   /* 1830 */ 'X', '6', '_', 'X', '7', 0,
    1417             :   /* 1836 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0,
    1418             :   /* 1848 */ 'B', '1', '8', 0,
    1419             :   /* 1852 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
    1420             :   /* 1868 */ 'H', '1', '8', 0,
    1421             :   /* 1872 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
    1422             :   /* 1888 */ 'S', '1', '8', 0,
    1423             :   /* 1892 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
    1424             :   /* 1900 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
    1425             :   /* 1908 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0,
    1426             :   /* 1924 */ 'B', '2', '8', 0,
    1427             :   /* 1928 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
    1428             :   /* 1944 */ 'H', '2', '8', 0,
    1429             :   /* 1948 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
    1430             :   /* 1964 */ 'S', '2', '8', 0,
    1431             :   /* 1968 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
    1432             :   /* 1976 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
    1433             :   /* 1984 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0,
    1434             :   /* 2000 */ 'B', '8', 0,
    1435             :   /* 2003 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
    1436             :   /* 2015 */ 'H', '8', 0,
    1437             :   /* 2018 */ 'P', '8', 0,
    1438             :   /* 2021 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
    1439             :   /* 2033 */ 'S', '8', 0,
    1440             :   /* 2036 */ 'W', '7', '_', 'W', '8', 0,
    1441             :   /* 2042 */ 'X', '7', '_', 'X', '8', 0,
    1442             :   /* 2048 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0,
    1443             :   /* 2060 */ 'B', '1', '9', 0,
    1444             :   /* 2064 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
    1445             :   /* 2080 */ 'H', '1', '9', 0,
    1446             :   /* 2084 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
    1447             :   /* 2100 */ 'S', '1', '9', 0,
    1448             :   /* 2104 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
    1449             :   /* 2112 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
    1450             :   /* 2120 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0,
    1451             :   /* 2136 */ 'B', '2', '9', 0,
    1452             :   /* 2140 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
    1453             :   /* 2156 */ 'H', '2', '9', 0,
    1454             :   /* 2160 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
    1455             :   /* 2176 */ 'S', '2', '9', 0,
    1456             :   /* 2180 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
    1457             :   /* 2188 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0,
    1458             :   /* 2204 */ 'B', '9', 0,
    1459             :   /* 2207 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
    1460             :   /* 2219 */ 'H', '9', 0,
    1461             :   /* 2222 */ 'P', '9', 0,
    1462             :   /* 2225 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
    1463             :   /* 2237 */ 'S', '9', 0,
    1464             :   /* 2240 */ 'W', '8', '_', 'W', '9', 0,
    1465             :   /* 2246 */ 'X', '8', '_', 'X', '9', 0,
    1466             :   /* 2252 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0,
    1467             :   /* 2264 */ 'Z', '1', '0', '_', 'H', 'I', 0,
    1468             :   /* 2271 */ 'Z', '2', '0', '_', 'H', 'I', 0,
    1469             :   /* 2278 */ 'Z', '3', '0', '_', 'H', 'I', 0,
    1470             :   /* 2285 */ 'Z', '0', '_', 'H', 'I', 0,
    1471             :   /* 2291 */ 'Z', '1', '1', '_', 'H', 'I', 0,
    1472             :   /* 2298 */ 'Z', '2', '1', '_', 'H', 'I', 0,
    1473             :   /* 2305 */ 'Z', '3', '1', '_', 'H', 'I', 0,
    1474             :   /* 2312 */ 'Z', '1', '_', 'H', 'I', 0,
    1475             :   /* 2318 */ 'Z', '1', '2', '_', 'H', 'I', 0,
    1476             :   /* 2325 */ 'Z', '2', '2', '_', 'H', 'I', 0,
    1477             :   /* 2332 */ 'Z', '2', '_', 'H', 'I', 0,
    1478             :   /* 2338 */ 'Z', '1', '3', '_', 'H', 'I', 0,
    1479             :   /* 2345 */ 'Z', '2', '3', '_', 'H', 'I', 0,
    1480             :   /* 2352 */ 'Z', '3', '_', 'H', 'I', 0,
    1481             :   /* 2358 */ 'Z', '1', '4', '_', 'H', 'I', 0,
    1482             :   /* 2365 */ 'Z', '2', '4', '_', 'H', 'I', 0,
    1483             :   /* 2372 */ 'Z', '4', '_', 'H', 'I', 0,
    1484             :   /* 2378 */ 'Z', '1', '5', '_', 'H', 'I', 0,
    1485             :   /* 2385 */ 'Z', '2', '5', '_', 'H', 'I', 0,
    1486             :   /* 2392 */ 'Z', '5', '_', 'H', 'I', 0,
    1487             :   /* 2398 */ 'Z', '1', '6', '_', 'H', 'I', 0,
    1488             :   /* 2405 */ 'Z', '2', '6', '_', 'H', 'I', 0,
    1489             :   /* 2412 */ 'Z', '6', '_', 'H', 'I', 0,
    1490             :   /* 2418 */ 'Z', '1', '7', '_', 'H', 'I', 0,
    1491             :   /* 2425 */ 'Z', '2', '7', '_', 'H', 'I', 0,
    1492             :   /* 2432 */ 'Z', '7', '_', 'H', 'I', 0,
    1493             :   /* 2438 */ 'Z', '1', '8', '_', 'H', 'I', 0,
    1494             :   /* 2445 */ 'Z', '2', '8', '_', 'H', 'I', 0,
    1495             :   /* 2452 */ 'Z', '8', '_', 'H', 'I', 0,
    1496             :   /* 2458 */ 'Z', '1', '9', '_', 'H', 'I', 0,
    1497             :   /* 2465 */ 'Z', '2', '9', '_', 'H', 'I', 0,
    1498             :   /* 2472 */ 'Z', '9', '_', 'H', 'I', 0,
    1499             :   /* 2478 */ 'X', '2', '8', '_', 'F', 'P', 0,
    1500             :   /* 2485 */ 'W', 'S', 'P', 0,
    1501             :   /* 2489 */ 'F', 'F', 'R', 0,
    1502             :   /* 2493 */ 'F', 'P', '_', 'L', 'R', 0,
    1503             :   /* 2499 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
    1504             :   /* 2507 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
    1505             :   /* 2514 */ 'N', 'Z', 'C', 'V', 0,
    1506             : };
    1507             : 
    1508             : extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
    1509             :   { 3, 0, 0, 0, 0, 0 },
    1510             :   { 2489, 8, 8, 4, 20465, 0 },
    1511             :   { 2482, 878, 405, 5, 20465, 27 },
    1512             :   { 2496, 878, 132, 5, 20465, 27 },
    1513             :   { 2514, 8, 8, 4, 20465, 0 },
    1514             :   { 2486, 7, 8, 5, 6576, 27 },
    1515             :   { 2485, 8, 1279, 4, 6576, 0 },
    1516             :   { 2503, 8, 79, 4, 6608, 0 },
    1517             :   { 2510, 1279, 129, 5, 6608, 27 },
    1518             :   { 213, 8, 214, 4, 20433, 0 },
    1519             :   { 494, 8, 296, 4, 20433, 0 },
    1520             :   { 713, 8, 438, 4, 20433, 0 },
    1521             :   { 932, 8, 150, 4, 20433, 0 },
    1522             :   { 1148, 8, 150, 4, 20433, 0 },
    1523             :   { 1364, 8, 150, 4, 20433, 0 },
    1524             :   { 1576, 8, 150, 4, 20433, 0 },
    1525             :   { 1788, 8, 150, 4, 20433, 0 },
    1526             :   { 2000, 8, 150, 4, 20433, 0 },
    1527             :   { 2204, 8, 150, 4, 20433, 0 },
    1528             :   { 0, 8, 150, 4, 20433, 0 },
    1529             :   { 284, 8, 150, 4, 20433, 0 },
    1530             :   { 560, 8, 150, 4, 20433, 0 },
    1531             :   { 776, 8, 150, 4, 20433, 0 },
    1532             :   { 992, 8, 150, 4, 20433, 0 },
    1533             :   { 1208, 8, 150, 4, 20433, 0 },
    1534             :   { 1424, 8, 150, 4, 20433, 0 },
    1535             :   { 1636, 8, 150, 4, 20433, 0 },
    1536             :   { 1848, 8, 150, 4, 20433, 0 },
    1537             :   { 2060, 8, 150, 4, 20433, 0 },
    1538             :   { 69, 8, 150, 4, 20433, 0 },
    1539             :   { 358, 8, 150, 4, 20433, 0 },
    1540             :   { 637, 8, 150, 4, 20433, 0 },
    1541             :   { 856, 8, 150, 4, 20433, 0 },
    1542             :   { 1072, 8, 150, 4, 20433, 0 },
    1543             :   { 1288, 8, 150, 4, 20433, 0 },
    1544             :   { 1500, 8, 150, 4, 20433, 0 },
    1545             :   { 1712, 8, 150, 4, 20433, 0 },
    1546             :   { 1924, 8, 150, 4, 20433, 0 },
    1547             :   { 2136, 8, 150, 4, 20433, 0 },
    1548             :   { 145, 8, 150, 4, 20433, 0 },
    1549             :   { 434, 8, 150, 4, 20433, 0 },
    1550             :   { 228, 1080, 217, 1, 20161, 3 },
    1551             :   { 508, 1080, 299, 1, 20161, 3 },
    1552             :   { 726, 1080, 441, 1, 20161, 3 },
    1553             :   { 944, 1080, 153, 1, 20161, 3 },
    1554             :   { 1160, 1080, 153, 1, 20161, 3 },
    1555             :   { 1376, 1080, 153, 1, 20161, 3 },
    1556             :   { 1588, 1080, 153, 1, 20161, 3 },
    1557             :   { 1800, 1080, 153, 1, 20161, 3 },
    1558             :   { 2012, 1080, 153, 1, 20161, 3 },
    1559             :   { 2216, 1080, 153, 1, 20161, 3 },
    1560             :   { 13, 1080, 153, 1, 20161, 3 },
    1561             :   { 298, 1080, 153, 1, 20161, 3 },
    1562             :   { 575, 1080, 153, 1, 20161, 3 },
    1563             :   { 792, 1080, 153, 1, 20161, 3 },
    1564             :   { 1008, 1080, 153, 1, 20161, 3 },
    1565             :   { 1224, 1080, 153, 1, 20161, 3 },
    1566             :   { 1440, 1080, 153, 1, 20161, 3 },
    1567             :   { 1652, 1080, 153, 1, 20161, 3 },
    1568             :   { 1864, 1080, 153, 1, 20161, 3 },
    1569             :   { 2076, 1080, 153, 1, 20161, 3 },
    1570             :   { 85, 1080, 153, 1, 20161, 3 },
    1571             :   { 374, 1080, 153, 1, 20161, 3 },
    1572             :   { 653, 1080, 153, 1, 20161, 3 },
    1573             :   { 872, 1080, 153, 1, 20161, 3 },
    1574             :   { 1088, 1080, 153, 1, 20161, 3 },
    1575             :   { 1304, 1080, 153, 1, 20161, 3 },
    1576             :   { 1516, 1080, 153, 1, 20161, 3 },
    1577             :   { 1728, 1080, 153, 1, 20161, 3 },
    1578             :   { 1940, 1080, 153, 1, 20161, 3 },
    1579             :   { 2152, 1080, 153, 1, 20161, 3 },
    1580             :   { 161, 1080, 153, 1, 20161, 3 },
    1581             :   { 450, 1080, 153, 1, 20161, 3 },
    1582             :   { 231, 1082, 215, 3, 17169, 3 },
    1583             :   { 511, 1082, 297, 3, 17169, 3 },
    1584             :   { 729, 1082, 439, 3, 17169, 3 },
    1585             :   { 947, 1082, 151, 3, 17169, 3 },
    1586             :   { 1163, 1082, 151, 3, 17169, 3 },
    1587             :   { 1379, 1082, 151, 3, 17169, 3 },
    1588             :   { 1591, 1082, 151, 3, 17169, 3 },
    1589             :   { 1803, 1082, 151, 3, 17169, 3 },
    1590             :   { 2015, 1082, 151, 3, 17169, 3 },
    1591             :   { 2219, 1082, 151, 3, 17169, 3 },
    1592             :   { 17, 1082, 151, 3, 17169, 3 },
    1593             :   { 302, 1082, 151, 3, 17169, 3 },
    1594             :   { 579, 1082, 151, 3, 17169, 3 },
    1595             :   { 796, 1082, 151, 3, 17169, 3 },
    1596             :   { 1012, 1082, 151, 3, 17169, 3 },
    1597             :   { 1228, 1082, 151, 3, 17169, 3 },
    1598             :   { 1444, 1082, 151, 3, 17169, 3 },
    1599             :   { 1656, 1082, 151, 3, 17169, 3 },
    1600             :   { 1868, 1082, 151, 3, 17169, 3 },
    1601             :   { 2080, 1082, 151, 3, 17169, 3 },
    1602             :   { 89, 1082, 151, 3, 17169, 3 },
    1603             :   { 378, 1082, 151, 3, 17169, 3 },
    1604             :   { 657, 1082, 151, 3, 17169, 3 },
    1605             :   { 876, 1082, 151, 3, 17169, 3 },
    1606             :   { 1092, 1082, 151, 3, 17169, 3 },
    1607             :   { 1308, 1082, 151, 3, 17169, 3 },
    1608             :   { 1520, 1082, 151, 3, 17169, 3 },
    1609             :   { 1732, 1082, 151, 3, 17169, 3 },
    1610             :   { 1944, 1082, 151, 3, 17169, 3 },
    1611             :   { 2156, 1082, 151, 3, 17169, 3 },
    1612             :   { 165, 1082, 151, 3, 17169, 3 },
    1613             :   { 454, 1082, 151, 3, 17169, 3 },
    1614             :   { 234, 8, 8, 4, 17169, 0 },
    1615             :   { 514, 8, 8, 4, 17169, 0 },
    1616             :   { 732, 8, 8, 4, 17169, 0 },
    1617             :   { 950, 8, 8, 4, 17169, 0 },
    1618             :   { 1166, 8, 8, 4, 17169, 0 },
    1619             :   { 1382, 8, 8, 4, 17169, 0 },
    1620             :   { 1594, 8, 8, 4, 17169, 0 },
    1621             :   { 1806, 8, 8, 4, 17169, 0 },
    1622             :   { 2018, 8, 8, 4, 17169, 0 },
    1623             :   { 2222, 8, 8, 4, 17169, 0 },
    1624             :   { 21, 8, 8, 4, 17169, 0 },
    1625             :   { 306, 8, 8, 4, 17169, 0 },
    1626             :   { 583, 8, 8, 4, 17169, 0 },
    1627             :   { 800, 8, 8, 4, 17169, 0 },
    1628             :   { 1016, 8, 8, 4, 17169, 0 },
    1629             :   { 1232, 8, 8, 4, 17169, 0 },
    1630             :   { 249, 1093, 247, 0, 15265, 3 },
    1631             :   { 528, 1093, 329, 0, 15265, 3 },
    1632             :   { 745, 1093, 471, 0, 15265, 3 },
    1633             :   { 962, 1093, 183, 0, 15265, 3 },
    1634             :   { 1178, 1093, 183, 0, 15265, 3 },
    1635             :   { 1394, 1093, 183, 0, 15265, 3 },
    1636             :   { 1606, 1093, 183, 0, 15265, 3 },
    1637             :   { 1818, 1093, 183, 0, 15265, 3 },
    1638             :   { 2030, 1093, 183, 0, 15265, 3 },
    1639             :   { 2234, 1093, 183, 0, 15265, 3 },
    1640             :   { 34, 1093, 183, 0, 15265, 3 },
    1641             :   { 320, 1093, 183, 0, 15265, 3 },
    1642             :   { 598, 1093, 183, 0, 15265, 3 },
    1643             :   { 816, 1093, 183, 0, 15265, 3 },
    1644             :   { 1032, 1093, 183, 0, 15265, 3 },
    1645             :   { 1248, 1093, 183, 0, 15265, 3 },
    1646             :   { 1460, 1093, 183, 0, 15265, 3 },
    1647             :   { 1672, 1093, 183, 0, 15265, 3 },
    1648             :   { 1884, 1093, 183, 0, 15265, 3 },
    1649             :   { 2096, 1093, 183, 0, 15265, 3 },
    1650             :   { 105, 1093, 183, 0, 15265, 3 },
    1651             :   { 394, 1093, 183, 0, 15265, 3 },
    1652             :   { 673, 1093, 183, 0, 15265, 3 },
    1653             :   { 892, 1093, 183, 0, 15265, 3 },
    1654             :   { 1108, 1093, 183, 0, 15265, 3 },
    1655             :   { 1324, 1093, 183, 0, 15265, 3 },
    1656             :   { 1536, 1093, 183, 0, 15265, 3 },
    1657             :   { 1748, 1093, 183, 0, 15265, 3 },
    1658             :   { 1960, 1093, 183, 0, 15265, 3 },
    1659             :   { 2172, 1093, 183, 0, 15265, 3 },
    1660             :   { 181, 1093, 183, 0, 15265, 3 },
    1661             :   { 470, 1093, 183, 0, 15265, 3 },
    1662             :   { 252, 1081, 216, 2, 15201, 3 },
    1663             :   { 531, 1081, 298, 2, 15201, 3 },
    1664             :   { 748, 1081, 440, 2, 15201, 3 },
    1665             :   { 965, 1081, 152, 2, 15201, 3 },
    1666             :   { 1181, 1081, 152, 2, 15201, 3 },
    1667             :   { 1397, 1081, 152, 2, 15201, 3 },
    1668             :   { 1609, 1081, 152, 2, 15201, 3 },
    1669             :   { 1821, 1081, 152, 2, 15201, 3 },
    1670             :   { 2033, 1081, 152, 2, 15201, 3 },
    1671             :   { 2237, 1081, 152, 2, 15201, 3 },
    1672             :   { 38, 1081, 152, 2, 15201, 3 },
    1673             :   { 324, 1081, 152, 2, 15201, 3 },
    1674             :   { 602, 1081, 152, 2, 15201, 3 },
    1675             :   { 820, 1081, 152, 2, 15201, 3 },
    1676             :   { 1036, 1081, 152, 2, 15201, 3 },
    1677             :   { 1252, 1081, 152, 2, 15201, 3 },
    1678             :   { 1464, 1081, 152, 2, 15201, 3 },
    1679             :   { 1676, 1081, 152, 2, 15201, 3 },
    1680             :   { 1888, 1081, 152, 2, 15201, 3 },
    1681             :   { 2100, 1081, 152, 2, 15201, 3 },
    1682             :   { 109, 1081, 152, 2, 15201, 3 },
    1683             :   { 398, 1081, 152, 2, 15201, 3 },
    1684             :   { 677, 1081, 152, 2, 15201, 3 },
    1685             :   { 896, 1081, 152, 2, 15201, 3 },
    1686             :   { 1112, 1081, 152, 2, 15201, 3 },
    1687             :   { 1328, 1081, 152, 2, 15201, 3 },
    1688             :   { 1540, 1081, 152, 2, 15201, 3 },
    1689             :   { 1752, 1081, 152, 2, 15201, 3 },
    1690             :   { 1964, 1081, 152, 2, 15201, 3 },
    1691             :   { 2176, 1081, 152, 2, 15201, 3 },
    1692             :   { 185, 1081, 152, 2, 15201, 3 },
    1693             :   { 474, 1081, 152, 2, 15201, 3 },
    1694             :   { 259, 8, 387, 4, 15233, 0 },
    1695             :   { 537, 8, 85, 4, 15233, 0 },
    1696             :   { 754, 8, 85, 4, 15233, 0 },
    1697             :   { 971, 8, 85, 4, 15233, 0 },
    1698             :   { 1187, 8, 85, 4, 15233, 0 },
    1699             :   { 1403, 8, 85, 4, 15233, 0 },
    1700             :   { 1615, 8, 85, 4, 15233, 0 },
    1701             :   { 1827, 8, 85, 4, 15233, 0 },
    1702             :   { 2039, 8, 85, 4, 15233, 0 },
    1703             :   { 2243, 8, 85, 4, 15233, 0 },
    1704             :   { 45, 8, 85, 4, 15233, 0 },
    1705             :   { 332, 8, 85, 4, 15233, 0 },
    1706             :   { 610, 8, 85, 4, 15233, 0 },
    1707             :   { 828, 8, 85, 4, 15233, 0 },
    1708             :   { 1044, 8, 85, 4, 15233, 0 },
    1709             :   { 1260, 8, 85, 4, 15233, 0 },
    1710             :   { 1472, 8, 85, 4, 15233, 0 },
    1711             :   { 1684, 8, 85, 4, 15233, 0 },
    1712             :   { 1896, 8, 85, 4, 15233, 0 },
    1713             :   { 2108, 8, 85, 4, 15233, 0 },
    1714             :   { 117, 8, 85, 4, 15233, 0 },
    1715             :   { 406, 8, 85, 4, 15233, 0 },
    1716             :   { 685, 8, 85, 4, 15233, 0 },
    1717             :   { 904, 8, 85, 4, 15233, 0 },
    1718             :   { 1120, 8, 85, 4, 15233, 0 },
    1719             :   { 1336, 8, 85, 4, 15233, 0 },
    1720             :   { 1548, 8, 85, 4, 15233, 0 },
    1721             :   { 1760, 8, 85, 4, 15233, 0 },
    1722             :   { 1972, 8, 415, 4, 15233, 0 },
    1723             :   { 2184, 8, 396, 4, 15057, 0 },
    1724             :   { 193, 8, 33, 4, 15057, 0 },
    1725             :   { 266, 1275, 393, 5, 15169, 27 },
    1726             :   { 543, 1275, 111, 5, 15169, 27 },
    1727             :   { 760, 1275, 111, 5, 15169, 27 },
    1728             :   { 977, 1275, 111, 5, 15169, 27 },
    1729             :   { 1193, 1275, 111, 5, 15169, 27 },
    1730             :   { 1409, 1275, 111, 5, 15169, 27 },
    1731             :   { 1621, 1275, 111, 5, 15169, 27 },
    1732             :   { 1833, 1275, 111, 5, 15169, 27 },
    1733             :   { 2045, 1275, 111, 5, 15169, 27 },
    1734             :   { 2249, 1275, 111, 5, 15169, 27 },
    1735             :   { 52, 1275, 111, 5, 15169, 27 },
    1736             :   { 340, 1275, 111, 5, 15169, 27 },
    1737             :   { 618, 1275, 111, 5, 15169, 27 },
    1738             :   { 836, 1275, 111, 5, 15169, 27 },
    1739             :   { 1052, 1275, 111, 5, 15169, 27 },
    1740             :   { 1268, 1275, 111, 5, 15169, 27 },
    1741             :   { 1480, 1275, 111, 5, 15169, 27 },
    1742             :   { 1692, 1275, 111, 5, 15169, 27 },
    1743             :   { 1904, 1275, 111, 5, 15169, 27 },
    1744             :   { 2116, 1275, 111, 5, 15169, 27 },
    1745             :   { 125, 1275, 111, 5, 15169, 27 },
    1746             :   { 414, 1275, 111, 5, 15169, 27 },
    1747             :   { 693, 1275, 111, 5, 15169, 27 },
    1748             :   { 912, 1275, 111, 5, 15169, 27 },
    1749             :   { 1128, 1275, 111, 5, 15169, 27 },
    1750             :   { 1344, 1275, 111, 5, 15169, 27 },
    1751             :   { 1556, 1275, 111, 5, 15169, 27 },
    1752             :   { 1768, 1275, 111, 5, 15169, 27 },
    1753             :   { 1980, 1275, 421, 5, 15169, 27 },
    1754             :   { 281, 880, 268, 10, 8929, 35 },
    1755             :   { 557, 880, 350, 10, 8929, 35 },
    1756             :   { 773, 880, 492, 10, 8929, 35 },
    1757             :   { 989, 880, 204, 10, 8929, 35 },
    1758             :   { 1205, 880, 204, 10, 8929, 35 },
    1759             :   { 1421, 880, 204, 10, 8929, 35 },
    1760             :   { 1633, 880, 204, 10, 8929, 35 },
    1761             :   { 1845, 880, 204, 10, 8929, 35 },
    1762             :   { 2057, 880, 204, 10, 8929, 35 },
    1763             :   { 2261, 880, 204, 10, 8929, 35 },
    1764             :   { 65, 880, 204, 10, 8929, 35 },
    1765             :   { 354, 880, 204, 10, 8929, 35 },
    1766             :   { 633, 880, 204, 10, 8929, 35 },
    1767             :   { 852, 880, 204, 10, 8929, 35 },
    1768             :   { 1068, 880, 204, 10, 8929, 35 },
    1769             :   { 1284, 880, 204, 10, 8929, 35 },
    1770             :   { 1496, 880, 204, 10, 8929, 35 },
    1771             :   { 1708, 880, 204, 10, 8929, 35 },
    1772             :   { 1920, 880, 204, 10, 8929, 35 },
    1773             :   { 2132, 880, 204, 10, 8929, 35 },
    1774             :   { 141, 880, 204, 10, 8929, 35 },
    1775             :   { 430, 880, 204, 10, 8929, 35 },
    1776             :   { 709, 880, 204, 10, 8929, 35 },
    1777             :   { 928, 880, 204, 10, 8929, 35 },
    1778             :   { 1144, 880, 204, 10, 8929, 35 },
    1779             :   { 1360, 880, 204, 10, 8929, 35 },
    1780             :   { 1572, 880, 204, 10, 8929, 35 },
    1781             :   { 1784, 880, 204, 10, 8929, 35 },
    1782             :   { 1996, 880, 204, 10, 8929, 35 },
    1783             :   { 2200, 880, 204, 10, 8929, 35 },
    1784             :   { 209, 880, 204, 10, 8929, 35 },
    1785             :   { 490, 880, 204, 10, 8929, 35 },
    1786             :   { 2285, 8, 267, 4, 15137, 0 },
    1787             :   { 2312, 8, 349, 4, 15137, 0 },
    1788             :   { 2332, 8, 491, 4, 15137, 0 },
    1789             :   { 2352, 8, 203, 4, 15137, 0 },
    1790             :   { 2372, 8, 203, 4, 15137, 0 },
    1791             :   { 2392, 8, 203, 4, 15137, 0 },
    1792             :   { 2412, 8, 203, 4, 15137, 0 },
    1793             :   { 2432, 8, 203, 4, 15137, 0 },
    1794             :   { 2452, 8, 203, 4, 15137, 0 },
    1795             :   { 2472, 8, 203, 4, 15137, 0 },
    1796             :   { 2264, 8, 203, 4, 15137, 0 },
    1797             :   { 2291, 8, 203, 4, 15137, 0 },
    1798             :   { 2318, 8, 203, 4, 15137, 0 },
    1799             :   { 2338, 8, 203, 4, 15137, 0 },
    1800             :   { 2358, 8, 203, 4, 15137, 0 },
    1801             :   { 2378, 8, 203, 4, 15137, 0 },
    1802             :   { 2398, 8, 203, 4, 15137, 0 },
    1803             :   { 2418, 8, 203, 4, 15137, 0 },
    1804             :   { 2438, 8, 203, 4, 15137, 0 },
    1805             :   { 2458, 8, 203, 4, 15137, 0 },
    1806             :   { 2271, 8, 203, 4, 15137, 0 },
    1807             :   { 2298, 8, 203, 4, 15137, 0 },
    1808             :   { 2325, 8, 203, 4, 15137, 0 },
    1809             :   { 2345, 8, 203, 4, 15137, 0 },
    1810             :   { 2365, 8, 203, 4, 15137, 0 },
    1811             :   { 2385, 8, 203, 4, 15137, 0 },
    1812             :   { 2405, 8, 203, 4, 15137, 0 },
    1813             :   { 2425, 8, 203, 4, 15137, 0 },
    1814             :   { 2445, 8, 203, 4, 15137, 0 },
    1815             :   { 2465, 8, 203, 4, 15137, 0 },
    1816             :   { 2278, 8, 203, 4, 15137, 0 },
    1817             :   { 2305, 8, 203, 4, 15137, 0 },
    1818             :   { 505, 1084, 360, 17, 2353, 61 },
    1819             :   { 723, 1084, 513, 17, 2353, 61 },
    1820             :   { 941, 1084, 278, 17, 2353, 61 },
    1821             :   { 1157, 1084, 278, 17, 2353, 61 },
    1822             :   { 1373, 1084, 278, 17, 2353, 61 },
    1823             :   { 1585, 1084, 278, 17, 2353, 61 },
    1824             :   { 1797, 1084, 278, 17, 2353, 61 },
    1825             :   { 2009, 1084, 278, 17, 2353, 61 },
    1826             :   { 2213, 1084, 278, 17, 2353, 61 },
    1827             :   { 10, 1084, 278, 17, 2353, 61 },
    1828             :   { 294, 1084, 278, 17, 2353, 61 },
    1829             :   { 571, 1084, 278, 17, 2353, 61 },
    1830             :   { 788, 1084, 278, 17, 2353, 61 },
    1831             :   { 1004, 1084, 278, 17, 2353, 61 },
    1832             :   { 1220, 1084, 278, 17, 2353, 61 },
    1833             :   { 1436, 1084, 278, 17, 2353, 61 },
    1834             :   { 1648, 1084, 278, 17, 2353, 61 },
    1835             :   { 1860, 1084, 278, 17, 2353, 61 },
    1836             :   { 2072, 1084, 278, 17, 2353, 61 },
    1837             :   { 81, 1084, 278, 17, 2353, 61 },
    1838             :   { 370, 1084, 278, 17, 2353, 61 },
    1839             :   { 649, 1084, 278, 17, 2353, 61 },
    1840             :   { 868, 1084, 278, 17, 2353, 61 },
    1841             :   { 1084, 1084, 278, 17, 2353, 61 },
    1842             :   { 1300, 1084, 278, 17, 2353, 61 },
    1843             :   { 1512, 1084, 278, 17, 2353, 61 },
    1844             :   { 1724, 1084, 278, 17, 2353, 61 },
    1845             :   { 1936, 1084, 278, 17, 2353, 61 },
    1846             :   { 2148, 1084, 278, 17, 2353, 61 },
    1847             :   { 157, 1084, 278, 17, 2353, 61 },
    1848             :   { 446, 1084, 278, 17, 2353, 61 },
    1849             :   { 224, 1075, 278, 17, 8496, 2 },
    1850             :   { 935, 1216, 872, 41, 225, 68 },
    1851             :   { 1151, 1216, 872, 41, 225, 68 },
    1852             :   { 1367, 1216, 872, 41, 225, 68 },
    1853             :   { 1579, 1216, 872, 41, 225, 68 },
    1854             :   { 1791, 1216, 872, 41, 225, 68 },
    1855             :   { 2003, 1216, 872, 41, 225, 68 },
    1856             :   { 2207, 1216, 872, 41, 225, 68 },
    1857             :   { 4, 1216, 872, 41, 225, 68 },
    1858             :   { 288, 1216, 872, 41, 225, 68 },
    1859             :   { 564, 1216, 872, 41, 225, 68 },
    1860             :   { 780, 1216, 872, 41, 225, 68 },
    1861             :   { 996, 1216, 872, 41, 225, 68 },
    1862             :   { 1212, 1216, 872, 41, 225, 68 },
    1863             :   { 1428, 1216, 872, 41, 225, 68 },
    1864             :   { 1640, 1216, 872, 41, 225, 68 },
    1865             :   { 1852, 1216, 872, 41, 225, 68 },
    1866             :   { 2064, 1216, 872, 41, 225, 68 },
    1867             :   { 73, 1216, 872, 41, 225, 68 },
    1868             :   { 362, 1216, 872, 41, 225, 68 },
    1869             :   { 641, 1216, 872, 41, 225, 68 },
    1870             :   { 860, 1216, 872, 41, 225, 68 },
    1871             :   { 1076, 1216, 872, 41, 225, 68 },
    1872             :   { 1292, 1216, 872, 41, 225, 68 },
    1873             :   { 1504, 1216, 872, 41, 225, 68 },
    1874             :   { 1716, 1216, 872, 41, 225, 68 },
    1875             :   { 1928, 1216, 872, 41, 225, 68 },
    1876             :   { 2140, 1216, 872, 41, 225, 68 },
    1877             :   { 149, 1216, 872, 41, 225, 68 },
    1878             :   { 438, 1216, 872, 41, 225, 68 },
    1879             :   { 216, 1238, 872, 41, 304, 73 },
    1880             :   { 497, 1051, 872, 41, 864, 59 },
    1881             :   { 716, 1194, 872, 41, 6784, 5 },
    1882             :   { 720, 96, 539, 26, 801, 74 },
    1883             :   { 938, 96, 378, 26, 801, 74 },
    1884             :   { 1154, 96, 378, 26, 801, 74 },
    1885             :   { 1370, 96, 378, 26, 801, 74 },
    1886             :   { 1582, 96, 378, 26, 801, 74 },
    1887             :   { 1794, 96, 378, 26, 801, 74 },
    1888             :   { 2006, 96, 378, 26, 801, 74 },
    1889             :   { 2210, 96, 378, 26, 801, 74 },
    1890             :   { 7, 96, 378, 26, 801, 74 },
    1891             :   { 291, 96, 378, 26, 801, 74 },
    1892             :   { 567, 96, 378, 26, 801, 74 },
    1893             :   { 784, 96, 378, 26, 801, 74 },
    1894             :   { 1000, 96, 378, 26, 801, 74 },
    1895             :   { 1216, 96, 378, 26, 801, 74 },
    1896             :   { 1432, 96, 378, 26, 801, 74 },
    1897             :   { 1644, 96, 378, 26, 801, 74 },
    1898             :   { 1856, 96, 378, 26, 801, 74 },
    1899             :   { 2068, 96, 378, 26, 801, 74 },
    1900             :   { 77, 96, 378, 26, 801, 74 },
    1901             :   { 366, 96, 378, 26, 801, 74 },
    1902             :   { 645, 96, 378, 26, 801, 74 },
    1903             :   { 864, 96, 378, 26, 801, 74 },
    1904             :   { 1080, 96, 378, 26, 801, 74 },
    1905             :   { 1296, 96, 378, 26, 801, 74 },
    1906             :   { 1508, 96, 378, 26, 801, 74 },
    1907             :   { 1720, 96, 378, 26, 801, 74 },
    1908             :   { 1932, 96, 378, 26, 801, 74 },
    1909             :   { 2144, 96, 378, 26, 801, 74 },
    1910             :   { 153, 96, 378, 26, 801, 74 },
    1911             :   { 442, 96, 378, 26, 801, 74 },
    1912             :   { 220, 114, 378, 26, 1088, 64 },
    1913             :   { 501, 1262, 378, 26, 8032, 10 },
    1914             :   { 525, 887, 366, 63, 2257, 80 },
    1915             :   { 742, 887, 519, 63, 2257, 80 },
    1916             :   { 959, 887, 284, 63, 2257, 80 },
    1917             :   { 1175, 887, 284, 63, 2257, 80 },
    1918             :   { 1391, 887, 284, 63, 2257, 80 },
    1919             :   { 1603, 887, 284, 63, 2257, 80 },
    1920             :   { 1815, 887, 284, 63, 2257, 80 },
    1921             :   { 2027, 887, 284, 63, 2257, 80 },
    1922             :   { 2231, 887, 284, 63, 2257, 80 },
    1923             :   { 31, 887, 284, 63, 2257, 80 },
    1924             :   { 316, 887, 284, 63, 2257, 80 },
    1925             :   { 594, 887, 284, 63, 2257, 80 },
    1926             :   { 812, 887, 284, 63, 2257, 80 },
    1927             :   { 1028, 887, 284, 63, 2257, 80 },
    1928             :   { 1244, 887, 284, 63, 2257, 80 },
    1929             :   { 1456, 887, 284, 63, 2257, 80 },
    1930             :   { 1668, 887, 284, 63, 2257, 80 },
    1931             :   { 1880, 887, 284, 63, 2257, 80 },
    1932             :   { 2092, 887, 284, 63, 2257, 80 },
    1933             :   { 101, 887, 284, 63, 2257, 80 },
    1934             :   { 390, 887, 284, 63, 2257, 80 },
    1935             :   { 669, 887, 284, 63, 2257, 80 },
    1936             :   { 888, 887, 284, 63, 2257, 80 },
    1937             :   { 1104, 887, 284, 63, 2257, 80 },
    1938             :   { 1320, 887, 284, 63, 2257, 80 },
    1939             :   { 1532, 887, 284, 63, 2257, 80 },
    1940             :   { 1744, 887, 284, 63, 2257, 80 },
    1941             :   { 1956, 887, 284, 63, 2257, 80 },
    1942             :   { 2168, 887, 284, 63, 2257, 80 },
    1943             :   { 177, 887, 284, 63, 2257, 80 },
    1944             :   { 466, 887, 284, 63, 2257, 80 },
    1945             :   { 245, 923, 284, 63, 8496, 14 },
    1946             :   { 953, 1130, 873, 96, 145, 87 },
    1947             :   { 1169, 1130, 873, 96, 145, 87 },
    1948             :   { 1385, 1130, 873, 96, 145, 87 },
    1949             :   { 1597, 1130, 873, 96, 145, 87 },
    1950             :   { 1809, 1130, 873, 96, 145, 87 },
    1951             :   { 2021, 1130, 873, 96, 145, 87 },
    1952             :   { 2225, 1130, 873, 96, 145, 87 },
    1953             :   { 25, 1130, 873, 96, 145, 87 },
    1954             :   { 310, 1130, 873, 96, 145, 87 },
    1955             :   { 587, 1130, 873, 96, 145, 87 },
    1956             :   { 804, 1130, 873, 96, 145, 87 },
    1957             :   { 1020, 1130, 873, 96, 145, 87 },
    1958             :   { 1236, 1130, 873, 96, 145, 87 },
    1959             :   { 1448, 1130, 873, 96, 145, 87 },
    1960             :   { 1660, 1130, 873, 96, 145, 87 },
    1961             :   { 1872, 1130, 873, 96, 145, 87 },
    1962             :   { 2084, 1130, 873, 96, 145, 87 },
    1963             :   { 93, 1130, 873, 96, 145, 87 },
    1964             :   { 382, 1130, 873, 96, 145, 87 },
    1965             :   { 661, 1130, 873, 96, 145, 87 },
    1966             :   { 880, 1130, 873, 96, 145, 87 },
    1967             :   { 1096, 1130, 873, 96, 145, 87 },
    1968             :   { 1312, 1130, 873, 96, 145, 87 },
    1969             :   { 1524, 1130, 873, 96, 145, 87 },
    1970             :   { 1736, 1130, 873, 96, 145, 87 },
    1971             :   { 1948, 1130, 873, 96, 145, 87 },
    1972             :   { 2160, 1130, 873, 96, 145, 87 },
    1973             :   { 169, 1130, 873, 96, 145, 87 },
    1974             :   { 458, 1130, 873, 96, 145, 87 },
    1975             :   { 237, 1162, 873, 96, 304, 92 },
    1976             :   { 517, 1019, 873, 96, 864, 78 },
    1977             :   { 735, 1098, 873, 96, 6784, 17 },
    1978             :   { 739, 956, 542, 75, 737, 93 },
    1979             :   { 956, 956, 381, 75, 737, 93 },
    1980             :   { 1172, 956, 381, 75, 737, 93 },
    1981             :   { 1388, 956, 381, 75, 737, 93 },
    1982             :   { 1600, 956, 381, 75, 737, 93 },
    1983             :   { 1812, 956, 381, 75, 737, 93 },
    1984             :   { 2024, 956, 381, 75, 737, 93 },
    1985             :   { 2228, 956, 381, 75, 737, 93 },
    1986             :   { 28, 956, 381, 75, 737, 93 },
    1987             :   { 313, 956, 381, 75, 737, 93 },
    1988             :   { 590, 956, 381, 75, 737, 93 },
    1989             :   { 808, 956, 381, 75, 737, 93 },
    1990             :   { 1024, 956, 381, 75, 737, 93 },
    1991             :   { 1240, 956, 381, 75, 737, 93 },
    1992             :   { 1452, 956, 381, 75, 737, 93 },
    1993             :   { 1664, 956, 381, 75, 737, 93 },
    1994             :   { 1876, 956, 381, 75, 737, 93 },
    1995             :   { 2088, 956, 381, 75, 737, 93 },
    1996             :   { 97, 956, 381, 75, 737, 93 },
    1997             :   { 386, 956, 381, 75, 737, 93 },
    1998             :   { 665, 956, 381, 75, 737, 93 },
    1999             :   { 884, 956, 381, 75, 737, 93 },
    2000             :   { 1100, 956, 381, 75, 737, 93 },
    2001             :   { 1316, 956, 381, 75, 737, 93 },
    2002             :   { 1528, 956, 381, 75, 737, 93 },
    2003             :   { 1740, 956, 381, 75, 737, 93 },
    2004             :   { 1952, 956, 381, 75, 737, 93 },
    2005             :   { 2164, 956, 381, 75, 737, 93 },
    2006             :   { 173, 956, 381, 75, 737, 93 },
    2007             :   { 462, 956, 381, 75, 737, 93 },
    2008             :   { 241, 977, 381, 75, 1088, 83 },
    2009             :   { 521, 998, 381, 75, 8032, 22 },
    2010             :   { 255, 875, 550, 7, 8832, 32 },
    2011             :   { 2499, 943, 548, 7, 6432, 32 },
    2012             :   { 534, 144, 550, 7, 2209, 32 },
    2013             :   { 751, 144, 550, 7, 2209, 32 },
    2014             :   { 968, 144, 550, 7, 2209, 32 },
    2015             :   { 1184, 144, 550, 7, 2209, 32 },
    2016             :   { 1400, 144, 550, 7, 2209, 32 },
    2017             :   { 1612, 144, 550, 7, 2209, 32 },
    2018             :   { 1824, 144, 550, 7, 2209, 32 },
    2019             :   { 2036, 144, 550, 7, 2209, 32 },
    2020             :   { 2240, 144, 550, 7, 2209, 32 },
    2021             :   { 42, 144, 550, 7, 2209, 32 },
    2022             :   { 328, 144, 550, 7, 2209, 32 },
    2023             :   { 606, 144, 550, 7, 2209, 32 },
    2024             :   { 824, 144, 550, 7, 2209, 32 },
    2025             :   { 1040, 144, 550, 7, 2209, 32 },
    2026             :   { 1256, 144, 550, 7, 2209, 32 },
    2027             :   { 1468, 144, 550, 7, 2209, 32 },
    2028             :   { 1680, 144, 550, 7, 2209, 32 },
    2029             :   { 1892, 144, 550, 7, 2209, 32 },
    2030             :   { 2104, 144, 550, 7, 2209, 32 },
    2031             :   { 113, 144, 550, 7, 2209, 32 },
    2032             :   { 402, 144, 550, 7, 2209, 32 },
    2033             :   { 681, 144, 550, 7, 2209, 32 },
    2034             :   { 900, 144, 550, 7, 2209, 32 },
    2035             :   { 1116, 144, 550, 7, 2209, 32 },
    2036             :   { 1332, 144, 550, 7, 2209, 32 },
    2037             :   { 1544, 144, 550, 7, 2209, 32 },
    2038             :   { 1756, 144, 550, 7, 2209, 32 },
    2039             :   { 1968, 144, 550, 7, 2209, 32 },
    2040             :   { 2180, 144, 413, 7, 8976, 29 },
    2041             :   { 189, 144, 7, 7, 96, 32 },
    2042             :   { 2493, 905, 8, 128, 96, 97 },
    2043             :   { 2507, 935, 8, 128, 6529, 97 },
    2044             :   { 262, 899, 8, 128, 8883, 97 },
    2045             :   { 2478, 911, 8, 128, 8976, 26 },
    2046             :   { 540, 917, 8, 128, 2161, 97 },
    2047             :   { 757, 917, 8, 128, 2161, 97 },
    2048             :   { 974, 917, 8, 128, 2161, 97 },
    2049             :   { 1190, 917, 8, 128, 2161, 97 },
    2050             :   { 1406, 917, 8, 128, 2161, 97 },
    2051             :   { 1618, 917, 8, 128, 2161, 97 },
    2052             :   { 1830, 917, 8, 128, 2161, 97 },
    2053             :   { 2042, 917, 8, 128, 2161, 97 },
    2054             :   { 2246, 917, 8, 128, 2161, 97 },
    2055             :   { 49, 917, 8, 128, 2161, 97 },
    2056             :   { 336, 917, 8, 128, 2161, 97 },
    2057             :   { 614, 917, 8, 128, 2161, 97 },
    2058             :   { 832, 917, 8, 128, 2161, 97 },
    2059             :   { 1048, 917, 8, 128, 2161, 97 },
    2060             :   { 1264, 917, 8, 128, 2161, 97 },
    2061             :   { 1476, 917, 8, 128, 2161, 97 },
    2062             :   { 1688, 917, 8, 128, 2161, 97 },
    2063             :   { 1900, 917, 8, 128, 2161, 97 },
    2064             :   { 2112, 917, 8, 128, 2161, 97 },
    2065             :   { 121, 917, 8, 128, 2161, 97 },
    2066             :   { 410, 917, 8, 128, 2161, 97 },
    2067             :   { 689, 917, 8, 128, 2161, 97 },
    2068             :   { 908, 917, 8, 128, 2161, 97 },
    2069             :   { 1124, 917, 8, 128, 2161, 97 },
    2070             :   { 1340, 917, 8, 128, 2161, 97 },
    2071             :   { 1552, 917, 8, 128, 2161, 97 },
    2072             :   { 1764, 917, 8, 128, 2161, 97 },
    2073             :   { 1976, 917, 8, 128, 2161, 97 },
    2074             :   { 554, 564, 372, 134, 1457, 100 },
    2075             :   { 770, 564, 525, 134, 1457, 100 },
    2076             :   { 986, 564, 290, 134, 1457, 100 },
    2077             :   { 1202, 564, 290, 134, 1457, 100 },
    2078             :   { 1418, 564, 290, 134, 1457, 100 },
    2079             :   { 1630, 564, 290, 134, 1457, 100 },
    2080             :   { 1842, 564, 290, 134, 1457, 100 },
    2081             :   { 2054, 564, 290, 134, 1457, 100 },
    2082             :   { 2258, 564, 290, 134, 1457, 100 },
    2083             :   { 62, 564, 290, 134, 1457, 100 },
    2084             :   { 350, 564, 290, 134, 1457, 100 },
    2085             :   { 629, 564, 290, 134, 1457, 100 },
    2086             :   { 848, 564, 290, 134, 1457, 100 },
    2087             :   { 1064, 564, 290, 134, 1457, 100 },
    2088             :   { 1280, 564, 290, 134, 1457, 100 },
    2089             :   { 1492, 564, 290, 134, 1457, 100 },
    2090             :   { 1704, 564, 290, 134, 1457, 100 },
    2091             :   { 1916, 564, 290, 134, 1457, 100 },
    2092             :   { 2128, 564, 290, 134, 1457, 100 },
    2093             :   { 137, 564, 290, 134, 1457, 100 },
    2094             :   { 426, 564, 290, 134, 1457, 100 },
    2095             :   { 705, 564, 290, 134, 1457, 100 },
    2096             :   { 924, 564, 290, 134, 1457, 100 },
    2097             :   { 1140, 564, 290, 134, 1457, 100 },
    2098             :   { 1356, 564, 290, 134, 1457, 100 },
    2099             :   { 1568, 564, 290, 134, 1457, 100 },
    2100             :   { 1780, 564, 290, 134, 1457, 100 },
    2101             :   { 1992, 564, 290, 134, 1457, 100 },
    2102             :   { 2196, 564, 290, 134, 1457, 100 },
    2103             :   { 205, 564, 290, 134, 1457, 100 },
    2104             :   { 486, 564, 290, 134, 1457, 100 },
    2105             :   { 277, 581, 290, 134, 8544, 38 },
    2106             :   { 980, 780, 8, 181, 1, 121 },
    2107             :   { 1196, 780, 8, 181, 1, 121 },
    2108             :   { 1412, 780, 8, 181, 1, 121 },
    2109             :   { 1624, 780, 8, 181, 1, 121 },
    2110             :   { 1836, 780, 8, 181, 1, 121 },
    2111             :   { 2048, 780, 8, 181, 1, 121 },
    2112             :   { 2252, 780, 8, 181, 1, 121 },
    2113             :   { 56, 780, 8, 181, 1, 121 },
    2114             :   { 344, 780, 8, 181, 1, 121 },
    2115             :   { 622, 780, 8, 181, 1, 121 },
    2116             :   { 840, 780, 8, 181, 1, 121 },
    2117             :   { 1056, 780, 8, 181, 1, 121 },
    2118             :   { 1272, 780, 8, 181, 1, 121 },
    2119             :   { 1484, 780, 8, 181, 1, 121 },
    2120             :   { 1696, 780, 8, 181, 1, 121 },
    2121             :   { 1908, 780, 8, 181, 1, 121 },
    2122             :   { 2120, 780, 8, 181, 1, 121 },
    2123             :   { 129, 780, 8, 181, 1, 121 },
    2124             :   { 418, 780, 8, 181, 1, 121 },
    2125             :   { 697, 780, 8, 181, 1, 121 },
    2126             :   { 916, 780, 8, 181, 1, 121 },
    2127             :   { 1132, 780, 8, 181, 1, 121 },
    2128             :   { 1348, 780, 8, 181, 1, 121 },
    2129             :   { 1560, 780, 8, 181, 1, 121 },
    2130             :   { 1772, 780, 8, 181, 1, 121 },
    2131             :   { 1984, 780, 8, 181, 1, 121 },
    2132             :   { 2188, 780, 8, 181, 1, 121 },
    2133             :   { 197, 780, 8, 181, 1, 121 },
    2134             :   { 478, 780, 8, 181, 1, 121 },
    2135             :   { 269, 826, 8, 181, 384, 130 },
    2136             :   { 546, 688, 8, 181, 944, 105 },
    2137             :   { 763, 734, 8, 181, 6864, 43 },
    2138             :   { 767, 598, 545, 151, 625, 139 },
    2139             :   { 983, 598, 180, 151, 625, 139 },
    2140             :   { 1199, 598, 180, 151, 625, 139 },
    2141             :   { 1415, 598, 180, 151, 625, 139 },
    2142             :   { 1627, 598, 180, 151, 625, 139 },
    2143             :   { 1839, 598, 180, 151, 625, 139 },
    2144             :   { 2051, 598, 180, 151, 625, 139 },
    2145             :   { 2255, 598, 180, 151, 625, 139 },
    2146             :   { 59, 598, 180, 151, 625, 139 },
    2147             :   { 347, 598, 180, 151, 625, 139 },
    2148             :   { 625, 598, 180, 151, 625, 139 },
    2149             :   { 844, 598, 180, 151, 625, 139 },
    2150             :   { 1060, 598, 180, 151, 625, 139 },
    2151             :   { 1276, 598, 180, 151, 625, 139 },
    2152             :   { 1488, 598, 180, 151, 625, 139 },
    2153             :   { 1700, 598, 180, 151, 625, 139 },
    2154             :   { 1912, 598, 180, 151, 625, 139 },
    2155             :   { 2124, 598, 180, 151, 625, 139 },
    2156             :   { 133, 598, 180, 151, 625, 139 },
    2157             :   { 422, 598, 180, 151, 625, 139 },
    2158             :   { 701, 598, 180, 151, 625, 139 },
    2159             :   { 920, 598, 180, 151, 625, 139 },
    2160             :   { 1136, 598, 180, 151, 625, 139 },
    2161             :   { 1352, 598, 180, 151, 625, 139 },
    2162             :   { 1564, 598, 180, 151, 625, 139 },
    2163             :   { 1776, 598, 180, 151, 625, 139 },
    2164             :   { 1988, 598, 180, 151, 625, 139 },
    2165             :   { 2192, 598, 180, 151, 625, 139 },
    2166             :   { 201, 598, 180, 151, 625, 139 },
    2167             :   { 482, 598, 180, 151, 625, 139 },
    2168             :   { 273, 628, 180, 151, 1152, 114 },
    2169             :   { 550, 658, 180, 151, 8096, 52 },
    2170             : };
    2171             : 
    2172             : extern const MCPhysReg AArch64RegUnitRoots[][2] = {
    2173             :   { AArch64::FFR },
    2174             :   { AArch64::W29 },
    2175             :   { AArch64::W30 },
    2176             :   { AArch64::NZCV },
    2177             :   { AArch64::WSP },
    2178             :   { AArch64::WZR },
    2179             :   { AArch64::B0 },
    2180             :   { AArch64::B1 },
    2181             :   { AArch64::B2 },
    2182             :   { AArch64::B3 },
    2183             :   { AArch64::B4 },
    2184             :   { AArch64::B5 },
    2185             :   { AArch64::B6 },
    2186             :   { AArch64::B7 },
    2187             :   { AArch64::B8 },
    2188             :   { AArch64::B9 },
    2189             :   { AArch64::B10 },
    2190             :   { AArch64::B11 },
    2191             :   { AArch64::B12 },
    2192             :   { AArch64::B13 },
    2193             :   { AArch64::B14 },
    2194             :   { AArch64::B15 },
    2195             :   { AArch64::B16 },
    2196             :   { AArch64::B17 },
    2197             :   { AArch64::B18 },
    2198             :   { AArch64::B19 },
    2199             :   { AArch64::B20 },
    2200             :   { AArch64::B21 },
    2201             :   { AArch64::B22 },
    2202             :   { AArch64::B23 },
    2203             :   { AArch64::B24 },
    2204             :   { AArch64::B25 },
    2205             :   { AArch64::B26 },
    2206             :   { AArch64::B27 },
    2207             :   { AArch64::B28 },
    2208             :   { AArch64::B29 },
    2209             :   { AArch64::B30 },
    2210             :   { AArch64::B31 },
    2211             :   { AArch64::P0 },
    2212             :   { AArch64::P1 },
    2213             :   { AArch64::P2 },
    2214             :   { AArch64::P3 },
    2215             :   { AArch64::P4 },
    2216             :   { AArch64::P5 },
    2217             :   { AArch64::P6 },
    2218             :   { AArch64::P7 },
    2219             :   { AArch64::P8 },
    2220             :   { AArch64::P9 },
    2221             :   { AArch64::P10 },
    2222             :   { AArch64::P11 },
    2223             :   { AArch64::P12 },
    2224             :   { AArch64::P13 },
    2225             :   { AArch64::P14 },
    2226             :   { AArch64::P15 },
    2227             :   { AArch64::W0 },
    2228             :   { AArch64::W1 },
    2229             :   { AArch64::W2 },
    2230             :   { AArch64::W3 },
    2231             :   { AArch64::W4 },
    2232             :   { AArch64::W5 },
    2233             :   { AArch64::W6 },
    2234             :   { AArch64::W7 },
    2235             :   { AArch64::W8 },
    2236             :   { AArch64::W9 },
    2237             :   { AArch64::W10 },
    2238             :   { AArch64::W11 },
    2239             :   { AArch64::W12 },
    2240             :   { AArch64::W13 },
    2241             :   { AArch64::W14 },
    2242             :   { AArch64::W15 },
    2243             :   { AArch64::W16 },
    2244             :   { AArch64::W17 },
    2245             :   { AArch64::W18 },
    2246             :   { AArch64::W19 },
    2247             :   { AArch64::W20 },
    2248             :   { AArch64::W21 },
    2249             :   { AArch64::W22 },
    2250             :   { AArch64::W23 },
    2251             :   { AArch64::W24 },
    2252             :   { AArch64::W25 },
    2253             :   { AArch64::W26 },
    2254             :   { AArch64::W27 },
    2255             :   { AArch64::W28 },
    2256             :   { AArch64::Z0_HI },
    2257             :   { AArch64::Z1_HI },
    2258             :   { AArch64::Z2_HI },
    2259             :   { AArch64::Z3_HI },
    2260             :   { AArch64::Z4_HI },
    2261             :   { AArch64::Z5_HI },
    2262             :   { AArch64::Z6_HI },
    2263             :   { AArch64::Z7_HI },
    2264             :   { AArch64::Z8_HI },
    2265             :   { AArch64::Z9_HI },
    2266             :   { AArch64::Z10_HI },
    2267             :   { AArch64::Z11_HI },
    2268             :   { AArch64::Z12_HI },
    2269             :   { AArch64::Z13_HI },
    2270             :   { AArch64::Z14_HI },
    2271             :   { AArch64::Z15_HI },
    2272             :   { AArch64::Z16_HI },
    2273             :   { AArch64::Z17_HI },
    2274             :   { AArch64::Z18_HI },
    2275             :   { AArch64::Z19_HI },
    2276             :   { AArch64::Z20_HI },
    2277             :   { AArch64::Z21_HI },
    2278             :   { AArch64::Z22_HI },
    2279             :   { AArch64::Z23_HI },
    2280             :   { AArch64::Z24_HI },
    2281             :   { AArch64::Z25_HI },
    2282             :   { AArch64::Z26_HI },
    2283             :   { AArch64::Z27_HI },
    2284             :   { AArch64::Z28_HI },
    2285             :   { AArch64::Z29_HI },
    2286             :   { AArch64::Z30_HI },
    2287             :   { AArch64::Z31_HI },
    2288             : };
    2289             : 
    2290             : namespace {     // Register classes...
    2291             :   // FPR8 Register Class...
    2292             :   const MCPhysReg FPR8[] = {
    2293             :     AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, 
    2294             :   };
    2295             : 
    2296             :   // FPR8 Bit set.
    2297             :   const uint8_t FPR8Bits[] = {
    2298             :     0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2299             :   };
    2300             : 
    2301             :   // FPR16 Register Class...
    2302             :   const MCPhysReg FPR16[] = {
    2303             :     AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, 
    2304             :   };
    2305             : 
    2306             :   // FPR16 Bit set.
    2307             :   const uint8_t FPR16Bits[] = {
    2308             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2309             :   };
    2310             : 
    2311             :   // PPR Register Class...
    2312             :   const MCPhysReg PPR[] = {
    2313             :     AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, 
    2314             :   };
    2315             : 
    2316             :   // PPR Bit set.
    2317             :   const uint8_t PPRBits[] = {
    2318             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
    2319             :   };
    2320             : 
    2321             :   // PPR_3b Register Class...
    2322             :   const MCPhysReg PPR_3b[] = {
    2323             :     AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 
    2324             :   };
    2325             : 
    2326             :   // PPR_3b Bit set.
    2327             :   const uint8_t PPR_3bBits[] = {
    2328             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
    2329             :   };
    2330             : 
    2331             :   // GPR32all Register Class...
    2332             :   const MCPhysReg GPR32all[] = {
    2333             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, 
    2334             :   };
    2335             : 
    2336             :   // GPR32all Bit set.
    2337             :   const uint8_t GPR32allBits[] = {
    2338             :     0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
    2339             :   };
    2340             : 
    2341             :   // FPR32 Register Class...
    2342             :   const MCPhysReg FPR32[] = {
    2343             :     AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, 
    2344             :   };
    2345             : 
    2346             :   // FPR32 Bit set.
    2347             :   const uint8_t FPR32Bits[] = {
    2348             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2349             :   };
    2350             : 
    2351             :   // GPR32 Register Class...
    2352             :   const MCPhysReg GPR32[] = {
    2353             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, 
    2354             :   };
    2355             : 
    2356             :   // GPR32 Bit set.
    2357             :   const uint8_t GPR32Bits[] = {
    2358             :     0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
    2359             :   };
    2360             : 
    2361             :   // GPR32sp Register Class...
    2362             :   const MCPhysReg GPR32sp[] = {
    2363             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, 
    2364             :   };
    2365             : 
    2366             :   // GPR32sp Bit set.
    2367             :   const uint8_t GPR32spBits[] = {
    2368             :     0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
    2369             :   };
    2370             : 
    2371             :   // GPR32common Register Class...
    2372             :   const MCPhysReg GPR32common[] = {
    2373             :     AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, 
    2374             :   };
    2375             : 
    2376             :   // GPR32common Bit set.
    2377             :   const uint8_t GPR32commonBits[] = {
    2378             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
    2379             :   };
    2380             : 
    2381             :   // CCR Register Class...
    2382             :   const MCPhysReg CCR[] = {
    2383             :     AArch64::NZCV, 
    2384             :   };
    2385             : 
    2386             :   // CCR Bit set.
    2387             :   const uint8_t CCRBits[] = {
    2388             :     0x10, 
    2389             :   };
    2390             : 
    2391             :   // GPR32sponly Register Class...
    2392             :   const MCPhysReg GPR32sponly[] = {
    2393             :     AArch64::WSP, 
    2394             :   };
    2395             : 
    2396             :   // GPR32sponly Bit set.
    2397             :   const uint8_t GPR32sponlyBits[] = {
    2398             :     0x40, 
    2399             :   };
    2400             : 
    2401             :   // WSeqPairsClass Register Class...
    2402             :   const MCPhysReg WSeqPairsClass[] = {
    2403             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, AArch64::WZR_W0, 
    2404             :   };
    2405             : 
    2406             :   // WSeqPairsClass Bit set.
    2407             :   const uint8_t WSeqPairsClassBits[] = {
    2408             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2409             :   };
    2410             : 
    2411             :   // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
    2412             :   const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
    2413             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, 
    2414             :   };
    2415             : 
    2416             :   // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
    2417             :   const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
    2418             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 
    2419             :   };
    2420             : 
    2421             :   // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
    2422             :   const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
    2423             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::WZR_W0, 
    2424             :   };
    2425             : 
    2426             :   // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
    2427             :   const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    2428             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, 
    2429             :   };
    2430             : 
    2431             :   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
    2432             :   const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
    2433             :     AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, 
    2434             :   };
    2435             : 
    2436             :   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
    2437             :   const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    2438             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
    2439             :   };
    2440             : 
    2441             :   // GPR64all Register Class...
    2442             :   const MCPhysReg GPR64all[] = {
    2443             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, 
    2444             :   };
    2445             : 
    2446             :   // GPR64all Bit set.
    2447             :   const uint8_t GPR64allBits[] = {
    2448             :     0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
    2449             :   };
    2450             : 
    2451             :   // FPR64 Register Class...
    2452             :   const MCPhysReg FPR64[] = {
    2453             :     AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 
    2454             :   };
    2455             : 
    2456             :   // FPR64 Bit set.
    2457             :   const uint8_t FPR64Bits[] = {
    2458             :     0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2459             :   };
    2460             : 
    2461             :   // GPR64 Register Class...
    2462             :   const MCPhysReg GPR64[] = {
    2463             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, 
    2464             :   };
    2465             : 
    2466             :   // GPR64 Bit set.
    2467             :   const uint8_t GPR64Bits[] = {
    2468             :     0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
    2469             :   };
    2470             : 
    2471             :   // GPR64sp Register Class...
    2472             :   const MCPhysReg GPR64sp[] = {
    2473             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, 
    2474             :   };
    2475             : 
    2476             :   // GPR64sp Bit set.
    2477             :   const uint8_t GPR64spBits[] = {
    2478             :     0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
    2479             :   };
    2480             : 
    2481             :   // GPR64common Register Class...
    2482             :   const MCPhysReg GPR64common[] = {
    2483             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, 
    2484             :   };
    2485             : 
    2486             :   // GPR64common Bit set.
    2487             :   const uint8_t GPR64commonBits[] = {
    2488             :     0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
    2489             :   };
    2490             : 
    2491             :   // tcGPR64 Register Class...
    2492             :   const MCPhysReg tcGPR64[] = {
    2493             :     AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, 
    2494             :   };
    2495             : 
    2496             :   // tcGPR64 Bit set.
    2497             :   const uint8_t tcGPR64Bits[] = {
    2498             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, 
    2499             :   };
    2500             : 
    2501             :   // GPR64sponly Register Class...
    2502             :   const MCPhysReg GPR64sponly[] = {
    2503             :     AArch64::SP, 
    2504             :   };
    2505             : 
    2506             :   // GPR64sponly Bit set.
    2507             :   const uint8_t GPR64sponlyBits[] = {
    2508             :     0x20, 
    2509             :   };
    2510             : 
    2511             :   // DD Register Class...
    2512             :   const MCPhysReg DD[] = {
    2513             :     AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, 
    2514             :   };
    2515             : 
    2516             :   // DD Bit set.
    2517             :   const uint8_t DDBits[] = {
    2518             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2519             :   };
    2520             : 
    2521             :   // XSeqPairsClass Register Class...
    2522             :   const MCPhysReg XSeqPairsClass[] = {
    2523             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, AArch64::XZR_X0, 
    2524             :   };
    2525             : 
    2526             :   // XSeqPairsClass Bit set.
    2527             :   const uint8_t XSeqPairsClassBits[] = {
    2528             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2529             :   };
    2530             : 
    2531             :   // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
    2532             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
    2533             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, 
    2534             :   };
    2535             : 
    2536             :   // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
    2537             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
    2538             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f, 
    2539             :   };
    2540             : 
    2541             :   // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
    2542             :   const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
    2543             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::XZR_X0, 
    2544             :   };
    2545             : 
    2546             :   // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
    2547             :   const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    2548             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, 
    2549             :   };
    2550             : 
    2551             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
    2552             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
    2553             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, 
    2554             :   };
    2555             : 
    2556             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
    2557             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    2558             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xff, 0x1f, 
    2559             :   };
    2560             : 
    2561             :   // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
    2562             :   const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
    2563             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, 
    2564             :   };
    2565             : 
    2566             :   // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
    2567             :   const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
    2568             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f, 
    2569             :   };
    2570             : 
    2571             :   // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
    2572             :   const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    2573             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::XZR_X0, 
    2574             :   };
    2575             : 
    2576             :   // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
    2577             :   const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    2578             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xfe, 0xff, 0x07, 
    2579             :   };
    2580             : 
    2581             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
    2582             :   const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    2583             :     AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, 
    2584             :   };
    2585             : 
    2586             :   // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
    2587             :   const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    2588             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, 
    2589             :   };
    2590             : 
    2591             :   // FPR128 Register Class...
    2592             :   const MCPhysReg FPR128[] = {
    2593             :     AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 
    2594             :   };
    2595             : 
    2596             :   // FPR128 Bit set.
    2597             :   const uint8_t FPR128Bits[] = {
    2598             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
    2599             :   };
    2600             : 
    2601             :   // ZPR Register Class...
    2602             :   const MCPhysReg ZPR[] = {
    2603             :     AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31, 
    2604             :   };
    2605             : 
    2606             :   // ZPR Bit set.
    2607             :   const uint8_t ZPRBits[] = {
    2608             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2609             :   };
    2610             : 
    2611             :   // FPR128_lo Register Class...
    2612             :   const MCPhysReg FPR128_lo[] = {
    2613             :     AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, 
    2614             :   };
    2615             : 
    2616             :   // FPR128_lo Bit set.
    2617             :   const uint8_t FPR128_loBits[] = {
    2618             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
    2619             :   };
    2620             : 
    2621             :   // ZPR_4b Register Class...
    2622             :   const MCPhysReg ZPR_4b[] = {
    2623             :     AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 
    2624             :   };
    2625             : 
    2626             :   // ZPR_4b Bit set.
    2627             :   const uint8_t ZPR_4bBits[] = {
    2628             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2629             :   };
    2630             : 
    2631             :   // ZPR_3b Register Class...
    2632             :   const MCPhysReg ZPR_3b[] = {
    2633             :     AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 
    2634             :   };
    2635             : 
    2636             :   // ZPR_3b Bit set.
    2637             :   const uint8_t ZPR_3bBits[] = {
    2638             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
    2639             :   };
    2640             : 
    2641             :   // DDD Register Class...
    2642             :   const MCPhysReg DDD[] = {
    2643             :     AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, 
    2644             :   };
    2645             : 
    2646             :   // DDD Bit set.
    2647             :   const uint8_t DDDBits[] = {
    2648             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2649             :   };
    2650             : 
    2651             :   // DDDD Register Class...
    2652             :   const MCPhysReg DDDD[] = {
    2653             :     AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, 
    2654             :   };
    2655             : 
    2656             :   // DDDD Bit set.
    2657             :   const uint8_t DDDDBits[] = {
    2658             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2659             :   };
    2660             : 
    2661             :   // QQ Register Class...
    2662             :   const MCPhysReg QQ[] = {
    2663             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, 
    2664             :   };
    2665             : 
    2666             :   // QQ Bit set.
    2667             :   const uint8_t QQBits[] = {
    2668             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2669             :   };
    2670             : 
    2671             :   // ZPR2 Register Class...
    2672             :   const MCPhysReg ZPR2[] = {
    2673             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0, 
    2674             :   };
    2675             : 
    2676             :   // ZPR2 Bit set.
    2677             :   const uint8_t ZPR2Bits[] = {
    2678             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2679             :   };
    2680             : 
    2681             :   // QQ_with_qsub0_in_FPR128_lo Register Class...
    2682             :   const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
    2683             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 
    2684             :   };
    2685             : 
    2686             :   // QQ_with_qsub0_in_FPR128_lo Bit set.
    2687             :   const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
    2688             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2689             :   };
    2690             : 
    2691             :   // QQ_with_qsub1_in_FPR128_lo Register Class...
    2692             :   const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
    2693             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, 
    2694             :   };
    2695             : 
    2696             :   // QQ_with_qsub1_in_FPR128_lo Bit set.
    2697             :   const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
    2698             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2699             :   };
    2700             : 
    2701             :   // ZPR2_with_zsub1_in_ZPR_4b Register Class...
    2702             :   const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = {
    2703             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0, 
    2704             :   };
    2705             : 
    2706             :   // ZPR2_with_zsub1_in_ZPR_4b Bit set.
    2707             :   const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = {
    2708             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2709             :   };
    2710             : 
    2711             :   // ZPR2_with_zsub_in_FPR128_lo Register Class...
    2712             :   const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
    2713             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 
    2714             :   };
    2715             : 
    2716             :   // ZPR2_with_zsub_in_FPR128_lo Bit set.
    2717             :   const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
    2718             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2719             :   };
    2720             : 
    2721             :   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
    2722             :   const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
    2723             :     AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, 
    2724             :   };
    2725             : 
    2726             :   // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
    2727             :   const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
    2728             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2729             :   };
    2730             : 
    2731             :   // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class...
    2732             :   const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = {
    2733             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, 
    2734             :   };
    2735             : 
    2736             :   // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set.
    2737             :   const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = {
    2738             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2739             :   };
    2740             : 
    2741             :   // ZPR2_with_zsub0_in_ZPR_3b Register Class...
    2742             :   const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = {
    2743             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 
    2744             :   };
    2745             : 
    2746             :   // ZPR2_with_zsub0_in_ZPR_3b Bit set.
    2747             :   const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = {
    2748             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
    2749             :   };
    2750             : 
    2751             :   // ZPR2_with_zsub1_in_ZPR_3b Register Class...
    2752             :   const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = {
    2753             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z31_Z0, 
    2754             :   };
    2755             : 
    2756             :   // ZPR2_with_zsub1_in_ZPR_3b Bit set.
    2757             :   const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = {
    2758             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
    2759             :   };
    2760             : 
    2761             :   // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class...
    2762             :   const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = {
    2763             :     AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, 
    2764             :   };
    2765             : 
    2766             :   // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set.
    2767             :   const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = {
    2768             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
    2769             :   };
    2770             : 
    2771             :   // QQQ Register Class...
    2772             :   const MCPhysReg QQQ[] = {
    2773             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
    2774             :   };
    2775             : 
    2776             :   // QQQ Bit set.
    2777             :   const uint8_t QQQBits[] = {
    2778             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2779             :   };
    2780             : 
    2781             :   // ZPR3 Register Class...
    2782             :   const MCPhysReg ZPR3[] = {
    2783             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
    2784             :   };
    2785             : 
    2786             :   // ZPR3 Bit set.
    2787             :   const uint8_t ZPR3Bits[] = {
    2788             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2789             :   };
    2790             : 
    2791             :   // QQQ_with_qsub0_in_FPR128_lo Register Class...
    2792             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
    2793             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, 
    2794             :   };
    2795             : 
    2796             :   // QQQ_with_qsub0_in_FPR128_lo Bit set.
    2797             :   const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
    2798             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2799             :   };
    2800             : 
    2801             :   // QQQ_with_qsub1_in_FPR128_lo Register Class...
    2802             :   const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
    2803             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, 
    2804             :   };
    2805             : 
    2806             :   // QQQ_with_qsub1_in_FPR128_lo Bit set.
    2807             :   const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
    2808             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2809             :   };
    2810             : 
    2811             :   // QQQ_with_qsub2_in_FPR128_lo Register Class...
    2812             :   const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
    2813             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
    2814             :   };
    2815             : 
    2816             :   // QQQ_with_qsub2_in_FPR128_lo Bit set.
    2817             :   const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
    2818             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
    2819             :   };
    2820             : 
    2821             :   // ZPR3_with_zsub1_in_ZPR_4b Register Class...
    2822             :   const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = {
    2823             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1, 
    2824             :   };
    2825             : 
    2826             :   // ZPR3_with_zsub1_in_ZPR_4b Bit set.
    2827             :   const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = {
    2828             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    2829             :   };
    2830             : 
    2831             :   // ZPR3_with_zsub2_in_ZPR_4b Register Class...
    2832             :   const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = {
    2833             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
    2834             :   };
    2835             : 
    2836             :   // ZPR3_with_zsub2_in_ZPR_4b Bit set.
    2837             :   const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = {
    2838             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
    2839             :   };
    2840             : 
    2841             :   // ZPR3_with_zsub_in_FPR128_lo Register Class...
    2842             :   const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
    2843             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, 
    2844             :   };
    2845             : 
    2846             :   // ZPR3_with_zsub_in_FPR128_lo Bit set.
    2847             :   const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
    2848             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2849             :   };
    2850             : 
    2851             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
    2852             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
    2853             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 
    2854             :   };
    2855             : 
    2856             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
    2857             :   const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
    2858             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2859             :   };
    2860             : 
    2861             :   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
    2862             :   const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    2863             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, 
    2864             :   };
    2865             : 
    2866             :   // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
    2867             :   const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    2868             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
    2869             :   };
    2870             : 
    2871             :   // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
    2872             :   const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
    2873             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1, 
    2874             :   };
    2875             : 
    2876             :   // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
    2877             :   const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
    2878             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
    2879             :   };
    2880             : 
    2881             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class...
    2882             :   const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = {
    2883             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 
    2884             :   };
    2885             : 
    2886             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set.
    2887             :   const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = {
    2888             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2889             :   };
    2890             : 
    2891             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
    2892             :   const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    2893             :     AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, 
    2894             :   };
    2895             : 
    2896             :   // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
    2897             :   const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    2898             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
    2899             :   };
    2900             : 
    2901             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
    2902             :   const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
    2903             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, 
    2904             :   };
    2905             : 
    2906             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
    2907             :   const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
    2908             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
    2909             :   };
    2910             : 
    2911             :   // ZPR3_with_zsub0_in_ZPR_3b Register Class...
    2912             :   const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = {
    2913             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, 
    2914             :   };
    2915             : 
    2916             :   // ZPR3_with_zsub0_in_ZPR_3b Bit set.
    2917             :   const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = {
    2918             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
    2919             :   };
    2920             : 
    2921             :   // ZPR3_with_zsub1_in_ZPR_3b Register Class...
    2922             :   const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = {
    2923             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z31_Z0_Z1, 
    2924             :   };
    2925             : 
    2926             :   // ZPR3_with_zsub1_in_ZPR_3b Bit set.
    2927             :   const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = {
    2928             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
    2929             :   };
    2930             : 
    2931             :   // ZPR3_with_zsub2_in_ZPR_3b Register Class...
    2932             :   const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = {
    2933             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
    2934             :   };
    2935             : 
    2936             :   // ZPR3_with_zsub2_in_ZPR_3b Bit set.
    2937             :   const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = {
    2938             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, 
    2939             :   };
    2940             : 
    2941             :   // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
    2942             :   const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
    2943             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1, 
    2944             :   };
    2945             : 
    2946             :   // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
    2947             :   const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
    2948             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, 
    2949             :   };
    2950             : 
    2951             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class...
    2952             :   const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = {
    2953             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, 
    2954             :   };
    2955             : 
    2956             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set.
    2957             :   const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = {
    2958             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
    2959             :   };
    2960             : 
    2961             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
    2962             :   const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
    2963             :     AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 
    2964             :   };
    2965             : 
    2966             :   // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
    2967             :   const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
    2968             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
    2969             :   };
    2970             : 
    2971             :   // QQQQ Register Class...
    2972             :   const MCPhysReg QQQQ[] = {
    2973             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    2974             :   };
    2975             : 
    2976             :   // QQQQ Bit set.
    2977             :   const uint8_t QQQQBits[] = {
    2978             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2979             :   };
    2980             : 
    2981             :   // ZPR4 Register Class...
    2982             :   const MCPhysReg ZPR4[] = {
    2983             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    2984             :   };
    2985             : 
    2986             :   // ZPR4 Bit set.
    2987             :   const uint8_t ZPR4Bits[] = {
    2988             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
    2989             :   };
    2990             : 
    2991             :   // QQQQ_with_qsub0_in_FPR128_lo Register Class...
    2992             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
    2993             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, 
    2994             :   };
    2995             : 
    2996             :   // QQQQ_with_qsub0_in_FPR128_lo Bit set.
    2997             :   const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
    2998             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    2999             :   };
    3000             : 
    3001             :   // QQQQ_with_qsub1_in_FPR128_lo Register Class...
    3002             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
    3003             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, 
    3004             :   };
    3005             : 
    3006             :   // QQQQ_with_qsub1_in_FPR128_lo Bit set.
    3007             :   const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
    3008             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    3009             :   };
    3010             : 
    3011             :   // QQQQ_with_qsub2_in_FPR128_lo Register Class...
    3012             :   const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
    3013             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    3014             :   };
    3015             : 
    3016             :   // QQQQ_with_qsub2_in_FPR128_lo Bit set.
    3017             :   const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
    3018             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
    3019             :   };
    3020             : 
    3021             :   // QQQQ_with_qsub3_in_FPR128_lo Register Class...
    3022             :   const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
    3023             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    3024             :   };
    3025             : 
    3026             :   // QQQQ_with_qsub3_in_FPR128_lo Bit set.
    3027             :   const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
    3028             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
    3029             :   };
    3030             : 
    3031             :   // ZPR4_with_zsub1_in_ZPR_4b Register Class...
    3032             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = {
    3033             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2, 
    3034             :   };
    3035             : 
    3036             :   // ZPR4_with_zsub1_in_ZPR_4b Bit set.
    3037             :   const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = {
    3038             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
    3039             :   };
    3040             : 
    3041             :   // ZPR4_with_zsub2_in_ZPR_4b Register Class...
    3042             :   const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = {
    3043             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    3044             :   };
    3045             : 
    3046             :   // ZPR4_with_zsub2_in_ZPR_4b Bit set.
    3047             :   const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = {
    3048             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
    3049             :   };
    3050             : 
    3051             :   // ZPR4_with_zsub3_in_ZPR_4b Register Class...
    3052             :   const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = {
    3053             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    3054             :   };
    3055             : 
    3056             :   // ZPR4_with_zsub3_in_ZPR_4b Bit set.
    3057             :   const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = {
    3058             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
    3059             :   };
    3060             : 
    3061             :   // ZPR4_with_zsub_in_FPR128_lo Register Class...
    3062             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
    3063             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, 
    3064             :   };
    3065             : 
    3066             :   // ZPR4_with_zsub_in_FPR128_lo Bit set.
    3067             :   const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
    3068             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
    3069             :   };
    3070             : 
    3071             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
    3072             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
    3073             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 
    3074             :   };
    3075             : 
    3076             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
    3077             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
    3078             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    3079             :   };
    3080             : 
    3081             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
    3082             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    3083             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, 
    3084             :   };
    3085             : 
    3086             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
    3087             :   const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    3088             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
    3089             :   };
    3090             : 
    3091             :   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    3092             :   const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    3093             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
    3094             :   };
    3095             : 
    3096             :   // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    3097             :   const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    3098             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
    3099             :   };
    3100             : 
    3101             :   // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
    3102             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
    3103             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2, 
    3104             :   };
    3105             : 
    3106             :   // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
    3107             :   const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
    3108             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
    3109             :   };
    3110             : 
    3111             :   // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
    3112             :   const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
    3113             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    3114             :   };
    3115             : 
    3116             :   // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
    3117             :   const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
    3118             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
    3119             :   };
    3120             : 
    3121             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class...
    3122             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = {
    3123             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 
    3124             :   };
    3125             : 
    3126             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set.
    3127             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = {
    3128             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    3129             :   };
    3130             : 
    3131             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
    3132             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    3133             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, 
    3134             :   };
    3135             : 
    3136             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
    3137             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    3138             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
    3139             :   };
    3140             : 
    3141             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    3142             :   const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    3143             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, 
    3144             :   };
    3145             : 
    3146             :   // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    3147             :   const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    3148             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
    3149             :   };
    3150             : 
    3151             :   // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
    3152             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
    3153             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2, 
    3154             :   };
    3155             : 
    3156             :   // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
    3157             :   const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
    3158             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
    3159             :   };
    3160             : 
    3161             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
    3162             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
    3163             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, 
    3164             :   };
    3165             : 
    3166             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
    3167             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
    3168             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
    3169             :   };
    3170             : 
    3171             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
    3172             :   const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    3173             :     AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, 
    3174             :   };
    3175             : 
    3176             :   // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
    3177             :   const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    3178             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
    3179             :   };
    3180             : 
    3181             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
    3182             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
    3183             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, 
    3184             :   };
    3185             : 
    3186             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
    3187             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
    3188             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
    3189             :   };
    3190             : 
    3191             :   // ZPR4_with_zsub0_in_ZPR_3b Register Class...
    3192             :   const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = {
    3193             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, 
    3194             :   };
    3195             : 
    3196             :   // ZPR4_with_zsub0_in_ZPR_3b Bit set.
    3197             :   const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = {
    3198             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
    3199             :   };
    3200             : 
    3201             :   // ZPR4_with_zsub1_in_ZPR_3b Register Class...
    3202             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = {
    3203             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z31_Z0_Z1_Z2, 
    3204             :   };
    3205             : 
    3206             :   // ZPR4_with_zsub1_in_ZPR_3b Bit set.
    3207             :   const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = {
    3208             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
    3209             :   };
    3210             : 
    3211             :   // ZPR4_with_zsub2_in_ZPR_3b Register Class...
    3212             :   const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = {
    3213             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    3214             :   };
    3215             : 
    3216             :   // ZPR4_with_zsub2_in_ZPR_3b Bit set.
    3217             :   const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = {
    3218             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, 
    3219             :   };
    3220             : 
    3221             :   // ZPR4_with_zsub3_in_ZPR_3b Register Class...
    3222             :   const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = {
    3223             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    3224             :   };
    3225             : 
    3226             :   // ZPR4_with_zsub3_in_ZPR_3b Bit set.
    3227             :   const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = {
    3228             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c, 
    3229             :   };
    3230             : 
    3231             :   // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
    3232             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
    3233             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2, 
    3234             :   };
    3235             : 
    3236             :   // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
    3237             :   const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
    3238             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, 
    3239             :   };
    3240             : 
    3241             :   // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
    3242             :   const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
    3243             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
    3244             :   };
    3245             : 
    3246             :   // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
    3247             :   const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
    3248             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18, 
    3249             :   };
    3250             : 
    3251             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class...
    3252             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = {
    3253             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, 
    3254             :   };
    3255             : 
    3256             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set.
    3257             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = {
    3258             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
    3259             :   };
    3260             : 
    3261             :   // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
    3262             :   const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
    3263             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z31_Z0_Z1_Z2, 
    3264             :   };
    3265             : 
    3266             :   // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
    3267             :   const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
    3268             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10, 
    3269             :   };
    3270             : 
    3271             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
    3272             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
    3273             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 
    3274             :   };
    3275             : 
    3276             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
    3277             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
    3278             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
    3279             :   };
    3280             : 
    3281             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
    3282             :   const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
    3283             :     AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, 
    3284             :   };
    3285             : 
    3286             :   // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
    3287             :   const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
    3288             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 
    3289             :   };
    3290             : 
    3291             : } // end anonymous namespace
    3292             : 
    3293             : extern const char AArch64RegClassStrings[] = {
    3294             :   /* 0 */ 'F', 'P', 'R', '3', '2', 0,
    3295             :   /* 6 */ 'G', 'P', 'R', '3', '2', 0,
    3296             :   /* 12 */ 'Z', 'P', 'R', '2', 0,
    3297             :   /* 17 */ 'Z', 'P', 'R', '3', 0,
    3298             :   /* 22 */ 'F', 'P', 'R', '6', '4', 0,
    3299             :   /* 28 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
    3300             :   /* 66 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
    3301             :   /* 150 */ 'Z', 'P', 'R', '4', 0,
    3302             :   /* 155 */ 'F', 'P', 'R', '1', '6', 0,
    3303             :   /* 161 */ 'F', 'P', 'R', '1', '2', '8', 0,
    3304             :   /* 168 */ 'F', 'P', 'R', '8', 0,
    3305             :   /* 173 */ 'D', 'D', 'D', 'D', 0,
    3306             :   /* 178 */ 'Q', 'Q', 'Q', 'Q', 0,
    3307             :   /* 183 */ 'C', 'C', 'R', 0,
    3308             :   /* 187 */ 'P', 'P', 'R', 0,
    3309             :   /* 191 */ 'Z', 'P', 'R', 0,
    3310             :   /* 195 */ 'P', 'P', 'R', '_', '3', 'b', 0,
    3311             :   /* 202 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3312             :   /* 228 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3313             :   /* 254 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3314             :   /* 280 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3315             :   /* 338 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3316             :   /* 396 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3317             :   /* 454 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3318             :   /* 510 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3319             :   /* 568 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3320             :   /* 624 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3321             :   /* 682 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3322             :   /* 738 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3323             :   /* 794 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
    3324             :   /* 852 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3325             :   /* 910 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3326             :   /* 968 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3327             :   /* 1026 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3328             :   /* 1082 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3329             :   /* 1140 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3330             :   /* 1196 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3331             :   /* 1254 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3332             :   /* 1310 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3333             :   /* 1366 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
    3334             :   /* 1424 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
    3335             :   /* 1433 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
    3336             :   /* 1442 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    3337             :   /* 1484 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    3338             :   /* 1526 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    3339             :   /* 1614 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
    3340             :   /* 1702 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3341             :   /* 1731 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3342             :   /* 1793 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3343             :   /* 1853 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3344             :   /* 1911 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3345             :   /* 1973 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3346             :   /* 2035 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3347             :   /* 2095 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3348             :   /* 2155 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3349             :   /* 2217 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3350             :   /* 2279 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3351             :   /* 2341 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3352             :   /* 2369 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3353             :   /* 2397 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
    3354             :   /* 2425 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
    3355             :   /* 2433 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
    3356             :   /* 2441 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
    3357             :   /* 2456 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
    3358             :   /* 2471 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
    3359             :   /* 2483 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
    3360             : };
    3361             : 
    3362             : extern const MCRegisterClass AArch64MCRegisterClasses[] = {
    3363             :   { FPR8, FPR8Bits, 168, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, 1, true },
    3364             :   { FPR16, FPR16Bits, 155, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 2, 1, true },
    3365             :   { PPR, PPRBits, 187, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 2, 1, true },
    3366             :   { PPR_3b, PPR_3bBits, 195, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 2, 1, true },
    3367             :   { GPR32all, GPR32allBits, 1424, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 4, 1, true },
    3368             :   { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 4, 1, true },
    3369             :   { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 4, 1, true },
    3370             :   { GPR32sp, GPR32spBits, 2425, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 4, 1, true },
    3371             :   { GPR32common, GPR32commonBits, 1472, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 4, 1, true },
    3372             :   { CCR, CCRBits, 183, 1, sizeof(CCRBits), AArch64::CCRRegClassID, 4, -1, false },
    3373             :   { GPR32sponly, GPR32sponlyBits, 2471, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 4, 1, true },
    3374             :   { WSeqPairsClass, WSeqPairsClassBits, 2441, 32, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 8, 1, true },
    3375             :   { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, 1484, 31, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClassID, 8, 1, true },
    3376             :   { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 1572, 31, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 1, true },
    3377             :   { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, 1526, 30, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 1, true },
    3378             :   { GPR64all, GPR64allBits, 1433, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 8, 1, true },
    3379             :   { FPR64, FPR64Bits, 22, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 8, 1, true },
    3380             :   { GPR64, GPR64Bits, 60, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 8, 1, true },
    3381             :   { GPR64sp, GPR64spBits, 2433, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 8, 1, true },
    3382             :   { GPR64common, GPR64commonBits, 1690, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 8, 1, true },
    3383             :   { tcGPR64, tcGPR64Bits, 58, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 8, 1, true },
    3384             :   { GPR64sponly, GPR64sponlyBits, 2483, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 8, 1, true },
    3385             :   { DD, DDBits, 175, 32, sizeof(DDBits), AArch64::DDRegClassID, 16, 1, true },
    3386             :   { XSeqPairsClass, XSeqPairsClassBits, 2456, 32, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 16, 1, true },
    3387             :   { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, 1442, 31, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID, 16, 1, true },
    3388             :   { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 1660, 31, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 1, true },
    3389             :   { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, 1614, 30, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 1, true },
    3390             :   { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 28, 19, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 16, 1, true },
    3391             :   { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 112, 19, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 1, true },
    3392             :   { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, 66, 18, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 1, true },
    3393             :   { FPR128, FPR128Bits, 161, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 16, 1, true },
    3394             :   { ZPR, ZPRBits, 191, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 16, 1, true },
    3395             :   { FPR128_lo, FPR128_loBits, 1721, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 16, 1, true },
    3396             :   { ZPR_4b, ZPR_4bBits, 903, 16, sizeof(ZPR_4bBits), AArch64::ZPR_4bRegClassID, 16, 1, true },
    3397             :   { ZPR_3b, ZPR_3bBits, 221, 8, sizeof(ZPR_3bBits), AArch64::ZPR_3bRegClassID, 16, 1, true },
    3398             :   { DDD, DDDBits, 174, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 24, 1, true },
    3399             :   { DDDD, DDDDBits, 173, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 32, 1, true },
    3400             :   { QQ, QQBits, 180, 32, sizeof(QQBits), AArch64::QQRegClassID, 32, 1, true },
    3401             :   { ZPR2, ZPR2Bits, 12, 32, sizeof(ZPR2Bits), AArch64::ZPR2RegClassID, 32, 1, true },
    3402             :   { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 1704, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 32, 1, true },
    3403             :   { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 1766, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 32, 1, true },
    3404             :   { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, 884, 16, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClassID, 32, 1, true },
    3405             :   { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, 2341, 16, sizeof(ZPR2_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub_in_FPR128_loRegClassID, 32, 1, true },
    3406             :   { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 1853, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 1, true },
    3407             :   { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, 852, 15, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID, 32, 1, true },
    3408             :   { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, 202, 8, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits), AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClassID, 32, 1, true },
    3409             :   { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, 312, 8, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClassID, 32, 1, true },
    3410             :   { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, 280, 7, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID, 32, 1, true },
    3411             :   { QQQ, QQQBits, 179, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 48, 1, true },
    3412             :   { ZPR3, ZPR3Bits, 17, 32, sizeof(ZPR3Bits), AArch64::ZPR3RegClassID, 48, 1, true },
    3413             :   { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 1703, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 1, true },
    3414             :   { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 1765, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 1, true },
    3415             :   { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 1945, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    3416             :   { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, 942, 16, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClassID, 48, 1, true },
    3417             :   { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, 1056, 16, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClassID, 48, 1, true },
    3418             :   { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, 2369, 16, sizeof(ZPR3_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_loRegClassID, 48, 1, true },
    3419             :   { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 1793, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 1, true },
    3420             :   { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2095, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    3421             :   { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1026, 15, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 48, 1, true },
    3422             :   { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, 910, 15, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID, 48, 1, true },
    3423             :   { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2035, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 1, true },
    3424             :   { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1082, 14, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 48, 1, true },
    3425             :   { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, 228, 8, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits), AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClassID, 48, 1, true },
    3426             :   { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, 370, 8, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClassID, 48, 1, true },
    3427             :   { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, 484, 8, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClassID, 48, 1, true },
    3428             :   { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, 454, 7, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 48, 1, true },
    3429             :   { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, 338, 7, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID, 48, 1, true },
    3430             :   { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, 510, 6, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 48, 1, true },
    3431             :   { QQQQ, QQQQBits, 178, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 64, 1, true },
    3432             :   { ZPR4, ZPR4Bits, 150, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 64, 1, true },
    3433             :   { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 1702, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 1, true },
    3434             :   { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 1764, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 1, true },
    3435             :   { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 1944, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    3436             :   { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 2188, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    3437             :   { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, 1000, 16, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClassID, 64, 1, true },
    3438             :   { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, 1170, 16, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClassID, 64, 1, true },
    3439             :   { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, 1284, 16, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClassID, 64, 1, true },
    3440             :   { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, 2397, 16, sizeof(ZPR4_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_loRegClassID, 64, 1, true },
    3441             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 1731, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 1, true },
    3442             :   { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 1973, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    3443             :   { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2279, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    3444             :   { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1140, 15, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 64, 1, true },
    3445             :   { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1310, 15, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 64, 1, true },
    3446             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, 968, 15, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID, 64, 1, true },
    3447             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 1911, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 1, true },
    3448             :   { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2217, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    3449             :   { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1254, 14, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 64, 1, true },
    3450             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1196, 14, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 64, 1, true },
    3451             :   { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2155, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 1, true },
    3452             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1366, 13, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 64, 1, true },
    3453             :   { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, 254, 8, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits), AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClassID, 64, 1, true },
    3454             :   { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, 428, 8, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClassID, 64, 1, true },
    3455             :   { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, 598, 8, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClassID, 64, 1, true },
    3456             :   { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, 712, 8, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClassID, 64, 1, true },
    3457             :   { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, 568, 7, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 64, 1, true },
    3458             :   { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 738, 7, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 64, 1, true },
    3459             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, 396, 7, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID, 64, 1, true },
    3460             :   { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 682, 6, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 64, 1, true },
    3461             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, 624, 6, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 64, 1, true },
    3462             :   { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, 794, 5, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 64, 1, true },
    3463             : };
    3464             : 
    3465             : // AArch64 Dwarf<->LLVM register mappings.
    3466             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
    3467             :   { 0U, AArch64::W0 },
    3468             :   { 1U, AArch64::W1 },
    3469             :   { 2U, AArch64::W2 },
    3470             :   { 3U, AArch64::W3 },
    3471             :   { 4U, AArch64::W4 },
    3472             :   { 5U, AArch64::W5 },
    3473             :   { 6U, AArch64::W6 },
    3474             :   { 7U, AArch64::W7 },
    3475             :   { 8U, AArch64::W8 },
    3476             :   { 9U, AArch64::W9 },
    3477             :   { 10U, AArch64::W10 },
    3478             :   { 11U, AArch64::W11 },
    3479             :   { 12U, AArch64::W12 },
    3480             :   { 13U, AArch64::W13 },
    3481             :   { 14U, AArch64::W14 },
    3482             :   { 15U, AArch64::W15 },
    3483             :   { 16U, AArch64::W16 },
    3484             :   { 17U, AArch64::W17 },
    3485             :   { 18U, AArch64::W18 },
    3486             :   { 19U, AArch64::W19 },
    3487             :   { 20U, AArch64::W20 },
    3488             :   { 21U, AArch64::W21 },
    3489             :   { 22U, AArch64::W22 },
    3490             :   { 23U, AArch64::W23 },
    3491             :   { 24U, AArch64::W24 },
    3492             :   { 25U, AArch64::W25 },
    3493             :   { 26U, AArch64::W26 },
    3494             :   { 27U, AArch64::W27 },
    3495             :   { 28U, AArch64::W28 },
    3496             :   { 29U, AArch64::W29 },
    3497             :   { 30U, AArch64::W30 },
    3498             :   { 31U, AArch64::WSP },
    3499             :   { 47U, AArch64::FFR },
    3500             :   { 48U, AArch64::P0 },
    3501             :   { 49U, AArch64::P1 },
    3502             :   { 50U, AArch64::P2 },
    3503             :   { 51U, AArch64::P3 },
    3504             :   { 52U, AArch64::P4 },
    3505             :   { 53U, AArch64::P5 },
    3506             :   { 54U, AArch64::P6 },
    3507             :   { 55U, AArch64::P7 },
    3508             :   { 56U, AArch64::P8 },
    3509             :   { 57U, AArch64::P9 },
    3510             :   { 58U, AArch64::P10 },
    3511             :   { 59U, AArch64::P11 },
    3512             :   { 60U, AArch64::P12 },
    3513             :   { 61U, AArch64::P13 },
    3514             :   { 62U, AArch64::P14 },
    3515             :   { 63U, AArch64::P15 },
    3516             :   { 64U, AArch64::B0 },
    3517             :   { 65U, AArch64::B1 },
    3518             :   { 66U, AArch64::B2 },
    3519             :   { 67U, AArch64::B3 },
    3520             :   { 68U, AArch64::B4 },
    3521             :   { 69U, AArch64::B5 },
    3522             :   { 70U, AArch64::B6 },
    3523             :   { 71U, AArch64::B7 },
    3524             :   { 72U, AArch64::B8 },
    3525             :   { 73U, AArch64::B9 },
    3526             :   { 74U, AArch64::B10 },
    3527             :   { 75U, AArch64::B11 },
    3528             :   { 76U, AArch64::B12 },
    3529             :   { 77U, AArch64::B13 },
    3530             :   { 78U, AArch64::B14 },
    3531             :   { 79U, AArch64::B15 },
    3532             :   { 80U, AArch64::B16 },
    3533             :   { 81U, AArch64::B17 },
    3534             :   { 82U, AArch64::B18 },
    3535             :   { 83U, AArch64::B19 },
    3536             :   { 84U, AArch64::B20 },
    3537             :   { 85U, AArch64::B21 },
    3538             :   { 86U, AArch64::B22 },
    3539             :   { 87U, AArch64::B23 },
    3540             :   { 88U, AArch64::B24 },
    3541             :   { 89U, AArch64::B25 },
    3542             :   { 90U, AArch64::B26 },
    3543             :   { 91U, AArch64::B27 },
    3544             :   { 92U, AArch64::B28 },
    3545             :   { 93U, AArch64::B29 },
    3546             :   { 94U, AArch64::B30 },
    3547             :   { 95U, AArch64::B31 },
    3548             :   { 96U, AArch64::Z0 },
    3549             :   { 97U, AArch64::Z1 },
    3550             :   { 98U, AArch64::Z2 },
    3551             :   { 99U, AArch64::Z3 },
    3552             :   { 100U, AArch64::Z4 },
    3553             :   { 101U, AArch64::Z5 },
    3554             :   { 102U, AArch64::Z6 },
    3555             :   { 103U, AArch64::Z7 },
    3556             :   { 104U, AArch64::Z8 },
    3557             :   { 105U, AArch64::Z9 },
    3558             :   { 106U, AArch64::Z10 },
    3559             :   { 107U, AArch64::Z11 },
    3560             :   { 108U, AArch64::Z12 },
    3561             :   { 109U, AArch64::Z13 },
    3562             :   { 110U, AArch64::Z14 },
    3563             :   { 111U, AArch64::Z15 },
    3564             :   { 112U, AArch64::Z16 },
    3565             :   { 113U, AArch64::Z17 },
    3566             :   { 114U, AArch64::Z18 },
    3567             :   { 115U, AArch64::Z19 },
    3568             :   { 116U, AArch64::Z20 },
    3569             :   { 117U, AArch64::Z21 },
    3570             :   { 118U, AArch64::Z22 },
    3571             :   { 119U, AArch64::Z23 },
    3572             :   { 120U, AArch64::Z24 },
    3573             :   { 121U, AArch64::Z25 },
    3574             :   { 122U, AArch64::Z26 },
    3575             :   { 123U, AArch64::Z27 },
    3576             :   { 124U, AArch64::Z28 },
    3577             :   { 125U, AArch64::Z29 },
    3578             :   { 126U, AArch64::Z30 },
    3579             :   { 127U, AArch64::Z31 },
    3580             : };
    3581             : extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
    3582             : 
    3583             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
    3584             :   { 0U, AArch64::W0 },
    3585             :   { 1U, AArch64::W1 },
    3586             :   { 2U, AArch64::W2 },
    3587             :   { 3U, AArch64::W3 },
    3588             :   { 4U, AArch64::W4 },
    3589             :   { 5U, AArch64::W5 },
    3590             :   { 6U, AArch64::W6 },
    3591             :   { 7U, AArch64::W7 },
    3592             :   { 8U, AArch64::W8 },
    3593             :   { 9U, AArch64::W9 },
    3594             :   { 10U, AArch64::W10 },
    3595             :   { 11U, AArch64::W11 },
    3596             :   { 12U, AArch64::W12 },
    3597             :   { 13U, AArch64::W13 },
    3598             :   { 14U, AArch64::W14 },
    3599             :   { 15U, AArch64::W15 },
    3600             :   { 16U, AArch64::W16 },
    3601             :   { 17U, AArch64::W17 },
    3602             :   { 18U, AArch64::W18 },
    3603             :   { 19U, AArch64::W19 },
    3604             :   { 20U, AArch64::W20 },
    3605             :   { 21U, AArch64::W21 },
    3606             :   { 22U, AArch64::W22 },
    3607             :   { 23U, AArch64::W23 },
    3608             :   { 24U, AArch64::W24 },
    3609             :   { 25U, AArch64::W25 },
    3610             :   { 26U, AArch64::W26 },
    3611             :   { 27U, AArch64::W27 },
    3612             :   { 28U, AArch64::W28 },
    3613             :   { 29U, AArch64::W29 },
    3614             :   { 30U, AArch64::W30 },
    3615             :   { 31U, AArch64::WSP },
    3616             :   { 47U, AArch64::FFR },
    3617             :   { 48U, AArch64::P0 },
    3618             :   { 49U, AArch64::P1 },
    3619             :   { 50U, AArch64::P2 },
    3620             :   { 51U, AArch64::P3 },
    3621             :   { 52U, AArch64::P4 },
    3622             :   { 53U, AArch64::P5 },
    3623             :   { 54U, AArch64::P6 },
    3624             :   { 55U, AArch64::P7 },
    3625             :   { 56U, AArch64::P8 },
    3626             :   { 57U, AArch64::P9 },
    3627             :   { 58U, AArch64::P10 },
    3628             :   { 59U, AArch64::P11 },
    3629             :   { 60U, AArch64::P12 },
    3630             :   { 61U, AArch64::P13 },
    3631             :   { 62U, AArch64::P14 },
    3632             :   { 63U, AArch64::P15 },
    3633             :   { 64U, AArch64::B0 },
    3634             :   { 65U, AArch64::B1 },
    3635             :   { 66U, AArch64::B2 },
    3636             :   { 67U, AArch64::B3 },
    3637             :   { 68U, AArch64::B4 },
    3638             :   { 69U, AArch64::B5 },
    3639             :   { 70U, AArch64::B6 },
    3640             :   { 71U, AArch64::B7 },
    3641             :   { 72U, AArch64::B8 },
    3642             :   { 73U, AArch64::B9 },
    3643             :   { 74U, AArch64::B10 },
    3644             :   { 75U, AArch64::B11 },
    3645             :   { 76U, AArch64::B12 },
    3646             :   { 77U, AArch64::B13 },
    3647             :   { 78U, AArch64::B14 },
    3648             :   { 79U, AArch64::B15 },
    3649             :   { 80U, AArch64::B16 },
    3650             :   { 81U, AArch64::B17 },
    3651             :   { 82U, AArch64::B18 },
    3652             :   { 83U, AArch64::B19 },
    3653             :   { 84U, AArch64::B20 },
    3654             :   { 85U, AArch64::B21 },
    3655             :   { 86U, AArch64::B22 },
    3656             :   { 87U, AArch64::B23 },
    3657             :   { 88U, AArch64::B24 },
    3658             :   { 89U, AArch64::B25 },
    3659             :   { 90U, AArch64::B26 },
    3660             :   { 91U, AArch64::B27 },
    3661             :   { 92U, AArch64::B28 },
    3662             :   { 93U, AArch64::B29 },
    3663             :   { 94U, AArch64::B30 },
    3664             :   { 95U, AArch64::B31 },
    3665             :   { 96U, AArch64::Z0 },
    3666             :   { 97U, AArch64::Z1 },
    3667             :   { 98U, AArch64::Z2 },
    3668             :   { 99U, AArch64::Z3 },
    3669             :   { 100U, AArch64::Z4 },
    3670             :   { 101U, AArch64::Z5 },
    3671             :   { 102U, AArch64::Z6 },
    3672             :   { 103U, AArch64::Z7 },
    3673             :   { 104U, AArch64::Z8 },
    3674             :   { 105U, AArch64::Z9 },
    3675             :   { 106U, AArch64::Z10 },
    3676             :   { 107U, AArch64::Z11 },
    3677             :   { 108U, AArch64::Z12 },
    3678             :   { 109U, AArch64::Z13 },
    3679             :   { 110U, AArch64::Z14 },
    3680             :   { 111U, AArch64::Z15 },
    3681             :   { 112U, AArch64::Z16 },
    3682             :   { 113U, AArch64::Z17 },
    3683             :   { 114U, AArch64::Z18 },
    3684             :   { 115U, AArch64::Z19 },
    3685             :   { 116U, AArch64::Z20 },
    3686             :   { 117U, AArch64::Z21 },
    3687             :   { 118U, AArch64::Z22 },
    3688             :   { 119U, AArch64::Z23 },
    3689             :   { 120U, AArch64::Z24 },
    3690             :   { 121U, AArch64::Z25 },
    3691             :   { 122U, AArch64::Z26 },
    3692             :   { 123U, AArch64::Z27 },
    3693             :   { 124U, AArch64::Z28 },
    3694             :   { 125U, AArch64::Z29 },
    3695             :   { 126U, AArch64::Z30 },
    3696             :   { 127U, AArch64::Z31 },
    3697             : };
    3698             : extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
    3699             : 
    3700             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
    3701             :   { AArch64::FFR, 47U },
    3702             :   { AArch64::FP, 29U },
    3703             :   { AArch64::LR, 30U },
    3704             :   { AArch64::SP, 31U },
    3705             :   { AArch64::WSP, 31U },
    3706             :   { AArch64::WZR, 31U },
    3707             :   { AArch64::XZR, 31U },
    3708             :   { AArch64::B0, 64U },
    3709             :   { AArch64::B1, 65U },
    3710             :   { AArch64::B2, 66U },
    3711             :   { AArch64::B3, 67U },
    3712             :   { AArch64::B4, 68U },
    3713             :   { AArch64::B5, 69U },
    3714             :   { AArch64::B6, 70U },
    3715             :   { AArch64::B7, 71U },
    3716             :   { AArch64::B8, 72U },
    3717             :   { AArch64::B9, 73U },
    3718             :   { AArch64::B10, 74U },
    3719             :   { AArch64::B11, 75U },
    3720             :   { AArch64::B12, 76U },
    3721             :   { AArch64::B13, 77U },
    3722             :   { AArch64::B14, 78U },
    3723             :   { AArch64::B15, 79U },
    3724             :   { AArch64::B16, 80U },
    3725             :   { AArch64::B17, 81U },
    3726             :   { AArch64::B18, 82U },
    3727             :   { AArch64::B19, 83U },
    3728             :   { AArch64::B20, 84U },
    3729             :   { AArch64::B21, 85U },
    3730             :   { AArch64::B22, 86U },
    3731             :   { AArch64::B23, 87U },
    3732             :   { AArch64::B24, 88U },
    3733             :   { AArch64::B25, 89U },
    3734             :   { AArch64::B26, 90U },
    3735             :   { AArch64::B27, 91U },
    3736             :   { AArch64::B28, 92U },
    3737             :   { AArch64::B29, 93U },
    3738             :   { AArch64::B30, 94U },
    3739             :   { AArch64::B31, 95U },
    3740             :   { AArch64::D0, 64U },
    3741             :   { AArch64::D1, 65U },
    3742             :   { AArch64::D2, 66U },
    3743             :   { AArch64::D3, 67U },
    3744             :   { AArch64::D4, 68U },
    3745             :   { AArch64::D5, 69U },
    3746             :   { AArch64::D6, 70U },
    3747             :   { AArch64::D7, 71U },
    3748             :   { AArch64::D8, 72U },
    3749             :   { AArch64::D9, 73U },
    3750             :   { AArch64::D10, 74U },
    3751             :   { AArch64::D11, 75U },
    3752             :   { AArch64::D12, 76U },
    3753             :   { AArch64::D13, 77U },
    3754             :   { AArch64::D14, 78U },
    3755             :   { AArch64::D15, 79U },
    3756             :   { AArch64::D16, 80U },
    3757             :   { AArch64::D17, 81U },
    3758             :   { AArch64::D18, 82U },
    3759             :   { AArch64::D19, 83U },
    3760             :   { AArch64::D20, 84U },
    3761             :   { AArch64::D21, 85U },
    3762             :   { AArch64::D22, 86U },
    3763             :   { AArch64::D23, 87U },
    3764             :   { AArch64::D24, 88U },
    3765             :   { AArch64::D25, 89U },
    3766             :   { AArch64::D26, 90U },
    3767             :   { AArch64::D27, 91U },
    3768             :   { AArch64::D28, 92U },
    3769             :   { AArch64::D29, 93U },
    3770             :   { AArch64::D30, 94U },
    3771             :   { AArch64::D31, 95U },
    3772             :   { AArch64::H0, 64U },
    3773             :   { AArch64::H1, 65U },
    3774             :   { AArch64::H2, 66U },
    3775             :   { AArch64::H3, 67U },
    3776             :   { AArch64::H4, 68U },
    3777             :   { AArch64::H5, 69U },
    3778             :   { AArch64::H6, 70U },
    3779             :   { AArch64::H7, 71U },
    3780             :   { AArch64::H8, 72U },
    3781             :   { AArch64::H9, 73U },
    3782             :   { AArch64::H10, 74U },
    3783             :   { AArch64::H11, 75U },
    3784             :   { AArch64::H12, 76U },
    3785             :   { AArch64::H13, 77U },
    3786             :   { AArch64::H14, 78U },
    3787             :   { AArch64::H15, 79U },
    3788             :   { AArch64::H16, 80U },
    3789             :   { AArch64::H17, 81U },
    3790             :   { AArch64::H18, 82U },
    3791             :   { AArch64::H19, 83U },
    3792             :   { AArch64::H20, 84U },
    3793             :   { AArch64::H21, 85U },
    3794             :   { AArch64::H22, 86U },
    3795             :   { AArch64::H23, 87U },
    3796             :   { AArch64::H24, 88U },
    3797             :   { AArch64::H25, 89U },
    3798             :   { AArch64::H26, 90U },
    3799             :   { AArch64::H27, 91U },
    3800             :   { AArch64::H28, 92U },
    3801             :   { AArch64::H29, 93U },
    3802             :   { AArch64::H30, 94U },
    3803             :   { AArch64::H31, 95U },
    3804             :   { AArch64::P0, 48U },
    3805             :   { AArch64::P1, 49U },
    3806             :   { AArch64::P2, 50U },
    3807             :   { AArch64::P3, 51U },
    3808             :   { AArch64::P4, 52U },
    3809             :   { AArch64::P5, 53U },
    3810             :   { AArch64::P6, 54U },
    3811             :   { AArch64::P7, 55U },
    3812             :   { AArch64::P8, 56U },
    3813             :   { AArch64::P9, 57U },
    3814             :   { AArch64::P10, 58U },
    3815             :   { AArch64::P11, 59U },
    3816             :   { AArch64::P12, 60U },
    3817             :   { AArch64::P13, 61U },
    3818             :   { AArch64::P14, 62U },
    3819             :   { AArch64::P15, 63U },
    3820             :   { AArch64::Q0, 64U },
    3821             :   { AArch64::Q1, 65U },
    3822             :   { AArch64::Q2, 66U },
    3823             :   { AArch64::Q3, 67U },
    3824             :   { AArch64::Q4, 68U },
    3825             :   { AArch64::Q5, 69U },
    3826             :   { AArch64::Q6, 70U },
    3827             :   { AArch64::Q7, 71U },
    3828             :   { AArch64::Q8, 72U },
    3829             :   { AArch64::Q9, 73U },
    3830             :   { AArch64::Q10, 74U },
    3831             :   { AArch64::Q11, 75U },
    3832             :   { AArch64::Q12, 76U },
    3833             :   { AArch64::Q13, 77U },
    3834             :   { AArch64::Q14, 78U },
    3835             :   { AArch64::Q15, 79U },
    3836             :   { AArch64::Q16, 80U },
    3837             :   { AArch64::Q17, 81U },
    3838             :   { AArch64::Q18, 82U },
    3839             :   { AArch64::Q19, 83U },
    3840             :   { AArch64::Q20, 84U },
    3841             :   { AArch64::Q21, 85U },
    3842             :   { AArch64::Q22, 86U },
    3843             :   { AArch64::Q23, 87U },
    3844             :   { AArch64::Q24, 88U },
    3845             :   { AArch64::Q25, 89U },
    3846             :   { AArch64::Q26, 90U },
    3847             :   { AArch64::Q27, 91U },
    3848             :   { AArch64::Q28, 92U },
    3849             :   { AArch64::Q29, 93U },
    3850             :   { AArch64::Q30, 94U },
    3851             :   { AArch64::Q31, 95U },
    3852             :   { AArch64::S0, 64U },
    3853             :   { AArch64::S1, 65U },
    3854             :   { AArch64::S2, 66U },
    3855             :   { AArch64::S3, 67U },
    3856             :   { AArch64::S4, 68U },
    3857             :   { AArch64::S5, 69U },
    3858             :   { AArch64::S6, 70U },
    3859             :   { AArch64::S7, 71U },
    3860             :   { AArch64::S8, 72U },
    3861             :   { AArch64::S9, 73U },
    3862             :   { AArch64::S10, 74U },
    3863             :   { AArch64::S11, 75U },
    3864             :   { AArch64::S12, 76U },
    3865             :   { AArch64::S13, 77U },
    3866             :   { AArch64::S14, 78U },
    3867             :   { AArch64::S15, 79U },
    3868             :   { AArch64::S16, 80U },
    3869             :   { AArch64::S17, 81U },
    3870             :   { AArch64::S18, 82U },
    3871             :   { AArch64::S19, 83U },
    3872             :   { AArch64::S20, 84U },
    3873             :   { AArch64::S21, 85U },
    3874             :   { AArch64::S22, 86U },
    3875             :   { AArch64::S23, 87U },
    3876             :   { AArch64::S24, 88U },
    3877             :   { AArch64::S25, 89U },
    3878             :   { AArch64::S26, 90U },
    3879             :   { AArch64::S27, 91U },
    3880             :   { AArch64::S28, 92U },
    3881             :   { AArch64::S29, 93U },
    3882             :   { AArch64::S30, 94U },
    3883             :   { AArch64::S31, 95U },
    3884             :   { AArch64::W0, 0U },
    3885             :   { AArch64::W1, 1U },
    3886             :   { AArch64::W2, 2U },
    3887             :   { AArch64::W3, 3U },
    3888             :   { AArch64::W4, 4U },
    3889             :   { AArch64::W5, 5U },
    3890             :   { AArch64::W6, 6U },
    3891             :   { AArch64::W7, 7U },
    3892             :   { AArch64::W8, 8U },
    3893             :   { AArch64::W9, 9U },
    3894             :   { AArch64::W10, 10U },
    3895             :   { AArch64::W11, 11U },
    3896             :   { AArch64::W12, 12U },
    3897             :   { AArch64::W13, 13U },
    3898             :   { AArch64::W14, 14U },
    3899             :   { AArch64::W15, 15U },
    3900             :   { AArch64::W16, 16U },
    3901             :   { AArch64::W17, 17U },
    3902             :   { AArch64::W18, 18U },
    3903             :   { AArch64::W19, 19U },
    3904             :   { AArch64::W20, 20U },
    3905             :   { AArch64::W21, 21U },
    3906             :   { AArch64::W22, 22U },
    3907             :   { AArch64::W23, 23U },
    3908             :   { AArch64::W24, 24U },
    3909             :   { AArch64::W25, 25U },
    3910             :   { AArch64::W26, 26U },
    3911             :   { AArch64::W27, 27U },
    3912             :   { AArch64::W28, 28U },
    3913             :   { AArch64::W29, 29U },
    3914             :   { AArch64::W30, 30U },
    3915             :   { AArch64::X0, 0U },
    3916             :   { AArch64::X1, 1U },
    3917             :   { AArch64::X2, 2U },
    3918             :   { AArch64::X3, 3U },
    3919             :   { AArch64::X4, 4U },
    3920             :   { AArch64::X5, 5U },
    3921             :   { AArch64::X6, 6U },
    3922             :   { AArch64::X7, 7U },
    3923             :   { AArch64::X8, 8U },
    3924             :   { AArch64::X9, 9U },
    3925             :   { AArch64::X10, 10U },
    3926             :   { AArch64::X11, 11U },
    3927             :   { AArch64::X12, 12U },
    3928             :   { AArch64::X13, 13U },
    3929             :   { AArch64::X14, 14U },
    3930             :   { AArch64::X15, 15U },
    3931             :   { AArch64::X16, 16U },
    3932             :   { AArch64::X17, 17U },
    3933             :   { AArch64::X18, 18U },
    3934             :   { AArch64::X19, 19U },
    3935             :   { AArch64::X20, 20U },
    3936             :   { AArch64::X21, 21U },
    3937             :   { AArch64::X22, 22U },
    3938             :   { AArch64::X23, 23U },
    3939             :   { AArch64::X24, 24U },
    3940             :   { AArch64::X25, 25U },
    3941             :   { AArch64::X26, 26U },
    3942             :   { AArch64::X27, 27U },
    3943             :   { AArch64::X28, 28U },
    3944             :   { AArch64::Z0, 96U },
    3945             :   { AArch64::Z1, 97U },
    3946             :   { AArch64::Z2, 98U },
    3947             :   { AArch64::Z3, 99U },
    3948             :   { AArch64::Z4, 100U },
    3949             :   { AArch64::Z5, 101U },
    3950             :   { AArch64::Z6, 102U },
    3951             :   { AArch64::Z7, 103U },
    3952             :   { AArch64::Z8, 104U },
    3953             :   { AArch64::Z9, 105U },
    3954             :   { AArch64::Z10, 106U },
    3955             :   { AArch64::Z11, 107U },
    3956             :   { AArch64::Z12, 108U },
    3957             :   { AArch64::Z13, 109U },
    3958             :   { AArch64::Z14, 110U },
    3959             :   { AArch64::Z15, 111U },
    3960             :   { AArch64::Z16, 112U },
    3961             :   { AArch64::Z17, 113U },
    3962             :   { AArch64::Z18, 114U },
    3963             :   { AArch64::Z19, 115U },
    3964             :   { AArch64::Z20, 116U },
    3965             :   { AArch64::Z21, 117U },
    3966             :   { AArch64::Z22, 118U },
    3967             :   { AArch64::Z23, 119U },
    3968             :   { AArch64::Z24, 120U },
    3969             :   { AArch64::Z25, 121U },
    3970             :   { AArch64::Z26, 122U },
    3971             :   { AArch64::Z27, 123U },
    3972             :   { AArch64::Z28, 124U },
    3973             :   { AArch64::Z29, 125U },
    3974             :   { AArch64::Z30, 126U },
    3975             :   { AArch64::Z31, 127U },
    3976             : };
    3977             : extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
    3978             : 
    3979             : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
    3980             :   { AArch64::FFR, 47U },
    3981             :   { AArch64::FP, 29U },
    3982             :   { AArch64::LR, 30U },
    3983             :   { AArch64::SP, 31U },
    3984             :   { AArch64::WSP, 31U },
    3985             :   { AArch64::WZR, 31U },
    3986             :   { AArch64::XZR, 31U },
    3987             :   { AArch64::B0, 64U },
    3988             :   { AArch64::B1, 65U },
    3989             :   { AArch64::B2, 66U },
    3990             :   { AArch64::B3, 67U },
    3991             :   { AArch64::B4, 68U },
    3992             :   { AArch64::B5, 69U },
    3993             :   { AArch64::B6, 70U },
    3994             :   { AArch64::B7, 71U },
    3995             :   { AArch64::B8, 72U },
    3996             :   { AArch64::B9, 73U },
    3997             :   { AArch64::B10, 74U },
    3998             :   { AArch64::B11, 75U },
    3999             :   { AArch64::B12, 76U },
    4000             :   { AArch64::B13, 77U },
    4001             :   { AArch64::B14, 78U },
    4002             :   { AArch64::B15, 79U },
    4003             :   { AArch64::B16, 80U },
    4004             :   { AArch64::B17, 81U },
    4005             :   { AArch64::B18, 82U },
    4006             :   { AArch64::B19, 83U },
    4007             :   { AArch64::B20, 84U },
    4008             :   { AArch64::B21, 85U },
    4009             :   { AArch64::B22, 86U },
    4010             :   { AArch64::B23, 87U },
    4011             :   { AArch64::B24, 88U },
    4012             :   { AArch64::B25, 89U },
    4013             :   { AArch64::B26, 90U },
    4014             :   { AArch64::B27, 91U },
    4015             :   { AArch64::B28, 92U },
    4016             :   { AArch64::B29, 93U },
    4017             :   { AArch64::B30, 94U },
    4018             :   { AArch64::B31, 95U },
    4019             :   { AArch64::D0, 64U },
    4020             :   { AArch64::D1, 65U },
    4021             :   { AArch64::D2, 66U },
    4022             :   { AArch64::D3, 67U },
    4023             :   { AArch64::D4, 68U },
    4024             :   { AArch64::D5, 69U },
    4025             :   { AArch64::D6, 70U },
    4026             :   { AArch64::D7, 71U },
    4027             :   { AArch64::D8, 72U },
    4028             :   { AArch64::D9, 73U },
    4029             :   { AArch64::D10, 74U },
    4030             :   { AArch64::D11, 75U },
    4031             :   { AArch64::D12, 76U },
    4032             :   { AArch64::D13, 77U },
    4033             :   { AArch64::D14, 78U },
    4034             :   { AArch64::D15, 79U },
    4035             :   { AArch64::D16, 80U },
    4036             :   { AArch64::D17, 81U },
    4037             :   { AArch64::D18, 82U },
    4038             :   { AArch64::D19, 83U },
    4039             :   { AArch64::D20, 84U },
    4040             :   { AArch64::D21, 85U },
    4041             :   { AArch64::D22, 86U },
    4042             :   { AArch64::D23, 87U },
    4043             :   { AArch64::D24, 88U },
    4044             :   { AArch64::D25, 89U },
    4045             :   { AArch64::D26, 90U },
    4046             :   { AArch64::D27, 91U },
    4047             :   { AArch64::D28, 92U },
    4048             :   { AArch64::D29, 93U },
    4049             :   { AArch64::D30, 94U },
    4050             :   { AArch64::D31, 95U },
    4051             :   { AArch64::H0, 64U },
    4052             :   { AArch64::H1, 65U },
    4053             :   { AArch64::H2, 66U },
    4054             :   { AArch64::H3, 67U },
    4055             :   { AArch64::H4, 68U },
    4056             :   { AArch64::H5, 69U },
    4057             :   { AArch64::H6, 70U },
    4058             :   { AArch64::H7, 71U },
    4059             :   { AArch64::H8, 72U },
    4060             :   { AArch64::H9, 73U },
    4061             :   { AArch64::H10, 74U },
    4062             :   { AArch64::H11, 75U },
    4063             :   { AArch64::H12, 76U },
    4064             :   { AArch64::H13, 77U },
    4065             :   { AArch64::H14, 78U },
    4066             :   { AArch64::H15, 79U },
    4067             :   { AArch64::H16, 80U },
    4068             :   { AArch64::H17, 81U },
    4069             :   { AArch64::H18, 82U },
    4070             :   { AArch64::H19, 83U },
    4071             :   { AArch64::H20, 84U },
    4072             :   { AArch64::H21, 85U },
    4073             :   { AArch64::H22, 86U },
    4074             :   { AArch64::H23, 87U },
    4075             :   { AArch64::H24, 88U },
    4076             :   { AArch64::H25, 89U },
    4077             :   { AArch64::H26, 90U },
    4078             :   { AArch64::H27, 91U },
    4079             :   { AArch64::H28, 92U },
    4080             :   { AArch64::H29, 93U },
    4081             :   { AArch64::H30, 94U },
    4082             :   { AArch64::H31, 95U },
    4083             :   { AArch64::P0, 48U },
    4084             :   { AArch64::P1, 49U },
    4085             :   { AArch64::P2, 50U },
    4086             :   { AArch64::P3, 51U },
    4087             :   { AArch64::P4, 52U },
    4088             :   { AArch64::P5, 53U },
    4089             :   { AArch64::P6, 54U },
    4090             :   { AArch64::P7, 55U },
    4091             :   { AArch64::P8, 56U },
    4092             :   { AArch64::P9, 57U },
    4093             :   { AArch64::P10, 58U },
    4094             :   { AArch64::P11, 59U },
    4095             :   { AArch64::P12, 60U },
    4096             :   { AArch64::P13, 61U },
    4097             :   { AArch64::P14, 62U },
    4098             :   { AArch64::P15, 63U },
    4099             :   { AArch64::Q0, 64U },
    4100             :   { AArch64::Q1, 65U },
    4101             :   { AArch64::Q2, 66U },
    4102             :   { AArch64::Q3, 67U },
    4103             :   { AArch64::Q4, 68U },
    4104             :   { AArch64::Q5, 69U },
    4105             :   { AArch64::Q6, 70U },
    4106             :   { AArch64::Q7, 71U },
    4107             :   { AArch64::Q8, 72U },
    4108             :   { AArch64::Q9, 73U },
    4109             :   { AArch64::Q10, 74U },
    4110             :   { AArch64::Q11, 75U },
    4111             :   { AArch64::Q12, 76U },
    4112             :   { AArch64::Q13, 77U },
    4113             :   { AArch64::Q14, 78U },
    4114             :   { AArch64::Q15, 79U },
    4115             :   { AArch64::Q16, 80U },
    4116             :   { AArch64::Q17, 81U },
    4117             :   { AArch64::Q18, 82U },
    4118             :   { AArch64::Q19, 83U },
    4119             :   { AArch64::Q20, 84U },
    4120             :   { AArch64::Q21, 85U },
    4121             :   { AArch64::Q22, 86U },
    4122             :   { AArch64::Q23, 87U },
    4123             :   { AArch64::Q24, 88U },
    4124             :   { AArch64::Q25, 89U },
    4125             :   { AArch64::Q26, 90U },
    4126             :   { AArch64::Q27, 91U },
    4127             :   { AArch64::Q28, 92U },
    4128             :   { AArch64::Q29, 93U },
    4129             :   { AArch64::Q30, 94U },
    4130             :   { AArch64::Q31, 95U },
    4131             :   { AArch64::S0, 64U },
    4132             :   { AArch64::S1, 65U },
    4133             :   { AArch64::S2, 66U },
    4134             :   { AArch64::S3, 67U },
    4135             :   { AArch64::S4, 68U },
    4136             :   { AArch64::S5, 69U },
    4137             :   { AArch64::S6, 70U },
    4138             :   { AArch64::S7, 71U },
    4139             :   { AArch64::S8, 72U },
    4140             :   { AArch64::S9, 73U },
    4141             :   { AArch64::S10, 74U },
    4142             :   { AArch64::S11, 75U },
    4143             :   { AArch64::S12, 76U },
    4144             :   { AArch64::S13, 77U },
    4145             :   { AArch64::S14, 78U },
    4146             :   { AArch64::S15, 79U },
    4147             :   { AArch64::S16, 80U },
    4148             :   { AArch64::S17, 81U },
    4149             :   { AArch64::S18, 82U },
    4150             :   { AArch64::S19, 83U },
    4151             :   { AArch64::S20, 84U },
    4152             :   { AArch64::S21, 85U },
    4153             :   { AArch64::S22, 86U },
    4154             :   { AArch64::S23, 87U },
    4155             :   { AArch64::S24, 88U },
    4156             :   { AArch64::S25, 89U },
    4157             :   { AArch64::S26, 90U },
    4158             :   { AArch64::S27, 91U },
    4159             :   { AArch64::S28, 92U },
    4160             :   { AArch64::S29, 93U },
    4161             :   { AArch64::S30, 94U },
    4162             :   { AArch64::S31, 95U },
    4163             :   { AArch64::W0, 0U },
    4164             :   { AArch64::W1, 1U },
    4165             :   { AArch64::W2, 2U },
    4166             :   { AArch64::W3, 3U },
    4167             :   { AArch64::W4, 4U },
    4168             :   { AArch64::W5, 5U },
    4169             :   { AArch64::W6, 6U },
    4170             :   { AArch64::W7, 7U },
    4171             :   { AArch64::W8, 8U },
    4172             :   { AArch64::W9, 9U },
    4173             :   { AArch64::W10, 10U },
    4174             :   { AArch64::W11, 11U },
    4175             :   { AArch64::W12, 12U },
    4176             :   { AArch64::W13, 13U },
    4177             :   { AArch64::W14, 14U },
    4178             :   { AArch64::W15, 15U },
    4179             :   { AArch64::W16, 16U },
    4180             :   { AArch64::W17, 17U },
    4181             :   { AArch64::W18, 18U },
    4182             :   { AArch64::W19, 19U },
    4183             :   { AArch64::W20, 20U },
    4184             :   { AArch64::W21, 21U },
    4185             :   { AArch64::W22, 22U },
    4186             :   { AArch64::W23, 23U },
    4187             :   { AArch64::W24, 24U },
    4188             :   { AArch64::W25, 25U },
    4189             :   { AArch64::W26, 26U },
    4190             :   { AArch64::W27, 27U },
    4191             :   { AArch64::W28, 28U },
    4192             :   { AArch64::W29, 29U },
    4193             :   { AArch64::W30, 30U },
    4194             :   { AArch64::X0, 0U },
    4195             :   { AArch64::X1, 1U },
    4196             :   { AArch64::X2, 2U },
    4197             :   { AArch64::X3, 3U },
    4198             :   { AArch64::X4, 4U },
    4199             :   { AArch64::X5, 5U },
    4200             :   { AArch64::X6, 6U },
    4201             :   { AArch64::X7, 7U },
    4202             :   { AArch64::X8, 8U },
    4203             :   { AArch64::X9, 9U },
    4204             :   { AArch64::X10, 10U },
    4205             :   { AArch64::X11, 11U },
    4206             :   { AArch64::X12, 12U },
    4207             :   { AArch64::X13, 13U },
    4208             :   { AArch64::X14, 14U },
    4209             :   { AArch64::X15, 15U },
    4210             :   { AArch64::X16, 16U },
    4211             :   { AArch64::X17, 17U },
    4212             :   { AArch64::X18, 18U },
    4213             :   { AArch64::X19, 19U },
    4214             :   { AArch64::X20, 20U },
    4215             :   { AArch64::X21, 21U },
    4216             :   { AArch64::X22, 22U },
    4217             :   { AArch64::X23, 23U },
    4218             :   { AArch64::X24, 24U },
    4219             :   { AArch64::X25, 25U },
    4220             :   { AArch64::X26, 26U },
    4221             :   { AArch64::X27, 27U },
    4222             :   { AArch64::X28, 28U },
    4223             :   { AArch64::Z0, 96U },
    4224             :   { AArch64::Z1, 97U },
    4225             :   { AArch64::Z2, 98U },
    4226             :   { AArch64::Z3, 99U },
    4227             :   { AArch64::Z4, 100U },
    4228             :   { AArch64::Z5, 101U },
    4229             :   { AArch64::Z6, 102U },
    4230             :   { AArch64::Z7, 103U },
    4231             :   { AArch64::Z8, 104U },
    4232             :   { AArch64::Z9, 105U },
    4233             :   { AArch64::Z10, 106U },
    4234             :   { AArch64::Z11, 107U },
    4235             :   { AArch64::Z12, 108U },
    4236             :   { AArch64::Z13, 109U },
    4237             :   { AArch64::Z14, 110U },
    4238             :   { AArch64::Z15, 111U },
    4239             :   { AArch64::Z16, 112U },
    4240             :   { AArch64::Z17, 113U },
    4241             :   { AArch64::Z18, 114U },
    4242             :   { AArch64::Z19, 115U },
    4243             :   { AArch64::Z20, 116U },
    4244             :   { AArch64::Z21, 117U },
    4245             :   { AArch64::Z22, 118U },
    4246             :   { AArch64::Z23, 119U },
    4247             :   { AArch64::Z24, 120U },
    4248             :   { AArch64::Z25, 121U },
    4249             :   { AArch64::Z26, 122U },
    4250             :   { AArch64::Z27, 123U },
    4251             :   { AArch64::Z28, 124U },
    4252             :   { AArch64::Z29, 125U },
    4253             :   { AArch64::Z30, 126U },
    4254             :   { AArch64::Z31, 127U },
    4255             : };
    4256             : extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
    4257             : 
    4258             : extern const uint16_t AArch64RegEncodingTable[] = {
    4259             :   0,
    4260             :   0,
    4261             :   29,
    4262             :   30,
    4263             :   0,
    4264             :   31,
    4265             :   31,
    4266             :   31,
    4267             :   31,
    4268             :   0,
    4269             :   1,
    4270             :   2,
    4271             :   3,
    4272             :   4,
    4273             :   5,
    4274             :   6,
    4275             :   7,
    4276             :   8,
    4277             :   9,
    4278             :   10,
    4279             :   11,
    4280             :   12,
    4281             :   13,
    4282             :   14,
    4283             :   15,
    4284             :   16,
    4285             :   17,
    4286             :   18,
    4287             :   19,
    4288             :   20,
    4289             :   21,
    4290             :   22,
    4291             :   23,
    4292             :   24,
    4293             :   25,
    4294             :   26,
    4295             :   27,
    4296             :   28,
    4297             :   29,
    4298             :   30,
    4299             :   31,
    4300             :   0,
    4301             :   1,
    4302             :   2,
    4303             :   3,
    4304             :   4,
    4305             :   5,
    4306             :   6,
    4307             :   7,
    4308             :   8,
    4309             :   9,
    4310             :   10,
    4311             :   11,
    4312             :   12,
    4313             :   13,
    4314             :   14,
    4315             :   15,
    4316             :   16,
    4317             :   17,
    4318             :   18,
    4319             :   19,
    4320             :   20,
    4321             :   21,
    4322             :   22,
    4323             :   23,
    4324             :   24,
    4325             :   25,
    4326             :   26,
    4327             :   27,
    4328             :   28,
    4329             :   29,
    4330             :   30,
    4331             :   31,
    4332             :   0,
    4333             :   1,
    4334             :   2,
    4335             :   3,
    4336             :   4,
    4337             :   5,
    4338             :   6,
    4339             :   7,
    4340             :   8,
    4341             :   9,
    4342             :   10,
    4343             :   11,
    4344             :   12,
    4345             :   13,
    4346             :   14,
    4347             :   15,
    4348             :   16,
    4349             :   17,
    4350             :   18,
    4351             :   19,
    4352             :   20,
    4353             :   21,
    4354             :   22,
    4355             :   23,
    4356             :   24,
    4357             :   25,
    4358             :   26,
    4359             :   27,
    4360             :   28,
    4361             :   29,
    4362             :   30,
    4363             :   31,
    4364             :   0,
    4365             :   1,
    4366             :   2,
    4367             :   3,
    4368             :   4,
    4369             :   5,
    4370             :   6,
    4371             :   7,
    4372             :   8,
    4373             :   9,
    4374             :   10,
    4375             :   11,
    4376             :   12,
    4377             :   13,
    4378             :   14,
    4379             :   15,
    4380             :   0,
    4381             :   1,
    4382             :   2,
    4383             :   3,
    4384             :   4,
    4385             :   5,
    4386             :   6,
    4387             :   7,
    4388             :   8,
    4389             :   9,
    4390             :   10,
    4391             :   11,
    4392             :   12,
    4393             :   13,
    4394             :   14,
    4395             :   15,
    4396             :   16,
    4397             :   17,
    4398             :   18,
    4399             :   19,
    4400             :   20,
    4401             :   21,
    4402             :   22,
    4403             :   23,
    4404             :   24,
    4405             :   25,
    4406             :   26,
    4407             :   27,
    4408             :   28,
    4409             :   29,
    4410             :   30,
    4411             :   31,
    4412             :   0,
    4413             :   1,
    4414             :   2,
    4415             :   3,
    4416             :   4,
    4417             :   5,
    4418             :   6,
    4419             :   7,
    4420             :   8,
    4421             :   9,
    4422             :   10,
    4423             :   11,
    4424             :   12,
    4425             :   13,
    4426             :   14,
    4427             :   15,
    4428             :   16,
    4429             :   17,
    4430             :   18,
    4431             :   19,
    4432             :   20,
    4433             :   21,
    4434             :   22,
    4435             :   23,
    4436             :   24,
    4437             :   25,
    4438             :   26,
    4439             :   27,
    4440             :   28,
    4441             :   29,
    4442             :   30,
    4443             :   31,
    4444             :   0,
    4445             :   1,
    4446             :   2,
    4447             :   3,
    4448             :   4,
    4449             :   5,
    4450             :   6,
    4451             :   7,
    4452             :   8,
    4453             :   9,
    4454             :   10,
    4455             :   11,
    4456             :   12,
    4457             :   13,
    4458             :   14,
    4459             :   15,
    4460             :   16,
    4461             :   17,
    4462             :   18,
    4463             :   19,
    4464             :   20,
    4465             :   21,
    4466             :   22,
    4467             :   23,
    4468             :   24,
    4469             :   25,
    4470             :   26,
    4471             :   27,
    4472             :   28,
    4473             :   29,
    4474             :   30,
    4475             :   0,
    4476             :   1,
    4477             :   2,
    4478             :   3,
    4479             :   4,
    4480             :   5,
    4481             :   6,
    4482             :   7,
    4483             :   8,
    4484             :   9,
    4485             :   10,
    4486             :   11,
    4487             :   12,
    4488             :   13,
    4489             :   14,
    4490             :   15,
    4491             :   16,
    4492             :   17,
    4493             :   18,
    4494             :   19,
    4495             :   20,
    4496             :   21,
    4497             :   22,
    4498             :   23,
    4499             :   24,
    4500             :   25,
    4501             :   26,
    4502             :   27,
    4503             :   28,
    4504             :   0,
    4505             :   1,
    4506             :   2,
    4507             :   3,
    4508             :   4,
    4509             :   5,
    4510             :   6,
    4511             :   7,
    4512             :   8,
    4513             :   9,
    4514             :   10,
    4515             :   11,
    4516             :   12,
    4517             :   13,
    4518             :   14,
    4519             :   15,
    4520             :   16,
    4521             :   17,
    4522             :   18,
    4523             :   19,
    4524             :   20,
    4525             :   21,
    4526             :   22,
    4527             :   23,
    4528             :   24,
    4529             :   25,
    4530             :   26,
    4531             :   27,
    4532             :   28,
    4533             :   29,
    4534             :   30,
    4535             :   31,
    4536             :   0,
    4537             :   1,
    4538             :   2,
    4539             :   3,
    4540             :   4,
    4541             :   5,
    4542             :   6,
    4543             :   7,
    4544             :   8,
    4545             :   9,
    4546             :   10,
    4547             :   11,
    4548             :   12,
    4549             :   13,
    4550             :   14,
    4551             :   15,
    4552             :   16,
    4553             :   17,
    4554             :   18,
    4555             :   19,
    4556             :   20,
    4557             :   21,
    4558             :   22,
    4559             :   23,
    4560             :   24,
    4561             :   25,
    4562             :   26,
    4563             :   27,
    4564             :   28,
    4565             :   29,
    4566             :   30,
    4567             :   31,
    4568             :   0,
    4569             :   1,
    4570             :   2,
    4571             :   3,
    4572             :   4,
    4573             :   5,
    4574             :   6,
    4575             :   7,
    4576             :   8,
    4577             :   9,
    4578             :   10,
    4579             :   11,
    4580             :   12,
    4581             :   13,
    4582             :   14,
    4583             :   15,
    4584             :   16,
    4585             :   17,
    4586             :   18,
    4587             :   19,
    4588             :   20,
    4589             :   21,
    4590             :   22,
    4591             :   23,
    4592             :   24,
    4593             :   25,
    4594             :   26,
    4595             :   27,
    4596             :   28,
    4597             :   29,
    4598             :   30,
    4599             :   31,
    4600             :   0,
    4601             :   1,
    4602             :   2,
    4603             :   3,
    4604             :   4,
    4605             :   5,
    4606             :   6,
    4607             :   7,
    4608             :   8,
    4609             :   9,
    4610             :   10,
    4611             :   11,
    4612             :   12,
    4613             :   13,
    4614             :   14,
    4615             :   15,
    4616             :   16,
    4617             :   17,
    4618             :   18,
    4619             :   19,
    4620             :   20,
    4621             :   21,
    4622             :   22,
    4623             :   23,
    4624             :   24,
    4625             :   25,
    4626             :   26,
    4627             :   27,
    4628             :   28,
    4629             :   29,
    4630             :   30,
    4631             :   31,
    4632             :   0,
    4633             :   1,
    4634             :   2,
    4635             :   3,
    4636             :   4,
    4637             :   5,
    4638             :   6,
    4639             :   7,
    4640             :   8,
    4641             :   9,
    4642             :   10,
    4643             :   11,
    4644             :   12,
    4645             :   13,
    4646             :   14,
    4647             :   15,
    4648             :   16,
    4649             :   17,
    4650             :   18,
    4651             :   19,
    4652             :   20,
    4653             :   21,
    4654             :   22,
    4655             :   23,
    4656             :   24,
    4657             :   25,
    4658             :   26,
    4659             :   27,
    4660             :   28,
    4661             :   29,
    4662             :   30,
    4663             :   31,
    4664             :   0,
    4665             :   1,
    4666             :   2,
    4667             :   3,
    4668             :   4,
    4669             :   5,
    4670             :   6,
    4671             :   7,
    4672             :   8,
    4673             :   9,
    4674             :   10,
    4675             :   11,
    4676             :   12,
    4677             :   13,
    4678             :   14,
    4679             :   15,
    4680             :   16,
    4681             :   17,
    4682             :   18,
    4683             :   19,
    4684             :   20,
    4685             :   21,
    4686             :   22,
    4687             :   23,
    4688             :   24,
    4689             :   25,
    4690             :   26,
    4691             :   27,
    4692             :   28,
    4693             :   29,
    4694             :   30,
    4695             :   31,
    4696             :   0,
    4697             :   1,
    4698             :   2,
    4699             :   3,
    4700             :   4,
    4701             :   5,
    4702             :   6,
    4703             :   7,
    4704             :   8,
    4705             :   9,
    4706             :   10,
    4707             :   11,
    4708             :   12,
    4709             :   13,
    4710             :   14,
    4711             :   15,
    4712             :   16,
    4713             :   17,
    4714             :   18,
    4715             :   19,
    4716             :   20,
    4717             :   21,
    4718             :   22,
    4719             :   23,
    4720             :   24,
    4721             :   25,
    4722             :   26,
    4723             :   27,
    4724             :   28,
    4725             :   29,
    4726             :   30,
    4727             :   31,
    4728             :   0,
    4729             :   1,
    4730             :   2,
    4731             :   3,
    4732             :   4,
    4733             :   5,
    4734             :   6,
    4735             :   7,
    4736             :   8,
    4737             :   9,
    4738             :   10,
    4739             :   11,
    4740             :   12,
    4741             :   13,
    4742             :   14,
    4743             :   15,
    4744             :   16,
    4745             :   17,
    4746             :   18,
    4747             :   19,
    4748             :   20,
    4749             :   21,
    4750             :   22,
    4751             :   23,
    4752             :   24,
    4753             :   25,
    4754             :   26,
    4755             :   27,
    4756             :   28,
    4757             :   29,
    4758             :   30,
    4759             :   31,
    4760             :   31,
    4761             :   30,
    4762             :   0,
    4763             :   1,
    4764             :   2,
    4765             :   3,
    4766             :   4,
    4767             :   5,
    4768             :   6,
    4769             :   7,
    4770             :   8,
    4771             :   9,
    4772             :   10,
    4773             :   11,
    4774             :   12,
    4775             :   13,
    4776             :   14,
    4777             :   15,
    4778             :   16,
    4779             :   17,
    4780             :   18,
    4781             :   19,
    4782             :   20,
    4783             :   21,
    4784             :   22,
    4785             :   23,
    4786             :   24,
    4787             :   25,
    4788             :   26,
    4789             :   27,
    4790             :   28,
    4791             :   29,
    4792             :   29,
    4793             :   30,
    4794             :   31,
    4795             :   28,
    4796             :   0,
    4797             :   1,
    4798             :   2,
    4799             :   3,
    4800             :   4,
    4801             :   5,
    4802             :   6,
    4803             :   7,
    4804             :   8,
    4805             :   9,
    4806             :   10,
    4807             :   11,
    4808             :   12,
    4809             :   13,
    4810             :   14,
    4811             :   15,
    4812             :   16,
    4813             :   17,
    4814             :   18,
    4815             :   19,
    4816             :   20,
    4817             :   21,
    4818             :   22,
    4819             :   23,
    4820             :   24,
    4821             :   25,
    4822             :   26,
    4823             :   27,
    4824             :   0,
    4825             :   1,
    4826             :   2,
    4827             :   3,
    4828             :   4,
    4829             :   5,
    4830             :   6,
    4831             :   7,
    4832             :   8,
    4833             :   9,
    4834             :   10,
    4835             :   11,
    4836             :   12,
    4837             :   13,
    4838             :   14,
    4839             :   15,
    4840             :   16,
    4841             :   17,
    4842             :   18,
    4843             :   19,
    4844             :   20,
    4845             :   21,
    4846             :   22,
    4847             :   23,
    4848             :   24,
    4849             :   25,
    4850             :   26,
    4851             :   27,
    4852             :   28,
    4853             :   29,
    4854             :   30,
    4855             :   31,
    4856             :   0,
    4857             :   1,
    4858             :   2,
    4859             :   3,
    4860             :   4,
    4861             :   5,
    4862             :   6,
    4863             :   7,
    4864             :   8,
    4865             :   9,
    4866             :   10,
    4867             :   11,
    4868             :   12,
    4869             :   13,
    4870             :   14,
    4871             :   15,
    4872             :   16,
    4873             :   17,
    4874             :   18,
    4875             :   19,
    4876             :   20,
    4877             :   21,
    4878             :   22,
    4879             :   23,
    4880             :   24,
    4881             :   25,
    4882             :   26,
    4883             :   27,
    4884             :   28,
    4885             :   29,
    4886             :   30,
    4887             :   31,
    4888             :   0,
    4889             :   1,
    4890             :   2,
    4891             :   3,
    4892             :   4,
    4893             :   5,
    4894             :   6,
    4895             :   7,
    4896             :   8,
    4897             :   9,
    4898             :   10,
    4899             :   11,
    4900             :   12,
    4901             :   13,
    4902             :   14,
    4903             :   15,
    4904             :   16,
    4905             :   17,
    4906             :   18,
    4907             :   19,
    4908             :   20,
    4909             :   21,
    4910             :   22,
    4911             :   23,
    4912             :   24,
    4913             :   25,
    4914             :   26,
    4915             :   27,
    4916             :   28,
    4917             :   29,
    4918             :   30,
    4919             :   31,
    4920             : };
    4921             : static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
    4922             :   RI->InitMCRegisterInfo(AArch64RegDesc, 661, RA, PC, AArch64MCRegisterClasses, 100, AArch64RegUnitRoots, 115, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 100,
    4923             : AArch64SubRegIdxRanges, AArch64RegEncodingTable);
    4924             : 
    4925             :   switch (DwarfFlavour) {
    4926             :   default:
    4927             :     llvm_unreachable("Unknown DWARF flavour");
    4928             :   case 0:
    4929             :     RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
    4930             :     break;
    4931             :   }
    4932             :   switch (EHFlavour) {
    4933             :   default:
    4934             :     llvm_unreachable("Unknown DWARF flavour");
    4935             :   case 0:
    4936             :     RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
    4937             :     break;
    4938             :   }
    4939             :   switch (DwarfFlavour) {
    4940             :   default:
    4941             :     llvm_unreachable("Unknown DWARF flavour");
    4942             :   case 0:
    4943             :     RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
    4944             :     break;
    4945             :   }
    4946             :   switch (EHFlavour) {
    4947             :   default:
    4948             :     llvm_unreachable("Unknown DWARF flavour");
    4949             :   case 0:
    4950             :     RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
    4951             :     break;
    4952             :   }
    4953             : }
    4954             : 
    4955             : } // end namespace llvm
    4956             : 
    4957             : #endif // GET_REGINFO_MC_DESC
    4958             : 
    4959             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    4960             : |*                                                                            *|
    4961             : |* Register Information Header Fragment                                       *|
    4962             : |*                                                                            *|
    4963             : |* Automatically generated file, do not edit!                                 *|
    4964             : |*                                                                            *|
    4965             : \*===----------------------------------------------------------------------===*/
    4966             : 
    4967             : 
    4968             : #ifdef GET_REGINFO_HEADER
    4969             : #undef GET_REGINFO_HEADER
    4970             : 
    4971             : #include "llvm/CodeGen/TargetRegisterInfo.h"
    4972             : 
    4973             : namespace llvm {
    4974             : 
    4975             : class AArch64FrameLowering;
    4976             : 
    4977        1411 : struct AArch64GenRegisterInfo : public TargetRegisterInfo {
    4978             :   explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
    4979             :       unsigned PC = 0, unsigned HwMode = 0);
    4980             :   unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
    4981             :   LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    4982             :   LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    4983             :   const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
    4984             :   const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
    4985             :   unsigned getRegUnitWeight(unsigned RegUnit) const override;
    4986             :   unsigned getNumRegPressureSets() const override;
    4987             :   const char *getRegPressureSetName(unsigned Idx) const override;
    4988             :   unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
    4989             :   const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
    4990             :   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
    4991             :   ArrayRef<const char *> getRegMaskNames() const override;
    4992             :   ArrayRef<const uint32_t *> getRegMasks() const override;
    4993             :   /// Devirtualized TargetFrameLowering.
    4994             :   static const AArch64FrameLowering *getFrameLowering(
    4995             :       const MachineFunction &MF);
    4996             : };
    4997             : 
    4998             : namespace AArch64 { // Register classes
    4999             :   extern const TargetRegisterClass FPR8RegClass;
    5000             :   extern const TargetRegisterClass FPR16RegClass;
    5001             :   extern const TargetRegisterClass PPRRegClass;
    5002             :   extern const TargetRegisterClass PPR_3bRegClass;
    5003             :   extern const TargetRegisterClass GPR32allRegClass;
    5004             :   extern const TargetRegisterClass FPR32RegClass;
    5005             :   extern const TargetRegisterClass GPR32RegClass;
    5006             :   extern const TargetRegisterClass GPR32spRegClass;
    5007             :   extern const TargetRegisterClass GPR32commonRegClass;
    5008             :   extern const TargetRegisterClass CCRRegClass;
    5009             :   extern const TargetRegisterClass GPR32sponlyRegClass;
    5010             :   extern const TargetRegisterClass WSeqPairsClassRegClass;
    5011             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass;
    5012             :   extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
    5013             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
    5014             :   extern const TargetRegisterClass GPR64allRegClass;
    5015             :   extern const TargetRegisterClass FPR64RegClass;
    5016             :   extern const TargetRegisterClass GPR64RegClass;
    5017             :   extern const TargetRegisterClass GPR64spRegClass;
    5018             :   extern const TargetRegisterClass GPR64commonRegClass;
    5019             :   extern const TargetRegisterClass tcGPR64RegClass;
    5020             :   extern const TargetRegisterClass GPR64sponlyRegClass;
    5021             :   extern const TargetRegisterClass DDRegClass;
    5022             :   extern const TargetRegisterClass XSeqPairsClassRegClass;
    5023             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass;
    5024             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
    5025             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
    5026             :   extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
    5027             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
    5028             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
    5029             :   extern const TargetRegisterClass FPR128RegClass;
    5030             :   extern const TargetRegisterClass ZPRRegClass;
    5031             :   extern const TargetRegisterClass FPR128_loRegClass;
    5032             :   extern const TargetRegisterClass ZPR_4bRegClass;
    5033             :   extern const TargetRegisterClass ZPR_3bRegClass;
    5034             :   extern const TargetRegisterClass DDDRegClass;
    5035             :   extern const TargetRegisterClass DDDDRegClass;
    5036             :   extern const TargetRegisterClass QQRegClass;
    5037             :   extern const TargetRegisterClass ZPR2RegClass;
    5038             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
    5039             :   extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;
    5040             :   extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass;
    5041             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass;
    5042             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass;
    5043             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass;
    5044             :   extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass;
    5045             :   extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass;
    5046             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass;
    5047             :   extern const TargetRegisterClass QQQRegClass;
    5048             :   extern const TargetRegisterClass ZPR3RegClass;
    5049             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass;
    5050             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass;
    5051             :   extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass;
    5052             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass;
    5053             :   extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass;
    5054             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass;
    5055             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass;
    5056             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
    5057             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
    5058             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass;
    5059             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
    5060             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
    5061             :   extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass;
    5062             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass;
    5063             :   extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass;
    5064             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
    5065             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass;
    5066             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
    5067             :   extern const TargetRegisterClass QQQQRegClass;
    5068             :   extern const TargetRegisterClass ZPR4RegClass;
    5069             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass;
    5070             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass;
    5071             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass;
    5072             :   extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass;
    5073             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass;
    5074             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass;
    5075             :   extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass;
    5076             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass;
    5077             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass;
    5078             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
    5079             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    5080             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;
    5081             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
    5082             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass;
    5083             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
    5084             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    5085             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
    5086             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;
    5087             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
    5088             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
    5089             :   extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass;
    5090             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass;
    5091             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass;
    5092             :   extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass;
    5093             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass;
    5094             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
    5095             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass;
    5096             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
    5097             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass;
    5098             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
    5099             : } // end namespace AArch64
    5100             : 
    5101             : } // end namespace llvm
    5102             : 
    5103             : #endif // GET_REGINFO_HEADER
    5104             : 
    5105             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    5106             : |*                                                                            *|
    5107             : |* Target Register and Register Classes Information                           *|
    5108             : |*                                                                            *|
    5109             : |* Automatically generated file, do not edit!                                 *|
    5110             : |*                                                                            *|
    5111             : \*===----------------------------------------------------------------------===*/
    5112             : 
    5113             : 
    5114             : #ifdef GET_REGINFO_TARGET_DESC
    5115             : #undef GET_REGINFO_TARGET_DESC
    5116             : 
    5117             : namespace llvm {
    5118             : 
    5119             : extern const MCRegisterClass AArch64MCRegisterClasses[];
    5120             : 
    5121             : static const MVT::SimpleValueType VTLists[] = {
    5122             :   /* 0 */ MVT::f32, MVT::i32, MVT::Other,
    5123             :   /* 3 */ MVT::i64, MVT::Other,
    5124             :   /* 5 */ MVT::f16, MVT::Other,
    5125             :   /* 7 */ MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::Other,
    5126             :   /* 12 */ MVT::f64, MVT::i64, MVT::v2f32, MVT::v1f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v4f16, MVT::Other,
    5127             :   /* 22 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::v8f16, MVT::Other,
    5128             :   /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
    5129             :   /* 39 */ MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64, MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv1f32, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv1f64, MVT::nxv2f64, MVT::Other,
    5130             :   /* 52 */ MVT::Untyped, MVT::Other,
    5131             : };
    5132             : 
    5133             : static const char *const SubRegIndexNameTable[] = { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1", "qsub2", "qsub3", "ssub", "sub_32", "sube32", "sube64", "subo32", "subo64", "zsub", "zsub0", "zsub1", "zsub2", "zsub3", "zsub_hi", "dsub1_then_bsub", "dsub1_then_hsub", "dsub1_then_ssub", "dsub3_then_bsub", "dsub3_then_hsub", "dsub3_then_ssub", "dsub2_then_bsub", "dsub2_then_hsub", "dsub2_then_ssub", "qsub1_then_bsub", "qsub1_then_dsub", "qsub1_then_hsub", "qsub1_then_ssub", "qsub3_then_bsub", "qsub3_then_dsub", "qsub3_then_hsub", "qsub3_then_ssub", "qsub2_then_bsub", "qsub2_then_dsub", "qsub2_then_hsub", "qsub2_then_ssub", "subo64_then_sub_32", "zsub1_then_bsub", "zsub1_then_dsub", "zsub1_then_hsub", "zsub1_then_ssub", "zsub1_then_zsub", "zsub1_then_zsub_hi", "zsub3_then_bsub", "zsub3_then_dsub", "zsub3_then_hsub", "zsub3_then_ssub", "zsub3_then_zsub", "zsub3_then_zsub_hi", "zsub2_then_bsub", "zsub2_then_dsub", "zsub2_then_hsub", "zsub2_then_ssub", "zsub2_then_zsub", "zsub2_then_zsub_hi", "dsub0_dsub1", "dsub0_dsub1_dsub2", "dsub1_dsub2", "dsub1_dsub2_dsub3", "dsub2_dsub3", "dsub_qsub1_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub", "qsub0_qsub1", "qsub0_qsub1_qsub2", "qsub1_qsub2", "qsub1_qsub2_qsub3", "qsub2_qsub3", "qsub1_then_dsub_qsub2_then_dsub", "qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "qsub2_then_dsub_qsub3_then_dsub", "sub_32_subo64_then_sub_32", "dsub_zsub1_then_dsub", "zsub_zsub1_then_zsub", "dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub", "dsub_zsub1_then_dsub_zsub2_then_dsub", "zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub", "zsub_zsub1_then_zsub_zsub2_then_zsub", "zsub0_zsub1", "zsub0_zsub1_zsub2", "zsub1_zsub2", "zsub1_zsub2_zsub3", "zsub2_zsub3", "zsub1_then_dsub_zsub2_then_dsub", "zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub", "zsub1_then_zsub_zsub2_then_zsub", "zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub", "zsub2_then_dsub_zsub3_then_dsub", "zsub2_then_zsub_zsub3_then_zsub", "" };
    5134             : 
    5135             : 
    5136             : static const LaneBitmask SubRegIndexLaneMaskTable[] = {
    5137             :   LaneBitmask::getAll(),
    5138             :   LaneBitmask(0x00000001), // bsub
    5139             :   LaneBitmask(0x00000001), // dsub
    5140             :   LaneBitmask(0x00000001), // dsub0
    5141             :   LaneBitmask(0x00000080), // dsub1
    5142             :   LaneBitmask(0x00000200), // dsub2
    5143             :   LaneBitmask(0x00000100), // dsub3
    5144             :   LaneBitmask(0x00000001), // hsub
    5145             :   LaneBitmask(0x00000002), // qhisub
    5146             :   LaneBitmask(0x00000004), // qsub
    5147             :   LaneBitmask(0x00000001), // qsub0
    5148             :   LaneBitmask(0x00000400), // qsub1
    5149             :   LaneBitmask(0x00001000), // qsub2
    5150             :   LaneBitmask(0x00000800), // qsub3
    5151             :   LaneBitmask(0x00000001), // ssub
    5152             :   LaneBitmask(0x00000008), // sub_32
    5153             :   LaneBitmask(0x00000010), // sube32
    5154             :   LaneBitmask(0x00000008), // sube64
    5155             :   LaneBitmask(0x00000020), // subo32
    5156             :   LaneBitmask(0x00002000), // subo64
    5157             :   LaneBitmask(0x00000001), // zsub
    5158             :   LaneBitmask(0x00000041), // zsub0
    5159             :   LaneBitmask(0x0000C000), // zsub1
    5160             :   LaneBitmask(0x000C0000), // zsub2
    5161             :   LaneBitmask(0x00030000), // zsub3
    5162             :   LaneBitmask(0x00000040), // zsub_hi
    5163             :   LaneBitmask(0x00000080), // dsub1_then_bsub
    5164             :   LaneBitmask(0x00000080), // dsub1_then_hsub
    5165             :   LaneBitmask(0x00000080), // dsub1_then_ssub
    5166             :   LaneBitmask(0x00000100), // dsub3_then_bsub
    5167             :   LaneBitmask(0x00000100), // dsub3_then_hsub
    5168             :   LaneBitmask(0x00000100), // dsub3_then_ssub
    5169             :   LaneBitmask(0x00000200), // dsub2_then_bsub
    5170             :   LaneBitmask(0x00000200), // dsub2_then_hsub
    5171             :   LaneBitmask(0x00000200), // dsub2_then_ssub
    5172             :   LaneBitmask(0x00000400), // qsub1_then_bsub
    5173             :   LaneBitmask(0x00000400), // qsub1_then_dsub
    5174             :   LaneBitmask(0x00000400), // qsub1_then_hsub
    5175             :   LaneBitmask(0x00000400), // qsub1_then_ssub
    5176             :   LaneBitmask(0x00000800), // qsub3_then_bsub
    5177             :   LaneBitmask(0x00000800), // qsub3_then_dsub
    5178             :   LaneBitmask(0x00000800), // qsub3_then_hsub
    5179             :   LaneBitmask(0x00000800), // qsub3_then_ssub
    5180             :   LaneBitmask(0x00001000), // qsub2_then_bsub
    5181             :   LaneBitmask(0x00001000), // qsub2_then_dsub
    5182             :   LaneBitmask(0x00001000), // qsub2_then_hsub
    5183             :   LaneBitmask(0x00001000), // qsub2_then_ssub
    5184             :   LaneBitmask(0x00002000), // subo64_then_sub_32
    5185             :   LaneBitmask(0x00004000), // zsub1_then_bsub
    5186             :   LaneBitmask(0x00004000), // zsub1_then_dsub
    5187             :   LaneBitmask(0x00004000), // zsub1_then_hsub
    5188             :   LaneBitmask(0x00004000), // zsub1_then_ssub
    5189             :   LaneBitmask(0x00004000), // zsub1_then_zsub
    5190             :   LaneBitmask(0x00008000), // zsub1_then_zsub_hi
    5191             :   LaneBitmask(0x00010000), // zsub3_then_bsub
    5192             :   LaneBitmask(0x00010000), // zsub3_then_dsub
    5193             :   LaneBitmask(0x00010000), // zsub3_then_hsub
    5194             :   LaneBitmask(0x00010000), // zsub3_then_ssub
    5195             :   LaneBitmask(0x00010000), // zsub3_then_zsub
    5196             :   LaneBitmask(0x00020000), // zsub3_then_zsub_hi
    5197             :   LaneBitmask(0x00040000), // zsub2_then_bsub
    5198             :   LaneBitmask(0x00040000), // zsub2_then_dsub
    5199             :   LaneBitmask(0x00040000), // zsub2_then_hsub
    5200             :   LaneBitmask(0x00040000), // zsub2_then_ssub
    5201             :   LaneBitmask(0x00040000), // zsub2_then_zsub
    5202             :   LaneBitmask(0x00080000), // zsub2_then_zsub_hi
    5203             :   LaneBitmask(0x00000081), // dsub0_dsub1
    5204             :   LaneBitmask(0x00000281), // dsub0_dsub1_dsub2
    5205             :   LaneBitmask(0x00000280), // dsub1_dsub2
    5206             :   LaneBitmask(0x00000380), // dsub1_dsub2_dsub3
    5207             :   LaneBitmask(0x00000300), // dsub2_dsub3
    5208             :   LaneBitmask(0x00000401), // dsub_qsub1_then_dsub
    5209             :   LaneBitmask(0x00001C01), // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5210             :   LaneBitmask(0x00001401), // dsub_qsub1_then_dsub_qsub2_then_dsub
    5211             :   LaneBitmask(0x00000401), // qsub0_qsub1
    5212             :   LaneBitmask(0x00001401), // qsub0_qsub1_qsub2
    5213             :   LaneBitmask(0x00001400), // qsub1_qsub2
    5214             :   LaneBitmask(0x00001C00), // qsub1_qsub2_qsub3
    5215             :   LaneBitmask(0x00001800), // qsub2_qsub3
    5216             :   LaneBitmask(0x00001400), // qsub1_then_dsub_qsub2_then_dsub
    5217             :   LaneBitmask(0x00001C00), // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5218             :   LaneBitmask(0x00001800), // qsub2_then_dsub_qsub3_then_dsub
    5219             :   LaneBitmask(0x00002008), // sub_32_subo64_then_sub_32
    5220             :   LaneBitmask(0x00004001), // dsub_zsub1_then_dsub
    5221             :   LaneBitmask(0x00004001), // zsub_zsub1_then_zsub
    5222             :   LaneBitmask(0x00054001), // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    5223             :   LaneBitmask(0x00044001), // dsub_zsub1_then_dsub_zsub2_then_dsub
    5224             :   LaneBitmask(0x00054001), // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5225             :   LaneBitmask(0x00044001), // zsub_zsub1_then_zsub_zsub2_then_zsub
    5226             :   LaneBitmask(0x0000C041), // zsub0_zsub1
    5227             :   LaneBitmask(0x000CC041), // zsub0_zsub1_zsub2
    5228             :   LaneBitmask(0x000CC000), // zsub1_zsub2
    5229             :   LaneBitmask(0x000FC000), // zsub1_zsub2_zsub3
    5230             :   LaneBitmask(0x000F0000), // zsub2_zsub3
    5231             :   LaneBitmask(0x00044000), // zsub1_then_dsub_zsub2_then_dsub
    5232             :   LaneBitmask(0x00054000), // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    5233             :   LaneBitmask(0x00044000), // zsub1_then_zsub_zsub2_then_zsub
    5234             :   LaneBitmask(0x00054000), // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5235             :   LaneBitmask(0x00050000), // zsub2_then_dsub_zsub3_then_dsub
    5236             :   LaneBitmask(0x00050000), // zsub2_then_zsub_zsub3_then_zsub
    5237             :  };
    5238             : 
    5239             : 
    5240             : 
    5241             : static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
    5242             :   // Mode = 0 (Default)
    5243             :   { 8, 8, 8, VTLists+52 },    // FPR8
    5244             :   { 16, 16, 16, VTLists+5 },    // FPR16
    5245             :   { 16, 16, 16, VTLists+7 },    // PPR
    5246             :   { 16, 16, 16, VTLists+7 },    // PPR_3b
    5247             :   { 32, 32, 32, VTLists+1 },    // GPR32all
    5248             :   { 32, 32, 32, VTLists+0 },    // FPR32
    5249             :   { 32, 32, 32, VTLists+1 },    // GPR32
    5250             :   { 32, 32, 32, VTLists+1 },    // GPR32sp
    5251             :   { 32, 32, 32, VTLists+1 },    // GPR32common
    5252             :   { 32, 32, 32, VTLists+1 },    // CCR
    5253             :   { 32, 32, 32, VTLists+1 },    // GPR32sponly
    5254             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass
    5255             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_sube32_in_GPR32common
    5256             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_subo32_in_GPR32common
    5257             :   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
    5258             :   { 64, 64, 64, VTLists+3 },    // GPR64all
    5259             :   { 64, 64, 64, VTLists+12 },    // FPR64
    5260             :   { 64, 64, 64, VTLists+3 },    // GPR64
    5261             :   { 64, 64, 64, VTLists+3 },    // GPR64sp
    5262             :   { 64, 64, 64, VTLists+3 },    // GPR64common
    5263             :   { 64, 64, 64, VTLists+3 },    // tcGPR64
    5264             :   { 64, 64, 64, VTLists+3 },    // GPR64sponly
    5265             :   { 128, 128, 64, VTLists+52 },    // DD
    5266             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass
    5267             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common
    5268             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_GPR64common
    5269             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
    5270             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sube64_in_tcGPR64
    5271             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_tcGPR64
    5272             :   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
    5273             :   { 128, 128, 128, VTLists+22 },    // FPR128
    5274             :   { 128, 128, 128, VTLists+39 },    // ZPR
    5275             :   { 128, 128, 128, VTLists+31 },    // FPR128_lo
    5276             :   { 128, 128, 128, VTLists+39 },    // ZPR_4b
    5277             :   { 128, 128, 128, VTLists+39 },    // ZPR_3b
    5278             :   { 192, 192, 64, VTLists+52 },    // DDD
    5279             :   { 256, 256, 64, VTLists+52 },    // DDDD
    5280             :   { 256, 256, 128, VTLists+52 },    // QQ
    5281             :   { 256, 256, 128, VTLists+52 },    // ZPR2
    5282             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub0_in_FPR128_lo
    5283             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub1_in_FPR128_lo
    5284             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub1_in_ZPR_4b
    5285             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub_in_FPR128_lo
    5286             :   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
    5287             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
    5288             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub0_in_ZPR_3b
    5289             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub1_in_ZPR_3b
    5290             :   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
    5291             :   { 384, 384, 128, VTLists+52 },    // QQQ
    5292             :   { 384, 384, 128, VTLists+52 },    // ZPR3
    5293             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo
    5294             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub1_in_FPR128_lo
    5295             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub2_in_FPR128_lo
    5296             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_4b
    5297             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub2_in_ZPR_4b
    5298             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo
    5299             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
    5300             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    5301             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
    5302             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
    5303             :   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
    5304             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
    5305             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub0_in_ZPR_3b
    5306             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_3b
    5307             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub2_in_ZPR_3b
    5308             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
    5309             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
    5310             :   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
    5311             :   { 512, 512, 128, VTLists+52 },    // QQQQ
    5312             :   { 512, 512, 128, VTLists+52 },    // ZPR4
    5313             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo
    5314             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo
    5315             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub2_in_FPR128_lo
    5316             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub3_in_FPR128_lo
    5317             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_4b
    5318             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_4b
    5319             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub3_in_ZPR_4b
    5320             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo
    5321             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
    5322             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    5323             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    5324             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
    5325             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
    5326             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
    5327             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
    5328             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    5329             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
    5330             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
    5331             :   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
    5332             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
    5333             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub0_in_ZPR_3b
    5334             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_3b
    5335             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_3b
    5336             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub3_in_ZPR_3b
    5337             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
    5338             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
    5339             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
    5340             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
    5341             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
    5342             :   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
    5343             : };
    5344             : 
    5345             : static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
    5346             : 
    5347             : static const uint32_t FPR8SubClassMask[] = {
    5348             :   0x00000001, 0x00000000, 0x00000000, 0x00000000, 
    5349             :   0xc0410022, 0xffffffff, 0xffffffff, 0x0000000f, // bsub
    5350             :   0x00400000, 0x00000018, 0x00000000, 0x00000000, // dsub1_then_bsub
    5351             :   0x00000000, 0x00000010, 0x00000000, 0x00000000, // dsub3_then_bsub
    5352             :   0x00000000, 0x00000018, 0x00000000, 0x00000000, // dsub2_then_bsub
    5353             :   0x00000000, 0x131d09a0, 0x0131c3d0, 0x00000000, // qsub1_then_bsub
    5354             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub3_then_bsub
    5355             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // qsub2_then_bsub
    5356             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // zsub1_then_bsub
    5357             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub3_then_bsub
    5358             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub2_then_bsub
    5359             : };
    5360             : 
    5361             : static const uint32_t FPR16SubClassMask[] = {
    5362             :   0x00000002, 0x00000000, 0x00000000, 0x00000000, 
    5363             :   0xc0410020, 0xffffffff, 0xffffffff, 0x0000000f, // hsub
    5364             :   0x00400000, 0x00000018, 0x00000000, 0x00000000, // dsub1_then_hsub
    5365             :   0x00000000, 0x00000010, 0x00000000, 0x00000000, // dsub3_then_hsub
    5366             :   0x00000000, 0x00000018, 0x00000000, 0x00000000, // dsub2_then_hsub
    5367             :   0x00000000, 0x131d09a0, 0x0131c3d0, 0x00000000, // qsub1_then_hsub
    5368             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub3_then_hsub
    5369             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // qsub2_then_hsub
    5370             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // zsub1_then_hsub
    5371             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub3_then_hsub
    5372             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub2_then_hsub
    5373             : };
    5374             : 
    5375             : static const uint32_t PPRSubClassMask[] = {
    5376             :   0x0000000c, 0x00000000, 0x00000000, 0x00000000, 
    5377             : };
    5378             : 
    5379             : static const uint32_t PPR_3bSubClassMask[] = {
    5380             :   0x00000008, 0x00000000, 0x00000000, 0x00000000, 
    5381             : };
    5382             : 
    5383             : static const uint32_t GPR32allSubClassMask[] = {
    5384             :   0x000005d0, 0x00000000, 0x00000000, 0x00000000, 
    5385             :   0x3fbe8000, 0x00000000, 0x00000000, 0x00000000, // sub_32
    5386             :   0x00007800, 0x00000000, 0x00000000, 0x00000000, // sube32
    5387             :   0x00007800, 0x00000000, 0x00000000, 0x00000000, // subo32
    5388             :   0x3f800000, 0x00000000, 0x00000000, 0x00000000, // subo64_then_sub_32
    5389             : };
    5390             : 
    5391             : static const uint32_t FPR32SubClassMask[] = {
    5392             :   0x00000020, 0x00000000, 0x00000000, 0x00000000, 
    5393             :   0xc0410000, 0xffffffff, 0xffffffff, 0x0000000f, // ssub
    5394             :   0x00400000, 0x00000018, 0x00000000, 0x00000000, // dsub1_then_ssub
    5395             :   0x00000000, 0x00000010, 0x00000000, 0x00000000, // dsub3_then_ssub
    5396             :   0x00000000, 0x00000018, 0x00000000, 0x00000000, // dsub2_then_ssub
    5397             :   0x00000000, 0x131d09a0, 0x0131c3d0, 0x00000000, // qsub1_then_ssub
    5398             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub3_then_ssub
    5399             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // qsub2_then_ssub
    5400             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // zsub1_then_ssub
    5401             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub3_then_ssub
    5402             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub2_then_ssub
    5403             : };
    5404             : 
    5405             : static const uint32_t GPR32SubClassMask[] = {
    5406             :   0x00000140, 0x00000000, 0x00000000, 0x00000000, 
    5407             :   0x3f9a0000, 0x00000000, 0x00000000, 0x00000000, // sub_32
    5408             :   0x00007800, 0x00000000, 0x00000000, 0x00000000, // sube32
    5409             :   0x00007800, 0x00000000, 0x00000000, 0x00000000, // subo32
    5410             :   0x3f800000, 0x00000000, 0x00000000, 0x00000000, // subo64_then_sub_32
    5411             : };
    5412             : 
    5413             : static const uint32_t GPR32spSubClassMask[] = {
    5414             :   0x00000580, 0x00000000, 0x00000000, 0x00000000, 
    5415             :   0x2d3c0000, 0x00000000, 0x00000000, 0x00000000, // sub_32
    5416             :   0x00005000, 0x00000000, 0x00000000, 0x00000000, // sube32
    5417             :   0x00006000, 0x00000000, 0x00000000, 0x00000000, // subo32
    5418             :   0x3e000000, 0x00000000, 0x00000000, 0x00000000, // subo64_then_sub_32
    5419             : };
    5420             : 
    5421             : static const uint32_t GPR32commonSubClassMask[] = {
    5422             :   0x00000100, 0x00000000, 0x00000000, 0x00000000, 
    5423             :   0x2d180000, 0x00000000, 0x00000000, 0x00000000, // sub_32
    5424             :   0x00005000, 0x00000000, 0x00000000, 0x00000000, // sube32
    5425             :   0x00006000, 0x00000000, 0x00000000, 0x00000000, // subo32
    5426             :   0x3e000000, 0x00000000, 0x00000000, 0x00000000, // subo64_then_sub_32
    5427             : };
    5428             : 
    5429             : static const uint32_t CCRSubClassMask[] = {
    5430             :   0x00000200, 0x00000000, 0x00000000, 0x00000000, 
    5431             : };
    5432             : 
    5433             : static const uint32_t GPR32sponlySubClassMask[] = {
    5434             :   0x00000400, 0x00000000, 0x00000000, 0x00000000, 
    5435             :   0x00200000, 0x00000000, 0x00000000, 0x00000000, // sub_32
    5436             : };
    5437             : 
    5438             : static const uint32_t WSeqPairsClassSubClassMask[] = {
    5439             :   0x00007800, 0x00000000, 0x00000000, 0x00000000, 
    5440             :   0x3f800000, 0x00000000, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
    5441             : };
    5442             : 
    5443             : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask[] = {
    5444             :   0x00005000, 0x00000000, 0x00000000, 0x00000000, 
    5445             :   0x2d000000, 0x00000000, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
    5446             : };
    5447             : 
    5448             : static const uint32_t WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
    5449             :   0x00006000, 0x00000000, 0x00000000, 0x00000000, 
    5450             :   0x3e000000, 0x00000000, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
    5451             : };
    5452             : 
    5453             : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
    5454             :   0x00004000, 0x00000000, 0x00000000, 0x00000000, 
    5455             :   0x2c000000, 0x00000000, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
    5456             : };
    5457             : 
    5458             : static const uint32_t GPR64allSubClassMask[] = {
    5459             :   0x003e8000, 0x00000000, 0x00000000, 0x00000000, 
    5460             :   0x3f800000, 0x00000000, 0x00000000, 0x00000000, // sube64
    5461             :   0x3f800000, 0x00000000, 0x00000000, 0x00000000, // subo64
    5462             : };
    5463             : 
    5464             : static const uint32_t FPR64SubClassMask[] = {
    5465             :   0x00010000, 0x00000000, 0x00000000, 0x00000000, 
    5466             :   0xc0000000, 0xffffffe7, 0xffffffff, 0x0000000f, // dsub
    5467             :   0x00400000, 0x00000018, 0x00000000, 0x00000000, // dsub0
    5468             :   0x00400000, 0x00000018, 0x00000000, 0x00000000, // dsub1
    5469             :   0x00000000, 0x00000018, 0x00000000, 0x00000000, // dsub2
    5470             :   0x00000000, 0x00000010, 0x00000000, 0x00000000, // dsub3
    5471             :   0x00000000, 0x131d09a0, 0x0131c3d0, 0x00000000, // qsub1_then_dsub
    5472             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub3_then_dsub
    5473             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // qsub2_then_dsub
    5474             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // zsub1_then_dsub
    5475             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub3_then_dsub
    5476             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub2_then_dsub
    5477             : };
    5478             : 
    5479             : static const uint32_t GPR64SubClassMask[] = {
    5480             :   0x001a0000, 0x00000000, 0x00000000, 0x00000000, 
    5481             :   0x3f800000, 0x00000000, 0x00000000, 0x00000000, // sube64
    5482             :   0x3f800000, 0x00000000, 0x00000000, 0x00000000, // subo64
    5483             : };
    5484             : 
    5485             : static const uint32_t GPR64spSubClassMask[] = {
    5486             :   0x003c0000, 0x00000000, 0x00000000, 0x00000000, 
    5487             :   0x2d000000, 0x00000000, 0x00000000, 0x00000000, // sube64
    5488             :   0x3e000000, 0x00000000, 0x00000000, 0x00000000, // subo64
    5489             : };
    5490             : 
    5491             : static const uint32_t GPR64commonSubClassMask[] = {
    5492             :   0x00180000, 0x00000000, 0x00000000, 0x00000000, 
    5493             :   0x2d000000, 0x00000000, 0x00000000, 0x00000000, // sube64
    5494             :   0x3e000000, 0x00000000, 0x00000000, 0x00000000, // subo64
    5495             : };
    5496             : 
    5497             : static const uint32_t tcGPR64SubClassMask[] = {
    5498             :   0x00100000, 0x00000000, 0x00000000, 0x00000000, 
    5499             :   0x28000000, 0x00000000, 0x00000000, 0x00000000, // sube64
    5500             :   0x30000000, 0x00000000, 0x00000000, 0x00000000, // subo64
    5501             : };
    5502             : 
    5503             : static const uint32_t GPR64sponlySubClassMask[] = {
    5504             :   0x00200000, 0x00000000, 0x00000000, 0x00000000, 
    5505             : };
    5506             : 
    5507             : static const uint32_t DDSubClassMask[] = {
    5508             :   0x00400000, 0x00000000, 0x00000000, 0x00000000, 
    5509             :   0x00000000, 0x00000018, 0x00000000, 0x00000000, // dsub0_dsub1
    5510             :   0x00000000, 0x00000018, 0x00000000, 0x00000000, // dsub1_dsub2
    5511             :   0x00000000, 0x00000010, 0x00000000, 0x00000000, // dsub2_dsub3
    5512             :   0x00000000, 0x131d09a0, 0x0131c3d0, 0x00000000, // dsub_qsub1_then_dsub
    5513             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // qsub1_then_dsub_qsub2_then_dsub
    5514             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub2_then_dsub_qsub3_then_dsub
    5515             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // dsub_zsub1_then_dsub
    5516             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub1_then_dsub_zsub2_then_dsub
    5517             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub2_then_dsub_zsub3_then_dsub
    5518             : };
    5519             : 
    5520             : static const uint32_t XSeqPairsClassSubClassMask[] = {
    5521             :   0x3f800000, 0x00000000, 0x00000000, 0x00000000, 
    5522             : };
    5523             : 
    5524             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask[] = {
    5525             :   0x2d000000, 0x00000000, 0x00000000, 0x00000000, 
    5526             : };
    5527             : 
    5528             : static const uint32_t XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
    5529             :   0x3e000000, 0x00000000, 0x00000000, 0x00000000, 
    5530             : };
    5531             : 
    5532             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
    5533             :   0x2c000000, 0x00000000, 0x00000000, 0x00000000, 
    5534             : };
    5535             : 
    5536             : static const uint32_t XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask[] = {
    5537             :   0x28000000, 0x00000000, 0x00000000, 0x00000000, 
    5538             : };
    5539             : 
    5540             : static const uint32_t XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
    5541             :   0x30000000, 0x00000000, 0x00000000, 0x00000000, 
    5542             : };
    5543             : 
    5544             : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
    5545             :   0x20000000, 0x00000000, 0x00000000, 0x00000000, 
    5546             : };
    5547             : 
    5548             : static const uint32_t FPR128SubClassMask[] = {
    5549             :   0x40000000, 0x00000001, 0x00000000, 0x00000000, 
    5550             :   0x00000000, 0x131d09a0, 0x0131c3d0, 0x00000000, // qsub0
    5551             :   0x00000000, 0x131d09a0, 0x0131c3d0, 0x00000000, // qsub1
    5552             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // qsub2
    5553             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub3
    5554             :   0x80000000, 0xece2f646, 0xfece3c2f, 0x0000000f, // zsub
    5555             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // zsub1_then_zsub
    5556             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub3_then_zsub
    5557             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub2_then_zsub
    5558             : };
    5559             : 
    5560             : static const uint32_t ZPRSubClassMask[] = {
    5561             :   0x80000000, 0x00000006, 0x00000000, 0x00000000, 
    5562             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // zsub0
    5563             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // zsub1
    5564             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub2
    5565             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub3
    5566             : };
    5567             : 
    5568             : static const uint32_t FPR128_loSubClassMask[] = {
    5569             :   0x00000000, 0x00000001, 0x00000000, 0x00000000, 
    5570             :   0x00000000, 0x11040880, 0x01104040, 0x00000000, // qsub0
    5571             :   0x00000000, 0x13080900, 0x0130c080, 0x00000000, // qsub1
    5572             :   0x00000000, 0x12100000, 0x01318100, 0x00000000, // qsub2
    5573             :   0x00000000, 0x00000000, 0x01210200, 0x00000000, // qsub3
    5574             :   0x00000000, 0x6880b406, 0x0688200c, 0x0000000d, // zsub
    5575             :   0x00000000, 0xec20f200, 0x4eca040e, 0x0000000f, // zsub1_then_zsub
    5576             :   0x00000000, 0x00000000, 0xfe441000, 0x0000000f, // zsub3_then_zsub
    5577             :   0x00000000, 0xe4400000, 0xdec6080f, 0x0000000f, // zsub2_then_zsub
    5578             : };
    5579             : 
    5580             : static const uint32_t ZPR_4bSubClassMask[] = {
    5581             :   0x00000000, 0x00000006, 0x00000000, 0x00000000, 
    5582             :   0x00000000, 0x6880b400, 0x0688200c, 0x0000000d, // zsub0
    5583             :   0x00000000, 0xec20f200, 0x4eca040e, 0x0000000f, // zsub1
    5584             :   0x00000000, 0xe4400000, 0xdec6080f, 0x0000000f, // zsub2
    5585             :   0x00000000, 0x00000000, 0xfe441000, 0x0000000f, // zsub3
    5586             : };
    5587             : 
    5588             : static const uint32_t ZPR_3bSubClassMask[] = {
    5589             :   0x00000000, 0x00000004, 0x00000000, 0x00000000, 
    5590             :   0x00000000, 0x4000a000, 0x0400000c, 0x0000000d, // zsub0
    5591             :   0x00000000, 0x8000c000, 0x4800000e, 0x0000000f, // zsub1
    5592             :   0x00000000, 0x00000000, 0xd000000b, 0x0000000e, // zsub2
    5593             :   0x00000000, 0x00000000, 0xa0000000, 0x0000000a, // zsub3
    5594             : };
    5595             : 
    5596             : static const uint32_t DDDSubClassMask[] = {
    5597             :   0x00000000, 0x00000008, 0x00000000, 0x00000000, 
    5598             :   0x00000000, 0x00000010, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2
    5599             :   0x00000000, 0x00000010, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3
    5600             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // dsub_qsub1_then_dsub_qsub2_then_dsub
    5601             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5602             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // dsub_zsub1_then_dsub_zsub2_then_dsub
    5603             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    5604             : };
    5605             : 
    5606             : static const uint32_t DDDDSubClassMask[] = {
    5607             :   0x00000000, 0x00000010, 0x00000000, 0x00000000, 
    5608             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    5609             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    5610             : };
    5611             : 
    5612             : static const uint32_t QQSubClassMask[] = {
    5613             :   0x00000000, 0x000009a0, 0x00000000, 0x00000000, 
    5614             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // qsub0_qsub1
    5615             :   0x00000000, 0x131d0000, 0x0131c3d0, 0x00000000, // qsub1_qsub2
    5616             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub2_qsub3
    5617             :   0x00000000, 0xece2f640, 0xfece3c2f, 0x0000000f, // zsub_zsub1_then_zsub
    5618             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub
    5619             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub2_then_zsub_zsub3_then_zsub
    5620             : };
    5621             : 
    5622             : static const uint32_t ZPR2SubClassMask[] = {
    5623             :   0x00000000, 0x0000f640, 0x00000000, 0x00000000, 
    5624             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub0_zsub1
    5625             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub1_zsub2
    5626             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub2_zsub3
    5627             : };
    5628             : 
    5629             : static const uint32_t QQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    5630             :   0x00000000, 0x00000880, 0x00000000, 0x00000000, 
    5631             :   0x00000000, 0x11040000, 0x01104040, 0x00000000, // qsub0_qsub1
    5632             :   0x00000000, 0x13080000, 0x0130c080, 0x00000000, // qsub1_qsub2
    5633             :   0x00000000, 0x00000000, 0x01318100, 0x00000000, // qsub2_qsub3
    5634             :   0x00000000, 0x6880b400, 0x0688200c, 0x0000000d, // zsub_zsub1_then_zsub
    5635             :   0x00000000, 0xec200000, 0x4eca040e, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub
    5636             :   0x00000000, 0x00000000, 0xdec60800, 0x0000000f, // zsub2_then_zsub_zsub3_then_zsub
    5637             : };
    5638             : 
    5639             : static const uint32_t QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5640             :   0x00000000, 0x00000900, 0x00000000, 0x00000000, 
    5641             :   0x00000000, 0x13080000, 0x0130c080, 0x00000000, // qsub0_qsub1
    5642             :   0x00000000, 0x12100000, 0x01318100, 0x00000000, // qsub1_qsub2
    5643             :   0x00000000, 0x00000000, 0x01210200, 0x00000000, // qsub2_qsub3
    5644             :   0x00000000, 0xec20f200, 0x4eca040e, 0x0000000f, // zsub_zsub1_then_zsub
    5645             :   0x00000000, 0xe4400000, 0xdec6080f, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub
    5646             :   0x00000000, 0x00000000, 0xfe441000, 0x0000000f, // zsub2_then_zsub_zsub3_then_zsub
    5647             : };
    5648             : 
    5649             : static const uint32_t ZPR2_with_zsub1_in_ZPR_4bSubClassMask[] = {
    5650             :   0x00000000, 0x0000f200, 0x00000000, 0x00000000, 
    5651             :   0x00000000, 0xec200000, 0x4eca040e, 0x0000000f, // zsub0_zsub1
    5652             :   0x00000000, 0xe4400000, 0xdec6080f, 0x0000000f, // zsub1_zsub2
    5653             :   0x00000000, 0x00000000, 0xfe441000, 0x0000000f, // zsub2_zsub3
    5654             : };
    5655             : 
    5656             : static const uint32_t ZPR2_with_zsub_in_FPR128_loSubClassMask[] = {
    5657             :   0x00000000, 0x0000b400, 0x00000000, 0x00000000, 
    5658             :   0x00000000, 0x68800000, 0x0688200c, 0x0000000d, // zsub0_zsub1
    5659             :   0x00000000, 0xec200000, 0x4eca040e, 0x0000000f, // zsub1_zsub2
    5660             :   0x00000000, 0x00000000, 0xdec60800, 0x0000000f, // zsub2_zsub3
    5661             : };
    5662             : 
    5663             : static const uint32_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5664             :   0x00000000, 0x00000800, 0x00000000, 0x00000000, 
    5665             :   0x00000000, 0x11000000, 0x01104000, 0x00000000, // qsub0_qsub1
    5666             :   0x00000000, 0x12000000, 0x01308000, 0x00000000, // qsub1_qsub2
    5667             :   0x00000000, 0x00000000, 0x01210000, 0x00000000, // qsub2_qsub3
    5668             :   0x00000000, 0x6800b000, 0x0688000c, 0x0000000d, // zsub_zsub1_then_zsub
    5669             :   0x00000000, 0xe4000000, 0x4ec2000e, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub
    5670             :   0x00000000, 0x00000000, 0xde440000, 0x0000000f, // zsub2_then_zsub_zsub3_then_zsub
    5671             : };
    5672             : 
    5673             : static const uint32_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSubClassMask[] = {
    5674             :   0x00000000, 0x0000b000, 0x00000000, 0x00000000, 
    5675             :   0x00000000, 0x68000000, 0x0688000c, 0x0000000d, // zsub0_zsub1
    5676             :   0x00000000, 0xe4000000, 0x4ec2000e, 0x0000000f, // zsub1_zsub2
    5677             :   0x00000000, 0x00000000, 0xde440000, 0x0000000f, // zsub2_zsub3
    5678             : };
    5679             : 
    5680             : static const uint32_t ZPR2_with_zsub0_in_ZPR_3bSubClassMask[] = {
    5681             :   0x00000000, 0x0000a000, 0x00000000, 0x00000000, 
    5682             :   0x00000000, 0x40000000, 0x0400000c, 0x0000000d, // zsub0_zsub1
    5683             :   0x00000000, 0x80000000, 0x4800000e, 0x0000000f, // zsub1_zsub2
    5684             :   0x00000000, 0x00000000, 0xd0000000, 0x0000000e, // zsub2_zsub3
    5685             : };
    5686             : 
    5687             : static const uint32_t ZPR2_with_zsub1_in_ZPR_3bSubClassMask[] = {
    5688             :   0x00000000, 0x0000c000, 0x00000000, 0x00000000, 
    5689             :   0x00000000, 0x80000000, 0x4800000e, 0x0000000f, // zsub0_zsub1
    5690             :   0x00000000, 0x00000000, 0xd000000b, 0x0000000e, // zsub1_zsub2
    5691             :   0x00000000, 0x00000000, 0xa0000000, 0x0000000a, // zsub2_zsub3
    5692             : };
    5693             : 
    5694             : static const uint32_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSubClassMask[] = {
    5695             :   0x00000000, 0x00008000, 0x00000000, 0x00000000, 
    5696             :   0x00000000, 0x00000000, 0x0000000c, 0x0000000d, // zsub0_zsub1
    5697             :   0x00000000, 0x00000000, 0x4000000a, 0x0000000e, // zsub1_zsub2
    5698             :   0x00000000, 0x00000000, 0x80000000, 0x0000000a, // zsub2_zsub3
    5699             : };
    5700             : 
    5701             : static const uint32_t QQQSubClassMask[] = {
    5702             :   0x00000000, 0x131d0000, 0x00000000, 0x00000000, 
    5703             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub0_qsub1_qsub2
    5704             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, // qsub1_qsub2_qsub3
    5705             :   0x00000000, 0xece20000, 0xfece3c2f, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5706             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5707             : };
    5708             : 
    5709             : static const uint32_t ZPR3SubClassMask[] = {
    5710             :   0x00000000, 0xece20000, 0x0000000f, 0x00000000, 
    5711             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub0_zsub1_zsub2
    5712             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub1_zsub2_zsub3
    5713             : };
    5714             : 
    5715             : static const uint32_t QQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    5716             :   0x00000000, 0x11040000, 0x00000000, 0x00000000, 
    5717             :   0x00000000, 0x00000000, 0x01104040, 0x00000000, // qsub0_qsub1_qsub2
    5718             :   0x00000000, 0x00000000, 0x0130c080, 0x00000000, // qsub1_qsub2_qsub3
    5719             :   0x00000000, 0x68800000, 0x0688200c, 0x0000000d, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5720             :   0x00000000, 0x00000000, 0x4eca0400, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5721             : };
    5722             : 
    5723             : static const uint32_t QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5724             :   0x00000000, 0x13080000, 0x00000000, 0x00000000, 
    5725             :   0x00000000, 0x00000000, 0x0130c080, 0x00000000, // qsub0_qsub1_qsub2
    5726             :   0x00000000, 0x00000000, 0x01318100, 0x00000000, // qsub1_qsub2_qsub3
    5727             :   0x00000000, 0xec200000, 0x4eca040e, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5728             :   0x00000000, 0x00000000, 0xdec60800, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5729             : };
    5730             : 
    5731             : static const uint32_t QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5732             :   0x00000000, 0x12100000, 0x00000000, 0x00000000, 
    5733             :   0x00000000, 0x00000000, 0x01318100, 0x00000000, // qsub0_qsub1_qsub2
    5734             :   0x00000000, 0x00000000, 0x01210200, 0x00000000, // qsub1_qsub2_qsub3
    5735             :   0x00000000, 0xe4400000, 0xdec6080f, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5736             :   0x00000000, 0x00000000, 0xfe441000, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5737             : };
    5738             : 
    5739             : static const uint32_t ZPR3_with_zsub1_in_ZPR_4bSubClassMask[] = {
    5740             :   0x00000000, 0xec200000, 0x0000000e, 0x00000000, 
    5741             :   0x00000000, 0x00000000, 0x4eca0400, 0x0000000f, // zsub0_zsub1_zsub2
    5742             :   0x00000000, 0x00000000, 0xdec60800, 0x0000000f, // zsub1_zsub2_zsub3
    5743             : };
    5744             : 
    5745             : static const uint32_t ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
    5746             :   0x00000000, 0xe4400000, 0x0000000f, 0x00000000, 
    5747             :   0x00000000, 0x00000000, 0xdec60800, 0x0000000f, // zsub0_zsub1_zsub2
    5748             :   0x00000000, 0x00000000, 0xfe441000, 0x0000000f, // zsub1_zsub2_zsub3
    5749             : };
    5750             : 
    5751             : static const uint32_t ZPR3_with_zsub_in_FPR128_loSubClassMask[] = {
    5752             :   0x00000000, 0x68800000, 0x0000000c, 0x00000000, 
    5753             :   0x00000000, 0x00000000, 0x06882000, 0x0000000d, // zsub0_zsub1_zsub2
    5754             :   0x00000000, 0x00000000, 0x4eca0400, 0x0000000f, // zsub1_zsub2_zsub3
    5755             : };
    5756             : 
    5757             : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5758             :   0x00000000, 0x11000000, 0x00000000, 0x00000000, 
    5759             :   0x00000000, 0x00000000, 0x01104000, 0x00000000, // qsub0_qsub1_qsub2
    5760             :   0x00000000, 0x00000000, 0x01308000, 0x00000000, // qsub1_qsub2_qsub3
    5761             :   0x00000000, 0x68000000, 0x0688000c, 0x0000000d, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5762             :   0x00000000, 0x00000000, 0x4ec20000, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5763             : };
    5764             : 
    5765             : static const uint32_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5766             :   0x00000000, 0x12000000, 0x00000000, 0x00000000, 
    5767             :   0x00000000, 0x00000000, 0x01308000, 0x00000000, // qsub0_qsub1_qsub2
    5768             :   0x00000000, 0x00000000, 0x01210000, 0x00000000, // qsub1_qsub2_qsub3
    5769             :   0x00000000, 0xe4000000, 0x4ec2000e, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5770             :   0x00000000, 0x00000000, 0xde440000, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5771             : };
    5772             : 
    5773             : static const uint32_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
    5774             :   0x00000000, 0xe4000000, 0x0000000e, 0x00000000, 
    5775             :   0x00000000, 0x00000000, 0x4ec20000, 0x0000000f, // zsub0_zsub1_zsub2
    5776             :   0x00000000, 0x00000000, 0xde440000, 0x0000000f, // zsub1_zsub2_zsub3
    5777             : };
    5778             : 
    5779             : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSubClassMask[] = {
    5780             :   0x00000000, 0x68000000, 0x0000000c, 0x00000000, 
    5781             :   0x00000000, 0x00000000, 0x06880000, 0x0000000d, // zsub0_zsub1_zsub2
    5782             :   0x00000000, 0x00000000, 0x4ec20000, 0x0000000f, // zsub1_zsub2_zsub3
    5783             : };
    5784             : 
    5785             : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5786             :   0x00000000, 0x10000000, 0x00000000, 0x00000000, 
    5787             :   0x00000000, 0x00000000, 0x01100000, 0x00000000, // qsub0_qsub1_qsub2
    5788             :   0x00000000, 0x00000000, 0x01200000, 0x00000000, // qsub1_qsub2_qsub3
    5789             :   0x00000000, 0x60000000, 0x0680000c, 0x0000000d, // zsub_zsub1_then_zsub_zsub2_then_zsub
    5790             :   0x00000000, 0x00000000, 0x4e400000, 0x0000000f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5791             : };
    5792             : 
    5793             : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
    5794             :   0x00000000, 0x60000000, 0x0000000c, 0x00000000, 
    5795             :   0x00000000, 0x00000000, 0x06800000, 0x0000000d, // zsub0_zsub1_zsub2
    5796             :   0x00000000, 0x00000000, 0x4e400000, 0x0000000f, // zsub1_zsub2_zsub3
    5797             : };
    5798             : 
    5799             : static const uint32_t ZPR3_with_zsub0_in_ZPR_3bSubClassMask[] = {
    5800             :   0x00000000, 0x40000000, 0x0000000c, 0x00000000, 
    5801             :   0x00000000, 0x00000000, 0x04000000, 0x0000000d, // zsub0_zsub1_zsub2
    5802             :   0x00000000, 0x00000000, 0x48000000, 0x0000000f, // zsub1_zsub2_zsub3
    5803             : };
    5804             : 
    5805             : static const uint32_t ZPR3_with_zsub1_in_ZPR_3bSubClassMask[] = {
    5806             :   0x00000000, 0x80000000, 0x0000000e, 0x00000000, 
    5807             :   0x00000000, 0x00000000, 0x48000000, 0x0000000f, // zsub0_zsub1_zsub2
    5808             :   0x00000000, 0x00000000, 0xd0000000, 0x0000000e, // zsub1_zsub2_zsub3
    5809             : };
    5810             : 
    5811             : static const uint32_t ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
    5812             :   0x00000000, 0x00000000, 0x0000000b, 0x00000000, 
    5813             :   0x00000000, 0x00000000, 0xd0000000, 0x0000000e, // zsub0_zsub1_zsub2
    5814             :   0x00000000, 0x00000000, 0xa0000000, 0x0000000a, // zsub1_zsub2_zsub3
    5815             : };
    5816             : 
    5817             : static const uint32_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
    5818             :   0x00000000, 0x00000000, 0x0000000a, 0x00000000, 
    5819             :   0x00000000, 0x00000000, 0x40000000, 0x0000000e, // zsub0_zsub1_zsub2
    5820             :   0x00000000, 0x00000000, 0x80000000, 0x0000000a, // zsub1_zsub2_zsub3
    5821             : };
    5822             : 
    5823             : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSubClassMask[] = {
    5824             :   0x00000000, 0x00000000, 0x0000000c, 0x00000000, 
    5825             :   0x00000000, 0x00000000, 0x00000000, 0x0000000d, // zsub0_zsub1_zsub2
    5826             :   0x00000000, 0x00000000, 0x40000000, 0x0000000e, // zsub1_zsub2_zsub3
    5827             : };
    5828             : 
    5829             : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
    5830             :   0x00000000, 0x00000000, 0x00000008, 0x00000000, 
    5831             :   0x00000000, 0x00000000, 0x00000000, 0x0000000c, // zsub0_zsub1_zsub2
    5832             :   0x00000000, 0x00000000, 0x00000000, 0x0000000a, // zsub1_zsub2_zsub3
    5833             : };
    5834             : 
    5835             : static const uint32_t QQQQSubClassMask[] = {
    5836             :   0x00000000, 0x00000000, 0x0131c3d0, 0x00000000, 
    5837             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5838             : };
    5839             : 
    5840             : static const uint32_t ZPR4SubClassMask[] = {
    5841             :   0x00000000, 0x00000000, 0xfece3c20, 0x0000000f, 
    5842             : };
    5843             : 
    5844             : static const uint32_t QQQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
    5845             :   0x00000000, 0x00000000, 0x01104040, 0x00000000, 
    5846             :   0x00000000, 0x00000000, 0x06882000, 0x0000000d, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5847             : };
    5848             : 
    5849             : static const uint32_t QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5850             :   0x00000000, 0x00000000, 0x0130c080, 0x00000000, 
    5851             :   0x00000000, 0x00000000, 0x4eca0400, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5852             : };
    5853             : 
    5854             : static const uint32_t QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5855             :   0x00000000, 0x00000000, 0x01318100, 0x00000000, 
    5856             :   0x00000000, 0x00000000, 0xdec60800, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5857             : };
    5858             : 
    5859             : static const uint32_t QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    5860             :   0x00000000, 0x00000000, 0x01210200, 0x00000000, 
    5861             :   0x00000000, 0x00000000, 0xfe441000, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5862             : };
    5863             : 
    5864             : static const uint32_t ZPR4_with_zsub1_in_ZPR_4bSubClassMask[] = {
    5865             :   0x00000000, 0x00000000, 0x4eca0400, 0x0000000f, 
    5866             : };
    5867             : 
    5868             : static const uint32_t ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
    5869             :   0x00000000, 0x00000000, 0xdec60800, 0x0000000f, 
    5870             : };
    5871             : 
    5872             : static const uint32_t ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
    5873             :   0x00000000, 0x00000000, 0xfe441000, 0x0000000f, 
    5874             : };
    5875             : 
    5876             : static const uint32_t ZPR4_with_zsub_in_FPR128_loSubClassMask[] = {
    5877             :   0x00000000, 0x00000000, 0x06882000, 0x0000000d, 
    5878             : };
    5879             : 
    5880             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
    5881             :   0x00000000, 0x00000000, 0x01104000, 0x00000000, 
    5882             :   0x00000000, 0x00000000, 0x06880000, 0x0000000d, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5883             : };
    5884             : 
    5885             : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5886             :   0x00000000, 0x00000000, 0x01308000, 0x00000000, 
    5887             :   0x00000000, 0x00000000, 0x4ec20000, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5888             : };
    5889             : 
    5890             : static const uint32_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    5891             :   0x00000000, 0x00000000, 0x01210000, 0x00000000, 
    5892             :   0x00000000, 0x00000000, 0xde440000, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5893             : };
    5894             : 
    5895             : static const uint32_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
    5896             :   0x00000000, 0x00000000, 0x4ec20000, 0x0000000f, 
    5897             : };
    5898             : 
    5899             : static const uint32_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
    5900             :   0x00000000, 0x00000000, 0xde440000, 0x0000000f, 
    5901             : };
    5902             : 
    5903             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSubClassMask[] = {
    5904             :   0x00000000, 0x00000000, 0x06880000, 0x0000000d, 
    5905             : };
    5906             : 
    5907             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
    5908             :   0x00000000, 0x00000000, 0x01100000, 0x00000000, 
    5909             :   0x00000000, 0x00000000, 0x06800000, 0x0000000d, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5910             : };
    5911             : 
    5912             : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    5913             :   0x00000000, 0x00000000, 0x01200000, 0x00000000, 
    5914             :   0x00000000, 0x00000000, 0x4e400000, 0x0000000f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5915             : };
    5916             : 
    5917             : static const uint32_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
    5918             :   0x00000000, 0x00000000, 0x4e400000, 0x0000000f, 
    5919             : };
    5920             : 
    5921             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
    5922             :   0x00000000, 0x00000000, 0x06800000, 0x0000000d, 
    5923             : };
    5924             : 
    5925             : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
    5926             :   0x00000000, 0x00000000, 0x01000000, 0x00000000, 
    5927             :   0x00000000, 0x00000000, 0x06000000, 0x0000000d, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    5928             : };
    5929             : 
    5930             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
    5931             :   0x00000000, 0x00000000, 0x06000000, 0x0000000d, 
    5932             : };
    5933             : 
    5934             : static const uint32_t ZPR4_with_zsub0_in_ZPR_3bSubClassMask[] = {
    5935             :   0x00000000, 0x00000000, 0x04000000, 0x0000000d, 
    5936             : };
    5937             : 
    5938             : static const uint32_t ZPR4_with_zsub1_in_ZPR_3bSubClassMask[] = {
    5939             :   0x00000000, 0x00000000, 0x48000000, 0x0000000f, 
    5940             : };
    5941             : 
    5942             : static const uint32_t ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
    5943             :   0x00000000, 0x00000000, 0xd0000000, 0x0000000e, 
    5944             : };
    5945             : 
    5946             : static const uint32_t ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
    5947             :   0x00000000, 0x00000000, 0xa0000000, 0x0000000a, 
    5948             : };
    5949             : 
    5950             : static const uint32_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
    5951             :   0x00000000, 0x00000000, 0x40000000, 0x0000000e, 
    5952             : };
    5953             : 
    5954             : static const uint32_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
    5955             :   0x00000000, 0x00000000, 0x80000000, 0x0000000a, 
    5956             : };
    5957             : 
    5958             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSubClassMask[] = {
    5959             :   0x00000000, 0x00000000, 0x00000000, 0x0000000d, 
    5960             : };
    5961             : 
    5962             : static const uint32_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
    5963             :   0x00000000, 0x00000000, 0x00000000, 0x0000000a, 
    5964             : };
    5965             : 
    5966             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
    5967             :   0x00000000, 0x00000000, 0x00000000, 0x0000000c, 
    5968             : };
    5969             : 
    5970             : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
    5971             :   0x00000000, 0x00000000, 0x00000000, 0x00000008, 
    5972             : };
    5973             : 
    5974             : static const uint16_t SuperRegIdxSeqs[] = {
    5975             :   /* 0 */ 15, 0,
    5976             :   /* 2 */ 17, 19, 0,
    5977             :   /* 5 */ 21, 22, 23, 24, 0,
    5978             :   /* 10 */ 15, 16, 18, 47, 0,
    5979             :   /* 15 */ 1, 26, 29, 32, 35, 39, 43, 48, 54, 60, 0,
    5980             :   /* 26 */ 2, 3, 4, 5, 6, 36, 40, 44, 49, 55, 61, 0,
    5981             :   /* 38 */ 7, 27, 30, 33, 37, 41, 45, 50, 56, 62, 0,
    5982             :   /* 49 */ 14, 28, 31, 34, 38, 42, 46, 51, 57, 63, 0,
    5983             :   /* 60 */ 10, 11, 12, 13, 20, 52, 58, 64, 0,
    5984             :   /* 69 */ 82, 0,
    5985             :   /* 71 */ 72, 85, 0,
    5986             :   /* 74 */ 87, 0,
    5987             :   /* 76 */ 90, 92, 0,
    5988             :   /* 79 */ 89, 91, 93, 0,
    5989             :   /* 83 */ 67, 69, 73, 80, 86, 95, 0,
    5990             :   /* 90 */ 75, 77, 88, 97, 0,
    5991             :   /* 95 */ 66, 68, 70, 71, 79, 81, 83, 94, 98, 0,
    5992             :   /* 105 */ 74, 76, 78, 84, 96, 99, 0,
    5993             : };
    5994             : 
    5995             : static const TargetRegisterClass *const PPR_3bSuperclasses[] = {
    5996             :   &AArch64::PPRRegClass,
    5997             :   nullptr
    5998             : };
    5999             : 
    6000             : static const TargetRegisterClass *const GPR32Superclasses[] = {
    6001             :   &AArch64::GPR32allRegClass,
    6002             :   nullptr
    6003             : };
    6004             : 
    6005             : static const TargetRegisterClass *const GPR32spSuperclasses[] = {
    6006             :   &AArch64::GPR32allRegClass,
    6007             :   nullptr
    6008             : };
    6009             : 
    6010             : static const TargetRegisterClass *const GPR32commonSuperclasses[] = {
    6011             :   &AArch64::GPR32allRegClass,
    6012             :   &AArch64::GPR32RegClass,
    6013             :   &AArch64::GPR32spRegClass,
    6014             :   nullptr
    6015             : };
    6016             : 
    6017             : static const TargetRegisterClass *const GPR32sponlySuperclasses[] = {
    6018             :   &AArch64::GPR32allRegClass,
    6019             :   &AArch64::GPR32spRegClass,
    6020             :   nullptr
    6021             : };
    6022             : 
    6023             : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses[] = {
    6024             :   &AArch64::WSeqPairsClassRegClass,
    6025             :   nullptr
    6026             : };
    6027             : 
    6028             : static const TargetRegisterClass *const WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
    6029             :   &AArch64::WSeqPairsClassRegClass,
    6030             :   nullptr
    6031             : };
    6032             : 
    6033             : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
    6034             :   &AArch64::WSeqPairsClassRegClass,
    6035             :   &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
    6036             :   &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    6037             :   nullptr
    6038             : };
    6039             : 
    6040             : static const TargetRegisterClass *const GPR64Superclasses[] = {
    6041             :   &AArch64::GPR64allRegClass,
    6042             :   nullptr
    6043             : };
    6044             : 
    6045             : static const TargetRegisterClass *const GPR64spSuperclasses[] = {
    6046             :   &AArch64::GPR64allRegClass,
    6047             :   nullptr
    6048             : };
    6049             : 
    6050             : static const TargetRegisterClass *const GPR64commonSuperclasses[] = {
    6051             :   &AArch64::GPR64allRegClass,
    6052             :   &AArch64::GPR64RegClass,
    6053             :   &AArch64::GPR64spRegClass,
    6054             :   nullptr
    6055             : };
    6056             : 
    6057             : static const TargetRegisterClass *const tcGPR64Superclasses[] = {
    6058             :   &AArch64::GPR64allRegClass,
    6059             :   &AArch64::GPR64RegClass,
    6060             :   &AArch64::GPR64spRegClass,
    6061             :   &AArch64::GPR64commonRegClass,
    6062             :   nullptr
    6063             : };
    6064             : 
    6065             : static const TargetRegisterClass *const GPR64sponlySuperclasses[] = {
    6066             :   &AArch64::GPR64allRegClass,
    6067             :   &AArch64::GPR64spRegClass,
    6068             :   nullptr
    6069             : };
    6070             : 
    6071             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses[] = {
    6072             :   &AArch64::XSeqPairsClassRegClass,
    6073             :   nullptr
    6074             : };
    6075             : 
    6076             : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
    6077             :   &AArch64::XSeqPairsClassRegClass,
    6078             :   nullptr
    6079             : };
    6080             : 
    6081             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
    6082             :   &AArch64::XSeqPairsClassRegClass,
    6083             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    6084             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    6085             :   nullptr
    6086             : };
    6087             : 
    6088             : static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_tcGPR64Superclasses[] = {
    6089             :   &AArch64::XSeqPairsClassRegClass,
    6090             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    6091             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    6092             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    6093             :   nullptr
    6094             : };
    6095             : 
    6096             : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
    6097             :   &AArch64::XSeqPairsClassRegClass,
    6098             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    6099             :   nullptr
    6100             : };
    6101             : 
    6102             : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
    6103             :   &AArch64::XSeqPairsClassRegClass,
    6104             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    6105             :   &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    6106             :   &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    6107             :   &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
    6108             :   &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    6109             :   nullptr
    6110             : };
    6111             : 
    6112             : static const TargetRegisterClass *const FPR128_loSuperclasses[] = {
    6113             :   &AArch64::FPR128RegClass,
    6114             :   nullptr
    6115             : };
    6116             : 
    6117             : static const TargetRegisterClass *const ZPR_4bSuperclasses[] = {
    6118             :   &AArch64::ZPRRegClass,
    6119             :   nullptr
    6120             : };
    6121             : 
    6122             : static const TargetRegisterClass *const ZPR_3bSuperclasses[] = {
    6123             :   &AArch64::ZPRRegClass,
    6124             :   &AArch64::ZPR_4bRegClass,
    6125             :   nullptr
    6126             : };
    6127             : 
    6128             : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    6129             :   &AArch64::QQRegClass,
    6130             :   nullptr
    6131             : };
    6132             : 
    6133             : static const TargetRegisterClass *const QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    6134             :   &AArch64::QQRegClass,
    6135             :   nullptr
    6136             : };
    6137             : 
    6138             : static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = {
    6139             :   &AArch64::ZPR2RegClass,
    6140             :   nullptr
    6141             : };
    6142             : 
    6143             : static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_loSuperclasses[] = {
    6144             :   &AArch64::ZPR2RegClass,
    6145             :   nullptr
    6146             : };
    6147             : 
    6148             : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    6149             :   &AArch64::QQRegClass,
    6150             :   &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
    6151             :   &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
    6152             :   nullptr
    6153             : };
    6154             : 
    6155             : static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = {
    6156             :   &AArch64::ZPR2RegClass,
    6157             :   &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
    6158             :   &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
    6159             :   nullptr
    6160             : };
    6161             : 
    6162             : static const TargetRegisterClass *const ZPR2_with_zsub0_in_ZPR_3bSuperclasses[] = {
    6163             :   &AArch64::ZPR2RegClass,
    6164             :   &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
    6165             :   &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
    6166             :   &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
    6167             :   nullptr
    6168             : };
    6169             : 
    6170             : static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = {
    6171             :   &AArch64::ZPR2RegClass,
    6172             :   &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
    6173             :   nullptr
    6174             : };
    6175             : 
    6176             : static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = {
    6177             :   &AArch64::ZPR2RegClass,
    6178             :   &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
    6179             :   &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
    6180             :   &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
    6181             :   &AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClass,
    6182             :   &AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClass,
    6183             :   nullptr
    6184             : };
    6185             : 
    6186             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    6187             :   &AArch64::QQQRegClass,
    6188             :   nullptr
    6189             : };
    6190             : 
    6191             : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    6192             :   &AArch64::QQQRegClass,
    6193             :   nullptr
    6194             : };
    6195             : 
    6196             : static const TargetRegisterClass *const QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    6197             :   &AArch64::QQQRegClass,
    6198             :   nullptr
    6199             : };
    6200             : 
    6201             : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = {
    6202             :   &AArch64::ZPR3RegClass,
    6203             :   nullptr
    6204             : };
    6205             : 
    6206             : static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
    6207             :   &AArch64::ZPR3RegClass,
    6208             :   nullptr
    6209             : };
    6210             : 
    6211             : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_loSuperclasses[] = {
    6212             :   &AArch64::ZPR3RegClass,
    6213             :   nullptr
    6214             : };
    6215             : 
    6216             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    6217             :   &AArch64::QQQRegClass,
    6218             :   &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    6219             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    6220             :   nullptr
    6221             : };
    6222             : 
    6223             : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    6224             :   &AArch64::QQQRegClass,
    6225             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    6226             :   &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    6227             :   nullptr
    6228             : };
    6229             : 
    6230             : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
    6231             :   &AArch64::ZPR3RegClass,
    6232             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6233             :   &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6234             :   nullptr
    6235             : };
    6236             : 
    6237             : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = {
    6238             :   &AArch64::ZPR3RegClass,
    6239             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6240             :   &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    6241             :   nullptr
    6242             : };
    6243             : 
    6244             : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    6245             :   &AArch64::QQQRegClass,
    6246             :   &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    6247             :   &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    6248             :   &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    6249             :   &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
    6250             :   &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    6251             :   nullptr
    6252             : };
    6253             : 
    6254             : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
    6255             :   &AArch64::ZPR3RegClass,
    6256             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6257             :   &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6258             :   &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    6259             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6260             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6261             :   nullptr
    6262             : };
    6263             : 
    6264             : static const TargetRegisterClass *const ZPR3_with_zsub0_in_ZPR_3bSuperclasses[] = {
    6265             :   &AArch64::ZPR3RegClass,
    6266             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6267             :   &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6268             :   &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    6269             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6270             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6271             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6272             :   nullptr
    6273             : };
    6274             : 
    6275             : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = {
    6276             :   &AArch64::ZPR3RegClass,
    6277             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6278             :   &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6279             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6280             :   nullptr
    6281             : };
    6282             : 
    6283             : static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
    6284             :   &AArch64::ZPR3RegClass,
    6285             :   &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6286             :   nullptr
    6287             : };
    6288             : 
    6289             : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
    6290             :   &AArch64::ZPR3RegClass,
    6291             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6292             :   &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6293             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6294             :   &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
    6295             :   &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
    6296             :   nullptr
    6297             : };
    6298             : 
    6299             : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = {
    6300             :   &AArch64::ZPR3RegClass,
    6301             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6302             :   &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6303             :   &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    6304             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6305             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6306             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6307             :   &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
    6308             :   &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
    6309             :   nullptr
    6310             : };
    6311             : 
    6312             : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
    6313             :   &AArch64::ZPR3RegClass,
    6314             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6315             :   &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6316             :   &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    6317             :   &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6318             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
    6319             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    6320             :   &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
    6321             :   &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
    6322             :   &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
    6323             :   &AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
    6324             :   &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass,
    6325             :   nullptr
    6326             : };
    6327             : 
    6328             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
    6329             :   &AArch64::QQQQRegClass,
    6330             :   nullptr
    6331             : };
    6332             : 
    6333             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    6334             :   &AArch64::QQQQRegClass,
    6335             :   nullptr
    6336             : };
    6337             : 
    6338             : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    6339             :   &AArch64::QQQQRegClass,
    6340             :   nullptr
    6341             : };
    6342             : 
    6343             : static const TargetRegisterClass *const QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    6344             :   &AArch64::QQQQRegClass,
    6345             :   nullptr
    6346             : };
    6347             : 
    6348             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = {
    6349             :   &AArch64::ZPR4RegClass,
    6350             :   nullptr
    6351             : };
    6352             : 
    6353             : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
    6354             :   &AArch64::ZPR4RegClass,
    6355             :   nullptr
    6356             : };
    6357             : 
    6358             : static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
    6359             :   &AArch64::ZPR4RegClass,
    6360             :   nullptr
    6361             : };
    6362             : 
    6363             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_loSuperclasses[] = {
    6364             :   &AArch64::ZPR4RegClass,
    6365             :   nullptr
    6366             : };
    6367             : 
    6368             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
    6369             :   &AArch64::QQQQRegClass,
    6370             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    6371             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    6372             :   nullptr
    6373             : };
    6374             : 
    6375             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    6376             :   &AArch64::QQQQRegClass,
    6377             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    6378             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    6379             :   nullptr
    6380             : };
    6381             : 
    6382             : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    6383             :   &AArch64::QQQQRegClass,
    6384             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    6385             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    6386             :   nullptr
    6387             : };
    6388             : 
    6389             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
    6390             :   &AArch64::ZPR4RegClass,
    6391             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6392             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6393             :   nullptr
    6394             : };
    6395             : 
    6396             : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
    6397             :   &AArch64::ZPR4RegClass,
    6398             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6399             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6400             :   nullptr
    6401             : };
    6402             : 
    6403             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = {
    6404             :   &AArch64::ZPR4RegClass,
    6405             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6406             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    6407             :   nullptr
    6408             : };
    6409             : 
    6410             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
    6411             :   &AArch64::QQQQRegClass,
    6412             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    6413             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    6414             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    6415             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    6416             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    6417             :   nullptr
    6418             : };
    6419             : 
    6420             : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    6421             :   &AArch64::QQQQRegClass,
    6422             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    6423             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    6424             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    6425             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    6426             :   &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    6427             :   nullptr
    6428             : };
    6429             : 
    6430             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
    6431             :   &AArch64::ZPR4RegClass,
    6432             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6433             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6434             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6435             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6436             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6437             :   nullptr
    6438             : };
    6439             : 
    6440             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
    6441             :   &AArch64::ZPR4RegClass,
    6442             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6443             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6444             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    6445             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6446             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6447             :   nullptr
    6448             : };
    6449             : 
    6450             : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
    6451             :   &AArch64::QQQQRegClass,
    6452             :   &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    6453             :   &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    6454             :   &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    6455             :   &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    6456             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    6457             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    6458             :   &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    6459             :   &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    6460             :   &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    6461             :   nullptr
    6462             : };
    6463             : 
    6464             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
    6465             :   &AArch64::ZPR4RegClass,
    6466             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6467             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6468             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6469             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    6470             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6471             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6472             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6473             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6474             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6475             :   nullptr
    6476             : };
    6477             : 
    6478             : static const TargetRegisterClass *const ZPR4_with_zsub0_in_ZPR_3bSuperclasses[] = {
    6479             :   &AArch64::ZPR4RegClass,
    6480             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6481             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6482             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6483             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    6484             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6485             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6486             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6487             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6488             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6489             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6490             :   nullptr
    6491             : };
    6492             : 
    6493             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = {
    6494             :   &AArch64::ZPR4RegClass,
    6495             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6496             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6497             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6498             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6499             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6500             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6501             :   nullptr
    6502             : };
    6503             : 
    6504             : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
    6505             :   &AArch64::ZPR4RegClass,
    6506             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6507             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6508             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6509             :   nullptr
    6510             : };
    6511             : 
    6512             : static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
    6513             :   &AArch64::ZPR4RegClass,
    6514             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6515             :   nullptr
    6516             : };
    6517             : 
    6518             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
    6519             :   &AArch64::ZPR4RegClass,
    6520             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6521             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6522             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6523             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6524             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6525             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6526             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
    6527             :   &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6528             :   nullptr
    6529             : };
    6530             : 
    6531             : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
    6532             :   &AArch64::ZPR4RegClass,
    6533             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6534             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6535             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6536             :   &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6537             :   &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
    6538             :   nullptr
    6539             : };
    6540             : 
    6541             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = {
    6542             :   &AArch64::ZPR4RegClass,
    6543             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6544             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6545             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6546             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    6547             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6548             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6549             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6550             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6551             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6552             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6553             :   &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
    6554             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
    6555             :   nullptr
    6556             : };
    6557             : 
    6558             : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
    6559             :   &AArch64::ZPR4RegClass,
    6560             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6561             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6562             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6563             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6564             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6565             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6566             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
    6567             :   &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6568             :   &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
    6569             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6570             :   &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
    6571             :   nullptr
    6572             : };
    6573             : 
    6574             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
    6575             :   &AArch64::ZPR4RegClass,
    6576             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6577             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6578             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6579             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    6580             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6581             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6582             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6583             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6584             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6585             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6586             :   &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
    6587             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
    6588             :   &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6589             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6590             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
    6591             :   nullptr
    6592             : };
    6593             : 
    6594             : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
    6595             :   &AArch64::ZPR4RegClass,
    6596             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6597             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6598             :   &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6599             :   &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    6600             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6601             :   &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6602             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
    6603             :   &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6604             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    6605             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    6606             :   &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
    6607             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
    6608             :   &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6609             :   &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
    6610             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6611             :   &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
    6612             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
    6613             :   &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
    6614             :   &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
    6615             :   nullptr
    6616             : };
    6617             : 
    6618             : 
    6619             : static inline unsigned GPR32AltOrderSelect(const MachineFunction &MF) { return 1; }
    6620             : 
    6621         568 : static ArrayRef<MCPhysReg> GPR32GetRawAllocationOrder(const MachineFunction &MF) {
    6622             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    6623             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
    6624             :   const ArrayRef<MCPhysReg> Order[] = {
    6625             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6626             :     makeArrayRef(AltOrder1)
    6627             :   };
    6628             :   const unsigned Select = GPR32AltOrderSelect(MF);
    6629             :   assert(Select < 2);
    6630         568 :   return Order[Select];
    6631             : }
    6632             : 
    6633             : static inline unsigned GPR32spAltOrderSelect(const MachineFunction &MF) { return 1; }
    6634             : 
    6635          90 : static ArrayRef<MCPhysReg> GPR32spGetRawAllocationOrder(const MachineFunction &MF) {
    6636             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    6637             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
    6638             :   const ArrayRef<MCPhysReg> Order[] = {
    6639             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6640             :     makeArrayRef(AltOrder1)
    6641             :   };
    6642             :   const unsigned Select = GPR32spAltOrderSelect(MF);
    6643             :   assert(Select < 2);
    6644          90 :   return Order[Select];
    6645             : }
    6646             : 
    6647             : static inline unsigned GPR32commonAltOrderSelect(const MachineFunction &MF) { return 1; }
    6648             : 
    6649         237 : static ArrayRef<MCPhysReg> GPR32commonGetRawAllocationOrder(const MachineFunction &MF) {
    6650             :   static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
    6651             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];
    6652             :   const ArrayRef<MCPhysReg> Order[] = {
    6653             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6654             :     makeArrayRef(AltOrder1)
    6655             :   };
    6656             :   const unsigned Select = GPR32commonAltOrderSelect(MF);
    6657             :   assert(Select < 2);
    6658         237 :   return Order[Select];
    6659             : }
    6660             : 
    6661             : static inline unsigned GPR64AltOrderSelect(const MachineFunction &MF) { return 1; }
    6662             : 
    6663         752 : static ArrayRef<MCPhysReg> GPR64GetRawAllocationOrder(const MachineFunction &MF) {
    6664             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    6665             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
    6666             :   const ArrayRef<MCPhysReg> Order[] = {
    6667             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6668             :     makeArrayRef(AltOrder1)
    6669             :   };
    6670             :   const unsigned Select = GPR64AltOrderSelect(MF);
    6671             :   assert(Select < 2);
    6672         752 :   return Order[Select];
    6673             : }
    6674             : 
    6675             : static inline unsigned GPR64spAltOrderSelect(const MachineFunction &MF) { return 1; }
    6676             : 
    6677         174 : static ArrayRef<MCPhysReg> GPR64spGetRawAllocationOrder(const MachineFunction &MF) {
    6678             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    6679             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];
    6680             :   const ArrayRef<MCPhysReg> Order[] = {
    6681             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6682             :     makeArrayRef(AltOrder1)
    6683             :   };
    6684             :   const unsigned Select = GPR64spAltOrderSelect(MF);
    6685             :   assert(Select < 2);
    6686         174 :   return Order[Select];
    6687             : }
    6688             : 
    6689             : static inline unsigned GPR64commonAltOrderSelect(const MachineFunction &MF) { return 1; }
    6690             : 
    6691         747 : static ArrayRef<MCPhysReg> GPR64commonGetRawAllocationOrder(const MachineFunction &MF) {
    6692             :   static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
    6693             :   const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID];
    6694             :   const ArrayRef<MCPhysReg> Order[] = {
    6695             :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    6696             :     makeArrayRef(AltOrder1)
    6697             :   };
    6698             :   const unsigned Select = GPR64commonAltOrderSelect(MF);
    6699             :   assert(Select < 2);
    6700         747 :   return Order[Select];
    6701             : }
    6702             : 
    6703             : namespace AArch64 {   // Register class instances
    6704             :   extern const TargetRegisterClass FPR8RegClass = {
    6705             :     &AArch64MCRegisterClasses[FPR8RegClassID],
    6706             :     FPR8SubClassMask,
    6707             :     SuperRegIdxSeqs + 15,
    6708             :     LaneBitmask(0x00000001),
    6709             :     0,
    6710             :     false, /* HasDisjunctSubRegs */
    6711             :     false, /* CoveredBySubRegs */
    6712             :     NullRegClasses,
    6713             :     nullptr
    6714             :   };
    6715             : 
    6716             :   extern const TargetRegisterClass FPR16RegClass = {
    6717             :     &AArch64MCRegisterClasses[FPR16RegClassID],
    6718             :     FPR16SubClassMask,
    6719             :     SuperRegIdxSeqs + 38,
    6720             :     LaneBitmask(0x00000001),
    6721             :     0,
    6722             :     false, /* HasDisjunctSubRegs */
    6723             :     false, /* CoveredBySubRegs */
    6724             :     NullRegClasses,
    6725             :     nullptr
    6726             :   };
    6727             : 
    6728             :   extern const TargetRegisterClass PPRRegClass = {
    6729             :     &AArch64MCRegisterClasses[PPRRegClassID],
    6730             :     PPRSubClassMask,
    6731             :     SuperRegIdxSeqs + 1,
    6732             :     LaneBitmask(0x00000001),
    6733             :     0,
    6734             :     false, /* HasDisjunctSubRegs */
    6735             :     false, /* CoveredBySubRegs */
    6736             :     NullRegClasses,
    6737             :     nullptr
    6738             :   };
    6739             : 
    6740             :   extern const TargetRegisterClass PPR_3bRegClass = {
    6741             :     &AArch64MCRegisterClasses[PPR_3bRegClassID],
    6742             :     PPR_3bSubClassMask,
    6743             :     SuperRegIdxSeqs + 1,
    6744             :     LaneBitmask(0x00000001),
    6745             :     0,
    6746             :     false, /* HasDisjunctSubRegs */
    6747             :     false, /* CoveredBySubRegs */
    6748             :     PPR_3bSuperclasses,
    6749             :     nullptr
    6750             :   };
    6751             : 
    6752             :   extern const TargetRegisterClass GPR32allRegClass = {
    6753             :     &AArch64MCRegisterClasses[GPR32allRegClassID],
    6754             :     GPR32allSubClassMask,
    6755             :     SuperRegIdxSeqs + 10,
    6756             :     LaneBitmask(0x00000001),
    6757             :     0,
    6758             :     false, /* HasDisjunctSubRegs */
    6759             :     false, /* CoveredBySubRegs */
    6760             :     NullRegClasses,
    6761             :     nullptr
    6762             :   };
    6763             : 
    6764             :   extern const TargetRegisterClass FPR32RegClass = {
    6765             :     &AArch64MCRegisterClasses[FPR32RegClassID],
    6766             :     FPR32SubClassMask,
    6767             :     SuperRegIdxSeqs + 49,
    6768             :     LaneBitmask(0x00000001),
    6769             :     0,
    6770             :     false, /* HasDisjunctSubRegs */
    6771             :     false, /* CoveredBySubRegs */
    6772             :     NullRegClasses,
    6773             :     nullptr
    6774             :   };
    6775             : 
    6776             :   extern const TargetRegisterClass GPR32RegClass = {
    6777             :     &AArch64MCRegisterClasses[GPR32RegClassID],
    6778             :     GPR32SubClassMask,
    6779             :     SuperRegIdxSeqs + 10,
    6780             :     LaneBitmask(0x00000001),
    6781             :     0,
    6782             :     false, /* HasDisjunctSubRegs */
    6783             :     false, /* CoveredBySubRegs */
    6784             :     GPR32Superclasses,
    6785             :     GPR32GetRawAllocationOrder
    6786             :   };
    6787             : 
    6788             :   extern const TargetRegisterClass GPR32spRegClass = {
    6789             :     &AArch64MCRegisterClasses[GPR32spRegClassID],
    6790             :     GPR32spSubClassMask,
    6791             :     SuperRegIdxSeqs + 10,
    6792             :     LaneBitmask(0x00000001),
    6793             :     0,
    6794             :     false, /* HasDisjunctSubRegs */
    6795             :     false, /* CoveredBySubRegs */
    6796             :     GPR32spSuperclasses,
    6797             :     GPR32spGetRawAllocationOrder
    6798             :   };
    6799             : 
    6800             :   extern const TargetRegisterClass GPR32commonRegClass = {
    6801             :     &AArch64MCRegisterClasses[GPR32commonRegClassID],
    6802             :     GPR32commonSubClassMask,
    6803             :     SuperRegIdxSeqs + 10,
    6804             :     LaneBitmask(0x00000001),
    6805             :     0,
    6806             :     false, /* HasDisjunctSubRegs */
    6807             :     false, /* CoveredBySubRegs */
    6808             :     GPR32commonSuperclasses,
    6809             :     GPR32commonGetRawAllocationOrder
    6810             :   };
    6811             : 
    6812             :   extern const TargetRegisterClass CCRRegClass = {
    6813             :     &AArch64MCRegisterClasses[CCRRegClassID],
    6814             :     CCRSubClassMask,
    6815             :     SuperRegIdxSeqs + 1,
    6816             :     LaneBitmask(0x00000001),
    6817             :     0,
    6818             :     false, /* HasDisjunctSubRegs */
    6819             :     false, /* CoveredBySubRegs */
    6820             :     NullRegClasses,
    6821             :     nullptr
    6822             :   };
    6823             : 
    6824             :   extern const TargetRegisterClass GPR32sponlyRegClass = {
    6825             :     &AArch64MCRegisterClasses[GPR32sponlyRegClassID],
    6826             :     GPR32sponlySubClassMask,
    6827             :     SuperRegIdxSeqs + 0,
    6828             :     LaneBitmask(0x00000001),
    6829             :     0,
    6830             :     false, /* HasDisjunctSubRegs */
    6831             :     false, /* CoveredBySubRegs */
    6832             :     GPR32sponlySuperclasses,
    6833             :     nullptr
    6834             :   };
    6835             : 
    6836             :   extern const TargetRegisterClass WSeqPairsClassRegClass = {
    6837             :     &AArch64MCRegisterClasses[WSeqPairsClassRegClassID],
    6838             :     WSeqPairsClassSubClassMask,
    6839             :     SuperRegIdxSeqs + 69,
    6840             :     LaneBitmask(0x00000030),
    6841             :     0,
    6842             :     true, /* HasDisjunctSubRegs */
    6843             :     true, /* CoveredBySubRegs */
    6844             :     NullRegClasses,
    6845             :     nullptr
    6846             :   };
    6847             : 
    6848             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass = {
    6849             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32commonRegClassID],
    6850             :     WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask,
    6851             :     SuperRegIdxSeqs + 69,
    6852             :     LaneBitmask(0x00000030),
    6853             :     0,
    6854             :     true, /* HasDisjunctSubRegs */
    6855             :     true, /* CoveredBySubRegs */
    6856             :     WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses,
    6857             :     nullptr
    6858             :   };
    6859             : 
    6860             :   extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
    6861             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
    6862             :     WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
    6863             :     SuperRegIdxSeqs + 69,
    6864             :     LaneBitmask(0x00000030),
    6865             :     0,
    6866             :     true, /* HasDisjunctSubRegs */
    6867             :     true, /* CoveredBySubRegs */
    6868             :     WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
    6869             :     nullptr
    6870             :   };
    6871             : 
    6872             :   extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
    6873             :     &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
    6874             :     WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
    6875             :     SuperRegIdxSeqs + 69,
    6876             :     LaneBitmask(0x00000030),
    6877             :     0,
    6878             :     true, /* HasDisjunctSubRegs */
    6879             :     true, /* CoveredBySubRegs */
    6880             :     WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
    6881             :     nullptr
    6882             :   };
    6883             : 
    6884             :   extern const TargetRegisterClass GPR64allRegClass = {
    6885             :     &AArch64MCRegisterClasses[GPR64allRegClassID],
    6886             :     GPR64allSubClassMask,
    6887             :     SuperRegIdxSeqs + 2,
    6888             :     LaneBitmask(0x00000008),
    6889             :     0,
    6890             :     false, /* HasDisjunctSubRegs */
    6891             :     false, /* CoveredBySubRegs */
    6892             :     NullRegClasses,
    6893             :     nullptr
    6894             :   };
    6895             : 
    6896             :   extern const TargetRegisterClass FPR64RegClass = {
    6897             :     &AArch64MCRegisterClasses[FPR64RegClassID],
    6898             :     FPR64SubClassMask,
    6899             :     SuperRegIdxSeqs + 26,
    6900             :     LaneBitmask(0x00000001),
    6901             :     0,
    6902             :     false, /* HasDisjunctSubRegs */
    6903             :     false, /* CoveredBySubRegs */
    6904             :     NullRegClasses,
    6905             :     nullptr
    6906             :   };
    6907             : 
    6908             :   extern const TargetRegisterClass GPR64RegClass = {
    6909             :     &AArch64MCRegisterClasses[GPR64RegClassID],
    6910             :     GPR64SubClassMask,
    6911             :     SuperRegIdxSeqs + 2,
    6912             :     LaneBitmask(0x00000008),
    6913             :     0,
    6914             :     false, /* HasDisjunctSubRegs */
    6915             :     false, /* CoveredBySubRegs */
    6916             :     GPR64Superclasses,
    6917             :     GPR64GetRawAllocationOrder
    6918             :   };
    6919             : 
    6920             :   extern const TargetRegisterClass GPR64spRegClass = {
    6921             :     &AArch64MCRegisterClasses[GPR64spRegClassID],
    6922             :     GPR64spSubClassMask,
    6923             :     SuperRegIdxSeqs + 2,
    6924             :     LaneBitmask(0x00000008),
    6925             :     0,
    6926             :     false, /* HasDisjunctSubRegs */
    6927             :     false, /* CoveredBySubRegs */
    6928             :     GPR64spSuperclasses,
    6929             :     GPR64spGetRawAllocationOrder
    6930             :   };
    6931             : 
    6932             :   extern const TargetRegisterClass GPR64commonRegClass = {
    6933             :     &AArch64MCRegisterClasses[GPR64commonRegClassID],
    6934             :     GPR64commonSubClassMask,
    6935             :     SuperRegIdxSeqs + 2,
    6936             :     LaneBitmask(0x00000008),
    6937             :     0,
    6938             :     false, /* HasDisjunctSubRegs */
    6939             :     false, /* CoveredBySubRegs */
    6940             :     GPR64commonSuperclasses,
    6941             :     GPR64commonGetRawAllocationOrder
    6942             :   };
    6943             : 
    6944             :   extern const TargetRegisterClass tcGPR64RegClass = {
    6945             :     &AArch64MCRegisterClasses[tcGPR64RegClassID],
    6946             :     tcGPR64SubClassMask,
    6947             :     SuperRegIdxSeqs + 2,
    6948             :     LaneBitmask(0x00000008),
    6949             :     0,
    6950             :     false, /* HasDisjunctSubRegs */
    6951             :     false, /* CoveredBySubRegs */
    6952             :     tcGPR64Superclasses,
    6953             :     nullptr
    6954             :   };
    6955             : 
    6956             :   extern const TargetRegisterClass GPR64sponlyRegClass = {
    6957             :     &AArch64MCRegisterClasses[GPR64sponlyRegClassID],
    6958             :     GPR64sponlySubClassMask,
    6959             :     SuperRegIdxSeqs + 1,
    6960             :     LaneBitmask(0x00000008),
    6961             :     0,
    6962             :     false, /* HasDisjunctSubRegs */
    6963             :     false, /* CoveredBySubRegs */
    6964             :     GPR64sponlySuperclasses,
    6965             :     nullptr
    6966             :   };
    6967             : 
    6968             :   extern const TargetRegisterClass DDRegClass = {
    6969             :     &AArch64MCRegisterClasses[DDRegClassID],
    6970             :     DDSubClassMask,
    6971             :     SuperRegIdxSeqs + 95,
    6972             :     LaneBitmask(0x00000081),
    6973             :     0,
    6974             :     true, /* HasDisjunctSubRegs */
    6975             :     true, /* CoveredBySubRegs */
    6976             :     NullRegClasses,
    6977             :     nullptr
    6978             :   };
    6979             : 
    6980             :   extern const TargetRegisterClass XSeqPairsClassRegClass = {
    6981             :     &AArch64MCRegisterClasses[XSeqPairsClassRegClassID],
    6982             :     XSeqPairsClassSubClassMask,
    6983             :     SuperRegIdxSeqs + 1,
    6984             :     LaneBitmask(0x00002008),
    6985             :     0,
    6986             :     true, /* HasDisjunctSubRegs */
    6987             :     true, /* CoveredBySubRegs */
    6988             :     NullRegClasses,
    6989             :     nullptr
    6990             :   };
    6991             : 
    6992             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass = {
    6993             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID],
    6994             :     XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask,
    6995             :     SuperRegIdxSeqs + 1,
    6996             :     LaneBitmask(0x00002008),
    6997             :     0,
    6998             :     true, /* HasDisjunctSubRegs */
    6999             :     true, /* CoveredBySubRegs */
    7000             :     XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses,
    7001             :     nullptr
    7002             :   };
    7003             : 
    7004             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
    7005             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
    7006             :     XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
    7007             :     SuperRegIdxSeqs + 1,
    7008             :     LaneBitmask(0x00002008),
    7009             :     0,
    7010             :     true, /* HasDisjunctSubRegs */
    7011             :     true, /* CoveredBySubRegs */
    7012             :     XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
    7013             :     nullptr
    7014             :   };
    7015             : 
    7016             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
    7017             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
    7018             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
    7019             :     SuperRegIdxSeqs + 1,
    7020             :     LaneBitmask(0x00002008),
    7021             :     0,
    7022             :     true, /* HasDisjunctSubRegs */
    7023             :     true, /* CoveredBySubRegs */
    7024             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
    7025             :     nullptr
    7026             :   };
    7027             : 
    7028             :   extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass = {
    7029             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_tcGPR64RegClassID],
    7030             :     XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask,
    7031             :     SuperRegIdxSeqs + 1,
    7032             :     LaneBitmask(0x00002008),
    7033             :     0,
    7034             :     true, /* HasDisjunctSubRegs */
    7035             :     true, /* CoveredBySubRegs */
    7036             :     XSeqPairsClass_with_sube64_in_tcGPR64Superclasses,
    7037             :     nullptr
    7038             :   };
    7039             : 
    7040             :   extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
    7041             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
    7042             :     XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
    7043             :     SuperRegIdxSeqs + 1,
    7044             :     LaneBitmask(0x00002008),
    7045             :     0,
    7046             :     true, /* HasDisjunctSubRegs */
    7047             :     true, /* CoveredBySubRegs */
    7048             :     XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
    7049             :     nullptr
    7050             :   };
    7051             : 
    7052             :   extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
    7053             :     &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
    7054             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
    7055             :     SuperRegIdxSeqs + 1,
    7056             :     LaneBitmask(0x00002008),
    7057             :     0,
    7058             :     true, /* HasDisjunctSubRegs */
    7059             :     true, /* CoveredBySubRegs */
    7060             :     XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
    7061             :     nullptr
    7062             :   };
    7063             : 
    7064             :   extern const TargetRegisterClass FPR128RegClass = {
    7065             :     &AArch64MCRegisterClasses[FPR128RegClassID],
    7066             :     FPR128SubClassMask,
    7067             :     SuperRegIdxSeqs + 60,
    7068             :     LaneBitmask(0x00000001),
    7069             :     0,
    7070             :     false, /* HasDisjunctSubRegs */
    7071             :     false, /* CoveredBySubRegs */
    7072             :     NullRegClasses,
    7073             :     nullptr
    7074             :   };
    7075             : 
    7076             :   extern const TargetRegisterClass ZPRRegClass = {
    7077             :     &AArch64MCRegisterClasses[ZPRRegClassID],
    7078             :     ZPRSubClassMask,
    7079             :     SuperRegIdxSeqs + 5,
    7080             :     LaneBitmask(0x00000041),
    7081             :     0,
    7082             :     true, /* HasDisjunctSubRegs */
    7083             :     false, /* CoveredBySubRegs */
    7084             :     NullRegClasses,
    7085             :     nullptr
    7086             :   };
    7087             : 
    7088             :   extern const TargetRegisterClass FPR128_loRegClass = {
    7089             :     &AArch64MCRegisterClasses[FPR128_loRegClassID],
    7090             :     FPR128_loSubClassMask,
    7091             :     SuperRegIdxSeqs + 60,
    7092             :     LaneBitmask(0x00000001),
    7093             :     0,
    7094             :     false, /* HasDisjunctSubRegs */
    7095             :     false, /* CoveredBySubRegs */
    7096             :     FPR128_loSuperclasses,
    7097             :     nullptr
    7098             :   };
    7099             : 
    7100             :   extern const TargetRegisterClass ZPR_4bRegClass = {
    7101             :     &AArch64MCRegisterClasses[ZPR_4bRegClassID],
    7102             :     ZPR_4bSubClassMask,
    7103             :     SuperRegIdxSeqs + 5,
    7104             :     LaneBitmask(0x00000041),
    7105             :     0,
    7106             :     true, /* HasDisjunctSubRegs */
    7107             :     false, /* CoveredBySubRegs */
    7108             :     ZPR_4bSuperclasses,
    7109             :     nullptr
    7110             :   };
    7111             : 
    7112             :   extern const TargetRegisterClass ZPR_3bRegClass = {
    7113             :     &AArch64MCRegisterClasses[ZPR_3bRegClassID],
    7114             :     ZPR_3bSubClassMask,
    7115             :     SuperRegIdxSeqs + 5,
    7116             :     LaneBitmask(0x00000041),
    7117             :     0,
    7118             :     true, /* HasDisjunctSubRegs */
    7119             :     false, /* CoveredBySubRegs */
    7120             :     ZPR_3bSuperclasses,
    7121             :     nullptr
    7122             :   };
    7123             : 
    7124             :   extern const TargetRegisterClass DDDRegClass = {
    7125             :     &AArch64MCRegisterClasses[DDDRegClassID],
    7126             :     DDDSubClassMask,
    7127             :     SuperRegIdxSeqs + 83,
    7128             :     LaneBitmask(0x00000281),
    7129             :     0,
    7130             :     true, /* HasDisjunctSubRegs */
    7131             :     true, /* CoveredBySubRegs */
    7132             :     NullRegClasses,
    7133             :     nullptr
    7134             :   };
    7135             : 
    7136             :   extern const TargetRegisterClass DDDDRegClass = {
    7137             :     &AArch64MCRegisterClasses[DDDDRegClassID],
    7138             :     DDDDSubClassMask,
    7139             :     SuperRegIdxSeqs + 71,
    7140             :     LaneBitmask(0x00000381),
    7141             :     0,
    7142             :     true, /* HasDisjunctSubRegs */
    7143             :     true, /* CoveredBySubRegs */
    7144             :     NullRegClasses,
    7145             :     nullptr
    7146             :   };
    7147             : 
    7148             :   extern const TargetRegisterClass QQRegClass = {
    7149             :     &AArch64MCRegisterClasses[QQRegClassID],
    7150             :     QQSubClassMask,
    7151             :     SuperRegIdxSeqs + 105,
    7152             :     LaneBitmask(0x00000401),
    7153             :     0,
    7154             :     true, /* HasDisjunctSubRegs */
    7155             :     true, /* CoveredBySubRegs */
    7156             :     NullRegClasses,
    7157             :     nullptr
    7158             :   };
    7159             : 
    7160             :   extern const TargetRegisterClass ZPR2RegClass = {
    7161             :     &AArch64MCRegisterClasses[ZPR2RegClassID],
    7162             :     ZPR2SubClassMask,
    7163             :     SuperRegIdxSeqs + 79,
    7164             :     LaneBitmask(0x0000C041),
    7165             :     0,
    7166             :     true, /* HasDisjunctSubRegs */
    7167             :     true, /* CoveredBySubRegs */
    7168             :     NullRegClasses,
    7169             :     nullptr
    7170             :   };
    7171             : 
    7172             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass = {
    7173             :     &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_loRegClassID],
    7174             :     QQ_with_qsub0_in_FPR128_loSubClassMask,
    7175             :     SuperRegIdxSeqs + 105,
    7176             :     LaneBitmask(0x00000401),
    7177             :     0,
    7178             :     true, /* HasDisjunctSubRegs */
    7179             :     true, /* CoveredBySubRegs */
    7180             :     QQ_with_qsub0_in_FPR128_loSuperclasses,
    7181             :     nullptr
    7182             :   };
    7183             : 
    7184             :   extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass = {
    7185             :     &AArch64MCRegisterClasses[QQ_with_qsub1_in_FPR128_loRegClassID],
    7186             :     QQ_with_qsub1_in_FPR128_loSubClassMask,
    7187             :     SuperRegIdxSeqs + 105,
    7188             :     LaneBitmask(0x00000401),
    7189             :     0,
    7190             :     true, /* HasDisjunctSubRegs */
    7191             :     true, /* CoveredBySubRegs */
    7192             :     QQ_with_qsub1_in_FPR128_loSuperclasses,
    7193             :     nullptr
    7194             :   };
    7195             : 
    7196             :   extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass = {
    7197             :     &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_4bRegClassID],
    7198             :     ZPR2_with_zsub1_in_ZPR_4bSubClassMask,
    7199             :     SuperRegIdxSeqs + 79,
    7200             :     LaneBitmask(0x0000C041),
    7201             :     0,
    7202             :     true, /* HasDisjunctSubRegs */
    7203             :     true, /* CoveredBySubRegs */
    7204             :     ZPR2_with_zsub1_in_ZPR_4bSuperclasses,
    7205             :     nullptr
    7206             :   };
    7207             : 
    7208             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass = {
    7209             :     &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_loRegClassID],
    7210             :     ZPR2_with_zsub_in_FPR128_loSubClassMask,
    7211             :     SuperRegIdxSeqs + 79,
    7212             :     LaneBitmask(0x0000C041),
    7213             :     0,
    7214             :     true, /* HasDisjunctSubRegs */
    7215             :     true, /* CoveredBySubRegs */
    7216             :     ZPR2_with_zsub_in_FPR128_loSuperclasses,
    7217             :     nullptr
    7218             :   };
    7219             : 
    7220             :   extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass = {
    7221             :     &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID],
    7222             :     QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask,
    7223             :     SuperRegIdxSeqs + 105,
    7224             :     LaneBitmask(0x00000401),
    7225             :     0,
    7226             :     true, /* HasDisjunctSubRegs */
    7227             :     true, /* CoveredBySubRegs */
    7228             :     QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses,
    7229             :     nullptr
    7230             :   };
    7231             : 
    7232             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass = {
    7233             :     &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID],
    7234             :     ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSubClassMask,
    7235             :     SuperRegIdxSeqs + 79,
    7236             :     LaneBitmask(0x0000C041),
    7237             :     0,
    7238             :     true, /* HasDisjunctSubRegs */
    7239             :     true, /* CoveredBySubRegs */
    7240             :     ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses,
    7241             :     nullptr
    7242             :   };
    7243             : 
    7244             :   extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass = {
    7245             :     &AArch64MCRegisterClasses[ZPR2_with_zsub0_in_ZPR_3bRegClassID],
    7246             :     ZPR2_with_zsub0_in_ZPR_3bSubClassMask,
    7247             :     SuperRegIdxSeqs + 79,
    7248             :     LaneBitmask(0x0000C041),
    7249             :     0,
    7250             :     true, /* HasDisjunctSubRegs */
    7251             :     true, /* CoveredBySubRegs */
    7252             :     ZPR2_with_zsub0_in_ZPR_3bSuperclasses,
    7253             :     nullptr
    7254             :   };
    7255             : 
    7256             :   extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass = {
    7257             :     &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_3bRegClassID],
    7258             :     ZPR2_with_zsub1_in_ZPR_3bSubClassMask,
    7259             :     SuperRegIdxSeqs + 79,
    7260             :     LaneBitmask(0x0000C041),
    7261             :     0,
    7262             :     true, /* HasDisjunctSubRegs */
    7263             :     true, /* CoveredBySubRegs */
    7264             :     ZPR2_with_zsub1_in_ZPR_3bSuperclasses,
    7265             :     nullptr
    7266             :   };
    7267             : 
    7268             :   extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass = {
    7269             :     &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID],
    7270             :     ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSubClassMask,
    7271             :     SuperRegIdxSeqs + 79,
    7272             :     LaneBitmask(0x0000C041),
    7273             :     0,
    7274             :     true, /* HasDisjunctSubRegs */
    7275             :     true, /* CoveredBySubRegs */
    7276             :     ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses,
    7277             :     nullptr
    7278             :   };
    7279             : 
    7280             :   extern const TargetRegisterClass QQQRegClass = {
    7281             :     &AArch64MCRegisterClasses[QQQRegClassID],
    7282             :     QQQSubClassMask,
    7283             :     SuperRegIdxSeqs + 90,
    7284             :     LaneBitmask(0x00001401),
    7285             :     0,
    7286             :     true, /* HasDisjunctSubRegs */
    7287             :     true, /* CoveredBySubRegs */
    7288             :     NullRegClasses,
    7289             :     nullptr
    7290             :   };
    7291             : 
    7292             :   extern const TargetRegisterClass ZPR3RegClass = {
    7293             :     &AArch64MCRegisterClasses[ZPR3RegClassID],
    7294             :     ZPR3SubClassMask,
    7295             :     SuperRegIdxSeqs + 76,
    7296             :     LaneBitmask(0x000CC041),
    7297             :     0,
    7298             :     true, /* HasDisjunctSubRegs */
    7299             :     true, /* CoveredBySubRegs */
    7300             :     NullRegClasses,
    7301             :     nullptr
    7302             :   };
    7303             : 
    7304             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass = {
    7305             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_loRegClassID],
    7306             :     QQQ_with_qsub0_in_FPR128_loSubClassMask,
    7307             :     SuperRegIdxSeqs + 90,
    7308             :     LaneBitmask(0x00001401),
    7309             :     0,
    7310             :     true, /* HasDisjunctSubRegs */
    7311             :     true, /* CoveredBySubRegs */
    7312             :     QQQ_with_qsub0_in_FPR128_loSuperclasses,
    7313             :     nullptr
    7314             :   };
    7315             : 
    7316             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass = {
    7317             :     &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_loRegClassID],
    7318             :     QQQ_with_qsub1_in_FPR128_loSubClassMask,
    7319             :     SuperRegIdxSeqs + 90,
    7320             :     LaneBitmask(0x00001401),
    7321             :     0,
    7322             :     true, /* HasDisjunctSubRegs */
    7323             :     true, /* CoveredBySubRegs */
    7324             :     QQQ_with_qsub1_in_FPR128_loSuperclasses,
    7325             :     nullptr
    7326             :   };
    7327             : 
    7328             :   extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass = {
    7329             :     &AArch64MCRegisterClasses[QQQ_with_qsub2_in_FPR128_loRegClassID],
    7330             :     QQQ_with_qsub2_in_FPR128_loSubClassMask,
    7331             :     SuperRegIdxSeqs + 90,
    7332             :     LaneBitmask(0x00001401),
    7333             :     0,
    7334             :     true, /* HasDisjunctSubRegs */
    7335             :     true, /* CoveredBySubRegs */
    7336             :     QQQ_with_qsub2_in_FPR128_loSuperclasses,
    7337             :     nullptr
    7338             :   };
    7339             : 
    7340             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass = {
    7341             :     &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_4bRegClassID],
    7342             :     ZPR3_with_zsub1_in_ZPR_4bSubClassMask,
    7343             :     SuperRegIdxSeqs + 76,
    7344             :     LaneBitmask(0x000CC041),
    7345             :     0,
    7346             :     true, /* HasDisjunctSubRegs */
    7347             :     true, /* CoveredBySubRegs */
    7348             :     ZPR3_with_zsub1_in_ZPR_4bSuperclasses,
    7349             :     nullptr
    7350             :   };
    7351             : 
    7352             :   extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass = {
    7353             :     &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_4bRegClassID],
    7354             :     ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
    7355             :     SuperRegIdxSeqs + 76,
    7356             :     LaneBitmask(0x000CC041),
    7357             :     0,
    7358             :     true, /* HasDisjunctSubRegs */
    7359             :     true, /* CoveredBySubRegs */
    7360             :     ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
    7361             :     nullptr
    7362             :   };
    7363             : 
    7364             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass = {
    7365             :     &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_loRegClassID],
    7366             :     ZPR3_with_zsub_in_FPR128_loSubClassMask,
    7367             :     SuperRegIdxSeqs + 76,
    7368             :     LaneBitmask(0x000CC041),
    7369             :     0,
    7370             :     true, /* HasDisjunctSubRegs */
    7371             :     true, /* CoveredBySubRegs */
    7372             :     ZPR3_with_zsub_in_FPR128_loSuperclasses,
    7373             :     nullptr
    7374             :   };
    7375             : 
    7376             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass = {
    7377             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID],
    7378             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask,
    7379             :     SuperRegIdxSeqs + 90,
    7380             :     LaneBitmask(0x00001401),
    7381             :     0,
    7382             :     true, /* HasDisjunctSubRegs */
    7383             :     true, /* CoveredBySubRegs */
    7384             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses,
    7385             :     nullptr
    7386             :   };
    7387             : 
    7388             :   extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
    7389             :     &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
    7390             :     QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
    7391             :     SuperRegIdxSeqs + 90,
    7392             :     LaneBitmask(0x00001401),
    7393             :     0,
    7394             :     true, /* HasDisjunctSubRegs */
    7395             :     true, /* CoveredBySubRegs */
    7396             :     QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
    7397             :     nullptr
    7398             :   };
    7399             : 
    7400             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = {
    7401             :     &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID],
    7402             :     ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
    7403             :     SuperRegIdxSeqs + 76,
    7404             :     LaneBitmask(0x000CC041),
    7405             :     0,
    7406             :     true, /* HasDisjunctSubRegs */
    7407             :     true, /* CoveredBySubRegs */
    7408             :     ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
    7409             :     nullptr
    7410             :   };
    7411             : 
    7412             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass = {
    7413             :     &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID],
    7414             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSubClassMask,
    7415             :     SuperRegIdxSeqs + 76,
    7416             :     LaneBitmask(0x000CC041),
    7417             :     0,
    7418             :     true, /* HasDisjunctSubRegs */
    7419             :     true, /* CoveredBySubRegs */
    7420             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses,
    7421             :     nullptr
    7422             :   };
    7423             : 
    7424             :   extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
    7425             :     &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
    7426             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
    7427             :     SuperRegIdxSeqs + 90,
    7428             :     LaneBitmask(0x00001401),
    7429             :     0,
    7430             :     true, /* HasDisjunctSubRegs */
    7431             :     true, /* CoveredBySubRegs */
    7432             :     QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
    7433             :     nullptr
    7434             :   };
    7435             : 
    7436             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = {
    7437             :     &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID],
    7438             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
    7439             :     SuperRegIdxSeqs + 76,
    7440             :     LaneBitmask(0x000CC041),
    7441             :     0,
    7442             :     true, /* HasDisjunctSubRegs */
    7443             :     true, /* CoveredBySubRegs */
    7444             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
    7445             :     nullptr
    7446             :   };
    7447             : 
    7448             :   extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass = {
    7449             :     &AArch64MCRegisterClasses[ZPR3_with_zsub0_in_ZPR_3bRegClassID],
    7450             :     ZPR3_with_zsub0_in_ZPR_3bSubClassMask,
    7451             :     SuperRegIdxSeqs + 76,
    7452             :     LaneBitmask(0x000CC041),
    7453             :     0,
    7454             :     true, /* HasDisjunctSubRegs */
    7455             :     true, /* CoveredBySubRegs */
    7456             :     ZPR3_with_zsub0_in_ZPR_3bSuperclasses,
    7457             :     nullptr
    7458             :   };
    7459             : 
    7460             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass = {
    7461             :     &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_3bRegClassID],
    7462             :     ZPR3_with_zsub1_in_ZPR_3bSubClassMask,
    7463             :     SuperRegIdxSeqs + 76,
    7464             :     LaneBitmask(0x000CC041),
    7465             :     0,
    7466             :     true, /* HasDisjunctSubRegs */
    7467             :     true, /* CoveredBySubRegs */
    7468             :     ZPR3_with_zsub1_in_ZPR_3bSuperclasses,
    7469             :     nullptr
    7470             :   };
    7471             : 
    7472             :   extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass = {
    7473             :     &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_3bRegClassID],
    7474             :     ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
    7475             :     SuperRegIdxSeqs + 76,
    7476             :     LaneBitmask(0x000CC041),
    7477             :     0,
    7478             :     true, /* HasDisjunctSubRegs */
    7479             :     true, /* CoveredBySubRegs */
    7480             :     ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
    7481             :     nullptr
    7482             :   };
    7483             : 
    7484             :   extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = {
    7485             :     &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID],
    7486             :     ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
    7487             :     SuperRegIdxSeqs + 76,
    7488             :     LaneBitmask(0x000CC041),
    7489             :     0,
    7490             :     true, /* HasDisjunctSubRegs */
    7491             :     true, /* CoveredBySubRegs */
    7492             :     ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
    7493             :     nullptr
    7494             :   };
    7495             : 
    7496             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass = {
    7497             :     &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID],
    7498             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSubClassMask,
    7499             :     SuperRegIdxSeqs + 76,
    7500             :     LaneBitmask(0x000CC041),
    7501             :     0,
    7502             :     true, /* HasDisjunctSubRegs */
    7503             :     true, /* CoveredBySubRegs */
    7504             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses,
    7505             :     nullptr
    7506             :   };
    7507             : 
    7508             :   extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = {
    7509             :     &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID],
    7510             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
    7511             :     SuperRegIdxSeqs + 76,
    7512             :     LaneBitmask(0x000CC041),
    7513             :     0,
    7514             :     true, /* HasDisjunctSubRegs */
    7515             :     true, /* CoveredBySubRegs */
    7516             :     ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
    7517             :     nullptr
    7518             :   };
    7519             : 
    7520             :   extern const TargetRegisterClass QQQQRegClass = {
    7521             :     &AArch64MCRegisterClasses[QQQQRegClassID],
    7522             :     QQQQSubClassMask,
    7523             :     SuperRegIdxSeqs + 74,
    7524             :     LaneBitmask(0x00001C01),
    7525             :     0,
    7526             :     true, /* HasDisjunctSubRegs */
    7527             :     true, /* CoveredBySubRegs */
    7528             :     NullRegClasses,
    7529             :     nullptr
    7530             :   };
    7531             : 
    7532             :   extern const TargetRegisterClass ZPR4RegClass = {
    7533             :     &AArch64MCRegisterClasses[ZPR4RegClassID],
    7534             :     ZPR4SubClassMask,
    7535             :     SuperRegIdxSeqs + 1,
    7536             :     LaneBitmask(0x000FC041),
    7537             :     0,
    7538             :     true, /* HasDisjunctSubRegs */
    7539             :     true, /* CoveredBySubRegs */
    7540             :     NullRegClasses,
    7541             :     nullptr
    7542             :   };
    7543             : 
    7544             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass = {
    7545             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_loRegClassID],
    7546             :     QQQQ_with_qsub0_in_FPR128_loSubClassMask,
    7547             :     SuperRegIdxSeqs + 74,
    7548             :     LaneBitmask(0x00001C01),
    7549             :     0,
    7550             :     true, /* HasDisjunctSubRegs */
    7551             :     true, /* CoveredBySubRegs */
    7552             :     QQQQ_with_qsub0_in_FPR128_loSuperclasses,
    7553             :     nullptr
    7554             :   };
    7555             : 
    7556             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass = {
    7557             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_loRegClassID],
    7558             :     QQQQ_with_qsub1_in_FPR128_loSubClassMask,
    7559             :     SuperRegIdxSeqs + 74,
    7560             :     LaneBitmask(0x00001C01),
    7561             :     0,
    7562             :     true, /* HasDisjunctSubRegs */
    7563             :     true, /* CoveredBySubRegs */
    7564             :     QQQQ_with_qsub1_in_FPR128_loSuperclasses,
    7565             :     nullptr
    7566             :   };
    7567             : 
    7568             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass = {
    7569             :     &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_loRegClassID],
    7570             :     QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    7571             :     SuperRegIdxSeqs + 74,
    7572             :     LaneBitmask(0x00001C01),
    7573             :     0,
    7574             :     true, /* HasDisjunctSubRegs */
    7575             :     true, /* CoveredBySubRegs */
    7576             :     QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    7577             :     nullptr
    7578             :   };
    7579             : 
    7580             :   extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass = {
    7581             :     &AArch64MCRegisterClasses[QQQQ_with_qsub3_in_FPR128_loRegClassID],
    7582             :     QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    7583             :     SuperRegIdxSeqs + 74,
    7584             :     LaneBitmask(0x00001C01),
    7585             :     0,
    7586             :     true, /* HasDisjunctSubRegs */
    7587             :     true, /* CoveredBySubRegs */
    7588             :     QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    7589             :     nullptr
    7590             :   };
    7591             : 
    7592             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass = {
    7593             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4bRegClassID],
    7594             :     ZPR4_with_zsub1_in_ZPR_4bSubClassMask,
    7595             :     SuperRegIdxSeqs + 1,
    7596             :     LaneBitmask(0x000FC041),
    7597             :     0,
    7598             :     true, /* HasDisjunctSubRegs */
    7599             :     true, /* CoveredBySubRegs */
    7600             :     ZPR4_with_zsub1_in_ZPR_4bSuperclasses,
    7601             :     nullptr
    7602             :   };
    7603             : 
    7604             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass = {
    7605             :     &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_4bRegClassID],
    7606             :     ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
    7607             :     SuperRegIdxSeqs + 1,
    7608             :     LaneBitmask(0x000FC041),
    7609             :     0,
    7610             :     true, /* HasDisjunctSubRegs */
    7611             :     true, /* CoveredBySubRegs */
    7612             :     ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
    7613             :     nullptr
    7614             :   };
    7615             : 
    7616             :   extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass = {
    7617             :     &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_4bRegClassID],
    7618             :     ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
    7619             :     SuperRegIdxSeqs + 1,
    7620             :     LaneBitmask(0x000FC041),
    7621             :     0,
    7622             :     true, /* HasDisjunctSubRegs */
    7623             :     true, /* CoveredBySubRegs */
    7624             :     ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
    7625             :     nullptr
    7626             :   };
    7627             : 
    7628             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass = {
    7629             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_loRegClassID],
    7630             :     ZPR4_with_zsub_in_FPR128_loSubClassMask,
    7631             :     SuperRegIdxSeqs + 1,
    7632             :     LaneBitmask(0x000FC041),
    7633             :     0,
    7634             :     true, /* HasDisjunctSubRegs */
    7635             :     true, /* CoveredBySubRegs */
    7636             :     ZPR4_with_zsub_in_FPR128_loSuperclasses,
    7637             :     nullptr
    7638             :   };
    7639             : 
    7640             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass = {
    7641             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID],
    7642             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask,
    7643             :     SuperRegIdxSeqs + 74,
    7644             :     LaneBitmask(0x00001C01),
    7645             :     0,
    7646             :     true, /* HasDisjunctSubRegs */
    7647             :     true, /* CoveredBySubRegs */
    7648             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses,
    7649             :     nullptr
    7650             :   };
    7651             : 
    7652             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
    7653             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
    7654             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    7655             :     SuperRegIdxSeqs + 74,
    7656             :     LaneBitmask(0x00001C01),
    7657             :     0,
    7658             :     true, /* HasDisjunctSubRegs */
    7659             :     true, /* CoveredBySubRegs */
    7660             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    7661             :     nullptr
    7662             :   };
    7663             : 
    7664             :   extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    7665             :     &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    7666             :     QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    7667             :     SuperRegIdxSeqs + 74,
    7668             :     LaneBitmask(0x00001C01),
    7669             :     0,
    7670             :     true, /* HasDisjunctSubRegs */
    7671             :     true, /* CoveredBySubRegs */
    7672             :     QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    7673             :     nullptr
    7674             :   };
    7675             : 
    7676             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = {
    7677             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID],
    7678             :     ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
    7679             :     SuperRegIdxSeqs + 1,
    7680             :     LaneBitmask(0x000FC041),
    7681             :     0,
    7682             :     true, /* HasDisjunctSubRegs */
    7683             :     true, /* CoveredBySubRegs */
    7684             :     ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
    7685             :     nullptr
    7686             :   };
    7687             : 
    7688             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
    7689             :     &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
    7690             :     ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
    7691             :     SuperRegIdxSeqs + 1,
    7692             :     LaneBitmask(0x000FC041),
    7693             :     0,
    7694             :     true, /* HasDisjunctSubRegs */
    7695             :     true, /* CoveredBySubRegs */
    7696             :     ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
    7697             :     nullptr
    7698             :   };
    7699             : 
    7700             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass = {
    7701             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID],
    7702             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSubClassMask,
    7703             :     SuperRegIdxSeqs + 1,
    7704             :     LaneBitmask(0x000FC041),
    7705             :     0,
    7706             :     true, /* HasDisjunctSubRegs */
    7707             :     true, /* CoveredBySubRegs */
    7708             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses,
    7709             :     nullptr
    7710             :   };
    7711             : 
    7712             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
    7713             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
    7714             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
    7715             :     SuperRegIdxSeqs + 74,
    7716             :     LaneBitmask(0x00001C01),
    7717             :     0,
    7718             :     true, /* HasDisjunctSubRegs */
    7719             :     true, /* CoveredBySubRegs */
    7720             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
    7721             :     nullptr
    7722             :   };
    7723             : 
    7724             :   extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    7725             :     &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    7726             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    7727             :     SuperRegIdxSeqs + 74,
    7728             :     LaneBitmask(0x00001C01),
    7729             :     0,
    7730             :     true, /* HasDisjunctSubRegs */
    7731             :     true, /* CoveredBySubRegs */
    7732             :     QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    7733             :     nullptr
    7734             :   };
    7735             : 
    7736             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
    7737             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
    7738             :     ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
    7739             :     SuperRegIdxSeqs + 1,
    7740             :     LaneBitmask(0x000FC041),
    7741             :     0,
    7742             :     true, /* HasDisjunctSubRegs */
    7743             :     true, /* CoveredBySubRegs */
    7744             :     ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
    7745             :     nullptr
    7746             :   };
    7747             : 
    7748             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = {
    7749             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID],
    7750             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
    7751             :     SuperRegIdxSeqs + 1,
    7752             :     LaneBitmask(0x000FC041),
    7753             :     0,
    7754             :     true, /* HasDisjunctSubRegs */
    7755             :     true, /* CoveredBySubRegs */
    7756             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
    7757             :     nullptr
    7758             :   };
    7759             : 
    7760             :   extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
    7761             :     &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
    7762             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
    7763             :     SuperRegIdxSeqs + 74,
    7764             :     LaneBitmask(0x00001C01),
    7765             :     0,
    7766             :     true, /* HasDisjunctSubRegs */
    7767             :     true, /* CoveredBySubRegs */
    7768             :     QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
    7769             :     nullptr
    7770             :   };
    7771             : 
    7772             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
    7773             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
    7774             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
    7775             :     SuperRegIdxSeqs + 1,
    7776             :     LaneBitmask(0x000FC041),
    7777             :     0,
    7778             :     true, /* HasDisjunctSubRegs */
    7779             :     true, /* CoveredBySubRegs */
    7780             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
    7781             :     nullptr
    7782             :   };
    7783             : 
    7784             :   extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass = {
    7785             :     &AArch64MCRegisterClasses[ZPR4_with_zsub0_in_ZPR_3bRegClassID],
    7786             :     ZPR4_with_zsub0_in_ZPR_3bSubClassMask,
    7787             :     SuperRegIdxSeqs + 1,
    7788             :     LaneBitmask(0x000FC041),
    7789             :     0,
    7790             :     true, /* HasDisjunctSubRegs */
    7791             :     true, /* CoveredBySubRegs */
    7792             :     ZPR4_with_zsub0_in_ZPR_3bSuperclasses,
    7793             :     nullptr
    7794             :   };
    7795             : 
    7796             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass = {
    7797             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3bRegClassID],
    7798             :     ZPR4_with_zsub1_in_ZPR_3bSubClassMask,
    7799             :     SuperRegIdxSeqs + 1,
    7800             :     LaneBitmask(0x000FC041),
    7801             :     0,
    7802             :     true, /* HasDisjunctSubRegs */
    7803             :     true, /* CoveredBySubRegs */
    7804             :     ZPR4_with_zsub1_in_ZPR_3bSuperclasses,
    7805             :     nullptr
    7806             :   };
    7807             : 
    7808             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass = {
    7809             :     &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_3bRegClassID],
    7810             :     ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
    7811             :     SuperRegIdxSeqs + 1,
    7812             :     LaneBitmask(0x000FC041),
    7813             :     0,
    7814             :     true, /* HasDisjunctSubRegs */
    7815             :     true, /* CoveredBySubRegs */
    7816             :     ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
    7817             :     nullptr
    7818             :   };
    7819             : 
    7820             :   extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass = {
    7821             :     &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_3bRegClassID],
    7822             :     ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
    7823             :     SuperRegIdxSeqs + 1,
    7824             :     LaneBitmask(0x000FC041),
    7825             :     0,
    7826             :     true, /* HasDisjunctSubRegs */
    7827             :     true, /* CoveredBySubRegs */
    7828             :     ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
    7829             :     nullptr
    7830             :   };
    7831             : 
    7832             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = {
    7833             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID],
    7834             :     ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
    7835             :     SuperRegIdxSeqs + 1,
    7836             :     LaneBitmask(0x000FC041),
    7837             :     0,
    7838             :     true, /* HasDisjunctSubRegs */
    7839             :     true, /* CoveredBySubRegs */
    7840             :     ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
    7841             :     nullptr
    7842             :   };
    7843             : 
    7844             :   extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
    7845             :     &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
    7846             :     ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
    7847             :     SuperRegIdxSeqs + 1,
    7848             :     LaneBitmask(0x000FC041),
    7849             :     0,
    7850             :     true, /* HasDisjunctSubRegs */
    7851             :     true, /* CoveredBySubRegs */
    7852             :     ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
    7853             :     nullptr
    7854             :   };
    7855             : 
    7856             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass = {
    7857             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID],
    7858             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSubClassMask,
    7859             :     SuperRegIdxSeqs + 1,
    7860             :     LaneBitmask(0x000FC041),
    7861             :     0,
    7862             :     true, /* HasDisjunctSubRegs */
    7863             :     true, /* CoveredBySubRegs */
    7864             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses,
    7865             :     nullptr
    7866             :   };
    7867             : 
    7868             :   extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
    7869             :     &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
    7870             :     ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
    7871             :     SuperRegIdxSeqs + 1,
    7872             :     LaneBitmask(0x000FC041),
    7873             :     0,
    7874             :     true, /* HasDisjunctSubRegs */
    7875             :     true, /* CoveredBySubRegs */
    7876             :     ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
    7877             :     nullptr
    7878             :   };
    7879             : 
    7880             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = {
    7881             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID],
    7882             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
    7883             :     SuperRegIdxSeqs + 1,
    7884             :     LaneBitmask(0x000FC041),
    7885             :     0,
    7886             :     true, /* HasDisjunctSubRegs */
    7887             :     true, /* CoveredBySubRegs */
    7888             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
    7889             :     nullptr
    7890             :   };
    7891             : 
    7892             :   extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
    7893             :     &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
    7894             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
    7895             :     SuperRegIdxSeqs + 1,
    7896             :     LaneBitmask(0x000FC041),
    7897             :     0,
    7898             :     true, /* HasDisjunctSubRegs */
    7899             :     true, /* CoveredBySubRegs */
    7900             :     ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
    7901             :     nullptr
    7902             :   };
    7903             : 
    7904             : } // end namespace AArch64
    7905             : 
    7906             : namespace {
    7907             :   const TargetRegisterClass* const RegisterClasses[] = {
    7908             :     &AArch64::FPR8RegClass,
    7909             :     &AArch64::FPR16RegClass,
    7910             :     &AArch64::PPRRegClass,
    7911             :     &AArch64::PPR_3bRegClass,
    7912             :     &AArch64::GPR32allRegClass,
    7913             :     &AArch64::FPR32RegClass,
    7914             :     &AArch64::GPR32RegClass,
    7915             :     &AArch64::GPR32spRegClass,
    7916             :     &AArch64::GPR32commonRegClass,
    7917             :     &AArch64::CCRRegClass,
    7918             :     &AArch64::GPR32sponlyRegClass,
    7919             :     &AArch64::WSeqPairsClassRegClass,
    7920             :     &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
    7921             :     &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    7922             :     &AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
    7923             :     &AArch64::GPR64allRegClass,
    7924             :     &AArch64::FPR64RegClass,
    7925             :     &AArch64::GPR64RegClass,
    7926             :     &AArch64::GPR64spRegClass,
    7927             :     &AArch64::GPR64commonRegClass,
    7928             :     &AArch64::tcGPR64RegClass,
    7929             :     &AArch64::GPR64sponlyRegClass,
    7930             :     &AArch64::DDRegClass,
    7931             :     &AArch64::XSeqPairsClassRegClass,
    7932             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
    7933             :     &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    7934             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
    7935             :     &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
    7936             :     &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    7937             :     &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
    7938             :     &AArch64::FPR128RegClass,
    7939             :     &AArch64::ZPRRegClass,
    7940             :     &AArch64::FPR128_loRegClass,
    7941             :     &AArch64::ZPR_4bRegClass,
    7942             :     &AArch64::ZPR_3bRegClass,
    7943             :     &AArch64::DDDRegClass,
    7944             :     &AArch64::DDDDRegClass,
    7945             :     &AArch64::QQRegClass,
    7946             :     &AArch64::ZPR2RegClass,
    7947             :     &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
    7948             :     &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
    7949             :     &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
    7950             :     &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
    7951             :     &AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass,
    7952             :     &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
    7953             :     &AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClass,
    7954             :     &AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClass,
    7955             :     &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass,
    7956             :     &AArch64::QQQRegClass,
    7957             :     &AArch64::ZPR3RegClass,
    7958             :     &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
    7959             :     &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
    7960             :     &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
    7961             :     &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
    7962             :     &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
    7963             :     &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
    7964             :     &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
    7965             :     &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    7966             :     &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    7967             :     &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
    7968             :     &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
    7969             :     &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
    7970             :     &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
    7971             :     &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
    7972             :     &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
    7973             :     &AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
    7974             :     &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass,
    7975             :     &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
    7976             :     &AArch64::QQQQRegClass,
    7977             :     &AArch64::ZPR4RegClass,
    7978             :     &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
    7979             :     &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
    7980             :     &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
    7981             :     &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
    7982             :     &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
    7983             :     &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
    7984             :     &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
    7985             :     &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
    7986             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
    7987             :     &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    7988             :     &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    7989             :     &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    7990             :     &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    7991             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
    7992             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
    7993             :     &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    7994             :     &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    7995             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
    7996             :     &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
    7997             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
    7998             :     &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
    7999             :     &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
    8000             :     &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
    8001             :     &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
    8002             :     &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
    8003             :     &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
    8004             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
    8005             :     &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
    8006             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
    8007             :     &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
    8008             :   };
    8009             : } // end anonymous namespace
    8010             : 
    8011             : static const TargetRegisterInfoDesc AArch64RegInfoDesc[] = { // Extra Descriptors
    8012             :   { 0, false },
    8013             :   { 0, false },
    8014             :   { 0, true },
    8015             :   { 0, true },
    8016             :   { 0, false },
    8017             :   { 0, true },
    8018             :   { 0, true },
    8019             :   { 0, true },
    8020             :   { 0, true },
    8021             :   { 0, true },
    8022             :   { 0, true },
    8023             :   { 0, true },
    8024             :   { 0, true },
    8025             :   { 0, true },
    8026             :   { 0, true },
    8027             :   { 0, true },
    8028             :   { 0, true },
    8029             :   { 0, true },
    8030             :   { 0, true },
    8031             :   { 0, true },
    8032             :   { 0, true },
    8033             :   { 0, true },
    8034             :   { 0, true },
    8035             :   { 0, true },
    8036             :   { 0, true },
    8037             :   { 0, true },
    8038             :   { 0, true },
    8039             :   { 0, true },
    8040             :   { 0, true },
    8041             :   { 0, true },
    8042             :   { 0, true },
    8043             :   { 0, true },
    8044             :   { 0, true },
    8045             :   { 0, true },
    8046             :   { 0, true },
    8047             :   { 0, true },
    8048             :   { 0, true },
    8049             :   { 0, true },
    8050             :   { 0, true },
    8051             :   { 0, true },
    8052             :   { 0, true },
    8053             :   { 0, true },
    8054             :   { 0, true },
    8055             :   { 0, true },
    8056             :   { 0, true },
    8057             :   { 0, true },
    8058             :   { 0, true },
    8059             :   { 0, true },
    8060             :   { 0, true },
    8061             :   { 0, true },
    8062             :   { 0, true },
    8063             :   { 0, true },
    8064             :   { 0, true },
    8065             :   { 0, true },
    8066             :   { 0, true },
    8067             :   { 0, true },
    8068             :   { 0, true },
    8069             :   { 0, true },
    8070             :   { 0, true },
    8071             :   { 0, true },
    8072             :   { 0, true },
    8073             :   { 0, true },
    8074             :   { 0, true },
    8075             :   { 0, true },
    8076             :   { 0, true },
    8077             :   { 0, true },
    8078             :   { 0, true },
    8079             :   { 0, true },
    8080             :   { 0, true },
    8081             :   { 0, true },
    8082             :   { 0, true },
    8083             :   { 0, true },
    8084             :   { 0, true },
    8085             :   { 0, true },
    8086             :   { 0, true },
    8087             :   { 0, true },
    8088             :   { 0, true },
    8089             :   { 0, true },
    8090             :   { 0, true },
    8091             :   { 0, true },
    8092             :   { 0, true },
    8093             :   { 0, true },
    8094             :   { 0, true },
    8095             :   { 0, true },
    8096             :   { 0, true },
    8097             :   { 0, true },
    8098             :   { 0, true },
    8099             :   { 0, true },
    8100             :   { 0, true },
    8101             :   { 0, true },
    8102             :   { 0, true },
    8103             :   { 0, true },
    8104             :   { 0, true },
    8105             :   { 0, true },
    8106             :   { 0, true },
    8107             :   { 0, true },
    8108             :   { 0, true },
    8109             :   { 0, true },
    8110             :   { 0, true },
    8111             :   { 0, true },
    8112             :   { 0, true },
    8113             :   { 0, true },
    8114             :   { 0, true },
    8115             :   { 0, true },
    8116             :   { 0, true },
    8117             :   { 0, true },
    8118             :   { 0, true },
    8119             :   { 0, true },
    8120             :   { 0, true },
    8121             :   { 0, true },
    8122             :   { 0, true },
    8123             :   { 0, true },
    8124             :   { 0, true },
    8125             :   { 0, true },
    8126             :   { 0, true },
    8127             :   { 0, true },
    8128             :   { 0, true },
    8129             :   { 0, true },
    8130             :   { 0, true },
    8131             :   { 0, true },
    8132             :   { 0, true },
    8133             :   { 0, true },
    8134             :   { 0, true },
    8135             :   { 0, true },
    8136             :   { 0, true },
    8137             :   { 0, true },
    8138             :   { 0, true },
    8139             :   { 0, true },
    8140             :   { 0, true },
    8141             :   { 0, true },
    8142             :   { 0, true },
    8143             :   { 0, true },
    8144             :   { 0, true },
    8145             :   { 0, true },
    8146             :   { 0, true },
    8147             :   { 0, true },
    8148             :   { 0, true },
    8149             :   { 0, true },
    8150             :   { 0, true },
    8151             :   { 0, true },
    8152             :   { 0, true },
    8153             :   { 0, true },
    8154             :   { 0, true },
    8155             :   { 0, true },
    8156             :   { 0, true },
    8157             :   { 0, true },
    8158             :   { 0, true },
    8159             :   { 0, true },
    8160             :   { 0, true },
    8161             :   { 0, true },
    8162             :   { 0, true },
    8163             :   { 0, true },
    8164             :   { 0, true },
    8165             :   { 0, true },
    8166             :   { 0, true },
    8167             :   { 0, true },
    8168             :   { 0, true },
    8169             :   { 0, true },
    8170             :   { 0, true },
    8171             :   { 0, true },
    8172             :   { 0, true },
    8173             :   { 0, true },
    8174             :   { 0, true },
    8175             :   { 0, true },
    8176             :   { 0, true },
    8177             :   { 0, true },
    8178             :   { 0, true },
    8179             :   { 0, true },
    8180             :   { 0, true },
    8181             :   { 0, true },
    8182             :   { 0, true },
    8183             :   { 0, true },
    8184             :   { 0, true },
    8185             :   { 0, true },
    8186             :   { 0, true },
    8187             :   { 0, true },
    8188             :   { 0, true },
    8189             :   { 0, true },
    8190             :   { 0, true },
    8191             :   { 0, true },
    8192             :   { 0, true },
    8193             :   { 0, true },
    8194             :   { 0, true },
    8195             :   { 0, true },
    8196             :   { 0, true },
    8197             :   { 0, true },
    8198             :   { 0, true },
    8199             :   { 0, true },
    8200             :   { 0, true },
    8201             :   { 0, true },
    8202             :   { 0, true },
    8203             :   { 0, true },
    8204             :   { 0, true },
    8205             :   { 0, true },
    8206             :   { 0, true },
    8207             :   { 0, true },
    8208             :   { 0, true },
    8209             :   { 0, true },
    8210             :   { 0, true },
    8211             :   { 0, true },
    8212             :   { 0, true },
    8213             :   { 0, true },
    8214             :   { 0, true },
    8215             :   { 0, true },
    8216             :   { 0, true },
    8217             :   { 0, true },
    8218             :   { 0, true },
    8219             :   { 0, true },
    8220             :   { 0, true },
    8221             :   { 0, true },
    8222             :   { 0, true },
    8223             :   { 0, true },
    8224             :   { 0, true },
    8225             :   { 0, true },
    8226             :   { 0, true },
    8227             :   { 0, true },
    8228             :   { 0, true },
    8229             :   { 0, true },
    8230             :   { 0, true },
    8231             :   { 0, true },
    8232             :   { 0, true },
    8233             :   { 0, true },
    8234             :   { 0, true },
    8235             :   { 0, true },
    8236             :   { 0, true },
    8237             :   { 0, true },
    8238             :   { 0, true },
    8239             :   { 0, true },
    8240             :   { 0, true },
    8241             :   { 0, true },
    8242             :   { 0, true },
    8243             :   { 0, true },
    8244             :   { 0, true },
    8245             :   { 0, true },
    8246             :   { 0, true },
    8247             :   { 0, true },
    8248             :   { 0, true },
    8249             :   { 0, true },
    8250             :   { 0, true },
    8251             :   { 0, true },
    8252             :   { 0, true },
    8253             :   { 0, true },
    8254             :   { 0, true },
    8255             :   { 0, true },
    8256             :   { 0, true },
    8257             :   { 0, true },
    8258             :   { 0, true },
    8259             :   { 0, true },
    8260             :   { 0, true },
    8261             :   { 0, true },
    8262             :   { 0, true },
    8263             :   { 0, true },
    8264             :   { 0, true },
    8265             :   { 0, true },
    8266             :   { 0, true },
    8267             :   { 0, true },
    8268             :   { 0, true },
    8269             :   { 0, true },
    8270             :   { 0, true },
    8271             :   { 0, true },
    8272             :   { 0, true },
    8273             :   { 0, true },
    8274             :   { 0, true },
    8275             :   { 0, true },
    8276             :   { 0, true },
    8277             :   { 0, true },
    8278             :   { 0, true },
    8279             :   { 0, true },
    8280             :   { 0, true },
    8281             :   { 0, true },
    8282             :   { 0, true },
    8283             :   { 0, true },
    8284             :   { 0, true },
    8285             :   { 0, true },
    8286             :   { 0, true },
    8287             :   { 0, true },
    8288             :   { 0, true },
    8289             :   { 0, false },
    8290             :   { 0, false },
    8291             :   { 0, false },
    8292             :   { 0, false },
    8293             :   { 0, false },
    8294             :   { 0, false },
    8295             :   { 0, false },
    8296             :   { 0, false },
    8297             :   { 0, false },
    8298             :   { 0, false },
    8299             :   { 0, false },
    8300             :   { 0, false },
    8301             :   { 0, false },
    8302             :   { 0, false },
    8303             :   { 0, false },
    8304             :   { 0, false },
    8305             :   { 0, false },
    8306             :   { 0, false },
    8307             :   { 0, false },
    8308             :   { 0, false },
    8309             :   { 0, false },
    8310             :   { 0, false },
    8311             :   { 0, false },
    8312             :   { 0, false },
    8313             :   { 0, false },
    8314             :   { 0, false },
    8315             :   { 0, false },
    8316             :   { 0, false },
    8317             :   { 0, false },
    8318             :   { 0, false },
    8319             :   { 0, false },
    8320             :   { 0, false },
    8321             :   { 0, true },
    8322             :   { 0, true },
    8323             :   { 0, true },
    8324             :   { 0, true },
    8325             :   { 0, true },
    8326             :   { 0, true },
    8327             :   { 0, true },
    8328             :   { 0, true },
    8329             :   { 0, true },
    8330             :   { 0, true },
    8331             :   { 0, true },
    8332             :   { 0, true },
    8333             :   { 0, true },
    8334             :   { 0, true },
    8335             :   { 0, true },
    8336             :   { 0, true },
    8337             :   { 0, true },
    8338             :   { 0, true },
    8339             :   { 0, true },
    8340             :   { 0, true },
    8341             :   { 0, true },
    8342             :   { 0, true },
    8343             :   { 0, true },
    8344             :   { 0, true },
    8345             :   { 0, true },
    8346             :   { 0, true },
    8347             :   { 0, true },
    8348             :   { 0, true },
    8349             :   { 0, true },
    8350             :   { 0, true },
    8351             :   { 0, true },
    8352             :   { 0, true },
    8353             :   { 0, true },
    8354             :   { 0, true },
    8355             :   { 0, true },
    8356             :   { 0, true },
    8357             :   { 0, true },
    8358             :   { 0, true },
    8359             :   { 0, true },
    8360             :   { 0, true },
    8361             :   { 0, true },
    8362             :   { 0, true },
    8363             :   { 0, true },
    8364             :   { 0, true },
    8365             :   { 0, true },
    8366             :   { 0, true },
    8367             :   { 0, true },
    8368             :   { 0, true },
    8369             :   { 0, true },
    8370             :   { 0, true },
    8371             :   { 0, true },
    8372             :   { 0, true },
    8373             :   { 0, true },
    8374             :   { 0, true },
    8375             :   { 0, true },
    8376             :   { 0, true },
    8377             :   { 0, true },
    8378             :   { 0, true },
    8379             :   { 0, true },
    8380             :   { 0, true },
    8381             :   { 0, true },
    8382             :   { 0, true },
    8383             :   { 0, true },
    8384             :   { 0, true },
    8385             :   { 0, true },
    8386             :   { 0, true },
    8387             :   { 0, true },
    8388             :   { 0, true },
    8389             :   { 0, true },
    8390             :   { 0, true },
    8391             :   { 0, true },
    8392             :   { 0, true },
    8393             :   { 0, true },
    8394             :   { 0, true },
    8395             :   { 0, true },
    8396             :   { 0, true },
    8397             :   { 0, true },
    8398             :   { 0, true },
    8399             :   { 0, true },
    8400             :   { 0, true },
    8401             :   { 0, true },
    8402             :   { 0, true },
    8403             :   { 0, true },
    8404             :   { 0, true },
    8405             :   { 0, true },
    8406             :   { 0, true },
    8407             :   { 0, true },
    8408             :   { 0, true },
    8409             :   { 0, true },
    8410             :   { 0, true },
    8411             :   { 0, true },
    8412             :   { 0, true },
    8413             :   { 0, true },
    8414             :   { 0, true },
    8415             :   { 0, true },
    8416             :   { 0, true },
    8417             :   { 0, true },
    8418             :   { 0, true },
    8419             :   { 0, true },
    8420             :   { 0, true },
    8421             :   { 0, true },
    8422             :   { 0, true },
    8423             :   { 0, true },
    8424             :   { 0, true },
    8425             :   { 0, true },
    8426             :   { 0, true },
    8427             :   { 0, true },
    8428             :   { 0, true },
    8429             :   { 0, true },
    8430             :   { 0, true },
    8431             :   { 0, true },
    8432             :   { 0, true },
    8433             :   { 0, true },
    8434             :   { 0, true },
    8435             :   { 0, true },
    8436             :   { 0, true },
    8437             :   { 0, true },
    8438             :   { 0, true },
    8439             :   { 0, true },
    8440             :   { 0, true },
    8441             :   { 0, true },
    8442             :   { 0, true },
    8443             :   { 0, true },
    8444             :   { 0, true },
    8445             :   { 0, true },
    8446             :   { 0, true },
    8447             :   { 0, true },
    8448             :   { 0, true },
    8449             :   { 0, true },
    8450             :   { 0, true },
    8451             :   { 0, true },
    8452             :   { 0, true },
    8453             :   { 0, true },
    8454             :   { 0, true },
    8455             :   { 0, true },
    8456             :   { 0, true },
    8457             :   { 0, true },
    8458             :   { 0, true },
    8459             :   { 0, true },
    8460             :   { 0, true },
    8461             :   { 0, true },
    8462             :   { 0, true },
    8463             :   { 0, true },
    8464             :   { 0, true },
    8465             :   { 0, true },
    8466             :   { 0, true },
    8467             :   { 0, true },
    8468             :   { 0, true },
    8469             :   { 0, true },
    8470             :   { 0, true },
    8471             :   { 0, true },
    8472             :   { 0, true },
    8473             :   { 0, true },
    8474             :   { 0, true },
    8475             :   { 0, true },
    8476             :   { 0, true },
    8477             :   { 0, true },
    8478             :   { 0, true },
    8479             :   { 0, true },
    8480             :   { 0, true },
    8481             :   { 0, true },
    8482             :   { 0, true },
    8483             :   { 0, true },
    8484             :   { 0, true },
    8485             :   { 0, true },
    8486             :   { 0, true },
    8487             :   { 0, true },
    8488             :   { 0, true },
    8489             :   { 0, true },
    8490             :   { 0, true },
    8491             :   { 0, true },
    8492             :   { 0, true },
    8493             :   { 0, true },
    8494             :   { 0, true },
    8495             :   { 0, true },
    8496             :   { 0, true },
    8497             :   { 0, true },
    8498             :   { 0, true },
    8499             :   { 0, true },
    8500             :   { 0, true },
    8501             :   { 0, true },
    8502             :   { 0, true },
    8503             :   { 0, true },
    8504             :   { 0, true },
    8505             :   { 0, true },
    8506             :   { 0, true },
    8507             :   { 0, true },
    8508             :   { 0, true },
    8509             :   { 0, true },
    8510             :   { 0, true },
    8511             :   { 0, true },
    8512             :   { 0, true },
    8513             :   { 0, true },
    8514             :   { 0, true },
    8515             :   { 0, true },
    8516             :   { 0, true },
    8517             :   { 0, true },
    8518             :   { 0, true },
    8519             :   { 0, true },
    8520             :   { 0, true },
    8521             :   { 0, true },
    8522             :   { 0, true },
    8523             :   { 0, true },
    8524             :   { 0, true },
    8525             :   { 0, true },
    8526             :   { 0, true },
    8527             :   { 0, true },
    8528             :   { 0, true },
    8529             :   { 0, true },
    8530             :   { 0, true },
    8531             :   { 0, true },
    8532             :   { 0, true },
    8533             :   { 0, true },
    8534             :   { 0, true },
    8535             :   { 0, true },
    8536             :   { 0, true },
    8537             :   { 0, true },
    8538             :   { 0, true },
    8539             :   { 0, true },
    8540             :   { 0, true },
    8541             :   { 0, true },
    8542             :   { 0, true },
    8543             :   { 0, true },
    8544             :   { 0, true },
    8545             :   { 0, true },
    8546             :   { 0, true },
    8547             :   { 0, true },
    8548             :   { 0, true },
    8549             :   { 0, true },
    8550             :   { 0, true },
    8551             :   { 0, true },
    8552             :   { 0, true },
    8553             :   { 0, true },
    8554             :   { 0, true },
    8555             :   { 0, true },
    8556             :   { 0, true },
    8557             :   { 0, true },
    8558             :   { 0, true },
    8559             :   { 0, true },
    8560             :   { 0, true },
    8561             :   { 0, true },
    8562             :   { 0, true },
    8563             :   { 0, true },
    8564             :   { 0, true },
    8565             :   { 0, true },
    8566             :   { 0, true },
    8567             :   { 0, true },
    8568             :   { 0, true },
    8569             :   { 0, true },
    8570             :   { 0, true },
    8571             :   { 0, true },
    8572             :   { 0, true },
    8573             :   { 0, true },
    8574             :   { 0, true },
    8575             :   { 0, true },
    8576             :   { 0, true },
    8577             :   { 0, true },
    8578             :   { 0, true },
    8579             :   { 0, true },
    8580             :   { 0, true },
    8581             :   { 0, true },
    8582             :   { 0, true },
    8583             :   { 0, true },
    8584             :   { 0, true },
    8585             :   { 0, true },
    8586             :   { 0, true },
    8587             :   { 0, true },
    8588             :   { 0, true },
    8589             :   { 0, true },
    8590             :   { 0, true },
    8591             :   { 0, true },
    8592             :   { 0, true },
    8593             :   { 0, true },
    8594             :   { 0, true },
    8595             :   { 0, true },
    8596             :   { 0, true },
    8597             :   { 0, true },
    8598             :   { 0, true },
    8599             :   { 0, true },
    8600             :   { 0, true },
    8601             :   { 0, true },
    8602             :   { 0, true },
    8603             :   { 0, true },
    8604             :   { 0, true },
    8605             :   { 0, true },
    8606             :   { 0, true },
    8607             :   { 0, true },
    8608             :   { 0, true },
    8609             :   { 0, true },
    8610             :   { 0, true },
    8611             :   { 0, true },
    8612             :   { 0, true },
    8613             :   { 0, true },
    8614             :   { 0, true },
    8615             :   { 0, true },
    8616             :   { 0, true },
    8617             :   { 0, true },
    8618             :   { 0, true },
    8619             :   { 0, true },
    8620             :   { 0, true },
    8621             :   { 0, true },
    8622             :   { 0, true },
    8623             :   { 0, true },
    8624             :   { 0, true },
    8625             :   { 0, true },
    8626             :   { 0, true },
    8627             :   { 0, true },
    8628             :   { 0, true },
    8629             :   { 0, true },
    8630             :   { 0, true },
    8631             :   { 0, true },
    8632             :   { 0, true },
    8633             :   { 0, true },
    8634             :   { 0, true },
    8635             :   { 0, true },
    8636             :   { 0, true },
    8637             :   { 0, true },
    8638             :   { 0, true },
    8639             :   { 0, true },
    8640             :   { 0, true },
    8641             :   { 0, true },
    8642             :   { 0, true },
    8643             :   { 0, true },
    8644             :   { 0, true },
    8645             :   { 0, true },
    8646             :   { 0, true },
    8647             :   { 0, true },
    8648             :   { 0, true },
    8649             :   { 0, true },
    8650             :   { 0, true },
    8651             :   { 0, true },
    8652             :   { 0, true },
    8653             :   { 0, true },
    8654             :   { 0, true },
    8655             :   { 0, true },
    8656             :   { 0, true },
    8657             :   { 0, true },
    8658             :   { 0, true },
    8659             :   { 0, true },
    8660             :   { 0, true },
    8661             :   { 0, true },
    8662             :   { 0, true },
    8663             :   { 0, true },
    8664             :   { 0, true },
    8665             :   { 0, true },
    8666             :   { 0, true },
    8667             :   { 0, true },
    8668             :   { 0, true },
    8669             :   { 0, true },
    8670             :   { 0, true },
    8671             :   { 0, true },
    8672             :   { 0, true },
    8673             : };
    8674        1171 : unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
    8675             :   static const uint8_t RowMap[99] = {
    8676             :     0, 0, 0, 1, 2, 3, 0, 0, 0, 0, 4, 5, 6, 0, 0, 0, 0, 0, 1, 0, 0, 7, 8, 9, 0, 0, 1, 1, 0, 3, 3, 0, 2, 2, 0, 4, 4, 4, 0, 6, 6, 6, 0, 5, 5, 5, 0, 0, 7, 7, 7, 7, 0, 0, 9, 9, 9, 9, 0, 0, 8, 8, 8, 8, 0, 0, 0, 1, 1, 2, 10, 10, 10, 0, 0, 4, 4, 5, 4, 4, 5, 0, 11, 10, 11, 11, 10, 10, 0, 0, 7, 7, 8, 7, 7, 7, 7, 8, 8, 
    8677             :   };
    8678             :   static const uint8_t Rows[12][99] = {
    8679             :     { 1, 2, 3, 4, 5, 0, 7, 0, 0, 10, 11, 12, 0, 14, 15, 15, 0, 47, 0, 20, 21, 22, 23, 0, 25, 26, 27, 28, 0, 0, 0, 32, 33, 34, 35, 36, 37, 38, 0, 0, 0, 0, 43, 44, 45, 46, 0, 48, 49, 50, 51, 52, 53, 0, 0, 0, 0, 0, 0, 60, 61, 62, 63, 64, 65, 66, 0, 68, 0, 0, 71, 0, 73, 74, 0, 76, 0, 0, 79, 0, 0, 0, 83, 84, 0, 86, 0, 88, 89, 0, 91, 0, 0, 94, 0, 96, 0, 0, 0, },
    8680             :     { 26, 0, 4, 5, 6, 0, 27, 0, 0, 0, 0, 0, 0, 28, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 33, 34, 0, 0, 0, 29, 30, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 68, 0, 70, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8681             :     { 32, 0, 5, 6, 0, 0, 33, 0, 0, 0, 0, 0, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 30, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8682             :     { 29, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8683             :     { 35, 36, 36, 44, 40, 0, 37, 0, 0, 11, 12, 13, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 43, 45, 46, 0, 0, 0, 39, 41, 42, 43, 44, 45, 46, 0, 0, 0, 0, 39, 40, 41, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 79, 0, 81, 0, 0, 79, 0, 80, 76, 0, 78, 0, 0, 81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8684             :     { 43, 44, 44, 40, 0, 0, 45, 0, 0, 12, 13, 0, 0, 46, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 41, 42, 0, 0, 0, 0, 0, 0, 39, 40, 41, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8685             :     { 39, 40, 0, 0, 0, 0, 41, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8686             :     { 48, 49, 49, 61, 55, 0, 50, 0, 0, 52, 64, 58, 0, 51, 0, 0, 0, 0, 0, 52, 22, 23, 24, 0, 53, 60, 62, 63, 0, 0, 0, 54, 56, 57, 60, 61, 62, 63, 0, 0, 0, 0, 54, 55, 56, 57, 0, 60, 61, 62, 63, 64, 65, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 58, 59, 94, 0, 98, 0, 0, 94, 0, 95, 96, 0, 99, 0, 0, 98, 0, 0, 0, 94, 96, 0, 95, 0, 97, 91, 0, 93, 0, 0, 98, 0, 99, 0, 0, 0, },
    8687             :     { 60, 61, 61, 55, 0, 0, 62, 0, 0, 64, 58, 0, 0, 63, 0, 0, 0, 0, 0, 64, 23, 24, 0, 0, 65, 54, 56, 57, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 58, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8688             :     { 54, 55, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 57, 0, 0, 0, 0, 0, 58, 0, 0, 0, 0, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8689             :     { 1, 2, 2, 36, 44, 40, 7, 0, 0, 20, 52, 64, 58, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 35, 37, 38, 39, 41, 42, 43, 45, 46, 48, 49, 50, 51, 54, 55, 56, 57, 60, 61, 62, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 71, 73, 79, 80, 81, 83, 85, 86, 84, 88, 96, 97, 99, 94, 95, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8690             :     { 1, 0, 2, 49, 61, 55, 7, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 48, 50, 51, 54, 56, 57, 60, 62, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 83, 86, 94, 95, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    8691             :   };
    8692             : 
    8693        1171 :   --IdxA; assert(IdxA < 99);
    8694        1171 :   --IdxB; assert(IdxB < 99);
    8695        1171 :   return Rows[RowMap[IdxA]][IdxB];
    8696             : }
    8697             : 
    8698             :   struct MaskRolOp {
    8699             :     LaneBitmask Mask;
    8700             :     uint8_t  RotateLeft;
    8701             :   };
    8702             :   static const MaskRolOp LaneMaskComposeSequences[] = {
    8703             :     { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    8704             :     { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    8705             :     { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    8706             :     { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    8707             :     { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    8708             :     { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    8709             :     { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    8710             :     { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    8711             :     { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
    8712             :     { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
    8713             :     { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
    8714             :     { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
    8715             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
    8716             :     { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000040), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 27
    8717             :     { LaneBitmask(0x00000001), 16 }, { LaneBitmask(0x00000040), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 30
    8718             :     { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 33
    8719             :     { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 35
    8720             :     { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 37
    8721             :     { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 39
    8722             :     { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 41
    8723             :     { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 },   // Sequence 43
    8724             :     { LaneBitmask(0xFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 },   // Sequence 45
    8725             :     { LaneBitmask(0xFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 },   // Sequence 47
    8726             :     { LaneBitmask(0x00000001),  7 }, { LaneBitmask(0x00000080),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 49
    8727             :     { LaneBitmask(0x00000001),  7 }, { LaneBitmask(0x00000080),  2 }, { LaneBitmask(0x00000200), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 52
    8728             :     { LaneBitmask(0x00000001),  9 }, { LaneBitmask(0x00000080),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 56
    8729             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 59
    8730             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000380),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 62
    8731             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000280),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 65
    8732             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 68
    8733             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400),  2 }, { LaneBitmask(0x00001000), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 71
    8734             :     { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000400),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 75
    8735             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 78
    8736             :     { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080),  5 }, { LaneBitmask(0x00000200),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 81
    8737             :     { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000080),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 85
    8738             :     { LaneBitmask(0x00000010), 31 }, { LaneBitmask(0x00000020),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 88
    8739             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 91
    8740             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 94
    8741             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask(0x00000100),  8 }, { LaneBitmask(0x00000200),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 97
    8742             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask(0x00000200),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 102
    8743             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask(0x00000800),  5 }, { LaneBitmask(0x00001000),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 106
    8744             :     { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask(0x00001000),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 111
    8745             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask(0x0000C000),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 115
    8746             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask(0x0000C000),  4 }, { LaneBitmask(0x000C0000), 30 }, { LaneBitmask::getNone(), 0 },   // Sequence 119
    8747             :     { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000040), 13 }, { LaneBitmask(0x0000C000),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 124
    8748             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000080), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 128
    8749             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000080), 11 }, { LaneBitmask(0x00000200),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 131
    8750             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000400),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 135
    8751             :     { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000400),  8 }, { LaneBitmask(0x00001000),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 138
    8752             :     { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000080),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 142
    8753             :     { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000400),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 145
    8754             :   };
    8755             :   static const MaskRolOp *const CompositeSequences[] = {
    8756             :     &LaneMaskComposeSequences[0], // to bsub
    8757             :     &LaneMaskComposeSequences[0], // to dsub
    8758             :     &LaneMaskComposeSequences[0], // to dsub0
    8759             :     &LaneMaskComposeSequences[2], // to dsub1
    8760             :     &LaneMaskComposeSequences[4], // to dsub2
    8761             :     &LaneMaskComposeSequences[6], // to dsub3
    8762             :     &LaneMaskComposeSequences[0], // to hsub
    8763             :     &LaneMaskComposeSequences[8], // to qhisub
    8764             :     &LaneMaskComposeSequences[10], // to qsub
    8765             :     &LaneMaskComposeSequences[0], // to qsub0
    8766             :     &LaneMaskComposeSequences[12], // to qsub1
    8767             :     &LaneMaskComposeSequences[14], // to qsub2
    8768             :     &LaneMaskComposeSequences[16], // to qsub3
    8769             :     &LaneMaskComposeSequences[0], // to ssub
    8770             :     &LaneMaskComposeSequences[18], // to sub_32
    8771             :     &LaneMaskComposeSequences[20], // to sube32
    8772             :     &LaneMaskComposeSequences[0], // to sube64
    8773             :     &LaneMaskComposeSequences[22], // to subo32
    8774             :     &LaneMaskComposeSequences[12], // to subo64
    8775             :     &LaneMaskComposeSequences[0], // to zsub
    8776             :     &LaneMaskComposeSequences[0], // to zsub0
    8777             :     &LaneMaskComposeSequences[24], // to zsub1
    8778             :     &LaneMaskComposeSequences[27], // to zsub2
    8779             :     &LaneMaskComposeSequences[30], // to zsub3
    8780             :     &LaneMaskComposeSequences[33], // to zsub_hi
    8781             :     &LaneMaskComposeSequences[2], // to dsub1_then_bsub
    8782             :     &LaneMaskComposeSequences[2], // to dsub1_then_hsub
    8783             :     &LaneMaskComposeSequences[2], // to dsub1_then_ssub
    8784             :     &LaneMaskComposeSequences[6], // to dsub3_then_bsub
    8785             :     &LaneMaskComposeSequences[6], // to dsub3_then_hsub
    8786             :     &LaneMaskComposeSequences[6], // to dsub3_then_ssub
    8787             :     &LaneMaskComposeSequences[4], // to dsub2_then_bsub
    8788             :     &LaneMaskComposeSequences[4], // to dsub2_then_hsub
    8789             :     &LaneMaskComposeSequences[4], // to dsub2_then_ssub
    8790             :     &LaneMaskComposeSequences[12], // to qsub1_then_bsub
    8791             :     &LaneMaskComposeSequences[12], // to qsub1_then_dsub
    8792             :     &LaneMaskComposeSequences[12], // to qsub1_then_hsub
    8793             :     &LaneMaskComposeSequences[12], // to qsub1_then_ssub
    8794             :     &LaneMaskComposeSequences[16], // to qsub3_then_bsub
    8795             :     &LaneMaskComposeSequences[16], // to qsub3_then_dsub
    8796             :     &LaneMaskComposeSequences[16], // to qsub3_then_hsub
    8797             :     &LaneMaskComposeSequences[16], // to qsub3_then_ssub
    8798             :     &LaneMaskComposeSequences[14], // to qsub2_then_bsub
    8799             :     &LaneMaskComposeSequences[14], // to qsub2_then_dsub
    8800             :     &LaneMaskComposeSequences[14], // to qsub2_then_hsub
    8801             :     &LaneMaskComposeSequences[14], // to qsub2_then_ssub
    8802             :     &LaneMaskComposeSequences[35], // to subo64_then_sub_32
    8803             :     &LaneMaskComposeSequences[37], // to zsub1_then_bsub
    8804             :     &LaneMaskComposeSequences[37], // to zsub1_then_dsub
    8805             :     &LaneMaskComposeSequences[37], // to zsub1_then_hsub
    8806             :     &LaneMaskComposeSequences[37], // to zsub1_then_ssub
    8807             :     &LaneMaskComposeSequences[37], // to zsub1_then_zsub
    8808             :     &LaneMaskComposeSequences[39], // to zsub1_then_zsub_hi
    8809             :     &LaneMaskComposeSequences[41], // to zsub3_then_bsub
    8810             :     &LaneMaskComposeSequences[41], // to zsub3_then_dsub
    8811             :     &LaneMaskComposeSequences[41], // to zsub3_then_hsub
    8812             :     &LaneMaskComposeSequences[41], // to zsub3_then_ssub
    8813             :     &LaneMaskComposeSequences[41], // to zsub3_then_zsub
    8814             :     &LaneMaskComposeSequences[43], // to zsub3_then_zsub_hi
    8815             :     &LaneMaskComposeSequences[45], // to zsub2_then_bsub
    8816             :     &LaneMaskComposeSequences[45], // to zsub2_then_dsub
    8817             :     &LaneMaskComposeSequences[45], // to zsub2_then_hsub
    8818             :     &LaneMaskComposeSequences[45], // to zsub2_then_ssub
    8819             :     &LaneMaskComposeSequences[45], // to zsub2_then_zsub
    8820             :     &LaneMaskComposeSequences[47], // to zsub2_then_zsub_hi
    8821             :     &LaneMaskComposeSequences[0], // to dsub0_dsub1
    8822             :     &LaneMaskComposeSequences[0], // to dsub0_dsub1_dsub2
    8823             :     &LaneMaskComposeSequences[49], // to dsub1_dsub2
    8824             :     &LaneMaskComposeSequences[52], // to dsub1_dsub2_dsub3
    8825             :     &LaneMaskComposeSequences[56], // to dsub2_dsub3
    8826             :     &LaneMaskComposeSequences[59], // to dsub_qsub1_then_dsub
    8827             :     &LaneMaskComposeSequences[62], // to dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8828             :     &LaneMaskComposeSequences[65], // to dsub_qsub1_then_dsub_qsub2_then_dsub
    8829             :     &LaneMaskComposeSequences[0], // to qsub0_qsub1
    8830             :     &LaneMaskComposeSequences[0], // to qsub0_qsub1_qsub2
    8831             :     &LaneMaskComposeSequences[68], // to qsub1_qsub2
    8832             :     &LaneMaskComposeSequences[71], // to qsub1_qsub2_qsub3
    8833             :     &LaneMaskComposeSequences[75], // to qsub2_qsub3
    8834             :     &LaneMaskComposeSequences[78], // to qsub1_then_dsub_qsub2_then_dsub
    8835             :     &LaneMaskComposeSequences[81], // to qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8836             :     &LaneMaskComposeSequences[85], // to qsub2_then_dsub_qsub3_then_dsub
    8837             :     &LaneMaskComposeSequences[88], // to sub_32_subo64_then_sub_32
    8838             :     &LaneMaskComposeSequences[91], // to dsub_zsub1_then_dsub
    8839             :     &LaneMaskComposeSequences[94], // to zsub_zsub1_then_zsub
    8840             :     &LaneMaskComposeSequences[97], // to dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8841             :     &LaneMaskComposeSequences[102], // to dsub_zsub1_then_dsub_zsub2_then_dsub
    8842             :     &LaneMaskComposeSequences[106], // to zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8843             :     &LaneMaskComposeSequences[111], // to zsub_zsub1_then_zsub_zsub2_then_zsub
    8844             :     &LaneMaskComposeSequences[0], // to zsub0_zsub1
    8845             :     &LaneMaskComposeSequences[0], // to zsub0_zsub1_zsub2
    8846             :     &LaneMaskComposeSequences[115], // to zsub1_zsub2
    8847             :     &LaneMaskComposeSequences[119], // to zsub1_zsub2_zsub3
    8848             :     &LaneMaskComposeSequences[124], // to zsub2_zsub3
    8849             :     &LaneMaskComposeSequences[128], // to zsub1_then_dsub_zsub2_then_dsub
    8850             :     &LaneMaskComposeSequences[131], // to zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8851             :     &LaneMaskComposeSequences[135], // to zsub1_then_zsub_zsub2_then_zsub
    8852             :     &LaneMaskComposeSequences[138], // to zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8853             :     &LaneMaskComposeSequences[142], // to zsub2_then_dsub_zsub3_then_dsub
    8854             :     &LaneMaskComposeSequences[145] // to zsub2_then_zsub_zsub3_then_zsub
    8855             :   };
    8856             : 
    8857           0 : LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
    8858           0 :   --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
    8859             :   LaneBitmask Result;
    8860           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    8861           0 :     LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    8862           0 :     if (unsigned S = Ops->RotateLeft)
    8863           0 :       Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    8864             :     else
    8865             :       Result |= LaneBitmask(M);
    8866             :   }
    8867           0 :   return Result;
    8868             : }
    8869             : 
    8870           0 : LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
    8871           0 :   LaneMask &= getSubRegIndexLaneMask(IdxA);
    8872           0 :   --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
    8873             :   LaneBitmask Result;
    8874           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    8875             :     LaneBitmask::Type M = LaneMask.getAsInteger();
    8876           0 :     if (unsigned S = Ops->RotateLeft)
    8877           0 :       Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    8878             :     else
    8879             :       Result |= LaneBitmask(M);
    8880             :   }
    8881           0 :   return Result;
    8882             : }
    8883             : 
    8884       33621 : const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
    8885             :   static const uint8_t Table[100][99] = {
    8886             :     {   // FPR8
    8887             :       0,        // bsub
    8888             :       0,        // dsub
    8889             :       0,        // dsub0
    8890             :       0,        // dsub1
    8891             :       0,        // dsub2
    8892             :       0,        // dsub3
    8893             :       0,        // hsub
    8894             :       0,        // qhisub
    8895             :       0,        // qsub
    8896             :       0,        // qsub0
    8897             :       0,        // qsub1
    8898             :       0,        // qsub2
    8899             :       0,        // qsub3
    8900             :       0,        // ssub
    8901             :       0,        // sub_32
    8902             :       0,        // sube32
    8903             :       0,        // sube64
    8904             :       0,        // subo32
    8905             :       0,        // subo64
    8906             :       0,        // zsub
    8907             :       0,        // zsub0
    8908             :       0,        // zsub1
    8909             :       0,        // zsub2
    8910             :       0,        // zsub3
    8911             :       0,        // zsub_hi
    8912             :       0,        // dsub1_then_bsub
    8913             :       0,        // dsub1_then_hsub
    8914             :       0,        // dsub1_then_ssub
    8915             :       0,        // dsub3_then_bsub
    8916             :       0,        // dsub3_then_hsub
    8917             :       0,        // dsub3_then_ssub
    8918             :       0,        // dsub2_then_bsub
    8919             :       0,        // dsub2_then_hsub
    8920             :       0,        // dsub2_then_ssub
    8921             :       0,        // qsub1_then_bsub
    8922             :       0,        // qsub1_then_dsub
    8923             :       0,        // qsub1_then_hsub
    8924             :       0,        // qsub1_then_ssub
    8925             :       0,        // qsub3_then_bsub
    8926             :       0,        // qsub3_then_dsub
    8927             :       0,        // qsub3_then_hsub
    8928             :       0,        // qsub3_then_ssub
    8929             :       0,        // qsub2_then_bsub
    8930             :       0,        // qsub2_then_dsub
    8931             :       0,        // qsub2_then_hsub
    8932             :       0,        // qsub2_then_ssub
    8933             :       0,        // subo64_then_sub_32
    8934             :       0,        // zsub1_then_bsub
    8935             :       0,        // zsub1_then_dsub
    8936             :       0,        // zsub1_then_hsub
    8937             :       0,        // zsub1_then_ssub
    8938             :       0,        // zsub1_then_zsub
    8939             :       0,        // zsub1_then_zsub_hi
    8940             :       0,        // zsub3_then_bsub
    8941             :       0,        // zsub3_then_dsub
    8942             :       0,        // zsub3_then_hsub
    8943             :       0,        // zsub3_then_ssub
    8944             :       0,        // zsub3_then_zsub
    8945             :       0,        // zsub3_then_zsub_hi
    8946             :       0,        // zsub2_then_bsub
    8947             :       0,        // zsub2_then_dsub
    8948             :       0,        // zsub2_then_hsub
    8949             :       0,        // zsub2_then_ssub
    8950             :       0,        // zsub2_then_zsub
    8951             :       0,        // zsub2_then_zsub_hi
    8952             :       0,        // dsub0_dsub1
    8953             :       0,        // dsub0_dsub1_dsub2
    8954             :       0,        // dsub1_dsub2
    8955             :       0,        // dsub1_dsub2_dsub3
    8956             :       0,        // dsub2_dsub3
    8957             :       0,        // dsub_qsub1_then_dsub
    8958             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8959             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    8960             :       0,        // qsub0_qsub1
    8961             :       0,        // qsub0_qsub1_qsub2
    8962             :       0,        // qsub1_qsub2
    8963             :       0,        // qsub1_qsub2_qsub3
    8964             :       0,        // qsub2_qsub3
    8965             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    8966             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    8967             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    8968             :       0,        // sub_32_subo64_then_sub_32
    8969             :       0,        // dsub_zsub1_then_dsub
    8970             :       0,        // zsub_zsub1_then_zsub
    8971             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8972             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    8973             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8974             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    8975             :       0,        // zsub0_zsub1
    8976             :       0,        // zsub0_zsub1_zsub2
    8977             :       0,        // zsub1_zsub2
    8978             :       0,        // zsub1_zsub2_zsub3
    8979             :       0,        // zsub2_zsub3
    8980             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    8981             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    8982             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    8983             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    8984             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    8985             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    8986             :     },
    8987             :     {   // FPR16
    8988             :       2,        // bsub -> FPR16
    8989             :       0,        // dsub
    8990             :       0,        // dsub0
    8991             :       0,        // dsub1
    8992             :       0,        // dsub2
    8993             :       0,        // dsub3
    8994             :       0,        // hsub
    8995             :       0,        // qhisub
    8996             :       0,        // qsub
    8997             :       0,        // qsub0
    8998             :       0,        // qsub1
    8999             :       0,        // qsub2
    9000             :       0,        // qsub3
    9001             :       0,        // ssub
    9002             :       0,        // sub_32
    9003             :       0,        // sube32
    9004             :       0,        // sube64
    9005             :       0,        // subo32
    9006             :       0,        // subo64
    9007             :       0,        // zsub
    9008             :       0,        // zsub0
    9009             :       0,        // zsub1
    9010             :       0,        // zsub2
    9011             :       0,        // zsub3
    9012             :       0,        // zsub_hi
    9013             :       0,        // dsub1_then_bsub
    9014             :       0,        // dsub1_then_hsub
    9015             :       0,        // dsub1_then_ssub
    9016             :       0,        // dsub3_then_bsub
    9017             :       0,        // dsub3_then_hsub
    9018             :       0,        // dsub3_then_ssub
    9019             :       0,        // dsub2_then_bsub
    9020             :       0,        // dsub2_then_hsub
    9021             :       0,        // dsub2_then_ssub
    9022             :       0,        // qsub1_then_bsub
    9023             :       0,        // qsub1_then_dsub
    9024             :       0,        // qsub1_then_hsub
    9025             :       0,        // qsub1_then_ssub
    9026             :       0,        // qsub3_then_bsub
    9027             :       0,        // qsub3_then_dsub
    9028             :       0,        // qsub3_then_hsub
    9029             :       0,        // qsub3_then_ssub
    9030             :       0,        // qsub2_then_bsub
    9031             :       0,        // qsub2_then_dsub
    9032             :       0,        // qsub2_then_hsub
    9033             :       0,        // qsub2_then_ssub
    9034             :       0,        // subo64_then_sub_32
    9035             :       0,        // zsub1_then_bsub
    9036             :       0,        // zsub1_then_dsub
    9037             :       0,        // zsub1_then_hsub
    9038             :       0,        // zsub1_then_ssub
    9039             :       0,        // zsub1_then_zsub
    9040             :       0,        // zsub1_then_zsub_hi
    9041             :       0,        // zsub3_then_bsub
    9042             :       0,        // zsub3_then_dsub
    9043             :       0,        // zsub3_then_hsub
    9044             :       0,        // zsub3_then_ssub
    9045             :       0,        // zsub3_then_zsub
    9046             :       0,        // zsub3_then_zsub_hi
    9047             :       0,        // zsub2_then_bsub
    9048             :       0,        // zsub2_then_dsub
    9049             :       0,        // zsub2_then_hsub
    9050             :       0,        // zsub2_then_ssub
    9051             :       0,        // zsub2_then_zsub
    9052             :       0,        // zsub2_then_zsub_hi
    9053             :       0,        // dsub0_dsub1
    9054             :       0,        // dsub0_dsub1_dsub2
    9055             :       0,        // dsub1_dsub2
    9056             :       0,        // dsub1_dsub2_dsub3
    9057             :       0,        // dsub2_dsub3
    9058             :       0,        // dsub_qsub1_then_dsub
    9059             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9060             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9061             :       0,        // qsub0_qsub1
    9062             :       0,        // qsub0_qsub1_qsub2
    9063             :       0,        // qsub1_qsub2
    9064             :       0,        // qsub1_qsub2_qsub3
    9065             :       0,        // qsub2_qsub3
    9066             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9067             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9068             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9069             :       0,        // sub_32_subo64_then_sub_32
    9070             :       0,        // dsub_zsub1_then_dsub
    9071             :       0,        // zsub_zsub1_then_zsub
    9072             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9073             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9074             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9075             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9076             :       0,        // zsub0_zsub1
    9077             :       0,        // zsub0_zsub1_zsub2
    9078             :       0,        // zsub1_zsub2
    9079             :       0,        // zsub1_zsub2_zsub3
    9080             :       0,        // zsub2_zsub3
    9081             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9082             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9083             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9084             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9085             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9086             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9087             :     },
    9088             :     {   // PPR
    9089             :       0,        // bsub
    9090             :       0,        // dsub
    9091             :       0,        // dsub0
    9092             :       0,        // dsub1
    9093             :       0,        // dsub2
    9094             :       0,        // dsub3
    9095             :       0,        // hsub
    9096             :       0,        // qhisub
    9097             :       0,        // qsub
    9098             :       0,        // qsub0
    9099             :       0,        // qsub1
    9100             :       0,        // qsub2
    9101             :       0,        // qsub3
    9102             :       0,        // ssub
    9103             :       0,        // sub_32
    9104             :       0,        // sube32
    9105             :       0,        // sube64
    9106             :       0,        // subo32
    9107             :       0,        // subo64
    9108             :       0,        // zsub
    9109             :       0,        // zsub0
    9110             :       0,        // zsub1
    9111             :       0,        // zsub2
    9112             :       0,        // zsub3
    9113             :       0,        // zsub_hi
    9114             :       0,        // dsub1_then_bsub
    9115             :       0,        // dsub1_then_hsub
    9116             :       0,        // dsub1_then_ssub
    9117             :       0,        // dsub3_then_bsub
    9118             :       0,        // dsub3_then_hsub
    9119             :       0,        // dsub3_then_ssub
    9120             :       0,        // dsub2_then_bsub
    9121             :       0,        // dsub2_then_hsub
    9122             :       0,        // dsub2_then_ssub
    9123             :       0,        // qsub1_then_bsub
    9124             :       0,        // qsub1_then_dsub
    9125             :       0,        // qsub1_then_hsub
    9126             :       0,        // qsub1_then_ssub
    9127             :       0,        // qsub3_then_bsub
    9128             :       0,        // qsub3_then_dsub
    9129             :       0,        // qsub3_then_hsub
    9130             :       0,        // qsub3_then_ssub
    9131             :       0,        // qsub2_then_bsub
    9132             :       0,        // qsub2_then_dsub
    9133             :       0,        // qsub2_then_hsub
    9134             :       0,        // qsub2_then_ssub
    9135             :       0,        // subo64_then_sub_32
    9136             :       0,        // zsub1_then_bsub
    9137             :       0,        // zsub1_then_dsub
    9138             :       0,        // zsub1_then_hsub
    9139             :       0,        // zsub1_then_ssub
    9140             :       0,        // zsub1_then_zsub
    9141             :       0,        // zsub1_then_zsub_hi
    9142             :       0,        // zsub3_then_bsub
    9143             :       0,        // zsub3_then_dsub
    9144             :       0,        // zsub3_then_hsub
    9145             :       0,        // zsub3_then_ssub
    9146             :       0,        // zsub3_then_zsub
    9147             :       0,        // zsub3_then_zsub_hi
    9148             :       0,        // zsub2_then_bsub
    9149             :       0,        // zsub2_then_dsub
    9150             :       0,        // zsub2_then_hsub
    9151             :       0,        // zsub2_then_ssub
    9152             :       0,        // zsub2_then_zsub
    9153             :       0,        // zsub2_then_zsub_hi
    9154             :       0,        // dsub0_dsub1
    9155             :       0,        // dsub0_dsub1_dsub2
    9156             :       0,        // dsub1_dsub2
    9157             :       0,        // dsub1_dsub2_dsub3
    9158             :       0,        // dsub2_dsub3
    9159             :       0,        // dsub_qsub1_then_dsub
    9160             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9161             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9162             :       0,        // qsub0_qsub1
    9163             :       0,        // qsub0_qsub1_qsub2
    9164             :       0,        // qsub1_qsub2
    9165             :       0,        // qsub1_qsub2_qsub3
    9166             :       0,        // qsub2_qsub3
    9167             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9168             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9169             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9170             :       0,        // sub_32_subo64_then_sub_32
    9171             :       0,        // dsub_zsub1_then_dsub
    9172             :       0,        // zsub_zsub1_then_zsub
    9173             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9174             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9175             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9176             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9177             :       0,        // zsub0_zsub1
    9178             :       0,        // zsub0_zsub1_zsub2
    9179             :       0,        // zsub1_zsub2
    9180             :       0,        // zsub1_zsub2_zsub3
    9181             :       0,        // zsub2_zsub3
    9182             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9183             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9184             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9185             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9186             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9187             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9188             :     },
    9189             :     {   // PPR_3b
    9190             :       0,        // bsub
    9191             :       0,        // dsub
    9192             :       0,        // dsub0
    9193             :       0,        // dsub1
    9194             :       0,        // dsub2
    9195             :       0,        // dsub3
    9196             :       0,        // hsub
    9197             :       0,        // qhisub
    9198             :       0,        // qsub
    9199             :       0,        // qsub0
    9200             :       0,        // qsub1
    9201             :       0,        // qsub2
    9202             :       0,        // qsub3
    9203             :       0,        // ssub
    9204             :       0,        // sub_32
    9205             :       0,        // sube32
    9206             :       0,        // sube64
    9207             :       0,        // subo32
    9208             :       0,        // subo64
    9209             :       0,        // zsub
    9210             :       0,        // zsub0
    9211             :       0,        // zsub1
    9212             :       0,        // zsub2
    9213             :       0,        // zsub3
    9214             :       0,        // zsub_hi
    9215             :       0,        // dsub1_then_bsub
    9216             :       0,        // dsub1_then_hsub
    9217             :       0,        // dsub1_then_ssub
    9218             :       0,        // dsub3_then_bsub
    9219             :       0,        // dsub3_then_hsub
    9220             :       0,        // dsub3_then_ssub
    9221             :       0,        // dsub2_then_bsub
    9222             :       0,        // dsub2_then_hsub
    9223             :       0,        // dsub2_then_ssub
    9224             :       0,        // qsub1_then_bsub
    9225             :       0,        // qsub1_then_dsub
    9226             :       0,        // qsub1_then_hsub
    9227             :       0,        // qsub1_then_ssub
    9228             :       0,        // qsub3_then_bsub
    9229             :       0,        // qsub3_then_dsub
    9230             :       0,        // qsub3_then_hsub
    9231             :       0,        // qsub3_then_ssub
    9232             :       0,        // qsub2_then_bsub
    9233             :       0,        // qsub2_then_dsub
    9234             :       0,        // qsub2_then_hsub
    9235             :       0,        // qsub2_then_ssub
    9236             :       0,        // subo64_then_sub_32
    9237             :       0,        // zsub1_then_bsub
    9238             :       0,        // zsub1_then_dsub
    9239             :       0,        // zsub1_then_hsub
    9240             :       0,        // zsub1_then_ssub
    9241             :       0,        // zsub1_then_zsub
    9242             :       0,        // zsub1_then_zsub_hi
    9243             :       0,        // zsub3_then_bsub
    9244             :       0,        // zsub3_then_dsub
    9245             :       0,        // zsub3_then_hsub
    9246             :       0,        // zsub3_then_ssub
    9247             :       0,        // zsub3_then_zsub
    9248             :       0,        // zsub3_then_zsub_hi
    9249             :       0,        // zsub2_then_bsub
    9250             :       0,        // zsub2_then_dsub
    9251             :       0,        // zsub2_then_hsub
    9252             :       0,        // zsub2_then_ssub
    9253             :       0,        // zsub2_then_zsub
    9254             :       0,        // zsub2_then_zsub_hi
    9255             :       0,        // dsub0_dsub1
    9256             :       0,        // dsub0_dsub1_dsub2
    9257             :       0,        // dsub1_dsub2
    9258             :       0,        // dsub1_dsub2_dsub3
    9259             :       0,        // dsub2_dsub3
    9260             :       0,        // dsub_qsub1_then_dsub
    9261             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9262             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9263             :       0,        // qsub0_qsub1
    9264             :       0,        // qsub0_qsub1_qsub2
    9265             :       0,        // qsub1_qsub2
    9266             :       0,        // qsub1_qsub2_qsub3
    9267             :       0,        // qsub2_qsub3
    9268             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9269             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9270             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9271             :       0,        // sub_32_subo64_then_sub_32
    9272             :       0,        // dsub_zsub1_then_dsub
    9273             :       0,        // zsub_zsub1_then_zsub
    9274             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9275             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9276             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9277             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9278             :       0,        // zsub0_zsub1
    9279             :       0,        // zsub0_zsub1_zsub2
    9280             :       0,        // zsub1_zsub2
    9281             :       0,        // zsub1_zsub2_zsub3
    9282             :       0,        // zsub2_zsub3
    9283             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9284             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9285             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9286             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9287             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9288             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9289             :     },
    9290             :     {   // GPR32all
    9291             :       0,        // bsub
    9292             :       0,        // dsub
    9293             :       0,        // dsub0
    9294             :       0,        // dsub1
    9295             :       0,        // dsub2
    9296             :       0,        // dsub3
    9297             :       0,        // hsub
    9298             :       0,        // qhisub
    9299             :       0,        // qsub
    9300             :       0,        // qsub0
    9301             :       0,        // qsub1
    9302             :       0,        // qsub2
    9303             :       0,        // qsub3
    9304             :       0,        // ssub
    9305             :       0,        // sub_32
    9306             :       0,        // sube32
    9307             :       0,        // sube64
    9308             :       0,        // subo32
    9309             :       0,        // subo64
    9310             :       0,        // zsub
    9311             :       0,        // zsub0
    9312             :       0,        // zsub1
    9313             :       0,        // zsub2
    9314             :       0,        // zsub3
    9315             :       0,        // zsub_hi
    9316             :       0,        // dsub1_then_bsub
    9317             :       0,        // dsub1_then_hsub
    9318             :       0,        // dsub1_then_ssub
    9319             :       0,        // dsub3_then_bsub
    9320             :       0,        // dsub3_then_hsub
    9321             :       0,        // dsub3_then_ssub
    9322             :       0,        // dsub2_then_bsub
    9323             :       0,        // dsub2_then_hsub
    9324             :       0,        // dsub2_then_ssub
    9325             :       0,        // qsub1_then_bsub
    9326             :       0,        // qsub1_then_dsub
    9327             :       0,        // qsub1_then_hsub
    9328             :       0,        // qsub1_then_ssub
    9329             :       0,        // qsub3_then_bsub
    9330             :       0,        // qsub3_then_dsub
    9331             :       0,        // qsub3_then_hsub
    9332             :       0,        // qsub3_then_ssub
    9333             :       0,        // qsub2_then_bsub
    9334             :       0,        // qsub2_then_dsub
    9335             :       0,        // qsub2_then_hsub
    9336             :       0,        // qsub2_then_ssub
    9337             :       0,        // subo64_then_sub_32
    9338             :       0,        // zsub1_then_bsub
    9339             :       0,        // zsub1_then_dsub
    9340             :       0,        // zsub1_then_hsub
    9341             :       0,        // zsub1_then_ssub
    9342             :       0,        // zsub1_then_zsub
    9343             :       0,        // zsub1_then_zsub_hi
    9344             :       0,        // zsub3_then_bsub
    9345             :       0,        // zsub3_then_dsub
    9346             :       0,        // zsub3_then_hsub
    9347             :       0,        // zsub3_then_ssub
    9348             :       0,        // zsub3_then_zsub
    9349             :       0,        // zsub3_then_zsub_hi
    9350             :       0,        // zsub2_then_bsub
    9351             :       0,        // zsub2_then_dsub
    9352             :       0,        // zsub2_then_hsub
    9353             :       0,        // zsub2_then_ssub
    9354             :       0,        // zsub2_then_zsub
    9355             :       0,        // zsub2_then_zsub_hi
    9356             :       0,        // dsub0_dsub1
    9357             :       0,        // dsub0_dsub1_dsub2
    9358             :       0,        // dsub1_dsub2
    9359             :       0,        // dsub1_dsub2_dsub3
    9360             :       0,        // dsub2_dsub3
    9361             :       0,        // dsub_qsub1_then_dsub
    9362             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9363             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9364             :       0,        // qsub0_qsub1
    9365             :       0,        // qsub0_qsub1_qsub2
    9366             :       0,        // qsub1_qsub2
    9367             :       0,        // qsub1_qsub2_qsub3
    9368             :       0,        // qsub2_qsub3
    9369             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9370             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9371             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9372             :       0,        // sub_32_subo64_then_sub_32
    9373             :       0,        // dsub_zsub1_then_dsub
    9374             :       0,        // zsub_zsub1_then_zsub
    9375             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9376             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9377             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9378             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9379             :       0,        // zsub0_zsub1
    9380             :       0,        // zsub0_zsub1_zsub2
    9381             :       0,        // zsub1_zsub2
    9382             :       0,        // zsub1_zsub2_zsub3
    9383             :       0,        // zsub2_zsub3
    9384             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9385             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9386             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9387             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9388             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9389             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9390             :     },
    9391             :     {   // FPR32
    9392             :       6,        // bsub -> FPR32
    9393             :       0,        // dsub
    9394             :       0,        // dsub0
    9395             :       0,        // dsub1
    9396             :       0,        // dsub2
    9397             :       0,        // dsub3
    9398             :       6,        // hsub -> FPR32
    9399             :       0,        // qhisub
    9400             :       0,        // qsub
    9401             :       0,        // qsub0
    9402             :       0,        // qsub1
    9403             :       0,        // qsub2
    9404             :       0,        // qsub3
    9405             :       0,        // ssub
    9406             :       0,        // sub_32
    9407             :       0,        // sube32
    9408             :       0,        // sube64
    9409             :       0,        // subo32
    9410             :       0,        // subo64
    9411             :       0,        // zsub
    9412             :       0,        // zsub0
    9413             :       0,        // zsub1
    9414             :       0,        // zsub2
    9415             :       0,        // zsub3
    9416             :       0,        // zsub_hi
    9417             :       0,        // dsub1_then_bsub
    9418             :       0,        // dsub1_then_hsub
    9419             :       0,        // dsub1_then_ssub
    9420             :       0,        // dsub3_then_bsub
    9421             :       0,        // dsub3_then_hsub
    9422             :       0,        // dsub3_then_ssub
    9423             :       0,        // dsub2_then_bsub
    9424             :       0,        // dsub2_then_hsub
    9425             :       0,        // dsub2_then_ssub
    9426             :       0,        // qsub1_then_bsub
    9427             :       0,        // qsub1_then_dsub
    9428             :       0,        // qsub1_then_hsub
    9429             :       0,        // qsub1_then_ssub
    9430             :       0,        // qsub3_then_bsub
    9431             :       0,        // qsub3_then_dsub
    9432             :       0,        // qsub3_then_hsub
    9433             :       0,        // qsub3_then_ssub
    9434             :       0,        // qsub2_then_bsub
    9435             :       0,        // qsub2_then_dsub
    9436             :       0,        // qsub2_then_hsub
    9437             :       0,        // qsub2_then_ssub
    9438             :       0,        // subo64_then_sub_32
    9439             :       0,        // zsub1_then_bsub
    9440             :       0,        // zsub1_then_dsub
    9441             :       0,        // zsub1_then_hsub
    9442             :       0,        // zsub1_then_ssub
    9443             :       0,        // zsub1_then_zsub
    9444             :       0,        // zsub1_then_zsub_hi
    9445             :       0,        // zsub3_then_bsub
    9446             :       0,        // zsub3_then_dsub
    9447             :       0,        // zsub3_then_hsub
    9448             :       0,        // zsub3_then_ssub
    9449             :       0,        // zsub3_then_zsub
    9450             :       0,        // zsub3_then_zsub_hi
    9451             :       0,        // zsub2_then_bsub
    9452             :       0,        // zsub2_then_dsub
    9453             :       0,        // zsub2_then_hsub
    9454             :       0,        // zsub2_then_ssub
    9455             :       0,        // zsub2_then_zsub
    9456             :       0,        // zsub2_then_zsub_hi
    9457             :       0,        // dsub0_dsub1
    9458             :       0,        // dsub0_dsub1_dsub2
    9459             :       0,        // dsub1_dsub2
    9460             :       0,        // dsub1_dsub2_dsub3
    9461             :       0,        // dsub2_dsub3
    9462             :       0,        // dsub_qsub1_then_dsub
    9463             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9464             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9465             :       0,        // qsub0_qsub1
    9466             :       0,        // qsub0_qsub1_qsub2
    9467             :       0,        // qsub1_qsub2
    9468             :       0,        // qsub1_qsub2_qsub3
    9469             :       0,        // qsub2_qsub3
    9470             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9471             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9472             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9473             :       0,        // sub_32_subo64_then_sub_32
    9474             :       0,        // dsub_zsub1_then_dsub
    9475             :       0,        // zsub_zsub1_then_zsub
    9476             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9477             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9478             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9479             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9480             :       0,        // zsub0_zsub1
    9481             :       0,        // zsub0_zsub1_zsub2
    9482             :       0,        // zsub1_zsub2
    9483             :       0,        // zsub1_zsub2_zsub3
    9484             :       0,        // zsub2_zsub3
    9485             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9486             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9487             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9488             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9489             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9490             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9491             :     },
    9492             :     {   // GPR32
    9493             :       0,        // bsub
    9494             :       0,        // dsub
    9495             :       0,        // dsub0
    9496             :       0,        // dsub1
    9497             :       0,        // dsub2
    9498             :       0,        // dsub3
    9499             :       0,        // hsub
    9500             :       0,        // qhisub
    9501             :       0,        // qsub
    9502             :       0,        // qsub0
    9503             :       0,        // qsub1
    9504             :       0,        // qsub2
    9505             :       0,        // qsub3
    9506             :       0,        // ssub
    9507             :       0,        // sub_32
    9508             :       0,        // sube32
    9509             :       0,        // sube64
    9510             :       0,        // subo32
    9511             :       0,        // subo64
    9512             :       0,        // zsub
    9513             :       0,        // zsub0
    9514             :       0,        // zsub1
    9515             :       0,        // zsub2
    9516             :       0,        // zsub3
    9517             :       0,        // zsub_hi
    9518             :       0,        // dsub1_then_bsub
    9519             :       0,        // dsub1_then_hsub
    9520             :       0,        // dsub1_then_ssub
    9521             :       0,        // dsub3_then_bsub
    9522             :       0,        // dsub3_then_hsub
    9523             :       0,        // dsub3_then_ssub
    9524             :       0,        // dsub2_then_bsub
    9525             :       0,        // dsub2_then_hsub
    9526             :       0,        // dsub2_then_ssub
    9527             :       0,        // qsub1_then_bsub
    9528             :       0,        // qsub1_then_dsub
    9529             :       0,        // qsub1_then_hsub
    9530             :       0,        // qsub1_then_ssub
    9531             :       0,        // qsub3_then_bsub
    9532             :       0,        // qsub3_then_dsub
    9533             :       0,        // qsub3_then_hsub
    9534             :       0,        // qsub3_then_ssub
    9535             :       0,        // qsub2_then_bsub
    9536             :       0,        // qsub2_then_dsub
    9537             :       0,        // qsub2_then_hsub
    9538             :       0,        // qsub2_then_ssub
    9539             :       0,        // subo64_then_sub_32
    9540             :       0,        // zsub1_then_bsub
    9541             :       0,        // zsub1_then_dsub
    9542             :       0,        // zsub1_then_hsub
    9543             :       0,        // zsub1_then_ssub
    9544             :       0,        // zsub1_then_zsub
    9545             :       0,        // zsub1_then_zsub_hi
    9546             :       0,        // zsub3_then_bsub
    9547             :       0,        // zsub3_then_dsub
    9548             :       0,        // zsub3_then_hsub
    9549             :       0,        // zsub3_then_ssub
    9550             :       0,        // zsub3_then_zsub
    9551             :       0,        // zsub3_then_zsub_hi
    9552             :       0,        // zsub2_then_bsub
    9553             :       0,        // zsub2_then_dsub
    9554             :       0,        // zsub2_then_hsub
    9555             :       0,        // zsub2_then_ssub
    9556             :       0,        // zsub2_then_zsub
    9557             :       0,        // zsub2_then_zsub_hi
    9558             :       0,        // dsub0_dsub1
    9559             :       0,        // dsub0_dsub1_dsub2
    9560             :       0,        // dsub1_dsub2
    9561             :       0,        // dsub1_dsub2_dsub3
    9562             :       0,        // dsub2_dsub3
    9563             :       0,        // dsub_qsub1_then_dsub
    9564             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9565             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9566             :       0,        // qsub0_qsub1
    9567             :       0,        // qsub0_qsub1_qsub2
    9568             :       0,        // qsub1_qsub2
    9569             :       0,        // qsub1_qsub2_qsub3
    9570             :       0,        // qsub2_qsub3
    9571             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9572             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9573             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9574             :       0,        // sub_32_subo64_then_sub_32
    9575             :       0,        // dsub_zsub1_then_dsub
    9576             :       0,        // zsub_zsub1_then_zsub
    9577             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9578             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9579             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9580             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9581             :       0,        // zsub0_zsub1
    9582             :       0,        // zsub0_zsub1_zsub2
    9583             :       0,        // zsub1_zsub2
    9584             :       0,        // zsub1_zsub2_zsub3
    9585             :       0,        // zsub2_zsub3
    9586             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9587             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9588             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9589             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9590             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9591             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9592             :     },
    9593             :     {   // GPR32sp
    9594             :       0,        // bsub
    9595             :       0,        // dsub
    9596             :       0,        // dsub0
    9597             :       0,        // dsub1
    9598             :       0,        // dsub2
    9599             :       0,        // dsub3
    9600             :       0,        // hsub
    9601             :       0,        // qhisub
    9602             :       0,        // qsub
    9603             :       0,        // qsub0
    9604             :       0,        // qsub1
    9605             :       0,        // qsub2
    9606             :       0,        // qsub3
    9607             :       0,        // ssub
    9608             :       0,        // sub_32
    9609             :       0,        // sube32
    9610             :       0,        // sube64
    9611             :       0,        // subo32
    9612             :       0,        // subo64
    9613             :       0,        // zsub
    9614             :       0,        // zsub0
    9615             :       0,        // zsub1
    9616             :       0,        // zsub2
    9617             :       0,        // zsub3
    9618             :       0,        // zsub_hi
    9619             :       0,        // dsub1_then_bsub
    9620             :       0,        // dsub1_then_hsub
    9621             :       0,        // dsub1_then_ssub
    9622             :       0,        // dsub3_then_bsub
    9623             :       0,        // dsub3_then_hsub
    9624             :       0,        // dsub3_then_ssub
    9625             :       0,        // dsub2_then_bsub
    9626             :       0,        // dsub2_then_hsub
    9627             :       0,        // dsub2_then_ssub
    9628             :       0,        // qsub1_then_bsub
    9629             :       0,        // qsub1_then_dsub
    9630             :       0,        // qsub1_then_hsub
    9631             :       0,        // qsub1_then_ssub
    9632             :       0,        // qsub3_then_bsub
    9633             :       0,        // qsub3_then_dsub
    9634             :       0,        // qsub3_then_hsub
    9635             :       0,        // qsub3_then_ssub
    9636             :       0,        // qsub2_then_bsub
    9637             :       0,        // qsub2_then_dsub
    9638             :       0,        // qsub2_then_hsub
    9639             :       0,        // qsub2_then_ssub
    9640             :       0,        // subo64_then_sub_32
    9641             :       0,        // zsub1_then_bsub
    9642             :       0,        // zsub1_then_dsub
    9643             :       0,        // zsub1_then_hsub
    9644             :       0,        // zsub1_then_ssub
    9645             :       0,        // zsub1_then_zsub
    9646             :       0,        // zsub1_then_zsub_hi
    9647             :       0,        // zsub3_then_bsub
    9648             :       0,        // zsub3_then_dsub
    9649             :       0,        // zsub3_then_hsub
    9650             :       0,        // zsub3_then_ssub
    9651             :       0,        // zsub3_then_zsub
    9652             :       0,        // zsub3_then_zsub_hi
    9653             :       0,        // zsub2_then_bsub
    9654             :       0,        // zsub2_then_dsub
    9655             :       0,        // zsub2_then_hsub
    9656             :       0,        // zsub2_then_ssub
    9657             :       0,        // zsub2_then_zsub
    9658             :       0,        // zsub2_then_zsub_hi
    9659             :       0,        // dsub0_dsub1
    9660             :       0,        // dsub0_dsub1_dsub2
    9661             :       0,        // dsub1_dsub2
    9662             :       0,        // dsub1_dsub2_dsub3
    9663             :       0,        // dsub2_dsub3
    9664             :       0,        // dsub_qsub1_then_dsub
    9665             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9666             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9667             :       0,        // qsub0_qsub1
    9668             :       0,        // qsub0_qsub1_qsub2
    9669             :       0,        // qsub1_qsub2
    9670             :       0,        // qsub1_qsub2_qsub3
    9671             :       0,        // qsub2_qsub3
    9672             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9673             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9674             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9675             :       0,        // sub_32_subo64_then_sub_32
    9676             :       0,        // dsub_zsub1_then_dsub
    9677             :       0,        // zsub_zsub1_then_zsub
    9678             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9679             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9680             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9681             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9682             :       0,        // zsub0_zsub1
    9683             :       0,        // zsub0_zsub1_zsub2
    9684             :       0,        // zsub1_zsub2
    9685             :       0,        // zsub1_zsub2_zsub3
    9686             :       0,        // zsub2_zsub3
    9687             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9688             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9689             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9690             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9691             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9692             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9693             :     },
    9694             :     {   // GPR32common
    9695             :       0,        // bsub
    9696             :       0,        // dsub
    9697             :       0,        // dsub0
    9698             :       0,        // dsub1
    9699             :       0,        // dsub2
    9700             :       0,        // dsub3
    9701             :       0,        // hsub
    9702             :       0,        // qhisub
    9703             :       0,        // qsub
    9704             :       0,        // qsub0
    9705             :       0,        // qsub1
    9706             :       0,        // qsub2
    9707             :       0,        // qsub3
    9708             :       0,        // ssub
    9709             :       0,        // sub_32
    9710             :       0,        // sube32
    9711             :       0,        // sube64
    9712             :       0,        // subo32
    9713             :       0,        // subo64
    9714             :       0,        // zsub
    9715             :       0,        // zsub0
    9716             :       0,        // zsub1
    9717             :       0,        // zsub2
    9718             :       0,        // zsub3
    9719             :       0,        // zsub_hi
    9720             :       0,        // dsub1_then_bsub
    9721             :       0,        // dsub1_then_hsub
    9722             :       0,        // dsub1_then_ssub
    9723             :       0,        // dsub3_then_bsub
    9724             :       0,        // dsub3_then_hsub
    9725             :       0,        // dsub3_then_ssub
    9726             :       0,        // dsub2_then_bsub
    9727             :       0,        // dsub2_then_hsub
    9728             :       0,        // dsub2_then_ssub
    9729             :       0,        // qsub1_then_bsub
    9730             :       0,        // qsub1_then_dsub
    9731             :       0,        // qsub1_then_hsub
    9732             :       0,        // qsub1_then_ssub
    9733             :       0,        // qsub3_then_bsub
    9734             :       0,        // qsub3_then_dsub
    9735             :       0,        // qsub3_then_hsub
    9736             :       0,        // qsub3_then_ssub
    9737             :       0,        // qsub2_then_bsub
    9738             :       0,        // qsub2_then_dsub
    9739             :       0,        // qsub2_then_hsub
    9740             :       0,        // qsub2_then_ssub
    9741             :       0,        // subo64_then_sub_32
    9742             :       0,        // zsub1_then_bsub
    9743             :       0,        // zsub1_then_dsub
    9744             :       0,        // zsub1_then_hsub
    9745             :       0,        // zsub1_then_ssub
    9746             :       0,        // zsub1_then_zsub
    9747             :       0,        // zsub1_then_zsub_hi
    9748             :       0,        // zsub3_then_bsub
    9749             :       0,        // zsub3_then_dsub
    9750             :       0,        // zsub3_then_hsub
    9751             :       0,        // zsub3_then_ssub
    9752             :       0,        // zsub3_then_zsub
    9753             :       0,        // zsub3_then_zsub_hi
    9754             :       0,        // zsub2_then_bsub
    9755             :       0,        // zsub2_then_dsub
    9756             :       0,        // zsub2_then_hsub
    9757             :       0,        // zsub2_then_ssub
    9758             :       0,        // zsub2_then_zsub
    9759             :       0,        // zsub2_then_zsub_hi
    9760             :       0,        // dsub0_dsub1
    9761             :       0,        // dsub0_dsub1_dsub2
    9762             :       0,        // dsub1_dsub2
    9763             :       0,        // dsub1_dsub2_dsub3
    9764             :       0,        // dsub2_dsub3
    9765             :       0,        // dsub_qsub1_then_dsub
    9766             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9767             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9768             :       0,        // qsub0_qsub1
    9769             :       0,        // qsub0_qsub1_qsub2
    9770             :       0,        // qsub1_qsub2
    9771             :       0,        // qsub1_qsub2_qsub3
    9772             :       0,        // qsub2_qsub3
    9773             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9774             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9775             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9776             :       0,        // sub_32_subo64_then_sub_32
    9777             :       0,        // dsub_zsub1_then_dsub
    9778             :       0,        // zsub_zsub1_then_zsub
    9779             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9780             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9781             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9782             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9783             :       0,        // zsub0_zsub1
    9784             :       0,        // zsub0_zsub1_zsub2
    9785             :       0,        // zsub1_zsub2
    9786             :       0,        // zsub1_zsub2_zsub3
    9787             :       0,        // zsub2_zsub3
    9788             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9789             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9790             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9791             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9792             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9793             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9794             :     },
    9795             :     {   // CCR
    9796             :       0,        // bsub
    9797             :       0,        // dsub
    9798             :       0,        // dsub0
    9799             :       0,        // dsub1
    9800             :       0,        // dsub2
    9801             :       0,        // dsub3
    9802             :       0,        // hsub
    9803             :       0,        // qhisub
    9804             :       0,        // qsub
    9805             :       0,        // qsub0
    9806             :       0,        // qsub1
    9807             :       0,        // qsub2
    9808             :       0,        // qsub3
    9809             :       0,        // ssub
    9810             :       0,        // sub_32
    9811             :       0,        // sube32
    9812             :       0,        // sube64
    9813             :       0,        // subo32
    9814             :       0,        // subo64
    9815             :       0,        // zsub
    9816             :       0,        // zsub0
    9817             :       0,        // zsub1
    9818             :       0,        // zsub2
    9819             :       0,        // zsub3
    9820             :       0,        // zsub_hi
    9821             :       0,        // dsub1_then_bsub
    9822             :       0,        // dsub1_then_hsub
    9823             :       0,        // dsub1_then_ssub
    9824             :       0,        // dsub3_then_bsub
    9825             :       0,        // dsub3_then_hsub
    9826             :       0,        // dsub3_then_ssub
    9827             :       0,        // dsub2_then_bsub
    9828             :       0,        // dsub2_then_hsub
    9829             :       0,        // dsub2_then_ssub
    9830             :       0,        // qsub1_then_bsub
    9831             :       0,        // qsub1_then_dsub
    9832             :       0,        // qsub1_then_hsub
    9833             :       0,        // qsub1_then_ssub
    9834             :       0,        // qsub3_then_bsub
    9835             :       0,        // qsub3_then_dsub
    9836             :       0,        // qsub3_then_hsub
    9837             :       0,        // qsub3_then_ssub
    9838             :       0,        // qsub2_then_bsub
    9839             :       0,        // qsub2_then_dsub
    9840             :       0,        // qsub2_then_hsub
    9841             :       0,        // qsub2_then_ssub
    9842             :       0,        // subo64_then_sub_32
    9843             :       0,        // zsub1_then_bsub
    9844             :       0,        // zsub1_then_dsub
    9845             :       0,        // zsub1_then_hsub
    9846             :       0,        // zsub1_then_ssub
    9847             :       0,        // zsub1_then_zsub
    9848             :       0,        // zsub1_then_zsub_hi
    9849             :       0,        // zsub3_then_bsub
    9850             :       0,        // zsub3_then_dsub
    9851             :       0,        // zsub3_then_hsub
    9852             :       0,        // zsub3_then_ssub
    9853             :       0,        // zsub3_then_zsub
    9854             :       0,        // zsub3_then_zsub_hi
    9855             :       0,        // zsub2_then_bsub
    9856             :       0,        // zsub2_then_dsub
    9857             :       0,        // zsub2_then_hsub
    9858             :       0,        // zsub2_then_ssub
    9859             :       0,        // zsub2_then_zsub
    9860             :       0,        // zsub2_then_zsub_hi
    9861             :       0,        // dsub0_dsub1
    9862             :       0,        // dsub0_dsub1_dsub2
    9863             :       0,        // dsub1_dsub2
    9864             :       0,        // dsub1_dsub2_dsub3
    9865             :       0,        // dsub2_dsub3
    9866             :       0,        // dsub_qsub1_then_dsub
    9867             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9868             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9869             :       0,        // qsub0_qsub1
    9870             :       0,        // qsub0_qsub1_qsub2
    9871             :       0,        // qsub1_qsub2
    9872             :       0,        // qsub1_qsub2_qsub3
    9873             :       0,        // qsub2_qsub3
    9874             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9875             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9876             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9877             :       0,        // sub_32_subo64_then_sub_32
    9878             :       0,        // dsub_zsub1_then_dsub
    9879             :       0,        // zsub_zsub1_then_zsub
    9880             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9881             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9882             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9883             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9884             :       0,        // zsub0_zsub1
    9885             :       0,        // zsub0_zsub1_zsub2
    9886             :       0,        // zsub1_zsub2
    9887             :       0,        // zsub1_zsub2_zsub3
    9888             :       0,        // zsub2_zsub3
    9889             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9890             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9891             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9892             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9893             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9894             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9895             :     },
    9896             :     {   // GPR32sponly
    9897             :       0,        // bsub
    9898             :       0,        // dsub
    9899             :       0,        // dsub0
    9900             :       0,        // dsub1
    9901             :       0,        // dsub2
    9902             :       0,        // dsub3
    9903             :       0,        // hsub
    9904             :       0,        // qhisub
    9905             :       0,        // qsub
    9906             :       0,        // qsub0
    9907             :       0,        // qsub1
    9908             :       0,        // qsub2
    9909             :       0,        // qsub3
    9910             :       0,        // ssub
    9911             :       0,        // sub_32
    9912             :       0,        // sube32
    9913             :       0,        // sube64
    9914             :       0,        // subo32
    9915             :       0,        // subo64
    9916             :       0,        // zsub
    9917             :       0,        // zsub0
    9918             :       0,        // zsub1
    9919             :       0,        // zsub2
    9920             :       0,        // zsub3
    9921             :       0,        // zsub_hi
    9922             :       0,        // dsub1_then_bsub
    9923             :       0,        // dsub1_then_hsub
    9924             :       0,        // dsub1_then_ssub
    9925             :       0,        // dsub3_then_bsub
    9926             :       0,        // dsub3_then_hsub
    9927             :       0,        // dsub3_then_ssub
    9928             :       0,        // dsub2_then_bsub
    9929             :       0,        // dsub2_then_hsub
    9930             :       0,        // dsub2_then_ssub
    9931             :       0,        // qsub1_then_bsub
    9932             :       0,        // qsub1_then_dsub
    9933             :       0,        // qsub1_then_hsub
    9934             :       0,        // qsub1_then_ssub
    9935             :       0,        // qsub3_then_bsub
    9936             :       0,        // qsub3_then_dsub
    9937             :       0,        // qsub3_then_hsub
    9938             :       0,        // qsub3_then_ssub
    9939             :       0,        // qsub2_then_bsub
    9940             :       0,        // qsub2_then_dsub
    9941             :       0,        // qsub2_then_hsub
    9942             :       0,        // qsub2_then_ssub
    9943             :       0,        // subo64_then_sub_32
    9944             :       0,        // zsub1_then_bsub
    9945             :       0,        // zsub1_then_dsub
    9946             :       0,        // zsub1_then_hsub
    9947             :       0,        // zsub1_then_ssub
    9948             :       0,        // zsub1_then_zsub
    9949             :       0,        // zsub1_then_zsub_hi
    9950             :       0,        // zsub3_then_bsub
    9951             :       0,        // zsub3_then_dsub
    9952             :       0,        // zsub3_then_hsub
    9953             :       0,        // zsub3_then_ssub
    9954             :       0,        // zsub3_then_zsub
    9955             :       0,        // zsub3_then_zsub_hi
    9956             :       0,        // zsub2_then_bsub
    9957             :       0,        // zsub2_then_dsub
    9958             :       0,        // zsub2_then_hsub
    9959             :       0,        // zsub2_then_ssub
    9960             :       0,        // zsub2_then_zsub
    9961             :       0,        // zsub2_then_zsub_hi
    9962             :       0,        // dsub0_dsub1
    9963             :       0,        // dsub0_dsub1_dsub2
    9964             :       0,        // dsub1_dsub2
    9965             :       0,        // dsub1_dsub2_dsub3
    9966             :       0,        // dsub2_dsub3
    9967             :       0,        // dsub_qsub1_then_dsub
    9968             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9969             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
    9970             :       0,        // qsub0_qsub1
    9971             :       0,        // qsub0_qsub1_qsub2
    9972             :       0,        // qsub1_qsub2
    9973             :       0,        // qsub1_qsub2_qsub3
    9974             :       0,        // qsub2_qsub3
    9975             :       0,        // qsub1_then_dsub_qsub2_then_dsub
    9976             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
    9977             :       0,        // qsub2_then_dsub_qsub3_then_dsub
    9978             :       0,        // sub_32_subo64_then_sub_32
    9979             :       0,        // dsub_zsub1_then_dsub
    9980             :       0,        // zsub_zsub1_then_zsub
    9981             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9982             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
    9983             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9984             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
    9985             :       0,        // zsub0_zsub1
    9986             :       0,        // zsub0_zsub1_zsub2
    9987             :       0,        // zsub1_zsub2
    9988             :       0,        // zsub1_zsub2_zsub3
    9989             :       0,        // zsub2_zsub3
    9990             :       0,        // zsub1_then_dsub_zsub2_then_dsub
    9991             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
    9992             :       0,        // zsub1_then_zsub_zsub2_then_zsub
    9993             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
    9994             :       0,        // zsub2_then_dsub_zsub3_then_dsub
    9995             :       0,        // zsub2_then_zsub_zsub3_then_zsub
    9996             :     },
    9997             :     {   // WSeqPairsClass
    9998             :       0,        // bsub
    9999             :       0,        // dsub
   10000             :       0,        // dsub0
   10001             :       0,        // dsub1
   10002             :       0,        // dsub2
   10003             :       0,        // dsub3
   10004             :       0,        // hsub
   10005             :       0,        // qhisub
   10006             :       0,        // qsub
   10007             :       0,        // qsub0
   10008             :       0,        // qsub1
   10009             :       0,        // qsub2
   10010             :       0,        // qsub3
   10011             :       0,        // ssub
   10012             :       0,        // sub_32
   10013             :       12,       // sube32 -> WSeqPairsClass
   10014             :       0,        // sube64
   10015             :       12,       // subo32 -> WSeqPairsClass
   10016             :       0,        // subo64
   10017             :       0,        // zsub
   10018             :       0,        // zsub0
   10019             :       0,        // zsub1
   10020             :       0,        // zsub2
   10021             :       0,        // zsub3
   10022             :       0,        // zsub_hi
   10023             :       0,        // dsub1_then_bsub
   10024             :       0,        // dsub1_then_hsub
   10025             :       0,        // dsub1_then_ssub
   10026             :       0,        // dsub3_then_bsub
   10027             :       0,        // dsub3_then_hsub
   10028             :       0,        // dsub3_then_ssub
   10029             :       0,        // dsub2_then_bsub
   10030             :       0,        // dsub2_then_hsub
   10031             :       0,        // dsub2_then_ssub
   10032             :       0,        // qsub1_then_bsub
   10033             :       0,        // qsub1_then_dsub
   10034             :       0,        // qsub1_then_hsub
   10035             :       0,        // qsub1_then_ssub
   10036             :       0,        // qsub3_then_bsub
   10037             :       0,        // qsub3_then_dsub
   10038             :       0,        // qsub3_then_hsub
   10039             :       0,        // qsub3_then_ssub
   10040             :       0,        // qsub2_then_bsub
   10041             :       0,        // qsub2_then_dsub
   10042             :       0,        // qsub2_then_hsub
   10043             :       0,        // qsub2_then_ssub
   10044             :       0,        // subo64_then_sub_32
   10045             :       0,        // zsub1_then_bsub
   10046             :       0,        // zsub1_then_dsub
   10047             :       0,        // zsub1_then_hsub
   10048             :       0,        // zsub1_then_ssub
   10049             :       0,        // zsub1_then_zsub
   10050             :       0,        // zsub1_then_zsub_hi
   10051             :       0,        // zsub3_then_bsub
   10052             :       0,        // zsub3_then_dsub
   10053             :       0,        // zsub3_then_hsub
   10054             :       0,        // zsub3_then_ssub
   10055             :       0,        // zsub3_then_zsub
   10056             :       0,        // zsub3_then_zsub_hi
   10057             :       0,        // zsub2_then_bsub
   10058             :       0,        // zsub2_then_dsub
   10059             :       0,        // zsub2_then_hsub
   10060             :       0,        // zsub2_then_ssub
   10061             :       0,        // zsub2_then_zsub
   10062             :       0,        // zsub2_then_zsub_hi
   10063             :       0,        // dsub0_dsub1
   10064             :       0,        // dsub0_dsub1_dsub2
   10065             :       0,        // dsub1_dsub2
   10066             :       0,        // dsub1_dsub2_dsub3
   10067             :       0,        // dsub2_dsub3
   10068             :       0,        // dsub_qsub1_then_dsub
   10069             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10070             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10071             :       0,        // qsub0_qsub1
   10072             :       0,        // qsub0_qsub1_qsub2
   10073             :       0,        // qsub1_qsub2
   10074             :       0,        // qsub1_qsub2_qsub3
   10075             :       0,        // qsub2_qsub3
   10076             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10077             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10078             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10079             :       0,        // sub_32_subo64_then_sub_32
   10080             :       0,        // dsub_zsub1_then_dsub
   10081             :       0,        // zsub_zsub1_then_zsub
   10082             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10083             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10084             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10085             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10086             :       0,        // zsub0_zsub1
   10087             :       0,        // zsub0_zsub1_zsub2
   10088             :       0,        // zsub1_zsub2
   10089             :       0,        // zsub1_zsub2_zsub3
   10090             :       0,        // zsub2_zsub3
   10091             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10092             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10093             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10094             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10095             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10096             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10097             :     },
   10098             :     {   // WSeqPairsClass_with_sube32_in_GPR32common
   10099             :       0,        // bsub
   10100             :       0,        // dsub
   10101             :       0,        // dsub0
   10102             :       0,        // dsub1
   10103             :       0,        // dsub2
   10104             :       0,        // dsub3
   10105             :       0,        // hsub
   10106             :       0,        // qhisub
   10107             :       0,        // qsub
   10108             :       0,        // qsub0
   10109             :       0,        // qsub1
   10110             :       0,        // qsub2
   10111             :       0,        // qsub3
   10112             :       0,        // ssub
   10113             :       0,        // sub_32
   10114             :       13,       // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common
   10115             :       0,        // sube64
   10116             :       13,       // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common
   10117             :       0,        // subo64
   10118             :       0,        // zsub
   10119             :       0,        // zsub0
   10120             :       0,        // zsub1
   10121             :       0,        // zsub2
   10122             :       0,        // zsub3
   10123             :       0,        // zsub_hi
   10124             :       0,        // dsub1_then_bsub
   10125             :       0,        // dsub1_then_hsub
   10126             :       0,        // dsub1_then_ssub
   10127             :       0,        // dsub3_then_bsub
   10128             :       0,        // dsub3_then_hsub
   10129             :       0,        // dsub3_then_ssub
   10130             :       0,        // dsub2_then_bsub
   10131             :       0,        // dsub2_then_hsub
   10132             :       0,        // dsub2_then_ssub
   10133             :       0,        // qsub1_then_bsub
   10134             :       0,        // qsub1_then_dsub
   10135             :       0,        // qsub1_then_hsub
   10136             :       0,        // qsub1_then_ssub
   10137             :       0,        // qsub3_then_bsub
   10138             :       0,        // qsub3_then_dsub
   10139             :       0,        // qsub3_then_hsub
   10140             :       0,        // qsub3_then_ssub
   10141             :       0,        // qsub2_then_bsub
   10142             :       0,        // qsub2_then_dsub
   10143             :       0,        // qsub2_then_hsub
   10144             :       0,        // qsub2_then_ssub
   10145             :       0,        // subo64_then_sub_32
   10146             :       0,        // zsub1_then_bsub
   10147             :       0,        // zsub1_then_dsub
   10148             :       0,        // zsub1_then_hsub
   10149             :       0,        // zsub1_then_ssub
   10150             :       0,        // zsub1_then_zsub
   10151             :       0,        // zsub1_then_zsub_hi
   10152             :       0,        // zsub3_then_bsub
   10153             :       0,        // zsub3_then_dsub
   10154             :       0,        // zsub3_then_hsub
   10155             :       0,        // zsub3_then_ssub
   10156             :       0,        // zsub3_then_zsub
   10157             :       0,        // zsub3_then_zsub_hi
   10158             :       0,        // zsub2_then_bsub
   10159             :       0,        // zsub2_then_dsub
   10160             :       0,        // zsub2_then_hsub
   10161             :       0,        // zsub2_then_ssub
   10162             :       0,        // zsub2_then_zsub
   10163             :       0,        // zsub2_then_zsub_hi
   10164             :       0,        // dsub0_dsub1
   10165             :       0,        // dsub0_dsub1_dsub2
   10166             :       0,        // dsub1_dsub2
   10167             :       0,        // dsub1_dsub2_dsub3
   10168             :       0,        // dsub2_dsub3
   10169             :       0,        // dsub_qsub1_then_dsub
   10170             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10171             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10172             :       0,        // qsub0_qsub1
   10173             :       0,        // qsub0_qsub1_qsub2
   10174             :       0,        // qsub1_qsub2
   10175             :       0,        // qsub1_qsub2_qsub3
   10176             :       0,        // qsub2_qsub3
   10177             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10178             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10179             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10180             :       0,        // sub_32_subo64_then_sub_32
   10181             :       0,        // dsub_zsub1_then_dsub
   10182             :       0,        // zsub_zsub1_then_zsub
   10183             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10184             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10185             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10186             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10187             :       0,        // zsub0_zsub1
   10188             :       0,        // zsub0_zsub1_zsub2
   10189             :       0,        // zsub1_zsub2
   10190             :       0,        // zsub1_zsub2_zsub3
   10191             :       0,        // zsub2_zsub3
   10192             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10193             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10194             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10195             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10196             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10197             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10198             :     },
   10199             :     {   // WSeqPairsClass_with_subo32_in_GPR32common
   10200             :       0,        // bsub
   10201             :       0,        // dsub
   10202             :       0,        // dsub0
   10203             :       0,        // dsub1
   10204             :       0,        // dsub2
   10205             :       0,        // dsub3
   10206             :       0,        // hsub
   10207             :       0,        // qhisub
   10208             :       0,        // qsub
   10209             :       0,        // qsub0
   10210             :       0,        // qsub1
   10211             :       0,        // qsub2
   10212             :       0,        // qsub3
   10213             :       0,        // ssub
   10214             :       0,        // sub_32
   10215             :       14,       // sube32 -> WSeqPairsClass_with_subo32_in_GPR32common
   10216             :       0,        // sube64
   10217             :       14,       // subo32 -> WSeqPairsClass_with_subo32_in_GPR32common
   10218             :       0,        // subo64
   10219             :       0,        // zsub
   10220             :       0,        // zsub0
   10221             :       0,        // zsub1
   10222             :       0,        // zsub2
   10223             :       0,        // zsub3
   10224             :       0,        // zsub_hi
   10225             :       0,        // dsub1_then_bsub
   10226             :       0,        // dsub1_then_hsub
   10227             :       0,        // dsub1_then_ssub
   10228             :       0,        // dsub3_then_bsub
   10229             :       0,        // dsub3_then_hsub
   10230             :       0,        // dsub3_then_ssub
   10231             :       0,        // dsub2_then_bsub
   10232             :       0,        // dsub2_then_hsub
   10233             :       0,        // dsub2_then_ssub
   10234             :       0,        // qsub1_then_bsub
   10235             :       0,        // qsub1_then_dsub
   10236             :       0,        // qsub1_then_hsub
   10237             :       0,        // qsub1_then_ssub
   10238             :       0,        // qsub3_then_bsub
   10239             :       0,        // qsub3_then_dsub
   10240             :       0,        // qsub3_then_hsub
   10241             :       0,        // qsub3_then_ssub
   10242             :       0,        // qsub2_then_bsub
   10243             :       0,        // qsub2_then_dsub
   10244             :       0,        // qsub2_then_hsub
   10245             :       0,        // qsub2_then_ssub
   10246             :       0,        // subo64_then_sub_32
   10247             :       0,        // zsub1_then_bsub
   10248             :       0,        // zsub1_then_dsub
   10249             :       0,        // zsub1_then_hsub
   10250             :       0,        // zsub1_then_ssub
   10251             :       0,        // zsub1_then_zsub
   10252             :       0,        // zsub1_then_zsub_hi
   10253             :       0,        // zsub3_then_bsub
   10254             :       0,        // zsub3_then_dsub
   10255             :       0,        // zsub3_then_hsub
   10256             :       0,        // zsub3_then_ssub
   10257             :       0,        // zsub3_then_zsub
   10258             :       0,        // zsub3_then_zsub_hi
   10259             :       0,        // zsub2_then_bsub
   10260             :       0,        // zsub2_then_dsub
   10261             :       0,        // zsub2_then_hsub
   10262             :       0,        // zsub2_then_ssub
   10263             :       0,        // zsub2_then_zsub
   10264             :       0,        // zsub2_then_zsub_hi
   10265             :       0,        // dsub0_dsub1
   10266             :       0,        // dsub0_dsub1_dsub2
   10267             :       0,        // dsub1_dsub2
   10268             :       0,        // dsub1_dsub2_dsub3
   10269             :       0,        // dsub2_dsub3
   10270             :       0,        // dsub_qsub1_then_dsub
   10271             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10272             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10273             :       0,        // qsub0_qsub1
   10274             :       0,        // qsub0_qsub1_qsub2
   10275             :       0,        // qsub1_qsub2
   10276             :       0,        // qsub1_qsub2_qsub3
   10277             :       0,        // qsub2_qsub3
   10278             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10279             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10280             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10281             :       0,        // sub_32_subo64_then_sub_32
   10282             :       0,        // dsub_zsub1_then_dsub
   10283             :       0,        // zsub_zsub1_then_zsub
   10284             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10285             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10286             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10287             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10288             :       0,        // zsub0_zsub1
   10289             :       0,        // zsub0_zsub1_zsub2
   10290             :       0,        // zsub1_zsub2
   10291             :       0,        // zsub1_zsub2_zsub3
   10292             :       0,        // zsub2_zsub3
   10293             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10294             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10295             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10296             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10297             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10298             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10299             :     },
   10300             :     {   // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
   10301             :       0,        // bsub
   10302             :       0,        // dsub
   10303             :       0,        // dsub0
   10304             :       0,        // dsub1
   10305             :       0,        // dsub2
   10306             :       0,        // dsub3
   10307             :       0,        // hsub
   10308             :       0,        // qhisub
   10309             :       0,        // qsub
   10310             :       0,        // qsub0
   10311             :       0,        // qsub1
   10312             :       0,        // qsub2
   10313             :       0,        // qsub3
   10314             :       0,        // ssub
   10315             :       0,        // sub_32
   10316             :       15,       // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
   10317             :       0,        // sube64
   10318             :       15,       // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
   10319             :       0,        // subo64
   10320             :       0,        // zsub
   10321             :       0,        // zsub0
   10322             :       0,        // zsub1
   10323             :       0,        // zsub2
   10324             :       0,        // zsub3
   10325             :       0,        // zsub_hi
   10326             :       0,        // dsub1_then_bsub
   10327             :       0,        // dsub1_then_hsub
   10328             :       0,        // dsub1_then_ssub
   10329             :       0,        // dsub3_then_bsub
   10330             :       0,        // dsub3_then_hsub
   10331             :       0,        // dsub3_then_ssub
   10332             :       0,        // dsub2_then_bsub
   10333             :       0,        // dsub2_then_hsub
   10334             :       0,        // dsub2_then_ssub
   10335             :       0,        // qsub1_then_bsub
   10336             :       0,        // qsub1_then_dsub
   10337             :       0,        // qsub1_then_hsub
   10338             :       0,        // qsub1_then_ssub
   10339             :       0,        // qsub3_then_bsub
   10340             :       0,        // qsub3_then_dsub
   10341             :       0,        // qsub3_then_hsub
   10342             :       0,        // qsub3_then_ssub
   10343             :       0,        // qsub2_then_bsub
   10344             :       0,        // qsub2_then_dsub
   10345             :       0,        // qsub2_then_hsub
   10346             :       0,        // qsub2_then_ssub
   10347             :       0,        // subo64_then_sub_32
   10348             :       0,        // zsub1_then_bsub
   10349             :       0,        // zsub1_then_dsub
   10350             :       0,        // zsub1_then_hsub
   10351             :       0,        // zsub1_then_ssub
   10352             :       0,        // zsub1_then_zsub
   10353             :       0,        // zsub1_then_zsub_hi
   10354             :       0,        // zsub3_then_bsub
   10355             :       0,        // zsub3_then_dsub
   10356             :       0,        // zsub3_then_hsub
   10357             :       0,        // zsub3_then_ssub
   10358             :       0,        // zsub3_then_zsub
   10359             :       0,        // zsub3_then_zsub_hi
   10360             :       0,        // zsub2_then_bsub
   10361             :       0,        // zsub2_then_dsub
   10362             :       0,        // zsub2_then_hsub
   10363             :       0,        // zsub2_then_ssub
   10364             :       0,        // zsub2_then_zsub
   10365             :       0,        // zsub2_then_zsub_hi
   10366             :       0,        // dsub0_dsub1
   10367             :       0,        // dsub0_dsub1_dsub2
   10368             :       0,        // dsub1_dsub2
   10369             :       0,        // dsub1_dsub2_dsub3
   10370             :       0,        // dsub2_dsub3
   10371             :       0,        // dsub_qsub1_then_dsub
   10372             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10373             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10374             :       0,        // qsub0_qsub1
   10375             :       0,        // qsub0_qsub1_qsub2
   10376             :       0,        // qsub1_qsub2
   10377             :       0,        // qsub1_qsub2_qsub3
   10378             :       0,        // qsub2_qsub3
   10379             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10380             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10381             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10382             :       0,        // sub_32_subo64_then_sub_32
   10383             :       0,        // dsub_zsub1_then_dsub
   10384             :       0,        // zsub_zsub1_then_zsub
   10385             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10386             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10387             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10388             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10389             :       0,        // zsub0_zsub1
   10390             :       0,        // zsub0_zsub1_zsub2
   10391             :       0,        // zsub1_zsub2
   10392             :       0,        // zsub1_zsub2_zsub3
   10393             :       0,        // zsub2_zsub3
   10394             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10395             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10396             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10397             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10398             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10399             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10400             :     },
   10401             :     {   // GPR64all
   10402             :       0,        // bsub
   10403             :       0,        // dsub
   10404             :       0,        // dsub0
   10405             :       0,        // dsub1
   10406             :       0,        // dsub2
   10407             :       0,        // dsub3
   10408             :       0,        // hsub
   10409             :       0,        // qhisub
   10410             :       0,        // qsub
   10411             :       0,        // qsub0
   10412             :       0,        // qsub1
   10413             :       0,        // qsub2
   10414             :       0,        // qsub3
   10415             :       0,        // ssub
   10416             :       16,       // sub_32 -> GPR64all
   10417             :       0,        // sube32
   10418             :       0,        // sube64
   10419             :       0,        // subo32
   10420             :       0,        // subo64
   10421             :       0,        // zsub
   10422             :       0,        // zsub0
   10423             :       0,        // zsub1
   10424             :       0,        // zsub2
   10425             :       0,        // zsub3
   10426             :       0,        // zsub_hi
   10427             :       0,        // dsub1_then_bsub
   10428             :       0,        // dsub1_then_hsub
   10429             :       0,        // dsub1_then_ssub
   10430             :       0,        // dsub3_then_bsub
   10431             :       0,        // dsub3_then_hsub
   10432             :       0,        // dsub3_then_ssub
   10433             :       0,        // dsub2_then_bsub
   10434             :       0,        // dsub2_then_hsub
   10435             :       0,        // dsub2_then_ssub
   10436             :       0,        // qsub1_then_bsub
   10437             :       0,        // qsub1_then_dsub
   10438             :       0,        // qsub1_then_hsub
   10439             :       0,        // qsub1_then_ssub
   10440             :       0,        // qsub3_then_bsub
   10441             :       0,        // qsub3_then_dsub
   10442             :       0,        // qsub3_then_hsub
   10443             :       0,        // qsub3_then_ssub
   10444             :       0,        // qsub2_then_bsub
   10445             :       0,        // qsub2_then_dsub
   10446             :       0,        // qsub2_then_hsub
   10447             :       0,        // qsub2_then_ssub
   10448             :       0,        // subo64_then_sub_32
   10449             :       0,        // zsub1_then_bsub
   10450             :       0,        // zsub1_then_dsub
   10451             :       0,        // zsub1_then_hsub
   10452             :       0,        // zsub1_then_ssub
   10453             :       0,        // zsub1_then_zsub
   10454             :       0,        // zsub1_then_zsub_hi
   10455             :       0,        // zsub3_then_bsub
   10456             :       0,        // zsub3_then_dsub
   10457             :       0,        // zsub3_then_hsub
   10458             :       0,        // zsub3_then_ssub
   10459             :       0,        // zsub3_then_zsub
   10460             :       0,        // zsub3_then_zsub_hi
   10461             :       0,        // zsub2_then_bsub
   10462             :       0,        // zsub2_then_dsub
   10463             :       0,        // zsub2_then_hsub
   10464             :       0,        // zsub2_then_ssub
   10465             :       0,        // zsub2_then_zsub
   10466             :       0,        // zsub2_then_zsub_hi
   10467             :       0,        // dsub0_dsub1
   10468             :       0,        // dsub0_dsub1_dsub2
   10469             :       0,        // dsub1_dsub2
   10470             :       0,        // dsub1_dsub2_dsub3
   10471             :       0,        // dsub2_dsub3
   10472             :       0,        // dsub_qsub1_then_dsub
   10473             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10474             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10475             :       0,        // qsub0_qsub1
   10476             :       0,        // qsub0_qsub1_qsub2
   10477             :       0,        // qsub1_qsub2
   10478             :       0,        // qsub1_qsub2_qsub3
   10479             :       0,        // qsub2_qsub3
   10480             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10481             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10482             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10483             :       0,        // sub_32_subo64_then_sub_32
   10484             :       0,        // dsub_zsub1_then_dsub
   10485             :       0,        // zsub_zsub1_then_zsub
   10486             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10487             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10488             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10489             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10490             :       0,        // zsub0_zsub1
   10491             :       0,        // zsub0_zsub1_zsub2
   10492             :       0,        // zsub1_zsub2
   10493             :       0,        // zsub1_zsub2_zsub3
   10494             :       0,        // zsub2_zsub3
   10495             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10496             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10497             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10498             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10499             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10500             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10501             :     },
   10502             :     {   // FPR64
   10503             :       17,       // bsub -> FPR64
   10504             :       0,        // dsub
   10505             :       0,        // dsub0
   10506             :       0,        // dsub1
   10507             :       0,        // dsub2
   10508             :       0,        // dsub3
   10509             :       17,       // hsub -> FPR64
   10510             :       0,        // qhisub
   10511             :       0,        // qsub
   10512             :       0,        // qsub0
   10513             :       0,        // qsub1
   10514             :       0,        // qsub2
   10515             :       0,        // qsub3
   10516             :       17,       // ssub -> FPR64
   10517             :       0,        // sub_32
   10518             :       0,        // sube32
   10519             :       0,        // sube64
   10520             :       0,        // subo32
   10521             :       0,        // subo64
   10522             :       0,        // zsub
   10523             :       0,        // zsub0
   10524             :       0,        // zsub1
   10525             :       0,        // zsub2
   10526             :       0,        // zsub3
   10527             :       0,        // zsub_hi
   10528             :       0,        // dsub1_then_bsub
   10529             :       0,        // dsub1_then_hsub
   10530             :       0,        // dsub1_then_ssub
   10531             :       0,        // dsub3_then_bsub
   10532             :       0,        // dsub3_then_hsub
   10533             :       0,        // dsub3_then_ssub
   10534             :       0,        // dsub2_then_bsub
   10535             :       0,        // dsub2_then_hsub
   10536             :       0,        // dsub2_then_ssub
   10537             :       0,        // qsub1_then_bsub
   10538             :       0,        // qsub1_then_dsub
   10539             :       0,        // qsub1_then_hsub
   10540             :       0,        // qsub1_then_ssub
   10541             :       0,        // qsub3_then_bsub
   10542             :       0,        // qsub3_then_dsub
   10543             :       0,        // qsub3_then_hsub
   10544             :       0,        // qsub3_then_ssub
   10545             :       0,        // qsub2_then_bsub
   10546             :       0,        // qsub2_then_dsub
   10547             :       0,        // qsub2_then_hsub
   10548             :       0,        // qsub2_then_ssub
   10549             :       0,        // subo64_then_sub_32
   10550             :       0,        // zsub1_then_bsub
   10551             :       0,        // zsub1_then_dsub
   10552             :       0,        // zsub1_then_hsub
   10553             :       0,        // zsub1_then_ssub
   10554             :       0,        // zsub1_then_zsub
   10555             :       0,        // zsub1_then_zsub_hi
   10556             :       0,        // zsub3_then_bsub
   10557             :       0,        // zsub3_then_dsub
   10558             :       0,        // zsub3_then_hsub
   10559             :       0,        // zsub3_then_ssub
   10560             :       0,        // zsub3_then_zsub
   10561             :       0,        // zsub3_then_zsub_hi
   10562             :       0,        // zsub2_then_bsub
   10563             :       0,        // zsub2_then_dsub
   10564             :       0,        // zsub2_then_hsub
   10565             :       0,        // zsub2_then_ssub
   10566             :       0,        // zsub2_then_zsub
   10567             :       0,        // zsub2_then_zsub_hi
   10568             :       0,        // dsub0_dsub1
   10569             :       0,        // dsub0_dsub1_dsub2
   10570             :       0,        // dsub1_dsub2
   10571             :       0,        // dsub1_dsub2_dsub3
   10572             :       0,        // dsub2_dsub3
   10573             :       0,        // dsub_qsub1_then_dsub
   10574             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10575             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10576             :       0,        // qsub0_qsub1
   10577             :       0,        // qsub0_qsub1_qsub2
   10578             :       0,        // qsub1_qsub2
   10579             :       0,        // qsub1_qsub2_qsub3
   10580             :       0,        // qsub2_qsub3
   10581             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10582             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10583             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10584             :       0,        // sub_32_subo64_then_sub_32
   10585             :       0,        // dsub_zsub1_then_dsub
   10586             :       0,        // zsub_zsub1_then_zsub
   10587             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10588             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10589             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10590             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10591             :       0,        // zsub0_zsub1
   10592             :       0,        // zsub0_zsub1_zsub2
   10593             :       0,        // zsub1_zsub2
   10594             :       0,        // zsub1_zsub2_zsub3
   10595             :       0,        // zsub2_zsub3
   10596             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10597             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10598             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10599             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10600             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10601             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10602             :     },
   10603             :     {   // GPR64
   10604             :       0,        // bsub
   10605             :       0,        // dsub
   10606             :       0,        // dsub0
   10607             :       0,        // dsub1
   10608             :       0,        // dsub2
   10609             :       0,        // dsub3
   10610             :       0,        // hsub
   10611             :       0,        // qhisub
   10612             :       0,        // qsub
   10613             :       0,        // qsub0
   10614             :       0,        // qsub1
   10615             :       0,        // qsub2
   10616             :       0,        // qsub3
   10617             :       0,        // ssub
   10618             :       18,       // sub_32 -> GPR64
   10619             :       0,        // sube32
   10620             :       0,        // sube64
   10621             :       0,        // subo32
   10622             :       0,        // subo64
   10623             :       0,        // zsub
   10624             :       0,        // zsub0
   10625             :       0,        // zsub1
   10626             :       0,        // zsub2
   10627             :       0,        // zsub3
   10628             :       0,        // zsub_hi
   10629             :       0,        // dsub1_then_bsub
   10630             :       0,        // dsub1_then_hsub
   10631             :       0,        // dsub1_then_ssub
   10632             :       0,        // dsub3_then_bsub
   10633             :       0,        // dsub3_then_hsub
   10634             :       0,        // dsub3_then_ssub
   10635             :       0,        // dsub2_then_bsub
   10636             :       0,        // dsub2_then_hsub
   10637             :       0,        // dsub2_then_ssub
   10638             :       0,        // qsub1_then_bsub
   10639             :       0,        // qsub1_then_dsub
   10640             :       0,        // qsub1_then_hsub
   10641             :       0,        // qsub1_then_ssub
   10642             :       0,        // qsub3_then_bsub
   10643             :       0,        // qsub3_then_dsub
   10644             :       0,        // qsub3_then_hsub
   10645             :       0,        // qsub3_then_ssub
   10646             :       0,        // qsub2_then_bsub
   10647             :       0,        // qsub2_then_dsub
   10648             :       0,        // qsub2_then_hsub
   10649             :       0,        // qsub2_then_ssub
   10650             :       0,        // subo64_then_sub_32
   10651             :       0,        // zsub1_then_bsub
   10652             :       0,        // zsub1_then_dsub
   10653             :       0,        // zsub1_then_hsub
   10654             :       0,        // zsub1_then_ssub
   10655             :       0,        // zsub1_then_zsub
   10656             :       0,        // zsub1_then_zsub_hi
   10657             :       0,        // zsub3_then_bsub
   10658             :       0,        // zsub3_then_dsub
   10659             :       0,        // zsub3_then_hsub
   10660             :       0,        // zsub3_then_ssub
   10661             :       0,        // zsub3_then_zsub
   10662             :       0,        // zsub3_then_zsub_hi
   10663             :       0,        // zsub2_then_bsub
   10664             :       0,        // zsub2_then_dsub
   10665             :       0,        // zsub2_then_hsub
   10666             :       0,        // zsub2_then_ssub
   10667             :       0,        // zsub2_then_zsub
   10668             :       0,        // zsub2_then_zsub_hi
   10669             :       0,        // dsub0_dsub1
   10670             :       0,        // dsub0_dsub1_dsub2
   10671             :       0,        // dsub1_dsub2
   10672             :       0,        // dsub1_dsub2_dsub3
   10673             :       0,        // dsub2_dsub3
   10674             :       0,        // dsub_qsub1_then_dsub
   10675             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10676             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10677             :       0,        // qsub0_qsub1
   10678             :       0,        // qsub0_qsub1_qsub2
   10679             :       0,        // qsub1_qsub2
   10680             :       0,        // qsub1_qsub2_qsub3
   10681             :       0,        // qsub2_qsub3
   10682             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10683             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10684             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10685             :       0,        // sub_32_subo64_then_sub_32
   10686             :       0,        // dsub_zsub1_then_dsub
   10687             :       0,        // zsub_zsub1_then_zsub
   10688             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10689             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10690             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10691             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10692             :       0,        // zsub0_zsub1
   10693             :       0,        // zsub0_zsub1_zsub2
   10694             :       0,        // zsub1_zsub2
   10695             :       0,        // zsub1_zsub2_zsub3
   10696             :       0,        // zsub2_zsub3
   10697             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10698             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10699             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10700             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10701             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10702             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10703             :     },
   10704             :     {   // GPR64sp
   10705             :       0,        // bsub
   10706             :       0,        // dsub
   10707             :       0,        // dsub0
   10708             :       0,        // dsub1
   10709             :       0,        // dsub2
   10710             :       0,        // dsub3
   10711             :       0,        // hsub
   10712             :       0,        // qhisub
   10713             :       0,        // qsub
   10714             :       0,        // qsub0
   10715             :       0,        // qsub1
   10716             :       0,        // qsub2
   10717             :       0,        // qsub3
   10718             :       0,        // ssub
   10719             :       19,       // sub_32 -> GPR64sp
   10720             :       0,        // sube32
   10721             :       0,        // sube64
   10722             :       0,        // subo32
   10723             :       0,        // subo64
   10724             :       0,        // zsub
   10725             :       0,        // zsub0
   10726             :       0,        // zsub1
   10727             :       0,        // zsub2
   10728             :       0,        // zsub3
   10729             :       0,        // zsub_hi
   10730             :       0,        // dsub1_then_bsub
   10731             :       0,        // dsub1_then_hsub
   10732             :       0,        // dsub1_then_ssub
   10733             :       0,        // dsub3_then_bsub
   10734             :       0,        // dsub3_then_hsub
   10735             :       0,        // dsub3_then_ssub
   10736             :       0,        // dsub2_then_bsub
   10737             :       0,        // dsub2_then_hsub
   10738             :       0,        // dsub2_then_ssub
   10739             :       0,        // qsub1_then_bsub
   10740             :       0,        // qsub1_then_dsub
   10741             :       0,        // qsub1_then_hsub
   10742             :       0,        // qsub1_then_ssub
   10743             :       0,        // qsub3_then_bsub
   10744             :       0,        // qsub3_then_dsub
   10745             :       0,        // qsub3_then_hsub
   10746             :       0,        // qsub3_then_ssub
   10747             :       0,        // qsub2_then_bsub
   10748             :       0,        // qsub2_then_dsub
   10749             :       0,        // qsub2_then_hsub
   10750             :       0,        // qsub2_then_ssub
   10751             :       0,        // subo64_then_sub_32
   10752             :       0,        // zsub1_then_bsub
   10753             :       0,        // zsub1_then_dsub
   10754             :       0,        // zsub1_then_hsub
   10755             :       0,        // zsub1_then_ssub
   10756             :       0,        // zsub1_then_zsub
   10757             :       0,        // zsub1_then_zsub_hi
   10758             :       0,        // zsub3_then_bsub
   10759             :       0,        // zsub3_then_dsub
   10760             :       0,        // zsub3_then_hsub
   10761             :       0,        // zsub3_then_ssub
   10762             :       0,        // zsub3_then_zsub
   10763             :       0,        // zsub3_then_zsub_hi
   10764             :       0,        // zsub2_then_bsub
   10765             :       0,        // zsub2_then_dsub
   10766             :       0,        // zsub2_then_hsub
   10767             :       0,        // zsub2_then_ssub
   10768             :       0,        // zsub2_then_zsub
   10769             :       0,        // zsub2_then_zsub_hi
   10770             :       0,        // dsub0_dsub1
   10771             :       0,        // dsub0_dsub1_dsub2
   10772             :       0,        // dsub1_dsub2
   10773             :       0,        // dsub1_dsub2_dsub3
   10774             :       0,        // dsub2_dsub3
   10775             :       0,        // dsub_qsub1_then_dsub
   10776             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10777             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10778             :       0,        // qsub0_qsub1
   10779             :       0,        // qsub0_qsub1_qsub2
   10780             :       0,        // qsub1_qsub2
   10781             :       0,        // qsub1_qsub2_qsub3
   10782             :       0,        // qsub2_qsub3
   10783             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10784             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10785             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10786             :       0,        // sub_32_subo64_then_sub_32
   10787             :       0,        // dsub_zsub1_then_dsub
   10788             :       0,        // zsub_zsub1_then_zsub
   10789             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10790             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10791             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10792             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10793             :       0,        // zsub0_zsub1
   10794             :       0,        // zsub0_zsub1_zsub2
   10795             :       0,        // zsub1_zsub2
   10796             :       0,        // zsub1_zsub2_zsub3
   10797             :       0,        // zsub2_zsub3
   10798             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10799             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10800             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10801             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10802             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10803             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10804             :     },
   10805             :     {   // GPR64common
   10806             :       0,        // bsub
   10807             :       0,        // dsub
   10808             :       0,        // dsub0
   10809             :       0,        // dsub1
   10810             :       0,        // dsub2
   10811             :       0,        // dsub3
   10812             :       0,        // hsub
   10813             :       0,        // qhisub
   10814             :       0,        // qsub
   10815             :       0,        // qsub0
   10816             :       0,        // qsub1
   10817             :       0,        // qsub2
   10818             :       0,        // qsub3
   10819             :       0,        // ssub
   10820             :       20,       // sub_32 -> GPR64common
   10821             :       0,        // sube32
   10822             :       0,        // sube64
   10823             :       0,        // subo32
   10824             :       0,        // subo64
   10825             :       0,        // zsub
   10826             :       0,        // zsub0
   10827             :       0,        // zsub1
   10828             :       0,        // zsub2
   10829             :       0,        // zsub3
   10830             :       0,        // zsub_hi
   10831             :       0,        // dsub1_then_bsub
   10832             :       0,        // dsub1_then_hsub
   10833             :       0,        // dsub1_then_ssub
   10834             :       0,        // dsub3_then_bsub
   10835             :       0,        // dsub3_then_hsub
   10836             :       0,        // dsub3_then_ssub
   10837             :       0,        // dsub2_then_bsub
   10838             :       0,        // dsub2_then_hsub
   10839             :       0,        // dsub2_then_ssub
   10840             :       0,        // qsub1_then_bsub
   10841             :       0,        // qsub1_then_dsub
   10842             :       0,        // qsub1_then_hsub
   10843             :       0,        // qsub1_then_ssub
   10844             :       0,        // qsub3_then_bsub
   10845             :       0,        // qsub3_then_dsub
   10846             :       0,        // qsub3_then_hsub
   10847             :       0,        // qsub3_then_ssub
   10848             :       0,        // qsub2_then_bsub
   10849             :       0,        // qsub2_then_dsub
   10850             :       0,        // qsub2_then_hsub
   10851             :       0,        // qsub2_then_ssub
   10852             :       0,        // subo64_then_sub_32
   10853             :       0,        // zsub1_then_bsub
   10854             :       0,        // zsub1_then_dsub
   10855             :       0,        // zsub1_then_hsub
   10856             :       0,        // zsub1_then_ssub
   10857             :       0,        // zsub1_then_zsub
   10858             :       0,        // zsub1_then_zsub_hi
   10859             :       0,        // zsub3_then_bsub
   10860             :       0,        // zsub3_then_dsub
   10861             :       0,        // zsub3_then_hsub
   10862             :       0,        // zsub3_then_ssub
   10863             :       0,        // zsub3_then_zsub
   10864             :       0,        // zsub3_then_zsub_hi
   10865             :       0,        // zsub2_then_bsub
   10866             :       0,        // zsub2_then_dsub
   10867             :       0,        // zsub2_then_hsub
   10868             :       0,        // zsub2_then_ssub
   10869             :       0,        // zsub2_then_zsub
   10870             :       0,        // zsub2_then_zsub_hi
   10871             :       0,        // dsub0_dsub1
   10872             :       0,        // dsub0_dsub1_dsub2
   10873             :       0,        // dsub1_dsub2
   10874             :       0,        // dsub1_dsub2_dsub3
   10875             :       0,        // dsub2_dsub3
   10876             :       0,        // dsub_qsub1_then_dsub
   10877             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10878             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10879             :       0,        // qsub0_qsub1
   10880             :       0,        // qsub0_qsub1_qsub2
   10881             :       0,        // qsub1_qsub2
   10882             :       0,        // qsub1_qsub2_qsub3
   10883             :       0,        // qsub2_qsub3
   10884             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10885             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10886             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10887             :       0,        // sub_32_subo64_then_sub_32
   10888             :       0,        // dsub_zsub1_then_dsub
   10889             :       0,        // zsub_zsub1_then_zsub
   10890             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10891             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10892             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10893             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10894             :       0,        // zsub0_zsub1
   10895             :       0,        // zsub0_zsub1_zsub2
   10896             :       0,        // zsub1_zsub2
   10897             :       0,        // zsub1_zsub2_zsub3
   10898             :       0,        // zsub2_zsub3
   10899             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   10900             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10901             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   10902             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10903             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   10904             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   10905             :     },
   10906             :     {   // tcGPR64
   10907             :       0,        // bsub
   10908             :       0,        // dsub
   10909             :       0,        // dsub0
   10910             :       0,        // dsub1
   10911             :       0,        // dsub2
   10912             :       0,        // dsub3
   10913             :       0,        // hsub
   10914             :       0,        // qhisub
   10915             :       0,        // qsub
   10916             :       0,        // qsub0
   10917             :       0,        // qsub1
   10918             :       0,        // qsub2
   10919             :       0,        // qsub3
   10920             :       0,        // ssub
   10921             :       21,       // sub_32 -> tcGPR64
   10922             :       0,        // sube32
   10923             :       0,        // sube64
   10924             :       0,        // subo32
   10925             :       0,        // subo64
   10926             :       0,        // zsub
   10927             :       0,        // zsub0
   10928             :       0,        // zsub1
   10929             :       0,        // zsub2
   10930             :       0,        // zsub3
   10931             :       0,        // zsub_hi
   10932             :       0,        // dsub1_then_bsub
   10933             :       0,        // dsub1_then_hsub
   10934             :       0,        // dsub1_then_ssub
   10935             :       0,        // dsub3_then_bsub
   10936             :       0,        // dsub3_then_hsub
   10937             :       0,        // dsub3_then_ssub
   10938             :       0,        // dsub2_then_bsub
   10939             :       0,        // dsub2_then_hsub
   10940             :       0,        // dsub2_then_ssub
   10941             :       0,        // qsub1_then_bsub
   10942             :       0,        // qsub1_then_dsub
   10943             :       0,        // qsub1_then_hsub
   10944             :       0,        // qsub1_then_ssub
   10945             :       0,        // qsub3_then_bsub
   10946             :       0,        // qsub3_then_dsub
   10947             :       0,        // qsub3_then_hsub
   10948             :       0,        // qsub3_then_ssub
   10949             :       0,        // qsub2_then_bsub
   10950             :       0,        // qsub2_then_dsub
   10951             :       0,        // qsub2_then_hsub
   10952             :       0,        // qsub2_then_ssub
   10953             :       0,        // subo64_then_sub_32
   10954             :       0,        // zsub1_then_bsub
   10955             :       0,        // zsub1_then_dsub
   10956             :       0,        // zsub1_then_hsub
   10957             :       0,        // zsub1_then_ssub
   10958             :       0,        // zsub1_then_zsub
   10959             :       0,        // zsub1_then_zsub_hi
   10960             :       0,        // zsub3_then_bsub
   10961             :       0,        // zsub3_then_dsub
   10962             :       0,        // zsub3_then_hsub
   10963             :       0,        // zsub3_then_ssub
   10964             :       0,        // zsub3_then_zsub
   10965             :       0,        // zsub3_then_zsub_hi
   10966             :       0,        // zsub2_then_bsub
   10967             :       0,        // zsub2_then_dsub
   10968             :       0,        // zsub2_then_hsub
   10969             :       0,        // zsub2_then_ssub
   10970             :       0,        // zsub2_then_zsub
   10971             :       0,        // zsub2_then_zsub_hi
   10972             :       0,        // dsub0_dsub1
   10973             :       0,        // dsub0_dsub1_dsub2
   10974             :       0,        // dsub1_dsub2
   10975             :       0,        // dsub1_dsub2_dsub3
   10976             :       0,        // dsub2_dsub3
   10977             :       0,        // dsub_qsub1_then_dsub
   10978             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10979             :       0,        // dsub_qsub1_then_dsub_qsub2_then_dsub
   10980             :       0,        // qsub0_qsub1
   10981             :       0,        // qsub0_qsub1_qsub2
   10982             :       0,        // qsub1_qsub2
   10983             :       0,        // qsub1_qsub2_qsub3
   10984             :       0,        // qsub2_qsub3
   10985             :       0,        // qsub1_then_dsub_qsub2_then_dsub
   10986             :       0,        // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
   10987             :       0,        // qsub2_then_dsub_qsub3_then_dsub
   10988             :       0,        // sub_32_subo64_then_sub_32
   10989             :       0,        // dsub_zsub1_then_dsub
   10990             :       0,        // zsub_zsub1_then_zsub
   10991             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   10992             :       0,        // dsub_zsub1_then_dsub_zsub2_then_dsub
   10993             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   10994             :       0,        // zsub_zsub1_then_zsub_zsub2_then_zsub
   10995             :       0,        // zsub0_zsub1
   10996             :       0,        // zsub0_zsub1_zsub2
   10997             :       0,        // zsub1_zsub2
   10998             :       0,        // zsub1_zsub2_zsub3
   10999             :       0,        // zsub2_zsub3
   11000             :       0,        // zsub1_then_dsub_zsub2_then_dsub
   11001             :       0,        // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
   11002             :       0,        // zsub1_then_zsub_zsub2_then_zsub
   11003             :       0,        // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
   11004             :       0,        // zsub2_then_dsub_zsub3_then_dsub
   11005             :       0,        // zsub2_then_zsub_zsub3_then_zsub
   11006             :     },
   11007             :     {   // GPR64sponly
   11008             :       0,        // bsub
   11009             :       0,        // dsub
   11010             :       0,        // dsub0
   11011             :       0,        // dsub1
   11012             :       0,        // dsub2
   11013             :       0,        // dsub3
   11014             :       0,        // hsub
   11015             :       0,        // qhisub
   11016             :       0,        // qsub
   11017             :       0,        // qsub0
   11018             :       0,        // qsub1
   11019             :       0,        // qsub2
   11020             :       0,        // qsub3
   11021             :       0,        // ssub
   11022             :       22,       // sub_32 -> GPR64sponly
   11023             :       0,        // sube32
   11024             :       0,        // sube64
   11025             :       0,        // subo32
   11026             :       0,        // subo64
   11027             :       0,        // zsub
   11028             :       0,        // zsub0
   11029             :       0,        // zsub1
   11030             :       0,        // zsub2
   11031             :       0,        // zsub3
   11032             :       0,        // zsub_hi
   11033             :       0,        // dsub1_then_bsub
   11034             :       0,        // dsub1_then_hsub
   11035             :       0,        // dsub1_then_ssub
   11036             :       0,        // dsub3_then_bsub
   11037             :       0,        // dsub3_then_hsub
   11038             :       0,        // dsub3_then_ssub
   11039             :       0,        // dsub2_then_bsub
   11040             :       0,        // dsub2_then_hsub
   11041             :       0,        // dsub2_then_ssub
   11042             :       0,        // qsub1_then_bsub
   11043             :       0,        // qsub1_then_dsub
   11044             :       0,        // qsub1_then_hsub
   11045             :