LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenCallingConv.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 125 127 98.4 %
Date: 2018-07-13 00:08:38 Functions: 5 5 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Calling Convention Implementation Fragment                                 *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
      10             :                       MVT LocVT, CCValAssign::LocInfo LocInfo,
      11             :                       ISD::ArgFlagsTy ArgFlags, CCState &State);
      12             : static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
      13             :                            MVT LocVT, CCValAssign::LocInfo LocInfo,
      14             :                            ISD::ArgFlagsTy ArgFlags, CCState &State);
      15             : static bool CC_SI(unsigned ValNo, MVT ValVT,
      16             :                   MVT LocVT, CCValAssign::LocInfo LocInfo,
      17             :                   ISD::ArgFlagsTy ArgFlags, CCState &State);
      18             : static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
      19             :                               MVT LocVT, CCValAssign::LocInfo LocInfo,
      20             :                               ISD::ArgFlagsTy ArgFlags, CCState &State);
      21             : static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
      22             :                             MVT LocVT, CCValAssign::LocInfo LocInfo,
      23             :                             ISD::ArgFlagsTy ArgFlags, CCState &State);
      24             : 
      25             : 
      26       10246 : static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
      27             :                       MVT LocVT, CCValAssign::LocInfo LocInfo,
      28             :                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
      29             : 
      30       10246 :   if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
      31       10246 :     if (!CC_SI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      32             :       return false;
      33             :   }
      34             : 
      35           0 :   if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C) {
      36           0 :     if (!CC_AMDGPU_Func(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      37             :       return false;
      38             :   }
      39             : 
      40             :   return true;  // CC didn't match.
      41             : }
      42             : 
      43             : 
      44        5155 : static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
      45             :                            MVT LocVT, CCValAssign::LocInfo LocInfo,
      46             :                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
      47             : 
      48        5155 :   if (ArgFlags.isByVal()) {
      49          98 :     State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
      50          98 :     return false;
      51             :   }
      52             : 
      53        5057 :   if (LocVT == MVT::i1) {
      54             :     LocVT = MVT::i32;
      55          28 :     if (ArgFlags.isSExt())
      56             :         LocInfo = CCValAssign::SExt;
      57          21 :     else if (ArgFlags.isZExt())
      58             :         LocInfo = CCValAssign::ZExt;
      59             :     else
      60             :         LocInfo = CCValAssign::AExt;
      61             :   }
      62             : 
      63        5057 :   if (LocVT == MVT::i1 ||
      64       10114 :       LocVT == MVT::i8 ||
      65             :       LocVT == MVT::i16) {
      66         235 :     if (ArgFlags.isSExt() || ArgFlags.isZExt()) {
      67             :       LocVT = MVT::i32;
      68          26 :       if (ArgFlags.isSExt())
      69             :             LocInfo = CCValAssign::SExt;
      70          15 :       else if (ArgFlags.isZExt())
      71             :             LocInfo = CCValAssign::ZExt;
      72             :       else
      73             :             LocInfo = CCValAssign::AExt;
      74             :     }
      75             :   }
      76             : 
      77        2069 :   if (LocVT == MVT::i32 ||
      78        1560 :       LocVT == MVT::f32 ||
      79        1340 :       LocVT == MVT::i16 ||
      80         885 :       LocVT == MVT::f16 ||
      81         872 :       LocVT == MVT::v2i16 ||
      82        5822 :       LocVT == MVT::v2f16 ||
      83             :       LocVT == MVT::i1) {
      84             :     static const MCPhysReg RegList1[] = {
      85             :       AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
      86             :     };
      87        4292 :     if (unsigned Reg = State.AllocateReg(RegList1)) {
      88        8224 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      89        4112 :       return false;
      90             :     }
      91             :   }
      92             : 
      93         603 :   if (LocVT == MVT::i64 ||
      94         579 :       LocVT == MVT::f64 ||
      95         562 :       LocVT == MVT::v2i32 ||
      96         551 :       LocVT == MVT::v2f32 ||
      97         534 :       LocVT == MVT::v4i32 ||
      98         518 :       LocVT == MVT::v4f32 ||
      99         505 :       LocVT == MVT::v8i32 ||
     100         499 :       LocVT == MVT::v8f32 ||
     101         413 :       LocVT == MVT::v16i32 ||
     102         407 :       LocVT == MVT::v16f32 ||
     103         358 :       LocVT == MVT::v2i64 ||
     104         310 :       LocVT == MVT::v2f64 ||
     105        1195 :       LocVT == MVT::v4i16 ||
     106             :       LocVT == MVT::v4f16) {
     107         765 :     if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     108             :         return false;
     109             :   }
     110             : 
     111          78 :   if (LocVT == MVT::i32 ||
     112          75 :       LocVT == MVT::f32 ||
     113          73 :       LocVT == MVT::v2i16 ||
     114          71 :       LocVT == MVT::v2f16 ||
     115          35 :       LocVT == MVT::i16 ||
     116         246 :       LocVT == MVT::f16 ||
     117             :       LocVT == MVT::i1) {
     118         180 :     unsigned Offset2 = State.AllocateStack(4, 4);
     119         360 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
     120         180 :     return false;
     121             :   }
     122             : 
     123          30 :   if (LocVT == MVT::i64 ||
     124          30 :       LocVT == MVT::f64 ||
     125          60 :       LocVT == MVT::v2i32 ||
     126             :       LocVT == MVT::v2f32) {
     127           9 :     unsigned Offset3 = State.AllocateStack(8, 4);
     128          18 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
     129           9 :     return false;
     130             :   }
     131             : 
     132          21 :   if (LocVT == MVT::v4i32 ||
     133          18 :       LocVT == MVT::v4f32 ||
     134          39 :       LocVT == MVT::v2i64 ||
     135             :       LocVT == MVT::v2f64) {
     136          12 :     unsigned Offset4 = State.AllocateStack(16, 4);
     137          24 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
     138          12 :     return false;
     139             :   }
     140             : 
     141          21 :   if (LocVT == MVT::v8i32 ||
     142             :       LocVT == MVT::v8f32) {
     143           6 :     unsigned Offset5 = State.AllocateStack(32, 4);
     144          12 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
     145           6 :     return false;
     146             :   }
     147             : 
     148           9 :   if (LocVT == MVT::v16i32 ||
     149             :       LocVT == MVT::v16f32) {
     150           6 :     unsigned Offset6 = State.AllocateStack(64, 4);
     151          12 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
     152           6 :     return false;
     153             :   }
     154             : 
     155             :   return true;  // CC didn't match.
     156             : }
     157             : 
     158             : 
     159       10246 : static bool CC_SI(unsigned ValNo, MVT ValVT,
     160             :                   MVT LocVT, CCValAssign::LocInfo LocInfo,
     161             :                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
     162             : 
     163       10246 :   if (ArgFlags.isInReg()) {
     164        6924 :     if (LocVT == MVT::f32 ||
     165        7131 :         LocVT == MVT::i32 ||
     166             :         LocVT == MVT::f16) {
     167             :       static const MCPhysReg RegList1[] = {
     168             :         AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
     169             :       };
     170        6846 :       if (unsigned Reg = State.AllocateReg(RegList1)) {
     171       13692 :         State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     172        6846 :         return false;
     173             :       }
     174             :     }
     175             :   }
     176             : 
     177        3400 :   if (ArgFlags.isInReg()) {
     178         142 :     if (LocVT == MVT::i64) {
     179         142 :       if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     180             :             return false;
     181             :     }
     182             :   }
     183             : 
     184        3258 :   if (ArgFlags.isByVal()) {
     185         166 :     if (LocVT == MVT::i64) {
     186         117 :       if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     187             :             return false;
     188             :     }
     189             :   }
     190             : 
     191        3141 :   if (!ArgFlags.isInReg()) {
     192        1383 :     if (LocVT == MVT::f32 ||
     193        3165 :         LocVT == MVT::i32 ||
     194             :         LocVT == MVT::f16) {
     195             :       static const MCPhysReg RegList2[] = {
     196             :         AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
     197             :       };
     198        3141 :       if (unsigned Reg = State.AllocateReg(RegList2)) {
     199        6282 :         State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     200        3141 :         return false;
     201             :       }
     202             :     }
     203             :   }
     204             : 
     205             :   return true;  // CC didn't match.
     206             : }
     207             : 
     208             : 
     209        2066 : static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
     210             :                               MVT LocVT, CCValAssign::LocInfo LocInfo,
     211             :                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
     212             : 
     213        2066 :   if (LocVT == MVT::i1) {
     214             :     LocVT = MVT::i32;
     215          18 :     if (ArgFlags.isSExt())
     216             :         LocInfo = CCValAssign::SExt;
     217          15 :     else if (ArgFlags.isZExt())
     218             :         LocInfo = CCValAssign::ZExt;
     219             :     else
     220             :         LocInfo = CCValAssign::AExt;
     221             :   }
     222             : 
     223        2066 :   if (LocVT == MVT::i1 ||
     224             :       LocVT == MVT::i16) {
     225         388 :     if (ArgFlags.isSExt() || ArgFlags.isZExt()) {
     226             :       LocVT = MVT::i32;
     227           8 :       if (ArgFlags.isSExt())
     228             :             LocInfo = CCValAssign::SExt;
     229           4 :       else if (ArgFlags.isZExt())
     230             :             LocInfo = CCValAssign::ZExt;
     231             :       else
     232             :             LocInfo = CCValAssign::AExt;
     233             :     }
     234             :   }
     235             : 
     236        1446 :   if (LocVT == MVT::i32 ||
     237         898 :       LocVT == MVT::f32 ||
     238         710 :       LocVT == MVT::i16 ||
     239         666 :       LocVT == MVT::f16 ||
     240        2658 :       LocVT == MVT::v2i16 ||
     241             :       LocVT == MVT::v2f16) {
     242             :     static const MCPhysReg RegList1[] = {
     243             :       AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
     244             :     };
     245        1534 :     if (unsigned Reg = State.AllocateReg(RegList1)) {
     246        3050 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     247        1525 :       return false;
     248             :     }
     249             :   }
     250             : 
     251         379 :   if (LocVT == MVT::i64 ||
     252         351 :       LocVT == MVT::f64 ||
     253         335 :       LocVT == MVT::v2i32 ||
     254         295 :       LocVT == MVT::v2f32 ||
     255         271 :       LocVT == MVT::v4i32 ||
     256         265 :       LocVT == MVT::v4f32 ||
     257         241 :       LocVT == MVT::v8i32 ||
     258         241 :       LocVT == MVT::v8f32 ||
     259         187 :       LocVT == MVT::v16i32 ||
     260         187 :       LocVT == MVT::v16f32 ||
     261          97 :       LocVT == MVT::v2i64 ||
     262          85 :       LocVT == MVT::v2f64 ||
     263         582 :       LocVT == MVT::v4i16 ||
     264             :       LocVT == MVT::v4f16) {
     265         532 :     if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     266             :         return false;
     267             :   }
     268             : 
     269             :   return true;  // CC didn't match.
     270             : }
     271             : 
     272             : 
     273        2654 : static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
     274             :                             MVT LocVT, CCValAssign::LocInfo LocInfo,
     275             :                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
     276             : 
     277        2654 :   if (LocVT == MVT::i32) {
     278             :     static const MCPhysReg RegList1[] = {
     279             :       AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
     280             :     };
     281         151 :     if (unsigned Reg = State.AllocateReg(RegList1)) {
     282         302 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     283         151 :       return false;
     284             :     }
     285             :   }
     286             : 
     287        2503 :   if (LocVT == MVT::f32 ||
     288             :       LocVT == MVT::f16) {
     289             :     static const MCPhysReg RegList2[] = {
     290             :       AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
     291             :     };
     292        2503 :     if (unsigned Reg = State.AllocateReg(RegList2)) {
     293        5006 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     294        2503 :       return false;
     295             :     }
     296             :   }
     297             : 
     298             :   return true;  // CC didn't match.
     299             : }

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