LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenCallingConv.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 134 136 98.5 %
Date: 2018-05-20 00:06:23 Functions: 7 7 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Calling Convention Implementation Fragment                                 *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
      10             :                       MVT LocVT, CCValAssign::LocInfo LocInfo,
      11             :                       ISD::ArgFlagsTy ArgFlags, CCState &State);
      12             : static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
      13             :                            MVT LocVT, CCValAssign::LocInfo LocInfo,
      14             :                            ISD::ArgFlagsTy ArgFlags, CCState &State);
      15             : static bool CC_AMDGPU_Kernel(unsigned ValNo, MVT ValVT,
      16             :                              MVT LocVT, CCValAssign::LocInfo LocInfo,
      17             :                              ISD::ArgFlagsTy ArgFlags, CCState &State);
      18             : static bool CC_R600(unsigned ValNo, MVT ValVT,
      19             :                     MVT LocVT, CCValAssign::LocInfo LocInfo,
      20             :                     ISD::ArgFlagsTy ArgFlags, CCState &State);
      21             : static bool CC_SI(unsigned ValNo, MVT ValVT,
      22             :                   MVT LocVT, CCValAssign::LocInfo LocInfo,
      23             :                   ISD::ArgFlagsTy ArgFlags, CCState &State);
      24             : static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
      25             :                               MVT LocVT, CCValAssign::LocInfo LocInfo,
      26             :                               ISD::ArgFlagsTy ArgFlags, CCState &State);
      27             : static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
      28             :                             MVT LocVT, CCValAssign::LocInfo LocInfo,
      29             :                             ISD::ArgFlagsTy ArgFlags, CCState &State);
      30             : 
      31             : 
      32        6993 : static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
      33             :                       MVT LocVT, CCValAssign::LocInfo LocInfo,
      34             :                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
      35             : 
      36        6993 :   if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >=AMDGPUSubtarget::SOUTHERN_ISLANDS && !AMDGPU::isShader(State.getCallingConv())) {
      37             :     if (!CC_AMDGPU_Kernel(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      38             :       return false;
      39             :   }
      40             : 
      41        6993 :   if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !AMDGPU::isShader(State.getCallingConv())) {
      42             :     if (!CC_AMDGPU_Kernel(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      43             :       return false;
      44             :   }
      45             : 
      46        6993 :   if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
      47        6930 :     if (!CC_SI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      48             :       return false;
      49             :   }
      50             : 
      51          63 :   if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C) {
      52           0 :     if (!CC_AMDGPU_Func(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      53             :       return false;
      54             :   }
      55             : 
      56          63 :   if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
      57          63 :     if (!CC_R600(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      58             :       return false;
      59             :   }
      60             : 
      61             :   return true;  // CC didn't match.
      62             : }
      63             : 
      64             : 
      65        5327 : static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
      66             :                            MVT LocVT, CCValAssign::LocInfo LocInfo,
      67             :                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
      68             : 
      69        5327 :   if (ArgFlags.isByVal()) {
      70          98 :     State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
      71          98 :     return false;
      72             :   }
      73             : 
      74        5229 :   if (LocVT == MVT::i1) {
      75             :     LocVT = MVT::i32;
      76          27 :     if (ArgFlags.isSExt())
      77             :         LocInfo = CCValAssign::SExt;
      78          20 :     else if (ArgFlags.isZExt())
      79             :         LocInfo = CCValAssign::ZExt;
      80             :     else
      81             :         LocInfo = CCValAssign::AExt;
      82             :   }
      83             : 
      84        5229 :   if (LocVT == MVT::i1 ||
      85       10458 :       LocVT == MVT::i8 ||
      86             :       LocVT == MVT::i16) {
      87         690 :     if (ArgFlags.isSExt() || ArgFlags.isZExt()) {
      88             :       LocVT = MVT::i32;
      89          23 :       if (ArgFlags.isSExt())
      90             :             LocInfo = CCValAssign::SExt;
      91          13 :       else if (ArgFlags.isZExt())
      92             :             LocInfo = CCValAssign::ZExt;
      93             :       else
      94             :             LocInfo = CCValAssign::AExt;
      95             :     }
      96             :   }
      97             : 
      98        2332 :   if (LocVT == MVT::i32 ||
      99        1823 :       LocVT == MVT::f32 ||
     100        1496 :       LocVT == MVT::i16 ||
     101         791 :       LocVT == MVT::f16 ||
     102         738 :       LocVT == MVT::v2i16 ||
     103        5855 :       LocVT == MVT::v2f16 ||
     104             :       LocVT == MVT::i1) {
     105             :     static const MCPhysReg RegList1[] = {
     106             :       AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
     107             :     };
     108        4603 :     if (unsigned Reg = State.AllocateReg(RegList1)) {
     109        8842 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     110        4421 :       return false;
     111             :     }
     112             :   }
     113             : 
     114         475 :   if (LocVT == MVT::i64 ||
     115         451 :       LocVT == MVT::f64 ||
     116         434 :       LocVT == MVT::v2i32 ||
     117         423 :       LocVT == MVT::v2f32 ||
     118         406 :       LocVT == MVT::v4i32 ||
     119         390 :       LocVT == MVT::v4f32 ||
     120         377 :       LocVT == MVT::v8i32 ||
     121         371 :       LocVT == MVT::v8f32 ||
     122         285 :       LocVT == MVT::v16i32 ||
     123         279 :       LocVT == MVT::v16f32 ||
     124        1038 :       LocVT == MVT::v2i64 ||
     125             :       LocVT == MVT::v2f64) {
     126         626 :     if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     127             :         return false;
     128             :   }
     129             : 
     130          80 :   if (LocVT == MVT::i32 ||
     131          77 :       LocVT == MVT::f32 ||
     132          76 :       LocVT == MVT::v2i16 ||
     133          75 :       LocVT == MVT::v2f16 ||
     134          37 :       LocVT == MVT::i16 ||
     135         248 :       LocVT == MVT::f16 ||
     136             :       LocVT == MVT::i1) {
     137         182 :     unsigned Offset2 = State.AllocateStack(4, 4);
     138         364 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
     139         182 :     return false;
     140             :   }
     141             : 
     142          30 :   if (LocVT == MVT::i64 ||
     143          30 :       LocVT == MVT::f64 ||
     144          60 :       LocVT == MVT::v2i32 ||
     145             :       LocVT == MVT::v2f32) {
     146           9 :     unsigned Offset3 = State.AllocateStack(8, 4);
     147          18 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
     148           9 :     return false;
     149             :   }
     150             : 
     151          21 :   if (LocVT == MVT::v4i32 ||
     152          18 :       LocVT == MVT::v4f32 ||
     153          39 :       LocVT == MVT::v2i64 ||
     154             :       LocVT == MVT::v2f64) {
     155          12 :     unsigned Offset4 = State.AllocateStack(16, 4);
     156          24 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
     157          12 :     return false;
     158             :   }
     159             : 
     160          21 :   if (LocVT == MVT::v8i32 ||
     161             :       LocVT == MVT::v8f32) {
     162           6 :     unsigned Offset5 = State.AllocateStack(32, 4);
     163          12 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
     164           6 :     return false;
     165             :   }
     166             : 
     167           9 :   if (LocVT == MVT::v16i32 ||
     168             :       LocVT == MVT::v16f32) {
     169           6 :     unsigned Offset6 = State.AllocateStack(64, 4);
     170          12 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
     171           6 :     return false;
     172             :   }
     173             : 
     174             :   return true;  // CC didn't match.
     175             : }
     176             : 
     177             : 
     178          26 : static bool CC_AMDGPU_Kernel(unsigned ValNo, MVT ValVT,
     179             :                              MVT LocVT, CCValAssign::LocInfo LocInfo,
     180             :                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
     181             : 
     182          26 :   if (allocateKernArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     183             :     return false;
     184             : 
     185           0 :   return true;  // CC didn't match.
     186             : }
     187             : 
     188             : 
     189          63 : static bool CC_R600(unsigned ValNo, MVT ValVT,
     190             :                     MVT LocVT, CCValAssign::LocInfo LocInfo,
     191             :                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
     192             : 
     193          63 :   if (ArgFlags.isInReg()) {
     194          63 :     if (LocVT == MVT::v4f32 ||
     195             :         LocVT == MVT::v4i32) {
     196             :       static const MCPhysReg RegList1[] = {
     197             :         AMDGPU::T0_XYZW, AMDGPU::T1_XYZW, AMDGPU::T2_XYZW, AMDGPU::T3_XYZW, AMDGPU::T4_XYZW, AMDGPU::T5_XYZW, AMDGPU::T6_XYZW, AMDGPU::T7_XYZW, AMDGPU::T8_XYZW, AMDGPU::T9_XYZW, AMDGPU::T10_XYZW, AMDGPU::T11_XYZW, AMDGPU::T12_XYZW, AMDGPU::T13_XYZW, AMDGPU::T14_XYZW, AMDGPU::T15_XYZW, AMDGPU::T16_XYZW, AMDGPU::T17_XYZW, AMDGPU::T18_XYZW, AMDGPU::T19_XYZW, AMDGPU::T20_XYZW, AMDGPU::T21_XYZW, AMDGPU::T22_XYZW, AMDGPU::T23_XYZW, AMDGPU::T24_XYZW, AMDGPU::T25_XYZW, AMDGPU::T26_XYZW, AMDGPU::T27_XYZW, AMDGPU::T28_XYZW, AMDGPU::T29_XYZW, AMDGPU::T30_XYZW, AMDGPU::T31_XYZW, AMDGPU::T32_XYZW
     198             :       };
     199          63 :       if (unsigned Reg = State.AllocateReg(RegList1)) {
     200         126 :         State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     201          63 :         return false;
     202             :       }
     203             :     }
     204             :   }
     205             : 
     206             :   return true;  // CC didn't match.
     207             : }
     208             : 
     209             : 
     210        6930 : static bool CC_SI(unsigned ValNo, MVT ValVT,
     211             :                   MVT LocVT, CCValAssign::LocInfo LocInfo,
     212             :                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
     213             : 
     214        6930 :   if (ArgFlags.isInReg()) {
     215        4368 :     if (LocVT == MVT::f32 ||
     216        4581 :         LocVT == MVT::i32 ||
     217             :         LocVT == MVT::f16) {
     218             :       static const MCPhysReg RegList1[] = {
     219             :         AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
     220             :       };
     221        4286 :       if (unsigned Reg = State.AllocateReg(RegList1)) {
     222        8572 :         State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     223        4286 :         return false;
     224             :       }
     225             :     }
     226             :   }
     227             : 
     228        2644 :   if (ArgFlags.isInReg()) {
     229         147 :     if (LocVT == MVT::i64) {
     230         147 :       if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     231             :             return false;
     232             :     }
     233             :   }
     234             : 
     235        2497 :   if (ArgFlags.isByVal()) {
     236         171 :     if (LocVT == MVT::i64) {
     237         117 :       if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     238             :             return false;
     239             :     }
     240             :   }
     241             : 
     242        2380 :   if (!ArgFlags.isInReg()) {
     243        1311 :     if (LocVT == MVT::f32 ||
     244        2404 :         LocVT == MVT::i32 ||
     245             :         LocVT == MVT::f16) {
     246             :       static const MCPhysReg RegList2[] = {
     247             :         AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
     248             :       };
     249        2380 :       if (unsigned Reg = State.AllocateReg(RegList2)) {
     250        4760 :         State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     251        2380 :         return false;
     252             :       }
     253             :     }
     254             :   }
     255             : 
     256             :   return true;  // CC didn't match.
     257             : }
     258             : 
     259             : 
     260        2081 : static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
     261             :                               MVT LocVT, CCValAssign::LocInfo LocInfo,
     262             :                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
     263             : 
     264        2081 :   if (LocVT == MVT::i1) {
     265             :     LocVT = MVT::i32;
     266          18 :     if (ArgFlags.isSExt())
     267             :         LocInfo = CCValAssign::SExt;
     268          15 :     else if (ArgFlags.isZExt())
     269             :         LocInfo = CCValAssign::ZExt;
     270             :     else
     271             :         LocInfo = CCValAssign::AExt;
     272             :   }
     273             : 
     274        2081 :   if (LocVT == MVT::i1 ||
     275             :       LocVT == MVT::i16) {
     276         620 :     if (ArgFlags.isSExt() || ArgFlags.isZExt()) {
     277             :       LocVT = MVT::i32;
     278           8 :       if (ArgFlags.isSExt())
     279             :             LocInfo = CCValAssign::SExt;
     280           4 :       else if (ArgFlags.isZExt())
     281             :             LocInfo = CCValAssign::ZExt;
     282             :       else
     283             :             LocInfo = CCValAssign::AExt;
     284             :     }
     285             :   }
     286             : 
     287        1542 :   if (LocVT == MVT::i32 ||
     288        1012 :       LocVT == MVT::f32 ||
     289         708 :       LocVT == MVT::i16 ||
     290         544 :       LocVT == MVT::f16 ||
     291        2553 :       LocVT == MVT::v2i16 ||
     292             :       LocVT == MVT::v2f16) {
     293             :     static const MCPhysReg RegList1[] = {
     294             :       AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
     295             :     };
     296        1651 :     if (unsigned Reg = State.AllocateReg(RegList1)) {
     297        3284 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     298        1642 :       return false;
     299             :     }
     300             :   }
     301             : 
     302         287 :   if (LocVT == MVT::i64 ||
     303         259 :       LocVT == MVT::f64 ||
     304         243 :       LocVT == MVT::v2i32 ||
     305         203 :       LocVT == MVT::v2f32 ||
     306         179 :       LocVT == MVT::v4i32 ||
     307         177 :       LocVT == MVT::v4f32 ||
     308         153 :       LocVT == MVT::v8i32 ||
     309         153 :       LocVT == MVT::v8f32 ||
     310          99 :       LocVT == MVT::v16i32 ||
     311          99 :       LocVT == MVT::v16f32 ||
     312         448 :       LocVT == MVT::v2i64 ||
     313             :       LocVT == MVT::v2f64) {
     314         430 :     if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
     315             :         return false;
     316             :   }
     317             : 
     318             :   return true;  // CC didn't match.
     319             : }
     320             : 
     321             : 
     322        1865 : static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
     323             :                             MVT LocVT, CCValAssign::LocInfo LocInfo,
     324             :                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
     325             : 
     326        1865 :   if (LocVT == MVT::i32) {
     327             :     static const MCPhysReg RegList1[] = {
     328             :       AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
     329             :     };
     330         161 :     if (unsigned Reg = State.AllocateReg(RegList1)) {
     331         322 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     332         161 :       return false;
     333             :     }
     334             :   }
     335             : 
     336        1704 :   if (LocVT == MVT::f32 ||
     337             :       LocVT == MVT::f16) {
     338             :     static const MCPhysReg RegList2[] = {
     339             :       AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
     340             :     };
     341        1704 :     if (unsigned Reg = State.AllocateReg(RegList2)) {
     342        3408 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     343        1704 :       return false;
     344             :     }
     345             :   }
     346             : 
     347             :   return true;  // CC didn't match.
     348             : }

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