LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenDAGISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 446 469 95.1 %
Date: 2017-09-14 15:23:50 Functions: 4 4 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* DAG Instruction Selector for the AMDGPU target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : // *** NOTE: This file is #included into the middle of the target
      10             : // *** instruction selector class.  These functions are really methods.
      11             : 
      12             : // The main instruction selector code.
      13             : void SelectCode(SDNode *N) {
      14             :   // Some target values are emitted as 2 bytes, TARGET_VAL handles
      15             :   // this.
      16             :   #define TARGET_VAL(X) X & 255, unsigned(X) >> 8
      17             :   static const unsigned char MatcherTable[] = {
      18             : /*0*/       OPC_SwitchOpcode /*186 cases */, 72|128,27/*3528*/, TARGET_VAL(ISD::LOAD),// ->3533
      19             : /*5*/         OPC_RecordMemRef,
      20             : /*6*/         OPC_RecordNode, // #0 = 'ld' chained node
      21             : /*7*/         OPC_Scope, 13|128,13/*1677*/, /*->1687*/ // 7 children in Scope
      22             : /*10*/          OPC_RecordChild1, // #1 = $SMRDImm:sbase:offset
      23             : /*11*/          OPC_CheckPredicate, 0, // Predicate_unindexedload
      24             : /*13*/          OPC_Scope, 66, /*->81*/ // 35 children in Scope
      25             : /*15*/            OPC_CheckPredicate, 1, // Predicate_load
      26             : /*17*/            OPC_CheckPredicate, 2, // Predicate_smrd_load
      27             : /*19*/            OPC_CheckType, MVT::i32,
      28             : /*21*/            OPC_Scope, 38, /*->61*/ // 2 children in Scope
      29             : /*23*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
      30             : /*25*/              OPC_Scope, 16, /*->43*/ // 2 children in Scope
      31             : /*27*/                OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectSMRDImm:$ #2 #3
      32             : /*30*/                OPC_EmitMergeInputChains1_0,
      33             : /*31*/                OPC_EmitInteger, MVT::i1, 0, 
      34             : /*34*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
      35             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
      36             :                       // Src: (ld:i32 (SMRDImm:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
      37             :                       // Dst: (S_LOAD_DWORD_IMM:i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
      38             : /*43*/              /*Scope*/ 16, /*->60*/
      39             : /*44*/                OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectSMRDSgpr:$ #2 #3
      40             : /*47*/                OPC_EmitMergeInputChains1_0,
      41             : /*48*/                OPC_EmitInteger, MVT::i1, 0, 
      42             : /*51*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORD_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
      43             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
      44             :                       // Src: (ld:i32 (SMRDSgpr:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
      45             :                       // Dst: (S_LOAD_DWORD_SGPR:i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
      46             : /*60*/              0, /*End of Scope*/
      47             : /*61*/            /*Scope*/ 18, /*->80*/
      48             : /*62*/              OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() ==SISubtarget::SEA_ISLANDS)
      49             : /*64*/              OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectSMRDImm32:$ #2 #3
      50             : /*67*/              OPC_EmitMergeInputChains1_0,
      51             : /*68*/              OPC_EmitInteger, MVT::i1, 0, 
      52             : /*71*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM_ci), 0|OPFL_Chain|OPFL_MemRefs,
      53             :                         MVT::i32, 3/*#Ops*/, 2, 3, 4, 
      54             :                     // Src: (ld:i32 (SMRDImm32:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
      55             :                     // Dst: (S_LOAD_DWORD_IMM_ci:i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
      56             : /*80*/            0, /*End of Scope*/
      57             : /*81*/          /*Scope*/ 27, /*->109*/
      58             : /*82*/            OPC_CheckPredicate, 3, // Predicate_az_extload
      59             : /*84*/            OPC_CheckPredicate, 4, // Predicate_az_extloadi8
      60             : /*86*/            OPC_CheckPredicate, 5, // Predicate_mubuf_az_extloadi8
      61             : /*88*/            OPC_CheckType, MVT::i32,
      62             : /*90*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
      63             : /*92*/            OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
      64             : /*95*/            OPC_EmitMergeInputChains1_0,
      65             : /*96*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
      66             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
      67             :                   // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_mubuf_az_extloadi8>> - Complexity = 28
      68             :                   // Dst: (BUFFER_LOAD_UBYTE_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
      69             : /*109*/         /*Scope*/ 27, /*->137*/
      70             : /*110*/           OPC_CheckPredicate, 6, // Predicate_sextload
      71             : /*112*/           OPC_CheckPredicate, 4, // Predicate_sextloadi8
      72             : /*114*/           OPC_CheckPredicate, 5, // Predicate_mubuf_sextloadi8
      73             : /*116*/           OPC_CheckType, MVT::i32,
      74             : /*118*/           OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
      75             : /*120*/           OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
      76             : /*123*/           OPC_EmitMergeInputChains1_0,
      77             : /*124*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
      78             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
      79             :                   // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_mubuf_sextloadi8>> - Complexity = 28
      80             :                   // Dst: (BUFFER_LOAD_SBYTE_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
      81             : /*137*/         /*Scope*/ 27, /*->165*/
      82             : /*138*/           OPC_CheckPredicate, 3, // Predicate_az_extload
      83             : /*140*/           OPC_CheckPredicate, 7, // Predicate_az_extloadi16
      84             : /*142*/           OPC_CheckPredicate, 5, // Predicate_mubuf_az_extloadi16
      85             : /*144*/           OPC_CheckType, MVT::i32,
      86             : /*146*/           OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
      87             : /*148*/           OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
      88             : /*151*/           OPC_EmitMergeInputChains1_0,
      89             : /*152*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
      90             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
      91             :                   // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_mubuf_az_extloadi16>> - Complexity = 28
      92             :                   // Dst: (BUFFER_LOAD_USHORT_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
      93             : /*165*/         /*Scope*/ 27, /*->193*/
      94             : /*166*/           OPC_CheckPredicate, 6, // Predicate_sextload
      95             : /*168*/           OPC_CheckPredicate, 7, // Predicate_sextloadi16
      96             : /*170*/           OPC_CheckPredicate, 5, // Predicate_mubuf_sextloadi16
      97             : /*172*/           OPC_CheckType, MVT::i32,
      98             : /*174*/           OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
      99             : /*176*/           OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
     100             : /*179*/           OPC_EmitMergeInputChains1_0,
     101             : /*180*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
     102             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     103             :                   // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_mubuf_sextloadi16>> - Complexity = 28
     104             :                   // Dst: (BUFFER_LOAD_SSHORT_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     105             : /*193*/         /*Scope*/ 48, /*->242*/
     106             : /*194*/           OPC_CheckPredicate, 1, // Predicate_load
     107             : /*196*/           OPC_CheckPredicate, 5, // Predicate_mubuf_load
     108             : /*198*/           OPC_SwitchType /*2 cases */, 19, MVT::i32,// ->220
     109             : /*201*/             OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     110             : /*203*/             OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
     111             : /*206*/             OPC_EmitMergeInputChains1_0,
     112             : /*207*/             OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
     113             :                         MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     114             :                     // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 28
     115             :                     // Dst: (BUFFER_LOAD_DWORD_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     116             : /*220*/           /*SwitchType*/ 19, MVT::Untyped,// ->241
     117             : /*222*/             OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     118             : /*224*/             OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
     119             : /*227*/             OPC_EmitMergeInputChains1_0,
     120             : /*228*/             OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
     121             :                         MVT::Untyped, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     122             :                     // Src: (ld:Untyped (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 28
     123             :                     // Dst: (BUFFER_LOAD_DWORDX3_ADDR64:Untyped i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     124             : /*241*/           0, // EndSwitchType
     125             : /*242*/         /*Scope*/ 27, /*->270*/
     126             : /*243*/           OPC_CheckPredicate, 6, // Predicate_sextload
     127             : /*245*/           OPC_CheckPredicate, 4, // Predicate_sextloadi8
     128             : /*247*/           OPC_CheckPredicate, 8, // Predicate_sextloadi8_constant
     129             : /*249*/           OPC_CheckType, MVT::i32,
     130             : /*251*/           OPC_CheckPatternPredicate, 3, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
     131             : /*253*/           OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
     132             : /*256*/           OPC_EmitMergeInputChains1_0,
     133             : /*257*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
     134             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     135             :                   // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>> - Complexity = 28
     136             :                   // Dst: (BUFFER_LOAD_SBYTE_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     137             : /*270*/         /*Scope*/ 27, /*->298*/
     138             : /*271*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     139             : /*273*/           OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     140             : /*275*/           OPC_CheckPredicate, 8, // Predicate_az_extloadi8_constant
     141             : /*277*/           OPC_CheckType, MVT::i32,
     142             : /*279*/           OPC_CheckPatternPredicate, 3, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
     143             : /*281*/           OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
     144             : /*284*/           OPC_EmitMergeInputChains1_0,
     145             : /*285*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
     146             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     147             :                   // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_constant>> - Complexity = 28
     148             :                   // Dst: (BUFFER_LOAD_UBYTE_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     149             : /*298*/         /*Scope*/ 27, /*->326*/
     150             : /*299*/           OPC_CheckPredicate, 6, // Predicate_sextload
     151             : /*301*/           OPC_CheckPredicate, 7, // Predicate_sextloadi16
     152             : /*303*/           OPC_CheckPredicate, 8, // Predicate_sextloadi16_constant
     153             : /*305*/           OPC_CheckType, MVT::i32,
     154             : /*307*/           OPC_CheckPatternPredicate, 3, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
     155             : /*309*/           OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
     156             : /*312*/           OPC_EmitMergeInputChains1_0,
     157             : /*313*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
     158             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     159             :                   // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>> - Complexity = 28
     160             :                   // Dst: (BUFFER_LOAD_SSHORT_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     161             : /*326*/         /*Scope*/ 27, /*->354*/
     162             : /*327*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     163             : /*329*/           OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     164             : /*331*/           OPC_CheckPredicate, 8, // Predicate_az_extloadi16_constant
     165             : /*333*/           OPC_CheckType, MVT::i32,
     166             : /*335*/           OPC_CheckPatternPredicate, 3, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
     167             : /*337*/           OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
     168             : /*340*/           OPC_EmitMergeInputChains1_0,
     169             : /*341*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
     170             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     171             :                   // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_constant>> - Complexity = 28
     172             :                   // Dst: (BUFFER_LOAD_USHORT_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     173             : /*354*/         /*Scope*/ 35, /*->390*/
     174             : /*355*/           OPC_CheckPredicate, 6, // Predicate_sextload
     175             : /*357*/           OPC_CheckPredicate, 4, // Predicate_sextloadi8
     176             : /*359*/           OPC_CheckPredicate, 9, // Predicate_sextloadi8_private
     177             : /*361*/           OPC_CheckType, MVT::i32,
     178             : /*363*/           OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     179             : /*365*/           OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
     180             : /*368*/           OPC_EmitMergeInputChains1_0,
     181             : /*369*/           OPC_EmitInteger, MVT::i1, 0, 
     182             : /*372*/           OPC_EmitInteger, MVT::i1, 0, 
     183             : /*375*/           OPC_EmitInteger, MVT::i1, 0, 
     184             : /*378*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     185             :                       MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     186             :                   // Src: (ld:i32 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> - Complexity = 27
     187             :                   // Dst: (BUFFER_LOAD_SBYTE_OFFSET:i32 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     188             : /*390*/         /*Scope*/ 35, /*->426*/
     189             : /*391*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     190             : /*393*/           OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     191             : /*395*/           OPC_CheckPredicate, 9, // Predicate_extloadi8_private
     192             : /*397*/           OPC_CheckType, MVT::i32,
     193             : /*399*/           OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     194             : /*401*/           OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
     195             : /*404*/           OPC_EmitMergeInputChains1_0,
     196             : /*405*/           OPC_EmitInteger, MVT::i1, 0, 
     197             : /*408*/           OPC_EmitInteger, MVT::i1, 0, 
     198             : /*411*/           OPC_EmitInteger, MVT::i1, 0, 
     199             : /*414*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     200             :                       MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     201             :                   // Src: (ld:i32 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_extloadi8_private>> - Complexity = 27
     202             :                   // Dst: (BUFFER_LOAD_UBYTE_OFFSET:i32 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     203             : /*426*/         /*Scope*/ 35, /*->462*/
     204             : /*427*/           OPC_CheckPredicate, 6, // Predicate_sextload
     205             : /*429*/           OPC_CheckPredicate, 4, // Predicate_sextloadi8
     206             : /*431*/           OPC_CheckPredicate, 9, // Predicate_sextloadi8_private
     207             : /*433*/           OPC_CheckType, MVT::i16,
     208             : /*435*/           OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     209             : /*437*/           OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
     210             : /*440*/           OPC_EmitMergeInputChains1_0,
     211             : /*441*/           OPC_EmitInteger, MVT::i1, 0, 
     212             : /*444*/           OPC_EmitInteger, MVT::i1, 0, 
     213             : /*447*/           OPC_EmitInteger, MVT::i1, 0, 
     214             : /*450*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     215             :                       MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     216             :                   // Src: (ld:i16 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> - Complexity = 27
     217             :                   // Dst: (BUFFER_LOAD_SBYTE_OFFSET:i16 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     218             : /*462*/         /*Scope*/ 35, /*->498*/
     219             : /*463*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     220             : /*465*/           OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     221             : /*467*/           OPC_CheckPredicate, 9, // Predicate_extloadi8_private
     222             : /*469*/           OPC_CheckType, MVT::i16,
     223             : /*471*/           OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     224             : /*473*/           OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
     225             : /*476*/           OPC_EmitMergeInputChains1_0,
     226             : /*477*/           OPC_EmitInteger, MVT::i1, 0, 
     227             : /*480*/           OPC_EmitInteger, MVT::i1, 0, 
     228             : /*483*/           OPC_EmitInteger, MVT::i1, 0, 
     229             : /*486*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     230             :                       MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     231             :                   // Src: (ld:i16 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_extloadi8_private>> - Complexity = 27
     232             :                   // Dst: (BUFFER_LOAD_UBYTE_OFFSET:i16 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     233             : /*498*/         /*Scope*/ 35, /*->534*/
     234             : /*499*/           OPC_CheckPredicate, 6, // Predicate_sextload
     235             : /*501*/           OPC_CheckPredicate, 7, // Predicate_sextloadi16
     236             : /*503*/           OPC_CheckPredicate, 9, // Predicate_sextloadi16_private
     237             : /*505*/           OPC_CheckType, MVT::i32,
     238             : /*507*/           OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     239             : /*509*/           OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
     240             : /*512*/           OPC_EmitMergeInputChains1_0,
     241             : /*513*/           OPC_EmitInteger, MVT::i1, 0, 
     242             : /*516*/           OPC_EmitInteger, MVT::i1, 0, 
     243             : /*519*/           OPC_EmitInteger, MVT::i1, 0, 
     244             : /*522*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     245             :                       MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     246             :                   // Src: (ld:i32 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> - Complexity = 27
     247             :                   // Dst: (BUFFER_LOAD_SSHORT_OFFSET:i32 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     248             : /*534*/         /*Scope*/ 35, /*->570*/
     249             : /*535*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     250             : /*537*/           OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     251             : /*539*/           OPC_CheckPredicate, 9, // Predicate_extloadi16_private
     252             : /*541*/           OPC_CheckType, MVT::i32,
     253             : /*543*/           OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     254             : /*545*/           OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
     255             : /*548*/           OPC_EmitMergeInputChains1_0,
     256             : /*549*/           OPC_EmitInteger, MVT::i1, 0, 
     257             : /*552*/           OPC_EmitInteger, MVT::i1, 0, 
     258             : /*555*/           OPC_EmitInteger, MVT::i1, 0, 
     259             : /*558*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     260             :                       MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     261             :                   // Src: (ld:i32 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_extloadi16_private>> - Complexity = 27
     262             :                   // Dst: (BUFFER_LOAD_USHORT_OFFSET:i32 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     263             : /*570*/         /*Scope*/ 64, /*->635*/
     264             : /*571*/           OPC_CheckPredicate, 1, // Predicate_load
     265             : /*573*/           OPC_CheckPredicate, 9, // Predicate_load_private
     266             : /*575*/           OPC_SwitchType /*2 cases */, 27, MVT::i16,// ->605
     267             : /*578*/             OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     268             : /*580*/             OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
     269             : /*583*/             OPC_EmitMergeInputChains1_0,
     270             : /*584*/             OPC_EmitInteger, MVT::i1, 0, 
     271             : /*587*/             OPC_EmitInteger, MVT::i1, 0, 
     272             : /*590*/             OPC_EmitInteger, MVT::i1, 0, 
     273             : /*593*/             OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     274             :                         MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     275             :                     // Src: (ld:i16 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 27
     276             :                     // Dst: (BUFFER_LOAD_USHORT_OFFSET:i16 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     277             : /*605*/           /*SwitchType*/ 27, MVT::i32,// ->634
     278             : /*607*/             OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     279             : /*609*/             OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
     280             : /*612*/             OPC_EmitMergeInputChains1_0,
     281             : /*613*/             OPC_EmitInteger, MVT::i1, 0, 
     282             : /*616*/             OPC_EmitInteger, MVT::i1, 0, 
     283             : /*619*/             OPC_EmitInteger, MVT::i1, 0, 
     284             : /*622*/             OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     285             :                         MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     286             :                     // Src: (ld:i32 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 27
     287             :                     // Dst: (BUFFER_LOAD_DWORD_OFFSET:i32 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     288             : /*634*/           0, // EndSwitchType
     289             : /*635*/         /*Scope*/ 26, /*->662*/
     290             : /*636*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     291             : /*638*/           OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     292             : /*640*/           OPC_CheckPredicate, 5, // Predicate_mubuf_az_extloadi8
     293             : /*642*/           OPC_CheckType, MVT::i32,
     294             : /*644*/           OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     295             : /*646*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     296             : /*649*/           OPC_EmitMergeInputChains1_0,
     297             : /*650*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     298             :                       MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     299             :                   // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_mubuf_az_extloadi8>> - Complexity = 25
     300             :                   // Dst: (BUFFER_LOAD_UBYTE_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     301             : /*662*/         /*Scope*/ 26, /*->689*/
     302             : /*663*/           OPC_CheckPredicate, 6, // Predicate_sextload
     303             : /*665*/           OPC_CheckPredicate, 4, // Predicate_sextloadi8
     304             : /*667*/           OPC_CheckPredicate, 5, // Predicate_mubuf_sextloadi8
     305             : /*669*/           OPC_CheckType, MVT::i32,
     306             : /*671*/           OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     307             : /*673*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     308             : /*676*/           OPC_EmitMergeInputChains1_0,
     309             : /*677*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     310             :                       MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     311             :                   // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_mubuf_sextloadi8>> - Complexity = 25
     312             :                   // Dst: (BUFFER_LOAD_SBYTE_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     313             : /*689*/         /*Scope*/ 26, /*->716*/
     314             : /*690*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     315             : /*692*/           OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     316             : /*694*/           OPC_CheckPredicate, 5, // Predicate_mubuf_az_extloadi16
     317             : /*696*/           OPC_CheckType, MVT::i32,
     318             : /*698*/           OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     319             : /*700*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     320             : /*703*/           OPC_EmitMergeInputChains1_0,
     321             : /*704*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     322             :                       MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     323             :                   // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_mubuf_az_extloadi16>> - Complexity = 25
     324             :                   // Dst: (BUFFER_LOAD_USHORT_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     325             : /*716*/         /*Scope*/ 26, /*->743*/
     326             : /*717*/           OPC_CheckPredicate, 6, // Predicate_sextload
     327             : /*719*/           OPC_CheckPredicate, 7, // Predicate_sextloadi16
     328             : /*721*/           OPC_CheckPredicate, 5, // Predicate_mubuf_sextloadi16
     329             : /*723*/           OPC_CheckType, MVT::i32,
     330             : /*725*/           OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     331             : /*727*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     332             : /*730*/           OPC_EmitMergeInputChains1_0,
     333             : /*731*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     334             :                       MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     335             :                   // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_mubuf_sextloadi16>> - Complexity = 25
     336             :                   // Dst: (BUFFER_LOAD_SSHORT_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     337             : /*743*/         /*Scope*/ 46, /*->790*/
     338             : /*744*/           OPC_CheckPredicate, 1, // Predicate_load
     339             : /*746*/           OPC_CheckPredicate, 5, // Predicate_mubuf_load
     340             : /*748*/           OPC_SwitchType /*2 cases */, 18, MVT::i32,// ->769
     341             : /*751*/             OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     342             : /*753*/             OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     343             : /*756*/             OPC_EmitMergeInputChains1_0,
     344             : /*757*/             OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     345             :                         MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     346             :                     // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 25
     347             :                     // Dst: (BUFFER_LOAD_DWORD_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     348             : /*769*/           /*SwitchType*/ 18, MVT::Untyped,// ->789
     349             : /*771*/             OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     350             : /*773*/             OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     351             : /*776*/             OPC_EmitMergeInputChains1_0,
     352             : /*777*/             OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     353             :                         MVT::Untyped, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     354             :                     // Src: (ld:Untyped (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 25
     355             :                     // Dst: (BUFFER_LOAD_DWORDX3_OFFSET:Untyped v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
     356             : /*789*/           0, // EndSwitchType
     357             : /*790*/         /*Scope*/ 26, /*->817*/
     358             : /*791*/           OPC_CheckPredicate, 6, // Predicate_sextload
     359             : /*793*/           OPC_CheckPredicate, 4, // Predicate_sextloadi8
     360             : /*795*/           OPC_CheckPredicate, 8, // Predicate_sextloadi8_constant
     361             : /*797*/           OPC_CheckType, MVT::i16,
     362             : /*799*/           OPC_CheckPatternPredicate, 4, // (Subtarget->has16BitInsts())
     363             : /*801*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     364             : /*804*/           OPC_EmitMergeInputChains1_0,
     365             : /*805*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     366             :                       MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     367             :                   // Src: (ld:i16 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>> - Complexity = 25
     368             :                   // Dst: (BUFFER_LOAD_SBYTE_OFFSET:i16 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     369             : /*817*/         /*Scope*/ 26, /*->844*/
     370             : /*818*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     371             : /*820*/           OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     372             : /*822*/           OPC_CheckPredicate, 8, // Predicate_az_extloadi8_constant
     373             : /*824*/           OPC_CheckType, MVT::i16,
     374             : /*826*/           OPC_CheckPatternPredicate, 4, // (Subtarget->has16BitInsts())
     375             : /*828*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     376             : /*831*/           OPC_EmitMergeInputChains1_0,
     377             : /*832*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     378             :                       MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     379             :                   // Src: (ld:i16 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_constant>> - Complexity = 25
     380             :                   // Dst: (BUFFER_LOAD_UBYTE_OFFSET:i16 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     381             : /*844*/         /*Scope*/ 26, /*->871*/
     382             : /*845*/           OPC_CheckPredicate, 6, // Predicate_sextload
     383             : /*847*/           OPC_CheckPredicate, 4, // Predicate_sextloadi8
     384             : /*849*/           OPC_CheckPredicate, 5, // Predicate_mubuf_sextloadi8
     385             : /*851*/           OPC_CheckType, MVT::i16,
     386             : /*853*/           OPC_CheckPatternPredicate, 4, // (Subtarget->has16BitInsts())
     387             : /*855*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     388             : /*858*/           OPC_EmitMergeInputChains1_0,
     389             : /*859*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     390             :                       MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     391             :                   // Src: (ld:i16 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_mubuf_sextloadi8>> - Complexity = 25
     392             :                   // Dst: (BUFFER_LOAD_SBYTE_OFFSET:i16 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     393             : /*871*/         /*Scope*/ 26, /*->898*/
     394             : /*872*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     395             : /*874*/           OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     396             : /*876*/           OPC_CheckPredicate, 5, // Predicate_mubuf_az_extloadi8
     397             : /*878*/           OPC_CheckType, MVT::i16,
     398             : /*880*/           OPC_CheckPatternPredicate, 4, // (Subtarget->has16BitInsts())
     399             : /*882*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     400             : /*885*/           OPC_EmitMergeInputChains1_0,
     401             : /*886*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     402             :                       MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     403             :                   // Src: (ld:i16 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_mubuf_az_extloadi8>> - Complexity = 25
     404             :                   // Dst: (BUFFER_LOAD_UBYTE_OFFSET:i16 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     405             : /*898*/         /*Scope*/ 24, /*->923*/
     406             : /*899*/           OPC_CheckPredicate, 1, // Predicate_load
     407             : /*901*/           OPC_CheckPredicate, 5, // Predicate_mubuf_load
     408             : /*903*/           OPC_CheckType, MVT::i16,
     409             : /*905*/           OPC_CheckPatternPredicate, 4, // (Subtarget->has16BitInsts())
     410             : /*907*/           OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
     411             : /*910*/           OPC_EmitMergeInputChains1_0,
     412             : /*911*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
     413             :                       MVT::i16, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
     414             :                   // Src: (ld:i16 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 25
     415             :                   // Dst: (BUFFER_LOAD_USHORT_OFFSET:i16 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
     416             : /*923*/         /*Scope*/ 36, /*->960*/
     417             : /*924*/           OPC_CheckPredicate, 6, // Predicate_sextload
     418             : /*926*/           OPC_CheckPredicate, 4, // Predicate_sextloadi8
     419             : /*928*/           OPC_CheckPredicate, 9, // Predicate_sextloadi8_private
     420             : /*930*/           OPC_CheckType, MVT::i32,
     421             : /*932*/           OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     422             : /*934*/           OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
     423             : /*937*/           OPC_EmitMergeInputChains1_0,
     424             : /*938*/           OPC_EmitInteger, MVT::i1, 0, 
     425             : /*941*/           OPC_EmitInteger, MVT::i1, 0, 
     426             : /*944*/           OPC_EmitInteger, MVT::i1, 0, 
     427             : /*947*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
     428             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     429             :                   // Src: (ld:i32 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> - Complexity = 19
     430             :                   // Dst: (BUFFER_LOAD_SBYTE_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     431             : /*960*/         /*Scope*/ 36, /*->997*/
     432             : /*961*/           OPC_CheckPredicate, 3, // Predicate_az_extload
     433             : /*963*/           OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     434             : /*965*/           OPC_CheckPredicate, 9, // Predicate_extloadi8_private
     435             : /*967*/           OPC_CheckType, MVT::i32,
     436             : /*969*/           OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     437             : /*971*/           OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
     438             : /*974*/           OPC_EmitMergeInputChains1_0,
     439             : /*975*/           OPC_EmitInteger, MVT::i1, 0, 
     440             : /*978*/           OPC_EmitInteger, MVT::i1, 0, 
     441             : /*981*/           OPC_EmitInteger, MVT::i1, 0, 
     442             : /*984*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
     443             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     444             :                   // Src: (ld:i32 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_extloadi8_private>> - Complexity = 19
     445             :                   // Dst: (BUFFER_LOAD_UBYTE_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     446             : /*997*/         /*Scope*/ 36, /*->1034*/
     447             : /*998*/           OPC_CheckPredicate, 6, // Predicate_sextload
     448             : /*1000*/          OPC_CheckPredicate, 4, // Predicate_sextloadi8
     449             : /*1002*/          OPC_CheckPredicate, 9, // Predicate_sextloadi8_private
     450             : /*1004*/          OPC_CheckType, MVT::i16,
     451             : /*1006*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     452             : /*1008*/          OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
     453             : /*1011*/          OPC_EmitMergeInputChains1_0,
     454             : /*1012*/          OPC_EmitInteger, MVT::i1, 0, 
     455             : /*1015*/          OPC_EmitInteger, MVT::i1, 0, 
     456             : /*1018*/          OPC_EmitInteger, MVT::i1, 0, 
     457             : /*1021*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
     458             :                       MVT::i16, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     459             :                   // Src: (ld:i16 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> - Complexity = 19
     460             :                   // Dst: (BUFFER_LOAD_SBYTE_OFFEN:i16 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     461             : /*1034*/        /*Scope*/ 36, /*->1071*/
     462             : /*1035*/          OPC_CheckPredicate, 3, // Predicate_az_extload
     463             : /*1037*/          OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     464             : /*1039*/          OPC_CheckPredicate, 9, // Predicate_extloadi8_private
     465             : /*1041*/          OPC_CheckType, MVT::i16,
     466             : /*1043*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     467             : /*1045*/          OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
     468             : /*1048*/          OPC_EmitMergeInputChains1_0,
     469             : /*1049*/          OPC_EmitInteger, MVT::i1, 0, 
     470             : /*1052*/          OPC_EmitInteger, MVT::i1, 0, 
     471             : /*1055*/          OPC_EmitInteger, MVT::i1, 0, 
     472             : /*1058*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
     473             :                       MVT::i16, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     474             :                   // Src: (ld:i16 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_extloadi8_private>> - Complexity = 19
     475             :                   // Dst: (BUFFER_LOAD_UBYTE_OFFEN:i16 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     476             : /*1071*/        /*Scope*/ 36, /*->1108*/
     477             : /*1072*/          OPC_CheckPredicate, 6, // Predicate_sextload
     478             : /*1074*/          OPC_CheckPredicate, 7, // Predicate_sextloadi16
     479             : /*1076*/          OPC_CheckPredicate, 9, // Predicate_sextloadi16_private
     480             : /*1078*/          OPC_CheckType, MVT::i32,
     481             : /*1080*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     482             : /*1082*/          OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
     483             : /*1085*/          OPC_EmitMergeInputChains1_0,
     484             : /*1086*/          OPC_EmitInteger, MVT::i1, 0, 
     485             : /*1089*/          OPC_EmitInteger, MVT::i1, 0, 
     486             : /*1092*/          OPC_EmitInteger, MVT::i1, 0, 
     487             : /*1095*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
     488             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     489             :                   // Src: (ld:i32 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> - Complexity = 19
     490             :                   // Dst: (BUFFER_LOAD_SSHORT_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     491             : /*1108*/        /*Scope*/ 36, /*->1145*/
     492             : /*1109*/          OPC_CheckPredicate, 3, // Predicate_az_extload
     493             : /*1111*/          OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     494             : /*1113*/          OPC_CheckPredicate, 9, // Predicate_extloadi16_private
     495             : /*1115*/          OPC_CheckType, MVT::i32,
     496             : /*1117*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     497             : /*1119*/          OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
     498             : /*1122*/          OPC_EmitMergeInputChains1_0,
     499             : /*1123*/          OPC_EmitInteger, MVT::i1, 0, 
     500             : /*1126*/          OPC_EmitInteger, MVT::i1, 0, 
     501             : /*1129*/          OPC_EmitInteger, MVT::i1, 0, 
     502             : /*1132*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
     503             :                       MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     504             :                   // Src: (ld:i32 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_extloadi16_private>> - Complexity = 19
     505             :                   // Dst: (BUFFER_LOAD_USHORT_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     506             : /*1145*/        /*Scope*/ 88, /*->1234*/
     507             : /*1146*/          OPC_CheckPredicate, 1, // Predicate_load
     508             : /*1148*/          OPC_CheckPredicate, 9, // Predicate_load_private
     509             : /*1150*/          OPC_SwitchType /*2 cases */, 28, MVT::i16,// ->1181
     510             : /*1153*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     511             : /*1155*/            OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
     512             : /*1158*/            OPC_EmitMergeInputChains1_0,
     513             : /*1159*/            OPC_EmitInteger, MVT::i1, 0, 
     514             : /*1162*/            OPC_EmitInteger, MVT::i1, 0, 
     515             : /*1165*/            OPC_EmitInteger, MVT::i1, 0, 
     516             : /*1168*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
     517             :                         MVT::i16, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     518             :                     // Src: (ld:i16 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 19
     519             :                     // Dst: (BUFFER_LOAD_USHORT_OFFEN:i16 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     520             : /*1181*/          /*SwitchType*/ 50, MVT::i32,// ->1233
     521             : /*1183*/            OPC_Scope, 28, /*->1213*/ // 2 children in Scope
     522             : /*1185*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     523             : /*1187*/              OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
     524             : /*1190*/              OPC_EmitMergeInputChains1_0,
     525             : /*1191*/              OPC_EmitInteger, MVT::i1, 0, 
     526             : /*1194*/              OPC_EmitInteger, MVT::i1, 0, 
     527             : /*1197*/              OPC_EmitInteger, MVT::i1, 0, 
     528             : /*1200*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
     529             :                           MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
     530             :                       // Src: (ld:i32 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 19
     531             :                       // Dst: (BUFFER_LOAD_DWORD_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
     532             : /*1213*/            /*Scope*/ 18, /*->1232*/
     533             : /*1214*/              OPC_CheckPatternPredicate, 5, // (Subtarget->getGeneration() <= R600Subtarget::NORTHERN_ISLANDS)
     534             : /*1216*/              OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectADDRIndirect:$addr #2 #3
     535             : /*1219*/              OPC_EmitMergeInputChains1_0,
     536             : /*1220*/              OPC_EmitInteger, MVT::i32, 0, 
     537             : /*1223*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::R600_RegisterLoad), 0|OPFL_Chain|OPFL_MemRefs,
     538             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     539             :                       // Src: (ld:i32 ADDRIndirect:iPTR:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 13
     540             :                       // Dst: (R600_RegisterLoad:i32 FRAMEri:iPTR:$addr, 0:i32)
     541             : /*1232*/            0, /*End of Scope*/
     542             : /*1233*/          0, // EndSwitchType
     543             : /*1234*/        /*Scope*/ 66|128,3/*450*/, /*->1686*/
     544             : /*1236*/          OPC_CheckChild1Type, MVT::i32,
     545             : /*1238*/          OPC_CheckType, MVT::i32,
     546             : /*1240*/          OPC_Scope, 50, /*->1292*/ // 12 children in Scope
     547             : /*1242*/            OPC_CheckPredicate, 3, // Predicate_az_extload
     548             : /*1244*/            OPC_Scope, 22, /*->1268*/ // 2 children in Scope
     549             : /*1246*/              OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     550             : /*1248*/              OPC_CheckPredicate, 10, // Predicate_vtx_id3_az_extloadi8
     551             : /*1250*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     552             : /*1252*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     553             : /*1255*/              OPC_EmitMergeInputChains1_0,
     554             : /*1256*/              OPC_EmitInteger, MVT::i8, 3, 
     555             : /*1259*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_8_eg), 0|OPFL_Chain|OPFL_MemRefs,
     556             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     557             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_vtx_id3_az_extloadi8>> - Complexity = 13
     558             :                       // Dst: (VTX_READ_8_eg:i32 MEMxi:i32:$src_gpr, 3:i8)
     559             : /*1268*/            /*Scope*/ 22, /*->1291*/
     560             : /*1269*/              OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     561             : /*1271*/              OPC_CheckPredicate, 10, // Predicate_vtx_id3_az_extloadi16
     562             : /*1273*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     563             : /*1275*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     564             : /*1278*/              OPC_EmitMergeInputChains1_0,
     565             : /*1279*/              OPC_EmitInteger, MVT::i8, 3, 
     566             : /*1282*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_16_eg), 0|OPFL_Chain|OPFL_MemRefs,
     567             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     568             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_vtx_id3_az_extloadi16>> - Complexity = 13
     569             :                       // Dst: (VTX_READ_16_eg:i32 MEMxi:i32:$src_gpr, 3:i8)
     570             : /*1291*/            0, /*End of Scope*/
     571             : /*1292*/          /*Scope*/ 22, /*->1315*/
     572             : /*1293*/            OPC_CheckPredicate, 1, // Predicate_load
     573             : /*1295*/            OPC_CheckPredicate, 10, // Predicate_vtx_id3_load
     574             : /*1297*/            OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     575             : /*1299*/            OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     576             : /*1302*/            OPC_EmitMergeInputChains1_0,
     577             : /*1303*/            OPC_EmitInteger, MVT::i8, 3, 
     578             : /*1306*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_32_eg), 0|OPFL_Chain|OPFL_MemRefs,
     579             :                         MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     580             :                     // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id3_load>> - Complexity = 13
     581             :                     // Dst: (VTX_READ_32_eg:i32 MEMxi:i32:$src_gpr, 3:i8)
     582             : /*1315*/          /*Scope*/ 50, /*->1366*/
     583             : /*1316*/            OPC_CheckPredicate, 3, // Predicate_az_extload
     584             : /*1318*/            OPC_Scope, 22, /*->1342*/ // 2 children in Scope
     585             : /*1320*/              OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     586             : /*1322*/              OPC_CheckPredicate, 11, // Predicate_vtx_id2_az_extloadi8
     587             : /*1324*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     588             : /*1326*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     589             : /*1329*/              OPC_EmitMergeInputChains1_0,
     590             : /*1330*/              OPC_EmitInteger, MVT::i8, 2, 
     591             : /*1333*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_8_eg), 0|OPFL_Chain|OPFL_MemRefs,
     592             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     593             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_vtx_id2_az_extloadi8>> - Complexity = 13
     594             :                       // Dst: (VTX_READ_8_eg:i32 MEMxi:i32:$src_gpr, 2:i8)
     595             : /*1342*/            /*Scope*/ 22, /*->1365*/
     596             : /*1343*/              OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     597             : /*1345*/              OPC_CheckPredicate, 11, // Predicate_vtx_id2_az_extloadi16
     598             : /*1347*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     599             : /*1349*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     600             : /*1352*/              OPC_EmitMergeInputChains1_0,
     601             : /*1353*/              OPC_EmitInteger, MVT::i8, 2, 
     602             : /*1356*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_16_eg), 0|OPFL_Chain|OPFL_MemRefs,
     603             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     604             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_vtx_id2_az_extloadi16>> - Complexity = 13
     605             :                       // Dst: (VTX_READ_16_eg:i32 MEMxi:i32:$src_gpr, 2:i8)
     606             : /*1365*/            0, /*End of Scope*/
     607             : /*1366*/          /*Scope*/ 22, /*->1389*/
     608             : /*1367*/            OPC_CheckPredicate, 1, // Predicate_load
     609             : /*1369*/            OPC_CheckPredicate, 11, // Predicate_vtx_id2_load
     610             : /*1371*/            OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     611             : /*1373*/            OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     612             : /*1376*/            OPC_EmitMergeInputChains1_0,
     613             : /*1377*/            OPC_EmitInteger, MVT::i8, 2, 
     614             : /*1380*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_32_eg), 0|OPFL_Chain|OPFL_MemRefs,
     615             :                         MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     616             :                     // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id2_load>> - Complexity = 13
     617             :                     // Dst: (VTX_READ_32_eg:i32 MEMxi:i32:$src_gpr, 2:i8)
     618             : /*1389*/          /*Scope*/ 50, /*->1440*/
     619             : /*1390*/            OPC_CheckPredicate, 3, // Predicate_az_extload
     620             : /*1392*/            OPC_Scope, 22, /*->1416*/ // 2 children in Scope
     621             : /*1394*/              OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     622             : /*1396*/              OPC_CheckPredicate, 12, // Predicate_vtx_id1_az_extloadi8
     623             : /*1398*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     624             : /*1400*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     625             : /*1403*/              OPC_EmitMergeInputChains1_0,
     626             : /*1404*/              OPC_EmitInteger, MVT::i8, 1, 
     627             : /*1407*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_8_eg), 0|OPFL_Chain|OPFL_MemRefs,
     628             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     629             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_vtx_id1_az_extloadi8>> - Complexity = 13
     630             :                       // Dst: (VTX_READ_8_eg:i32 MEMxi:i32:$src_gpr, 1:i8)
     631             : /*1416*/            /*Scope*/ 22, /*->1439*/
     632             : /*1417*/              OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     633             : /*1419*/              OPC_CheckPredicate, 12, // Predicate_vtx_id1_az_extloadi16
     634             : /*1421*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     635             : /*1423*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     636             : /*1426*/              OPC_EmitMergeInputChains1_0,
     637             : /*1427*/              OPC_EmitInteger, MVT::i8, 1, 
     638             : /*1430*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_16_eg), 0|OPFL_Chain|OPFL_MemRefs,
     639             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     640             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_vtx_id1_az_extloadi16>> - Complexity = 13
     641             :                       // Dst: (VTX_READ_16_eg:i32 MEMxi:i32:$src_gpr, 1:i8)
     642             : /*1439*/            0, /*End of Scope*/
     643             : /*1440*/          /*Scope*/ 22, /*->1463*/
     644             : /*1441*/            OPC_CheckPredicate, 1, // Predicate_load
     645             : /*1443*/            OPC_CheckPredicate, 12, // Predicate_vtx_id1_load
     646             : /*1445*/            OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
     647             : /*1447*/            OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     648             : /*1450*/            OPC_EmitMergeInputChains1_0,
     649             : /*1451*/            OPC_EmitInteger, MVT::i8, 1, 
     650             : /*1454*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_32_eg), 0|OPFL_Chain|OPFL_MemRefs,
     651             :                         MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     652             :                     // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id1_load>> - Complexity = 13
     653             :                     // Dst: (VTX_READ_32_eg:i32 MEMxi:i32:$src_gpr, 1:i8)
     654             : /*1463*/          /*Scope*/ 50, /*->1514*/
     655             : /*1464*/            OPC_CheckPredicate, 3, // Predicate_az_extload
     656             : /*1466*/            OPC_Scope, 22, /*->1490*/ // 2 children in Scope
     657             : /*1468*/              OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     658             : /*1470*/              OPC_CheckPredicate, 10, // Predicate_vtx_id3_az_extloadi8
     659             : /*1472*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     660             : /*1474*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     661             : /*1477*/              OPC_EmitMergeInputChains1_0,
     662             : /*1478*/              OPC_EmitInteger, MVT::i8, 3, 
     663             : /*1481*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_8_cm), 0|OPFL_Chain|OPFL_MemRefs,
     664             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     665             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_vtx_id3_az_extloadi8>> - Complexity = 13
     666             :                       // Dst: (VTX_READ_8_cm:i32 MEMxi:i32:$src_gpr, 3:i8)
     667             : /*1490*/            /*Scope*/ 22, /*->1513*/
     668             : /*1491*/              OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     669             : /*1493*/              OPC_CheckPredicate, 10, // Predicate_vtx_id3_az_extloadi16
     670             : /*1495*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     671             : /*1497*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     672             : /*1500*/              OPC_EmitMergeInputChains1_0,
     673             : /*1501*/              OPC_EmitInteger, MVT::i8, 3, 
     674             : /*1504*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_16_cm), 0|OPFL_Chain|OPFL_MemRefs,
     675             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     676             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_vtx_id3_az_extloadi16>> - Complexity = 13
     677             :                       // Dst: (VTX_READ_16_cm:i32 MEMxi:i32:$src_gpr, 3:i8)
     678             : /*1513*/            0, /*End of Scope*/
     679             : /*1514*/          /*Scope*/ 22, /*->1537*/
     680             : /*1515*/            OPC_CheckPredicate, 1, // Predicate_load
     681             : /*1517*/            OPC_CheckPredicate, 10, // Predicate_vtx_id3_load
     682             : /*1519*/            OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     683             : /*1521*/            OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     684             : /*1524*/            OPC_EmitMergeInputChains1_0,
     685             : /*1525*/            OPC_EmitInteger, MVT::i8, 3, 
     686             : /*1528*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_32_cm), 0|OPFL_Chain|OPFL_MemRefs,
     687             :                         MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     688             :                     // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id3_load>> - Complexity = 13
     689             :                     // Dst: (VTX_READ_32_cm:i32 MEMxi:i32:$src_gpr, 3:i8)
     690             : /*1537*/          /*Scope*/ 50, /*->1588*/
     691             : /*1538*/            OPC_CheckPredicate, 3, // Predicate_az_extload
     692             : /*1540*/            OPC_Scope, 22, /*->1564*/ // 2 children in Scope
     693             : /*1542*/              OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     694             : /*1544*/              OPC_CheckPredicate, 11, // Predicate_vtx_id2_az_extloadi8
     695             : /*1546*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     696             : /*1548*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     697             : /*1551*/              OPC_EmitMergeInputChains1_0,
     698             : /*1552*/              OPC_EmitInteger, MVT::i8, 2, 
     699             : /*1555*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_8_cm), 0|OPFL_Chain|OPFL_MemRefs,
     700             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     701             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_vtx_id2_az_extloadi8>> - Complexity = 13
     702             :                       // Dst: (VTX_READ_8_cm:i32 MEMxi:i32:$src_gpr, 2:i8)
     703             : /*1564*/            /*Scope*/ 22, /*->1587*/
     704             : /*1565*/              OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     705             : /*1567*/              OPC_CheckPredicate, 11, // Predicate_vtx_id2_az_extloadi16
     706             : /*1569*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     707             : /*1571*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     708             : /*1574*/              OPC_EmitMergeInputChains1_0,
     709             : /*1575*/              OPC_EmitInteger, MVT::i8, 2, 
     710             : /*1578*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_16_cm), 0|OPFL_Chain|OPFL_MemRefs,
     711             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     712             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_vtx_id2_az_extloadi16>> - Complexity = 13
     713             :                       // Dst: (VTX_READ_16_cm:i32 MEMxi:i32:$src_gpr, 2:i8)
     714             : /*1587*/            0, /*End of Scope*/
     715             : /*1588*/          /*Scope*/ 22, /*->1611*/
     716             : /*1589*/            OPC_CheckPredicate, 1, // Predicate_load
     717             : /*1591*/            OPC_CheckPredicate, 11, // Predicate_vtx_id2_load
     718             : /*1593*/            OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     719             : /*1595*/            OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     720             : /*1598*/            OPC_EmitMergeInputChains1_0,
     721             : /*1599*/            OPC_EmitInteger, MVT::i8, 2, 
     722             : /*1602*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_32_cm), 0|OPFL_Chain|OPFL_MemRefs,
     723             :                         MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     724             :                     // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id2_load>> - Complexity = 13
     725             :                     // Dst: (VTX_READ_32_cm:i32 MEMxi:i32:$src_gpr, 2:i8)
     726             : /*1611*/          /*Scope*/ 50, /*->1662*/
     727             : /*1612*/            OPC_CheckPredicate, 3, // Predicate_az_extload
     728             : /*1614*/            OPC_Scope, 22, /*->1638*/ // 2 children in Scope
     729             : /*1616*/              OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     730             : /*1618*/              OPC_CheckPredicate, 12, // Predicate_vtx_id1_az_extloadi8
     731             : /*1620*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     732             : /*1622*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     733             : /*1625*/              OPC_EmitMergeInputChains1_0,
     734             : /*1626*/              OPC_EmitInteger, MVT::i8, 1, 
     735             : /*1629*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_8_cm), 0|OPFL_Chain|OPFL_MemRefs,
     736             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     737             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_vtx_id1_az_extloadi8>> - Complexity = 13
     738             :                       // Dst: (VTX_READ_8_cm:i32 MEMxi:i32:$src_gpr, 1:i8)
     739             : /*1638*/            /*Scope*/ 22, /*->1661*/
     740             : /*1639*/              OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     741             : /*1641*/              OPC_CheckPredicate, 12, // Predicate_vtx_id1_az_extloadi16
     742             : /*1643*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     743             : /*1645*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     744             : /*1648*/              OPC_EmitMergeInputChains1_0,
     745             : /*1649*/              OPC_EmitInteger, MVT::i8, 1, 
     746             : /*1652*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_16_cm), 0|OPFL_Chain|OPFL_MemRefs,
     747             :                           MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     748             :                       // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_vtx_id1_az_extloadi16>> - Complexity = 13
     749             :                       // Dst: (VTX_READ_16_cm:i32 MEMxi:i32:$src_gpr, 1:i8)
     750             : /*1661*/            0, /*End of Scope*/
     751             : /*1662*/          /*Scope*/ 22, /*->1685*/
     752             : /*1663*/            OPC_CheckPredicate, 1, // Predicate_load
     753             : /*1665*/            OPC_CheckPredicate, 12, // Predicate_vtx_id1_load
     754             : /*1667*/            OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
     755             : /*1669*/            OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
     756             : /*1672*/            OPC_EmitMergeInputChains1_0,
     757             : /*1673*/            OPC_EmitInteger, MVT::i8, 1, 
     758             : /*1676*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_32_cm), 0|OPFL_Chain|OPFL_MemRefs,
     759             :                         MVT::i32, 3/*#Ops*/, 2, 3, 4, 
     760             :                     // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id1_load>> - Complexity = 13
     761             :                     // Dst: (VTX_READ_32_cm:i32 MEMxi:i32:$src_gpr, 1:i8)
     762             : /*1685*/          0, /*End of Scope*/
     763             : /*1686*/        0, /*End of Scope*/
     764             : /*1687*/      /*Scope*/ 97|128,1/*225*/, /*->1914*/
     765             : /*1689*/        OPC_CaptureGlueInput,
     766             : /*1690*/        OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
     767             : /*1691*/        OPC_CheckPredicate, 13, // Predicate_si_ld_local
     768             : /*1693*/        OPC_Scope, 27, /*->1722*/ // 7 children in Scope
     769             : /*1695*/          OPC_CheckPredicate, 6, // Predicate_si_sextload_local
     770             : /*1697*/          OPC_CheckPredicate, 14, // Predicate_si_sextload_local_i8
     771             : /*1699*/          OPC_CheckType, MVT::i32,
     772             : /*1701*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     773             : /*1703*/          OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
     774             : /*1706*/          OPC_EmitMergeInputChains1_0,
     775             : /*1707*/          OPC_EmitNodeXForm, 0, 3, // as_i16imm
     776             : /*1710*/          OPC_EmitInteger, MVT::i1, 0, 
     777             : /*1713*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_I8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
     778             :                       MVT::i32, 3/*#Ops*/, 2, 4, 5, 
     779             :                   // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_sextload_local>><<P:Predicate_si_sextload_local_i8>> - Complexity = 13
     780             :                   // Dst: (DS_READ_I8:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
     781             : /*1722*/        /*Scope*/ 27, /*->1750*/
     782             : /*1723*/          OPC_CheckPredicate, 3, // Predicate_si_az_extload_local
     783             : /*1725*/          OPC_CheckPredicate, 14, // Predicate_si_az_extload_local_i8
     784             : /*1727*/          OPC_CheckType, MVT::i32,
     785             : /*1729*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     786             : /*1731*/          OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
     787             : /*1734*/          OPC_EmitMergeInputChains1_0,
     788             : /*1735*/          OPC_EmitNodeXForm, 0, 3, // as_i16imm
     789             : /*1738*/          OPC_EmitInteger, MVT::i1, 0, 
     790             : /*1741*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_U8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
     791             :                       MVT::i32, 3/*#Ops*/, 2, 4, 5, 
     792             :                   // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_az_extload_local>><<P:Predicate_si_az_extload_local_i8>> - Complexity = 13
     793             :                   // Dst: (DS_READ_U8:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
     794             : /*1750*/        /*Scope*/ 27, /*->1778*/
     795             : /*1751*/          OPC_CheckPredicate, 6, // Predicate_si_sextload_local
     796             : /*1753*/          OPC_CheckPredicate, 14, // Predicate_si_sextload_local_i8
     797             : /*1755*/          OPC_CheckType, MVT::i16,
     798             : /*1757*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     799             : /*1759*/          OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
     800             : /*1762*/          OPC_EmitMergeInputChains1_0,
     801             : /*1763*/          OPC_EmitNodeXForm, 0, 3, // as_i16imm
     802             : /*1766*/          OPC_EmitInteger, MVT::i1, 0, 
     803             : /*1769*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_I8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
     804             :                       MVT::i16, 3/*#Ops*/, 2, 4, 5, 
     805             :                   // Src: (SIld_local:i16 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_sextload_local>><<P:Predicate_si_sextload_local_i8>> - Complexity = 13
     806             :                   // Dst: (DS_READ_I8:i16 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
     807             : /*1778*/        /*Scope*/ 27, /*->1806*/
     808             : /*1779*/          OPC_CheckPredicate, 3, // Predicate_si_az_extload_local
     809             : /*1781*/          OPC_CheckPredicate, 14, // Predicate_si_az_extload_local_i8
     810             : /*1783*/          OPC_CheckType, MVT::i16,
     811             : /*1785*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     812             : /*1787*/          OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
     813             : /*1790*/          OPC_EmitMergeInputChains1_0,
     814             : /*1791*/          OPC_EmitNodeXForm, 0, 3, // as_i16imm
     815             : /*1794*/          OPC_EmitInteger, MVT::i1, 0, 
     816             : /*1797*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_U8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
     817             :                       MVT::i16, 3/*#Ops*/, 2, 4, 5, 
     818             :                   // Src: (SIld_local:i16 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_az_extload_local>><<P:Predicate_si_az_extload_local_i8>> - Complexity = 13
     819             :                   // Dst: (DS_READ_U8:i16 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
     820             : /*1806*/        /*Scope*/ 27, /*->1834*/
     821             : /*1807*/          OPC_CheckPredicate, 6, // Predicate_si_sextload_local
     822             : /*1809*/          OPC_CheckPredicate, 15, // Predicate_si_sextload_local_i16
     823             : /*1811*/          OPC_CheckType, MVT::i32,
     824             : /*1813*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     825             : /*1815*/          OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
     826             : /*1818*/          OPC_EmitMergeInputChains1_0,
     827             : /*1819*/          OPC_EmitNodeXForm, 0, 3, // as_i16imm
     828             : /*1822*/          OPC_EmitInteger, MVT::i1, 0, 
     829             : /*1825*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_I16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
     830             :                       MVT::i32, 3/*#Ops*/, 2, 4, 5, 
     831             :                   // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_sextload_local>><<P:Predicate_si_sextload_local_i16>> - Complexity = 13
     832             :                   // Dst: (DS_READ_I16:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
     833             : /*1834*/        /*Scope*/ 27, /*->1862*/
     834             : /*1835*/          OPC_CheckPredicate, 3, // Predicate_si_az_extload_local
     835             : /*1837*/          OPC_CheckPredicate, 15, // Predicate_si_az_extload_local_i16
     836             : /*1839*/          OPC_CheckType, MVT::i32,
     837             : /*1841*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     838             : /*1843*/          OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
     839             : /*1846*/          OPC_EmitMergeInputChains1_0,
     840             : /*1847*/          OPC_EmitNodeXForm, 0, 3, // as_i16imm
     841             : /*1850*/          OPC_EmitInteger, MVT::i1, 0, 
     842             : /*1853*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_U16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
     843             :                       MVT::i32, 3/*#Ops*/, 2, 4, 5, 
     844             :                   // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_az_extload_local>><<P:Predicate_si_az_extload_local_i16>> - Complexity = 13
     845             :                   // Dst: (DS_READ_U16:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
     846             : /*1862*/        /*Scope*/ 50, /*->1913*/
     847             : /*1863*/          OPC_CheckPredicate, 16, // Predicate_si_load_local
     848             : /*1865*/          OPC_SwitchType /*2 cases */, 21, MVT::i16,// ->1889
     849             : /*1868*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     850             : /*1870*/            OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
     851             : /*1873*/            OPC_EmitMergeInputChains1_0,
     852             : /*1874*/            OPC_EmitNodeXForm, 0, 3, // as_i16imm
     853             : /*1877*/            OPC_EmitInteger, MVT::i1, 0, 
     854             : /*1880*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_U16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
     855             :                         MVT::i16, 3/*#Ops*/, 2, 4, 5, 
     856             :                     // Src: (SIld_local:i16 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_load_local>> - Complexity = 13
     857             :                     // Dst: (DS_READ_U16:i16 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
     858             : /*1889*/          /*SwitchType*/ 21, MVT::i32,// ->1912
     859             : /*1891*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
     860             : /*1893*/            OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
     861             : /*1896*/            OPC_EmitMergeInputChains1_0,
     862             : /*1897*/            OPC_EmitNodeXForm, 0, 3, // as_i16imm
     863             : /*1900*/            OPC_EmitInteger, MVT::i1, 0, 
     864             : /*1903*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
     865             :                         MVT::i32, 3/*#Ops*/, 2, 4, 5, 
     866             :                     // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_load_local>> - Complexity = 13
     867             :                     // Dst: (DS_READ_B32:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
     868             : /*1912*/          0, // EndSwitchType
     869             : /*1913*/        0, /*End of Scope*/
     870             : /*1914*/      /*Scope*/ 45|128,7/*941*/, /*->2857*/
     871             : /*1916*/        OPC_RecordChild1, // #1 = $FLATOffsetSigned:vaddr:offset:slc
     872             : /*1917*/        OPC_CheckPredicate, 0, // Predicate_unindexedload
     873             : /*1919*/        OPC_Scope, 27, /*->1948*/ // 16 children in Scope
     874             : /*1921*/          OPC_CheckPredicate, 3, // Predicate_az_extload
     875             : /*1923*/          OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     876             : /*1925*/          OPC_CheckPredicate, 17, // Predicate_az_extloadi8_global
     877             : /*1927*/          OPC_CheckType, MVT::i32,
     878             : /*1929*/          OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
     879             : /*1931*/          OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
     880             : /*1934*/          OPC_EmitMergeInputChains1_0,
     881             : /*1935*/          OPC_EmitInteger, MVT::i1, 0, 
     882             : /*1938*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_UBYTE), 0|OPFL_Chain|OPFL_MemRefs,
     883             :                       MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
     884             :                   // Src: (ld:i32 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_global>> - Complexity = 7
     885             :                   // Dst: (GLOBAL_LOAD_UBYTE:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
     886             : /*1948*/        /*Scope*/ 27, /*->1976*/
     887             : /*1949*/          OPC_CheckPredicate, 6, // Predicate_sextload
     888             : /*1951*/          OPC_CheckPredicate, 4, // Predicate_sextloadi8
     889             : /*1953*/          OPC_CheckPredicate, 17, // Predicate_sextloadi8_global
     890             : /*1955*/          OPC_CheckType, MVT::i32,
     891             : /*1957*/          OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
     892             : /*1959*/          OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
     893             : /*1962*/          OPC_EmitMergeInputChains1_0,
     894             : /*1963*/          OPC_EmitInteger, MVT::i1, 0, 
     895             : /*1966*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_SBYTE), 0|OPFL_Chain|OPFL_MemRefs,
     896             :                       MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
     897             :                   // Src: (ld:i32 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> - Complexity = 7
     898             :                   // Dst: (GLOBAL_LOAD_SBYTE:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
     899             : /*1976*/        /*Scope*/ 27, /*->2004*/
     900             : /*1977*/          OPC_CheckPredicate, 3, // Predicate_az_extload
     901             : /*1979*/          OPC_CheckPredicate, 4, // Predicate_az_extloadi8
     902             : /*1981*/          OPC_CheckPredicate, 17, // Predicate_az_extloadi8_global
     903             : /*1983*/          OPC_CheckType, MVT::i16,
     904             : /*1985*/          OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
     905             : /*1987*/          OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
     906             : /*1990*/          OPC_EmitMergeInputChains1_0,
     907             : /*1991*/          OPC_EmitInteger, MVT::i1, 0, 
     908             : /*1994*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_UBYTE), 0|OPFL_Chain|OPFL_MemRefs,
     909             :                       MVT::i16, 4/*#Ops*/, 2, 3, 5, 4, 
     910             :                   // Src: (ld:i16 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_global>> - Complexity = 7
     911             :                   // Dst: (GLOBAL_LOAD_UBYTE:i16 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
     912             : /*2004*/        /*Scope*/ 27, /*->2032*/
     913             : /*2005*/          OPC_CheckPredicate, 6, // Predicate_sextload
     914             : /*2007*/          OPC_CheckPredicate, 4, // Predicate_sextloadi8
     915             : /*2009*/          OPC_CheckPredicate, 17, // Predicate_sextloadi8_global
     916             : /*2011*/          OPC_CheckType, MVT::i16,
     917             : /*2013*/          OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
     918             : /*2015*/          OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
     919             : /*2018*/          OPC_EmitMergeInputChains1_0,
     920             : /*2019*/          OPC_EmitInteger, MVT::i1, 0, 
     921             : /*2022*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_SBYTE), 0|OPFL_Chain|OPFL_MemRefs,
     922             :                       MVT::i16, 4/*#Ops*/, 2, 3, 5, 4, 
     923             :                   // Src: (ld:i16 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> - Complexity = 7
     924             :                   // Dst: (GLOBAL_LOAD_SBYTE:i16 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
     925             : /*2032*/        /*Scope*/ 27, /*->2060*/
     926             : /*2033*/          OPC_CheckPredicate, 3, // Predicate_az_extload
     927             : /*2035*/          OPC_CheckPredicate, 7, // Predicate_az_extloadi16
     928             : /*2037*/          OPC_CheckPredicate, 17, // Predicate_az_extloadi16_global
     929             : /*2039*/          OPC_CheckType, MVT::i32,
     930             : /*2041*/          OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
     931             : /*2043*/          OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
     932             : /*2046*/          OPC_EmitMergeInputChains1_0,
     933             : /*2047*/          OPC_EmitInteger, MVT::i1, 0, 
     934             : /*2050*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_USHORT), 0|OPFL_Chain|OPFL_MemRefs,
     935             :                       MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
     936             :                   // Src: (ld:i32 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_global>> - Complexity = 7
     937             :                   // Dst: (GLOBAL_LOAD_USHORT:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
     938             : /*2060*/        /*Scope*/ 27, /*->2088*/
     939             : /*2061*/          OPC_CheckPredicate, 6, // Predicate_sextload
     940             : /*2063*/          OPC_CheckPredicate, 7, // Predicate_sextloadi16
     941             : /*2065*/          OPC_CheckPredicate, 17, // Predicate_sextloadi16_global
     942             : /*2067*/          OPC_CheckType, MVT::i32,
     943             : /*2069*/          OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
     944             : /*2071*/          OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
     945             : /*2074*/          OPC_EmitMergeInputChains1_0,
     946             : /*2075*/          OPC_EmitInteger, MVT::i1, 0, 
     947             : /*2078*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_SSHORT), 0|OPFL_Chain|OPFL_MemRefs,
     948             :                       MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
     949             :                   // Src: (ld:i32 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> - Complexity = 7
     950             :                   // Dst: (GLOBAL_LOAD_SSHORT:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
     951             : /*2088*/        /*Scope*/ 97, /*->2186*/
     952             : /*2089*/          OPC_CheckPredicate, 1, // Predicate_load
     953             : /*2091*/          OPC_Scope, 46, /*->2139*/ // 2 children in Scope
     954             : /*2093*/            OPC_CheckPredicate, 17, // Predicate_global_load
     955             : /*2095*/            OPC_SwitchType /*2 cases */, 19, MVT::i16,// ->2117
     956             : /*2098*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
     957             : /*2100*/              OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
     958             : /*2103*/              OPC_EmitMergeInputChains1_0,
     959             : /*2104*/              OPC_EmitInteger, MVT::i1, 0, 
     960             : /*2107*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_USHORT), 0|OPFL_Chain|OPFL_MemRefs,
     961             :                           MVT::i16, 4/*#Ops*/, 2, 3, 5, 4, 
     962             :                       // Src: (ld:i16 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 7
     963             :                       // Dst: (GLOBAL_LOAD_USHORT:i16 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
     964             : /*2117*/            /*SwitchType*/ 19, MVT::i32,// ->2138
     965             : /*2119*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
     966             : /*2121*/              OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
     967             : /*2124*/              OPC_EmitMergeInputChains1_0,
     968             : /*2125*/              OPC_EmitInteger, MVT::i1, 0, 
     969             : /*2128*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_DWORD), 0|OPFL_Chain|OPFL_MemRefs,
     970             :                           MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
     971             :                       // Src: (ld:i32 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 7
     972             :                       // Dst: (GLOBAL_LOAD_DWORD:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
     973             : /*2138*/            0, // EndSwitchType
     974             : /*2139*/          /*Scope*/ 45, /*->2185*/
     975             : /*2140*/            OPC_CheckChild1Type, MVT::i32,
     976             : /*2142*/            OPC_CheckPredicate, 18, // Predicate_local_load
     977             : /*2144*/            OPC_CheckType, MVT::i32,
     978             : /*2146*/            OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
     979             : /*2148*/            OPC_EmitMergeInputChains1_0,
     980             : /*2149*/            OPC_EmitInteger, MVT::i32, 0, 
     981             : /*2152*/            OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
     982             : /*2164*/            OPC_EmitInteger, MVT::i32, 1, 
     983             : /*2167*/            OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
     984             : /*2170*/            OPC_EmitInteger, MVT::i32, 0, 
     985             : /*2173*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::LDS_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
     986             :                         MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6, 
     987             :                     // Src: (ld:i32 R600_Reg32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_local_load>> - Complexity = 4
     988             :                     // Dst: (LDS_READ_RET:i32 R600_Reg32:i32:$src0)
     989             : /*2185*/          0, /*End of Scope*/
     990             : /*2186*/        /*Scope*/ 62|128,1/*190*/, /*->2378*/
     991             : /*2188*/          OPC_CheckChild1Type, MVT::i32,
     992             : /*2190*/          OPC_CheckType, MVT::i32,
     993             : /*2192*/          OPC_Scope, 45, /*->2239*/ // 4 children in Scope
     994             : /*2194*/            OPC_CheckPredicate, 6, // Predicate_sextload
     995             : /*2196*/            OPC_CheckPredicate, 4, // Predicate_sextloadi8
     996             : /*2198*/            OPC_CheckPredicate, 18, // Predicate_sextloadi8_local
     997             : /*2200*/            OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
     998             : /*2202*/            OPC_EmitMergeInputChains1_0,
     999             : /*2203*/            OPC_EmitInteger, MVT::i32, 0, 
    1000             : /*2206*/            OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    1001             : /*2218*/            OPC_EmitInteger, MVT::i32, 1, 
    1002             : /*2221*/            OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
    1003             : /*2224*/            OPC_EmitInteger, MVT::i32, 0, 
    1004             : /*2227*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::LDS_BYTE_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
    1005             :                         MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6, 
    1006             :                     // Src: (ld:i32 i32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>> - Complexity = 4
    1007             :                     // Dst: (LDS_BYTE_READ_RET:i32 i32:i32:$src0)
    1008             : /*2239*/          /*Scope*/ 45, /*->2285*/
    1009             : /*2240*/            OPC_CheckPredicate, 3, // Predicate_az_extload
    1010             : /*2242*/            OPC_CheckPredicate, 4, // Predicate_az_extloadi8
    1011             : /*2244*/            OPC_CheckPredicate, 18, // Predicate_az_extloadi8_local
    1012             : /*2246*/            OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
    1013             : /*2248*/            OPC_EmitMergeInputChains1_0,
    1014             : /*2249*/            OPC_EmitInteger, MVT::i32, 0, 
    1015             : /*2252*/            OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    1016             : /*2264*/            OPC_EmitInteger, MVT::i32, 1, 
    1017             : /*2267*/            OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
    1018             : /*2270*/            OPC_EmitInteger, MVT::i32, 0, 
    1019             : /*2273*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::LDS_UBYTE_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
    1020             :                         MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6, 
    1021             :                     // Src: (ld:i32 i32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_local>> - Complexity = 4
    1022             :                     // Dst: (LDS_UBYTE_READ_RET:i32 i32:i32:$src0)
    1023             : /*2285*/          /*Scope*/ 45, /*->2331*/
    1024             : /*2286*/            OPC_CheckPredicate, 6, // Predicate_sextload
    1025             : /*2288*/            OPC_CheckPredicate, 7, // Predicate_sextloadi16
    1026             : /*2290*/            OPC_CheckPredicate, 18, // Predicate_sextloadi16_local
    1027             : /*2292*/            OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
    1028             : /*2294*/            OPC_EmitMergeInputChains1_0,
    1029             : /*2295*/            OPC_EmitInteger, MVT::i32, 0, 
    1030             : /*2298*/            OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    1031             : /*2310*/            OPC_EmitInteger, MVT::i32, 1, 
    1032             : /*2313*/            OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
    1033             : /*2316*/            OPC_EmitInteger, MVT::i32, 0, 
    1034             : /*2319*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::LDS_SHORT_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
    1035             :                         MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6, 
    1036             :                     // Src: (ld:i32 i32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>> - Complexity = 4
    1037             :                     // Dst: (LDS_SHORT_READ_RET:i32 i32:i32:$src0)
    1038             : /*2331*/          /*Scope*/ 45, /*->2377*/
    1039             : /*2332*/            OPC_CheckPredicate, 3, // Predicate_az_extload
    1040             : /*2334*/            OPC_CheckPredicate, 7, // Predicate_az_extloadi16
    1041             : /*2336*/            OPC_CheckPredicate, 18, // Predicate_az_extloadi16_local
    1042             : /*2338*/            OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
    1043             : /*2340*/            OPC_EmitMergeInputChains1_0,
    1044             : /*2341*/            OPC_EmitInteger, MVT::i32, 0, 
    1045             : /*2344*/            OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    1046             : /*2356*/            OPC_EmitInteger, MVT::i32, 1, 
    1047             : /*2359*/            OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
    1048             : /*2362*/            OPC_EmitInteger, MVT::i32, 0, 
    1049             : /*2365*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::LDS_USHORT_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
    1050             :                         MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6, 
    1051             :                     // Src: (ld:i32 i32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_local>> - Complexity = 4
    1052             :                     // Dst: (LDS_USHORT_READ_RET:i32 i32:i32:$src0)
    1053             : /*2377*/          0, /*End of Scope*/
    1054             : /*2378*/        /*Scope*/ 27, /*->2406*/
    1055             : /*2379*/          OPC_CheckPredicate, 3, // Predicate_az_extload
    1056             : /*2381*/          OPC_CheckPredicate, 4, // Predicate_az_extloadi8
    1057             : /*2383*/          OPC_CheckPredicate, 19, // Predicate_flat_az_extloadi8
    1058             : /*2385*/          OPC_CheckType, MVT::i32,
    1059             : /*2387*/          OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1060             : /*2389*/          OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1061             : /*2392*/          OPC_EmitMergeInputChains1_0,
    1062             : /*2393*/          OPC_EmitInteger, MVT::i1, 0, 
    1063             : /*2396*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_UBYTE), 0|OPFL_Chain|OPFL_MemRefs,
    1064             :                       MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1065             :                   // Src: (ld:i32 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_flat_az_extloadi8>> - Complexity = -3
    1066             :                   // Dst: (FLAT_LOAD_UBYTE:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1067             : /*2406*/        /*Scope*/ 27, /*->2434*/
    1068             : /*2407*/          OPC_CheckPredicate, 6, // Predicate_sextload
    1069             : /*2409*/          OPC_CheckPredicate, 4, // Predicate_sextloadi8
    1070             : /*2411*/          OPC_CheckPredicate, 19, // Predicate_flat_sextloadi8
    1071             : /*2413*/          OPC_CheckType, MVT::i32,
    1072             : /*2415*/          OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1073             : /*2417*/          OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1074             : /*2420*/          OPC_EmitMergeInputChains1_0,
    1075             : /*2421*/          OPC_EmitInteger, MVT::i1, 0, 
    1076             : /*2424*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_SBYTE), 0|OPFL_Chain|OPFL_MemRefs,
    1077             :                       MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1078             :                   // Src: (ld:i32 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_flat_sextloadi8>> - Complexity = -3
    1079             :                   // Dst: (FLAT_LOAD_SBYTE:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1080             : /*2434*/        /*Scope*/ 27, /*->2462*/
    1081             : /*2435*/          OPC_CheckPredicate, 3, // Predicate_az_extload
    1082             : /*2437*/          OPC_CheckPredicate, 4, // Predicate_az_extloadi8
    1083             : /*2439*/          OPC_CheckPredicate, 19, // Predicate_flat_az_extloadi8
    1084             : /*2441*/          OPC_CheckType, MVT::i16,
    1085             : /*2443*/          OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1086             : /*2445*/          OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1087             : /*2448*/          OPC_EmitMergeInputChains1_0,
    1088             : /*2449*/          OPC_EmitInteger, MVT::i1, 0, 
    1089             : /*2452*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_UBYTE), 0|OPFL_Chain|OPFL_MemRefs,
    1090             :                       MVT::i16, 4/*#Ops*/, 2, 3, 5, 4, 
    1091             :                   // Src: (ld:i16 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_flat_az_extloadi8>> - Complexity = -3
    1092             :                   // Dst: (FLAT_LOAD_UBYTE:i16 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1093             : /*2462*/        /*Scope*/ 27, /*->2490*/
    1094             : /*2463*/          OPC_CheckPredicate, 6, // Predicate_sextload
    1095             : /*2465*/          OPC_CheckPredicate, 4, // Predicate_sextloadi8
    1096             : /*2467*/          OPC_CheckPredicate, 19, // Predicate_flat_sextloadi8
    1097             : /*2469*/          OPC_CheckType, MVT::i16,
    1098             : /*2471*/          OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1099             : /*2473*/          OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1100             : /*2476*/          OPC_EmitMergeInputChains1_0,
    1101             : /*2477*/          OPC_EmitInteger, MVT::i1, 0, 
    1102             : /*2480*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_SBYTE), 0|OPFL_Chain|OPFL_MemRefs,
    1103             :                       MVT::i16, 4/*#Ops*/, 2, 3, 5, 4, 
    1104             :                   // Src: (ld:i16 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_flat_sextloadi8>> - Complexity = -3
    1105             :                   // Dst: (FLAT_LOAD_SBYTE:i16 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1106             : /*2490*/        /*Scope*/ 27, /*->2518*/
    1107             : /*2491*/          OPC_CheckPredicate, 3, // Predicate_az_extload
    1108             : /*2493*/          OPC_CheckPredicate, 7, // Predicate_az_extloadi16
    1109             : /*2495*/          OPC_CheckPredicate, 19, // Predicate_flat_az_extloadi16
    1110             : /*2497*/          OPC_CheckType, MVT::i32,
    1111             : /*2499*/          OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1112             : /*2501*/          OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1113             : /*2504*/          OPC_EmitMergeInputChains1_0,
    1114             : /*2505*/          OPC_EmitInteger, MVT::i1, 0, 
    1115             : /*2508*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_USHORT), 0|OPFL_Chain|OPFL_MemRefs,
    1116             :                       MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1117             :                   // Src: (ld:i32 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_flat_az_extloadi16>> - Complexity = -3
    1118             :                   // Dst: (FLAT_LOAD_USHORT:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1119             : /*2518*/        /*Scope*/ 25, /*->2544*/
    1120             : /*2519*/          OPC_CheckPredicate, 1, // Predicate_load
    1121             : /*2521*/          OPC_CheckPredicate, 19, // Predicate_flat_load
    1122             : /*2523*/          OPC_CheckType, MVT::i16,
    1123             : /*2525*/          OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1124             : /*2527*/          OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1125             : /*2530*/          OPC_EmitMergeInputChains1_0,
    1126             : /*2531*/          OPC_EmitInteger, MVT::i1, 0, 
    1127             : /*2534*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_USHORT), 0|OPFL_Chain|OPFL_MemRefs,
    1128             :                       MVT::i16, 4/*#Ops*/, 2, 3, 5, 4, 
    1129             :                   // Src: (ld:i16 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_flat_load>> - Complexity = -3
    1130             :                   // Dst: (FLAT_LOAD_USHORT:i16 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1131             : /*2544*/        /*Scope*/ 27, /*->2572*/
    1132             : /*2545*/          OPC_CheckPredicate, 6, // Predicate_sextload
    1133             : /*2547*/          OPC_CheckPredicate, 7, // Predicate_sextloadi16
    1134             : /*2549*/          OPC_CheckPredicate, 19, // Predicate_flat_sextloadi16
    1135             : /*2551*/          OPC_CheckType, MVT::i32,
    1136             : /*2553*/          OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1137             : /*2555*/          OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1138             : /*2558*/          OPC_EmitMergeInputChains1_0,
    1139             : /*2559*/          OPC_EmitInteger, MVT::i1, 0, 
    1140             : /*2562*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_SSHORT), 0|OPFL_Chain|OPFL_MemRefs,
    1141             :                       MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1142             :                   // Src: (ld:i32 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_flat_sextloadi16>> - Complexity = -3
    1143             :                   // Dst: (FLAT_LOAD_SSHORT:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1144             : /*2572*/        /*Scope*/ 26|128,2/*282*/, /*->2856*/
    1145             : /*2574*/          OPC_CheckPredicate, 1, // Predicate_load
    1146             : /*2576*/          OPC_Scope, 23, /*->2601*/ // 2 children in Scope
    1147             : /*2578*/            OPC_CheckPredicate, 19, // Predicate_flat_load
    1148             : /*2580*/            OPC_CheckType, MVT::i32,
    1149             : /*2582*/            OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1150             : /*2584*/            OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1151             : /*2587*/            OPC_EmitMergeInputChains1_0,
    1152             : /*2588*/            OPC_EmitInteger, MVT::i1, 0, 
    1153             : /*2591*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_DWORD), 0|OPFL_Chain|OPFL_MemRefs,
    1154             :                         MVT::i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1155             :                     // Src: (ld:i32 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_flat_load>> - Complexity = -3
    1156             :                     // Dst: (FLAT_LOAD_DWORD:i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1157             : /*2601*/          /*Scope*/ 124|128,1/*252*/, /*->2855*/
    1158             : /*2603*/            OPC_CheckPredicate, 2, // Predicate_smrd_load
    1159             : /*2605*/            OPC_SwitchType /*4 cases */, 60, MVT::v2i32,// ->2668
    1160             : /*2608*/              OPC_Scope, 38, /*->2648*/ // 2 children in Scope
    1161             : /*2610*/                OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1162             : /*2612*/                OPC_Scope, 16, /*->2630*/ // 2 children in Scope
    1163             : /*2614*/                  OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectSMRDImm:$ #2 #3
    1164             : /*2617*/                  OPC_EmitMergeInputChains1_0,
    1165             : /*2618*/                  OPC_EmitInteger, MVT::i1, 0, 
    1166             : /*2621*/                  OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_IMM), 0|OPFL_Chain|OPFL_MemRefs,
    1167             :                               MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1168             :                           // Src: (ld:v2i32 (SMRDImm:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1169             :                           // Dst: (S_LOAD_DWORDX2_IMM:v2i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1170             : /*2630*/                /*Scope*/ 16, /*->2647*/
    1171             : /*2631*/                  OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectSMRDSgpr:$ #2 #3
    1172             : /*2634*/                  OPC_EmitMergeInputChains1_0,
    1173             : /*2635*/                  OPC_EmitInteger, MVT::i1, 0, 
    1174             : /*2638*/                  OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
    1175             :                               MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1176             :                           // Src: (ld:v2i32 (SMRDSgpr:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1177             :                           // Dst: (S_LOAD_DWORDX2_SGPR:v2i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1178             : /*2647*/                0, /*End of Scope*/
    1179             : /*2648*/              /*Scope*/ 18, /*->2667*/
    1180             : /*2649*/                OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() ==SISubtarget::SEA_ISLANDS)
    1181             : /*2651*/                OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectSMRDImm32:$ #2 #3
    1182             : /*2654*/                OPC_EmitMergeInputChains1_0,
    1183             : /*2655*/                OPC_EmitInteger, MVT::i1, 0, 
    1184             : /*2658*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_IMM_ci), 0|OPFL_Chain|OPFL_MemRefs,
    1185             :                             MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1186             :                         // Src: (ld:v2i32 (SMRDImm32:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1187             :                         // Dst: (S_LOAD_DWORDX2_IMM_ci:v2i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1188             : /*2667*/              0, /*End of Scope*/
    1189             : /*2668*/            /*SwitchType*/ 60, MVT::v4i32,// ->2730
    1190             : /*2670*/              OPC_Scope, 38, /*->2710*/ // 2 children in Scope
    1191             : /*2672*/                OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1192             : /*2674*/                OPC_Scope, 16, /*->2692*/ // 2 children in Scope
    1193             : /*2676*/                  OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectSMRDImm:$ #2 #3
    1194             : /*2679*/                  OPC_EmitMergeInputChains1_0,
    1195             : /*2680*/                  OPC_EmitInteger, MVT::i1, 0, 
    1196             : /*2683*/                  OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_IMM), 0|OPFL_Chain|OPFL_MemRefs,
    1197             :                               MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1198             :                           // Src: (ld:v4i32 (SMRDImm:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1199             :                           // Dst: (S_LOAD_DWORDX4_IMM:v4i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1200             : /*2692*/                /*Scope*/ 16, /*->2709*/
    1201             : /*2693*/                  OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectSMRDSgpr:$ #2 #3
    1202             : /*2696*/                  OPC_EmitMergeInputChains1_0,
    1203             : /*2697*/                  OPC_EmitInteger, MVT::i1, 0, 
    1204             : /*2700*/                  OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
    1205             :                               MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1206             :                           // Src: (ld:v4i32 (SMRDSgpr:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1207             :                           // Dst: (S_LOAD_DWORDX4_SGPR:v4i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1208             : /*2709*/                0, /*End of Scope*/
    1209             : /*2710*/              /*Scope*/ 18, /*->2729*/
    1210             : /*2711*/                OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() ==SISubtarget::SEA_ISLANDS)
    1211             : /*2713*/                OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectSMRDImm32:$ #2 #3
    1212             : /*2716*/                OPC_EmitMergeInputChains1_0,
    1213             : /*2717*/                OPC_EmitInteger, MVT::i1, 0, 
    1214             : /*2720*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_IMM_ci), 0|OPFL_Chain|OPFL_MemRefs,
    1215             :                             MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1216             :                         // Src: (ld:v4i32 (SMRDImm32:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1217             :                         // Dst: (S_LOAD_DWORDX4_IMM_ci:v4i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1218             : /*2729*/              0, /*End of Scope*/
    1219             : /*2730*/            /*SwitchType*/ 60, MVT::v8i32,// ->2792
    1220             : /*2732*/              OPC_Scope, 38, /*->2772*/ // 2 children in Scope
    1221             : /*2734*/                OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1222             : /*2736*/                OPC_Scope, 16, /*->2754*/ // 2 children in Scope
    1223             : /*2738*/                  OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectSMRDImm:$ #2 #3
    1224             : /*2741*/                  OPC_EmitMergeInputChains1_0,
    1225             : /*2742*/                  OPC_EmitInteger, MVT::i1, 0, 
    1226             : /*2745*/                  OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
    1227             :                               MVT::v8i32, 3/*#Ops*/, 2, 3, 4, 
    1228             :                           // Src: (ld:v8i32 (SMRDImm:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1229             :                           // Dst: (S_LOAD_DWORDX8_IMM:v8i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1230             : /*2754*/                /*Scope*/ 16, /*->2771*/
    1231             : /*2755*/                  OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectSMRDSgpr:$ #2 #3
    1232             : /*2758*/                  OPC_EmitMergeInputChains1_0,
    1233             : /*2759*/                  OPC_EmitInteger, MVT::i1, 0, 
    1234             : /*2762*/                  OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
    1235             :                               MVT::v8i32, 3/*#Ops*/, 2, 3, 4, 
    1236             :                           // Src: (ld:v8i32 (SMRDSgpr:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1237             :                           // Dst: (S_LOAD_DWORDX8_SGPR:v8i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1238             : /*2771*/                0, /*End of Scope*/
    1239             : /*2772*/              /*Scope*/ 18, /*->2791*/
    1240             : /*2773*/                OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() ==SISubtarget::SEA_ISLANDS)
    1241             : /*2775*/                OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectSMRDImm32:$ #2 #3
    1242             : /*2778*/                OPC_EmitMergeInputChains1_0,
    1243             : /*2779*/                OPC_EmitInteger, MVT::i1, 0, 
    1244             : /*2782*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM_ci), 0|OPFL_Chain|OPFL_MemRefs,
    1245             :                             MVT::v8i32, 3/*#Ops*/, 2, 3, 4, 
    1246             :                         // Src: (ld:v8i32 (SMRDImm32:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1247             :                         // Dst: (S_LOAD_DWORDX8_IMM_ci:v8i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1248             : /*2791*/              0, /*End of Scope*/
    1249             : /*2792*/            /*SwitchType*/ 60, MVT::v16i32,// ->2854
    1250             : /*2794*/              OPC_Scope, 38, /*->2834*/ // 2 children in Scope
    1251             : /*2796*/                OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1252             : /*2798*/                OPC_Scope, 16, /*->2816*/ // 2 children in Scope
    1253             : /*2800*/                  OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectSMRDImm:$ #2 #3
    1254             : /*2803*/                  OPC_EmitMergeInputChains1_0,
    1255             : /*2804*/                  OPC_EmitInteger, MVT::i1, 0, 
    1256             : /*2807*/                  OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_IMM), 0|OPFL_Chain|OPFL_MemRefs,
    1257             :                               MVT::v16i32, 3/*#Ops*/, 2, 3, 4, 
    1258             :                           // Src: (ld:v16i32 (SMRDImm:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1259             :                           // Dst: (S_LOAD_DWORDX16_IMM:v16i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1260             : /*2816*/                /*Scope*/ 16, /*->2833*/
    1261             : /*2817*/                  OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectSMRDSgpr:$ #2 #3
    1262             : /*2820*/                  OPC_EmitMergeInputChains1_0,
    1263             : /*2821*/                  OPC_EmitInteger, MVT::i1, 0, 
    1264             : /*2824*/                  OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
    1265             :                               MVT::v16i32, 3/*#Ops*/, 2, 3, 4, 
    1266             :                           // Src: (ld:v16i32 (SMRDSgpr:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1267             :                           // Dst: (S_LOAD_DWORDX16_SGPR:v16i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1268             : /*2833*/                0, /*End of Scope*/
    1269             : /*2834*/              /*Scope*/ 18, /*->2853*/
    1270             : /*2835*/                OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() ==SISubtarget::SEA_ISLANDS)
    1271             : /*2837*/                OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectSMRDImm32:$ #2 #3
    1272             : /*2840*/                OPC_EmitMergeInputChains1_0,
    1273             : /*2841*/                OPC_EmitInteger, MVT::i1, 0, 
    1274             : /*2844*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_IMM_ci), 0|OPFL_Chain|OPFL_MemRefs,
    1275             :                             MVT::v16i32, 3/*#Ops*/, 2, 3, 4, 
    1276             :                         // Src: (ld:v16i32 (SMRDImm32:iPTR i64:i64:$sbase, i32:i32:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> - Complexity = 113
    1277             :                         // Dst: (S_LOAD_DWORDX16_IMM_ci:v16i32 ?:i64:$sbase, ?:i32:$offset, 0:i1)
    1278             : /*2853*/              0, /*End of Scope*/
    1279             : /*2854*/            0, // EndSwitchType
    1280             : /*2855*/          0, /*End of Scope*/
    1281             : /*2856*/        0, /*End of Scope*/
    1282             : /*2857*/      /*Scope*/ 31, /*->2889*/
    1283             : /*2858*/        OPC_CaptureGlueInput,
    1284             : /*2859*/        OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
    1285             : /*2860*/        OPC_CheckPredicate, 13, // Predicate_si_ld_local
    1286             : /*2862*/        OPC_CheckPredicate, 16, // Predicate_si_load_local
    1287             : /*2864*/        OPC_CheckPredicate, 20, // Predicate_si_load_local_align8
    1288             : /*2866*/        OPC_CheckType, MVT::v2i32,
    1289             : /*2868*/        OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1290             : /*2870*/        OPC_CheckComplexPat, /*CP*/9, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
    1291             : /*2873*/        OPC_EmitMergeInputChains1_0,
    1292             : /*2874*/        OPC_EmitNodeXForm, 0, 3, // as_i16imm
    1293             : /*2877*/        OPC_EmitInteger, MVT::i1, 0, 
    1294             : /*2880*/        OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    1295             :                     MVT::v2i32, 3/*#Ops*/, 2, 4, 5, 
    1296             :                 // Src: (SIld_local:v2i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_load_local>><<P:Predicate_si_load_local_align8>> - Complexity = 113
    1297             :                 // Dst: (DS_READ_B64:v2i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
    1298             : /*2889*/      /*Scope*/ 99|128,1/*227*/, /*->3118*/
    1299             : /*2891*/        OPC_RecordChild1, // #1 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
    1300             : /*2892*/        OPC_CheckPredicate, 0, // Predicate_unindexedload
    1301             : /*2894*/        OPC_CheckPredicate, 1, // Predicate_load
    1302             : /*2896*/        OPC_Scope, 46, /*->2944*/ // 4 children in Scope
    1303             : /*2898*/          OPC_CheckPredicate, 5, // Predicate_mubuf_load
    1304             : /*2900*/          OPC_SwitchType /*2 cases */, 19, MVT::v2i32,// ->2922
    1305             : /*2903*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1306             : /*2905*/            OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
    1307             : /*2908*/            OPC_EmitMergeInputChains1_0,
    1308             : /*2909*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
    1309             :                         MVT::v2i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
    1310             :                     // Src: (ld:v2i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 28
    1311             :                     // Dst: (BUFFER_LOAD_DWORDX2_ADDR64:v2i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1312             : /*2922*/          /*SwitchType*/ 19, MVT::v4i32,// ->2943
    1313             : /*2924*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1314             : /*2926*/            OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
    1315             : /*2929*/            OPC_EmitMergeInputChains1_0,
    1316             : /*2930*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
    1317             :                         MVT::v4i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
    1318             :                     // Src: (ld:v4i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 28
    1319             :                     // Dst: (BUFFER_LOAD_DWORDX4_ADDR64:v4i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1320             : /*2943*/          0, // EndSwitchType
    1321             : /*2944*/        /*Scope*/ 62, /*->3007*/
    1322             : /*2945*/          OPC_CheckPredicate, 9, // Predicate_load_private
    1323             : /*2947*/          OPC_SwitchType /*2 cases */, 27, MVT::v2i32,// ->2977
    1324             : /*2950*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1325             : /*2952*/            OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
    1326             : /*2955*/            OPC_EmitMergeInputChains1_0,
    1327             : /*2956*/            OPC_EmitInteger, MVT::i1, 0, 
    1328             : /*2959*/            OPC_EmitInteger, MVT::i1, 0, 
    1329             : /*2962*/            OPC_EmitInteger, MVT::i1, 0, 
    1330             : /*2965*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1331             :                         MVT::v2i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
    1332             :                     // Src: (ld:v2i32 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 27
    1333             :                     // Dst: (BUFFER_LOAD_DWORDX2_OFFSET:v2i32 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1334             : /*2977*/          /*SwitchType*/ 27, MVT::v4i32,// ->3006
    1335             : /*2979*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1336             : /*2981*/            OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectMUBUFScratchOffset:$ #2 #3 #4
    1337             : /*2984*/            OPC_EmitMergeInputChains1_0,
    1338             : /*2985*/            OPC_EmitInteger, MVT::i1, 0, 
    1339             : /*2988*/            OPC_EmitInteger, MVT::i1, 0, 
    1340             : /*2991*/            OPC_EmitInteger, MVT::i1, 0, 
    1341             : /*2994*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1342             :                         MVT::v4i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
    1343             :                     // Src: (ld:v4i32 (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 27
    1344             :                     // Dst: (BUFFER_LOAD_DWORDX4_OFFSET:v4i32 ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1345             : /*3006*/          0, // EndSwitchType
    1346             : /*3007*/        /*Scope*/ 44, /*->3052*/
    1347             : /*3008*/          OPC_CheckPredicate, 5, // Predicate_mubuf_load
    1348             : /*3010*/          OPC_SwitchType /*2 cases */, 18, MVT::v2i32,// ->3031
    1349             : /*3013*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1350             : /*3015*/            OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
    1351             : /*3018*/            OPC_EmitMergeInputChains1_0,
    1352             : /*3019*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1353             :                         MVT::v2i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
    1354             :                     // Src: (ld:v2i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 25
    1355             :                     // Dst: (BUFFER_LOAD_DWORDX2_OFFSET:v2i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1356             : /*3031*/          /*SwitchType*/ 18, MVT::v4i32,// ->3051
    1357             : /*3033*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1358             : /*3035*/            OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
    1359             : /*3038*/            OPC_EmitMergeInputChains1_0,
    1360             : /*3039*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1361             :                         MVT::v4i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7, 
    1362             :                     // Src: (ld:v4i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_mubuf_load>> - Complexity = 25
    1363             :                     // Dst: (BUFFER_LOAD_DWORDX4_OFFSET:v4i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1364             : /*3051*/          0, // EndSwitchType
    1365             : /*3052*/        /*Scope*/ 64, /*->3117*/
    1366             : /*3053*/          OPC_CheckPredicate, 9, // Predicate_load_private
    1367             : /*3055*/          OPC_SwitchType /*2 cases */, 28, MVT::v2i32,// ->3086
    1368             : /*3058*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1369             : /*3060*/            OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
    1370             : /*3063*/            OPC_EmitMergeInputChains1_0,
    1371             : /*3064*/            OPC_EmitInteger, MVT::i1, 0, 
    1372             : /*3067*/            OPC_EmitInteger, MVT::i1, 0, 
    1373             : /*3070*/            OPC_EmitInteger, MVT::i1, 0, 
    1374             : /*3073*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1375             :                         MVT::v2i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
    1376             :                     // Src: (ld:v2i32 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 19
    1377             :                     // Dst: (BUFFER_LOAD_DWORDX2_OFFEN:v2i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1378             : /*3086*/          /*SwitchType*/ 28, MVT::v4i32,// ->3116
    1379             : /*3088*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1380             : /*3090*/            OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFScratchOffen:$ #2 #3 #4 #5
    1381             : /*3093*/            OPC_EmitMergeInputChains1_0,
    1382             : /*3094*/            OPC_EmitInteger, MVT::i1, 0, 
    1383             : /*3097*/            OPC_EmitInteger, MVT::i1, 0, 
    1384             : /*3100*/            OPC_EmitInteger, MVT::i1, 0, 
    1385             : /*3103*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1386             :                         MVT::v4i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8, 
    1387             :                     // Src: (ld:v4i32 (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 19
    1388             :                     // Dst: (BUFFER_LOAD_DWORDX4_OFFEN:v4i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1389             : /*3116*/          0, // EndSwitchType
    1390             : /*3117*/        0, /*End of Scope*/
    1391             : /*3118*/      /*Scope*/ 27, /*->3146*/
    1392             : /*3119*/        OPC_CaptureGlueInput,
    1393             : /*3120*/        OPC_RecordChild1, // #1 = $DS64Bit4ByteAligned:ptr:offset0:offset1
    1394             : /*3121*/        OPC_CheckPredicate, 13, // Predicate_si_ld_local
    1395             : /*3123*/        OPC_CheckPredicate, 16, // Predicate_si_load_local
    1396             : /*3125*/        OPC_CheckType, MVT::v2i32,
    1397             : /*3127*/        OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1398             : /*3129*/        OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectDS64Bit4ByteAligned:$ #2 #3 #4
    1399             : /*3132*/        OPC_EmitMergeInputChains1_0,
    1400             : /*3133*/        OPC_EmitInteger, MVT::i1, 0, 
    1401             : /*3136*/        OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::DS_READ2_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    1402             :                     MVT::v2i32, 4/*#Ops*/, 2, 3, 4, 5, 
    1403             :                 // Src: (SIld_local:v2i32 (DS64Bit4ByteAligned:iPTR i32:i32:$ptr, i8:i8:$offset0, i8:i8:$offset1))<<P:Predicate_si_ld_local>><<P:Predicate_si_load_local>> - Complexity = 16
    1404             :                 // Dst: (DS_READ2_B32:v2i32 ?:i32:$ptr, ?:i8:$offset0, ?:i8:$offset1, 0:i1)
    1405             : /*3146*/      /*Scope*/ 0|128,3/*384*/, /*->3532*/
    1406             : /*3148*/        OPC_RecordChild1, // #1 = $src_gpr
    1407             : /*3149*/        OPC_Scope, 22|128,2/*278*/, /*->3430*/ // 2 children in Scope
    1408             : /*3152*/          OPC_CheckChild1Type, MVT::i32,
    1409             : /*3154*/          OPC_CheckPredicate, 0, // Predicate_unindexedload
    1410             : /*3156*/          OPC_CheckPredicate, 1, // Predicate_load
    1411             : /*3158*/          OPC_Scope, 44, /*->3204*/ // 6 children in Scope
    1412             : /*3160*/            OPC_CheckPredicate, 10, // Predicate_vtx_id3_load
    1413             : /*3162*/            OPC_SwitchType /*2 cases */, 18, MVT::v2i32,// ->3183
    1414             : /*3165*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    1415             : /*3167*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1416             : /*3170*/              OPC_EmitMergeInputChains1_0,
    1417             : /*3171*/              OPC_EmitInteger, MVT::i8, 3, 
    1418             : /*3174*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_64_eg), 0|OPFL_Chain|OPFL_MemRefs,
    1419             :                           MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1420             :                       // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id3_load>> - Complexity = 13
    1421             :                       // Dst: (VTX_READ_64_eg:v2i32 MEMxi:i32:$src_gpr, 3:i8)
    1422             : /*3183*/            /*SwitchType*/ 18, MVT::v4i32,// ->3203
    1423             : /*3185*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    1424             : /*3187*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1425             : /*3190*/              OPC_EmitMergeInputChains1_0,
    1426             : /*3191*/              OPC_EmitInteger, MVT::i8, 3, 
    1427             : /*3194*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_128_eg), 0|OPFL_Chain|OPFL_MemRefs,
    1428             :                           MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1429             :                       // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id3_load>> - Complexity = 13
    1430             :                       // Dst: (VTX_READ_128_eg:v4i32 MEMxi:i32:$src_gpr, 3:i8)
    1431             : /*3203*/            0, // EndSwitchType
    1432             : /*3204*/          /*Scope*/ 44, /*->3249*/
    1433             : /*3205*/            OPC_CheckPredicate, 11, // Predicate_vtx_id2_load
    1434             : /*3207*/            OPC_SwitchType /*2 cases */, 18, MVT::v2i32,// ->3228
    1435             : /*3210*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    1436             : /*3212*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1437             : /*3215*/              OPC_EmitMergeInputChains1_0,
    1438             : /*3216*/              OPC_EmitInteger, MVT::i8, 2, 
    1439             : /*3219*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_64_eg), 0|OPFL_Chain|OPFL_MemRefs,
    1440             :                           MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1441             :                       // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id2_load>> - Complexity = 13
    1442             :                       // Dst: (VTX_READ_64_eg:v2i32 MEMxi:i32:$src_gpr, 2:i8)
    1443             : /*3228*/            /*SwitchType*/ 18, MVT::v4i32,// ->3248
    1444             : /*3230*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    1445             : /*3232*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1446             : /*3235*/              OPC_EmitMergeInputChains1_0,
    1447             : /*3236*/              OPC_EmitInteger, MVT::i8, 2, 
    1448             : /*3239*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_128_eg), 0|OPFL_Chain|OPFL_MemRefs,
    1449             :                           MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1450             :                       // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id2_load>> - Complexity = 13
    1451             :                       // Dst: (VTX_READ_128_eg:v4i32 MEMxi:i32:$src_gpr, 2:i8)
    1452             : /*3248*/            0, // EndSwitchType
    1453             : /*3249*/          /*Scope*/ 44, /*->3294*/
    1454             : /*3250*/            OPC_CheckPredicate, 12, // Predicate_vtx_id1_load
    1455             : /*3252*/            OPC_SwitchType /*2 cases */, 18, MVT::v2i32,// ->3273
    1456             : /*3255*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    1457             : /*3257*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1458             : /*3260*/              OPC_EmitMergeInputChains1_0,
    1459             : /*3261*/              OPC_EmitInteger, MVT::i8, 1, 
    1460             : /*3264*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_64_eg), 0|OPFL_Chain|OPFL_MemRefs,
    1461             :                           MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1462             :                       // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id1_load>> - Complexity = 13
    1463             :                       // Dst: (VTX_READ_64_eg:v2i32 MEMxi:i32:$src_gpr, 1:i8)
    1464             : /*3273*/            /*SwitchType*/ 18, MVT::v4i32,// ->3293
    1465             : /*3275*/              OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    1466             : /*3277*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1467             : /*3280*/              OPC_EmitMergeInputChains1_0,
    1468             : /*3281*/              OPC_EmitInteger, MVT::i8, 1, 
    1469             : /*3284*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_128_eg), 0|OPFL_Chain|OPFL_MemRefs,
    1470             :                           MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1471             :                       // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id1_load>> - Complexity = 13
    1472             :                       // Dst: (VTX_READ_128_eg:v4i32 MEMxi:i32:$src_gpr, 1:i8)
    1473             : /*3293*/            0, // EndSwitchType
    1474             : /*3294*/          /*Scope*/ 44, /*->3339*/
    1475             : /*3295*/            OPC_CheckPredicate, 10, // Predicate_vtx_id3_load
    1476             : /*3297*/            OPC_SwitchType /*2 cases */, 18, MVT::v2i32,// ->3318
    1477             : /*3300*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    1478             : /*3302*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1479             : /*3305*/              OPC_EmitMergeInputChains1_0,
    1480             : /*3306*/              OPC_EmitInteger, MVT::i8, 3, 
    1481             : /*3309*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_64_cm), 0|OPFL_Chain|OPFL_MemRefs,
    1482             :                           MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1483             :                       // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id3_load>> - Complexity = 13
    1484             :                       // Dst: (VTX_READ_64_cm:v2i32 MEMxi:i32:$src_gpr, 3:i8)
    1485             : /*3318*/            /*SwitchType*/ 18, MVT::v4i32,// ->3338
    1486             : /*3320*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    1487             : /*3322*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1488             : /*3325*/              OPC_EmitMergeInputChains1_0,
    1489             : /*3326*/              OPC_EmitInteger, MVT::i8, 3, 
    1490             : /*3329*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_128_cm), 0|OPFL_Chain|OPFL_MemRefs,
    1491             :                           MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1492             :                       // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id3_load>> - Complexity = 13
    1493             :                       // Dst: (VTX_READ_128_cm:v4i32 MEMxi:i32:$src_gpr, 3:i8)
    1494             : /*3338*/            0, // EndSwitchType
    1495             : /*3339*/          /*Scope*/ 44, /*->3384*/
    1496             : /*3340*/            OPC_CheckPredicate, 11, // Predicate_vtx_id2_load
    1497             : /*3342*/            OPC_SwitchType /*2 cases */, 18, MVT::v2i32,// ->3363
    1498             : /*3345*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    1499             : /*3347*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1500             : /*3350*/              OPC_EmitMergeInputChains1_0,
    1501             : /*3351*/              OPC_EmitInteger, MVT::i8, 2, 
    1502             : /*3354*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_64_cm), 0|OPFL_Chain|OPFL_MemRefs,
    1503             :                           MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1504             :                       // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id2_load>> - Complexity = 13
    1505             :                       // Dst: (VTX_READ_64_cm:v2i32 MEMxi:i32:$src_gpr, 2:i8)
    1506             : /*3363*/            /*SwitchType*/ 18, MVT::v4i32,// ->3383
    1507             : /*3365*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    1508             : /*3367*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1509             : /*3370*/              OPC_EmitMergeInputChains1_0,
    1510             : /*3371*/              OPC_EmitInteger, MVT::i8, 2, 
    1511             : /*3374*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_128_cm), 0|OPFL_Chain|OPFL_MemRefs,
    1512             :                           MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1513             :                       // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id2_load>> - Complexity = 13
    1514             :                       // Dst: (VTX_READ_128_cm:v4i32 MEMxi:i32:$src_gpr, 2:i8)
    1515             : /*3383*/            0, // EndSwitchType
    1516             : /*3384*/          /*Scope*/ 44, /*->3429*/
    1517             : /*3385*/            OPC_CheckPredicate, 12, // Predicate_vtx_id1_load
    1518             : /*3387*/            OPC_SwitchType /*2 cases */, 18, MVT::v2i32,// ->3408
    1519             : /*3390*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    1520             : /*3392*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1521             : /*3395*/              OPC_EmitMergeInputChains1_0,
    1522             : /*3396*/              OPC_EmitInteger, MVT::i8, 1, 
    1523             : /*3399*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_64_cm), 0|OPFL_Chain|OPFL_MemRefs,
    1524             :                           MVT::v2i32, 3/*#Ops*/, 2, 3, 4, 
    1525             :                       // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id1_load>> - Complexity = 13
    1526             :                       // Dst: (VTX_READ_64_cm:v2i32 MEMxi:i32:$src_gpr, 1:i8)
    1527             : /*3408*/            /*SwitchType*/ 18, MVT::v4i32,// ->3428
    1528             : /*3410*/              OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    1529             : /*3412*/              OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
    1530             : /*3415*/              OPC_EmitMergeInputChains1_0,
    1531             : /*3416*/              OPC_EmitInteger, MVT::i8, 1, 
    1532             : /*3419*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::VTX_READ_128_cm), 0|OPFL_Chain|OPFL_MemRefs,
    1533             :                           MVT::v4i32, 3/*#Ops*/, 2, 3, 4, 
    1534             :                       // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_vtx_id1_load>> - Complexity = 13
    1535             :                       // Dst: (VTX_READ_128_cm:v4i32 MEMxi:i32:$src_gpr, 1:i8)
    1536             : /*3428*/            0, // EndSwitchType
    1537             : /*3429*/          0, /*End of Scope*/
    1538             : /*3430*/        /*Scope*/ 100, /*->3531*/
    1539             : /*3431*/          OPC_CheckPredicate, 0, // Predicate_unindexedload
    1540             : /*3433*/          OPC_CheckPredicate, 1, // Predicate_load
    1541             : /*3435*/          OPC_Scope, 46, /*->3483*/ // 2 children in Scope
    1542             : /*3437*/            OPC_CheckPredicate, 17, // Predicate_global_load
    1543             : /*3439*/            OPC_SwitchType /*2 cases */, 19, MVT::v2i32,// ->3461
    1544             : /*3442*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    1545             : /*3444*/              OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
    1546             : /*3447*/              OPC_EmitMergeInputChains1_0,
    1547             : /*3448*/              OPC_EmitInteger, MVT::i1, 0, 
    1548             : /*3451*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
    1549             :                           MVT::v2i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1550             :                       // Src: (ld:v2i32 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 7
    1551             :                       // Dst: (GLOBAL_LOAD_DWORDX2:v2i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1552             : /*3461*/            /*SwitchType*/ 19, MVT::v4i32,// ->3482
    1553             : /*3463*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    1554             : /*3465*/              OPC_CheckComplexPat, /*CP*/10, /*#*/1, // SelectFlatOffset<true>:$ #2 #3 #4
    1555             : /*3468*/              OPC_EmitMergeInputChains1_0,
    1556             : /*3469*/              OPC_EmitInteger, MVT::i1, 0, 
    1557             : /*3472*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::GLOBAL_LOAD_DWORDX4), 0|OPFL_Chain|OPFL_MemRefs,
    1558             :                           MVT::v4i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1559             :                       // Src: (ld:v4i32 (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 7
    1560             :                       // Dst: (GLOBAL_LOAD_DWORDX4:v4i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1561             : /*3482*/            0, // EndSwitchType
    1562             : /*3483*/          /*Scope*/ 46, /*->3530*/
    1563             : /*3484*/            OPC_CheckPredicate, 19, // Predicate_flat_load
    1564             : /*3486*/            OPC_SwitchType /*2 cases */, 19, MVT::v2i32,// ->3508
    1565             : /*3489*/              OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1566             : /*3491*/              OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1567             : /*3494*/              OPC_EmitMergeInputChains1_0,
    1568             : /*3495*/              OPC_EmitInteger, MVT::i1, 0, 
    1569             : /*3498*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
    1570             :                           MVT::v2i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1571             :                       // Src: (ld:v2i32 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_flat_load>> - Complexity = -3
    1572             :                       // Dst: (FLAT_LOAD_DWORDX2:v2i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1573             : /*3508*/            /*SwitchType*/ 19, MVT::v4i32,// ->3529
    1574             : /*3510*/              OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    1575             : /*3512*/              OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectFlatOffset<false>:$ #2 #3 #4
    1576             : /*3515*/              OPC_EmitMergeInputChains1_0,
    1577             : /*3516*/              OPC_EmitInteger, MVT::i1, 0, 
    1578             : /*3519*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::FLAT_LOAD_DWORDX4), 0|OPFL_Chain|OPFL_MemRefs,
    1579             :                           MVT::v4i32, 4/*#Ops*/, 2, 3, 5, 4, 
    1580             :                       // Src: (ld:v4i32 (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_flat_load>> - Complexity = -3
    1581             :                       // Dst: (FLAT_LOAD_DWORDX4:v4i32 ?:i64:$vaddr, ?:i16:$offset, 0:i1, ?:i1:$slc)
    1582             : /*3529*/            0, // EndSwitchType
    1583             : /*3530*/          0, /*End of Scope*/
    1584             : /*3531*/        0, /*End of Scope*/
    1585             : /*3532*/      0, /*End of Scope*/
    1586             : /*3533*/    /*SwitchOpcode*/ 123|128,13/*1787*/, TARGET_VAL(ISD::STORE),// ->5324
    1587             : /*3537*/      OPC_RecordMemRef,
    1588             : /*3538*/      OPC_RecordNode, // #0 = 'SIst_local' chained node
    1589             : /*3539*/      OPC_Scope, 32, /*->3573*/ // 6 children in Scope
    1590             : /*3541*/        OPC_CaptureGlueInput,
    1591             : /*3542*/        OPC_RecordChild1, // #1 = $value
    1592             : /*3543*/        OPC_CheckChild1Type, MVT::v2i32,
    1593             : /*3545*/        OPC_RecordChild2, // #2 = $DS1Addr1Offset:ptr:offset
    1594             : /*3546*/        OPC_CheckPredicate, 21, // Predicate_si_st_local
    1595             : /*3548*/        OPC_CheckPredicate, 22, // Predicate_si_store_local
    1596             : /*3550*/        OPC_CheckPredicate, 20, // Predicate_si_store_local_align8
    1597             : /*3552*/        OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1598             : /*3554*/        OPC_CheckComplexPat, /*CP*/9, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
    1599             : /*3557*/        OPC_EmitMergeInputChains1_0,
    1600             : /*3558*/        OPC_EmitNodeXForm, 0, 4, // as_i16imm
    1601             : /*3561*/        OPC_EmitInteger, MVT::i1, 0, 
    1602             : /*3564*/        OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::DS_WRITE_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    1603             :                     4/*#Ops*/, 3, 1, 5, 6, 
    1604             :                 // Src: (SIst_local v2i32:v2i32:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_store_local>><<P:Predicate_si_store_local_align8>> - Complexity = 113
    1605             :                 // Dst: (DS_WRITE_B64 ?:i32:$ptr, ?:v2i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
    1606             : /*3573*/      /*Scope*/ 68|128,6/*836*/, /*->4411*/
    1607             : /*3575*/        OPC_RecordChild1, // #1 = $vdata
    1608             : /*3576*/        OPC_Scope, 107|128,2/*363*/, /*->3942*/ // 5 children in Scope
    1609             : /*3579*/          OPC_CheckChild1Type, MVT::i32,
    1610             : /*3581*/          OPC_RecordChild2, // #2 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
    1611             : /*3582*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    1612             : /*3584*/          OPC_Scope, 52, /*->3638*/ // 8 children in Scope
    1613             : /*3586*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    1614             : /*3588*/            OPC_Scope, 23, /*->3613*/ // 2 children in Scope
    1615             : /*3590*/              OPC_CheckPredicate, 25, // Predicate_truncstorei8
    1616             : /*3592*/              OPC_CheckPredicate, 17, // Predicate_truncstorei8_global
    1617             : /*3594*/              OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1618             : /*3596*/              OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
    1619             : /*3599*/              OPC_EmitMergeInputChains1_0,
    1620             : /*3600*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
    1621             :                           8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1622             :                       // Src: (st i32:i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> - Complexity = 28
    1623             :                       // Dst: (BUFFER_STORE_BYTE_ADDR64 i32:i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1624             : /*3613*/            /*Scope*/ 23, /*->3637*/
    1625             : /*3614*/              OPC_CheckPredicate, 26, // Predicate_truncstorei16
    1626             : /*3616*/              OPC_CheckPredicate, 17, // Predicate_truncstorei16_global
    1627             : /*3618*/              OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1628             : /*3620*/              OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
    1629             : /*3623*/              OPC_EmitMergeInputChains1_0,
    1630             : /*3624*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
    1631             :                           8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1632             :                       // Src: (st i32:i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> - Complexity = 28
    1633             :                       // Dst: (BUFFER_STORE_SHORT_ADDR64 i32:i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1634             : /*3637*/            0, /*End of Scope*/
    1635             : /*3638*/          /*Scope*/ 23, /*->3662*/
    1636             : /*3639*/            OPC_CheckPredicate, 27, // Predicate_store
    1637             : /*3641*/            OPC_CheckPredicate, 17, // Predicate_global_store
    1638             : /*3643*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1639             : /*3645*/            OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
    1640             : /*3648*/            OPC_EmitMergeInputChains1_0,
    1641             : /*3649*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
    1642             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1643             :                     // Src: (st i32:i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 28
    1644             :                     // Dst: (BUFFER_STORE_DWORD_ADDR64 i32:i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1645             : /*3662*/          /*Scope*/ 68, /*->3731*/
    1646             : /*3663*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    1647             : /*3665*/            OPC_Scope, 31, /*->3698*/ // 2 children in Scope
    1648             : /*3667*/              OPC_CheckPredicate, 25, // Predicate_truncstorei8
    1649             : /*3669*/              OPC_CheckPredicate, 9, // Predicate_truncstorei8_private
    1650             : /*3671*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1651             : /*3673*/              OPC_CheckComplexPat, /*CP*/4, /*#*/2, // SelectMUBUFScratchOffset:$ #3 #4 #5
    1652             : /*3676*/              OPC_EmitMergeInputChains1_0,
    1653             : /*3677*/              OPC_EmitInteger, MVT::i1, 0, 
    1654             : /*3680*/              OPC_EmitInteger, MVT::i1, 0, 
    1655             : /*3683*/              OPC_EmitInteger, MVT::i1, 0, 
    1656             : /*3686*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1657             :                           7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1658             :                       // Src: (st i32:i32:$value, (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> - Complexity = 27
    1659             :                       // Dst: (BUFFER_STORE_BYTE_OFFSET ?:i32:$value, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1660             : /*3698*/            /*Scope*/ 31, /*->3730*/
    1661             : /*3699*/              OPC_CheckPredicate, 26, // Predicate_truncstorei16
    1662             : /*3701*/              OPC_CheckPredicate, 9, // Predicate_truncstorei16_private
    1663             : /*3703*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1664             : /*3705*/              OPC_CheckComplexPat, /*CP*/4, /*#*/2, // SelectMUBUFScratchOffset:$ #3 #4 #5
    1665             : /*3708*/              OPC_EmitMergeInputChains1_0,
    1666             : /*3709*/              OPC_EmitInteger, MVT::i1, 0, 
    1667             : /*3712*/              OPC_EmitInteger, MVT::i1, 0, 
    1668             : /*3715*/              OPC_EmitInteger, MVT::i1, 0, 
    1669             : /*3718*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1670             :                           7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1671             :                       // Src: (st i32:i32:$value, (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> - Complexity = 27
    1672             :                       // Dst: (BUFFER_STORE_SHORT_OFFSET ?:i32:$value, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1673             : /*3730*/            0, /*End of Scope*/
    1674             : /*3731*/          /*Scope*/ 31, /*->3763*/
    1675             : /*3732*/            OPC_CheckPredicate, 27, // Predicate_store
    1676             : /*3734*/            OPC_CheckPredicate, 9, // Predicate_store_private
    1677             : /*3736*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1678             : /*3738*/            OPC_CheckComplexPat, /*CP*/4, /*#*/2, // SelectMUBUFScratchOffset:$ #3 #4 #5
    1679             : /*3741*/            OPC_EmitMergeInputChains1_0,
    1680             : /*3742*/            OPC_EmitInteger, MVT::i1, 0, 
    1681             : /*3745*/            OPC_EmitInteger, MVT::i1, 0, 
    1682             : /*3748*/            OPC_EmitInteger, MVT::i1, 0, 
    1683             : /*3751*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1684             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1685             :                     // Src: (st i32:i32:$value, (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 27
    1686             :                     // Dst: (BUFFER_STORE_DWORD_OFFSET ?:i32:$value, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1687             : /*3763*/          /*Scope*/ 50, /*->3814*/
    1688             : /*3764*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    1689             : /*3766*/            OPC_Scope, 22, /*->3790*/ // 2 children in Scope
    1690             : /*3768*/              OPC_CheckPredicate, 25, // Predicate_truncstorei8
    1691             : /*3770*/              OPC_CheckPredicate, 17, // Predicate_truncstorei8_global
    1692             : /*3772*/              OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1693             : /*3774*/              OPC_CheckComplexPat, /*CP*/5, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
    1694             : /*3777*/              OPC_EmitMergeInputChains1_0,
    1695             : /*3778*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1696             :                           7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1697             :                       // Src: (st i32:i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> - Complexity = 25
    1698             :                       // Dst: (BUFFER_STORE_BYTE_OFFSET i32:i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1699             : /*3790*/            /*Scope*/ 22, /*->3813*/
    1700             : /*3791*/              OPC_CheckPredicate, 26, // Predicate_truncstorei16
    1701             : /*3793*/              OPC_CheckPredicate, 17, // Predicate_truncstorei16_global
    1702             : /*3795*/              OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1703             : /*3797*/              OPC_CheckComplexPat, /*CP*/5, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
    1704             : /*3800*/              OPC_EmitMergeInputChains1_0,
    1705             : /*3801*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1706             :                           7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1707             :                       // Src: (st i32:i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> - Complexity = 25
    1708             :                       // Dst: (BUFFER_STORE_SHORT_OFFSET i32:i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1709             : /*3813*/            0, /*End of Scope*/
    1710             : /*3814*/          /*Scope*/ 22, /*->3837*/
    1711             : /*3815*/            OPC_CheckPredicate, 27, // Predicate_store
    1712             : /*3817*/            OPC_CheckPredicate, 17, // Predicate_global_store
    1713             : /*3819*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1714             : /*3821*/            OPC_CheckComplexPat, /*CP*/5, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
    1715             : /*3824*/            OPC_EmitMergeInputChains1_0,
    1716             : /*3825*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1717             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1718             :                     // Src: (st i32:i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 25
    1719             :                     // Dst: (BUFFER_STORE_DWORD_OFFSET i32:i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1720             : /*3837*/          /*Scope*/ 70, /*->3908*/
    1721             : /*3838*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    1722             : /*3840*/            OPC_Scope, 32, /*->3874*/ // 2 children in Scope
    1723             : /*3842*/              OPC_CheckPredicate, 25, // Predicate_truncstorei8
    1724             : /*3844*/              OPC_CheckPredicate, 9, // Predicate_truncstorei8_private
    1725             : /*3846*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1726             : /*3848*/              OPC_CheckComplexPat, /*CP*/6, /*#*/2, // SelectMUBUFScratchOffen:$ #3 #4 #5 #6
    1727             : /*3851*/              OPC_EmitMergeInputChains1_0,
    1728             : /*3852*/              OPC_EmitInteger, MVT::i1, 0, 
    1729             : /*3855*/              OPC_EmitInteger, MVT::i1, 0, 
    1730             : /*3858*/              OPC_EmitInteger, MVT::i1, 0, 
    1731             : /*3861*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1732             :                           8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1733             :                       // Src: (st i32:i32:$value, (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> - Complexity = 19
    1734             :                       // Dst: (BUFFER_STORE_BYTE_OFFEN ?:i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1735             : /*3874*/            /*Scope*/ 32, /*->3907*/
    1736             : /*3875*/              OPC_CheckPredicate, 26, // Predicate_truncstorei16
    1737             : /*3877*/              OPC_CheckPredicate, 9, // Predicate_truncstorei16_private
    1738             : /*3879*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1739             : /*3881*/              OPC_CheckComplexPat, /*CP*/6, /*#*/2, // SelectMUBUFScratchOffen:$ #3 #4 #5 #6
    1740             : /*3884*/              OPC_EmitMergeInputChains1_0,
    1741             : /*3885*/              OPC_EmitInteger, MVT::i1, 0, 
    1742             : /*3888*/              OPC_EmitInteger, MVT::i1, 0, 
    1743             : /*3891*/              OPC_EmitInteger, MVT::i1, 0, 
    1744             : /*3894*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1745             :                           8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1746             :                       // Src: (st i32:i32:$value, (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> - Complexity = 19
    1747             :                       // Dst: (BUFFER_STORE_SHORT_OFFEN ?:i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1748             : /*3907*/            0, /*End of Scope*/
    1749             : /*3908*/          /*Scope*/ 32, /*->3941*/
    1750             : /*3909*/            OPC_CheckPredicate, 27, // Predicate_store
    1751             : /*3911*/            OPC_CheckPredicate, 9, // Predicate_store_private
    1752             : /*3913*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1753             : /*3915*/            OPC_CheckComplexPat, /*CP*/6, /*#*/2, // SelectMUBUFScratchOffen:$ #3 #4 #5 #6
    1754             : /*3918*/            OPC_EmitMergeInputChains1_0,
    1755             : /*3919*/            OPC_EmitInteger, MVT::i1, 0, 
    1756             : /*3922*/            OPC_EmitInteger, MVT::i1, 0, 
    1757             : /*3925*/            OPC_EmitInteger, MVT::i1, 0, 
    1758             : /*3928*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1759             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1760             :                     // Src: (st i32:i32:$value, (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 19
    1761             :                     // Dst: (BUFFER_STORE_DWORD_OFFEN ?:i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1762             : /*3941*/          0, /*End of Scope*/
    1763             : /*3942*/        /*Scope*/ 113, /*->4056*/
    1764             : /*3943*/          OPC_CheckChild1Type, MVT::v2i32,
    1765             : /*3945*/          OPC_RecordChild2, // #2 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
    1766             : /*3946*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    1767             : /*3948*/          OPC_CheckPredicate, 27, // Predicate_store
    1768             : /*3950*/          OPC_Scope, 21, /*->3973*/ // 4 children in Scope
    1769             : /*3952*/            OPC_CheckPredicate, 17, // Predicate_global_store
    1770             : /*3954*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1771             : /*3956*/            OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
    1772             : /*3959*/            OPC_EmitMergeInputChains1_0,
    1773             : /*3960*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
    1774             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1775             :                     // Src: (st v2i32:v2i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 28
    1776             :                     // Dst: (BUFFER_STORE_DWORDX2_ADDR64 v2i32:v2i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1777             : /*3973*/          /*Scope*/ 29, /*->4003*/
    1778             : /*3974*/            OPC_CheckPredicate, 9, // Predicate_store_private
    1779             : /*3976*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1780             : /*3978*/            OPC_CheckComplexPat, /*CP*/4, /*#*/2, // SelectMUBUFScratchOffset:$ #3 #4 #5
    1781             : /*3981*/            OPC_EmitMergeInputChains1_0,
    1782             : /*3982*/            OPC_EmitInteger, MVT::i1, 0, 
    1783             : /*3985*/            OPC_EmitInteger, MVT::i1, 0, 
    1784             : /*3988*/            OPC_EmitInteger, MVT::i1, 0, 
    1785             : /*3991*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1786             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1787             :                     // Src: (st v2i32:v2i32:$value, (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 27
    1788             :                     // Dst: (BUFFER_STORE_DWORDX2_OFFSET ?:v2i32:$value, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1789             : /*4003*/          /*Scope*/ 20, /*->4024*/
    1790             : /*4004*/            OPC_CheckPredicate, 17, // Predicate_global_store
    1791             : /*4006*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1792             : /*4008*/            OPC_CheckComplexPat, /*CP*/5, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
    1793             : /*4011*/            OPC_EmitMergeInputChains1_0,
    1794             : /*4012*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1795             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1796             :                     // Src: (st v2i32:v2i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 25
    1797             :                     // Dst: (BUFFER_STORE_DWORDX2_OFFSET v2i32:v2i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1798             : /*4024*/          /*Scope*/ 30, /*->4055*/
    1799             : /*4025*/            OPC_CheckPredicate, 9, // Predicate_store_private
    1800             : /*4027*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1801             : /*4029*/            OPC_CheckComplexPat, /*CP*/6, /*#*/2, // SelectMUBUFScratchOffen:$ #3 #4 #5 #6
    1802             : /*4032*/            OPC_EmitMergeInputChains1_0,
    1803             : /*4033*/            OPC_EmitInteger, MVT::i1, 0, 
    1804             : /*4036*/            OPC_EmitInteger, MVT::i1, 0, 
    1805             : /*4039*/            OPC_EmitInteger, MVT::i1, 0, 
    1806             : /*4042*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1807             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1808             :                     // Src: (st v2i32:v2i32:$value, (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 19
    1809             :                     // Dst: (BUFFER_STORE_DWORDX2_OFFEN ?:v2i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1810             : /*4055*/          0, /*End of Scope*/
    1811             : /*4056*/        /*Scope*/ 48, /*->4105*/
    1812             : /*4057*/          OPC_CheckChild1Type, MVT::Untyped,
    1813             : /*4059*/          OPC_RecordChild2, // #2 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
    1814             : /*4060*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    1815             : /*4062*/          OPC_CheckPredicate, 27, // Predicate_store
    1816             : /*4064*/          OPC_CheckPredicate, 17, // Predicate_global_store
    1817             : /*4066*/          OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1818             : /*4068*/          OPC_Scope, 17, /*->4087*/ // 2 children in Scope
    1819             : /*4070*/            OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
    1820             : /*4073*/            OPC_EmitMergeInputChains1_0,
    1821             : /*4074*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
    1822             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1823             :                     // Src: (st untyped:Untyped:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 28
    1824             :                     // Dst: (BUFFER_STORE_DWORDX3_ADDR64 untyped:Untyped:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1825             : /*4087*/          /*Scope*/ 16, /*->4104*/
    1826             : /*4088*/            OPC_CheckComplexPat, /*CP*/5, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
    1827             : /*4091*/            OPC_EmitMergeInputChains1_0,
    1828             : /*4092*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1829             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1830             :                     // Src: (st untyped:Untyped:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 25
    1831             :                     // Dst: (BUFFER_STORE_DWORDX3_OFFSET untyped:Untyped:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1832             : /*4104*/          0, /*End of Scope*/
    1833             : /*4105*/        /*Scope*/ 113, /*->4219*/
    1834             : /*4106*/          OPC_CheckChild1Type, MVT::v4i32,
    1835             : /*4108*/          OPC_RecordChild2, // #2 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
    1836             : /*4109*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    1837             : /*4111*/          OPC_CheckPredicate, 27, // Predicate_store
    1838             : /*4113*/          OPC_Scope, 21, /*->4136*/ // 4 children in Scope
    1839             : /*4115*/            OPC_CheckPredicate, 17, // Predicate_global_store
    1840             : /*4117*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1841             : /*4119*/            OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
    1842             : /*4122*/            OPC_EmitMergeInputChains1_0,
    1843             : /*4123*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
    1844             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1845             :                     // Src: (st v4i32:v4i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 28
    1846             :                     // Dst: (BUFFER_STORE_DWORDX4_ADDR64 v4i32:v4i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1847             : /*4136*/          /*Scope*/ 29, /*->4166*/
    1848             : /*4137*/            OPC_CheckPredicate, 9, // Predicate_store_private
    1849             : /*4139*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1850             : /*4141*/            OPC_CheckComplexPat, /*CP*/4, /*#*/2, // SelectMUBUFScratchOffset:$ #3 #4 #5
    1851             : /*4144*/            OPC_EmitMergeInputChains1_0,
    1852             : /*4145*/            OPC_EmitInteger, MVT::i1, 0, 
    1853             : /*4148*/            OPC_EmitInteger, MVT::i1, 0, 
    1854             : /*4151*/            OPC_EmitInteger, MVT::i1, 0, 
    1855             : /*4154*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1856             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1857             :                     // Src: (st v4i32:v4i32:$value, (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 27
    1858             :                     // Dst: (BUFFER_STORE_DWORDX4_OFFSET ?:v4i32:$value, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1859             : /*4166*/          /*Scope*/ 20, /*->4187*/
    1860             : /*4167*/            OPC_CheckPredicate, 17, // Predicate_global_store
    1861             : /*4169*/            OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1862             : /*4171*/            OPC_CheckComplexPat, /*CP*/5, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
    1863             : /*4174*/            OPC_EmitMergeInputChains1_0,
    1864             : /*4175*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1865             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1866             :                     // Src: (st v4i32:v4i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 25
    1867             :                     // Dst: (BUFFER_STORE_DWORDX4_OFFSET v4i32:v4i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
    1868             : /*4187*/          /*Scope*/ 30, /*->4218*/
    1869             : /*4188*/            OPC_CheckPredicate, 9, // Predicate_store_private
    1870             : /*4190*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1871             : /*4192*/            OPC_CheckComplexPat, /*CP*/6, /*#*/2, // SelectMUBUFScratchOffen:$ #3 #4 #5 #6
    1872             : /*4195*/            OPC_EmitMergeInputChains1_0,
    1873             : /*4196*/            OPC_EmitInteger, MVT::i1, 0, 
    1874             : /*4199*/            OPC_EmitInteger, MVT::i1, 0, 
    1875             : /*4202*/            OPC_EmitInteger, MVT::i1, 0, 
    1876             : /*4205*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1877             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1878             :                     // Src: (st v4i32:v4i32:$value, (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 19
    1879             :                     // Dst: (BUFFER_STORE_DWORDX4_OFFEN ?:v4i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1880             : /*4218*/          0, /*End of Scope*/
    1881             : /*4219*/        /*Scope*/ 61|128,1/*189*/, /*->4410*/
    1882             : /*4221*/          OPC_CheckChild1Type, MVT::i16,
    1883             : /*4223*/          OPC_RecordChild2, // #2 = $MUBUFScratchOffset:srsrc:soffset:offset
    1884             : /*4224*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    1885             : /*4226*/          OPC_Scope, 33, /*->4261*/ // 6 children in Scope
    1886             : /*4228*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    1887             : /*4230*/            OPC_CheckPredicate, 25, // Predicate_truncstorei8
    1888             : /*4232*/            OPC_CheckPredicate, 9, // Predicate_truncstorei8_private
    1889             : /*4234*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1890             : /*4236*/            OPC_CheckComplexPat, /*CP*/4, /*#*/2, // SelectMUBUFScratchOffset:$ #3 #4 #5
    1891             : /*4239*/            OPC_EmitMergeInputChains1_0,
    1892             : /*4240*/            OPC_EmitInteger, MVT::i1, 0, 
    1893             : /*4243*/            OPC_EmitInteger, MVT::i1, 0, 
    1894             : /*4246*/            OPC_EmitInteger, MVT::i1, 0, 
    1895             : /*4249*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1896             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1897             :                     // Src: (st i16:i16:$value, (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> - Complexity = 27
    1898             :                     // Dst: (BUFFER_STORE_BYTE_OFFSET ?:i16:$value, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1899             : /*4261*/          /*Scope*/ 31, /*->4293*/
    1900             : /*4262*/            OPC_CheckPredicate, 27, // Predicate_store
    1901             : /*4264*/            OPC_CheckPredicate, 9, // Predicate_store_private
    1902             : /*4266*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1903             : /*4268*/            OPC_CheckComplexPat, /*CP*/4, /*#*/2, // SelectMUBUFScratchOffset:$ #3 #4 #5
    1904             : /*4271*/            OPC_EmitMergeInputChains1_0,
    1905             : /*4272*/            OPC_EmitInteger, MVT::i1, 0, 
    1906             : /*4275*/            OPC_EmitInteger, MVT::i1, 0, 
    1907             : /*4278*/            OPC_EmitInteger, MVT::i1, 0, 
    1908             : /*4281*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1909             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1910             :                     // Src: (st i16:i16:$value, (MUBUFScratchOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 27
    1911             :                     // Dst: (BUFFER_STORE_SHORT_OFFSET ?:i16:$value, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1912             : /*4293*/          /*Scope*/ 24, /*->4318*/
    1913             : /*4294*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    1914             : /*4296*/            OPC_CheckPredicate, 25, // Predicate_truncstorei8
    1915             : /*4298*/            OPC_CheckPredicate, 17, // Predicate_truncstorei8_global
    1916             : /*4300*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1917             : /*4302*/            OPC_CheckComplexPat, /*CP*/5, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
    1918             : /*4305*/            OPC_EmitMergeInputChains1_0,
    1919             : /*4306*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1920             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1921             :                     // Src: (st i16:i16:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> - Complexity = 25
    1922             :                     // Dst: (BUFFER_STORE_BYTE_OFFSET ?:i16:$vdata, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
    1923             : /*4318*/          /*Scope*/ 22, /*->4341*/
    1924             : /*4319*/            OPC_CheckPredicate, 27, // Predicate_store
    1925             : /*4321*/            OPC_CheckPredicate, 17, // Predicate_global_store
    1926             : /*4323*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1927             : /*4325*/            OPC_CheckComplexPat, /*CP*/5, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
    1928             : /*4328*/            OPC_EmitMergeInputChains1_0,
    1929             : /*4329*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
    1930             :                         7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8, 
    1931             :                     // Src: (st i16:i16:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 25
    1932             :                     // Dst: (BUFFER_STORE_SHORT_OFFSET ?:i16:$vdata, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
    1933             : /*4341*/          /*Scope*/ 34, /*->4376*/
    1934             : /*4342*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    1935             : /*4344*/            OPC_CheckPredicate, 25, // Predicate_truncstorei8
    1936             : /*4346*/            OPC_CheckPredicate, 9, // Predicate_truncstorei8_private
    1937             : /*4348*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1938             : /*4350*/            OPC_CheckComplexPat, /*CP*/6, /*#*/2, // SelectMUBUFScratchOffen:$ #3 #4 #5 #6
    1939             : /*4353*/            OPC_EmitMergeInputChains1_0,
    1940             : /*4354*/            OPC_EmitInteger, MVT::i1, 0, 
    1941             : /*4357*/            OPC_EmitInteger, MVT::i1, 0, 
    1942             : /*4360*/            OPC_EmitInteger, MVT::i1, 0, 
    1943             : /*4363*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1944             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1945             :                     // Src: (st i16:i16:$value, (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> - Complexity = 19
    1946             :                     // Dst: (BUFFER_STORE_BYTE_OFFEN ?:i16:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1947             : /*4376*/          /*Scope*/ 32, /*->4409*/
    1948             : /*4377*/            OPC_CheckPredicate, 27, // Predicate_store
    1949             : /*4379*/            OPC_CheckPredicate, 9, // Predicate_store_private
    1950             : /*4381*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1951             : /*4383*/            OPC_CheckComplexPat, /*CP*/6, /*#*/2, // SelectMUBUFScratchOffen:$ #3 #4 #5 #6
    1952             : /*4386*/            OPC_EmitMergeInputChains1_0,
    1953             : /*4387*/            OPC_EmitInteger, MVT::i1, 0, 
    1954             : /*4390*/            OPC_EmitInteger, MVT::i1, 0, 
    1955             : /*4393*/            OPC_EmitInteger, MVT::i1, 0, 
    1956             : /*4396*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
    1957             :                         8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9, 
    1958             :                     // Src: (st i16:i16:$value, (MUBUFScratchOffen:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 19
    1959             :                     // Dst: (BUFFER_STORE_SHORT_OFFEN ?:i16:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
    1960             : /*4409*/          0, /*End of Scope*/
    1961             : /*4410*/        0, /*End of Scope*/
    1962             : /*4411*/      /*Scope*/ 51, /*->4463*/
    1963             : /*4412*/        OPC_CaptureGlueInput,
    1964             : /*4413*/        OPC_RecordChild1, // #1 = $value
    1965             : /*4414*/        OPC_CheckChild1Type, MVT::v2i32,
    1966             : /*4416*/        OPC_RecordChild2, // #2 = $DS64Bit4ByteAligned:ptr:offset0:offset1
    1967             : /*4417*/        OPC_CheckPredicate, 21, // Predicate_si_st_local
    1968             : /*4419*/        OPC_CheckPredicate, 22, // Predicate_si_store_local
    1969             : /*4421*/        OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    1970             : /*4423*/        OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectDS64Bit4ByteAligned:$ #3 #4 #5
    1971             : /*4426*/        OPC_EmitMergeInputChains1_0,
    1972             : /*4427*/        OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    1973             : /*4430*/        OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
    1974             :                     MVT::i32, 2/*#Ops*/, 1, 6,  // Results = #7
    1975             : /*4438*/        OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    1976             : /*4441*/        OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
    1977             :                     MVT::i32, 2/*#Ops*/, 1, 8,  // Results = #9
    1978             : /*4449*/        OPC_EmitInteger, MVT::i1, 0, 
    1979             : /*4452*/        OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::DS_WRITE2_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    1980             :                     6/*#Ops*/, 3, 7, 9, 4, 5, 10, 
    1981             :                 // Src: (SIst_local v2i32:v2i32:$value, (DS64Bit4ByteAligned:iPTR i32:i32:$ptr, i8:i8:$offset0, i8:i8:$offset1))<<P:Predicate_si_st_local>><<P:Predicate_si_store_local>> - Complexity = 16
    1982             :                 // Dst: (DS_WRITE2_B32 ?:i32:$ptr, (EXTRACT_SUBREG:i32 ?:v2i32:$value, sub0:i32), (EXTRACT_SUBREG:i32 ?:v2i32:$value, sub1:i32), ?:i8:$offset0, ?:i8:$offset1, 0:i1)
    1983             : /*4463*/      /*Scope*/ 28, /*->4492*/
    1984             : /*4464*/        OPC_RecordChild1, // #1 = $val
    1985             : /*4465*/        OPC_CheckChild1Type, MVT::i32,
    1986             : /*4467*/        OPC_RecordChild2, // #2 = $addr
    1987             : /*4468*/        OPC_CheckPredicate, 23, // Predicate_unindexedstore
    1988             : /*4470*/        OPC_CheckPredicate, 27, // Predicate_store
    1989             : /*4472*/        OPC_CheckPredicate, 9, // Predicate_store_private
    1990             : /*4474*/        OPC_CheckPatternPredicate, 5, // (Subtarget->getGeneration() <= R600Subtarget::NORTHERN_ISLANDS)
    1991             : /*4476*/        OPC_CheckComplexPat, /*CP*/7, /*#*/2, // SelectADDRIndirect:$addr #3 #4
    1992             : /*4479*/        OPC_EmitMergeInputChains1_0,
    1993             : /*4480*/        OPC_EmitInteger, MVT::i32, 0, 
    1994             : /*4483*/        OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::R600_RegisterStore), 0|OPFL_Chain|OPFL_MemRefs,
    1995             :                     4/*#Ops*/, 1, 3, 4, 5, 
    1996             :                 // Src: (st i32:i32:$val, ADDRIndirect:iPTR:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 13
    1997             :                 // Dst: (R600_RegisterStore i32:i32:$val, FRAMEri:iPTR:$addr, 0:i32)
    1998             : /*4492*/      /*Scope*/ 19|128,1/*147*/, /*->4641*/
    1999             : /*4494*/        OPC_CaptureGlueInput,
    2000             : /*4495*/        OPC_RecordChild1, // #1 = $value
    2001             : /*4496*/        OPC_Scope, 84, /*->4582*/ // 2 children in Scope
    2002             : /*4498*/          OPC_CheckChild1Type, MVT::i32,
    2003             : /*4500*/          OPC_RecordChild2, // #2 = $DS1Addr1Offset:ptr:offset
    2004             : /*4501*/          OPC_CheckPredicate, 21, // Predicate_si_st_local
    2005             : /*4503*/          OPC_Scope, 52, /*->4557*/ // 2 children in Scope
    2006             : /*4505*/            OPC_CheckPredicate, 24, // Predicate_si_truncstore_local
    2007             : /*4507*/            OPC_Scope, 23, /*->4532*/ // 2 children in Scope
    2008             : /*4509*/              OPC_CheckPredicate, 25, // Predicate_si_truncstore_local_i8
    2009             : /*4511*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2010             : /*4513*/              OPC_CheckComplexPat, /*CP*/9, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
    2011             : /*4516*/              OPC_EmitMergeInputChains1_0,
    2012             : /*4517*/              OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2013             : /*4520*/              OPC_EmitInteger, MVT::i1, 0, 
    2014             : /*4523*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::DS_WRITE_B8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    2015             :                           4/*#Ops*/, 3, 1, 5, 6, 
    2016             :                       // Src: (SIst_local i32:i32:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_truncstore_local>><<P:Predicate_si_truncstore_local_i8>> - Complexity = 13
    2017             :                       // Dst: (DS_WRITE_B8 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
    2018             : /*4532*/            /*Scope*/ 23, /*->4556*/
    2019             : /*4533*/              OPC_CheckPredicate, 26, // Predicate_si_truncstore_local_i16
    2020             : /*4535*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2021             : /*4537*/              OPC_CheckComplexPat, /*CP*/9, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
    2022             : /*4540*/              OPC_EmitMergeInputChains1_0,
    2023             : /*4541*/              OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2024             : /*4544*/              OPC_EmitInteger, MVT::i1, 0, 
    2025             : /*4547*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::DS_WRITE_B16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    2026             :                           4/*#Ops*/, 3, 1, 5, 6, 
    2027             :                       // Src: (SIst_local i32:i32:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_truncstore_local>><<P:Predicate_si_truncstore_local_i16>> - Complexity = 13
    2028             :                       // Dst: (DS_WRITE_B16 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
    2029             : /*4556*/            0, /*End of Scope*/
    2030             : /*4557*/          /*Scope*/ 23, /*->4581*/
    2031             : /*4558*/            OPC_CheckPredicate, 22, // Predicate_si_store_local
    2032             : /*4560*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2033             : /*4562*/            OPC_CheckComplexPat, /*CP*/9, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
    2034             : /*4565*/            OPC_EmitMergeInputChains1_0,
    2035             : /*4566*/            OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2036             : /*4569*/            OPC_EmitInteger, MVT::i1, 0, 
    2037             : /*4572*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::DS_WRITE_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    2038             :                         4/*#Ops*/, 3, 1, 5, 6, 
    2039             :                     // Src: (SIst_local i32:i32:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_store_local>> - Complexity = 13
    2040             :                     // Dst: (DS_WRITE_B32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
    2041             : /*4581*/          0, /*End of Scope*/
    2042             : /*4582*/        /*Scope*/ 57, /*->4640*/
    2043             : /*4583*/          OPC_CheckChild1Type, MVT::i16,
    2044             : /*4585*/          OPC_RecordChild2, // #2 = $DS1Addr1Offset:ptr:offset
    2045             : /*4586*/          OPC_CheckPredicate, 21, // Predicate_si_st_local
    2046             : /*4588*/          OPC_Scope, 25, /*->4615*/ // 2 children in Scope
    2047             : /*4590*/            OPC_CheckPredicate, 24, // Predicate_si_truncstore_local
    2048             : /*4592*/            OPC_CheckPredicate, 25, // Predicate_si_truncstore_local_i8
    2049             : /*4594*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2050             : /*4596*/            OPC_CheckComplexPat, /*CP*/9, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
    2051             : /*4599*/            OPC_EmitMergeInputChains1_0,
    2052             : /*4600*/            OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2053             : /*4603*/            OPC_EmitInteger, MVT::i1, 0, 
    2054             : /*4606*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::DS_WRITE_B8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    2055             :                         4/*#Ops*/, 3, 1, 5, 6, 
    2056             :                     // Src: (SIst_local i16:i16:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_truncstore_local>><<P:Predicate_si_truncstore_local_i8>> - Complexity = 13
    2057             :                     // Dst: (DS_WRITE_B8 ?:i32:$ptr, ?:i16:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
    2058             : /*4615*/          /*Scope*/ 23, /*->4639*/
    2059             : /*4616*/            OPC_CheckPredicate, 22, // Predicate_si_store_local
    2060             : /*4618*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2061             : /*4620*/            OPC_CheckComplexPat, /*CP*/9, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
    2062             : /*4623*/            OPC_EmitMergeInputChains1_0,
    2063             : /*4624*/            OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2064             : /*4627*/            OPC_EmitInteger, MVT::i1, 0, 
    2065             : /*4630*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::DS_WRITE_B16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
    2066             :                         4/*#Ops*/, 3, 1, 5, 6, 
    2067             :                     // Src: (SIst_local i16:i16:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_store_local>> - Complexity = 13
    2068             :                     // Dst: (DS_WRITE_B16 ?:i32:$ptr, ?:i16:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
    2069             : /*4639*/          0, /*End of Scope*/
    2070             : /*4640*/        0, /*End of Scope*/
    2071             : /*4641*/      /*Scope*/ 40|128,5/*680*/, /*->5323*/
    2072             : /*4643*/        OPC_RecordChild1, // #1 = $data
    2073             : /*4644*/        OPC_Scope, 7|128,3/*391*/, /*->5038*/ // 4 children in Scope
    2074             : /*4647*/          OPC_CheckChild1Type, MVT::i32,
    2075             : /*4649*/          OPC_RecordChild2, // #2 = $FLATOffsetSigned:vaddr:offset:slc
    2076             : /*4650*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    2077             : /*4652*/          OPC_Scope, 52, /*->4706*/ // 5 children in Scope
    2078             : /*4654*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    2079             : /*4656*/            OPC_Scope, 23, /*->4681*/ // 2 children in Scope
    2080             : /*4658*/              OPC_CheckPredicate, 25, // Predicate_truncstorei8
    2081             : /*4660*/              OPC_CheckPredicate, 17, // Predicate_truncstorei8_global
    2082             : /*4662*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    2083             : /*4664*/              OPC_CheckComplexPat, /*CP*/10, /*#*/2, // SelectFlatOffset<true>:$ #3 #4 #5
    2084             : /*4667*/              OPC_EmitMergeInputChains1_0,
    2085             : /*4668*/              OPC_EmitInteger, MVT::i1, 0, 
    2086             : /*4671*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::GLOBAL_STORE_BYTE), 0|OPFL_Chain|OPFL_MemRefs,
    2087             :                           5/*#Ops*/, 3, 1, 4, 6, 5, 
    2088             :                       // Src: (st i32:i32:$data, (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> - Complexity = 7
    2089             :                       // Dst: (GLOBAL_STORE_BYTE ?:i64:$vaddr, ?:i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2090             : /*4681*/            /*Scope*/ 23, /*->4705*/
    2091             : /*4682*/              OPC_CheckPredicate, 26, // Predicate_truncstorei16
    2092             : /*4684*/              OPC_CheckPredicate, 17, // Predicate_truncstorei16_global
    2093             : /*4686*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    2094             : /*4688*/              OPC_CheckComplexPat, /*CP*/10, /*#*/2, // SelectFlatOffset<true>:$ #3 #4 #5
    2095             : /*4691*/              OPC_EmitMergeInputChains1_0,
    2096             : /*4692*/              OPC_EmitInteger, MVT::i1, 0, 
    2097             : /*4695*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::GLOBAL_STORE_SHORT), 0|OPFL_Chain|OPFL_MemRefs,
    2098             :                           5/*#Ops*/, 3, 1, 4, 6, 5, 
    2099             :                       // Src: (st i32:i32:$data, (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> - Complexity = 7
    2100             :                       // Dst: (GLOBAL_STORE_SHORT ?:i64:$vaddr, ?:i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2101             : /*4705*/            0, /*End of Scope*/
    2102             : /*4706*/          /*Scope*/ 87, /*->4794*/
    2103             : /*4707*/            OPC_CheckPredicate, 27, // Predicate_store
    2104             : /*4709*/            OPC_Scope, 21, /*->4732*/ // 2 children in Scope
    2105             : /*4711*/              OPC_CheckPredicate, 17, // Predicate_global_store
    2106             : /*4713*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    2107             : /*4715*/              OPC_CheckComplexPat, /*CP*/10, /*#*/2, // SelectFlatOffset<true>:$ #3 #4 #5
    2108             : /*4718*/              OPC_EmitMergeInputChains1_0,
    2109             : /*4719*/              OPC_EmitInteger, MVT::i1, 0, 
    2110             : /*4722*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::GLOBAL_STORE_DWORD), 0|OPFL_Chain|OPFL_MemRefs,
    2111             :                           5/*#Ops*/, 3, 1, 4, 6, 5, 
    2112             :                       // Src: (st i32:i32:$data, (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 7
    2113             :                       // Dst: (GLOBAL_STORE_DWORD ?:i64:$vaddr, ?:i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2114             : /*4732*/            /*Scope*/ 60, /*->4793*/
    2115             : /*4733*/              OPC_CheckChild2Type, MVT::i32,
    2116             : /*4735*/              OPC_CheckPredicate, 18, // Predicate_local_store
    2117             : /*4737*/              OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
    2118             : /*4739*/              OPC_EmitMergeInputChains1_0,
    2119             : /*4740*/              OPC_EmitInteger, MVT::i32, 0, 
    2120             : /*4743*/              OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    2121             : /*4755*/              OPC_EmitInteger, MVT::i32, 0, 
    2122             : /*4758*/              OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    2123             : /*4770*/              OPC_EmitInteger, MVT::i32, 1, 
    2124             : /*4773*/              OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
    2125             : /*4776*/              OPC_EmitInteger, MVT::i32, 0, 
    2126             : /*4779*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::LDS_WRITE), 0|OPFL_Chain|OPFL_MemRefs,
    2127             :                           9/*#Ops*/, 2, 3, 4, 1, 5, 6, 7, 8, 9, 
    2128             :                       // Src: (st R600_Reg32:i32:$src1, R600_Reg32:i32:$src0)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_local_store>> - Complexity = 4
    2129             :                       // Dst: (LDS_WRITE R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
    2130             : /*4793*/            0, /*End of Scope*/
    2131             : /*4794*/          /*Scope*/ 36|128,1/*164*/, /*->4960*/
    2132             : /*4796*/            OPC_CheckChild2Type, MVT::i32,
    2133             : /*4798*/            OPC_Scope, 126, /*->4926*/ // 2 children in Scope
    2134             : /*4800*/              OPC_CheckPredicate, 24, // Predicate_truncstore
    2135             : /*4802*/              OPC_Scope, 60, /*->4864*/ // 2 children in Scope
    2136             : /*4804*/                OPC_CheckPredicate, 25, // Predicate_truncstorei8
    2137             : /*4806*/                OPC_CheckPredicate, 18, // Predicate_truncstorei8_local
    2138             : /*4808*/                OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
    2139             : /*4810*/                OPC_EmitMergeInputChains1_0,
    2140             : /*4811*/                OPC_EmitInteger, MVT::i32, 0, 
    2141             : /*4814*/                OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    2142             : /*4826*/                OPC_EmitInteger, MVT::i32, 0, 
    2143             : /*4829*/                OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    2144             : /*4841*/                OPC_EmitInteger, MVT::i32, 1, 
    2145             : /*4844*/                OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
    2146             : /*4847*/                OPC_EmitInteger, MVT::i32, 0, 
    2147             : /*4850*/                OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::LDS_BYTE_WRITE), 0|OPFL_Chain|OPFL_MemRefs,
    2148             :                             9/*#Ops*/, 2, 3, 4, 1, 5, 6, 7, 8, 9, 
    2149             :                         // Src: (st i32:i32:$src1, i32:i32:$src0)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>> - Complexity = 4
    2150             :                         // Dst: (LDS_BYTE_WRITE i32:i32:$src0, i32:i32:$src1)
    2151             : /*4864*/              /*Scope*/ 60, /*->4925*/
    2152             : /*4865*/                OPC_CheckPredicate, 26, // Predicate_truncstorei16
    2153             : /*4867*/                OPC_CheckPredicate, 18, // Predicate_truncstorei16_local
    2154             : /*4869*/                OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
    2155             : /*4871*/                OPC_EmitMergeInputChains1_0,
    2156             : /*4872*/                OPC_EmitInteger, MVT::i32, 0, 
    2157             : /*4875*/                OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    2158             : /*4887*/                OPC_EmitInteger, MVT::i32, 0, 
    2159             : /*4890*/                OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/, 
    2160             : /*4902*/                OPC_EmitInteger, MVT::i32, 1, 
    2161             : /*4905*/                OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
    2162             : /*4908*/                OPC_EmitInteger, MVT::i32, 0, 
    2163             : /*4911*/                OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::LDS_SHORT_WRITE), 0|OPFL_Chain|OPFL_MemRefs,
    2164             :                             9/*#Ops*/, 2, 3, 4, 1, 5, 6, 7, 8, 9, 
    2165             :                         // Src: (st i32:i32:$src1, i32:i32:$src0)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>> - Complexity = 4
    2166             :                         // Dst: (LDS_SHORT_WRITE i32:i32:$src0, i32:i32:$src1)
    2167             : /*4925*/              0, /*End of Scope*/
    2168             : /*4926*/            /*Scope*/ 32, /*->4959*/
    2169             : /*4927*/              OPC_CheckPredicate, 27, // Predicate_store
    2170             : /*4929*/              OPC_CheckPredicate, 17, // Predicate_global_store
    2171             : /*4931*/              OPC_Scope, 10, /*->4943*/ // 2 children in Scope
    2172             : /*4933*/                OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    2173             : /*4935*/                OPC_EmitMergeInputChains1_0,
    2174             : /*4936*/                OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::RAT_STORE_DWORD32), 0|OPFL_Chain|OPFL_MemRefs,
    2175             :                             2/*#Ops*/, 1, 2, 
    2176             :                         // Src: (st i32:i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
    2177             :                         // Dst: (RAT_STORE_DWORD32 i32:i32:$rw_gpr, i32:i32:$index_gpr)
    2178             : /*4943*/              /*Scope*/ 14, /*->4958*/
    2179             : /*4944*/                OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    2180             : /*4946*/                OPC_EmitMergeInputChains1_0,
    2181             : /*4947*/                OPC_EmitInteger, MVT::i32, 0, 
    2182             : /*4950*/                OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::RAT_WRITE_CACHELESS_32_eg), 0|OPFL_Chain|OPFL_MemRefs,
    2183             :                             3/*#Ops*/, 1, 2, 3, 
    2184             :                         // Src: (st i32:i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
    2185             :                         // Dst: (RAT_WRITE_CACHELESS_32_eg i32:i32:$rw_gpr, i32:i32:$index_gpr)
    2186             : /*4958*/              0, /*End of Scope*/
    2187             : /*4959*/            0, /*End of Scope*/
    2188             : /*4960*/          /*Scope*/ 52, /*->5013*/
    2189             : /*4961*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    2190             : /*4963*/            OPC_Scope, 23, /*->4988*/ // 2 children in Scope
    2191             : /*4965*/              OPC_CheckPredicate, 25, // Predicate_truncstorei8
    2192             : /*4967*/              OPC_CheckPredicate, 28, // Predicate_flat_truncstorei8
    2193             : /*4969*/              OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    2194             : /*4971*/              OPC_CheckComplexPat, /*CP*/11, /*#*/2, // SelectFlatOffset<false>:$ #3 #4 #5
    2195             : /*4974*/              OPC_EmitMergeInputChains1_0,
    2196             : /*4975*/              OPC_EmitInteger, MVT::i1, 0, 
    2197             : /*4978*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::FLAT_STORE_BYTE), 0|OPFL_Chain|OPFL_MemRefs,
    2198             :                           5/*#Ops*/, 3, 1, 4, 6, 5, 
    2199             :                       // Src: (st i32:i32:$data, (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_flat_truncstorei8>> - Complexity = -3
    2200             :                       // Dst: (FLAT_STORE_BYTE ?:i64:$vaddr, ?:i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2201             : /*4988*/            /*Scope*/ 23, /*->5012*/
    2202             : /*4989*/              OPC_CheckPredicate, 26, // Predicate_truncstorei16
    2203             : /*4991*/              OPC_CheckPredicate, 28, // Predicate_flat_truncstorei16
    2204             : /*4993*/              OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    2205             : /*4995*/              OPC_CheckComplexPat, /*CP*/11, /*#*/2, // SelectFlatOffset<false>:$ #3 #4 #5
    2206             : /*4998*/              OPC_EmitMergeInputChains1_0,
    2207             : /*4999*/              OPC_EmitInteger, MVT::i1, 0, 
    2208             : /*5002*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::FLAT_STORE_SHORT), 0|OPFL_Chain|OPFL_MemRefs,
    2209             :                           5/*#Ops*/, 3, 1, 4, 6, 5, 
    2210             :                       // Src: (st i32:i32:$data, (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_flat_truncstorei16>> - Complexity = -3
    2211             :                       // Dst: (FLAT_STORE_SHORT ?:i64:$vaddr, ?:i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2212             : /*5012*/            0, /*End of Scope*/
    2213             : /*5013*/          /*Scope*/ 23, /*->5037*/
    2214             : /*5014*/            OPC_CheckPredicate, 27, // Predicate_store
    2215             : /*5016*/            OPC_CheckPredicate, 28, // Predicate_flat_store
    2216             : /*5018*/            OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    2217             : /*5020*/            OPC_CheckComplexPat, /*CP*/11, /*#*/2, // SelectFlatOffset<false>:$ #3 #4 #5
    2218             : /*5023*/            OPC_EmitMergeInputChains1_0,
    2219             : /*5024*/            OPC_EmitInteger, MVT::i1, 0, 
    2220             : /*5027*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::FLAT_STORE_DWORD), 0|OPFL_Chain|OPFL_MemRefs,
    2221             :                         5/*#Ops*/, 3, 1, 4, 6, 5, 
    2222             :                     // Src: (st i32:i32:$data, (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_flat_store>> - Complexity = -3
    2223             :                     // Dst: (FLAT_STORE_DWORD ?:i64:$vaddr, ?:i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2224             : /*5037*/          0, /*End of Scope*/
    2225             : /*5038*/        /*Scope*/ 107, /*->5146*/
    2226             : /*5039*/          OPC_CheckChild1Type, MVT::i16,
    2227             : /*5041*/          OPC_RecordChild2, // #2 = $FLATOffsetSigned:vaddr:offset:slc
    2228             : /*5042*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    2229             : /*5044*/          OPC_Scope, 25, /*->5071*/ // 4 children in Scope
    2230             : /*5046*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    2231             : /*5048*/            OPC_CheckPredicate, 25, // Predicate_truncstorei8
    2232             : /*5050*/            OPC_CheckPredicate, 17, // Predicate_truncstorei8_global
    2233             : /*5052*/            OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    2234             : /*5054*/            OPC_CheckComplexPat, /*CP*/10, /*#*/2, // SelectFlatOffset<true>:$ #3 #4 #5
    2235             : /*5057*/            OPC_EmitMergeInputChains1_0,
    2236             : /*5058*/            OPC_EmitInteger, MVT::i1, 0, 
    2237             : /*5061*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::GLOBAL_STORE_BYTE), 0|OPFL_Chain|OPFL_MemRefs,
    2238             :                         5/*#Ops*/, 3, 1, 4, 6, 5, 
    2239             :                     // Src: (st i16:i16:$data, (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> - Complexity = 7
    2240             :                     // Dst: (GLOBAL_STORE_BYTE ?:i64:$vaddr, ?:i16:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2241             : /*5071*/          /*Scope*/ 23, /*->5095*/
    2242             : /*5072*/            OPC_CheckPredicate, 27, // Predicate_store
    2243             : /*5074*/            OPC_CheckPredicate, 17, // Predicate_global_store
    2244             : /*5076*/            OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    2245             : /*5078*/            OPC_CheckComplexPat, /*CP*/10, /*#*/2, // SelectFlatOffset<true>:$ #3 #4 #5
    2246             : /*5081*/            OPC_EmitMergeInputChains1_0,
    2247             : /*5082*/            OPC_EmitInteger, MVT::i1, 0, 
    2248             : /*5085*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::GLOBAL_STORE_SHORT), 0|OPFL_Chain|OPFL_MemRefs,
    2249             :                         5/*#Ops*/, 3, 1, 4, 6, 5, 
    2250             :                     // Src: (st i16:i16:$data, (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 7
    2251             :                     // Dst: (GLOBAL_STORE_SHORT ?:i64:$vaddr, ?:i16:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2252             : /*5095*/          /*Scope*/ 25, /*->5121*/
    2253             : /*5096*/            OPC_CheckPredicate, 24, // Predicate_truncstore
    2254             : /*5098*/            OPC_CheckPredicate, 25, // Predicate_truncstorei8
    2255             : /*5100*/            OPC_CheckPredicate, 28, // Predicate_flat_truncstorei8
    2256             : /*5102*/            OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    2257             : /*5104*/            OPC_CheckComplexPat, /*CP*/11, /*#*/2, // SelectFlatOffset<false>:$ #3 #4 #5
    2258             : /*5107*/            OPC_EmitMergeInputChains1_0,
    2259             : /*5108*/            OPC_EmitInteger, MVT::i1, 0, 
    2260             : /*5111*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::FLAT_STORE_BYTE), 0|OPFL_Chain|OPFL_MemRefs,
    2261             :                         5/*#Ops*/, 3, 1, 4, 6, 5, 
    2262             :                     // Src: (st i16:i16:$data, (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_flat_truncstorei8>> - Complexity = -3
    2263             :                     // Dst: (FLAT_STORE_BYTE ?:i64:$vaddr, ?:i16:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2264             : /*5121*/          /*Scope*/ 23, /*->5145*/
    2265             : /*5122*/            OPC_CheckPredicate, 27, // Predicate_store
    2266             : /*5124*/            OPC_CheckPredicate, 28, // Predicate_flat_store
    2267             : /*5126*/            OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    2268             : /*5128*/            OPC_CheckComplexPat, /*CP*/11, /*#*/2, // SelectFlatOffset<false>:$ #3 #4 #5
    2269             : /*5131*/            OPC_EmitMergeInputChains1_0,
    2270             : /*5132*/            OPC_EmitInteger, MVT::i1, 0, 
    2271             : /*5135*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::FLAT_STORE_SHORT), 0|OPFL_Chain|OPFL_MemRefs,
    2272             :                         5/*#Ops*/, 3, 1, 4, 6, 5, 
    2273             :                     // Src: (st i16:i16:$data, (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_flat_store>> - Complexity = -3
    2274             :                     // Dst: (FLAT_STORE_SHORT ?:i64:$vaddr, ?:i16:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2275             : /*5145*/          0, /*End of Scope*/
    2276             : /*5146*/        /*Scope*/ 87, /*->5234*/
    2277             : /*5147*/          OPC_CheckChild1Type, MVT::v2i32,
    2278             : /*5149*/          OPC_RecordChild2, // #2 = $FLATOffsetSigned:vaddr:offset:slc
    2279             : /*5150*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    2280             : /*5152*/          OPC_CheckPredicate, 27, // Predicate_store
    2281             : /*5154*/          OPC_Scope, 55, /*->5211*/ // 2 children in Scope
    2282             : /*5156*/            OPC_CheckPredicate, 17, // Predicate_global_store
    2283             : /*5158*/            OPC_Scope, 19, /*->5179*/ // 2 children in Scope
    2284             : /*5160*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    2285             : /*5162*/              OPC_CheckComplexPat, /*CP*/10, /*#*/2, // SelectFlatOffset<true>:$ #3 #4 #5
    2286             : /*5165*/              OPC_EmitMergeInputChains1_0,
    2287             : /*5166*/              OPC_EmitInteger, MVT::i1, 0, 
    2288             : /*5169*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::GLOBAL_STORE_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
    2289             :                           5/*#Ops*/, 3, 1, 4, 6, 5, 
    2290             :                       // Src: (st v2i32:v2i32:$data, (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 7
    2291             :                       // Dst: (GLOBAL_STORE_DWORDX2 ?:i64:$vaddr, ?:v2i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2292             : /*5179*/            /*Scope*/ 30, /*->5210*/
    2293             : /*5180*/              OPC_CheckChild2Type, MVT::i32,
    2294             : /*5182*/              OPC_Scope, 10, /*->5194*/ // 2 children in Scope
    2295             : /*5184*/                OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    2296             : /*5186*/                OPC_EmitMergeInputChains1_0,
    2297             : /*5187*/                OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::RAT_STORE_DWORD64), 0|OPFL_Chain|OPFL_MemRefs,
    2298             :                             2/*#Ops*/, 1, 2, 
    2299             :                         // Src: (st v2i32:v2i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
    2300             :                         // Dst: (RAT_STORE_DWORD64 v2i32:v2i32:$rw_gpr, i32:i32:$index_gpr)
    2301             : /*5194*/              /*Scope*/ 14, /*->5209*/
    2302             : /*5195*/                OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    2303             : /*5197*/                OPC_EmitMergeInputChains1_0,
    2304             : /*5198*/                OPC_EmitInteger, MVT::i32, 0, 
    2305             : /*5201*/                OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::RAT_WRITE_CACHELESS_64_eg), 0|OPFL_Chain|OPFL_MemRefs,
    2306             :                             3/*#Ops*/, 1, 2, 3, 
    2307             :                         // Src: (st v2i32:v2i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
    2308             :                         // Dst: (RAT_WRITE_CACHELESS_64_eg v2i32:v2i32:$rw_gpr, i32:i32:$index_gpr)
    2309             : /*5209*/              0, /*End of Scope*/
    2310             : /*5210*/            0, /*End of Scope*/
    2311             : /*5211*/          /*Scope*/ 21, /*->5233*/
    2312             : /*5212*/            OPC_CheckPredicate, 28, // Predicate_flat_store
    2313             : /*5214*/            OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    2314             : /*5216*/            OPC_CheckComplexPat, /*CP*/11, /*#*/2, // SelectFlatOffset<false>:$ #3 #4 #5
    2315             : /*5219*/            OPC_EmitMergeInputChains1_0,
    2316             : /*5220*/            OPC_EmitInteger, MVT::i1, 0, 
    2317             : /*5223*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::FLAT_STORE_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
    2318             :                         5/*#Ops*/, 3, 1, 4, 6, 5, 
    2319             :                     // Src: (st v2i32:v2i32:$data, (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_flat_store>> - Complexity = -3
    2320             :                     // Dst: (FLAT_STORE_DWORDX2 ?:i64:$vaddr, ?:v2i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2321             : /*5233*/          0, /*End of Scope*/
    2322             : /*5234*/        /*Scope*/ 87, /*->5322*/
    2323             : /*5235*/          OPC_CheckChild1Type, MVT::v4i32,
    2324             : /*5237*/          OPC_RecordChild2, // #2 = $FLATOffsetSigned:vaddr:offset:slc
    2325             : /*5238*/          OPC_CheckPredicate, 23, // Predicate_unindexedstore
    2326             : /*5240*/          OPC_CheckPredicate, 27, // Predicate_store
    2327             : /*5242*/          OPC_Scope, 55, /*->5299*/ // 2 children in Scope
    2328             : /*5244*/            OPC_CheckPredicate, 17, // Predicate_global_store
    2329             : /*5246*/            OPC_Scope, 19, /*->5267*/ // 2 children in Scope
    2330             : /*5248*/              OPC_CheckPatternPredicate, 8, // (Subtarget->hasFlatGlobalInsts())
    2331             : /*5250*/              OPC_CheckComplexPat, /*CP*/10, /*#*/2, // SelectFlatOffset<true>:$ #3 #4 #5
    2332             : /*5253*/              OPC_EmitMergeInputChains1_0,
    2333             : /*5254*/              OPC_EmitInteger, MVT::i1, 0, 
    2334             : /*5257*/              OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::GLOBAL_STORE_DWORDX4), 0|OPFL_Chain|OPFL_MemRefs,
    2335             :                           5/*#Ops*/, 3, 1, 4, 6, 5, 
    2336             :                       // Src: (st v4i32:v4i32:$data, (FLATOffsetSigned:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 7
    2337             :                       // Dst: (GLOBAL_STORE_DWORDX4 ?:i64:$vaddr, ?:v4i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2338             : /*5267*/            /*Scope*/ 30, /*->5298*/
    2339             : /*5268*/              OPC_CheckChild2Type, MVT::i32,
    2340             : /*5270*/              OPC_Scope, 10, /*->5282*/ // 2 children in Scope
    2341             : /*5272*/                OPC_CheckPatternPredicate, 7, // (Subtarget->hasCaymanISA())
    2342             : /*5274*/                OPC_EmitMergeInputChains1_0,
    2343             : /*5275*/                OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::RAT_STORE_DWORD128), 0|OPFL_Chain|OPFL_MemRefs,
    2344             :                             2/*#Ops*/, 1, 2, 
    2345             :                         // Src: (st v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
    2346             :                         // Dst: (RAT_STORE_DWORD128 v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)
    2347             : /*5282*/              /*Scope*/ 14, /*->5297*/
    2348             : /*5283*/                OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
    2349             : /*5285*/                OPC_EmitMergeInputChains1_0,
    2350             : /*5286*/                OPC_EmitInteger, MVT::i32, 0, 
    2351             : /*5289*/                OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::RAT_WRITE_CACHELESS_128_eg), 0|OPFL_Chain|OPFL_MemRefs,
    2352             :                             3/*#Ops*/, 1, 2, 3, 
    2353             :                         // Src: (st v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
    2354             :                         // Dst: (RAT_WRITE_CACHELESS_128_eg v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)
    2355             : /*5297*/              0, /*End of Scope*/
    2356             : /*5298*/            0, /*End of Scope*/
    2357             : /*5299*/          /*Scope*/ 21, /*->5321*/
    2358             : /*5300*/            OPC_CheckPredicate, 28, // Predicate_flat_store
    2359             : /*5302*/            OPC_CheckPatternPredicate, 10, // (Subtarget->hasFlatAddressSpace())
    2360             : /*5304*/            OPC_CheckComplexPat, /*CP*/11, /*#*/2, // SelectFlatOffset<false>:$ #3 #4 #5
    2361             : /*5307*/            OPC_EmitMergeInputChains1_0,
    2362             : /*5308*/            OPC_EmitInteger, MVT::i1, 0, 
    2363             : /*5311*/            OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::FLAT_STORE_DWORDX4), 0|OPFL_Chain|OPFL_MemRefs,
    2364             :                         5/*#Ops*/, 3, 1, 4, 6, 5, 
    2365             :                     // Src: (st v4i32:v4i32:$data, (FLATOffset:iPTR i64:i64:$vaddr, i16:i16:$offset, i1:i1:$slc))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_flat_store>> - Complexity = -3
    2366             :                     // Dst: (FLAT_STORE_DWORDX4 ?:i64:$vaddr, ?:v4i32:$data, ?:i16:$offset, 0:i1, ?:i1:$slc)
    2367             : /*5321*/          0, /*End of Scope*/
    2368             : /*5322*/        0, /*End of Scope*/
    2369             : /*5323*/      0, /*End of Scope*/
    2370             : /*5324*/    /*SwitchOpcode*/ 101|128,69|128,3/*58085*/, TARGET_VAL(ISD::INTRINSIC_W_CHAIN),// ->63414
    2371             : /*5329*/      OPC_RecordNode, // #0 = 'intrinsic_w_chain' chained node
    2372             : /*5330*/      OPC_Scope, 53|128,5/*693*/, /*->6026*/ // 96 children in Scope
    2373             : /*5333*/        OPC_CheckChild1Integer, 121|128,47/*6137*/, 
    2374             : /*5336*/        OPC_RecordChild2, // #1 = $rsrc
    2375             : /*5337*/        OPC_CheckChild2Type, MVT::v4i32,
    2376             : /*5339*/        OPC_Scope, 72, /*->5413*/ // 4 children in Scope
    2377             : /*5341*/          OPC_MoveChild3,
    2378             : /*5342*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2379             : /*5345*/          OPC_CheckType, MVT::i32,
    2380             : /*5347*/          OPC_MoveParent,
    2381             : /*5348*/          OPC_RecordChild4, // #2 = $soffset
    2382             : /*5349*/          OPC_RecordChild5, // #3 = $offset
    2383             : /*5350*/          OPC_MoveChild5,
    2384             : /*5351*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2385             : /*5354*/          OPC_MoveParent,
    2386             : /*5355*/          OPC_MoveChild6,
    2387             : /*5356*/          OPC_CheckInteger, 0, 
    2388             : /*5358*/          OPC_MoveParent,
    2389             : /*5359*/          OPC_MoveChild7,
    2390             : /*5360*/          OPC_CheckInteger, 0, 
    2391             : /*5362*/          OPC_MoveParent,
    2392             : /*5363*/          OPC_MoveChild, 8,
    2393             : /*5365*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2394             : /*5368*/          OPC_RecordNode, // #4 = $glc
    2395             : /*5369*/          OPC_MoveParent,
    2396             : /*5370*/          OPC_MoveChild, 9,
    2397             : /*5372*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2398             : /*5375*/          OPC_RecordNode, // #5 = $slc
    2399             : /*5376*/          OPC_MoveParent,
    2400             : /*5377*/          OPC_MoveChild, 10,
    2401             : /*5379*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2402             : /*5382*/          OPC_RecordNode, // #6 = $tfe
    2403             : /*5383*/          OPC_MoveParent,
    2404             : /*5384*/          OPC_CheckType, MVT::i32,
    2405             : /*5386*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2406             : /*5388*/          OPC_EmitMergeInputChains1_0,
    2407             : /*5389*/          OPC_EmitNodeXForm, 0, 3, // as_i16imm
    2408             : /*5392*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2409             : /*5395*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2410             : /*5398*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2411             : /*5401*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain,
    2412             :                       MVT::i32, 6/*#Ops*/, 1, 2, 7, 8, 9, 10, 
    2413             :                   // Src: (intrinsic_w_chain:i32 6137:iPTR, v4i32:v4i32:$rsrc, (imm:i32), i32:i32:$soffset, (imm:i32):$offset, 0:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 33
    2414             :                   // Dst: (BUFFER_LOAD_DWORD_OFFSET:i32 ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2415             : /*5413*/        /*Scope*/ 76|128,1/*204*/, /*->5619*/
    2416             : /*5415*/          OPC_RecordChild3, // #2 = $vaddr
    2417             : /*5416*/          OPC_Scope, 2|128,1/*130*/, /*->5549*/ // 2 children in Scope
    2418             : /*5419*/            OPC_CheckChild3Type, MVT::i32,
    2419             : /*5421*/            OPC_RecordChild4, // #3 = $soffset
    2420             : /*5422*/            OPC_RecordChild5, // #4 = $offset
    2421             : /*5423*/            OPC_MoveChild5,
    2422             : /*5424*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2423             : /*5427*/            OPC_MoveParent,
    2424             : /*5428*/            OPC_MoveChild6,
    2425             : /*5429*/            OPC_Scope, 58, /*->5489*/ // 2 children in Scope
    2426             : /*5431*/              OPC_CheckInteger, 1, 
    2427             : /*5433*/              OPC_MoveParent,
    2428             : /*5434*/              OPC_MoveChild7,
    2429             : /*5435*/              OPC_CheckInteger, 0, 
    2430             : /*5437*/              OPC_MoveParent,
    2431             : /*5438*/              OPC_MoveChild, 8,
    2432             : /*5440*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2433             : /*5443*/              OPC_RecordNode, // #5 = $glc
    2434             : /*5444*/              OPC_MoveParent,
    2435             : /*5445*/              OPC_MoveChild, 9,
    2436             : /*5447*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2437             : /*5450*/              OPC_RecordNode, // #6 = $slc
    2438             : /*5451*/              OPC_MoveParent,
    2439             : /*5452*/              OPC_MoveChild, 10,
    2440             : /*5454*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2441             : /*5457*/              OPC_RecordNode, // #7 = $tfe
    2442             : /*5458*/              OPC_MoveParent,
    2443             : /*5459*/              OPC_CheckType, MVT::i32,
    2444             : /*5461*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2445             : /*5463*/              OPC_EmitMergeInputChains1_0,
    2446             : /*5464*/              OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2447             : /*5467*/              OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2448             : /*5470*/              OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2449             : /*5473*/              OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2450             : /*5476*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), 0|OPFL_Chain,
    2451             :                           MVT::i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2452             :                       // Src: (intrinsic_w_chain:i32 6137:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2453             :                       // Dst: (BUFFER_LOAD_DWORD_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2454             : /*5489*/            /*Scope*/ 58, /*->5548*/
    2455             : /*5490*/              OPC_CheckInteger, 0, 
    2456             : /*5492*/              OPC_MoveParent,
    2457             : /*5493*/              OPC_MoveChild7,
    2458             : /*5494*/              OPC_CheckInteger, 1, 
    2459             : /*5496*/              OPC_MoveParent,
    2460             : /*5497*/              OPC_MoveChild, 8,
    2461             : /*5499*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2462             : /*5502*/              OPC_RecordNode, // #5 = $glc
    2463             : /*5503*/              OPC_MoveParent,
    2464             : /*5504*/              OPC_MoveChild, 9,
    2465             : /*5506*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2466             : /*5509*/              OPC_RecordNode, // #6 = $slc
    2467             : /*5510*/              OPC_MoveParent,
    2468             : /*5511*/              OPC_MoveChild, 10,
    2469             : /*5513*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2470             : /*5516*/              OPC_RecordNode, // #7 = $tfe
    2471             : /*5517*/              OPC_MoveParent,
    2472             : /*5518*/              OPC_CheckType, MVT::i32,
    2473             : /*5520*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2474             : /*5522*/              OPC_EmitMergeInputChains1_0,
    2475             : /*5523*/              OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2476             : /*5526*/              OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2477             : /*5529*/              OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2478             : /*5532*/              OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2479             : /*5535*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), 0|OPFL_Chain,
    2480             :                           MVT::i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2481             :                       // Src: (intrinsic_w_chain:i32 6137:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 0:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2482             :                       // Dst: (BUFFER_LOAD_DWORD_IDXEN:i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2483             : /*5548*/            0, /*End of Scope*/
    2484             : /*5549*/          /*Scope*/ 68, /*->5618*/
    2485             : /*5550*/            OPC_CheckChild3Type, MVT::v2i32,
    2486             : /*5552*/            OPC_RecordChild4, // #3 = $soffset
    2487             : /*5553*/            OPC_RecordChild5, // #4 = $offset
    2488             : /*5554*/            OPC_MoveChild5,
    2489             : /*5555*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2490             : /*5558*/            OPC_MoveParent,
    2491             : /*5559*/            OPC_MoveChild6,
    2492             : /*5560*/            OPC_CheckInteger, 1, 
    2493             : /*5562*/            OPC_MoveParent,
    2494             : /*5563*/            OPC_MoveChild7,
    2495             : /*5564*/            OPC_CheckInteger, 1, 
    2496             : /*5566*/            OPC_MoveParent,
    2497             : /*5567*/            OPC_MoveChild, 8,
    2498             : /*5569*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2499             : /*5572*/            OPC_RecordNode, // #5 = $glc
    2500             : /*5573*/            OPC_MoveParent,
    2501             : /*5574*/            OPC_MoveChild, 9,
    2502             : /*5576*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2503             : /*5579*/            OPC_RecordNode, // #6 = $slc
    2504             : /*5580*/            OPC_MoveParent,
    2505             : /*5581*/            OPC_MoveChild, 10,
    2506             : /*5583*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2507             : /*5586*/            OPC_RecordNode, // #7 = $tfe
    2508             : /*5587*/            OPC_MoveParent,
    2509             : /*5588*/            OPC_CheckType, MVT::i32,
    2510             : /*5590*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2511             : /*5592*/            OPC_EmitMergeInputChains1_0,
    2512             : /*5593*/            OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2513             : /*5596*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2514             : /*5599*/            OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2515             : /*5602*/            OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2516             : /*5605*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), 0|OPFL_Chain,
    2517             :                         MVT::i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2518             :                     // Src: (intrinsic_w_chain:i32 6137:iPTR, v4i32:v4i32:$rsrc, v2i32:v2i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2519             :                     // Dst: (BUFFER_LOAD_DWORD_BOTHEN:i32 ?:v2i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2520             : /*5618*/          0, /*End of Scope*/
    2521             : /*5619*/        /*Scope*/ 103, /*->5723*/
    2522             : /*5620*/          OPC_MoveChild3,
    2523             : /*5621*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2524             : /*5624*/          OPC_CheckType, MVT::i32,
    2525             : /*5626*/          OPC_MoveParent,
    2526             : /*5627*/          OPC_RecordChild4, // #2 = $soffset
    2527             : /*5628*/          OPC_RecordChild5, // #3 = $offset
    2528             : /*5629*/          OPC_MoveChild5,
    2529             : /*5630*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2530             : /*5633*/          OPC_MoveParent,
    2531             : /*5634*/          OPC_MoveChild6,
    2532             : /*5635*/          OPC_CheckInteger, 0, 
    2533             : /*5637*/          OPC_MoveParent,
    2534             : /*5638*/          OPC_MoveChild7,
    2535             : /*5639*/          OPC_CheckInteger, 0, 
    2536             : /*5641*/          OPC_MoveParent,
    2537             : /*5642*/          OPC_MoveChild, 8,
    2538             : /*5644*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2539             : /*5647*/          OPC_RecordNode, // #4 = $glc
    2540             : /*5648*/          OPC_MoveParent,
    2541             : /*5649*/          OPC_MoveChild, 9,
    2542             : /*5651*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2543             : /*5654*/          OPC_RecordNode, // #5 = $slc
    2544             : /*5655*/          OPC_MoveParent,
    2545             : /*5656*/          OPC_MoveChild, 10,
    2546             : /*5658*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2547             : /*5661*/          OPC_RecordNode, // #6 = $tfe
    2548             : /*5662*/          OPC_MoveParent,
    2549             : /*5663*/          OPC_SwitchType /*2 cases */, 27, MVT::v2i32,// ->5693
    2550             : /*5666*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2551             : /*5668*/            OPC_EmitMergeInputChains1_0,
    2552             : /*5669*/            OPC_EmitNodeXForm, 0, 3, // as_i16imm
    2553             : /*5672*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2554             : /*5675*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2555             : /*5678*/            OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2556             : /*5681*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), 0|OPFL_Chain,
    2557             :                         MVT::v2i32, 6/*#Ops*/, 1, 2, 7, 8, 9, 10, 
    2558             :                     // Src: (intrinsic_w_chain:v2i32 6137:iPTR, v4i32:v4i32:$rsrc, (imm:i32), i32:i32:$soffset, (imm:i32):$offset, 0:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 33
    2559             :                     // Dst: (BUFFER_LOAD_DWORDX2_OFFSET:v2i32 ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2560             : /*5693*/          /*SwitchType*/ 27, MVT::v4i32,// ->5722
    2561             : /*5695*/            OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2562             : /*5697*/            OPC_EmitMergeInputChains1_0,
    2563             : /*5698*/            OPC_EmitNodeXForm, 0, 3, // as_i16imm
    2564             : /*5701*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2565             : /*5704*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2566             : /*5707*/            OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2567             : /*5710*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), 0|OPFL_Chain,
    2568             :                         MVT::v4i32, 6/*#Ops*/, 1, 2, 7, 8, 9, 10, 
    2569             :                     // Src: (intrinsic_w_chain:v4i32 6137:iPTR, v4i32:v4i32:$rsrc, (imm:i32), i32:i32:$soffset, (imm:i32):$offset, 0:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 33
    2570             :                     // Dst: (BUFFER_LOAD_DWORDX4_OFFSET:v4i32 ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2571             : /*5722*/          0, // EndSwitchType
    2572             : /*5723*/        /*Scope*/ 44|128,2/*300*/, /*->6025*/
    2573             : /*5725*/          OPC_RecordChild3, // #2 = $vaddr
    2574             : /*5726*/          OPC_Scope, 66|128,1/*194*/, /*->5923*/ // 2 children in Scope
    2575             : /*5729*/            OPC_CheckChild3Type, MVT::i32,
    2576             : /*5731*/            OPC_RecordChild4, // #3 = $soffset
    2577             : /*5732*/            OPC_RecordChild5, // #4 = $offset
    2578             : /*5733*/            OPC_MoveChild5,
    2579             : /*5734*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2580             : /*5737*/            OPC_MoveParent,
    2581             : /*5738*/            OPC_MoveChild6,
    2582             : /*5739*/            OPC_Scope, 90, /*->5831*/ // 2 children in Scope
    2583             : /*5741*/              OPC_CheckInteger, 1, 
    2584             : /*5743*/              OPC_MoveParent,
    2585             : /*5744*/              OPC_MoveChild7,
    2586             : /*5745*/              OPC_CheckInteger, 0, 
    2587             : /*5747*/              OPC_MoveParent,
    2588             : /*5748*/              OPC_MoveChild, 8,
    2589             : /*5750*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2590             : /*5753*/              OPC_RecordNode, // #5 = $glc
    2591             : /*5754*/              OPC_MoveParent,
    2592             : /*5755*/              OPC_MoveChild, 9,
    2593             : /*5757*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2594             : /*5760*/              OPC_RecordNode, // #6 = $slc
    2595             : /*5761*/              OPC_MoveParent,
    2596             : /*5762*/              OPC_MoveChild, 10,
    2597             : /*5764*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2598             : /*5767*/              OPC_RecordNode, // #7 = $tfe
    2599             : /*5768*/              OPC_MoveParent,
    2600             : /*5769*/              OPC_SwitchType /*2 cases */, 28, MVT::v2i32,// ->5800
    2601             : /*5772*/                OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2602             : /*5774*/                OPC_EmitMergeInputChains1_0,
    2603             : /*5775*/                OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2604             : /*5778*/                OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2605             : /*5781*/                OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2606             : /*5784*/                OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2607             : /*5787*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), 0|OPFL_Chain,
    2608             :                             MVT::v2i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2609             :                         // Src: (intrinsic_w_chain:v2i32 6137:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2610             :                         // Dst: (BUFFER_LOAD_DWORDX2_OFFEN:v2i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2611             : /*5800*/              /*SwitchType*/ 28, MVT::v4i32,// ->5830
    2612             : /*5802*/                OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2613             : /*5804*/                OPC_EmitMergeInputChains1_0,
    2614             : /*5805*/                OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2615             : /*5808*/                OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2616             : /*5811*/                OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2617             : /*5814*/                OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2618             : /*5817*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), 0|OPFL_Chain,
    2619             :                             MVT::v4i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2620             :                         // Src: (intrinsic_w_chain:v4i32 6137:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2621             :                         // Dst: (BUFFER_LOAD_DWORDX4_OFFEN:v4i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2622             : /*5830*/              0, // EndSwitchType
    2623             : /*5831*/            /*Scope*/ 90, /*->5922*/
    2624             : /*5832*/              OPC_CheckInteger, 0, 
    2625             : /*5834*/              OPC_MoveParent,
    2626             : /*5835*/              OPC_MoveChild7,
    2627             : /*5836*/              OPC_CheckInteger, 1, 
    2628             : /*5838*/              OPC_MoveParent,
    2629             : /*5839*/              OPC_MoveChild, 8,
    2630             : /*5841*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2631             : /*5844*/              OPC_RecordNode, // #5 = $glc
    2632             : /*5845*/              OPC_MoveParent,
    2633             : /*5846*/              OPC_MoveChild, 9,
    2634             : /*5848*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2635             : /*5851*/              OPC_RecordNode, // #6 = $slc
    2636             : /*5852*/              OPC_MoveParent,
    2637             : /*5853*/              OPC_MoveChild, 10,
    2638             : /*5855*/              OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2639             : /*5858*/              OPC_RecordNode, // #7 = $tfe
    2640             : /*5859*/              OPC_MoveParent,
    2641             : /*5860*/              OPC_SwitchType /*2 cases */, 28, MVT::v2i32,// ->5891
    2642             : /*5863*/                OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2643             : /*5865*/                OPC_EmitMergeInputChains1_0,
    2644             : /*5866*/                OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2645             : /*5869*/                OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2646             : /*5872*/                OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2647             : /*5875*/                OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2648             : /*5878*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), 0|OPFL_Chain,
    2649             :                             MVT::v2i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2650             :                         // Src: (intrinsic_w_chain:v2i32 6137:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 0:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2651             :                         // Dst: (BUFFER_LOAD_DWORDX2_IDXEN:v2i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2652             : /*5891*/              /*SwitchType*/ 28, MVT::v4i32,// ->5921
    2653             : /*5893*/                OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2654             : /*5895*/                OPC_EmitMergeInputChains1_0,
    2655             : /*5896*/                OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2656             : /*5899*/                OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2657             : /*5902*/                OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2658             : /*5905*/                OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2659             : /*5908*/                OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), 0|OPFL_Chain,
    2660             :                             MVT::v4i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2661             :                         // Src: (intrinsic_w_chain:v4i32 6137:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 0:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2662             :                         // Dst: (BUFFER_LOAD_DWORDX4_IDXEN:v4i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2663             : /*5921*/              0, // EndSwitchType
    2664             : /*5922*/            0, /*End of Scope*/
    2665             : /*5923*/          /*Scope*/ 100, /*->6024*/
    2666             : /*5924*/            OPC_CheckChild3Type, MVT::v2i32,
    2667             : /*5926*/            OPC_RecordChild4, // #3 = $soffset
    2668             : /*5927*/            OPC_RecordChild5, // #4 = $offset
    2669             : /*5928*/            OPC_MoveChild5,
    2670             : /*5929*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2671             : /*5932*/            OPC_MoveParent,
    2672             : /*5933*/            OPC_MoveChild6,
    2673             : /*5934*/            OPC_CheckInteger, 1, 
    2674             : /*5936*/            OPC_MoveParent,
    2675             : /*5937*/            OPC_MoveChild7,
    2676             : /*5938*/            OPC_CheckInteger, 1, 
    2677             : /*5940*/            OPC_MoveParent,
    2678             : /*5941*/            OPC_MoveChild, 8,
    2679             : /*5943*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2680             : /*5946*/            OPC_RecordNode, // #5 = $glc
    2681             : /*5947*/            OPC_MoveParent,
    2682             : /*5948*/            OPC_MoveChild, 9,
    2683             : /*5950*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2684             : /*5953*/            OPC_RecordNode, // #6 = $slc
    2685             : /*5954*/            OPC_MoveParent,
    2686             : /*5955*/            OPC_MoveChild, 10,
    2687             : /*5957*/            OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2688             : /*5960*/            OPC_RecordNode, // #7 = $tfe
    2689             : /*5961*/            OPC_MoveParent,
    2690             : /*5962*/            OPC_SwitchType /*2 cases */, 28, MVT::v2i32,// ->5993
    2691             : /*5965*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2692             : /*5967*/              OPC_EmitMergeInputChains1_0,
    2693             : /*5968*/              OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2694             : /*5971*/              OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2695             : /*5974*/              OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2696             : /*5977*/              OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2697             : /*5980*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), 0|OPFL_Chain,
    2698             :                           MVT::v2i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2699             :                       // Src: (intrinsic_w_chain:v2i32 6137:iPTR, v4i32:v4i32:$rsrc, v2i32:v2i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2700             :                       // Dst: (BUFFER_LOAD_DWORDX2_BOTHEN:v2i32 ?:v2i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2701             : /*5993*/            /*SwitchType*/ 28, MVT::v4i32,// ->6023
    2702             : /*5995*/              OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2703             : /*5997*/              OPC_EmitMergeInputChains1_0,
    2704             : /*5998*/              OPC_EmitNodeXForm, 0, 4, // as_i16imm
    2705             : /*6001*/              OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2706             : /*6004*/              OPC_EmitNodeXForm, 1, 6, // as_i1imm
    2707             : /*6007*/              OPC_EmitNodeXForm, 1, 7, // as_i1imm
    2708             : /*6010*/              OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), 0|OPFL_Chain,
    2709             :                           MVT::v4i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11, 
    2710             :                       // Src: (intrinsic_w_chain:v4i32 6137:iPTR, v4i32:v4i32:$rsrc, v2i32:v2i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
    2711             :                       // Dst: (BUFFER_LOAD_DWORDX4_BOTHEN:v4i32 ?:v2i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
    2712             : /*6023*/            0, // EndSwitchType
    2713             : /*6024*/          0, /*End of Scope*/
    2714             : /*6025*/        0, /*End of Scope*/
    2715             : /*6026*/      /*Scope*/ 17|128,1/*145*/, /*->6173*/
    2716             : /*6028*/        OPC_CheckChild1Integer, 117|128,2/*373*/, 
    2717             : /*6031*/        OPC_RecordChild2, // #1 = $vdata_in
    2718             : /*6032*/        OPC_RecordChild3, // #2 = $rsrc
    2719             : /*6033*/        OPC_Scope, 58, /*->6093*/ // 2 children in Scope
    2720             : /*6035*/          OPC_CheckChild4Integer, 0, 
    2721             : /*6037*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2722             : /*6038*/          OPC_RecordChild6, // #4 = $slc
    2723             : /*6039*/          OPC_MoveChild6,
    2724             : /*6040*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2725             : /*6043*/          OPC_MoveParent,
    2726             : /*6044*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2727             : /*6046*/          OPC_Scope, 22, /*->6070*/ // 2 children in Scope
    2728             : /*6048*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    2729             : /*6051*/            OPC_EmitMergeInputChains1_0,
    2730             : /*6052*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2731             : /*6055*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2732             : /*6058*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN), 0|OPFL_Chain,
    2733             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    2734             :                     // Src: (intrinsic_w_chain:i32 373:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    2735             :                     // Dst: (BUFFER_ATOMIC_SWAP_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2736             : /*6070*/          /*Scope*/ 21, /*->6092*/
    2737             : /*6071*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    2738             : /*6074*/            OPC_EmitMergeInputChains1_0,
    2739             : /*6075*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2740             : /*6078*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2741             : /*6081*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN), 0|OPFL_Chain,
    2742             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    2743             :                     // Src: (intrinsic_w_chain:i32 373:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    2744             :                     // Dst: (BUFFER_ATOMIC_SWAP_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2745             : /*6092*/          0, /*End of Scope*/
    2746             : /*6093*/        /*Scope*/ 78, /*->6172*/
    2747             : /*6094*/          OPC_RecordChild4, // #3 = $vindex
    2748             : /*6095*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2749             : /*6096*/          OPC_RecordChild6, // #5 = $slc
    2750             : /*6097*/          OPC_MoveChild6,
    2751             : /*6098*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2752             : /*6101*/          OPC_MoveParent,
    2753             : /*6102*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2754             : /*6104*/          OPC_Scope, 42, /*->6148*/ // 2 children in Scope
    2755             : /*6106*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    2756             : /*6109*/            OPC_EmitMergeInputChains1_0,
    2757             : /*6110*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    2758             : /*6113*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    2759             : /*6116*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    2760             : /*6119*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    2761             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    2762             : /*6130*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    2763             : /*6133*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2764             : /*6136*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN), 0|OPFL_Chain,
    2765             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    2766             :                     // Src: (intrinsic_w_chain:i32 373:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    2767             :                     // Dst: (BUFFER_ATOMIC_SWAP_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2768             : /*6148*/          /*Scope*/ 22, /*->6171*/
    2769             : /*6149*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    2770             : /*6152*/            OPC_EmitMergeInputChains1_0,
    2771             : /*6153*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    2772             : /*6156*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2773             : /*6159*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN), 0|OPFL_Chain,
    2774             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    2775             :                     // Src: (intrinsic_w_chain:i32 373:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    2776             :                     // Dst: (BUFFER_ATOMIC_SWAP_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2777             : /*6171*/          0, /*End of Scope*/
    2778             : /*6172*/        0, /*End of Scope*/
    2779             : /*6173*/      /*Scope*/ 17|128,1/*145*/, /*->6320*/
    2780             : /*6175*/        OPC_CheckChild1Integer, 110|128,2/*366*/, 
    2781             : /*6178*/        OPC_RecordChild2, // #1 = $vdata_in
    2782             : /*6179*/        OPC_RecordChild3, // #2 = $rsrc
    2783             : /*6180*/        OPC_Scope, 58, /*->6240*/ // 2 children in Scope
    2784             : /*6182*/          OPC_CheckChild4Integer, 0, 
    2785             : /*6184*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2786             : /*6185*/          OPC_RecordChild6, // #4 = $slc
    2787             : /*6186*/          OPC_MoveChild6,
    2788             : /*6187*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2789             : /*6190*/          OPC_MoveParent,
    2790             : /*6191*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2791             : /*6193*/          OPC_Scope, 22, /*->6217*/ // 2 children in Scope
    2792             : /*6195*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    2793             : /*6198*/            OPC_EmitMergeInputChains1_0,
    2794             : /*6199*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2795             : /*6202*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2796             : /*6205*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN), 0|OPFL_Chain,
    2797             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    2798             :                     // Src: (intrinsic_w_chain:i32 366:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    2799             :                     // Dst: (BUFFER_ATOMIC_ADD_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2800             : /*6217*/          /*Scope*/ 21, /*->6239*/
    2801             : /*6218*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    2802             : /*6221*/            OPC_EmitMergeInputChains1_0,
    2803             : /*6222*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2804             : /*6225*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2805             : /*6228*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN), 0|OPFL_Chain,
    2806             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    2807             :                     // Src: (intrinsic_w_chain:i32 366:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    2808             :                     // Dst: (BUFFER_ATOMIC_ADD_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2809             : /*6239*/          0, /*End of Scope*/
    2810             : /*6240*/        /*Scope*/ 78, /*->6319*/
    2811             : /*6241*/          OPC_RecordChild4, // #3 = $vindex
    2812             : /*6242*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2813             : /*6243*/          OPC_RecordChild6, // #5 = $slc
    2814             : /*6244*/          OPC_MoveChild6,
    2815             : /*6245*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2816             : /*6248*/          OPC_MoveParent,
    2817             : /*6249*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2818             : /*6251*/          OPC_Scope, 42, /*->6295*/ // 2 children in Scope
    2819             : /*6253*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    2820             : /*6256*/            OPC_EmitMergeInputChains1_0,
    2821             : /*6257*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    2822             : /*6260*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    2823             : /*6263*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    2824             : /*6266*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    2825             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    2826             : /*6277*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    2827             : /*6280*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2828             : /*6283*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN), 0|OPFL_Chain,
    2829             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    2830             :                     // Src: (intrinsic_w_chain:i32 366:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    2831             :                     // Dst: (BUFFER_ATOMIC_ADD_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2832             : /*6295*/          /*Scope*/ 22, /*->6318*/
    2833             : /*6296*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    2834             : /*6299*/            OPC_EmitMergeInputChains1_0,
    2835             : /*6300*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    2836             : /*6303*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2837             : /*6306*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN), 0|OPFL_Chain,
    2838             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    2839             :                     // Src: (intrinsic_w_chain:i32 366:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    2840             :                     // Dst: (BUFFER_ATOMIC_ADD_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2841             : /*6318*/          0, /*End of Scope*/
    2842             : /*6319*/        0, /*End of Scope*/
    2843             : /*6320*/      /*Scope*/ 17|128,1/*145*/, /*->6467*/
    2844             : /*6322*/        OPC_CheckChild1Integer, 116|128,2/*372*/, 
    2845             : /*6325*/        OPC_RecordChild2, // #1 = $vdata_in
    2846             : /*6326*/        OPC_RecordChild3, // #2 = $rsrc
    2847             : /*6327*/        OPC_Scope, 58, /*->6387*/ // 2 children in Scope
    2848             : /*6329*/          OPC_CheckChild4Integer, 0, 
    2849             : /*6331*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2850             : /*6332*/          OPC_RecordChild6, // #4 = $slc
    2851             : /*6333*/          OPC_MoveChild6,
    2852             : /*6334*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2853             : /*6337*/          OPC_MoveParent,
    2854             : /*6338*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2855             : /*6340*/          OPC_Scope, 22, /*->6364*/ // 2 children in Scope
    2856             : /*6342*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    2857             : /*6345*/            OPC_EmitMergeInputChains1_0,
    2858             : /*6346*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2859             : /*6349*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2860             : /*6352*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN), 0|OPFL_Chain,
    2861             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    2862             :                     // Src: (intrinsic_w_chain:i32 372:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    2863             :                     // Dst: (BUFFER_ATOMIC_SUB_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2864             : /*6364*/          /*Scope*/ 21, /*->6386*/
    2865             : /*6365*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    2866             : /*6368*/            OPC_EmitMergeInputChains1_0,
    2867             : /*6369*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2868             : /*6372*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2869             : /*6375*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN), 0|OPFL_Chain,
    2870             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    2871             :                     // Src: (intrinsic_w_chain:i32 372:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    2872             :                     // Dst: (BUFFER_ATOMIC_SUB_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2873             : /*6386*/          0, /*End of Scope*/
    2874             : /*6387*/        /*Scope*/ 78, /*->6466*/
    2875             : /*6388*/          OPC_RecordChild4, // #3 = $vindex
    2876             : /*6389*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2877             : /*6390*/          OPC_RecordChild6, // #5 = $slc
    2878             : /*6391*/          OPC_MoveChild6,
    2879             : /*6392*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2880             : /*6395*/          OPC_MoveParent,
    2881             : /*6396*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2882             : /*6398*/          OPC_Scope, 42, /*->6442*/ // 2 children in Scope
    2883             : /*6400*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    2884             : /*6403*/            OPC_EmitMergeInputChains1_0,
    2885             : /*6404*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    2886             : /*6407*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    2887             : /*6410*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    2888             : /*6413*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    2889             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    2890             : /*6424*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    2891             : /*6427*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2892             : /*6430*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN), 0|OPFL_Chain,
    2893             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    2894             :                     // Src: (intrinsic_w_chain:i32 372:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    2895             :                     // Dst: (BUFFER_ATOMIC_SUB_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2896             : /*6442*/          /*Scope*/ 22, /*->6465*/
    2897             : /*6443*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    2898             : /*6446*/            OPC_EmitMergeInputChains1_0,
    2899             : /*6447*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    2900             : /*6450*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2901             : /*6453*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN), 0|OPFL_Chain,
    2902             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    2903             :                     // Src: (intrinsic_w_chain:i32 372:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    2904             :                     // Dst: (BUFFER_ATOMIC_SUB_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2905             : /*6465*/          0, /*End of Scope*/
    2906             : /*6466*/        0, /*End of Scope*/
    2907             : /*6467*/      /*Scope*/ 17|128,1/*145*/, /*->6614*/
    2908             : /*6469*/        OPC_CheckChild1Integer, 115|128,2/*371*/, 
    2909             : /*6472*/        OPC_RecordChild2, // #1 = $vdata_in
    2910             : /*6473*/        OPC_RecordChild3, // #2 = $rsrc
    2911             : /*6474*/        OPC_Scope, 58, /*->6534*/ // 2 children in Scope
    2912             : /*6476*/          OPC_CheckChild4Integer, 0, 
    2913             : /*6478*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2914             : /*6479*/          OPC_RecordChild6, // #4 = $slc
    2915             : /*6480*/          OPC_MoveChild6,
    2916             : /*6481*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2917             : /*6484*/          OPC_MoveParent,
    2918             : /*6485*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2919             : /*6487*/          OPC_Scope, 22, /*->6511*/ // 2 children in Scope
    2920             : /*6489*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    2921             : /*6492*/            OPC_EmitMergeInputChains1_0,
    2922             : /*6493*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2923             : /*6496*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2924             : /*6499*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN), 0|OPFL_Chain,
    2925             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    2926             :                     // Src: (intrinsic_w_chain:i32 371:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    2927             :                     // Dst: (BUFFER_ATOMIC_SMIN_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2928             : /*6511*/          /*Scope*/ 21, /*->6533*/
    2929             : /*6512*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    2930             : /*6515*/            OPC_EmitMergeInputChains1_0,
    2931             : /*6516*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2932             : /*6519*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2933             : /*6522*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN), 0|OPFL_Chain,
    2934             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    2935             :                     // Src: (intrinsic_w_chain:i32 371:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    2936             :                     // Dst: (BUFFER_ATOMIC_SMIN_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2937             : /*6533*/          0, /*End of Scope*/
    2938             : /*6534*/        /*Scope*/ 78, /*->6613*/
    2939             : /*6535*/          OPC_RecordChild4, // #3 = $vindex
    2940             : /*6536*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2941             : /*6537*/          OPC_RecordChild6, // #5 = $slc
    2942             : /*6538*/          OPC_MoveChild6,
    2943             : /*6539*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2944             : /*6542*/          OPC_MoveParent,
    2945             : /*6543*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2946             : /*6545*/          OPC_Scope, 42, /*->6589*/ // 2 children in Scope
    2947             : /*6547*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    2948             : /*6550*/            OPC_EmitMergeInputChains1_0,
    2949             : /*6551*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    2950             : /*6554*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    2951             : /*6557*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    2952             : /*6560*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    2953             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    2954             : /*6571*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    2955             : /*6574*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2956             : /*6577*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN), 0|OPFL_Chain,
    2957             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    2958             :                     // Src: (intrinsic_w_chain:i32 371:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    2959             :                     // Dst: (BUFFER_ATOMIC_SMIN_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2960             : /*6589*/          /*Scope*/ 22, /*->6612*/
    2961             : /*6590*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    2962             : /*6593*/            OPC_EmitMergeInputChains1_0,
    2963             : /*6594*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    2964             : /*6597*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    2965             : /*6600*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN), 0|OPFL_Chain,
    2966             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    2967             :                     // Src: (intrinsic_w_chain:i32 371:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    2968             :                     // Dst: (BUFFER_ATOMIC_SMIN_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2969             : /*6612*/          0, /*End of Scope*/
    2970             : /*6613*/        0, /*End of Scope*/
    2971             : /*6614*/      /*Scope*/ 17|128,1/*145*/, /*->6761*/
    2972             : /*6616*/        OPC_CheckChild1Integer, 119|128,2/*375*/, 
    2973             : /*6619*/        OPC_RecordChild2, // #1 = $vdata_in
    2974             : /*6620*/        OPC_RecordChild3, // #2 = $rsrc
    2975             : /*6621*/        OPC_Scope, 58, /*->6681*/ // 2 children in Scope
    2976             : /*6623*/          OPC_CheckChild4Integer, 0, 
    2977             : /*6625*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    2978             : /*6626*/          OPC_RecordChild6, // #4 = $slc
    2979             : /*6627*/          OPC_MoveChild6,
    2980             : /*6628*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    2981             : /*6631*/          OPC_MoveParent,
    2982             : /*6632*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    2983             : /*6634*/          OPC_Scope, 22, /*->6658*/ // 2 children in Scope
    2984             : /*6636*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    2985             : /*6639*/            OPC_EmitMergeInputChains1_0,
    2986             : /*6640*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2987             : /*6643*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2988             : /*6646*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN), 0|OPFL_Chain,
    2989             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    2990             :                     // Src: (intrinsic_w_chain:i32 375:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    2991             :                     // Dst: (BUFFER_ATOMIC_UMIN_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    2992             : /*6658*/          /*Scope*/ 21, /*->6680*/
    2993             : /*6659*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    2994             : /*6662*/            OPC_EmitMergeInputChains1_0,
    2995             : /*6663*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    2996             : /*6666*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    2997             : /*6669*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN), 0|OPFL_Chain,
    2998             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    2999             :                     // Src: (intrinsic_w_chain:i32 375:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    3000             :                     // Dst: (BUFFER_ATOMIC_UMIN_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3001             : /*6680*/          0, /*End of Scope*/
    3002             : /*6681*/        /*Scope*/ 78, /*->6760*/
    3003             : /*6682*/          OPC_RecordChild4, // #3 = $vindex
    3004             : /*6683*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3005             : /*6684*/          OPC_RecordChild6, // #5 = $slc
    3006             : /*6685*/          OPC_MoveChild6,
    3007             : /*6686*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3008             : /*6689*/          OPC_MoveParent,
    3009             : /*6690*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3010             : /*6692*/          OPC_Scope, 42, /*->6736*/ // 2 children in Scope
    3011             : /*6694*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    3012             : /*6697*/            OPC_EmitMergeInputChains1_0,
    3013             : /*6698*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3014             : /*6701*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3015             : /*6704*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3016             : /*6707*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3017             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    3018             : /*6718*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3019             : /*6721*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3020             : /*6724*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN), 0|OPFL_Chain,
    3021             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    3022             :                     // Src: (intrinsic_w_chain:i32 375:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    3023             :                     // Dst: (BUFFER_ATOMIC_UMIN_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3024             : /*6736*/          /*Scope*/ 22, /*->6759*/
    3025             : /*6737*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    3026             : /*6740*/            OPC_EmitMergeInputChains1_0,
    3027             : /*6741*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3028             : /*6744*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3029             : /*6747*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN), 0|OPFL_Chain,
    3030             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    3031             :                     // Src: (intrinsic_w_chain:i32 375:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    3032             :                     // Dst: (BUFFER_ATOMIC_UMIN_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3033             : /*6759*/          0, /*End of Scope*/
    3034             : /*6760*/        0, /*End of Scope*/
    3035             : /*6761*/      /*Scope*/ 17|128,1/*145*/, /*->6908*/
    3036             : /*6763*/        OPC_CheckChild1Integer, 114|128,2/*370*/, 
    3037             : /*6766*/        OPC_RecordChild2, // #1 = $vdata_in
    3038             : /*6767*/        OPC_RecordChild3, // #2 = $rsrc
    3039             : /*6768*/        OPC_Scope, 58, /*->6828*/ // 2 children in Scope
    3040             : /*6770*/          OPC_CheckChild4Integer, 0, 
    3041             : /*6772*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3042             : /*6773*/          OPC_RecordChild6, // #4 = $slc
    3043             : /*6774*/          OPC_MoveChild6,
    3044             : /*6775*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3045             : /*6778*/          OPC_MoveParent,
    3046             : /*6779*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3047             : /*6781*/          OPC_Scope, 22, /*->6805*/ // 2 children in Scope
    3048             : /*6783*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    3049             : /*6786*/            OPC_EmitMergeInputChains1_0,
    3050             : /*6787*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3051             : /*6790*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3052             : /*6793*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN), 0|OPFL_Chain,
    3053             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    3054             :                     // Src: (intrinsic_w_chain:i32 370:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    3055             :                     // Dst: (BUFFER_ATOMIC_SMAX_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3056             : /*6805*/          /*Scope*/ 21, /*->6827*/
    3057             : /*6806*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    3058             : /*6809*/            OPC_EmitMergeInputChains1_0,
    3059             : /*6810*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3060             : /*6813*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3061             : /*6816*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN), 0|OPFL_Chain,
    3062             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    3063             :                     // Src: (intrinsic_w_chain:i32 370:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    3064             :                     // Dst: (BUFFER_ATOMIC_SMAX_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3065             : /*6827*/          0, /*End of Scope*/
    3066             : /*6828*/        /*Scope*/ 78, /*->6907*/
    3067             : /*6829*/          OPC_RecordChild4, // #3 = $vindex
    3068             : /*6830*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3069             : /*6831*/          OPC_RecordChild6, // #5 = $slc
    3070             : /*6832*/          OPC_MoveChild6,
    3071             : /*6833*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3072             : /*6836*/          OPC_MoveParent,
    3073             : /*6837*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3074             : /*6839*/          OPC_Scope, 42, /*->6883*/ // 2 children in Scope
    3075             : /*6841*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    3076             : /*6844*/            OPC_EmitMergeInputChains1_0,
    3077             : /*6845*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3078             : /*6848*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3079             : /*6851*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3080             : /*6854*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3081             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    3082             : /*6865*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3083             : /*6868*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3084             : /*6871*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN), 0|OPFL_Chain,
    3085             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    3086             :                     // Src: (intrinsic_w_chain:i32 370:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    3087             :                     // Dst: (BUFFER_ATOMIC_SMAX_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3088             : /*6883*/          /*Scope*/ 22, /*->6906*/
    3089             : /*6884*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    3090             : /*6887*/            OPC_EmitMergeInputChains1_0,
    3091             : /*6888*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3092             : /*6891*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3093             : /*6894*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN), 0|OPFL_Chain,
    3094             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    3095             :                     // Src: (intrinsic_w_chain:i32 370:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    3096             :                     // Dst: (BUFFER_ATOMIC_SMAX_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3097             : /*6906*/          0, /*End of Scope*/
    3098             : /*6907*/        0, /*End of Scope*/
    3099             : /*6908*/      /*Scope*/ 17|128,1/*145*/, /*->7055*/
    3100             : /*6910*/        OPC_CheckChild1Integer, 118|128,2/*374*/, 
    3101             : /*6913*/        OPC_RecordChild2, // #1 = $vdata_in
    3102             : /*6914*/        OPC_RecordChild3, // #2 = $rsrc
    3103             : /*6915*/        OPC_Scope, 58, /*->6975*/ // 2 children in Scope
    3104             : /*6917*/          OPC_CheckChild4Integer, 0, 
    3105             : /*6919*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3106             : /*6920*/          OPC_RecordChild6, // #4 = $slc
    3107             : /*6921*/          OPC_MoveChild6,
    3108             : /*6922*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3109             : /*6925*/          OPC_MoveParent,
    3110             : /*6926*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3111             : /*6928*/          OPC_Scope, 22, /*->6952*/ // 2 children in Scope
    3112             : /*6930*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    3113             : /*6933*/            OPC_EmitMergeInputChains1_0,
    3114             : /*6934*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3115             : /*6937*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3116             : /*6940*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN), 0|OPFL_Chain,
    3117             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    3118             :                     // Src: (intrinsic_w_chain:i32 374:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    3119             :                     // Dst: (BUFFER_ATOMIC_UMAX_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3120             : /*6952*/          /*Scope*/ 21, /*->6974*/
    3121             : /*6953*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    3122             : /*6956*/            OPC_EmitMergeInputChains1_0,
    3123             : /*6957*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3124             : /*6960*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3125             : /*6963*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN), 0|OPFL_Chain,
    3126             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    3127             :                     // Src: (intrinsic_w_chain:i32 374:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    3128             :                     // Dst: (BUFFER_ATOMIC_UMAX_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3129             : /*6974*/          0, /*End of Scope*/
    3130             : /*6975*/        /*Scope*/ 78, /*->7054*/
    3131             : /*6976*/          OPC_RecordChild4, // #3 = $vindex
    3132             : /*6977*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3133             : /*6978*/          OPC_RecordChild6, // #5 = $slc
    3134             : /*6979*/          OPC_MoveChild6,
    3135             : /*6980*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3136             : /*6983*/          OPC_MoveParent,
    3137             : /*6984*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3138             : /*6986*/          OPC_Scope, 42, /*->7030*/ // 2 children in Scope
    3139             : /*6988*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    3140             : /*6991*/            OPC_EmitMergeInputChains1_0,
    3141             : /*6992*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3142             : /*6995*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3143             : /*6998*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3144             : /*7001*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3145             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    3146             : /*7012*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3147             : /*7015*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3148             : /*7018*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN), 0|OPFL_Chain,
    3149             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    3150             :                     // Src: (intrinsic_w_chain:i32 374:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    3151             :                     // Dst: (BUFFER_ATOMIC_UMAX_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3152             : /*7030*/          /*Scope*/ 22, /*->7053*/
    3153             : /*7031*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    3154             : /*7034*/            OPC_EmitMergeInputChains1_0,
    3155             : /*7035*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3156             : /*7038*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3157             : /*7041*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN), 0|OPFL_Chain,
    3158             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    3159             :                     // Src: (intrinsic_w_chain:i32 374:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    3160             :                     // Dst: (BUFFER_ATOMIC_UMAX_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3161             : /*7053*/          0, /*End of Scope*/
    3162             : /*7054*/        0, /*End of Scope*/
    3163             : /*7055*/      /*Scope*/ 17|128,1/*145*/, /*->7202*/
    3164             : /*7057*/        OPC_CheckChild1Integer, 111|128,2/*367*/, 
    3165             : /*7060*/        OPC_RecordChild2, // #1 = $vdata_in
    3166             : /*7061*/        OPC_RecordChild3, // #2 = $rsrc
    3167             : /*7062*/        OPC_Scope, 58, /*->7122*/ // 2 children in Scope
    3168             : /*7064*/          OPC_CheckChild4Integer, 0, 
    3169             : /*7066*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3170             : /*7067*/          OPC_RecordChild6, // #4 = $slc
    3171             : /*7068*/          OPC_MoveChild6,
    3172             : /*7069*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3173             : /*7072*/          OPC_MoveParent,
    3174             : /*7073*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3175             : /*7075*/          OPC_Scope, 22, /*->7099*/ // 2 children in Scope
    3176             : /*7077*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    3177             : /*7080*/            OPC_EmitMergeInputChains1_0,
    3178             : /*7081*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3179             : /*7084*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3180             : /*7087*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN), 0|OPFL_Chain,
    3181             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    3182             :                     // Src: (intrinsic_w_chain:i32 367:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    3183             :                     // Dst: (BUFFER_ATOMIC_AND_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3184             : /*7099*/          /*Scope*/ 21, /*->7121*/
    3185             : /*7100*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    3186             : /*7103*/            OPC_EmitMergeInputChains1_0,
    3187             : /*7104*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3188             : /*7107*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3189             : /*7110*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN), 0|OPFL_Chain,
    3190             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    3191             :                     // Src: (intrinsic_w_chain:i32 367:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    3192             :                     // Dst: (BUFFER_ATOMIC_AND_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3193             : /*7121*/          0, /*End of Scope*/
    3194             : /*7122*/        /*Scope*/ 78, /*->7201*/
    3195             : /*7123*/          OPC_RecordChild4, // #3 = $vindex
    3196             : /*7124*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3197             : /*7125*/          OPC_RecordChild6, // #5 = $slc
    3198             : /*7126*/          OPC_MoveChild6,
    3199             : /*7127*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3200             : /*7130*/          OPC_MoveParent,
    3201             : /*7131*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3202             : /*7133*/          OPC_Scope, 42, /*->7177*/ // 2 children in Scope
    3203             : /*7135*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    3204             : /*7138*/            OPC_EmitMergeInputChains1_0,
    3205             : /*7139*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3206             : /*7142*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3207             : /*7145*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3208             : /*7148*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3209             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    3210             : /*7159*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3211             : /*7162*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3212             : /*7165*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN), 0|OPFL_Chain,
    3213             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    3214             :                     // Src: (intrinsic_w_chain:i32 367:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    3215             :                     // Dst: (BUFFER_ATOMIC_AND_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3216             : /*7177*/          /*Scope*/ 22, /*->7200*/
    3217             : /*7178*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    3218             : /*7181*/            OPC_EmitMergeInputChains1_0,
    3219             : /*7182*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3220             : /*7185*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3221             : /*7188*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN), 0|OPFL_Chain,
    3222             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    3223             :                     // Src: (intrinsic_w_chain:i32 367:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    3224             :                     // Dst: (BUFFER_ATOMIC_AND_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3225             : /*7200*/          0, /*End of Scope*/
    3226             : /*7201*/        0, /*End of Scope*/
    3227             : /*7202*/      /*Scope*/ 17|128,1/*145*/, /*->7349*/
    3228             : /*7204*/        OPC_CheckChild1Integer, 113|128,2/*369*/, 
    3229             : /*7207*/        OPC_RecordChild2, // #1 = $vdata_in
    3230             : /*7208*/        OPC_RecordChild3, // #2 = $rsrc
    3231             : /*7209*/        OPC_Scope, 58, /*->7269*/ // 2 children in Scope
    3232             : /*7211*/          OPC_CheckChild4Integer, 0, 
    3233             : /*7213*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3234             : /*7214*/          OPC_RecordChild6, // #4 = $slc
    3235             : /*7215*/          OPC_MoveChild6,
    3236             : /*7216*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3237             : /*7219*/          OPC_MoveParent,
    3238             : /*7220*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3239             : /*7222*/          OPC_Scope, 22, /*->7246*/ // 2 children in Scope
    3240             : /*7224*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    3241             : /*7227*/            OPC_EmitMergeInputChains1_0,
    3242             : /*7228*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3243             : /*7231*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3244             : /*7234*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN), 0|OPFL_Chain,
    3245             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    3246             :                     // Src: (intrinsic_w_chain:i32 369:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    3247             :                     // Dst: (BUFFER_ATOMIC_OR_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3248             : /*7246*/          /*Scope*/ 21, /*->7268*/
    3249             : /*7247*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    3250             : /*7250*/            OPC_EmitMergeInputChains1_0,
    3251             : /*7251*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3252             : /*7254*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3253             : /*7257*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN), 0|OPFL_Chain,
    3254             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    3255             :                     // Src: (intrinsic_w_chain:i32 369:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    3256             :                     // Dst: (BUFFER_ATOMIC_OR_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3257             : /*7268*/          0, /*End of Scope*/
    3258             : /*7269*/        /*Scope*/ 78, /*->7348*/
    3259             : /*7270*/          OPC_RecordChild4, // #3 = $vindex
    3260             : /*7271*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3261             : /*7272*/          OPC_RecordChild6, // #5 = $slc
    3262             : /*7273*/          OPC_MoveChild6,
    3263             : /*7274*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3264             : /*7277*/          OPC_MoveParent,
    3265             : /*7278*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3266             : /*7280*/          OPC_Scope, 42, /*->7324*/ // 2 children in Scope
    3267             : /*7282*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    3268             : /*7285*/            OPC_EmitMergeInputChains1_0,
    3269             : /*7286*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3270             : /*7289*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3271             : /*7292*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3272             : /*7295*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3273             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    3274             : /*7306*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3275             : /*7309*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3276             : /*7312*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN), 0|OPFL_Chain,
    3277             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    3278             :                     // Src: (intrinsic_w_chain:i32 369:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    3279             :                     // Dst: (BUFFER_ATOMIC_OR_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3280             : /*7324*/          /*Scope*/ 22, /*->7347*/
    3281             : /*7325*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    3282             : /*7328*/            OPC_EmitMergeInputChains1_0,
    3283             : /*7329*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3284             : /*7332*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3285             : /*7335*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN), 0|OPFL_Chain,
    3286             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    3287             :                     // Src: (intrinsic_w_chain:i32 369:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    3288             :                     // Dst: (BUFFER_ATOMIC_OR_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3289             : /*7347*/          0, /*End of Scope*/
    3290             : /*7348*/        0, /*End of Scope*/
    3291             : /*7349*/      /*Scope*/ 17|128,1/*145*/, /*->7496*/
    3292             : /*7351*/        OPC_CheckChild1Integer, 120|128,2/*376*/, 
    3293             : /*7354*/        OPC_RecordChild2, // #1 = $vdata_in
    3294             : /*7355*/        OPC_RecordChild3, // #2 = $rsrc
    3295             : /*7356*/        OPC_Scope, 58, /*->7416*/ // 2 children in Scope
    3296             : /*7358*/          OPC_CheckChild4Integer, 0, 
    3297             : /*7360*/          OPC_RecordChild5, // #3 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3298             : /*7361*/          OPC_RecordChild6, // #4 = $slc
    3299             : /*7362*/          OPC_MoveChild6,
    3300             : /*7363*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3301             : /*7366*/          OPC_MoveParent,
    3302             : /*7367*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3303             : /*7369*/          OPC_Scope, 22, /*->7393*/ // 2 children in Scope
    3304             : /*7371*/            OPC_CheckComplexPat, /*CP*/13, /*#*/3, // SelectMUBUFIntrinsicVOffset:$ #5 #6 #7
    3305             : /*7374*/            OPC_EmitMergeInputChains1_0,
    3306             : /*7375*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3307             : /*7378*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3308             : /*7381*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN), 0|OPFL_Chain,
    3309             :                         MVT::i32, 6/*#Ops*/, 1, 7, 2, 5, 8, 9, 
    3310             :                     // Src: (intrinsic_w_chain:i32 376:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    3311             :                     // Dst: (BUFFER_ATOMIC_XOR_OFFEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3312             : /*7393*/          /*Scope*/ 21, /*->7415*/
    3313             : /*7394*/            OPC_CheckComplexPat, /*CP*/14, /*#*/3, // SelectMUBUFIntrinsicOffset:$ #5 #6
    3314             : /*7397*/            OPC_EmitMergeInputChains1_0,
    3315             : /*7398*/            OPC_EmitNodeXForm, 0, 6, // as_i16imm
    3316             : /*7401*/            OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3317             : /*7404*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN), 0|OPFL_Chain,
    3318             :                         MVT::i32, 5/*#Ops*/, 1, 2, 5, 7, 8, 
    3319             :                     // Src: (intrinsic_w_chain:i32 376:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    3320             :                     // Dst: (BUFFER_ATOMIC_XOR_OFFSET_RTN:i32 ?:i32:$vdata_in, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3321             : /*7415*/          0, /*End of Scope*/
    3322             : /*7416*/        /*Scope*/ 78, /*->7495*/
    3323             : /*7417*/          OPC_RecordChild4, // #3 = $vindex
    3324             : /*7418*/          OPC_RecordChild5, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3325             : /*7419*/          OPC_RecordChild6, // #5 = $slc
    3326             : /*7420*/          OPC_MoveChild6,
    3327             : /*7421*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3328             : /*7424*/          OPC_MoveParent,
    3329             : /*7425*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3330             : /*7427*/          OPC_Scope, 42, /*->7471*/ // 2 children in Scope
    3331             : /*7429*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    3332             : /*7432*/            OPC_EmitMergeInputChains1_0,
    3333             : /*7433*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3334             : /*7436*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3335             : /*7439*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3336             : /*7442*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3337             :                         MVT::i64, 5/*#Ops*/, 9, 3, 10, 8, 11,  // Results = #12
    3338             : /*7453*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3339             : /*7456*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3340             : /*7459*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN), 0|OPFL_Chain,
    3341             :                         MVT::i32, 6/*#Ops*/, 1, 12, 2, 6, 13, 14, 
    3342             :                     // Src: (intrinsic_w_chain:i32 376:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    3343             :                     // Dst: (BUFFER_ATOMIC_XOR_BOTHEN_RTN:i32 ?:i32:$vdata_in, (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3344             : /*7471*/          /*Scope*/ 22, /*->7494*/
    3345             : /*7472*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    3346             : /*7475*/            OPC_EmitMergeInputChains1_0,
    3347             : /*7476*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3348             : /*7479*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3349             : /*7482*/            OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN), 0|OPFL_Chain,
    3350             :                         MVT::i32, 6/*#Ops*/, 1, 3, 2, 6, 8, 9, 
    3351             :                     // Src: (intrinsic_w_chain:i32 376:iPTR, i32:i32:$vdata_in, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    3352             :                     // Dst: (BUFFER_ATOMIC_XOR_IDXEN_RTN:i32 ?:i32:$vdata_in, ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc))
    3353             : /*7494*/          0, /*End of Scope*/
    3354             : /*7495*/        0, /*End of Scope*/
    3355             : /*7496*/      /*Scope*/ 17|128,2/*273*/, /*->7771*/
    3356             : /*7498*/        OPC_CheckChild1Integer, 112|128,2/*368*/, 
    3357             : /*7501*/        OPC_RecordChild2, // #1 = $data
    3358             : /*7502*/        OPC_RecordChild3, // #2 = $cmp
    3359             : /*7503*/        OPC_RecordChild4, // #3 = $rsrc
    3360             : /*7504*/        OPC_Scope, 122, /*->7628*/ // 2 children in Scope
    3361             : /*7506*/          OPC_MoveChild5,
    3362             : /*7507*/          OPC_CheckInteger, 0, 
    3363             : /*7509*/          OPC_MoveParent,
    3364             : /*7510*/          OPC_RecordChild6, // #4 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3365             : /*7511*/          OPC_RecordChild7, // #5 = $slc
    3366             : /*7512*/          OPC_MoveChild7,
    3367             : /*7513*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3368             : /*7516*/          OPC_MoveParent,
    3369             : /*7517*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3370             : /*7519*/          OPC_Scope, 53, /*->7574*/ // 2 children in Scope
    3371             : /*7521*/            OPC_CheckComplexPat, /*CP*/13, /*#*/4, // SelectMUBUFIntrinsicVOffset:$ #6 #7 #8
    3372             : /*7524*/            OPC_EmitMergeInputChains1_0,
    3373             : /*7525*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3374             : /*7528*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3375             : /*7531*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3376             : /*7534*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3377             :                         MVT::i64, 5/*#Ops*/, 9, 1, 10, 2, 11,  // Results = #12
    3378             : /*7545*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3379             : /*7548*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3380             : /*7551*/            OPC_EmitNode1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN), 0|OPFL_Chain,
    3381             :                         MVT::i64, 6/*#Ops*/, 12, 8, 3, 6, 13, 14,  // Results = #15
    3382             : /*7563*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3383             : /*7566*/            OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0|OPFL_Chain,
    3384             :                         MVT::i32, 2/*#Ops*/, 15, 16, 
    3385             :                     // Src: (intrinsic_w_chain:i32 368:iPTR, i32:i32:$data, i32:i32:$cmp, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 28
    3386             :                     // Dst: (EXTRACT_SUBREG:i32 (BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:i64 (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$data, sub0:i32, ?:i32:$cmp, sub1:i32), ?:i32:$voffset, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc)), sub0:i32)
    3387             : /*7574*/          /*Scope*/ 52, /*->7627*/
    3388             : /*7575*/            OPC_CheckComplexPat, /*CP*/14, /*#*/4, // SelectMUBUFIntrinsicOffset:$ #6 #7
    3389             : /*7578*/            OPC_EmitMergeInputChains1_0,
    3390             : /*7579*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3391             : /*7582*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3392             : /*7585*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3393             : /*7588*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3394             :                         MVT::i64, 5/*#Ops*/, 8, 1, 9, 2, 10,  // Results = #11
    3395             : /*7599*/            OPC_EmitNodeXForm, 0, 7, // as_i16imm
    3396             : /*7602*/            OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3397             : /*7605*/            OPC_EmitNode1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN), 0|OPFL_Chain,
    3398             :                         MVT::i64, 5/*#Ops*/, 11, 3, 6, 12, 13,  // Results = #14
    3399             : /*7616*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3400             : /*7619*/            OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0|OPFL_Chain,
    3401             :                         MVT::i32, 2/*#Ops*/, 14, 15, 
    3402             :                     // Src: (intrinsic_w_chain:i32 368:iPTR, i32:i32:$data, i32:i32:$cmp, v4i32:v4i32:$rsrc, 0:i32, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 25
    3403             :                     // Dst: (EXTRACT_SUBREG:i32 (BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:i64 (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$data, sub0:i32, ?:i32:$cmp, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc)), sub0:i32)
    3404             : /*7627*/          0, /*End of Scope*/
    3405             : /*7628*/        /*Scope*/ 12|128,1/*140*/, /*->7770*/
    3406             : /*7630*/          OPC_RecordChild5, // #4 = $vindex
    3407             : /*7631*/          OPC_RecordChild6, // #5 = $MUBUFIntrinsicVOffset:soffset:offset:voffset
    3408             : /*7632*/          OPC_RecordChild7, // #6 = $slc
    3409             : /*7633*/          OPC_MoveChild7,
    3410             : /*7634*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3411             : /*7637*/          OPC_MoveParent,
    3412             : /*7638*/          OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    3413             : /*7640*/          OPC_Scope, 73, /*->7715*/ // 2 children in Scope
    3414             : /*7642*/            OPC_CheckComplexPat, /*CP*/13, /*#*/5, // SelectMUBUFIntrinsicVOffset:$ #7 #8 #9
    3415             : /*7645*/            OPC_EmitMergeInputChains1_0,
    3416             : /*7646*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3417             : /*7649*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3418             : /*7652*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3419             : /*7655*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3420             :                         MVT::i64, 5/*#Ops*/, 10, 1, 11, 2, 12,  // Results = #13
    3421             : /*7666*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3422             : /*7669*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3423             : /*7672*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3424             : /*7675*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3425             :                         MVT::i64, 5/*#Ops*/, 14, 4, 15, 9, 16,  // Results = #17
    3426             : /*7686*/            OPC_EmitNodeXForm, 0, 8, // as_i16imm
    3427             : /*7689*/            OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3428             : /*7692*/            OPC_EmitNode1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN), 0|OPFL_Chain,
    3429             :                         MVT::i64, 6/*#Ops*/, 13, 17, 3, 7, 18, 19,  // Results = #20
    3430             : /*7704*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3431             : /*7707*/            OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0|OPFL_Chain,
    3432             :                         MVT::i32, 2/*#Ops*/, 20, 21, 
    3433             :                     // Src: (intrinsic_w_chain:i32 368:iPTR, i32:i32:$data, i32:i32:$cmp, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicVOffset:i32 i32:i32:$soffset, i16:i16:$offset, i32:i32:$voffset), (imm:i1):$slc) - Complexity = 23
    3434             :                     // Dst: (EXTRACT_SUBREG:i32 (BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:i64 (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$data, sub0:i32, ?:i32:$cmp, sub1:i32), (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vindex, sub0:i32, ?:i32:$voffset, sub1:i32), ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc)), sub0:i32)
    3435             : /*7715*/          /*Scope*/ 53, /*->7769*/
    3436             : /*7716*/            OPC_CheckComplexPat, /*CP*/14, /*#*/5, // SelectMUBUFIntrinsicOffset:$ #7 #8
    3437             : /*7719*/            OPC_EmitMergeInputChains1_0,
    3438             : /*7720*/            OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    3439             : /*7723*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3440             : /*7726*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    3441             : /*7729*/            OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    3442             :                         MVT::i64, 5/*#Ops*/, 9, 1, 10, 2, 11,  // Results = #12
    3443             : /*7740*/            OPC_EmitNodeXForm, 0, 8, // as_i16imm
    3444             : /*7743*/            OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3445             : /*7746*/            OPC_EmitNode1, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN), 0|OPFL_Chain,
    3446             :                         MVT::i64, 6/*#Ops*/, 12, 4, 3, 7, 13, 14,  // Results = #15
    3447             : /*7758*/            OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    3448             : /*7761*/            OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0|OPFL_Chain,
    3449             :                         MVT::i32, 2/*#Ops*/, 15, 16, 
    3450             :                     // Src: (intrinsic_w_chain:i32 368:iPTR, i32:i32:$data, i32:i32:$cmp, v4i32:v4i32:$rsrc, i32:i32:$vindex, (MUBUFIntrinsicOffset:i32 i32:i32:$soffset, i16:i16:$offset), (imm:i1):$slc) - Complexity = 20
    3451             :                     // Dst: (EXTRACT_SUBREG:i32 (BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN:i64 (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$data, sub0:i32, ?:i32:$cmp, sub1:i32), ?:i32:$vindex, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i16:$offset), (as_i1imm:i1 ?:i1:$slc)), sub0:i32)
    3452             : /*7769*/          0, /*End of Scope*/
    3453             : /*7770*/        0, /*End of Scope*/
    3454             : /*7771*/      /*Scope*/ 71|128,1/*199*/, /*->7972*/
    3455             : /*7773*/        OPC_CheckChild1Integer, 41|128,3/*425*/, 
    3456             : /*7776*/        OPC_RecordChild2, // #1 = $vdata
    3457             : /*7777*/        OPC_RecordChild3, // #2 = $addr
    3458             : /*7778*/        OPC_Scope, 63, /*->7843*/ // 3 children in Scope
    3459             : /*7780*/          OPC_CheckChild3Type, MVT::i32,
    3460             : /*7782*/          OPC_RecordChild4, // #3 = $rsrc
    3461             : /*7783*/          OPC_RecordChild5, // #4 = $r128
    3462             : /*7784*/          OPC_MoveChild5,
    3463             : /*7785*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3464             : /*7788*/          OPC_MoveParent,
    3465             : /*7789*/          OPC_RecordChild6, // #5 = $da
    3466             : /*7790*/          OPC_MoveChild6,
    3467             : /*7791*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3468             : /*7794*/          OPC_MoveParent,
    3469             : /*7795*/          OPC_RecordChild7, // #6 = $slc
    3470             : /*7796*/          OPC_MoveChild7,
    3471             : /*7797*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3472             : /*7800*/          OPC_MoveParent,
    3473             : /*7801*/          OPC_EmitMergeInputChains1_0,
    3474             : /*7802*/          OPC_EmitInteger, MVT::i16, 1, 
    3475             : /*7805*/          OPC_EmitInteger, MVT::i1, 1, 
    3476             : /*7808*/          OPC_EmitInteger, MVT::i1, 1, 
    3477             : /*7811*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3478             : /*7814*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3479             : /*7817*/          OPC_EmitInteger, MVT::i1, 0, 
    3480             : /*7820*/          OPC_EmitInteger, MVT::i1, 0, 
    3481             : /*7823*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3482             : /*7826*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SWAP_V1), 0|OPFL_Chain,
    3483             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3484             :                   // Src: (intrinsic_w_chain:i32 425:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3485             :                   // Dst: (IMAGE_ATOMIC_SWAP_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3486             : /*7843*/        /*Scope*/ 63, /*->7907*/
    3487             : /*7844*/          OPC_CheckChild3Type, MVT::v2i32,
    3488             : /*7846*/          OPC_RecordChild4, // #3 = $rsrc
    3489             : /*7847*/          OPC_RecordChild5, // #4 = $r128
    3490             : /*7848*/          OPC_MoveChild5,
    3491             : /*7849*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3492             : /*7852*/          OPC_MoveParent,
    3493             : /*7853*/          OPC_RecordChild6, // #5 = $da
    3494             : /*7854*/          OPC_MoveChild6,
    3495             : /*7855*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3496             : /*7858*/          OPC_MoveParent,
    3497             : /*7859*/          OPC_RecordChild7, // #6 = $slc
    3498             : /*7860*/          OPC_MoveChild7,
    3499             : /*7861*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3500             : /*7864*/          OPC_MoveParent,
    3501             : /*7865*/          OPC_EmitMergeInputChains1_0,
    3502             : /*7866*/          OPC_EmitInteger, MVT::i16, 1, 
    3503             : /*7869*/          OPC_EmitInteger, MVT::i1, 1, 
    3504             : /*7872*/          OPC_EmitInteger, MVT::i1, 1, 
    3505             : /*7875*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3506             : /*7878*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3507             : /*7881*/          OPC_EmitInteger, MVT::i1, 0, 
    3508             : /*7884*/          OPC_EmitInteger, MVT::i1, 0, 
    3509             : /*7887*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3510             : /*7890*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SWAP_V2), 0|OPFL_Chain,
    3511             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3512             :                   // Src: (intrinsic_w_chain:i32 425:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3513             :                   // Dst: (IMAGE_ATOMIC_SWAP_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3514             : /*7907*/        /*Scope*/ 63, /*->7971*/
    3515             : /*7908*/          OPC_CheckChild3Type, MVT::v4i32,
    3516             : /*7910*/          OPC_RecordChild4, // #3 = $rsrc
    3517             : /*7911*/          OPC_RecordChild5, // #4 = $r128
    3518             : /*7912*/          OPC_MoveChild5,
    3519             : /*7913*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3520             : /*7916*/          OPC_MoveParent,
    3521             : /*7917*/          OPC_RecordChild6, // #5 = $da
    3522             : /*7918*/          OPC_MoveChild6,
    3523             : /*7919*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3524             : /*7922*/          OPC_MoveParent,
    3525             : /*7923*/          OPC_RecordChild7, // #6 = $slc
    3526             : /*7924*/          OPC_MoveChild7,
    3527             : /*7925*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3528             : /*7928*/          OPC_MoveParent,
    3529             : /*7929*/          OPC_EmitMergeInputChains1_0,
    3530             : /*7930*/          OPC_EmitInteger, MVT::i16, 1, 
    3531             : /*7933*/          OPC_EmitInteger, MVT::i1, 1, 
    3532             : /*7936*/          OPC_EmitInteger, MVT::i1, 1, 
    3533             : /*7939*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3534             : /*7942*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3535             : /*7945*/          OPC_EmitInteger, MVT::i1, 0, 
    3536             : /*7948*/          OPC_EmitInteger, MVT::i1, 0, 
    3537             : /*7951*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3538             : /*7954*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SWAP_V4), 0|OPFL_Chain,
    3539             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3540             :                   // Src: (intrinsic_w_chain:i32 425:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3541             :                   // Dst: (IMAGE_ATOMIC_SWAP_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3542             : /*7971*/        0, /*End of Scope*/
    3543             : /*7972*/      /*Scope*/ 71|128,1/*199*/, /*->8173*/
    3544             : /*7974*/        OPC_CheckChild1Integer, 32|128,3/*416*/, 
    3545             : /*7977*/        OPC_RecordChild2, // #1 = $vdata
    3546             : /*7978*/        OPC_RecordChild3, // #2 = $addr
    3547             : /*7979*/        OPC_Scope, 63, /*->8044*/ // 3 children in Scope
    3548             : /*7981*/          OPC_CheckChild3Type, MVT::i32,
    3549             : /*7983*/          OPC_RecordChild4, // #3 = $rsrc
    3550             : /*7984*/          OPC_RecordChild5, // #4 = $r128
    3551             : /*7985*/          OPC_MoveChild5,
    3552             : /*7986*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3553             : /*7989*/          OPC_MoveParent,
    3554             : /*7990*/          OPC_RecordChild6, // #5 = $da
    3555             : /*7991*/          OPC_MoveChild6,
    3556             : /*7992*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3557             : /*7995*/          OPC_MoveParent,
    3558             : /*7996*/          OPC_RecordChild7, // #6 = $slc
    3559             : /*7997*/          OPC_MoveChild7,
    3560             : /*7998*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3561             : /*8001*/          OPC_MoveParent,
    3562             : /*8002*/          OPC_EmitMergeInputChains1_0,
    3563             : /*8003*/          OPC_EmitInteger, MVT::i16, 1, 
    3564             : /*8006*/          OPC_EmitInteger, MVT::i1, 1, 
    3565             : /*8009*/          OPC_EmitInteger, MVT::i1, 1, 
    3566             : /*8012*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3567             : /*8015*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3568             : /*8018*/          OPC_EmitInteger, MVT::i1, 0, 
    3569             : /*8021*/          OPC_EmitInteger, MVT::i1, 0, 
    3570             : /*8024*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3571             : /*8027*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_ADD_V1), 0|OPFL_Chain,
    3572             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3573             :                   // Src: (intrinsic_w_chain:i32 416:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3574             :                   // Dst: (IMAGE_ATOMIC_ADD_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3575             : /*8044*/        /*Scope*/ 63, /*->8108*/
    3576             : /*8045*/          OPC_CheckChild3Type, MVT::v2i32,
    3577             : /*8047*/          OPC_RecordChild4, // #3 = $rsrc
    3578             : /*8048*/          OPC_RecordChild5, // #4 = $r128
    3579             : /*8049*/          OPC_MoveChild5,
    3580             : /*8050*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3581             : /*8053*/          OPC_MoveParent,
    3582             : /*8054*/          OPC_RecordChild6, // #5 = $da
    3583             : /*8055*/          OPC_MoveChild6,
    3584             : /*8056*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3585             : /*8059*/          OPC_MoveParent,
    3586             : /*8060*/          OPC_RecordChild7, // #6 = $slc
    3587             : /*8061*/          OPC_MoveChild7,
    3588             : /*8062*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3589             : /*8065*/          OPC_MoveParent,
    3590             : /*8066*/          OPC_EmitMergeInputChains1_0,
    3591             : /*8067*/          OPC_EmitInteger, MVT::i16, 1, 
    3592             : /*8070*/          OPC_EmitInteger, MVT::i1, 1, 
    3593             : /*8073*/          OPC_EmitInteger, MVT::i1, 1, 
    3594             : /*8076*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3595             : /*8079*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3596             : /*8082*/          OPC_EmitInteger, MVT::i1, 0, 
    3597             : /*8085*/          OPC_EmitInteger, MVT::i1, 0, 
    3598             : /*8088*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3599             : /*8091*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_ADD_V2), 0|OPFL_Chain,
    3600             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3601             :                   // Src: (intrinsic_w_chain:i32 416:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3602             :                   // Dst: (IMAGE_ATOMIC_ADD_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3603             : /*8108*/        /*Scope*/ 63, /*->8172*/
    3604             : /*8109*/          OPC_CheckChild3Type, MVT::v4i32,
    3605             : /*8111*/          OPC_RecordChild4, // #3 = $rsrc
    3606             : /*8112*/          OPC_RecordChild5, // #4 = $r128
    3607             : /*8113*/          OPC_MoveChild5,
    3608             : /*8114*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3609             : /*8117*/          OPC_MoveParent,
    3610             : /*8118*/          OPC_RecordChild6, // #5 = $da
    3611             : /*8119*/          OPC_MoveChild6,
    3612             : /*8120*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3613             : /*8123*/          OPC_MoveParent,
    3614             : /*8124*/          OPC_RecordChild7, // #6 = $slc
    3615             : /*8125*/          OPC_MoveChild7,
    3616             : /*8126*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3617             : /*8129*/          OPC_MoveParent,
    3618             : /*8130*/          OPC_EmitMergeInputChains1_0,
    3619             : /*8131*/          OPC_EmitInteger, MVT::i16, 1, 
    3620             : /*8134*/          OPC_EmitInteger, MVT::i1, 1, 
    3621             : /*8137*/          OPC_EmitInteger, MVT::i1, 1, 
    3622             : /*8140*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3623             : /*8143*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3624             : /*8146*/          OPC_EmitInteger, MVT::i1, 0, 
    3625             : /*8149*/          OPC_EmitInteger, MVT::i1, 0, 
    3626             : /*8152*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3627             : /*8155*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_ADD_V4), 0|OPFL_Chain,
    3628             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3629             :                   // Src: (intrinsic_w_chain:i32 416:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3630             :                   // Dst: (IMAGE_ATOMIC_ADD_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3631             : /*8172*/        0, /*End of Scope*/
    3632             : /*8173*/      /*Scope*/ 71|128,1/*199*/, /*->8374*/
    3633             : /*8175*/        OPC_CheckChild1Integer, 40|128,3/*424*/, 
    3634             : /*8178*/        OPC_RecordChild2, // #1 = $vdata
    3635             : /*8179*/        OPC_RecordChild3, // #2 = $addr
    3636             : /*8180*/        OPC_Scope, 63, /*->8245*/ // 3 children in Scope
    3637             : /*8182*/          OPC_CheckChild3Type, MVT::i32,
    3638             : /*8184*/          OPC_RecordChild4, // #3 = $rsrc
    3639             : /*8185*/          OPC_RecordChild5, // #4 = $r128
    3640             : /*8186*/          OPC_MoveChild5,
    3641             : /*8187*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3642             : /*8190*/          OPC_MoveParent,
    3643             : /*8191*/          OPC_RecordChild6, // #5 = $da
    3644             : /*8192*/          OPC_MoveChild6,
    3645             : /*8193*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3646             : /*8196*/          OPC_MoveParent,
    3647             : /*8197*/          OPC_RecordChild7, // #6 = $slc
    3648             : /*8198*/          OPC_MoveChild7,
    3649             : /*8199*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3650             : /*8202*/          OPC_MoveParent,
    3651             : /*8203*/          OPC_EmitMergeInputChains1_0,
    3652             : /*8204*/          OPC_EmitInteger, MVT::i16, 1, 
    3653             : /*8207*/          OPC_EmitInteger, MVT::i1, 1, 
    3654             : /*8210*/          OPC_EmitInteger, MVT::i1, 1, 
    3655             : /*8213*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3656             : /*8216*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3657             : /*8219*/          OPC_EmitInteger, MVT::i1, 0, 
    3658             : /*8222*/          OPC_EmitInteger, MVT::i1, 0, 
    3659             : /*8225*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3660             : /*8228*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SUB_V1), 0|OPFL_Chain,
    3661             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3662             :                   // Src: (intrinsic_w_chain:i32 424:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3663             :                   // Dst: (IMAGE_ATOMIC_SUB_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3664             : /*8245*/        /*Scope*/ 63, /*->8309*/
    3665             : /*8246*/          OPC_CheckChild3Type, MVT::v2i32,
    3666             : /*8248*/          OPC_RecordChild4, // #3 = $rsrc
    3667             : /*8249*/          OPC_RecordChild5, // #4 = $r128
    3668             : /*8250*/          OPC_MoveChild5,
    3669             : /*8251*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3670             : /*8254*/          OPC_MoveParent,
    3671             : /*8255*/          OPC_RecordChild6, // #5 = $da
    3672             : /*8256*/          OPC_MoveChild6,
    3673             : /*8257*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3674             : /*8260*/          OPC_MoveParent,
    3675             : /*8261*/          OPC_RecordChild7, // #6 = $slc
    3676             : /*8262*/          OPC_MoveChild7,
    3677             : /*8263*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3678             : /*8266*/          OPC_MoveParent,
    3679             : /*8267*/          OPC_EmitMergeInputChains1_0,
    3680             : /*8268*/          OPC_EmitInteger, MVT::i16, 1, 
    3681             : /*8271*/          OPC_EmitInteger, MVT::i1, 1, 
    3682             : /*8274*/          OPC_EmitInteger, MVT::i1, 1, 
    3683             : /*8277*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3684             : /*8280*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3685             : /*8283*/          OPC_EmitInteger, MVT::i1, 0, 
    3686             : /*8286*/          OPC_EmitInteger, MVT::i1, 0, 
    3687             : /*8289*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3688             : /*8292*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SUB_V2), 0|OPFL_Chain,
    3689             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3690             :                   // Src: (intrinsic_w_chain:i32 424:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3691             :                   // Dst: (IMAGE_ATOMIC_SUB_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3692             : /*8309*/        /*Scope*/ 63, /*->8373*/
    3693             : /*8310*/          OPC_CheckChild3Type, MVT::v4i32,
    3694             : /*8312*/          OPC_RecordChild4, // #3 = $rsrc
    3695             : /*8313*/          OPC_RecordChild5, // #4 = $r128
    3696             : /*8314*/          OPC_MoveChild5,
    3697             : /*8315*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3698             : /*8318*/          OPC_MoveParent,
    3699             : /*8319*/          OPC_RecordChild6, // #5 = $da
    3700             : /*8320*/          OPC_MoveChild6,
    3701             : /*8321*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3702             : /*8324*/          OPC_MoveParent,
    3703             : /*8325*/          OPC_RecordChild7, // #6 = $slc
    3704             : /*8326*/          OPC_MoveChild7,
    3705             : /*8327*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3706             : /*8330*/          OPC_MoveParent,
    3707             : /*8331*/          OPC_EmitMergeInputChains1_0,
    3708             : /*8332*/          OPC_EmitInteger, MVT::i16, 1, 
    3709             : /*8335*/          OPC_EmitInteger, MVT::i1, 1, 
    3710             : /*8338*/          OPC_EmitInteger, MVT::i1, 1, 
    3711             : /*8341*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3712             : /*8344*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3713             : /*8347*/          OPC_EmitInteger, MVT::i1, 0, 
    3714             : /*8350*/          OPC_EmitInteger, MVT::i1, 0, 
    3715             : /*8353*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3716             : /*8356*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SUB_V4), 0|OPFL_Chain,
    3717             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3718             :                   // Src: (intrinsic_w_chain:i32 424:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3719             :                   // Dst: (IMAGE_ATOMIC_SUB_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3720             : /*8373*/        0, /*End of Scope*/
    3721             : /*8374*/      /*Scope*/ 71|128,1/*199*/, /*->8575*/
    3722             : /*8376*/        OPC_CheckChild1Integer, 39|128,3/*423*/, 
    3723             : /*8379*/        OPC_RecordChild2, // #1 = $vdata
    3724             : /*8380*/        OPC_RecordChild3, // #2 = $addr
    3725             : /*8381*/        OPC_Scope, 63, /*->8446*/ // 3 children in Scope
    3726             : /*8383*/          OPC_CheckChild3Type, MVT::i32,
    3727             : /*8385*/          OPC_RecordChild4, // #3 = $rsrc
    3728             : /*8386*/          OPC_RecordChild5, // #4 = $r128
    3729             : /*8387*/          OPC_MoveChild5,
    3730             : /*8388*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3731             : /*8391*/          OPC_MoveParent,
    3732             : /*8392*/          OPC_RecordChild6, // #5 = $da
    3733             : /*8393*/          OPC_MoveChild6,
    3734             : /*8394*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3735             : /*8397*/          OPC_MoveParent,
    3736             : /*8398*/          OPC_RecordChild7, // #6 = $slc
    3737             : /*8399*/          OPC_MoveChild7,
    3738             : /*8400*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3739             : /*8403*/          OPC_MoveParent,
    3740             : /*8404*/          OPC_EmitMergeInputChains1_0,
    3741             : /*8405*/          OPC_EmitInteger, MVT::i16, 1, 
    3742             : /*8408*/          OPC_EmitInteger, MVT::i1, 1, 
    3743             : /*8411*/          OPC_EmitInteger, MVT::i1, 1, 
    3744             : /*8414*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3745             : /*8417*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3746             : /*8420*/          OPC_EmitInteger, MVT::i1, 0, 
    3747             : /*8423*/          OPC_EmitInteger, MVT::i1, 0, 
    3748             : /*8426*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3749             : /*8429*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SMIN_V1), 0|OPFL_Chain,
    3750             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3751             :                   // Src: (intrinsic_w_chain:i32 423:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3752             :                   // Dst: (IMAGE_ATOMIC_SMIN_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3753             : /*8446*/        /*Scope*/ 63, /*->8510*/
    3754             : /*8447*/          OPC_CheckChild3Type, MVT::v2i32,
    3755             : /*8449*/          OPC_RecordChild4, // #3 = $rsrc
    3756             : /*8450*/          OPC_RecordChild5, // #4 = $r128
    3757             : /*8451*/          OPC_MoveChild5,
    3758             : /*8452*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3759             : /*8455*/          OPC_MoveParent,
    3760             : /*8456*/          OPC_RecordChild6, // #5 = $da
    3761             : /*8457*/          OPC_MoveChild6,
    3762             : /*8458*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3763             : /*8461*/          OPC_MoveParent,
    3764             : /*8462*/          OPC_RecordChild7, // #6 = $slc
    3765             : /*8463*/          OPC_MoveChild7,
    3766             : /*8464*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3767             : /*8467*/          OPC_MoveParent,
    3768             : /*8468*/          OPC_EmitMergeInputChains1_0,
    3769             : /*8469*/          OPC_EmitInteger, MVT::i16, 1, 
    3770             : /*8472*/          OPC_EmitInteger, MVT::i1, 1, 
    3771             : /*8475*/          OPC_EmitInteger, MVT::i1, 1, 
    3772             : /*8478*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3773             : /*8481*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3774             : /*8484*/          OPC_EmitInteger, MVT::i1, 0, 
    3775             : /*8487*/          OPC_EmitInteger, MVT::i1, 0, 
    3776             : /*8490*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3777             : /*8493*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SMIN_V2), 0|OPFL_Chain,
    3778             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3779             :                   // Src: (intrinsic_w_chain:i32 423:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3780             :                   // Dst: (IMAGE_ATOMIC_SMIN_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3781             : /*8510*/        /*Scope*/ 63, /*->8574*/
    3782             : /*8511*/          OPC_CheckChild3Type, MVT::v4i32,
    3783             : /*8513*/          OPC_RecordChild4, // #3 = $rsrc
    3784             : /*8514*/          OPC_RecordChild5, // #4 = $r128
    3785             : /*8515*/          OPC_MoveChild5,
    3786             : /*8516*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3787             : /*8519*/          OPC_MoveParent,
    3788             : /*8520*/          OPC_RecordChild6, // #5 = $da
    3789             : /*8521*/          OPC_MoveChild6,
    3790             : /*8522*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3791             : /*8525*/          OPC_MoveParent,
    3792             : /*8526*/          OPC_RecordChild7, // #6 = $slc
    3793             : /*8527*/          OPC_MoveChild7,
    3794             : /*8528*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3795             : /*8531*/          OPC_MoveParent,
    3796             : /*8532*/          OPC_EmitMergeInputChains1_0,
    3797             : /*8533*/          OPC_EmitInteger, MVT::i16, 1, 
    3798             : /*8536*/          OPC_EmitInteger, MVT::i1, 1, 
    3799             : /*8539*/          OPC_EmitInteger, MVT::i1, 1, 
    3800             : /*8542*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3801             : /*8545*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3802             : /*8548*/          OPC_EmitInteger, MVT::i1, 0, 
    3803             : /*8551*/          OPC_EmitInteger, MVT::i1, 0, 
    3804             : /*8554*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3805             : /*8557*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SMIN_V4), 0|OPFL_Chain,
    3806             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3807             :                   // Src: (intrinsic_w_chain:i32 423:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3808             :                   // Dst: (IMAGE_ATOMIC_SMIN_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3809             : /*8574*/        0, /*End of Scope*/
    3810             : /*8575*/      /*Scope*/ 71|128,1/*199*/, /*->8776*/
    3811             : /*8577*/        OPC_CheckChild1Integer, 43|128,3/*427*/, 
    3812             : /*8580*/        OPC_RecordChild2, // #1 = $vdata
    3813             : /*8581*/        OPC_RecordChild3, // #2 = $addr
    3814             : /*8582*/        OPC_Scope, 63, /*->8647*/ // 3 children in Scope
    3815             : /*8584*/          OPC_CheckChild3Type, MVT::i32,
    3816             : /*8586*/          OPC_RecordChild4, // #3 = $rsrc
    3817             : /*8587*/          OPC_RecordChild5, // #4 = $r128
    3818             : /*8588*/          OPC_MoveChild5,
    3819             : /*8589*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3820             : /*8592*/          OPC_MoveParent,
    3821             : /*8593*/          OPC_RecordChild6, // #5 = $da
    3822             : /*8594*/          OPC_MoveChild6,
    3823             : /*8595*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3824             : /*8598*/          OPC_MoveParent,
    3825             : /*8599*/          OPC_RecordChild7, // #6 = $slc
    3826             : /*8600*/          OPC_MoveChild7,
    3827             : /*8601*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3828             : /*8604*/          OPC_MoveParent,
    3829             : /*8605*/          OPC_EmitMergeInputChains1_0,
    3830             : /*8606*/          OPC_EmitInteger, MVT::i16, 1, 
    3831             : /*8609*/          OPC_EmitInteger, MVT::i1, 1, 
    3832             : /*8612*/          OPC_EmitInteger, MVT::i1, 1, 
    3833             : /*8615*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3834             : /*8618*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3835             : /*8621*/          OPC_EmitInteger, MVT::i1, 0, 
    3836             : /*8624*/          OPC_EmitInteger, MVT::i1, 0, 
    3837             : /*8627*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3838             : /*8630*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_UMIN_V1), 0|OPFL_Chain,
    3839             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3840             :                   // Src: (intrinsic_w_chain:i32 427:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3841             :                   // Dst: (IMAGE_ATOMIC_UMIN_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3842             : /*8647*/        /*Scope*/ 63, /*->8711*/
    3843             : /*8648*/          OPC_CheckChild3Type, MVT::v2i32,
    3844             : /*8650*/          OPC_RecordChild4, // #3 = $rsrc
    3845             : /*8651*/          OPC_RecordChild5, // #4 = $r128
    3846             : /*8652*/          OPC_MoveChild5,
    3847             : /*8653*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3848             : /*8656*/          OPC_MoveParent,
    3849             : /*8657*/          OPC_RecordChild6, // #5 = $da
    3850             : /*8658*/          OPC_MoveChild6,
    3851             : /*8659*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3852             : /*8662*/          OPC_MoveParent,
    3853             : /*8663*/          OPC_RecordChild7, // #6 = $slc
    3854             : /*8664*/          OPC_MoveChild7,
    3855             : /*8665*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3856             : /*8668*/          OPC_MoveParent,
    3857             : /*8669*/          OPC_EmitMergeInputChains1_0,
    3858             : /*8670*/          OPC_EmitInteger, MVT::i16, 1, 
    3859             : /*8673*/          OPC_EmitInteger, MVT::i1, 1, 
    3860             : /*8676*/          OPC_EmitInteger, MVT::i1, 1, 
    3861             : /*8679*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3862             : /*8682*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3863             : /*8685*/          OPC_EmitInteger, MVT::i1, 0, 
    3864             : /*8688*/          OPC_EmitInteger, MVT::i1, 0, 
    3865             : /*8691*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3866             : /*8694*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_UMIN_V2), 0|OPFL_Chain,
    3867             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3868             :                   // Src: (intrinsic_w_chain:i32 427:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3869             :                   // Dst: (IMAGE_ATOMIC_UMIN_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3870             : /*8711*/        /*Scope*/ 63, /*->8775*/
    3871             : /*8712*/          OPC_CheckChild3Type, MVT::v4i32,
    3872             : /*8714*/          OPC_RecordChild4, // #3 = $rsrc
    3873             : /*8715*/          OPC_RecordChild5, // #4 = $r128
    3874             : /*8716*/          OPC_MoveChild5,
    3875             : /*8717*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3876             : /*8720*/          OPC_MoveParent,
    3877             : /*8721*/          OPC_RecordChild6, // #5 = $da
    3878             : /*8722*/          OPC_MoveChild6,
    3879             : /*8723*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3880             : /*8726*/          OPC_MoveParent,
    3881             : /*8727*/          OPC_RecordChild7, // #6 = $slc
    3882             : /*8728*/          OPC_MoveChild7,
    3883             : /*8729*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3884             : /*8732*/          OPC_MoveParent,
    3885             : /*8733*/          OPC_EmitMergeInputChains1_0,
    3886             : /*8734*/          OPC_EmitInteger, MVT::i16, 1, 
    3887             : /*8737*/          OPC_EmitInteger, MVT::i1, 1, 
    3888             : /*8740*/          OPC_EmitInteger, MVT::i1, 1, 
    3889             : /*8743*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3890             : /*8746*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3891             : /*8749*/          OPC_EmitInteger, MVT::i1, 0, 
    3892             : /*8752*/          OPC_EmitInteger, MVT::i1, 0, 
    3893             : /*8755*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3894             : /*8758*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_UMIN_V4), 0|OPFL_Chain,
    3895             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3896             :                   // Src: (intrinsic_w_chain:i32 427:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3897             :                   // Dst: (IMAGE_ATOMIC_UMIN_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3898             : /*8775*/        0, /*End of Scope*/
    3899             : /*8776*/      /*Scope*/ 71|128,1/*199*/, /*->8977*/
    3900             : /*8778*/        OPC_CheckChild1Integer, 38|128,3/*422*/, 
    3901             : /*8781*/        OPC_RecordChild2, // #1 = $vdata
    3902             : /*8782*/        OPC_RecordChild3, // #2 = $addr
    3903             : /*8783*/        OPC_Scope, 63, /*->8848*/ // 3 children in Scope
    3904             : /*8785*/          OPC_CheckChild3Type, MVT::i32,
    3905             : /*8787*/          OPC_RecordChild4, // #3 = $rsrc
    3906             : /*8788*/          OPC_RecordChild5, // #4 = $r128
    3907             : /*8789*/          OPC_MoveChild5,
    3908             : /*8790*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3909             : /*8793*/          OPC_MoveParent,
    3910             : /*8794*/          OPC_RecordChild6, // #5 = $da
    3911             : /*8795*/          OPC_MoveChild6,
    3912             : /*8796*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3913             : /*8799*/          OPC_MoveParent,
    3914             : /*8800*/          OPC_RecordChild7, // #6 = $slc
    3915             : /*8801*/          OPC_MoveChild7,
    3916             : /*8802*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3917             : /*8805*/          OPC_MoveParent,
    3918             : /*8806*/          OPC_EmitMergeInputChains1_0,
    3919             : /*8807*/          OPC_EmitInteger, MVT::i16, 1, 
    3920             : /*8810*/          OPC_EmitInteger, MVT::i1, 1, 
    3921             : /*8813*/          OPC_EmitInteger, MVT::i1, 1, 
    3922             : /*8816*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3923             : /*8819*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3924             : /*8822*/          OPC_EmitInteger, MVT::i1, 0, 
    3925             : /*8825*/          OPC_EmitInteger, MVT::i1, 0, 
    3926             : /*8828*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3927             : /*8831*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SMAX_V1), 0|OPFL_Chain,
    3928             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3929             :                   // Src: (intrinsic_w_chain:i32 422:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3930             :                   // Dst: (IMAGE_ATOMIC_SMAX_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3931             : /*8848*/        /*Scope*/ 63, /*->8912*/
    3932             : /*8849*/          OPC_CheckChild3Type, MVT::v2i32,
    3933             : /*8851*/          OPC_RecordChild4, // #3 = $rsrc
    3934             : /*8852*/          OPC_RecordChild5, // #4 = $r128
    3935             : /*8853*/          OPC_MoveChild5,
    3936             : /*8854*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3937             : /*8857*/          OPC_MoveParent,
    3938             : /*8858*/          OPC_RecordChild6, // #5 = $da
    3939             : /*8859*/          OPC_MoveChild6,
    3940             : /*8860*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3941             : /*8863*/          OPC_MoveParent,
    3942             : /*8864*/          OPC_RecordChild7, // #6 = $slc
    3943             : /*8865*/          OPC_MoveChild7,
    3944             : /*8866*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3945             : /*8869*/          OPC_MoveParent,
    3946             : /*8870*/          OPC_EmitMergeInputChains1_0,
    3947             : /*8871*/          OPC_EmitInteger, MVT::i16, 1, 
    3948             : /*8874*/          OPC_EmitInteger, MVT::i1, 1, 
    3949             : /*8877*/          OPC_EmitInteger, MVT::i1, 1, 
    3950             : /*8880*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3951             : /*8883*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3952             : /*8886*/          OPC_EmitInteger, MVT::i1, 0, 
    3953             : /*8889*/          OPC_EmitInteger, MVT::i1, 0, 
    3954             : /*8892*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3955             : /*8895*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SMAX_V2), 0|OPFL_Chain,
    3956             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3957             :                   // Src: (intrinsic_w_chain:i32 422:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3958             :                   // Dst: (IMAGE_ATOMIC_SMAX_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3959             : /*8912*/        /*Scope*/ 63, /*->8976*/
    3960             : /*8913*/          OPC_CheckChild3Type, MVT::v4i32,
    3961             : /*8915*/          OPC_RecordChild4, // #3 = $rsrc
    3962             : /*8916*/          OPC_RecordChild5, // #4 = $r128
    3963             : /*8917*/          OPC_MoveChild5,
    3964             : /*8918*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3965             : /*8921*/          OPC_MoveParent,
    3966             : /*8922*/          OPC_RecordChild6, // #5 = $da
    3967             : /*8923*/          OPC_MoveChild6,
    3968             : /*8924*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3969             : /*8927*/          OPC_MoveParent,
    3970             : /*8928*/          OPC_RecordChild7, // #6 = $slc
    3971             : /*8929*/          OPC_MoveChild7,
    3972             : /*8930*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3973             : /*8933*/          OPC_MoveParent,
    3974             : /*8934*/          OPC_EmitMergeInputChains1_0,
    3975             : /*8935*/          OPC_EmitInteger, MVT::i16, 1, 
    3976             : /*8938*/          OPC_EmitInteger, MVT::i1, 1, 
    3977             : /*8941*/          OPC_EmitInteger, MVT::i1, 1, 
    3978             : /*8944*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    3979             : /*8947*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    3980             : /*8950*/          OPC_EmitInteger, MVT::i1, 0, 
    3981             : /*8953*/          OPC_EmitInteger, MVT::i1, 0, 
    3982             : /*8956*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    3983             : /*8959*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_SMAX_V4), 0|OPFL_Chain,
    3984             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    3985             :                   // Src: (intrinsic_w_chain:i32 422:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    3986             :                   // Dst: (IMAGE_ATOMIC_SMAX_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    3987             : /*8976*/        0, /*End of Scope*/
    3988             : /*8977*/      /*Scope*/ 71|128,1/*199*/, /*->9178*/
    3989             : /*8979*/        OPC_CheckChild1Integer, 42|128,3/*426*/, 
    3990             : /*8982*/        OPC_RecordChild2, // #1 = $vdata
    3991             : /*8983*/        OPC_RecordChild3, // #2 = $addr
    3992             : /*8984*/        OPC_Scope, 63, /*->9049*/ // 3 children in Scope
    3993             : /*8986*/          OPC_CheckChild3Type, MVT::i32,
    3994             : /*8988*/          OPC_RecordChild4, // #3 = $rsrc
    3995             : /*8989*/          OPC_RecordChild5, // #4 = $r128
    3996             : /*8990*/          OPC_MoveChild5,
    3997             : /*8991*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    3998             : /*8994*/          OPC_MoveParent,
    3999             : /*8995*/          OPC_RecordChild6, // #5 = $da
    4000             : /*8996*/          OPC_MoveChild6,
    4001             : /*8997*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4002             : /*9000*/          OPC_MoveParent,
    4003             : /*9001*/          OPC_RecordChild7, // #6 = $slc
    4004             : /*9002*/          OPC_MoveChild7,
    4005             : /*9003*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4006             : /*9006*/          OPC_MoveParent,
    4007             : /*9007*/          OPC_EmitMergeInputChains1_0,
    4008             : /*9008*/          OPC_EmitInteger, MVT::i16, 1, 
    4009             : /*9011*/          OPC_EmitInteger, MVT::i1, 1, 
    4010             : /*9014*/          OPC_EmitInteger, MVT::i1, 1, 
    4011             : /*9017*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4012             : /*9020*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4013             : /*9023*/          OPC_EmitInteger, MVT::i1, 0, 
    4014             : /*9026*/          OPC_EmitInteger, MVT::i1, 0, 
    4015             : /*9029*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4016             : /*9032*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_UMAX_V1), 0|OPFL_Chain,
    4017             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4018             :                   // Src: (intrinsic_w_chain:i32 426:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4019             :                   // Dst: (IMAGE_ATOMIC_UMAX_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4020             : /*9049*/        /*Scope*/ 63, /*->9113*/
    4021             : /*9050*/          OPC_CheckChild3Type, MVT::v2i32,
    4022             : /*9052*/          OPC_RecordChild4, // #3 = $rsrc
    4023             : /*9053*/          OPC_RecordChild5, // #4 = $r128
    4024             : /*9054*/          OPC_MoveChild5,
    4025             : /*9055*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4026             : /*9058*/          OPC_MoveParent,
    4027             : /*9059*/          OPC_RecordChild6, // #5 = $da
    4028             : /*9060*/          OPC_MoveChild6,
    4029             : /*9061*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4030             : /*9064*/          OPC_MoveParent,
    4031             : /*9065*/          OPC_RecordChild7, // #6 = $slc
    4032             : /*9066*/          OPC_MoveChild7,
    4033             : /*9067*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4034             : /*9070*/          OPC_MoveParent,
    4035             : /*9071*/          OPC_EmitMergeInputChains1_0,
    4036             : /*9072*/          OPC_EmitInteger, MVT::i16, 1, 
    4037             : /*9075*/          OPC_EmitInteger, MVT::i1, 1, 
    4038             : /*9078*/          OPC_EmitInteger, MVT::i1, 1, 
    4039             : /*9081*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4040             : /*9084*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4041             : /*9087*/          OPC_EmitInteger, MVT::i1, 0, 
    4042             : /*9090*/          OPC_EmitInteger, MVT::i1, 0, 
    4043             : /*9093*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4044             : /*9096*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_UMAX_V2), 0|OPFL_Chain,
    4045             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4046             :                   // Src: (intrinsic_w_chain:i32 426:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4047             :                   // Dst: (IMAGE_ATOMIC_UMAX_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4048             : /*9113*/        /*Scope*/ 63, /*->9177*/
    4049             : /*9114*/          OPC_CheckChild3Type, MVT::v4i32,
    4050             : /*9116*/          OPC_RecordChild4, // #3 = $rsrc
    4051             : /*9117*/          OPC_RecordChild5, // #4 = $r128
    4052             : /*9118*/          OPC_MoveChild5,
    4053             : /*9119*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4054             : /*9122*/          OPC_MoveParent,
    4055             : /*9123*/          OPC_RecordChild6, // #5 = $da
    4056             : /*9124*/          OPC_MoveChild6,
    4057             : /*9125*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4058             : /*9128*/          OPC_MoveParent,
    4059             : /*9129*/          OPC_RecordChild7, // #6 = $slc
    4060             : /*9130*/          OPC_MoveChild7,
    4061             : /*9131*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4062             : /*9134*/          OPC_MoveParent,
    4063             : /*9135*/          OPC_EmitMergeInputChains1_0,
    4064             : /*9136*/          OPC_EmitInteger, MVT::i16, 1, 
    4065             : /*9139*/          OPC_EmitInteger, MVT::i1, 1, 
    4066             : /*9142*/          OPC_EmitInteger, MVT::i1, 1, 
    4067             : /*9145*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4068             : /*9148*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4069             : /*9151*/          OPC_EmitInteger, MVT::i1, 0, 
    4070             : /*9154*/          OPC_EmitInteger, MVT::i1, 0, 
    4071             : /*9157*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4072             : /*9160*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_UMAX_V4), 0|OPFL_Chain,
    4073             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4074             :                   // Src: (intrinsic_w_chain:i32 426:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4075             :                   // Dst: (IMAGE_ATOMIC_UMAX_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4076             : /*9177*/        0, /*End of Scope*/
    4077             : /*9178*/      /*Scope*/ 71|128,1/*199*/, /*->9379*/
    4078             : /*9180*/        OPC_CheckChild1Integer, 33|128,3/*417*/, 
    4079             : /*9183*/        OPC_RecordChild2, // #1 = $vdata
    4080             : /*9184*/        OPC_RecordChild3, // #2 = $addr
    4081             : /*9185*/        OPC_Scope, 63, /*->9250*/ // 3 children in Scope
    4082             : /*9187*/          OPC_CheckChild3Type, MVT::i32,
    4083             : /*9189*/          OPC_RecordChild4, // #3 = $rsrc
    4084             : /*9190*/          OPC_RecordChild5, // #4 = $r128
    4085             : /*9191*/          OPC_MoveChild5,
    4086             : /*9192*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4087             : /*9195*/          OPC_MoveParent,
    4088             : /*9196*/          OPC_RecordChild6, // #5 = $da
    4089             : /*9197*/          OPC_MoveChild6,
    4090             : /*9198*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4091             : /*9201*/          OPC_MoveParent,
    4092             : /*9202*/          OPC_RecordChild7, // #6 = $slc
    4093             : /*9203*/          OPC_MoveChild7,
    4094             : /*9204*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4095             : /*9207*/          OPC_MoveParent,
    4096             : /*9208*/          OPC_EmitMergeInputChains1_0,
    4097             : /*9209*/          OPC_EmitInteger, MVT::i16, 1, 
    4098             : /*9212*/          OPC_EmitInteger, MVT::i1, 1, 
    4099             : /*9215*/          OPC_EmitInteger, MVT::i1, 1, 
    4100             : /*9218*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4101             : /*9221*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4102             : /*9224*/          OPC_EmitInteger, MVT::i1, 0, 
    4103             : /*9227*/          OPC_EmitInteger, MVT::i1, 0, 
    4104             : /*9230*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4105             : /*9233*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_AND_V1), 0|OPFL_Chain,
    4106             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4107             :                   // Src: (intrinsic_w_chain:i32 417:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4108             :                   // Dst: (IMAGE_ATOMIC_AND_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4109             : /*9250*/        /*Scope*/ 63, /*->9314*/
    4110             : /*9251*/          OPC_CheckChild3Type, MVT::v2i32,
    4111             : /*9253*/          OPC_RecordChild4, // #3 = $rsrc
    4112             : /*9254*/          OPC_RecordChild5, // #4 = $r128
    4113             : /*9255*/          OPC_MoveChild5,
    4114             : /*9256*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4115             : /*9259*/          OPC_MoveParent,
    4116             : /*9260*/          OPC_RecordChild6, // #5 = $da
    4117             : /*9261*/          OPC_MoveChild6,
    4118             : /*9262*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4119             : /*9265*/          OPC_MoveParent,
    4120             : /*9266*/          OPC_RecordChild7, // #6 = $slc
    4121             : /*9267*/          OPC_MoveChild7,
    4122             : /*9268*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4123             : /*9271*/          OPC_MoveParent,
    4124             : /*9272*/          OPC_EmitMergeInputChains1_0,
    4125             : /*9273*/          OPC_EmitInteger, MVT::i16, 1, 
    4126             : /*9276*/          OPC_EmitInteger, MVT::i1, 1, 
    4127             : /*9279*/          OPC_EmitInteger, MVT::i1, 1, 
    4128             : /*9282*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4129             : /*9285*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4130             : /*9288*/          OPC_EmitInteger, MVT::i1, 0, 
    4131             : /*9291*/          OPC_EmitInteger, MVT::i1, 0, 
    4132             : /*9294*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4133             : /*9297*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_AND_V2), 0|OPFL_Chain,
    4134             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4135             :                   // Src: (intrinsic_w_chain:i32 417:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4136             :                   // Dst: (IMAGE_ATOMIC_AND_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4137             : /*9314*/        /*Scope*/ 63, /*->9378*/
    4138             : /*9315*/          OPC_CheckChild3Type, MVT::v4i32,
    4139             : /*9317*/          OPC_RecordChild4, // #3 = $rsrc
    4140             : /*9318*/          OPC_RecordChild5, // #4 = $r128
    4141             : /*9319*/          OPC_MoveChild5,
    4142             : /*9320*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4143             : /*9323*/          OPC_MoveParent,
    4144             : /*9324*/          OPC_RecordChild6, // #5 = $da
    4145             : /*9325*/          OPC_MoveChild6,
    4146             : /*9326*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4147             : /*9329*/          OPC_MoveParent,
    4148             : /*9330*/          OPC_RecordChild7, // #6 = $slc
    4149             : /*9331*/          OPC_MoveChild7,
    4150             : /*9332*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4151             : /*9335*/          OPC_MoveParent,
    4152             : /*9336*/          OPC_EmitMergeInputChains1_0,
    4153             : /*9337*/          OPC_EmitInteger, MVT::i16, 1, 
    4154             : /*9340*/          OPC_EmitInteger, MVT::i1, 1, 
    4155             : /*9343*/          OPC_EmitInteger, MVT::i1, 1, 
    4156             : /*9346*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4157             : /*9349*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4158             : /*9352*/          OPC_EmitInteger, MVT::i1, 0, 
    4159             : /*9355*/          OPC_EmitInteger, MVT::i1, 0, 
    4160             : /*9358*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4161             : /*9361*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_AND_V4), 0|OPFL_Chain,
    4162             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4163             :                   // Src: (intrinsic_w_chain:i32 417:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4164             :                   // Dst: (IMAGE_ATOMIC_AND_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4165             : /*9378*/        0, /*End of Scope*/
    4166             : /*9379*/      /*Scope*/ 71|128,1/*199*/, /*->9580*/
    4167             : /*9381*/        OPC_CheckChild1Integer, 37|128,3/*421*/, 
    4168             : /*9384*/        OPC_RecordChild2, // #1 = $vdata
    4169             : /*9385*/        OPC_RecordChild3, // #2 = $addr
    4170             : /*9386*/        OPC_Scope, 63, /*->9451*/ // 3 children in Scope
    4171             : /*9388*/          OPC_CheckChild3Type, MVT::i32,
    4172             : /*9390*/          OPC_RecordChild4, // #3 = $rsrc
    4173             : /*9391*/          OPC_RecordChild5, // #4 = $r128
    4174             : /*9392*/          OPC_MoveChild5,
    4175             : /*9393*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4176             : /*9396*/          OPC_MoveParent,
    4177             : /*9397*/          OPC_RecordChild6, // #5 = $da
    4178             : /*9398*/          OPC_MoveChild6,
    4179             : /*9399*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4180             : /*9402*/          OPC_MoveParent,
    4181             : /*9403*/          OPC_RecordChild7, // #6 = $slc
    4182             : /*9404*/          OPC_MoveChild7,
    4183             : /*9405*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4184             : /*9408*/          OPC_MoveParent,
    4185             : /*9409*/          OPC_EmitMergeInputChains1_0,
    4186             : /*9410*/          OPC_EmitInteger, MVT::i16, 1, 
    4187             : /*9413*/          OPC_EmitInteger, MVT::i1, 1, 
    4188             : /*9416*/          OPC_EmitInteger, MVT::i1, 1, 
    4189             : /*9419*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4190             : /*9422*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4191             : /*9425*/          OPC_EmitInteger, MVT::i1, 0, 
    4192             : /*9428*/          OPC_EmitInteger, MVT::i1, 0, 
    4193             : /*9431*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4194             : /*9434*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_OR_V1), 0|OPFL_Chain,
    4195             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4196             :                   // Src: (intrinsic_w_chain:i32 421:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4197             :                   // Dst: (IMAGE_ATOMIC_OR_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4198             : /*9451*/        /*Scope*/ 63, /*->9515*/
    4199             : /*9452*/          OPC_CheckChild3Type, MVT::v2i32,
    4200             : /*9454*/          OPC_RecordChild4, // #3 = $rsrc
    4201             : /*9455*/          OPC_RecordChild5, // #4 = $r128
    4202             : /*9456*/          OPC_MoveChild5,
    4203             : /*9457*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4204             : /*9460*/          OPC_MoveParent,
    4205             : /*9461*/          OPC_RecordChild6, // #5 = $da
    4206             : /*9462*/          OPC_MoveChild6,
    4207             : /*9463*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4208             : /*9466*/          OPC_MoveParent,
    4209             : /*9467*/          OPC_RecordChild7, // #6 = $slc
    4210             : /*9468*/          OPC_MoveChild7,
    4211             : /*9469*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4212             : /*9472*/          OPC_MoveParent,
    4213             : /*9473*/          OPC_EmitMergeInputChains1_0,
    4214             : /*9474*/          OPC_EmitInteger, MVT::i16, 1, 
    4215             : /*9477*/          OPC_EmitInteger, MVT::i1, 1, 
    4216             : /*9480*/          OPC_EmitInteger, MVT::i1, 1, 
    4217             : /*9483*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4218             : /*9486*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4219             : /*9489*/          OPC_EmitInteger, MVT::i1, 0, 
    4220             : /*9492*/          OPC_EmitInteger, MVT::i1, 0, 
    4221             : /*9495*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4222             : /*9498*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_OR_V2), 0|OPFL_Chain,
    4223             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4224             :                   // Src: (intrinsic_w_chain:i32 421:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4225             :                   // Dst: (IMAGE_ATOMIC_OR_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4226             : /*9515*/        /*Scope*/ 63, /*->9579*/
    4227             : /*9516*/          OPC_CheckChild3Type, MVT::v4i32,
    4228             : /*9518*/          OPC_RecordChild4, // #3 = $rsrc
    4229             : /*9519*/          OPC_RecordChild5, // #4 = $r128
    4230             : /*9520*/          OPC_MoveChild5,
    4231             : /*9521*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4232             : /*9524*/          OPC_MoveParent,
    4233             : /*9525*/          OPC_RecordChild6, // #5 = $da
    4234             : /*9526*/          OPC_MoveChild6,
    4235             : /*9527*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4236             : /*9530*/          OPC_MoveParent,
    4237             : /*9531*/          OPC_RecordChild7, // #6 = $slc
    4238             : /*9532*/          OPC_MoveChild7,
    4239             : /*9533*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4240             : /*9536*/          OPC_MoveParent,
    4241             : /*9537*/          OPC_EmitMergeInputChains1_0,
    4242             : /*9538*/          OPC_EmitInteger, MVT::i16, 1, 
    4243             : /*9541*/          OPC_EmitInteger, MVT::i1, 1, 
    4244             : /*9544*/          OPC_EmitInteger, MVT::i1, 1, 
    4245             : /*9547*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4246             : /*9550*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4247             : /*9553*/          OPC_EmitInteger, MVT::i1, 0, 
    4248             : /*9556*/          OPC_EmitInteger, MVT::i1, 0, 
    4249             : /*9559*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4250             : /*9562*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_OR_V4), 0|OPFL_Chain,
    4251             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4252             :                   // Src: (intrinsic_w_chain:i32 421:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4253             :                   // Dst: (IMAGE_ATOMIC_OR_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4254             : /*9579*/        0, /*End of Scope*/
    4255             : /*9580*/      /*Scope*/ 71|128,1/*199*/, /*->9781*/
    4256             : /*9582*/        OPC_CheckChild1Integer, 44|128,3/*428*/, 
    4257             : /*9585*/        OPC_RecordChild2, // #1 = $vdata
    4258             : /*9586*/        OPC_RecordChild3, // #2 = $addr
    4259             : /*9587*/        OPC_Scope, 63, /*->9652*/ // 3 children in Scope
    4260             : /*9589*/          OPC_CheckChild3Type, MVT::i32,
    4261             : /*9591*/          OPC_RecordChild4, // #3 = $rsrc
    4262             : /*9592*/          OPC_RecordChild5, // #4 = $r128
    4263             : /*9593*/          OPC_MoveChild5,
    4264             : /*9594*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4265             : /*9597*/          OPC_MoveParent,
    4266             : /*9598*/          OPC_RecordChild6, // #5 = $da
    4267             : /*9599*/          OPC_MoveChild6,
    4268             : /*9600*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4269             : /*9603*/          OPC_MoveParent,
    4270             : /*9604*/          OPC_RecordChild7, // #6 = $slc
    4271             : /*9605*/          OPC_MoveChild7,
    4272             : /*9606*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4273             : /*9609*/          OPC_MoveParent,
    4274             : /*9610*/          OPC_EmitMergeInputChains1_0,
    4275             : /*9611*/          OPC_EmitInteger, MVT::i16, 1, 
    4276             : /*9614*/          OPC_EmitInteger, MVT::i1, 1, 
    4277             : /*9617*/          OPC_EmitInteger, MVT::i1, 1, 
    4278             : /*9620*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4279             : /*9623*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4280             : /*9626*/          OPC_EmitInteger, MVT::i1, 0, 
    4281             : /*9629*/          OPC_EmitInteger, MVT::i1, 0, 
    4282             : /*9632*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4283             : /*9635*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_XOR_V1), 0|OPFL_Chain,
    4284             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4285             :                   // Src: (intrinsic_w_chain:i32 428:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4286             :                   // Dst: (IMAGE_ATOMIC_XOR_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4287             : /*9652*/        /*Scope*/ 63, /*->9716*/
    4288             : /*9653*/          OPC_CheckChild3Type, MVT::v2i32,
    4289             : /*9655*/          OPC_RecordChild4, // #3 = $rsrc
    4290             : /*9656*/          OPC_RecordChild5, // #4 = $r128
    4291             : /*9657*/          OPC_MoveChild5,
    4292             : /*9658*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4293             : /*9661*/          OPC_MoveParent,
    4294             : /*9662*/          OPC_RecordChild6, // #5 = $da
    4295             : /*9663*/          OPC_MoveChild6,
    4296             : /*9664*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4297             : /*9667*/          OPC_MoveParent,
    4298             : /*9668*/          OPC_RecordChild7, // #6 = $slc
    4299             : /*9669*/          OPC_MoveChild7,
    4300             : /*9670*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4301             : /*9673*/          OPC_MoveParent,
    4302             : /*9674*/          OPC_EmitMergeInputChains1_0,
    4303             : /*9675*/          OPC_EmitInteger, MVT::i16, 1, 
    4304             : /*9678*/          OPC_EmitInteger, MVT::i1, 1, 
    4305             : /*9681*/          OPC_EmitInteger, MVT::i1, 1, 
    4306             : /*9684*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4307             : /*9687*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4308             : /*9690*/          OPC_EmitInteger, MVT::i1, 0, 
    4309             : /*9693*/          OPC_EmitInteger, MVT::i1, 0, 
    4310             : /*9696*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4311             : /*9699*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_XOR_V2), 0|OPFL_Chain,
    4312             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4313             :                   // Src: (intrinsic_w_chain:i32 428:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4314             :                   // Dst: (IMAGE_ATOMIC_XOR_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4315             : /*9716*/        /*Scope*/ 63, /*->9780*/
    4316             : /*9717*/          OPC_CheckChild3Type, MVT::v4i32,
    4317             : /*9719*/          OPC_RecordChild4, // #3 = $rsrc
    4318             : /*9720*/          OPC_RecordChild5, // #4 = $r128
    4319             : /*9721*/          OPC_MoveChild5,
    4320             : /*9722*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4321             : /*9725*/          OPC_MoveParent,
    4322             : /*9726*/          OPC_RecordChild6, // #5 = $da
    4323             : /*9727*/          OPC_MoveChild6,
    4324             : /*9728*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4325             : /*9731*/          OPC_MoveParent,
    4326             : /*9732*/          OPC_RecordChild7, // #6 = $slc
    4327             : /*9733*/          OPC_MoveChild7,
    4328             : /*9734*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4329             : /*9737*/          OPC_MoveParent,
    4330             : /*9738*/          OPC_EmitMergeInputChains1_0,
    4331             : /*9739*/          OPC_EmitInteger, MVT::i16, 1, 
    4332             : /*9742*/          OPC_EmitInteger, MVT::i1, 1, 
    4333             : /*9745*/          OPC_EmitInteger, MVT::i1, 1, 
    4334             : /*9748*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4335             : /*9751*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4336             : /*9754*/          OPC_EmitInteger, MVT::i1, 0, 
    4337             : /*9757*/          OPC_EmitInteger, MVT::i1, 0, 
    4338             : /*9760*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4339             : /*9763*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_XOR_V4), 0|OPFL_Chain,
    4340             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4341             :                   // Src: (intrinsic_w_chain:i32 428:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4342             :                   // Dst: (IMAGE_ATOMIC_XOR_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4343             : /*9780*/        0, /*End of Scope*/
    4344             : /*9781*/      /*Scope*/ 71|128,1/*199*/, /*->9982*/
    4345             : /*9783*/        OPC_CheckChild1Integer, 36|128,3/*420*/, 
    4346             : /*9786*/        OPC_RecordChild2, // #1 = $vdata
    4347             : /*9787*/        OPC_RecordChild3, // #2 = $addr
    4348             : /*9788*/        OPC_Scope, 63, /*->9853*/ // 3 children in Scope
    4349             : /*9790*/          OPC_CheckChild3Type, MVT::i32,
    4350             : /*9792*/          OPC_RecordChild4, // #3 = $rsrc
    4351             : /*9793*/          OPC_RecordChild5, // #4 = $r128
    4352             : /*9794*/          OPC_MoveChild5,
    4353             : /*9795*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4354             : /*9798*/          OPC_MoveParent,
    4355             : /*9799*/          OPC_RecordChild6, // #5 = $da
    4356             : /*9800*/          OPC_MoveChild6,
    4357             : /*9801*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4358             : /*9804*/          OPC_MoveParent,
    4359             : /*9805*/          OPC_RecordChild7, // #6 = $slc
    4360             : /*9806*/          OPC_MoveChild7,
    4361             : /*9807*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4362             : /*9810*/          OPC_MoveParent,
    4363             : /*9811*/          OPC_EmitMergeInputChains1_0,
    4364             : /*9812*/          OPC_EmitInteger, MVT::i16, 1, 
    4365             : /*9815*/          OPC_EmitInteger, MVT::i1, 1, 
    4366             : /*9818*/          OPC_EmitInteger, MVT::i1, 1, 
    4367             : /*9821*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4368             : /*9824*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4369             : /*9827*/          OPC_EmitInteger, MVT::i1, 0, 
    4370             : /*9830*/          OPC_EmitInteger, MVT::i1, 0, 
    4371             : /*9833*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4372             : /*9836*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_INC_V1), 0|OPFL_Chain,
    4373             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4374             :                   // Src: (intrinsic_w_chain:i32 420:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4375             :                   // Dst: (IMAGE_ATOMIC_INC_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4376             : /*9853*/        /*Scope*/ 63, /*->9917*/
    4377             : /*9854*/          OPC_CheckChild3Type, MVT::v2i32,
    4378             : /*9856*/          OPC_RecordChild4, // #3 = $rsrc
    4379             : /*9857*/          OPC_RecordChild5, // #4 = $r128
    4380             : /*9858*/          OPC_MoveChild5,
    4381             : /*9859*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4382             : /*9862*/          OPC_MoveParent,
    4383             : /*9863*/          OPC_RecordChild6, // #5 = $da
    4384             : /*9864*/          OPC_MoveChild6,
    4385             : /*9865*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4386             : /*9868*/          OPC_MoveParent,
    4387             : /*9869*/          OPC_RecordChild7, // #6 = $slc
    4388             : /*9870*/          OPC_MoveChild7,
    4389             : /*9871*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4390             : /*9874*/          OPC_MoveParent,
    4391             : /*9875*/          OPC_EmitMergeInputChains1_0,
    4392             : /*9876*/          OPC_EmitInteger, MVT::i16, 1, 
    4393             : /*9879*/          OPC_EmitInteger, MVT::i1, 1, 
    4394             : /*9882*/          OPC_EmitInteger, MVT::i1, 1, 
    4395             : /*9885*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4396             : /*9888*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4397             : /*9891*/          OPC_EmitInteger, MVT::i1, 0, 
    4398             : /*9894*/          OPC_EmitInteger, MVT::i1, 0, 
    4399             : /*9897*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4400             : /*9900*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_INC_V2), 0|OPFL_Chain,
    4401             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4402             :                   // Src: (intrinsic_w_chain:i32 420:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4403             :                   // Dst: (IMAGE_ATOMIC_INC_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4404             : /*9917*/        /*Scope*/ 63, /*->9981*/
    4405             : /*9918*/          OPC_CheckChild3Type, MVT::v4i32,
    4406             : /*9920*/          OPC_RecordChild4, // #3 = $rsrc
    4407             : /*9921*/          OPC_RecordChild5, // #4 = $r128
    4408             : /*9922*/          OPC_MoveChild5,
    4409             : /*9923*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4410             : /*9926*/          OPC_MoveParent,
    4411             : /*9927*/          OPC_RecordChild6, // #5 = $da
    4412             : /*9928*/          OPC_MoveChild6,
    4413             : /*9929*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4414             : /*9932*/          OPC_MoveParent,
    4415             : /*9933*/          OPC_RecordChild7, // #6 = $slc
    4416             : /*9934*/          OPC_MoveChild7,
    4417             : /*9935*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4418             : /*9938*/          OPC_MoveParent,
    4419             : /*9939*/          OPC_EmitMergeInputChains1_0,
    4420             : /*9940*/          OPC_EmitInteger, MVT::i16, 1, 
    4421             : /*9943*/          OPC_EmitInteger, MVT::i1, 1, 
    4422             : /*9946*/          OPC_EmitInteger, MVT::i1, 1, 
    4423             : /*9949*/          OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4424             : /*9952*/          OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4425             : /*9955*/          OPC_EmitInteger, MVT::i1, 0, 
    4426             : /*9958*/          OPC_EmitInteger, MVT::i1, 0, 
    4427             : /*9961*/          OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4428             : /*9964*/          OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_INC_V4), 0|OPFL_Chain,
    4429             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4430             :                   // Src: (intrinsic_w_chain:i32 420:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4431             :                   // Dst: (IMAGE_ATOMIC_INC_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4432             : /*9981*/        0, /*End of Scope*/
    4433             : /*9982*/      /*Scope*/ 71|128,1/*199*/, /*->10183*/
    4434             : /*9984*/        OPC_CheckChild1Integer, 35|128,3/*419*/, 
    4435             : /*9987*/        OPC_RecordChild2, // #1 = $vdata
    4436             : /*9988*/        OPC_RecordChild3, // #2 = $addr
    4437             : /*9989*/        OPC_Scope, 63, /*->10054*/ // 3 children in Scope
    4438             : /*9991*/          OPC_CheckChild3Type, MVT::i32,
    4439             : /*9993*/          OPC_RecordChild4, // #3 = $rsrc
    4440             : /*9994*/          OPC_RecordChild5, // #4 = $r128
    4441             : /*9995*/          OPC_MoveChild5,
    4442             : /*9996*/          OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4443             : /*9999*/          OPC_MoveParent,
    4444             : /*10000*/         OPC_RecordChild6, // #5 = $da
    4445             : /*10001*/         OPC_MoveChild6,
    4446             : /*10002*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4447             : /*10005*/         OPC_MoveParent,
    4448             : /*10006*/         OPC_RecordChild7, // #6 = $slc
    4449             : /*10007*/         OPC_MoveChild7,
    4450             : /*10008*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4451             : /*10011*/         OPC_MoveParent,
    4452             : /*10012*/         OPC_EmitMergeInputChains1_0,
    4453             : /*10013*/         OPC_EmitInteger, MVT::i16, 1, 
    4454             : /*10016*/         OPC_EmitInteger, MVT::i1, 1, 
    4455             : /*10019*/         OPC_EmitInteger, MVT::i1, 1, 
    4456             : /*10022*/         OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4457             : /*10025*/         OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4458             : /*10028*/         OPC_EmitInteger, MVT::i1, 0, 
    4459             : /*10031*/         OPC_EmitInteger, MVT::i1, 0, 
    4460             : /*10034*/         OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4461             : /*10037*/         OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_DEC_V1), 0|OPFL_Chain,
    4462             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4463             :                   // Src: (intrinsic_w_chain:i32 419:iPTR, i32:i32:$vdata, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4464             :                   // Dst: (IMAGE_ATOMIC_DEC_V1:i32 ?:i32:$vdata, ?:i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4465             : /*10054*/       /*Scope*/ 63, /*->10118*/
    4466             : /*10055*/         OPC_CheckChild3Type, MVT::v2i32,
    4467             : /*10057*/         OPC_RecordChild4, // #3 = $rsrc
    4468             : /*10058*/         OPC_RecordChild5, // #4 = $r128
    4469             : /*10059*/         OPC_MoveChild5,
    4470             : /*10060*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4471             : /*10063*/         OPC_MoveParent,
    4472             : /*10064*/         OPC_RecordChild6, // #5 = $da
    4473             : /*10065*/         OPC_MoveChild6,
    4474             : /*10066*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4475             : /*10069*/         OPC_MoveParent,
    4476             : /*10070*/         OPC_RecordChild7, // #6 = $slc
    4477             : /*10071*/         OPC_MoveChild7,
    4478             : /*10072*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4479             : /*10075*/         OPC_MoveParent,
    4480             : /*10076*/         OPC_EmitMergeInputChains1_0,
    4481             : /*10077*/         OPC_EmitInteger, MVT::i16, 1, 
    4482             : /*10080*/         OPC_EmitInteger, MVT::i1, 1, 
    4483             : /*10083*/         OPC_EmitInteger, MVT::i1, 1, 
    4484             : /*10086*/         OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4485             : /*10089*/         OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4486             : /*10092*/         OPC_EmitInteger, MVT::i1, 0, 
    4487             : /*10095*/         OPC_EmitInteger, MVT::i1, 0, 
    4488             : /*10098*/         OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4489             : /*10101*/         OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_DEC_V2), 0|OPFL_Chain,
    4490             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4491             :                   // Src: (intrinsic_w_chain:i32 419:iPTR, i32:i32:$vdata, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4492             :                   // Dst: (IMAGE_ATOMIC_DEC_V2:i32 ?:i32:$vdata, ?:v2i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4493             : /*10118*/       /*Scope*/ 63, /*->10182*/
    4494             : /*10119*/         OPC_CheckChild3Type, MVT::v4i32,
    4495             : /*10121*/         OPC_RecordChild4, // #3 = $rsrc
    4496             : /*10122*/         OPC_RecordChild5, // #4 = $r128
    4497             : /*10123*/         OPC_MoveChild5,
    4498             : /*10124*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4499             : /*10127*/         OPC_MoveParent,
    4500             : /*10128*/         OPC_RecordChild6, // #5 = $da
    4501             : /*10129*/         OPC_MoveChild6,
    4502             : /*10130*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4503             : /*10133*/         OPC_MoveParent,
    4504             : /*10134*/         OPC_RecordChild7, // #6 = $slc
    4505             : /*10135*/         OPC_MoveChild7,
    4506             : /*10136*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4507             : /*10139*/         OPC_MoveParent,
    4508             : /*10140*/         OPC_EmitMergeInputChains1_0,
    4509             : /*10141*/         OPC_EmitInteger, MVT::i16, 1, 
    4510             : /*10144*/         OPC_EmitInteger, MVT::i1, 1, 
    4511             : /*10147*/         OPC_EmitInteger, MVT::i1, 1, 
    4512             : /*10150*/         OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4513             : /*10153*/         OPC_EmitNodeXForm, 1, 4, // as_i1imm
    4514             : /*10156*/         OPC_EmitInteger, MVT::i1, 0, 
    4515             : /*10159*/         OPC_EmitInteger, MVT::i1, 0, 
    4516             : /*10162*/         OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4517             : /*10165*/         OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_DEC_V4), 0|OPFL_Chain,
    4518             :                       MVT::i32, 11/*#Ops*/, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 
    4519             :                   // Src: (intrinsic_w_chain:i32 419:iPTR, i32:i32:$vdata, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4520             :                   // Dst: (IMAGE_ATOMIC_DEC_V4:i32 ?:i32:$vdata, ?:v4i32:$addr, ?:v8i32:$rsrc, 1:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da))
    4521             : /*10182*/       0, /*End of Scope*/
    4522             : /*10183*/     /*Scope*/ 40|128,2/*296*/, /*->10481*/
    4523             : /*10185*/       OPC_CheckChild1Integer, 34|128,3/*418*/, 
    4524             : /*10188*/       OPC_RecordChild2, // #1 = $vsrc
    4525             : /*10189*/       OPC_RecordChild3, // #2 = $vcmp
    4526             : /*10190*/       OPC_RecordChild4, // #3 = $addr
    4527             : /*10191*/       OPC_Scope, 95, /*->10288*/ // 3 children in Scope
    4528             : /*10193*/         OPC_CheckChild4Type, MVT::i32,
    4529             : /*10195*/         OPC_RecordChild5, // #4 = $rsrc
    4530             : /*10196*/         OPC_RecordChild6, // #5 = $r128
    4531             : /*10197*/         OPC_MoveChild6,
    4532             : /*10198*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4533             : /*10201*/         OPC_MoveParent,
    4534             : /*10202*/         OPC_RecordChild7, // #6 = $da
    4535             : /*10203*/         OPC_MoveChild7,
    4536             : /*10204*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4537             : /*10207*/         OPC_MoveParent,
    4538             : /*10208*/         OPC_MoveChild, 8,
    4539             : /*10210*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4540             : /*10213*/         OPC_RecordNode, // #7 = $slc
    4541             : /*10214*/         OPC_MoveParent,
    4542             : /*10215*/         OPC_EmitMergeInputChains1_0,
    4543             : /*10216*/         OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    4544             : /*10219*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    4545             : /*10222*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    4546             : /*10225*/         OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    4547             :                       MVT::i64, 5/*#Ops*/, 8, 1, 9, 2, 10,  // Results = #11
    4548             : /*10236*/         OPC_EmitInteger, MVT::i16, 3, 
    4549             : /*10239*/         OPC_EmitInteger, MVT::i1, 1, 
    4550             : /*10242*/         OPC_EmitInteger, MVT::i1, 1, 
    4551             : /*10245*/         OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4552             : /*10248*/         OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4553             : /*10251*/         OPC_EmitInteger, MVT::i1, 0, 
    4554             : /*10254*/         OPC_EmitInteger, MVT::i1, 0, 
    4555             : /*10257*/         OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4556             : /*10260*/         OPC_EmitNode1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1), 0|OPFL_Chain,
    4557             :                       MVT::i64, 11/*#Ops*/, 11, 3, 4, 12, 13, 14, 15, 16, 17, 18, 19,  // Results = #20
    4558             : /*10277*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    4559             : /*10280*/         OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0|OPFL_Chain,
    4560             :                       MVT::i32, 2/*#Ops*/, 20, 21, 
    4561             :                   // Src: (intrinsic_w_chain:i32 418:iPTR, i32:i32:$vsrc, i32:i32:$vcmp, i32:i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4562             :                   // Dst: (EXTRACT_SUBREG:i32 (IMAGE_ATOMIC_CMPSWAP_V1:i64 (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vsrc, sub0:i32, ?:i32:$vcmp, sub1:i32), ?:i32:$addr, ?:v8i32:$rsrc, 3:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da)), sub0:i32)
    4563             : /*10288*/       /*Scope*/ 95, /*->10384*/
    4564             : /*10289*/         OPC_CheckChild4Type, MVT::v2i32,
    4565             : /*10291*/         OPC_RecordChild5, // #4 = $rsrc
    4566             : /*10292*/         OPC_RecordChild6, // #5 = $r128
    4567             : /*10293*/         OPC_MoveChild6,
    4568             : /*10294*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4569             : /*10297*/         OPC_MoveParent,
    4570             : /*10298*/         OPC_RecordChild7, // #6 = $da
    4571             : /*10299*/         OPC_MoveChild7,
    4572             : /*10300*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4573             : /*10303*/         OPC_MoveParent,
    4574             : /*10304*/         OPC_MoveChild, 8,
    4575             : /*10306*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4576             : /*10309*/         OPC_RecordNode, // #7 = $slc
    4577             : /*10310*/         OPC_MoveParent,
    4578             : /*10311*/         OPC_EmitMergeInputChains1_0,
    4579             : /*10312*/         OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    4580             : /*10315*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    4581             : /*10318*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    4582             : /*10321*/         OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    4583             :                       MVT::i64, 5/*#Ops*/, 8, 1, 9, 2, 10,  // Results = #11
    4584             : /*10332*/         OPC_EmitInteger, MVT::i16, 3, 
    4585             : /*10335*/         OPC_EmitInteger, MVT::i1, 1, 
    4586             : /*10338*/         OPC_EmitInteger, MVT::i1, 1, 
    4587             : /*10341*/         OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4588             : /*10344*/         OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4589             : /*10347*/         OPC_EmitInteger, MVT::i1, 0, 
    4590             : /*10350*/         OPC_EmitInteger, MVT::i1, 0, 
    4591             : /*10353*/         OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4592             : /*10356*/         OPC_EmitNode1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2), 0|OPFL_Chain,
    4593             :                       MVT::i64, 11/*#Ops*/, 11, 3, 4, 12, 13, 14, 15, 16, 17, 18, 19,  // Results = #20
    4594             : /*10373*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    4595             : /*10376*/         OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0|OPFL_Chain,
    4596             :                       MVT::i32, 2/*#Ops*/, 20, 21, 
    4597             :                   // Src: (intrinsic_w_chain:i32 418:iPTR, i32:i32:$vsrc, i32:i32:$vcmp, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4598             :                   // Dst: (EXTRACT_SUBREG:i32 (IMAGE_ATOMIC_CMPSWAP_V2:i64 (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vsrc, sub0:i32, ?:i32:$vcmp, sub1:i32), ?:v2i32:$addr, ?:v8i32:$rsrc, 3:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da)), sub0:i32)
    4599             : /*10384*/       /*Scope*/ 95, /*->10480*/
    4600             : /*10385*/         OPC_CheckChild4Type, MVT::v4i32,
    4601             : /*10387*/         OPC_RecordChild5, // #4 = $rsrc
    4602             : /*10388*/         OPC_RecordChild6, // #5 = $r128
    4603             : /*10389*/         OPC_MoveChild6,
    4604             : /*10390*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4605             : /*10393*/         OPC_MoveParent,
    4606             : /*10394*/         OPC_RecordChild7, // #6 = $da
    4607             : /*10395*/         OPC_MoveChild7,
    4608             : /*10396*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4609             : /*10399*/         OPC_MoveParent,
    4610             : /*10400*/         OPC_MoveChild, 8,
    4611             : /*10402*/         OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4612             : /*10405*/         OPC_RecordNode, // #7 = $slc
    4613             : /*10406*/         OPC_MoveParent,
    4614             : /*10407*/         OPC_EmitMergeInputChains1_0,
    4615             : /*10408*/         OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
    4616             : /*10411*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    4617             : /*10414*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
    4618             : /*10417*/         OPC_EmitNode1, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
    4619             :                       MVT::i64, 5/*#Ops*/, 8, 1, 9, 2, 10,  // Results = #11
    4620             : /*10428*/         OPC_EmitInteger, MVT::i16, 3, 
    4621             : /*10431*/         OPC_EmitInteger, MVT::i1, 1, 
    4622             : /*10434*/         OPC_EmitInteger, MVT::i1, 1, 
    4623             : /*10437*/         OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4624             : /*10440*/         OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4625             : /*10443*/         OPC_EmitInteger, MVT::i1, 0, 
    4626             : /*10446*/         OPC_EmitInteger, MVT::i1, 0, 
    4627             : /*10449*/         OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4628             : /*10452*/         OPC_EmitNode1, TARGET_VAL(AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4), 0|OPFL_Chain,
    4629             :                       MVT::i64, 11/*#Ops*/, 11, 3, 4, 12, 13, 14, 15, 16, 17, 18, 19,  // Results = #20
    4630             : /*10469*/         OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
    4631             : /*10472*/         OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0|OPFL_Chain,
    4632             :                       MVT::i32, 2/*#Ops*/, 20, 21, 
    4633             :                   // Src: (intrinsic_w_chain:i32 418:iPTR, i32:i32:$vsrc, i32:i32:$vcmp, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, (imm:i1):$r128, (imm:i1):$da, (imm:i1):$slc) - Complexity = 17
    4634             :                   // Dst: (EXTRACT_SUBREG:i32 (IMAGE_ATOMIC_CMPSWAP_V4:i64 (REG_SEQUENCE:i64 VReg_64:i32, ?:i32:$vsrc, sub0:i32, ?:i32:$vcmp, sub1:i32), ?:v4i32:$addr, ?:v8i32:$rsrc, 3:i16, 1:i1, 1:i1, (as_i1imm:i1 ?:i1:$slc), (as_i1imm:i1 ?:i1:$r128), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$da)), sub0:i32)
    4635             : /*10480*/       0, /*End of Scope*/
    4636             : /*10481*/     /*Scope*/ 22, /*->10504*/
    4637             : /*10482*/       OPC_CheckChild1Integer, 22|128,4/*534*/, 
    4638             : /*10485*/       OPC_RecordChild2, // #1 = $simm16
    4639             : /*10486*/       OPC_MoveChild2,
    4640             : /*10487*/       OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
    4641             : /*10490*/       OPC_MoveParent,
    4642             : /*10491*/       OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    4643             : /*10493*/       OPC_EmitMergeInputChains1_0,
    4644             : /*10494*/       OPC_EmitNodeXForm, 0, 1, // as_i16imm
    4645             : /*10497*/       OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_GETREG_B32), 0|OPFL_Chain,
    4646             :                     MVT::i32, 1/*#Ops*/, 2, 
    4647             :                 // Src: (intrinsic_w_chain:i32 534:iPTR, (imm:i32):$simm16) - Complexity = 11
    4648             :                 // Dst: (S_GETREG_B32:i32 (as_i16imm:i16 ?:i32:$simm16))
    4649             : /*10504*/     /*Scope*/ 12, /*->10517*/
    4650             : /*10505*/       OPC_CheckChild1Integer, 25|128,4/*537*/, 
    4651             : /*10508*/       OPC_CheckPatternPredicate, 2, // (true) && (Subtarget->getGeneration() >= SISubtarget::SOUTHERN_ISLANDS)
    4652             : /*10510*/       OPC_EmitMergeInputChains1_0,
    4653             : /*10511*/       OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MEMTIME), 0|OPFL_Chain,
    4654             :                     MVT::i64, 0/*#Ops*/, 
    4655             :                 // Src: (intrinsic_w_chain:i64 537:iPTR) - Complexity = 8
    4656             :                 // Dst: (S_MEMTIME:i64)
    4657             : /*10517*/     /*Scope*/ 12, /*->10530*/
    4658             : /*10518*/       OPC_CheckChild1Integer, 24|128,4/*536*/, 
    4659             : /*10521*/       OPC_CheckPatternPredicate, 11, // (true) && (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
    4660             : /*10523*/       OPC_EmitMergeInputChains1_0,
    4661             : /*10524*/       OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MEMREALTIME), 0|OPFL_Chain,
    4662             :                     MVT::i64, 0/*#Ops*/, 
    4663             :                 // Src: (intrinsic_w_chain:i64 536:iPTR) - Complexity = 8
    4664             :                 // Dst: (S_MEMREALTIME:i64)
    4665             : /*10530*/     /*Scope*/ 23|128,6/*791*/, /*->11323*/
    4666             : /*10532*/       OPC_CheckChild1Integer, 45|128,3/*429*/, 
    4667             : /*10535*/       OPC_RecordChild2, // #1 = $addr
    4668             : /*10536*/       OPC_Scope, 27|128,1/*155*/, /*->10694*/ // 5 children in Scope
    4669             : /*10539*/         OPC_CheckChild2Type, MVT::f32,
    4670             : /*10541*/         OPC_RecordChild3, // #2 = $rsrc
    4671             : /*10542*/         OPC_CheckChild3Type, MVT::v8i32,
    4672             : /*10544*/         OPC_RecordChild4, // #3 = $sampler
    4673             : /*10545*/         OPC_RecordChild5, // #4 = $dmask
    4674             : /*10546*/         OPC_RecordChild6, // #5 = $unorm
    4675             : /*10547*/         OPC_RecordChild7, // #6 = $glc
    4676             : /*10548*/         OPC_MoveChild, 8,
    4677             : /*10550*/         OPC_RecordNode, // #7 = $slc
    4678             : /*10551*/         OPC_MoveParent,
    4679             : /*10552*/         OPC_MoveChild, 9,
    4680             : /*10554*/         OPC_RecordNode, // #8 = $lwe
    4681             : /*10555*/         OPC_MoveParent,
    4682             : /*10556*/         OPC_MoveChild, 10,
    4683             : /*10558*/         OPC_RecordNode, // #9 = $da
    4684             : /*10559*/         OPC_MoveParent,
    4685             : /*10560*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->10605
    4686             : /*10563*/           OPC_EmitMergeInputChains1_0,
    4687             : /*10564*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4688             : /*10567*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4689             : /*10570*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4690             : /*10573*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4691             : /*10576*/           OPC_EmitInteger, MVT::i1, 0, 
    4692             : /*10579*/           OPC_EmitInteger, MVT::i1, 0, 
    4693             : /*10582*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4694             : /*10585*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4695             : /*10588*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V1_V1), 0|OPFL_Chain,
    4696             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4697             :                     // Src: (intrinsic_w_chain:f32 429:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4698             :                     // Dst: (IMAGE_GATHER4_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4699             : /*10605*/         /*SwitchType*/ 42, MVT::v2f32,// ->10649
    4700             : /*10607*/           OPC_EmitMergeInputChains1_0,
    4701             : /*10608*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4702             : /*10611*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4703             : /*10614*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4704             : /*10617*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4705             : /*10620*/           OPC_EmitInteger, MVT::i1, 0, 
    4706             : /*10623*/           OPC_EmitInteger, MVT::i1, 0, 
    4707             : /*10626*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4708             : /*10629*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4709             : /*10632*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V2_V1), 0|OPFL_Chain,
    4710             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4711             :                     // Src: (intrinsic_w_chain:v2f32 429:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4712             :                     // Dst: (IMAGE_GATHER4_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4713             : /*10649*/         /*SwitchType*/ 42, MVT::v4f32,// ->10693
    4714             : /*10651*/           OPC_EmitMergeInputChains1_0,
    4715             : /*10652*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4716             : /*10655*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4717             : /*10658*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4718             : /*10661*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4719             : /*10664*/           OPC_EmitInteger, MVT::i1, 0, 
    4720             : /*10667*/           OPC_EmitInteger, MVT::i1, 0, 
    4721             : /*10670*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4722             : /*10673*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4723             : /*10676*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V4_V1), 0|OPFL_Chain,
    4724             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4725             :                     // Src: (intrinsic_w_chain:v4f32 429:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4726             :                     // Dst: (IMAGE_GATHER4_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4727             : /*10693*/         0, // EndSwitchType
    4728             : /*10694*/       /*Scope*/ 27|128,1/*155*/, /*->10851*/
    4729             : /*10696*/         OPC_CheckChild2Type, MVT::v2f32,
    4730             : /*10698*/         OPC_RecordChild3, // #2 = $rsrc
    4731             : /*10699*/         OPC_CheckChild3Type, MVT::v8i32,
    4732             : /*10701*/         OPC_RecordChild4, // #3 = $sampler
    4733             : /*10702*/         OPC_RecordChild5, // #4 = $dmask
    4734             : /*10703*/         OPC_RecordChild6, // #5 = $unorm
    4735             : /*10704*/         OPC_RecordChild7, // #6 = $glc
    4736             : /*10705*/         OPC_MoveChild, 8,
    4737             : /*10707*/         OPC_RecordNode, // #7 = $slc
    4738             : /*10708*/         OPC_MoveParent,
    4739             : /*10709*/         OPC_MoveChild, 9,
    4740             : /*10711*/         OPC_RecordNode, // #8 = $lwe
    4741             : /*10712*/         OPC_MoveParent,
    4742             : /*10713*/         OPC_MoveChild, 10,
    4743             : /*10715*/         OPC_RecordNode, // #9 = $da
    4744             : /*10716*/         OPC_MoveParent,
    4745             : /*10717*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->10762
    4746             : /*10720*/           OPC_EmitMergeInputChains1_0,
    4747             : /*10721*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4748             : /*10724*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4749             : /*10727*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4750             : /*10730*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4751             : /*10733*/           OPC_EmitInteger, MVT::i1, 0, 
    4752             : /*10736*/           OPC_EmitInteger, MVT::i1, 0, 
    4753             : /*10739*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4754             : /*10742*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4755             : /*10745*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V1_V2), 0|OPFL_Chain,
    4756             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4757             :                     // Src: (intrinsic_w_chain:f32 429:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4758             :                     // Dst: (IMAGE_GATHER4_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4759             : /*10762*/         /*SwitchType*/ 42, MVT::v2f32,// ->10806
    4760             : /*10764*/           OPC_EmitMergeInputChains1_0,
    4761             : /*10765*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4762             : /*10768*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4763             : /*10771*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4764             : /*10774*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4765             : /*10777*/           OPC_EmitInteger, MVT::i1, 0, 
    4766             : /*10780*/           OPC_EmitInteger, MVT::i1, 0, 
    4767             : /*10783*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4768             : /*10786*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4769             : /*10789*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V2_V2), 0|OPFL_Chain,
    4770             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4771             :                     // Src: (intrinsic_w_chain:v2f32 429:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4772             :                     // Dst: (IMAGE_GATHER4_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4773             : /*10806*/         /*SwitchType*/ 42, MVT::v4f32,// ->10850
    4774             : /*10808*/           OPC_EmitMergeInputChains1_0,
    4775             : /*10809*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4776             : /*10812*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4777             : /*10815*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4778             : /*10818*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4779             : /*10821*/           OPC_EmitInteger, MVT::i1, 0, 
    4780             : /*10824*/           OPC_EmitInteger, MVT::i1, 0, 
    4781             : /*10827*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4782             : /*10830*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4783             : /*10833*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V4_V2), 0|OPFL_Chain,
    4784             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4785             :                     // Src: (intrinsic_w_chain:v4f32 429:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4786             :                     // Dst: (IMAGE_GATHER4_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4787             : /*10850*/         0, // EndSwitchType
    4788             : /*10851*/       /*Scope*/ 27|128,1/*155*/, /*->11008*/
    4789             : /*10853*/         OPC_CheckChild2Type, MVT::v4f32,
    4790             : /*10855*/         OPC_RecordChild3, // #2 = $rsrc
    4791             : /*10856*/         OPC_CheckChild3Type, MVT::v8i32,
    4792             : /*10858*/         OPC_RecordChild4, // #3 = $sampler
    4793             : /*10859*/         OPC_RecordChild5, // #4 = $dmask
    4794             : /*10860*/         OPC_RecordChild6, // #5 = $unorm
    4795             : /*10861*/         OPC_RecordChild7, // #6 = $glc
    4796             : /*10862*/         OPC_MoveChild, 8,
    4797             : /*10864*/         OPC_RecordNode, // #7 = $slc
    4798             : /*10865*/         OPC_MoveParent,
    4799             : /*10866*/         OPC_MoveChild, 9,
    4800             : /*10868*/         OPC_RecordNode, // #8 = $lwe
    4801             : /*10869*/         OPC_MoveParent,
    4802             : /*10870*/         OPC_MoveChild, 10,
    4803             : /*10872*/         OPC_RecordNode, // #9 = $da
    4804             : /*10873*/         OPC_MoveParent,
    4805             : /*10874*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->10919
    4806             : /*10877*/           OPC_EmitMergeInputChains1_0,
    4807             : /*10878*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4808             : /*10881*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4809             : /*10884*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4810             : /*10887*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4811             : /*10890*/           OPC_EmitInteger, MVT::i1, 0, 
    4812             : /*10893*/           OPC_EmitInteger, MVT::i1, 0, 
    4813             : /*10896*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4814             : /*10899*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4815             : /*10902*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V1_V4), 0|OPFL_Chain,
    4816             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4817             :                     // Src: (intrinsic_w_chain:f32 429:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4818             :                     // Dst: (IMAGE_GATHER4_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4819             : /*10919*/         /*SwitchType*/ 42, MVT::v2f32,// ->10963
    4820             : /*10921*/           OPC_EmitMergeInputChains1_0,
    4821             : /*10922*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4822             : /*10925*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4823             : /*10928*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4824             : /*10931*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4825             : /*10934*/           OPC_EmitInteger, MVT::i1, 0, 
    4826             : /*10937*/           OPC_EmitInteger, MVT::i1, 0, 
    4827             : /*10940*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4828             : /*10943*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4829             : /*10946*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V2_V4), 0|OPFL_Chain,
    4830             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4831             :                     // Src: (intrinsic_w_chain:v2f32 429:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4832             :                     // Dst: (IMAGE_GATHER4_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4833             : /*10963*/         /*SwitchType*/ 42, MVT::v4f32,// ->11007
    4834             : /*10965*/           OPC_EmitMergeInputChains1_0,
    4835             : /*10966*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4836             : /*10969*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4837             : /*10972*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4838             : /*10975*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4839             : /*10978*/           OPC_EmitInteger, MVT::i1, 0, 
    4840             : /*10981*/           OPC_EmitInteger, MVT::i1, 0, 
    4841             : /*10984*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4842             : /*10987*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4843             : /*10990*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V4_V4), 0|OPFL_Chain,
    4844             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4845             :                     // Src: (intrinsic_w_chain:v4f32 429:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4846             :                     // Dst: (IMAGE_GATHER4_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4847             : /*11007*/         0, // EndSwitchType
    4848             : /*11008*/       /*Scope*/ 27|128,1/*155*/, /*->11165*/
    4849             : /*11010*/         OPC_CheckChild2Type, MVT::v8f32,
    4850             : /*11012*/         OPC_RecordChild3, // #2 = $rsrc
    4851             : /*11013*/         OPC_CheckChild3Type, MVT::v8i32,
    4852             : /*11015*/         OPC_RecordChild4, // #3 = $sampler
    4853             : /*11016*/         OPC_RecordChild5, // #4 = $dmask
    4854             : /*11017*/         OPC_RecordChild6, // #5 = $unorm
    4855             : /*11018*/         OPC_RecordChild7, // #6 = $glc
    4856             : /*11019*/         OPC_MoveChild, 8,
    4857             : /*11021*/         OPC_RecordNode, // #7 = $slc
    4858             : /*11022*/         OPC_MoveParent,
    4859             : /*11023*/         OPC_MoveChild, 9,
    4860             : /*11025*/         OPC_RecordNode, // #8 = $lwe
    4861             : /*11026*/         OPC_MoveParent,
    4862             : /*11027*/         OPC_MoveChild, 10,
    4863             : /*11029*/         OPC_RecordNode, // #9 = $da
    4864             : /*11030*/         OPC_MoveParent,
    4865             : /*11031*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->11076
    4866             : /*11034*/           OPC_EmitMergeInputChains1_0,
    4867             : /*11035*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4868             : /*11038*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4869             : /*11041*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4870             : /*11044*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4871             : /*11047*/           OPC_EmitInteger, MVT::i1, 0, 
    4872             : /*11050*/           OPC_EmitInteger, MVT::i1, 0, 
    4873             : /*11053*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4874             : /*11056*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4875             : /*11059*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V1_V8), 0|OPFL_Chain,
    4876             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4877             :                     // Src: (intrinsic_w_chain:f32 429:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4878             :                     // Dst: (IMAGE_GATHER4_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4879             : /*11076*/         /*SwitchType*/ 42, MVT::v2f32,// ->11120
    4880             : /*11078*/           OPC_EmitMergeInputChains1_0,
    4881             : /*11079*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4882             : /*11082*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4883             : /*11085*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4884             : /*11088*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4885             : /*11091*/           OPC_EmitInteger, MVT::i1, 0, 
    4886             : /*11094*/           OPC_EmitInteger, MVT::i1, 0, 
    4887             : /*11097*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4888             : /*11100*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4889             : /*11103*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V2_V8), 0|OPFL_Chain,
    4890             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4891             :                     // Src: (intrinsic_w_chain:v2f32 429:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4892             :                     // Dst: (IMAGE_GATHER4_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4893             : /*11120*/         /*SwitchType*/ 42, MVT::v4f32,// ->11164
    4894             : /*11122*/           OPC_EmitMergeInputChains1_0,
    4895             : /*11123*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4896             : /*11126*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4897             : /*11129*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4898             : /*11132*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4899             : /*11135*/           OPC_EmitInteger, MVT::i1, 0, 
    4900             : /*11138*/           OPC_EmitInteger, MVT::i1, 0, 
    4901             : /*11141*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4902             : /*11144*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4903             : /*11147*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V4_V8), 0|OPFL_Chain,
    4904             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4905             :                     // Src: (intrinsic_w_chain:v4f32 429:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4906             :                     // Dst: (IMAGE_GATHER4_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4907             : /*11164*/         0, // EndSwitchType
    4908             : /*11165*/       /*Scope*/ 27|128,1/*155*/, /*->11322*/
    4909             : /*11167*/         OPC_CheckChild2Type, MVT::v16f32,
    4910             : /*11169*/         OPC_RecordChild3, // #2 = $rsrc
    4911             : /*11170*/         OPC_CheckChild3Type, MVT::v8i32,
    4912             : /*11172*/         OPC_RecordChild4, // #3 = $sampler
    4913             : /*11173*/         OPC_RecordChild5, // #4 = $dmask
    4914             : /*11174*/         OPC_RecordChild6, // #5 = $unorm
    4915             : /*11175*/         OPC_RecordChild7, // #6 = $glc
    4916             : /*11176*/         OPC_MoveChild, 8,
    4917             : /*11178*/         OPC_RecordNode, // #7 = $slc
    4918             : /*11179*/         OPC_MoveParent,
    4919             : /*11180*/         OPC_MoveChild, 9,
    4920             : /*11182*/         OPC_RecordNode, // #8 = $lwe
    4921             : /*11183*/         OPC_MoveParent,
    4922             : /*11184*/         OPC_MoveChild, 10,
    4923             : /*11186*/         OPC_RecordNode, // #9 = $da
    4924             : /*11187*/         OPC_MoveParent,
    4925             : /*11188*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->11233
    4926             : /*11191*/           OPC_EmitMergeInputChains1_0,
    4927             : /*11192*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4928             : /*11195*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4929             : /*11198*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4930             : /*11201*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4931             : /*11204*/           OPC_EmitInteger, MVT::i1, 0, 
    4932             : /*11207*/           OPC_EmitInteger, MVT::i1, 0, 
    4933             : /*11210*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4934             : /*11213*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4935             : /*11216*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V1_V16), 0|OPFL_Chain,
    4936             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4937             :                     // Src: (intrinsic_w_chain:f32 429:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4938             :                     // Dst: (IMAGE_GATHER4_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4939             : /*11233*/         /*SwitchType*/ 42, MVT::v2f32,// ->11277
    4940             : /*11235*/           OPC_EmitMergeInputChains1_0,
    4941             : /*11236*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4942             : /*11239*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4943             : /*11242*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4944             : /*11245*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4945             : /*11248*/           OPC_EmitInteger, MVT::i1, 0, 
    4946             : /*11251*/           OPC_EmitInteger, MVT::i1, 0, 
    4947             : /*11254*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4948             : /*11257*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4949             : /*11260*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V2_V16), 0|OPFL_Chain,
    4950             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4951             :                     // Src: (intrinsic_w_chain:v2f32 429:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4952             :                     // Dst: (IMAGE_GATHER4_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4953             : /*11277*/         /*SwitchType*/ 42, MVT::v4f32,// ->11321
    4954             : /*11279*/           OPC_EmitMergeInputChains1_0,
    4955             : /*11280*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4956             : /*11283*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4957             : /*11286*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4958             : /*11289*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4959             : /*11292*/           OPC_EmitInteger, MVT::i1, 0, 
    4960             : /*11295*/           OPC_EmitInteger, MVT::i1, 0, 
    4961             : /*11298*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4962             : /*11301*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4963             : /*11304*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V4_V16), 0|OPFL_Chain,
    4964             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    4965             :                     // Src: (intrinsic_w_chain:v4f32 429:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    4966             :                     // Dst: (IMAGE_GATHER4_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    4967             : /*11321*/         0, // EndSwitchType
    4968             : /*11322*/       0, /*End of Scope*/
    4969             : /*11323*/     /*Scope*/ 23|128,6/*791*/, /*->12116*/
    4970             : /*11325*/       OPC_CheckChild1Integer, 62|128,3/*446*/, 
    4971             : /*11328*/       OPC_RecordChild2, // #1 = $addr
    4972             : /*11329*/       OPC_Scope, 27|128,1/*155*/, /*->11487*/ // 5 children in Scope
    4973             : /*11332*/         OPC_CheckChild2Type, MVT::f32,
    4974             : /*11334*/         OPC_RecordChild3, // #2 = $rsrc
    4975             : /*11335*/         OPC_CheckChild3Type, MVT::v8i32,
    4976             : /*11337*/         OPC_RecordChild4, // #3 = $sampler
    4977             : /*11338*/         OPC_RecordChild5, // #4 = $dmask
    4978             : /*11339*/         OPC_RecordChild6, // #5 = $unorm
    4979             : /*11340*/         OPC_RecordChild7, // #6 = $glc
    4980             : /*11341*/         OPC_MoveChild, 8,
    4981             : /*11343*/         OPC_RecordNode, // #7 = $slc
    4982             : /*11344*/         OPC_MoveParent,
    4983             : /*11345*/         OPC_MoveChild, 9,
    4984             : /*11347*/         OPC_RecordNode, // #8 = $lwe
    4985             : /*11348*/         OPC_MoveParent,
    4986             : /*11349*/         OPC_MoveChild, 10,
    4987             : /*11351*/         OPC_RecordNode, // #9 = $da
    4988             : /*11352*/         OPC_MoveParent,
    4989             : /*11353*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->11398
    4990             : /*11356*/           OPC_EmitMergeInputChains1_0,
    4991             : /*11357*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    4992             : /*11360*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    4993             : /*11363*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    4994             : /*11366*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    4995             : /*11369*/           OPC_EmitInteger, MVT::i1, 0, 
    4996             : /*11372*/           OPC_EmitInteger, MVT::i1, 0, 
    4997             : /*11375*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    4998             : /*11378*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    4999             : /*11381*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V1_V1), 0|OPFL_Chain,
    5000             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5001             :                     // Src: (intrinsic_w_chain:f32 446:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5002             :                     // Dst: (IMAGE_GATHER4_CL_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5003             : /*11398*/         /*SwitchType*/ 42, MVT::v2f32,// ->11442
    5004             : /*11400*/           OPC_EmitMergeInputChains1_0,
    5005             : /*11401*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5006             : /*11404*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5007             : /*11407*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5008             : /*11410*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5009             : /*11413*/           OPC_EmitInteger, MVT::i1, 0, 
    5010             : /*11416*/           OPC_EmitInteger, MVT::i1, 0, 
    5011             : /*11419*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5012             : /*11422*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5013             : /*11425*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V2_V1), 0|OPFL_Chain,
    5014             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5015             :                     // Src: (intrinsic_w_chain:v2f32 446:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5016             :                     // Dst: (IMAGE_GATHER4_CL_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5017             : /*11442*/         /*SwitchType*/ 42, MVT::v4f32,// ->11486
    5018             : /*11444*/           OPC_EmitMergeInputChains1_0,
    5019             : /*11445*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5020             : /*11448*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5021             : /*11451*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5022             : /*11454*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5023             : /*11457*/           OPC_EmitInteger, MVT::i1, 0, 
    5024             : /*11460*/           OPC_EmitInteger, MVT::i1, 0, 
    5025             : /*11463*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5026             : /*11466*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5027             : /*11469*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V4_V1), 0|OPFL_Chain,
    5028             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5029             :                     // Src: (intrinsic_w_chain:v4f32 446:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5030             :                     // Dst: (IMAGE_GATHER4_CL_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5031             : /*11486*/         0, // EndSwitchType
    5032             : /*11487*/       /*Scope*/ 27|128,1/*155*/, /*->11644*/
    5033             : /*11489*/         OPC_CheckChild2Type, MVT::v2f32,
    5034             : /*11491*/         OPC_RecordChild3, // #2 = $rsrc
    5035             : /*11492*/         OPC_CheckChild3Type, MVT::v8i32,
    5036             : /*11494*/         OPC_RecordChild4, // #3 = $sampler
    5037             : /*11495*/         OPC_RecordChild5, // #4 = $dmask
    5038             : /*11496*/         OPC_RecordChild6, // #5 = $unorm
    5039             : /*11497*/         OPC_RecordChild7, // #6 = $glc
    5040             : /*11498*/         OPC_MoveChild, 8,
    5041             : /*11500*/         OPC_RecordNode, // #7 = $slc
    5042             : /*11501*/         OPC_MoveParent,
    5043             : /*11502*/         OPC_MoveChild, 9,
    5044             : /*11504*/         OPC_RecordNode, // #8 = $lwe
    5045             : /*11505*/         OPC_MoveParent,
    5046             : /*11506*/         OPC_MoveChild, 10,
    5047             : /*11508*/         OPC_RecordNode, // #9 = $da
    5048             : /*11509*/         OPC_MoveParent,
    5049             : /*11510*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->11555
    5050             : /*11513*/           OPC_EmitMergeInputChains1_0,
    5051             : /*11514*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5052             : /*11517*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5053             : /*11520*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5054             : /*11523*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5055             : /*11526*/           OPC_EmitInteger, MVT::i1, 0, 
    5056             : /*11529*/           OPC_EmitInteger, MVT::i1, 0, 
    5057             : /*11532*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5058             : /*11535*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5059             : /*11538*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V1_V2), 0|OPFL_Chain,
    5060             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5061             :                     // Src: (intrinsic_w_chain:f32 446:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5062             :                     // Dst: (IMAGE_GATHER4_CL_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5063             : /*11555*/         /*SwitchType*/ 42, MVT::v2f32,// ->11599
    5064             : /*11557*/           OPC_EmitMergeInputChains1_0,
    5065             : /*11558*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5066             : /*11561*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5067             : /*11564*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5068             : /*11567*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5069             : /*11570*/           OPC_EmitInteger, MVT::i1, 0, 
    5070             : /*11573*/           OPC_EmitInteger, MVT::i1, 0, 
    5071             : /*11576*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5072             : /*11579*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5073             : /*11582*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V2_V2), 0|OPFL_Chain,
    5074             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5075             :                     // Src: (intrinsic_w_chain:v2f32 446:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5076             :                     // Dst: (IMAGE_GATHER4_CL_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5077             : /*11599*/         /*SwitchType*/ 42, MVT::v4f32,// ->11643
    5078             : /*11601*/           OPC_EmitMergeInputChains1_0,
    5079             : /*11602*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5080             : /*11605*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5081             : /*11608*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5082             : /*11611*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5083             : /*11614*/           OPC_EmitInteger, MVT::i1, 0, 
    5084             : /*11617*/           OPC_EmitInteger, MVT::i1, 0, 
    5085             : /*11620*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5086             : /*11623*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5087             : /*11626*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V4_V2), 0|OPFL_Chain,
    5088             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5089             :                     // Src: (intrinsic_w_chain:v4f32 446:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5090             :                     // Dst: (IMAGE_GATHER4_CL_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5091             : /*11643*/         0, // EndSwitchType
    5092             : /*11644*/       /*Scope*/ 27|128,1/*155*/, /*->11801*/
    5093             : /*11646*/         OPC_CheckChild2Type, MVT::v4f32,
    5094             : /*11648*/         OPC_RecordChild3, // #2 = $rsrc
    5095             : /*11649*/         OPC_CheckChild3Type, MVT::v8i32,
    5096             : /*11651*/         OPC_RecordChild4, // #3 = $sampler
    5097             : /*11652*/         OPC_RecordChild5, // #4 = $dmask
    5098             : /*11653*/         OPC_RecordChild6, // #5 = $unorm
    5099             : /*11654*/         OPC_RecordChild7, // #6 = $glc
    5100             : /*11655*/         OPC_MoveChild, 8,
    5101             : /*11657*/         OPC_RecordNode, // #7 = $slc
    5102             : /*11658*/         OPC_MoveParent,
    5103             : /*11659*/         OPC_MoveChild, 9,
    5104             : /*11661*/         OPC_RecordNode, // #8 = $lwe
    5105             : /*11662*/         OPC_MoveParent,
    5106             : /*11663*/         OPC_MoveChild, 10,
    5107             : /*11665*/         OPC_RecordNode, // #9 = $da
    5108             : /*11666*/         OPC_MoveParent,
    5109             : /*11667*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->11712
    5110             : /*11670*/           OPC_EmitMergeInputChains1_0,
    5111             : /*11671*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5112             : /*11674*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5113             : /*11677*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5114             : /*11680*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5115             : /*11683*/           OPC_EmitInteger, MVT::i1, 0, 
    5116             : /*11686*/           OPC_EmitInteger, MVT::i1, 0, 
    5117             : /*11689*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5118             : /*11692*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5119             : /*11695*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V1_V4), 0|OPFL_Chain,
    5120             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5121             :                     // Src: (intrinsic_w_chain:f32 446:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5122             :                     // Dst: (IMAGE_GATHER4_CL_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5123             : /*11712*/         /*SwitchType*/ 42, MVT::v2f32,// ->11756
    5124             : /*11714*/           OPC_EmitMergeInputChains1_0,
    5125             : /*11715*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5126             : /*11718*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5127             : /*11721*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5128             : /*11724*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5129             : /*11727*/           OPC_EmitInteger, MVT::i1, 0, 
    5130             : /*11730*/           OPC_EmitInteger, MVT::i1, 0, 
    5131             : /*11733*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5132             : /*11736*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5133             : /*11739*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V2_V4), 0|OPFL_Chain,
    5134             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5135             :                     // Src: (intrinsic_w_chain:v2f32 446:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5136             :                     // Dst: (IMAGE_GATHER4_CL_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5137             : /*11756*/         /*SwitchType*/ 42, MVT::v4f32,// ->11800
    5138             : /*11758*/           OPC_EmitMergeInputChains1_0,
    5139             : /*11759*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5140             : /*11762*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5141             : /*11765*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5142             : /*11768*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5143             : /*11771*/           OPC_EmitInteger, MVT::i1, 0, 
    5144             : /*11774*/           OPC_EmitInteger, MVT::i1, 0, 
    5145             : /*11777*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5146             : /*11780*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5147             : /*11783*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V4_V4), 0|OPFL_Chain,
    5148             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5149             :                     // Src: (intrinsic_w_chain:v4f32 446:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5150             :                     // Dst: (IMAGE_GATHER4_CL_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5151             : /*11800*/         0, // EndSwitchType
    5152             : /*11801*/       /*Scope*/ 27|128,1/*155*/, /*->11958*/
    5153             : /*11803*/         OPC_CheckChild2Type, MVT::v8f32,
    5154             : /*11805*/         OPC_RecordChild3, // #2 = $rsrc
    5155             : /*11806*/         OPC_CheckChild3Type, MVT::v8i32,
    5156             : /*11808*/         OPC_RecordChild4, // #3 = $sampler
    5157             : /*11809*/         OPC_RecordChild5, // #4 = $dmask
    5158             : /*11810*/         OPC_RecordChild6, // #5 = $unorm
    5159             : /*11811*/         OPC_RecordChild7, // #6 = $glc
    5160             : /*11812*/         OPC_MoveChild, 8,
    5161             : /*11814*/         OPC_RecordNode, // #7 = $slc
    5162             : /*11815*/         OPC_MoveParent,
    5163             : /*11816*/         OPC_MoveChild, 9,
    5164             : /*11818*/         OPC_RecordNode, // #8 = $lwe
    5165             : /*11819*/         OPC_MoveParent,
    5166             : /*11820*/         OPC_MoveChild, 10,
    5167             : /*11822*/         OPC_RecordNode, // #9 = $da
    5168             : /*11823*/         OPC_MoveParent,
    5169             : /*11824*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->11869
    5170             : /*11827*/           OPC_EmitMergeInputChains1_0,
    5171             : /*11828*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5172             : /*11831*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5173             : /*11834*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5174             : /*11837*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5175             : /*11840*/           OPC_EmitInteger, MVT::i1, 0, 
    5176             : /*11843*/           OPC_EmitInteger, MVT::i1, 0, 
    5177             : /*11846*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5178             : /*11849*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5179             : /*11852*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V1_V8), 0|OPFL_Chain,
    5180             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5181             :                     // Src: (intrinsic_w_chain:f32 446:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5182             :                     // Dst: (IMAGE_GATHER4_CL_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5183             : /*11869*/         /*SwitchType*/ 42, MVT::v2f32,// ->11913
    5184             : /*11871*/           OPC_EmitMergeInputChains1_0,
    5185             : /*11872*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5186             : /*11875*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5187             : /*11878*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5188             : /*11881*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5189             : /*11884*/           OPC_EmitInteger, MVT::i1, 0, 
    5190             : /*11887*/           OPC_EmitInteger, MVT::i1, 0, 
    5191             : /*11890*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5192             : /*11893*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5193             : /*11896*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V2_V8), 0|OPFL_Chain,
    5194             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5195             :                     // Src: (intrinsic_w_chain:v2f32 446:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5196             :                     // Dst: (IMAGE_GATHER4_CL_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5197             : /*11913*/         /*SwitchType*/ 42, MVT::v4f32,// ->11957
    5198             : /*11915*/           OPC_EmitMergeInputChains1_0,
    5199             : /*11916*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5200             : /*11919*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5201             : /*11922*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5202             : /*11925*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5203             : /*11928*/           OPC_EmitInteger, MVT::i1, 0, 
    5204             : /*11931*/           OPC_EmitInteger, MVT::i1, 0, 
    5205             : /*11934*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5206             : /*11937*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5207             : /*11940*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V4_V8), 0|OPFL_Chain,
    5208             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5209             :                     // Src: (intrinsic_w_chain:v4f32 446:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5210             :                     // Dst: (IMAGE_GATHER4_CL_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5211             : /*11957*/         0, // EndSwitchType
    5212             : /*11958*/       /*Scope*/ 27|128,1/*155*/, /*->12115*/
    5213             : /*11960*/         OPC_CheckChild2Type, MVT::v16f32,
    5214             : /*11962*/         OPC_RecordChild3, // #2 = $rsrc
    5215             : /*11963*/         OPC_CheckChild3Type, MVT::v8i32,
    5216             : /*11965*/         OPC_RecordChild4, // #3 = $sampler
    5217             : /*11966*/         OPC_RecordChild5, // #4 = $dmask
    5218             : /*11967*/         OPC_RecordChild6, // #5 = $unorm
    5219             : /*11968*/         OPC_RecordChild7, // #6 = $glc
    5220             : /*11969*/         OPC_MoveChild, 8,
    5221             : /*11971*/         OPC_RecordNode, // #7 = $slc
    5222             : /*11972*/         OPC_MoveParent,
    5223             : /*11973*/         OPC_MoveChild, 9,
    5224             : /*11975*/         OPC_RecordNode, // #8 = $lwe
    5225             : /*11976*/         OPC_MoveParent,
    5226             : /*11977*/         OPC_MoveChild, 10,
    5227             : /*11979*/         OPC_RecordNode, // #9 = $da
    5228             : /*11980*/         OPC_MoveParent,
    5229             : /*11981*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->12026
    5230             : /*11984*/           OPC_EmitMergeInputChains1_0,
    5231             : /*11985*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5232             : /*11988*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5233             : /*11991*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5234             : /*11994*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5235             : /*11997*/           OPC_EmitInteger, MVT::i1, 0, 
    5236             : /*12000*/           OPC_EmitInteger, MVT::i1, 0, 
    5237             : /*12003*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5238             : /*12006*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5239             : /*12009*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V1_V16), 0|OPFL_Chain,
    5240             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5241             :                     // Src: (intrinsic_w_chain:f32 446:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5242             :                     // Dst: (IMAGE_GATHER4_CL_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5243             : /*12026*/         /*SwitchType*/ 42, MVT::v2f32,// ->12070
    5244             : /*12028*/           OPC_EmitMergeInputChains1_0,
    5245             : /*12029*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5246             : /*12032*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5247             : /*12035*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5248             : /*12038*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5249             : /*12041*/           OPC_EmitInteger, MVT::i1, 0, 
    5250             : /*12044*/           OPC_EmitInteger, MVT::i1, 0, 
    5251             : /*12047*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5252             : /*12050*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5253             : /*12053*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V2_V16), 0|OPFL_Chain,
    5254             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5255             :                     // Src: (intrinsic_w_chain:v2f32 446:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5256             :                     // Dst: (IMAGE_GATHER4_CL_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5257             : /*12070*/         /*SwitchType*/ 42, MVT::v4f32,// ->12114
    5258             : /*12072*/           OPC_EmitMergeInputChains1_0,
    5259             : /*12073*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5260             : /*12076*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5261             : /*12079*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5262             : /*12082*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5263             : /*12085*/           OPC_EmitInteger, MVT::i1, 0, 
    5264             : /*12088*/           OPC_EmitInteger, MVT::i1, 0, 
    5265             : /*12091*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5266             : /*12094*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5267             : /*12097*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V4_V16), 0|OPFL_Chain,
    5268             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5269             :                     // Src: (intrinsic_w_chain:v4f32 446:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5270             :                     // Dst: (IMAGE_GATHER4_CL_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5271             : /*12114*/         0, // EndSwitchType
    5272             : /*12115*/       0, /*End of Scope*/
    5273             : /*12116*/     /*Scope*/ 23|128,6/*791*/, /*->12909*/
    5274             : /*12118*/       OPC_CheckChild1Integer, 64|128,3/*448*/, 
    5275             : /*12121*/       OPC_RecordChild2, // #1 = $addr
    5276             : /*12122*/       OPC_Scope, 27|128,1/*155*/, /*->12280*/ // 5 children in Scope
    5277             : /*12125*/         OPC_CheckChild2Type, MVT::f32,
    5278             : /*12127*/         OPC_RecordChild3, // #2 = $rsrc
    5279             : /*12128*/         OPC_CheckChild3Type, MVT::v8i32,
    5280             : /*12130*/         OPC_RecordChild4, // #3 = $sampler
    5281             : /*12131*/         OPC_RecordChild5, // #4 = $dmask
    5282             : /*12132*/         OPC_RecordChild6, // #5 = $unorm
    5283             : /*12133*/         OPC_RecordChild7, // #6 = $glc
    5284             : /*12134*/         OPC_MoveChild, 8,
    5285             : /*12136*/         OPC_RecordNode, // #7 = $slc
    5286             : /*12137*/         OPC_MoveParent,
    5287             : /*12138*/         OPC_MoveChild, 9,
    5288             : /*12140*/         OPC_RecordNode, // #8 = $lwe
    5289             : /*12141*/         OPC_MoveParent,
    5290             : /*12142*/         OPC_MoveChild, 10,
    5291             : /*12144*/         OPC_RecordNode, // #9 = $da
    5292             : /*12145*/         OPC_MoveParent,
    5293             : /*12146*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->12191
    5294             : /*12149*/           OPC_EmitMergeInputChains1_0,
    5295             : /*12150*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5296             : /*12153*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5297             : /*12156*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5298             : /*12159*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5299             : /*12162*/           OPC_EmitInteger, MVT::i1, 0, 
    5300             : /*12165*/           OPC_EmitInteger, MVT::i1, 0, 
    5301             : /*12168*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5302             : /*12171*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5303             : /*12174*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V1_V1), 0|OPFL_Chain,
    5304             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5305             :                     // Src: (intrinsic_w_chain:f32 448:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5306             :                     // Dst: (IMAGE_GATHER4_L_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5307             : /*12191*/         /*SwitchType*/ 42, MVT::v2f32,// ->12235
    5308             : /*12193*/           OPC_EmitMergeInputChains1_0,
    5309             : /*12194*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5310             : /*12197*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5311             : /*12200*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5312             : /*12203*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5313             : /*12206*/           OPC_EmitInteger, MVT::i1, 0, 
    5314             : /*12209*/           OPC_EmitInteger, MVT::i1, 0, 
    5315             : /*12212*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5316             : /*12215*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5317             : /*12218*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V2_V1), 0|OPFL_Chain,
    5318             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5319             :                     // Src: (intrinsic_w_chain:v2f32 448:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5320             :                     // Dst: (IMAGE_GATHER4_L_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5321             : /*12235*/         /*SwitchType*/ 42, MVT::v4f32,// ->12279
    5322             : /*12237*/           OPC_EmitMergeInputChains1_0,
    5323             : /*12238*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5324             : /*12241*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5325             : /*12244*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5326             : /*12247*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5327             : /*12250*/           OPC_EmitInteger, MVT::i1, 0, 
    5328             : /*12253*/           OPC_EmitInteger, MVT::i1, 0, 
    5329             : /*12256*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5330             : /*12259*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5331             : /*12262*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V4_V1), 0|OPFL_Chain,
    5332             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5333             :                     // Src: (intrinsic_w_chain:v4f32 448:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5334             :                     // Dst: (IMAGE_GATHER4_L_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5335             : /*12279*/         0, // EndSwitchType
    5336             : /*12280*/       /*Scope*/ 27|128,1/*155*/, /*->12437*/
    5337             : /*12282*/         OPC_CheckChild2Type, MVT::v2f32,
    5338             : /*12284*/         OPC_RecordChild3, // #2 = $rsrc
    5339             : /*12285*/         OPC_CheckChild3Type, MVT::v8i32,
    5340             : /*12287*/         OPC_RecordChild4, // #3 = $sampler
    5341             : /*12288*/         OPC_RecordChild5, // #4 = $dmask
    5342             : /*12289*/         OPC_RecordChild6, // #5 = $unorm
    5343             : /*12290*/         OPC_RecordChild7, // #6 = $glc
    5344             : /*12291*/         OPC_MoveChild, 8,
    5345             : /*12293*/         OPC_RecordNode, // #7 = $slc
    5346             : /*12294*/         OPC_MoveParent,
    5347             : /*12295*/         OPC_MoveChild, 9,
    5348             : /*12297*/         OPC_RecordNode, // #8 = $lwe
    5349             : /*12298*/         OPC_MoveParent,
    5350             : /*12299*/         OPC_MoveChild, 10,
    5351             : /*12301*/         OPC_RecordNode, // #9 = $da
    5352             : /*12302*/         OPC_MoveParent,
    5353             : /*12303*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->12348
    5354             : /*12306*/           OPC_EmitMergeInputChains1_0,
    5355             : /*12307*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5356             : /*12310*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5357             : /*12313*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5358             : /*12316*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5359             : /*12319*/           OPC_EmitInteger, MVT::i1, 0, 
    5360             : /*12322*/           OPC_EmitInteger, MVT::i1, 0, 
    5361             : /*12325*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5362             : /*12328*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5363             : /*12331*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V1_V2), 0|OPFL_Chain,
    5364             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5365             :                     // Src: (intrinsic_w_chain:f32 448:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5366             :                     // Dst: (IMAGE_GATHER4_L_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5367             : /*12348*/         /*SwitchType*/ 42, MVT::v2f32,// ->12392
    5368             : /*12350*/           OPC_EmitMergeInputChains1_0,
    5369             : /*12351*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5370             : /*12354*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5371             : /*12357*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5372             : /*12360*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5373             : /*12363*/           OPC_EmitInteger, MVT::i1, 0, 
    5374             : /*12366*/           OPC_EmitInteger, MVT::i1, 0, 
    5375             : /*12369*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5376             : /*12372*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5377             : /*12375*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V2_V2), 0|OPFL_Chain,
    5378             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5379             :                     // Src: (intrinsic_w_chain:v2f32 448:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5380             :                     // Dst: (IMAGE_GATHER4_L_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5381             : /*12392*/         /*SwitchType*/ 42, MVT::v4f32,// ->12436
    5382             : /*12394*/           OPC_EmitMergeInputChains1_0,
    5383             : /*12395*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5384             : /*12398*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5385             : /*12401*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5386             : /*12404*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5387             : /*12407*/           OPC_EmitInteger, MVT::i1, 0, 
    5388             : /*12410*/           OPC_EmitInteger, MVT::i1, 0, 
    5389             : /*12413*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5390             : /*12416*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5391             : /*12419*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V4_V2), 0|OPFL_Chain,
    5392             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5393             :                     // Src: (intrinsic_w_chain:v4f32 448:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5394             :                     // Dst: (IMAGE_GATHER4_L_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5395             : /*12436*/         0, // EndSwitchType
    5396             : /*12437*/       /*Scope*/ 27|128,1/*155*/, /*->12594*/
    5397             : /*12439*/         OPC_CheckChild2Type, MVT::v4f32,
    5398             : /*12441*/         OPC_RecordChild3, // #2 = $rsrc
    5399             : /*12442*/         OPC_CheckChild3Type, MVT::v8i32,
    5400             : /*12444*/         OPC_RecordChild4, // #3 = $sampler
    5401             : /*12445*/         OPC_RecordChild5, // #4 = $dmask
    5402             : /*12446*/         OPC_RecordChild6, // #5 = $unorm
    5403             : /*12447*/         OPC_RecordChild7, // #6 = $glc
    5404             : /*12448*/         OPC_MoveChild, 8,
    5405             : /*12450*/         OPC_RecordNode, // #7 = $slc
    5406             : /*12451*/         OPC_MoveParent,
    5407             : /*12452*/         OPC_MoveChild, 9,
    5408             : /*12454*/         OPC_RecordNode, // #8 = $lwe
    5409             : /*12455*/         OPC_MoveParent,
    5410             : /*12456*/         OPC_MoveChild, 10,
    5411             : /*12458*/         OPC_RecordNode, // #9 = $da
    5412             : /*12459*/         OPC_MoveParent,
    5413             : /*12460*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->12505
    5414             : /*12463*/           OPC_EmitMergeInputChains1_0,
    5415             : /*12464*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5416             : /*12467*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5417             : /*12470*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5418             : /*12473*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5419             : /*12476*/           OPC_EmitInteger, MVT::i1, 0, 
    5420             : /*12479*/           OPC_EmitInteger, MVT::i1, 0, 
    5421             : /*12482*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5422             : /*12485*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5423             : /*12488*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V1_V4), 0|OPFL_Chain,
    5424             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5425             :                     // Src: (intrinsic_w_chain:f32 448:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5426             :                     // Dst: (IMAGE_GATHER4_L_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5427             : /*12505*/         /*SwitchType*/ 42, MVT::v2f32,// ->12549
    5428             : /*12507*/           OPC_EmitMergeInputChains1_0,
    5429             : /*12508*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5430             : /*12511*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5431             : /*12514*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5432             : /*12517*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5433             : /*12520*/           OPC_EmitInteger, MVT::i1, 0, 
    5434             : /*12523*/           OPC_EmitInteger, MVT::i1, 0, 
    5435             : /*12526*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5436             : /*12529*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5437             : /*12532*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V2_V4), 0|OPFL_Chain,
    5438             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5439             :                     // Src: (intrinsic_w_chain:v2f32 448:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5440             :                     // Dst: (IMAGE_GATHER4_L_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5441             : /*12549*/         /*SwitchType*/ 42, MVT::v4f32,// ->12593
    5442             : /*12551*/           OPC_EmitMergeInputChains1_0,
    5443             : /*12552*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5444             : /*12555*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5445             : /*12558*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5446             : /*12561*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5447             : /*12564*/           OPC_EmitInteger, MVT::i1, 0, 
    5448             : /*12567*/           OPC_EmitInteger, MVT::i1, 0, 
    5449             : /*12570*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5450             : /*12573*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5451             : /*12576*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V4_V4), 0|OPFL_Chain,
    5452             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5453             :                     // Src: (intrinsic_w_chain:v4f32 448:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5454             :                     // Dst: (IMAGE_GATHER4_L_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5455             : /*12593*/         0, // EndSwitchType
    5456             : /*12594*/       /*Scope*/ 27|128,1/*155*/, /*->12751*/
    5457             : /*12596*/         OPC_CheckChild2Type, MVT::v8f32,
    5458             : /*12598*/         OPC_RecordChild3, // #2 = $rsrc
    5459             : /*12599*/         OPC_CheckChild3Type, MVT::v8i32,
    5460             : /*12601*/         OPC_RecordChild4, // #3 = $sampler
    5461             : /*12602*/         OPC_RecordChild5, // #4 = $dmask
    5462             : /*12603*/         OPC_RecordChild6, // #5 = $unorm
    5463             : /*12604*/         OPC_RecordChild7, // #6 = $glc
    5464             : /*12605*/         OPC_MoveChild, 8,
    5465             : /*12607*/         OPC_RecordNode, // #7 = $slc
    5466             : /*12608*/         OPC_MoveParent,
    5467             : /*12609*/         OPC_MoveChild, 9,
    5468             : /*12611*/         OPC_RecordNode, // #8 = $lwe
    5469             : /*12612*/         OPC_MoveParent,
    5470             : /*12613*/         OPC_MoveChild, 10,
    5471             : /*12615*/         OPC_RecordNode, // #9 = $da
    5472             : /*12616*/         OPC_MoveParent,
    5473             : /*12617*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->12662
    5474             : /*12620*/           OPC_EmitMergeInputChains1_0,
    5475             : /*12621*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5476             : /*12624*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5477             : /*12627*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5478             : /*12630*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5479             : /*12633*/           OPC_EmitInteger, MVT::i1, 0, 
    5480             : /*12636*/           OPC_EmitInteger, MVT::i1, 0, 
    5481             : /*12639*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5482             : /*12642*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5483             : /*12645*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V1_V8), 0|OPFL_Chain,
    5484             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5485             :                     // Src: (intrinsic_w_chain:f32 448:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5486             :                     // Dst: (IMAGE_GATHER4_L_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5487             : /*12662*/         /*SwitchType*/ 42, MVT::v2f32,// ->12706
    5488             : /*12664*/           OPC_EmitMergeInputChains1_0,
    5489             : /*12665*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5490             : /*12668*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5491             : /*12671*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5492             : /*12674*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5493             : /*12677*/           OPC_EmitInteger, MVT::i1, 0, 
    5494             : /*12680*/           OPC_EmitInteger, MVT::i1, 0, 
    5495             : /*12683*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5496             : /*12686*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5497             : /*12689*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V2_V8), 0|OPFL_Chain,
    5498             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5499             :                     // Src: (intrinsic_w_chain:v2f32 448:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5500             :                     // Dst: (IMAGE_GATHER4_L_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5501             : /*12706*/         /*SwitchType*/ 42, MVT::v4f32,// ->12750
    5502             : /*12708*/           OPC_EmitMergeInputChains1_0,
    5503             : /*12709*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5504             : /*12712*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5505             : /*12715*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5506             : /*12718*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5507             : /*12721*/           OPC_EmitInteger, MVT::i1, 0, 
    5508             : /*12724*/           OPC_EmitInteger, MVT::i1, 0, 
    5509             : /*12727*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5510             : /*12730*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5511             : /*12733*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V4_V8), 0|OPFL_Chain,
    5512             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5513             :                     // Src: (intrinsic_w_chain:v4f32 448:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5514             :                     // Dst: (IMAGE_GATHER4_L_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5515             : /*12750*/         0, // EndSwitchType
    5516             : /*12751*/       /*Scope*/ 27|128,1/*155*/, /*->12908*/
    5517             : /*12753*/         OPC_CheckChild2Type, MVT::v16f32,
    5518             : /*12755*/         OPC_RecordChild3, // #2 = $rsrc
    5519             : /*12756*/         OPC_CheckChild3Type, MVT::v8i32,
    5520             : /*12758*/         OPC_RecordChild4, // #3 = $sampler
    5521             : /*12759*/         OPC_RecordChild5, // #4 = $dmask
    5522             : /*12760*/         OPC_RecordChild6, // #5 = $unorm
    5523             : /*12761*/         OPC_RecordChild7, // #6 = $glc
    5524             : /*12762*/         OPC_MoveChild, 8,
    5525             : /*12764*/         OPC_RecordNode, // #7 = $slc
    5526             : /*12765*/         OPC_MoveParent,
    5527             : /*12766*/         OPC_MoveChild, 9,
    5528             : /*12768*/         OPC_RecordNode, // #8 = $lwe
    5529             : /*12769*/         OPC_MoveParent,
    5530             : /*12770*/         OPC_MoveChild, 10,
    5531             : /*12772*/         OPC_RecordNode, // #9 = $da
    5532             : /*12773*/         OPC_MoveParent,
    5533             : /*12774*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->12819
    5534             : /*12777*/           OPC_EmitMergeInputChains1_0,
    5535             : /*12778*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5536             : /*12781*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5537             : /*12784*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5538             : /*12787*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5539             : /*12790*/           OPC_EmitInteger, MVT::i1, 0, 
    5540             : /*12793*/           OPC_EmitInteger, MVT::i1, 0, 
    5541             : /*12796*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5542             : /*12799*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5543             : /*12802*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V1_V16), 0|OPFL_Chain,
    5544             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5545             :                     // Src: (intrinsic_w_chain:f32 448:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5546             :                     // Dst: (IMAGE_GATHER4_L_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5547             : /*12819*/         /*SwitchType*/ 42, MVT::v2f32,// ->12863
    5548             : /*12821*/           OPC_EmitMergeInputChains1_0,
    5549             : /*12822*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5550             : /*12825*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5551             : /*12828*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5552             : /*12831*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5553             : /*12834*/           OPC_EmitInteger, MVT::i1, 0, 
    5554             : /*12837*/           OPC_EmitInteger, MVT::i1, 0, 
    5555             : /*12840*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5556             : /*12843*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5557             : /*12846*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V2_V16), 0|OPFL_Chain,
    5558             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5559             :                     // Src: (intrinsic_w_chain:v2f32 448:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5560             :                     // Dst: (IMAGE_GATHER4_L_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5561             : /*12863*/         /*SwitchType*/ 42, MVT::v4f32,// ->12907
    5562             : /*12865*/           OPC_EmitMergeInputChains1_0,
    5563             : /*12866*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5564             : /*12869*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5565             : /*12872*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5566             : /*12875*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5567             : /*12878*/           OPC_EmitInteger, MVT::i1, 0, 
    5568             : /*12881*/           OPC_EmitInteger, MVT::i1, 0, 
    5569             : /*12884*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5570             : /*12887*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5571             : /*12890*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V4_V16), 0|OPFL_Chain,
    5572             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5573             :                     // Src: (intrinsic_w_chain:v4f32 448:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5574             :                     // Dst: (IMAGE_GATHER4_L_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5575             : /*12907*/         0, // EndSwitchType
    5576             : /*12908*/       0, /*End of Scope*/
    5577             : /*12909*/     /*Scope*/ 23|128,6/*791*/, /*->13702*/
    5578             : /*12911*/       OPC_CheckChild1Integer, 46|128,3/*430*/, 
    5579             : /*12914*/       OPC_RecordChild2, // #1 = $addr
    5580             : /*12915*/       OPC_Scope, 27|128,1/*155*/, /*->13073*/ // 5 children in Scope
    5581             : /*12918*/         OPC_CheckChild2Type, MVT::f32,
    5582             : /*12920*/         OPC_RecordChild3, // #2 = $rsrc
    5583             : /*12921*/         OPC_CheckChild3Type, MVT::v8i32,
    5584             : /*12923*/         OPC_RecordChild4, // #3 = $sampler
    5585             : /*12924*/         OPC_RecordChild5, // #4 = $dmask
    5586             : /*12925*/         OPC_RecordChild6, // #5 = $unorm
    5587             : /*12926*/         OPC_RecordChild7, // #6 = $glc
    5588             : /*12927*/         OPC_MoveChild, 8,
    5589             : /*12929*/         OPC_RecordNode, // #7 = $slc
    5590             : /*12930*/         OPC_MoveParent,
    5591             : /*12931*/         OPC_MoveChild, 9,
    5592             : /*12933*/         OPC_RecordNode, // #8 = $lwe
    5593             : /*12934*/         OPC_MoveParent,
    5594             : /*12935*/         OPC_MoveChild, 10,
    5595             : /*12937*/         OPC_RecordNode, // #9 = $da
    5596             : /*12938*/         OPC_MoveParent,
    5597             : /*12939*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->12984
    5598             : /*12942*/           OPC_EmitMergeInputChains1_0,
    5599             : /*12943*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5600             : /*12946*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5601             : /*12949*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5602             : /*12952*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5603             : /*12955*/           OPC_EmitInteger, MVT::i1, 0, 
    5604             : /*12958*/           OPC_EmitInteger, MVT::i1, 0, 
    5605             : /*12961*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5606             : /*12964*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5607             : /*12967*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V1_V1), 0|OPFL_Chain,
    5608             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5609             :                     // Src: (intrinsic_w_chain:f32 430:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5610             :                     // Dst: (IMAGE_GATHER4_B_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5611             : /*12984*/         /*SwitchType*/ 42, MVT::v2f32,// ->13028
    5612             : /*12986*/           OPC_EmitMergeInputChains1_0,
    5613             : /*12987*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5614             : /*12990*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5615             : /*12993*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5616             : /*12996*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5617             : /*12999*/           OPC_EmitInteger, MVT::i1, 0, 
    5618             : /*13002*/           OPC_EmitInteger, MVT::i1, 0, 
    5619             : /*13005*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5620             : /*13008*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5621             : /*13011*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V2_V1), 0|OPFL_Chain,
    5622             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5623             :                     // Src: (intrinsic_w_chain:v2f32 430:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5624             :                     // Dst: (IMAGE_GATHER4_B_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5625             : /*13028*/         /*SwitchType*/ 42, MVT::v4f32,// ->13072
    5626             : /*13030*/           OPC_EmitMergeInputChains1_0,
    5627             : /*13031*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5628             : /*13034*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5629             : /*13037*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5630             : /*13040*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5631             : /*13043*/           OPC_EmitInteger, MVT::i1, 0, 
    5632             : /*13046*/           OPC_EmitInteger, MVT::i1, 0, 
    5633             : /*13049*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5634             : /*13052*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5635             : /*13055*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V4_V1), 0|OPFL_Chain,
    5636             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5637             :                     // Src: (intrinsic_w_chain:v4f32 430:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5638             :                     // Dst: (IMAGE_GATHER4_B_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5639             : /*13072*/         0, // EndSwitchType
    5640             : /*13073*/       /*Scope*/ 27|128,1/*155*/, /*->13230*/
    5641             : /*13075*/         OPC_CheckChild2Type, MVT::v2f32,
    5642             : /*13077*/         OPC_RecordChild3, // #2 = $rsrc
    5643             : /*13078*/         OPC_CheckChild3Type, MVT::v8i32,
    5644             : /*13080*/         OPC_RecordChild4, // #3 = $sampler
    5645             : /*13081*/         OPC_RecordChild5, // #4 = $dmask
    5646             : /*13082*/         OPC_RecordChild6, // #5 = $unorm
    5647             : /*13083*/         OPC_RecordChild7, // #6 = $glc
    5648             : /*13084*/         OPC_MoveChild, 8,
    5649             : /*13086*/         OPC_RecordNode, // #7 = $slc
    5650             : /*13087*/         OPC_MoveParent,
    5651             : /*13088*/         OPC_MoveChild, 9,
    5652             : /*13090*/         OPC_RecordNode, // #8 = $lwe
    5653             : /*13091*/         OPC_MoveParent,
    5654             : /*13092*/         OPC_MoveChild, 10,
    5655             : /*13094*/         OPC_RecordNode, // #9 = $da
    5656             : /*13095*/         OPC_MoveParent,
    5657             : /*13096*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->13141
    5658             : /*13099*/           OPC_EmitMergeInputChains1_0,
    5659             : /*13100*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5660             : /*13103*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5661             : /*13106*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5662             : /*13109*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5663             : /*13112*/           OPC_EmitInteger, MVT::i1, 0, 
    5664             : /*13115*/           OPC_EmitInteger, MVT::i1, 0, 
    5665             : /*13118*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5666             : /*13121*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5667             : /*13124*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V1_V2), 0|OPFL_Chain,
    5668             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5669             :                     // Src: (intrinsic_w_chain:f32 430:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5670             :                     // Dst: (IMAGE_GATHER4_B_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5671             : /*13141*/         /*SwitchType*/ 42, MVT::v2f32,// ->13185
    5672             : /*13143*/           OPC_EmitMergeInputChains1_0,
    5673             : /*13144*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5674             : /*13147*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5675             : /*13150*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5676             : /*13153*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5677             : /*13156*/           OPC_EmitInteger, MVT::i1, 0, 
    5678             : /*13159*/           OPC_EmitInteger, MVT::i1, 0, 
    5679             : /*13162*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5680             : /*13165*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5681             : /*13168*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V2_V2), 0|OPFL_Chain,
    5682             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5683             :                     // Src: (intrinsic_w_chain:v2f32 430:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5684             :                     // Dst: (IMAGE_GATHER4_B_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5685             : /*13185*/         /*SwitchType*/ 42, MVT::v4f32,// ->13229
    5686             : /*13187*/           OPC_EmitMergeInputChains1_0,
    5687             : /*13188*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5688             : /*13191*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5689             : /*13194*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5690             : /*13197*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5691             : /*13200*/           OPC_EmitInteger, MVT::i1, 0, 
    5692             : /*13203*/           OPC_EmitInteger, MVT::i1, 0, 
    5693             : /*13206*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5694             : /*13209*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5695             : /*13212*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V4_V2), 0|OPFL_Chain,
    5696             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5697             :                     // Src: (intrinsic_w_chain:v4f32 430:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5698             :                     // Dst: (IMAGE_GATHER4_B_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5699             : /*13229*/         0, // EndSwitchType
    5700             : /*13230*/       /*Scope*/ 27|128,1/*155*/, /*->13387*/
    5701             : /*13232*/         OPC_CheckChild2Type, MVT::v4f32,
    5702             : /*13234*/         OPC_RecordChild3, // #2 = $rsrc
    5703             : /*13235*/         OPC_CheckChild3Type, MVT::v8i32,
    5704             : /*13237*/         OPC_RecordChild4, // #3 = $sampler
    5705             : /*13238*/         OPC_RecordChild5, // #4 = $dmask
    5706             : /*13239*/         OPC_RecordChild6, // #5 = $unorm
    5707             : /*13240*/         OPC_RecordChild7, // #6 = $glc
    5708             : /*13241*/         OPC_MoveChild, 8,
    5709             : /*13243*/         OPC_RecordNode, // #7 = $slc
    5710             : /*13244*/         OPC_MoveParent,
    5711             : /*13245*/         OPC_MoveChild, 9,
    5712             : /*13247*/         OPC_RecordNode, // #8 = $lwe
    5713             : /*13248*/         OPC_MoveParent,
    5714             : /*13249*/         OPC_MoveChild, 10,
    5715             : /*13251*/         OPC_RecordNode, // #9 = $da
    5716             : /*13252*/         OPC_MoveParent,
    5717             : /*13253*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->13298
    5718             : /*13256*/           OPC_EmitMergeInputChains1_0,
    5719             : /*13257*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5720             : /*13260*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5721             : /*13263*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5722             : /*13266*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5723             : /*13269*/           OPC_EmitInteger, MVT::i1, 0, 
    5724             : /*13272*/           OPC_EmitInteger, MVT::i1, 0, 
    5725             : /*13275*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5726             : /*13278*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5727             : /*13281*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V1_V4), 0|OPFL_Chain,
    5728             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5729             :                     // Src: (intrinsic_w_chain:f32 430:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5730             :                     // Dst: (IMAGE_GATHER4_B_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5731             : /*13298*/         /*SwitchType*/ 42, MVT::v2f32,// ->13342
    5732             : /*13300*/           OPC_EmitMergeInputChains1_0,
    5733             : /*13301*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5734             : /*13304*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5735             : /*13307*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5736             : /*13310*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5737             : /*13313*/           OPC_EmitInteger, MVT::i1, 0, 
    5738             : /*13316*/           OPC_EmitInteger, MVT::i1, 0, 
    5739             : /*13319*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5740             : /*13322*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5741             : /*13325*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V2_V4), 0|OPFL_Chain,
    5742             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5743             :                     // Src: (intrinsic_w_chain:v2f32 430:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5744             :                     // Dst: (IMAGE_GATHER4_B_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5745             : /*13342*/         /*SwitchType*/ 42, MVT::v4f32,// ->13386
    5746             : /*13344*/           OPC_EmitMergeInputChains1_0,
    5747             : /*13345*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5748             : /*13348*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5749             : /*13351*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5750             : /*13354*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5751             : /*13357*/           OPC_EmitInteger, MVT::i1, 0, 
    5752             : /*13360*/           OPC_EmitInteger, MVT::i1, 0, 
    5753             : /*13363*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5754             : /*13366*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5755             : /*13369*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V4_V4), 0|OPFL_Chain,
    5756             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5757             :                     // Src: (intrinsic_w_chain:v4f32 430:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5758             :                     // Dst: (IMAGE_GATHER4_B_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5759             : /*13386*/         0, // EndSwitchType
    5760             : /*13387*/       /*Scope*/ 27|128,1/*155*/, /*->13544*/
    5761             : /*13389*/         OPC_CheckChild2Type, MVT::v8f32,
    5762             : /*13391*/         OPC_RecordChild3, // #2 = $rsrc
    5763             : /*13392*/         OPC_CheckChild3Type, MVT::v8i32,
    5764             : /*13394*/         OPC_RecordChild4, // #3 = $sampler
    5765             : /*13395*/         OPC_RecordChild5, // #4 = $dmask
    5766             : /*13396*/         OPC_RecordChild6, // #5 = $unorm
    5767             : /*13397*/         OPC_RecordChild7, // #6 = $glc
    5768             : /*13398*/         OPC_MoveChild, 8,
    5769             : /*13400*/         OPC_RecordNode, // #7 = $slc
    5770             : /*13401*/         OPC_MoveParent,
    5771             : /*13402*/         OPC_MoveChild, 9,
    5772             : /*13404*/         OPC_RecordNode, // #8 = $lwe
    5773             : /*13405*/         OPC_MoveParent,
    5774             : /*13406*/         OPC_MoveChild, 10,
    5775             : /*13408*/         OPC_RecordNode, // #9 = $da
    5776             : /*13409*/         OPC_MoveParent,
    5777             : /*13410*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->13455
    5778             : /*13413*/           OPC_EmitMergeInputChains1_0,
    5779             : /*13414*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5780             : /*13417*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5781             : /*13420*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5782             : /*13423*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5783             : /*13426*/           OPC_EmitInteger, MVT::i1, 0, 
    5784             : /*13429*/           OPC_EmitInteger, MVT::i1, 0, 
    5785             : /*13432*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5786             : /*13435*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5787             : /*13438*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V1_V8), 0|OPFL_Chain,
    5788             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5789             :                     // Src: (intrinsic_w_chain:f32 430:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5790             :                     // Dst: (IMAGE_GATHER4_B_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5791             : /*13455*/         /*SwitchType*/ 42, MVT::v2f32,// ->13499
    5792             : /*13457*/           OPC_EmitMergeInputChains1_0,
    5793             : /*13458*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5794             : /*13461*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5795             : /*13464*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5796             : /*13467*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5797             : /*13470*/           OPC_EmitInteger, MVT::i1, 0, 
    5798             : /*13473*/           OPC_EmitInteger, MVT::i1, 0, 
    5799             : /*13476*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5800             : /*13479*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5801             : /*13482*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V2_V8), 0|OPFL_Chain,
    5802             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5803             :                     // Src: (intrinsic_w_chain:v2f32 430:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5804             :                     // Dst: (IMAGE_GATHER4_B_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5805             : /*13499*/         /*SwitchType*/ 42, MVT::v4f32,// ->13543
    5806             : /*13501*/           OPC_EmitMergeInputChains1_0,
    5807             : /*13502*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5808             : /*13505*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5809             : /*13508*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5810             : /*13511*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5811             : /*13514*/           OPC_EmitInteger, MVT::i1, 0, 
    5812             : /*13517*/           OPC_EmitInteger, MVT::i1, 0, 
    5813             : /*13520*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5814             : /*13523*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5815             : /*13526*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V4_V8), 0|OPFL_Chain,
    5816             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5817             :                     // Src: (intrinsic_w_chain:v4f32 430:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5818             :                     // Dst: (IMAGE_GATHER4_B_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5819             : /*13543*/         0, // EndSwitchType
    5820             : /*13544*/       /*Scope*/ 27|128,1/*155*/, /*->13701*/
    5821             : /*13546*/         OPC_CheckChild2Type, MVT::v16f32,
    5822             : /*13548*/         OPC_RecordChild3, // #2 = $rsrc
    5823             : /*13549*/         OPC_CheckChild3Type, MVT::v8i32,
    5824             : /*13551*/         OPC_RecordChild4, // #3 = $sampler
    5825             : /*13552*/         OPC_RecordChild5, // #4 = $dmask
    5826             : /*13553*/         OPC_RecordChild6, // #5 = $unorm
    5827             : /*13554*/         OPC_RecordChild7, // #6 = $glc
    5828             : /*13555*/         OPC_MoveChild, 8,
    5829             : /*13557*/         OPC_RecordNode, // #7 = $slc
    5830             : /*13558*/         OPC_MoveParent,
    5831             : /*13559*/         OPC_MoveChild, 9,
    5832             : /*13561*/         OPC_RecordNode, // #8 = $lwe
    5833             : /*13562*/         OPC_MoveParent,
    5834             : /*13563*/         OPC_MoveChild, 10,
    5835             : /*13565*/         OPC_RecordNode, // #9 = $da
    5836             : /*13566*/         OPC_MoveParent,
    5837             : /*13567*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->13612
    5838             : /*13570*/           OPC_EmitMergeInputChains1_0,
    5839             : /*13571*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5840             : /*13574*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5841             : /*13577*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5842             : /*13580*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5843             : /*13583*/           OPC_EmitInteger, MVT::i1, 0, 
    5844             : /*13586*/           OPC_EmitInteger, MVT::i1, 0, 
    5845             : /*13589*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5846             : /*13592*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5847             : /*13595*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V1_V16), 0|OPFL_Chain,
    5848             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5849             :                     // Src: (intrinsic_w_chain:f32 430:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5850             :                     // Dst: (IMAGE_GATHER4_B_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5851             : /*13612*/         /*SwitchType*/ 42, MVT::v2f32,// ->13656
    5852             : /*13614*/           OPC_EmitMergeInputChains1_0,
    5853             : /*13615*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5854             : /*13618*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5855             : /*13621*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5856             : /*13624*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5857             : /*13627*/           OPC_EmitInteger, MVT::i1, 0, 
    5858             : /*13630*/           OPC_EmitInteger, MVT::i1, 0, 
    5859             : /*13633*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5860             : /*13636*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5861             : /*13639*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V2_V16), 0|OPFL_Chain,
    5862             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5863             :                     // Src: (intrinsic_w_chain:v2f32 430:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5864             :                     // Dst: (IMAGE_GATHER4_B_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5865             : /*13656*/         /*SwitchType*/ 42, MVT::v4f32,// ->13700
    5866             : /*13658*/           OPC_EmitMergeInputChains1_0,
    5867             : /*13659*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5868             : /*13662*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5869             : /*13665*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5870             : /*13668*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5871             : /*13671*/           OPC_EmitInteger, MVT::i1, 0, 
    5872             : /*13674*/           OPC_EmitInteger, MVT::i1, 0, 
    5873             : /*13677*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5874             : /*13680*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5875             : /*13683*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V4_V16), 0|OPFL_Chain,
    5876             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5877             :                     // Src: (intrinsic_w_chain:v4f32 430:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5878             :                     // Dst: (IMAGE_GATHER4_B_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5879             : /*13700*/         0, // EndSwitchType
    5880             : /*13701*/       0, /*End of Scope*/
    5881             : /*13702*/     /*Scope*/ 23|128,6/*791*/, /*->14495*/
    5882             : /*13704*/       OPC_CheckChild1Integer, 47|128,3/*431*/, 
    5883             : /*13707*/       OPC_RecordChild2, // #1 = $addr
    5884             : /*13708*/       OPC_Scope, 27|128,1/*155*/, /*->13866*/ // 5 children in Scope
    5885             : /*13711*/         OPC_CheckChild2Type, MVT::f32,
    5886             : /*13713*/         OPC_RecordChild3, // #2 = $rsrc
    5887             : /*13714*/         OPC_CheckChild3Type, MVT::v8i32,
    5888             : /*13716*/         OPC_RecordChild4, // #3 = $sampler
    5889             : /*13717*/         OPC_RecordChild5, // #4 = $dmask
    5890             : /*13718*/         OPC_RecordChild6, // #5 = $unorm
    5891             : /*13719*/         OPC_RecordChild7, // #6 = $glc
    5892             : /*13720*/         OPC_MoveChild, 8,
    5893             : /*13722*/         OPC_RecordNode, // #7 = $slc
    5894             : /*13723*/         OPC_MoveParent,
    5895             : /*13724*/         OPC_MoveChild, 9,
    5896             : /*13726*/         OPC_RecordNode, // #8 = $lwe
    5897             : /*13727*/         OPC_MoveParent,
    5898             : /*13728*/         OPC_MoveChild, 10,
    5899             : /*13730*/         OPC_RecordNode, // #9 = $da
    5900             : /*13731*/         OPC_MoveParent,
    5901             : /*13732*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->13777
    5902             : /*13735*/           OPC_EmitMergeInputChains1_0,
    5903             : /*13736*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5904             : /*13739*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5905             : /*13742*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5906             : /*13745*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5907             : /*13748*/           OPC_EmitInteger, MVT::i1, 0, 
    5908             : /*13751*/           OPC_EmitInteger, MVT::i1, 0, 
    5909             : /*13754*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5910             : /*13757*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5911             : /*13760*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V1_V1), 0|OPFL_Chain,
    5912             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5913             :                     // Src: (intrinsic_w_chain:f32 431:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5914             :                     // Dst: (IMAGE_GATHER4_B_CL_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5915             : /*13777*/         /*SwitchType*/ 42, MVT::v2f32,// ->13821
    5916             : /*13779*/           OPC_EmitMergeInputChains1_0,
    5917             : /*13780*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5918             : /*13783*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5919             : /*13786*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5920             : /*13789*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5921             : /*13792*/           OPC_EmitInteger, MVT::i1, 0, 
    5922             : /*13795*/           OPC_EmitInteger, MVT::i1, 0, 
    5923             : /*13798*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5924             : /*13801*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5925             : /*13804*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V2_V1), 0|OPFL_Chain,
    5926             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5927             :                     // Src: (intrinsic_w_chain:v2f32 431:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5928             :                     // Dst: (IMAGE_GATHER4_B_CL_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5929             : /*13821*/         /*SwitchType*/ 42, MVT::v4f32,// ->13865
    5930             : /*13823*/           OPC_EmitMergeInputChains1_0,
    5931             : /*13824*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5932             : /*13827*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5933             : /*13830*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5934             : /*13833*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5935             : /*13836*/           OPC_EmitInteger, MVT::i1, 0, 
    5936             : /*13839*/           OPC_EmitInteger, MVT::i1, 0, 
    5937             : /*13842*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5938             : /*13845*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5939             : /*13848*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V4_V1), 0|OPFL_Chain,
    5940             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5941             :                     // Src: (intrinsic_w_chain:v4f32 431:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5942             :                     // Dst: (IMAGE_GATHER4_B_CL_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5943             : /*13865*/         0, // EndSwitchType
    5944             : /*13866*/       /*Scope*/ 27|128,1/*155*/, /*->14023*/
    5945             : /*13868*/         OPC_CheckChild2Type, MVT::v2f32,
    5946             : /*13870*/         OPC_RecordChild3, // #2 = $rsrc
    5947             : /*13871*/         OPC_CheckChild3Type, MVT::v8i32,
    5948             : /*13873*/         OPC_RecordChild4, // #3 = $sampler
    5949             : /*13874*/         OPC_RecordChild5, // #4 = $dmask
    5950             : /*13875*/         OPC_RecordChild6, // #5 = $unorm
    5951             : /*13876*/         OPC_RecordChild7, // #6 = $glc
    5952             : /*13877*/         OPC_MoveChild, 8,
    5953             : /*13879*/         OPC_RecordNode, // #7 = $slc
    5954             : /*13880*/         OPC_MoveParent,
    5955             : /*13881*/         OPC_MoveChild, 9,
    5956             : /*13883*/         OPC_RecordNode, // #8 = $lwe
    5957             : /*13884*/         OPC_MoveParent,
    5958             : /*13885*/         OPC_MoveChild, 10,
    5959             : /*13887*/         OPC_RecordNode, // #9 = $da
    5960             : /*13888*/         OPC_MoveParent,
    5961             : /*13889*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->13934
    5962             : /*13892*/           OPC_EmitMergeInputChains1_0,
    5963             : /*13893*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5964             : /*13896*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5965             : /*13899*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5966             : /*13902*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5967             : /*13905*/           OPC_EmitInteger, MVT::i1, 0, 
    5968             : /*13908*/           OPC_EmitInteger, MVT::i1, 0, 
    5969             : /*13911*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5970             : /*13914*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5971             : /*13917*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V1_V2), 0|OPFL_Chain,
    5972             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5973             :                     // Src: (intrinsic_w_chain:f32 431:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5974             :                     // Dst: (IMAGE_GATHER4_B_CL_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5975             : /*13934*/         /*SwitchType*/ 42, MVT::v2f32,// ->13978
    5976             : /*13936*/           OPC_EmitMergeInputChains1_0,
    5977             : /*13937*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5978             : /*13940*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5979             : /*13943*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5980             : /*13946*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5981             : /*13949*/           OPC_EmitInteger, MVT::i1, 0, 
    5982             : /*13952*/           OPC_EmitInteger, MVT::i1, 0, 
    5983             : /*13955*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5984             : /*13958*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5985             : /*13961*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V2_V2), 0|OPFL_Chain,
    5986             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    5987             :                     // Src: (intrinsic_w_chain:v2f32 431:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    5988             :                     // Dst: (IMAGE_GATHER4_B_CL_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    5989             : /*13978*/         /*SwitchType*/ 42, MVT::v4f32,// ->14022
    5990             : /*13980*/           OPC_EmitMergeInputChains1_0,
    5991             : /*13981*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    5992             : /*13984*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    5993             : /*13987*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    5994             : /*13990*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    5995             : /*13993*/           OPC_EmitInteger, MVT::i1, 0, 
    5996             : /*13996*/           OPC_EmitInteger, MVT::i1, 0, 
    5997             : /*13999*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    5998             : /*14002*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    5999             : /*14005*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V4_V2), 0|OPFL_Chain,
    6000             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6001             :                     // Src: (intrinsic_w_chain:v4f32 431:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6002             :                     // Dst: (IMAGE_GATHER4_B_CL_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6003             : /*14022*/         0, // EndSwitchType
    6004             : /*14023*/       /*Scope*/ 27|128,1/*155*/, /*->14180*/
    6005             : /*14025*/         OPC_CheckChild2Type, MVT::v4f32,
    6006             : /*14027*/         OPC_RecordChild3, // #2 = $rsrc
    6007             : /*14028*/         OPC_CheckChild3Type, MVT::v8i32,
    6008             : /*14030*/         OPC_RecordChild4, // #3 = $sampler
    6009             : /*14031*/         OPC_RecordChild5, // #4 = $dmask
    6010             : /*14032*/         OPC_RecordChild6, // #5 = $unorm
    6011             : /*14033*/         OPC_RecordChild7, // #6 = $glc
    6012             : /*14034*/         OPC_MoveChild, 8,
    6013             : /*14036*/         OPC_RecordNode, // #7 = $slc
    6014             : /*14037*/         OPC_MoveParent,
    6015             : /*14038*/         OPC_MoveChild, 9,
    6016             : /*14040*/         OPC_RecordNode, // #8 = $lwe
    6017             : /*14041*/         OPC_MoveParent,
    6018             : /*14042*/         OPC_MoveChild, 10,
    6019             : /*14044*/         OPC_RecordNode, // #9 = $da
    6020             : /*14045*/         OPC_MoveParent,
    6021             : /*14046*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->14091
    6022             : /*14049*/           OPC_EmitMergeInputChains1_0,
    6023             : /*14050*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6024             : /*14053*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6025             : /*14056*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6026             : /*14059*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6027             : /*14062*/           OPC_EmitInteger, MVT::i1, 0, 
    6028             : /*14065*/           OPC_EmitInteger, MVT::i1, 0, 
    6029             : /*14068*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6030             : /*14071*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6031             : /*14074*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V1_V4), 0|OPFL_Chain,
    6032             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6033             :                     // Src: (intrinsic_w_chain:f32 431:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6034             :                     // Dst: (IMAGE_GATHER4_B_CL_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6035             : /*14091*/         /*SwitchType*/ 42, MVT::v2f32,// ->14135
    6036             : /*14093*/           OPC_EmitMergeInputChains1_0,
    6037             : /*14094*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6038             : /*14097*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6039             : /*14100*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6040             : /*14103*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6041             : /*14106*/           OPC_EmitInteger, MVT::i1, 0, 
    6042             : /*14109*/           OPC_EmitInteger, MVT::i1, 0, 
    6043             : /*14112*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6044             : /*14115*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6045             : /*14118*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V2_V4), 0|OPFL_Chain,
    6046             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6047             :                     // Src: (intrinsic_w_chain:v2f32 431:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6048             :                     // Dst: (IMAGE_GATHER4_B_CL_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6049             : /*14135*/         /*SwitchType*/ 42, MVT::v4f32,// ->14179
    6050             : /*14137*/           OPC_EmitMergeInputChains1_0,
    6051             : /*14138*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6052             : /*14141*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6053             : /*14144*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6054             : /*14147*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6055             : /*14150*/           OPC_EmitInteger, MVT::i1, 0, 
    6056             : /*14153*/           OPC_EmitInteger, MVT::i1, 0, 
    6057             : /*14156*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6058             : /*14159*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6059             : /*14162*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V4_V4), 0|OPFL_Chain,
    6060             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6061             :                     // Src: (intrinsic_w_chain:v4f32 431:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6062             :                     // Dst: (IMAGE_GATHER4_B_CL_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6063             : /*14179*/         0, // EndSwitchType
    6064             : /*14180*/       /*Scope*/ 27|128,1/*155*/, /*->14337*/
    6065             : /*14182*/         OPC_CheckChild2Type, MVT::v8f32,
    6066             : /*14184*/         OPC_RecordChild3, // #2 = $rsrc
    6067             : /*14185*/         OPC_CheckChild3Type, MVT::v8i32,
    6068             : /*14187*/         OPC_RecordChild4, // #3 = $sampler
    6069             : /*14188*/         OPC_RecordChild5, // #4 = $dmask
    6070             : /*14189*/         OPC_RecordChild6, // #5 = $unorm
    6071             : /*14190*/         OPC_RecordChild7, // #6 = $glc
    6072             : /*14191*/         OPC_MoveChild, 8,
    6073             : /*14193*/         OPC_RecordNode, // #7 = $slc
    6074             : /*14194*/         OPC_MoveParent,
    6075             : /*14195*/         OPC_MoveChild, 9,
    6076             : /*14197*/         OPC_RecordNode, // #8 = $lwe
    6077             : /*14198*/         OPC_MoveParent,
    6078             : /*14199*/         OPC_MoveChild, 10,
    6079             : /*14201*/         OPC_RecordNode, // #9 = $da
    6080             : /*14202*/         OPC_MoveParent,
    6081             : /*14203*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->14248
    6082             : /*14206*/           OPC_EmitMergeInputChains1_0,
    6083             : /*14207*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6084             : /*14210*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6085             : /*14213*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6086             : /*14216*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6087             : /*14219*/           OPC_EmitInteger, MVT::i1, 0, 
    6088             : /*14222*/           OPC_EmitInteger, MVT::i1, 0, 
    6089             : /*14225*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6090             : /*14228*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6091             : /*14231*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V1_V8), 0|OPFL_Chain,
    6092             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6093             :                     // Src: (intrinsic_w_chain:f32 431:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6094             :                     // Dst: (IMAGE_GATHER4_B_CL_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6095             : /*14248*/         /*SwitchType*/ 42, MVT::v2f32,// ->14292
    6096             : /*14250*/           OPC_EmitMergeInputChains1_0,
    6097             : /*14251*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6098             : /*14254*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6099             : /*14257*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6100             : /*14260*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6101             : /*14263*/           OPC_EmitInteger, MVT::i1, 0, 
    6102             : /*14266*/           OPC_EmitInteger, MVT::i1, 0, 
    6103             : /*14269*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6104             : /*14272*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6105             : /*14275*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V2_V8), 0|OPFL_Chain,
    6106             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6107             :                     // Src: (intrinsic_w_chain:v2f32 431:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6108             :                     // Dst: (IMAGE_GATHER4_B_CL_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6109             : /*14292*/         /*SwitchType*/ 42, MVT::v4f32,// ->14336
    6110             : /*14294*/           OPC_EmitMergeInputChains1_0,
    6111             : /*14295*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6112             : /*14298*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6113             : /*14301*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6114             : /*14304*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6115             : /*14307*/           OPC_EmitInteger, MVT::i1, 0, 
    6116             : /*14310*/           OPC_EmitInteger, MVT::i1, 0, 
    6117             : /*14313*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6118             : /*14316*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6119             : /*14319*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V4_V8), 0|OPFL_Chain,
    6120             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6121             :                     // Src: (intrinsic_w_chain:v4f32 431:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6122             :                     // Dst: (IMAGE_GATHER4_B_CL_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6123             : /*14336*/         0, // EndSwitchType
    6124             : /*14337*/       /*Scope*/ 27|128,1/*155*/, /*->14494*/
    6125             : /*14339*/         OPC_CheckChild2Type, MVT::v16f32,
    6126             : /*14341*/         OPC_RecordChild3, // #2 = $rsrc
    6127             : /*14342*/         OPC_CheckChild3Type, MVT::v8i32,
    6128             : /*14344*/         OPC_RecordChild4, // #3 = $sampler
    6129             : /*14345*/         OPC_RecordChild5, // #4 = $dmask
    6130             : /*14346*/         OPC_RecordChild6, // #5 = $unorm
    6131             : /*14347*/         OPC_RecordChild7, // #6 = $glc
    6132             : /*14348*/         OPC_MoveChild, 8,
    6133             : /*14350*/         OPC_RecordNode, // #7 = $slc
    6134             : /*14351*/         OPC_MoveParent,
    6135             : /*14352*/         OPC_MoveChild, 9,
    6136             : /*14354*/         OPC_RecordNode, // #8 = $lwe
    6137             : /*14355*/         OPC_MoveParent,
    6138             : /*14356*/         OPC_MoveChild, 10,
    6139             : /*14358*/         OPC_RecordNode, // #9 = $da
    6140             : /*14359*/         OPC_MoveParent,
    6141             : /*14360*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->14405
    6142             : /*14363*/           OPC_EmitMergeInputChains1_0,
    6143             : /*14364*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6144             : /*14367*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6145             : /*14370*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6146             : /*14373*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6147             : /*14376*/           OPC_EmitInteger, MVT::i1, 0, 
    6148             : /*14379*/           OPC_EmitInteger, MVT::i1, 0, 
    6149             : /*14382*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6150             : /*14385*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6151             : /*14388*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V1_V16), 0|OPFL_Chain,
    6152             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6153             :                     // Src: (intrinsic_w_chain:f32 431:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6154             :                     // Dst: (IMAGE_GATHER4_B_CL_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6155             : /*14405*/         /*SwitchType*/ 42, MVT::v2f32,// ->14449
    6156             : /*14407*/           OPC_EmitMergeInputChains1_0,
    6157             : /*14408*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6158             : /*14411*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6159             : /*14414*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6160             : /*14417*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6161             : /*14420*/           OPC_EmitInteger, MVT::i1, 0, 
    6162             : /*14423*/           OPC_EmitInteger, MVT::i1, 0, 
    6163             : /*14426*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6164             : /*14429*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6165             : /*14432*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V2_V16), 0|OPFL_Chain,
    6166             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6167             :                     // Src: (intrinsic_w_chain:v2f32 431:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6168             :                     // Dst: (IMAGE_GATHER4_B_CL_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6169             : /*14449*/         /*SwitchType*/ 42, MVT::v4f32,// ->14493
    6170             : /*14451*/           OPC_EmitMergeInputChains1_0,
    6171             : /*14452*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6172             : /*14455*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6173             : /*14458*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6174             : /*14461*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6175             : /*14464*/           OPC_EmitInteger, MVT::i1, 0, 
    6176             : /*14467*/           OPC_EmitInteger, MVT::i1, 0, 
    6177             : /*14470*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6178             : /*14473*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6179             : /*14476*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V4_V16), 0|OPFL_Chain,
    6180             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6181             :                     // Src: (intrinsic_w_chain:v4f32 431:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6182             :                     // Dst: (IMAGE_GATHER4_B_CL_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6183             : /*14493*/         0, // EndSwitchType
    6184             : /*14494*/       0, /*End of Scope*/
    6185             : /*14495*/     /*Scope*/ 23|128,6/*791*/, /*->15288*/
    6186             : /*14497*/       OPC_CheckChild1Integer, 66|128,3/*450*/, 
    6187             : /*14500*/       OPC_RecordChild2, // #1 = $addr
    6188             : /*14501*/       OPC_Scope, 27|128,1/*155*/, /*->14659*/ // 5 children in Scope
    6189             : /*14504*/         OPC_CheckChild2Type, MVT::f32,
    6190             : /*14506*/         OPC_RecordChild3, // #2 = $rsrc
    6191             : /*14507*/         OPC_CheckChild3Type, MVT::v8i32,
    6192             : /*14509*/         OPC_RecordChild4, // #3 = $sampler
    6193             : /*14510*/         OPC_RecordChild5, // #4 = $dmask
    6194             : /*14511*/         OPC_RecordChild6, // #5 = $unorm
    6195             : /*14512*/         OPC_RecordChild7, // #6 = $glc
    6196             : /*14513*/         OPC_MoveChild, 8,
    6197             : /*14515*/         OPC_RecordNode, // #7 = $slc
    6198             : /*14516*/         OPC_MoveParent,
    6199             : /*14517*/         OPC_MoveChild, 9,
    6200             : /*14519*/         OPC_RecordNode, // #8 = $lwe
    6201             : /*14520*/         OPC_MoveParent,
    6202             : /*14521*/         OPC_MoveChild, 10,
    6203             : /*14523*/         OPC_RecordNode, // #9 = $da
    6204             : /*14524*/         OPC_MoveParent,
    6205             : /*14525*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->14570
    6206             : /*14528*/           OPC_EmitMergeInputChains1_0,
    6207             : /*14529*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6208             : /*14532*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6209             : /*14535*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6210             : /*14538*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6211             : /*14541*/           OPC_EmitInteger, MVT::i1, 0, 
    6212             : /*14544*/           OPC_EmitInteger, MVT::i1, 0, 
    6213             : /*14547*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6214             : /*14550*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6215             : /*14553*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V1_V1), 0|OPFL_Chain,
    6216             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6217             :                     // Src: (intrinsic_w_chain:f32 450:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6218             :                     // Dst: (IMAGE_GATHER4_LZ_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6219             : /*14570*/         /*SwitchType*/ 42, MVT::v2f32,// ->14614
    6220             : /*14572*/           OPC_EmitMergeInputChains1_0,
    6221             : /*14573*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6222             : /*14576*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6223             : /*14579*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6224             : /*14582*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6225             : /*14585*/           OPC_EmitInteger, MVT::i1, 0, 
    6226             : /*14588*/           OPC_EmitInteger, MVT::i1, 0, 
    6227             : /*14591*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6228             : /*14594*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6229             : /*14597*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V2_V1), 0|OPFL_Chain,
    6230             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6231             :                     // Src: (intrinsic_w_chain:v2f32 450:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6232             :                     // Dst: (IMAGE_GATHER4_LZ_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6233             : /*14614*/         /*SwitchType*/ 42, MVT::v4f32,// ->14658
    6234             : /*14616*/           OPC_EmitMergeInputChains1_0,
    6235             : /*14617*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6236             : /*14620*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6237             : /*14623*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6238             : /*14626*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6239             : /*14629*/           OPC_EmitInteger, MVT::i1, 0, 
    6240             : /*14632*/           OPC_EmitInteger, MVT::i1, 0, 
    6241             : /*14635*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6242             : /*14638*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6243             : /*14641*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V4_V1), 0|OPFL_Chain,
    6244             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6245             :                     // Src: (intrinsic_w_chain:v4f32 450:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6246             :                     // Dst: (IMAGE_GATHER4_LZ_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6247             : /*14658*/         0, // EndSwitchType
    6248             : /*14659*/       /*Scope*/ 27|128,1/*155*/, /*->14816*/
    6249             : /*14661*/         OPC_CheckChild2Type, MVT::v2f32,
    6250             : /*14663*/         OPC_RecordChild3, // #2 = $rsrc
    6251             : /*14664*/         OPC_CheckChild3Type, MVT::v8i32,
    6252             : /*14666*/         OPC_RecordChild4, // #3 = $sampler
    6253             : /*14667*/         OPC_RecordChild5, // #4 = $dmask
    6254             : /*14668*/         OPC_RecordChild6, // #5 = $unorm
    6255             : /*14669*/         OPC_RecordChild7, // #6 = $glc
    6256             : /*14670*/         OPC_MoveChild, 8,
    6257             : /*14672*/         OPC_RecordNode, // #7 = $slc
    6258             : /*14673*/         OPC_MoveParent,
    6259             : /*14674*/         OPC_MoveChild, 9,
    6260             : /*14676*/         OPC_RecordNode, // #8 = $lwe
    6261             : /*14677*/         OPC_MoveParent,
    6262             : /*14678*/         OPC_MoveChild, 10,
    6263             : /*14680*/         OPC_RecordNode, // #9 = $da
    6264             : /*14681*/         OPC_MoveParent,
    6265             : /*14682*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->14727
    6266             : /*14685*/           OPC_EmitMergeInputChains1_0,
    6267             : /*14686*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6268             : /*14689*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6269             : /*14692*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6270             : /*14695*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6271             : /*14698*/           OPC_EmitInteger, MVT::i1, 0, 
    6272             : /*14701*/           OPC_EmitInteger, MVT::i1, 0, 
    6273             : /*14704*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6274             : /*14707*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6275             : /*14710*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V1_V2), 0|OPFL_Chain,
    6276             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6277             :                     // Src: (intrinsic_w_chain:f32 450:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6278             :                     // Dst: (IMAGE_GATHER4_LZ_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6279             : /*14727*/         /*SwitchType*/ 42, MVT::v2f32,// ->14771
    6280             : /*14729*/           OPC_EmitMergeInputChains1_0,
    6281             : /*14730*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6282             : /*14733*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6283             : /*14736*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6284             : /*14739*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6285             : /*14742*/           OPC_EmitInteger, MVT::i1, 0, 
    6286             : /*14745*/           OPC_EmitInteger, MVT::i1, 0, 
    6287             : /*14748*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6288             : /*14751*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6289             : /*14754*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V2_V2), 0|OPFL_Chain,
    6290             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6291             :                     // Src: (intrinsic_w_chain:v2f32 450:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6292             :                     // Dst: (IMAGE_GATHER4_LZ_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6293             : /*14771*/         /*SwitchType*/ 42, MVT::v4f32,// ->14815
    6294             : /*14773*/           OPC_EmitMergeInputChains1_0,
    6295             : /*14774*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6296             : /*14777*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6297             : /*14780*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6298             : /*14783*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6299             : /*14786*/           OPC_EmitInteger, MVT::i1, 0, 
    6300             : /*14789*/           OPC_EmitInteger, MVT::i1, 0, 
    6301             : /*14792*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6302             : /*14795*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6303             : /*14798*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V4_V2), 0|OPFL_Chain,
    6304             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6305             :                     // Src: (intrinsic_w_chain:v4f32 450:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6306             :                     // Dst: (IMAGE_GATHER4_LZ_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6307             : /*14815*/         0, // EndSwitchType
    6308             : /*14816*/       /*Scope*/ 27|128,1/*155*/, /*->14973*/
    6309             : /*14818*/         OPC_CheckChild2Type, MVT::v4f32,
    6310             : /*14820*/         OPC_RecordChild3, // #2 = $rsrc
    6311             : /*14821*/         OPC_CheckChild3Type, MVT::v8i32,
    6312             : /*14823*/         OPC_RecordChild4, // #3 = $sampler
    6313             : /*14824*/         OPC_RecordChild5, // #4 = $dmask
    6314             : /*14825*/         OPC_RecordChild6, // #5 = $unorm
    6315             : /*14826*/         OPC_RecordChild7, // #6 = $glc
    6316             : /*14827*/         OPC_MoveChild, 8,
    6317             : /*14829*/         OPC_RecordNode, // #7 = $slc
    6318             : /*14830*/         OPC_MoveParent,
    6319             : /*14831*/         OPC_MoveChild, 9,
    6320             : /*14833*/         OPC_RecordNode, // #8 = $lwe
    6321             : /*14834*/         OPC_MoveParent,
    6322             : /*14835*/         OPC_MoveChild, 10,
    6323             : /*14837*/         OPC_RecordNode, // #9 = $da
    6324             : /*14838*/         OPC_MoveParent,
    6325             : /*14839*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->14884
    6326             : /*14842*/           OPC_EmitMergeInputChains1_0,
    6327             : /*14843*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6328             : /*14846*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6329             : /*14849*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6330             : /*14852*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6331             : /*14855*/           OPC_EmitInteger, MVT::i1, 0, 
    6332             : /*14858*/           OPC_EmitInteger, MVT::i1, 0, 
    6333             : /*14861*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6334             : /*14864*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6335             : /*14867*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V1_V4), 0|OPFL_Chain,
    6336             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6337             :                     // Src: (intrinsic_w_chain:f32 450:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6338             :                     // Dst: (IMAGE_GATHER4_LZ_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6339             : /*14884*/         /*SwitchType*/ 42, MVT::v2f32,// ->14928
    6340             : /*14886*/           OPC_EmitMergeInputChains1_0,
    6341             : /*14887*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6342             : /*14890*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6343             : /*14893*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6344             : /*14896*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6345             : /*14899*/           OPC_EmitInteger, MVT::i1, 0, 
    6346             : /*14902*/           OPC_EmitInteger, MVT::i1, 0, 
    6347             : /*14905*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6348             : /*14908*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6349             : /*14911*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V2_V4), 0|OPFL_Chain,
    6350             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6351             :                     // Src: (intrinsic_w_chain:v2f32 450:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6352             :                     // Dst: (IMAGE_GATHER4_LZ_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6353             : /*14928*/         /*SwitchType*/ 42, MVT::v4f32,// ->14972
    6354             : /*14930*/           OPC_EmitMergeInputChains1_0,
    6355             : /*14931*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6356             : /*14934*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6357             : /*14937*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6358             : /*14940*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6359             : /*14943*/           OPC_EmitInteger, MVT::i1, 0, 
    6360             : /*14946*/           OPC_EmitInteger, MVT::i1, 0, 
    6361             : /*14949*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6362             : /*14952*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6363             : /*14955*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V4_V4), 0|OPFL_Chain,
    6364             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6365             :                     // Src: (intrinsic_w_chain:v4f32 450:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6366             :                     // Dst: (IMAGE_GATHER4_LZ_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6367             : /*14972*/         0, // EndSwitchType
    6368             : /*14973*/       /*Scope*/ 27|128,1/*155*/, /*->15130*/
    6369             : /*14975*/         OPC_CheckChild2Type, MVT::v8f32,
    6370             : /*14977*/         OPC_RecordChild3, // #2 = $rsrc
    6371             : /*14978*/         OPC_CheckChild3Type, MVT::v8i32,
    6372             : /*14980*/         OPC_RecordChild4, // #3 = $sampler
    6373             : /*14981*/         OPC_RecordChild5, // #4 = $dmask
    6374             : /*14982*/         OPC_RecordChild6, // #5 = $unorm
    6375             : /*14983*/         OPC_RecordChild7, // #6 = $glc
    6376             : /*14984*/         OPC_MoveChild, 8,
    6377             : /*14986*/         OPC_RecordNode, // #7 = $slc
    6378             : /*14987*/         OPC_MoveParent,
    6379             : /*14988*/         OPC_MoveChild, 9,
    6380             : /*14990*/         OPC_RecordNode, // #8 = $lwe
    6381             : /*14991*/         OPC_MoveParent,
    6382             : /*14992*/         OPC_MoveChild, 10,
    6383             : /*14994*/         OPC_RecordNode, // #9 = $da
    6384             : /*14995*/         OPC_MoveParent,
    6385             : /*14996*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->15041
    6386             : /*14999*/           OPC_EmitMergeInputChains1_0,
    6387             : /*15000*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6388             : /*15003*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6389             : /*15006*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6390             : /*15009*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6391             : /*15012*/           OPC_EmitInteger, MVT::i1, 0, 
    6392             : /*15015*/           OPC_EmitInteger, MVT::i1, 0, 
    6393             : /*15018*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6394             : /*15021*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6395             : /*15024*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V1_V8), 0|OPFL_Chain,
    6396             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6397             :                     // Src: (intrinsic_w_chain:f32 450:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6398             :                     // Dst: (IMAGE_GATHER4_LZ_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6399             : /*15041*/         /*SwitchType*/ 42, MVT::v2f32,// ->15085
    6400             : /*15043*/           OPC_EmitMergeInputChains1_0,
    6401             : /*15044*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6402             : /*15047*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6403             : /*15050*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6404             : /*15053*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6405             : /*15056*/           OPC_EmitInteger, MVT::i1, 0, 
    6406             : /*15059*/           OPC_EmitInteger, MVT::i1, 0, 
    6407             : /*15062*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6408             : /*15065*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6409             : /*15068*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V2_V8), 0|OPFL_Chain,
    6410             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6411             :                     // Src: (intrinsic_w_chain:v2f32 450:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6412             :                     // Dst: (IMAGE_GATHER4_LZ_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6413             : /*15085*/         /*SwitchType*/ 42, MVT::v4f32,// ->15129
    6414             : /*15087*/           OPC_EmitMergeInputChains1_0,
    6415             : /*15088*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6416             : /*15091*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6417             : /*15094*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6418             : /*15097*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6419             : /*15100*/           OPC_EmitInteger, MVT::i1, 0, 
    6420             : /*15103*/           OPC_EmitInteger, MVT::i1, 0, 
    6421             : /*15106*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6422             : /*15109*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6423             : /*15112*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V4_V8), 0|OPFL_Chain,
    6424             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6425             :                     // Src: (intrinsic_w_chain:v4f32 450:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6426             :                     // Dst: (IMAGE_GATHER4_LZ_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6427             : /*15129*/         0, // EndSwitchType
    6428             : /*15130*/       /*Scope*/ 27|128,1/*155*/, /*->15287*/
    6429             : /*15132*/         OPC_CheckChild2Type, MVT::v16f32,
    6430             : /*15134*/         OPC_RecordChild3, // #2 = $rsrc
    6431             : /*15135*/         OPC_CheckChild3Type, MVT::v8i32,
    6432             : /*15137*/         OPC_RecordChild4, // #3 = $sampler
    6433             : /*15138*/         OPC_RecordChild5, // #4 = $dmask
    6434             : /*15139*/         OPC_RecordChild6, // #5 = $unorm
    6435             : /*15140*/         OPC_RecordChild7, // #6 = $glc
    6436             : /*15141*/         OPC_MoveChild, 8,
    6437             : /*15143*/         OPC_RecordNode, // #7 = $slc
    6438             : /*15144*/         OPC_MoveParent,
    6439             : /*15145*/         OPC_MoveChild, 9,
    6440             : /*15147*/         OPC_RecordNode, // #8 = $lwe
    6441             : /*15148*/         OPC_MoveParent,
    6442             : /*15149*/         OPC_MoveChild, 10,
    6443             : /*15151*/         OPC_RecordNode, // #9 = $da
    6444             : /*15152*/         OPC_MoveParent,
    6445             : /*15153*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->15198
    6446             : /*15156*/           OPC_EmitMergeInputChains1_0,
    6447             : /*15157*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6448             : /*15160*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6449             : /*15163*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6450             : /*15166*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6451             : /*15169*/           OPC_EmitInteger, MVT::i1, 0, 
    6452             : /*15172*/           OPC_EmitInteger, MVT::i1, 0, 
    6453             : /*15175*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6454             : /*15178*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6455             : /*15181*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V1_V16), 0|OPFL_Chain,
    6456             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6457             :                     // Src: (intrinsic_w_chain:f32 450:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6458             :                     // Dst: (IMAGE_GATHER4_LZ_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6459             : /*15198*/         /*SwitchType*/ 42, MVT::v2f32,// ->15242
    6460             : /*15200*/           OPC_EmitMergeInputChains1_0,
    6461             : /*15201*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6462             : /*15204*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6463             : /*15207*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6464             : /*15210*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6465             : /*15213*/           OPC_EmitInteger, MVT::i1, 0, 
    6466             : /*15216*/           OPC_EmitInteger, MVT::i1, 0, 
    6467             : /*15219*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6468             : /*15222*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6469             : /*15225*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V2_V16), 0|OPFL_Chain,
    6470             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6471             :                     // Src: (intrinsic_w_chain:v2f32 450:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6472             :                     // Dst: (IMAGE_GATHER4_LZ_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6473             : /*15242*/         /*SwitchType*/ 42, MVT::v4f32,// ->15286
    6474             : /*15244*/           OPC_EmitMergeInputChains1_0,
    6475             : /*15245*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6476             : /*15248*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6477             : /*15251*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6478             : /*15254*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6479             : /*15257*/           OPC_EmitInteger, MVT::i1, 0, 
    6480             : /*15260*/           OPC_EmitInteger, MVT::i1, 0, 
    6481             : /*15263*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6482             : /*15266*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6483             : /*15269*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V4_V16), 0|OPFL_Chain,
    6484             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6485             :                     // Src: (intrinsic_w_chain:v4f32 450:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6486             :                     // Dst: (IMAGE_GATHER4_LZ_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6487             : /*15286*/         0, // EndSwitchType
    6488             : /*15287*/       0, /*End of Scope*/
    6489             : /*15288*/     /*Scope*/ 23|128,6/*791*/, /*->16081*/
    6490             : /*15290*/       OPC_CheckChild1Integer, 50|128,3/*434*/, 
    6491             : /*15293*/       OPC_RecordChild2, // #1 = $addr
    6492             : /*15294*/       OPC_Scope, 27|128,1/*155*/, /*->15452*/ // 5 children in Scope
    6493             : /*15297*/         OPC_CheckChild2Type, MVT::f32,
    6494             : /*15299*/         OPC_RecordChild3, // #2 = $rsrc
    6495             : /*15300*/         OPC_CheckChild3Type, MVT::v8i32,
    6496             : /*15302*/         OPC_RecordChild4, // #3 = $sampler
    6497             : /*15303*/         OPC_RecordChild5, // #4 = $dmask
    6498             : /*15304*/         OPC_RecordChild6, // #5 = $unorm
    6499             : /*15305*/         OPC_RecordChild7, // #6 = $glc
    6500             : /*15306*/         OPC_MoveChild, 8,
    6501             : /*15308*/         OPC_RecordNode, // #7 = $slc
    6502             : /*15309*/         OPC_MoveParent,
    6503             : /*15310*/         OPC_MoveChild, 9,
    6504             : /*15312*/         OPC_RecordNode, // #8 = $lwe
    6505             : /*15313*/         OPC_MoveParent,
    6506             : /*15314*/         OPC_MoveChild, 10,
    6507             : /*15316*/         OPC_RecordNode, // #9 = $da
    6508             : /*15317*/         OPC_MoveParent,
    6509             : /*15318*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->15363
    6510             : /*15321*/           OPC_EmitMergeInputChains1_0,
    6511             : /*15322*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6512             : /*15325*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6513             : /*15328*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6514             : /*15331*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6515             : /*15334*/           OPC_EmitInteger, MVT::i1, 0, 
    6516             : /*15337*/           OPC_EmitInteger, MVT::i1, 0, 
    6517             : /*15340*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6518             : /*15343*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6519             : /*15346*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V1_V1), 0|OPFL_Chain,
    6520             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6521             :                     // Src: (intrinsic_w_chain:f32 434:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6522             :                     // Dst: (IMAGE_GATHER4_C_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6523             : /*15363*/         /*SwitchType*/ 42, MVT::v2f32,// ->15407
    6524             : /*15365*/           OPC_EmitMergeInputChains1_0,
    6525             : /*15366*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6526             : /*15369*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6527             : /*15372*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6528             : /*15375*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6529             : /*15378*/           OPC_EmitInteger, MVT::i1, 0, 
    6530             : /*15381*/           OPC_EmitInteger, MVT::i1, 0, 
    6531             : /*15384*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6532             : /*15387*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6533             : /*15390*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V2_V1), 0|OPFL_Chain,
    6534             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6535             :                     // Src: (intrinsic_w_chain:v2f32 434:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6536             :                     // Dst: (IMAGE_GATHER4_C_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6537             : /*15407*/         /*SwitchType*/ 42, MVT::v4f32,// ->15451
    6538             : /*15409*/           OPC_EmitMergeInputChains1_0,
    6539             : /*15410*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6540             : /*15413*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6541             : /*15416*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6542             : /*15419*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6543             : /*15422*/           OPC_EmitInteger, MVT::i1, 0, 
    6544             : /*15425*/           OPC_EmitInteger, MVT::i1, 0, 
    6545             : /*15428*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6546             : /*15431*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6547             : /*15434*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V4_V1), 0|OPFL_Chain,
    6548             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6549             :                     // Src: (intrinsic_w_chain:v4f32 434:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6550             :                     // Dst: (IMAGE_GATHER4_C_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6551             : /*15451*/         0, // EndSwitchType
    6552             : /*15452*/       /*Scope*/ 27|128,1/*155*/, /*->15609*/
    6553             : /*15454*/         OPC_CheckChild2Type, MVT::v2f32,
    6554             : /*15456*/         OPC_RecordChild3, // #2 = $rsrc
    6555             : /*15457*/         OPC_CheckChild3Type, MVT::v8i32,
    6556             : /*15459*/         OPC_RecordChild4, // #3 = $sampler
    6557             : /*15460*/         OPC_RecordChild5, // #4 = $dmask
    6558             : /*15461*/         OPC_RecordChild6, // #5 = $unorm
    6559             : /*15462*/         OPC_RecordChild7, // #6 = $glc
    6560             : /*15463*/         OPC_MoveChild, 8,
    6561             : /*15465*/         OPC_RecordNode, // #7 = $slc
    6562             : /*15466*/         OPC_MoveParent,
    6563             : /*15467*/         OPC_MoveChild, 9,
    6564             : /*15469*/         OPC_RecordNode, // #8 = $lwe
    6565             : /*15470*/         OPC_MoveParent,
    6566             : /*15471*/         OPC_MoveChild, 10,
    6567             : /*15473*/         OPC_RecordNode, // #9 = $da
    6568             : /*15474*/         OPC_MoveParent,
    6569             : /*15475*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->15520
    6570             : /*15478*/           OPC_EmitMergeInputChains1_0,
    6571             : /*15479*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6572             : /*15482*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6573             : /*15485*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6574             : /*15488*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6575             : /*15491*/           OPC_EmitInteger, MVT::i1, 0, 
    6576             : /*15494*/           OPC_EmitInteger, MVT::i1, 0, 
    6577             : /*15497*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6578             : /*15500*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6579             : /*15503*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V1_V2), 0|OPFL_Chain,
    6580             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6581             :                     // Src: (intrinsic_w_chain:f32 434:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6582             :                     // Dst: (IMAGE_GATHER4_C_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6583             : /*15520*/         /*SwitchType*/ 42, MVT::v2f32,// ->15564
    6584             : /*15522*/           OPC_EmitMergeInputChains1_0,
    6585             : /*15523*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6586             : /*15526*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6587             : /*15529*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6588             : /*15532*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6589             : /*15535*/           OPC_EmitInteger, MVT::i1, 0, 
    6590             : /*15538*/           OPC_EmitInteger, MVT::i1, 0, 
    6591             : /*15541*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6592             : /*15544*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6593             : /*15547*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V2_V2), 0|OPFL_Chain,
    6594             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6595             :                     // Src: (intrinsic_w_chain:v2f32 434:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6596             :                     // Dst: (IMAGE_GATHER4_C_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6597             : /*15564*/         /*SwitchType*/ 42, MVT::v4f32,// ->15608
    6598             : /*15566*/           OPC_EmitMergeInputChains1_0,
    6599             : /*15567*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6600             : /*15570*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6601             : /*15573*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6602             : /*15576*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6603             : /*15579*/           OPC_EmitInteger, MVT::i1, 0, 
    6604             : /*15582*/           OPC_EmitInteger, MVT::i1, 0, 
    6605             : /*15585*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6606             : /*15588*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6607             : /*15591*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V4_V2), 0|OPFL_Chain,
    6608             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6609             :                     // Src: (intrinsic_w_chain:v4f32 434:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6610             :                     // Dst: (IMAGE_GATHER4_C_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6611             : /*15608*/         0, // EndSwitchType
    6612             : /*15609*/       /*Scope*/ 27|128,1/*155*/, /*->15766*/
    6613             : /*15611*/         OPC_CheckChild2Type, MVT::v4f32,
    6614             : /*15613*/         OPC_RecordChild3, // #2 = $rsrc
    6615             : /*15614*/         OPC_CheckChild3Type, MVT::v8i32,
    6616             : /*15616*/         OPC_RecordChild4, // #3 = $sampler
    6617             : /*15617*/         OPC_RecordChild5, // #4 = $dmask
    6618             : /*15618*/         OPC_RecordChild6, // #5 = $unorm
    6619             : /*15619*/         OPC_RecordChild7, // #6 = $glc
    6620             : /*15620*/         OPC_MoveChild, 8,
    6621             : /*15622*/         OPC_RecordNode, // #7 = $slc
    6622             : /*15623*/         OPC_MoveParent,
    6623             : /*15624*/         OPC_MoveChild, 9,
    6624             : /*15626*/         OPC_RecordNode, // #8 = $lwe
    6625             : /*15627*/         OPC_MoveParent,
    6626             : /*15628*/         OPC_MoveChild, 10,
    6627             : /*15630*/         OPC_RecordNode, // #9 = $da
    6628             : /*15631*/         OPC_MoveParent,
    6629             : /*15632*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->15677
    6630             : /*15635*/           OPC_EmitMergeInputChains1_0,
    6631             : /*15636*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6632             : /*15639*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6633             : /*15642*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6634             : /*15645*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6635             : /*15648*/           OPC_EmitInteger, MVT::i1, 0, 
    6636             : /*15651*/           OPC_EmitInteger, MVT::i1, 0, 
    6637             : /*15654*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6638             : /*15657*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6639             : /*15660*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V1_V4), 0|OPFL_Chain,
    6640             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6641             :                     // Src: (intrinsic_w_chain:f32 434:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6642             :                     // Dst: (IMAGE_GATHER4_C_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6643             : /*15677*/         /*SwitchType*/ 42, MVT::v2f32,// ->15721
    6644             : /*15679*/           OPC_EmitMergeInputChains1_0,
    6645             : /*15680*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6646             : /*15683*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6647             : /*15686*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6648             : /*15689*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6649             : /*15692*/           OPC_EmitInteger, MVT::i1, 0, 
    6650             : /*15695*/           OPC_EmitInteger, MVT::i1, 0, 
    6651             : /*15698*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6652             : /*15701*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6653             : /*15704*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V2_V4), 0|OPFL_Chain,
    6654             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6655             :                     // Src: (intrinsic_w_chain:v2f32 434:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6656             :                     // Dst: (IMAGE_GATHER4_C_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6657             : /*15721*/         /*SwitchType*/ 42, MVT::v4f32,// ->15765
    6658             : /*15723*/           OPC_EmitMergeInputChains1_0,
    6659             : /*15724*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6660             : /*15727*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6661             : /*15730*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6662             : /*15733*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6663             : /*15736*/           OPC_EmitInteger, MVT::i1, 0, 
    6664             : /*15739*/           OPC_EmitInteger, MVT::i1, 0, 
    6665             : /*15742*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6666             : /*15745*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6667             : /*15748*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V4_V4), 0|OPFL_Chain,
    6668             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6669             :                     // Src: (intrinsic_w_chain:v4f32 434:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6670             :                     // Dst: (IMAGE_GATHER4_C_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6671             : /*15765*/         0, // EndSwitchType
    6672             : /*15766*/       /*Scope*/ 27|128,1/*155*/, /*->15923*/
    6673             : /*15768*/         OPC_CheckChild2Type, MVT::v8f32,
    6674             : /*15770*/         OPC_RecordChild3, // #2 = $rsrc
    6675             : /*15771*/         OPC_CheckChild3Type, MVT::v8i32,
    6676             : /*15773*/         OPC_RecordChild4, // #3 = $sampler
    6677             : /*15774*/         OPC_RecordChild5, // #4 = $dmask
    6678             : /*15775*/         OPC_RecordChild6, // #5 = $unorm
    6679             : /*15776*/         OPC_RecordChild7, // #6 = $glc
    6680             : /*15777*/         OPC_MoveChild, 8,
    6681             : /*15779*/         OPC_RecordNode, // #7 = $slc
    6682             : /*15780*/         OPC_MoveParent,
    6683             : /*15781*/         OPC_MoveChild, 9,
    6684             : /*15783*/         OPC_RecordNode, // #8 = $lwe
    6685             : /*15784*/         OPC_MoveParent,
    6686             : /*15785*/         OPC_MoveChild, 10,
    6687             : /*15787*/         OPC_RecordNode, // #9 = $da
    6688             : /*15788*/         OPC_MoveParent,
    6689             : /*15789*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->15834
    6690             : /*15792*/           OPC_EmitMergeInputChains1_0,
    6691             : /*15793*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6692             : /*15796*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6693             : /*15799*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6694             : /*15802*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6695             : /*15805*/           OPC_EmitInteger, MVT::i1, 0, 
    6696             : /*15808*/           OPC_EmitInteger, MVT::i1, 0, 
    6697             : /*15811*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6698             : /*15814*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6699             : /*15817*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V1_V8), 0|OPFL_Chain,
    6700             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6701             :                     // Src: (intrinsic_w_chain:f32 434:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6702             :                     // Dst: (IMAGE_GATHER4_C_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6703             : /*15834*/         /*SwitchType*/ 42, MVT::v2f32,// ->15878
    6704             : /*15836*/           OPC_EmitMergeInputChains1_0,
    6705             : /*15837*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6706             : /*15840*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6707             : /*15843*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6708             : /*15846*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6709             : /*15849*/           OPC_EmitInteger, MVT::i1, 0, 
    6710             : /*15852*/           OPC_EmitInteger, MVT::i1, 0, 
    6711             : /*15855*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6712             : /*15858*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6713             : /*15861*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V2_V8), 0|OPFL_Chain,
    6714             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6715             :                     // Src: (intrinsic_w_chain:v2f32 434:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6716             :                     // Dst: (IMAGE_GATHER4_C_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6717             : /*15878*/         /*SwitchType*/ 42, MVT::v4f32,// ->15922
    6718             : /*15880*/           OPC_EmitMergeInputChains1_0,
    6719             : /*15881*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6720             : /*15884*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6721             : /*15887*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6722             : /*15890*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6723             : /*15893*/           OPC_EmitInteger, MVT::i1, 0, 
    6724             : /*15896*/           OPC_EmitInteger, MVT::i1, 0, 
    6725             : /*15899*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6726             : /*15902*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6727             : /*15905*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V4_V8), 0|OPFL_Chain,
    6728             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6729             :                     // Src: (intrinsic_w_chain:v4f32 434:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6730             :                     // Dst: (IMAGE_GATHER4_C_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6731             : /*15922*/         0, // EndSwitchType
    6732             : /*15923*/       /*Scope*/ 27|128,1/*155*/, /*->16080*/
    6733             : /*15925*/         OPC_CheckChild2Type, MVT::v16f32,
    6734             : /*15927*/         OPC_RecordChild3, // #2 = $rsrc
    6735             : /*15928*/         OPC_CheckChild3Type, MVT::v8i32,
    6736             : /*15930*/         OPC_RecordChild4, // #3 = $sampler
    6737             : /*15931*/         OPC_RecordChild5, // #4 = $dmask
    6738             : /*15932*/         OPC_RecordChild6, // #5 = $unorm
    6739             : /*15933*/         OPC_RecordChild7, // #6 = $glc
    6740             : /*15934*/         OPC_MoveChild, 8,
    6741             : /*15936*/         OPC_RecordNode, // #7 = $slc
    6742             : /*15937*/         OPC_MoveParent,
    6743             : /*15938*/         OPC_MoveChild, 9,
    6744             : /*15940*/         OPC_RecordNode, // #8 = $lwe
    6745             : /*15941*/         OPC_MoveParent,
    6746             : /*15942*/         OPC_MoveChild, 10,
    6747             : /*15944*/         OPC_RecordNode, // #9 = $da
    6748             : /*15945*/         OPC_MoveParent,
    6749             : /*15946*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->15991
    6750             : /*15949*/           OPC_EmitMergeInputChains1_0,
    6751             : /*15950*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6752             : /*15953*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6753             : /*15956*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6754             : /*15959*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6755             : /*15962*/           OPC_EmitInteger, MVT::i1, 0, 
    6756             : /*15965*/           OPC_EmitInteger, MVT::i1, 0, 
    6757             : /*15968*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6758             : /*15971*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6759             : /*15974*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V1_V16), 0|OPFL_Chain,
    6760             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6761             :                     // Src: (intrinsic_w_chain:f32 434:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6762             :                     // Dst: (IMAGE_GATHER4_C_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6763             : /*15991*/         /*SwitchType*/ 42, MVT::v2f32,// ->16035
    6764             : /*15993*/           OPC_EmitMergeInputChains1_0,
    6765             : /*15994*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6766             : /*15997*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6767             : /*16000*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6768             : /*16003*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6769             : /*16006*/           OPC_EmitInteger, MVT::i1, 0, 
    6770             : /*16009*/           OPC_EmitInteger, MVT::i1, 0, 
    6771             : /*16012*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6772             : /*16015*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6773             : /*16018*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V2_V16), 0|OPFL_Chain,
    6774             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6775             :                     // Src: (intrinsic_w_chain:v2f32 434:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6776             :                     // Dst: (IMAGE_GATHER4_C_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6777             : /*16035*/         /*SwitchType*/ 42, MVT::v4f32,// ->16079
    6778             : /*16037*/           OPC_EmitMergeInputChains1_0,
    6779             : /*16038*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6780             : /*16041*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6781             : /*16044*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6782             : /*16047*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6783             : /*16050*/           OPC_EmitInteger, MVT::i1, 0, 
    6784             : /*16053*/           OPC_EmitInteger, MVT::i1, 0, 
    6785             : /*16056*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6786             : /*16059*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6787             : /*16062*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V4_V16), 0|OPFL_Chain,
    6788             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6789             :                     // Src: (intrinsic_w_chain:v4f32 434:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6790             :                     // Dst: (IMAGE_GATHER4_C_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6791             : /*16079*/         0, // EndSwitchType
    6792             : /*16080*/       0, /*End of Scope*/
    6793             : /*16081*/     /*Scope*/ 23|128,6/*791*/, /*->16874*/
    6794             : /*16083*/       OPC_CheckChild1Integer, 55|128,3/*439*/, 
    6795             : /*16086*/       OPC_RecordChild2, // #1 = $addr
    6796             : /*16087*/       OPC_Scope, 27|128,1/*155*/, /*->16245*/ // 5 children in Scope
    6797             : /*16090*/         OPC_CheckChild2Type, MVT::f32,
    6798             : /*16092*/         OPC_RecordChild3, // #2 = $rsrc
    6799             : /*16093*/         OPC_CheckChild3Type, MVT::v8i32,
    6800             : /*16095*/         OPC_RecordChild4, // #3 = $sampler
    6801             : /*16096*/         OPC_RecordChild5, // #4 = $dmask
    6802             : /*16097*/         OPC_RecordChild6, // #5 = $unorm
    6803             : /*16098*/         OPC_RecordChild7, // #6 = $glc
    6804             : /*16099*/         OPC_MoveChild, 8,
    6805             : /*16101*/         OPC_RecordNode, // #7 = $slc
    6806             : /*16102*/         OPC_MoveParent,
    6807             : /*16103*/         OPC_MoveChild, 9,
    6808             : /*16105*/         OPC_RecordNode, // #8 = $lwe
    6809             : /*16106*/         OPC_MoveParent,
    6810             : /*16107*/         OPC_MoveChild, 10,
    6811             : /*16109*/         OPC_RecordNode, // #9 = $da
    6812             : /*16110*/         OPC_MoveParent,
    6813             : /*16111*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->16156
    6814             : /*16114*/           OPC_EmitMergeInputChains1_0,
    6815             : /*16115*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6816             : /*16118*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6817             : /*16121*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6818             : /*16124*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6819             : /*16127*/           OPC_EmitInteger, MVT::i1, 0, 
    6820             : /*16130*/           OPC_EmitInteger, MVT::i1, 0, 
    6821             : /*16133*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6822             : /*16136*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6823             : /*16139*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V1_V1), 0|OPFL_Chain,
    6824             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6825             :                     // Src: (intrinsic_w_chain:f32 439:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6826             :                     // Dst: (IMAGE_GATHER4_C_CL_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6827             : /*16156*/         /*SwitchType*/ 42, MVT::v2f32,// ->16200
    6828             : /*16158*/           OPC_EmitMergeInputChains1_0,
    6829             : /*16159*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6830             : /*16162*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6831             : /*16165*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6832             : /*16168*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6833             : /*16171*/           OPC_EmitInteger, MVT::i1, 0, 
    6834             : /*16174*/           OPC_EmitInteger, MVT::i1, 0, 
    6835             : /*16177*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6836             : /*16180*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6837             : /*16183*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V2_V1), 0|OPFL_Chain,
    6838             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6839             :                     // Src: (intrinsic_w_chain:v2f32 439:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6840             :                     // Dst: (IMAGE_GATHER4_C_CL_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6841             : /*16200*/         /*SwitchType*/ 42, MVT::v4f32,// ->16244
    6842             : /*16202*/           OPC_EmitMergeInputChains1_0,
    6843             : /*16203*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6844             : /*16206*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6845             : /*16209*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6846             : /*16212*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6847             : /*16215*/           OPC_EmitInteger, MVT::i1, 0, 
    6848             : /*16218*/           OPC_EmitInteger, MVT::i1, 0, 
    6849             : /*16221*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6850             : /*16224*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6851             : /*16227*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V4_V1), 0|OPFL_Chain,
    6852             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6853             :                     // Src: (intrinsic_w_chain:v4f32 439:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6854             :                     // Dst: (IMAGE_GATHER4_C_CL_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6855             : /*16244*/         0, // EndSwitchType
    6856             : /*16245*/       /*Scope*/ 27|128,1/*155*/, /*->16402*/
    6857             : /*16247*/         OPC_CheckChild2Type, MVT::v2f32,
    6858             : /*16249*/         OPC_RecordChild3, // #2 = $rsrc
    6859             : /*16250*/         OPC_CheckChild3Type, MVT::v8i32,
    6860             : /*16252*/         OPC_RecordChild4, // #3 = $sampler
    6861             : /*16253*/         OPC_RecordChild5, // #4 = $dmask
    6862             : /*16254*/         OPC_RecordChild6, // #5 = $unorm
    6863             : /*16255*/         OPC_RecordChild7, // #6 = $glc
    6864             : /*16256*/         OPC_MoveChild, 8,
    6865             : /*16258*/         OPC_RecordNode, // #7 = $slc
    6866             : /*16259*/         OPC_MoveParent,
    6867             : /*16260*/         OPC_MoveChild, 9,
    6868             : /*16262*/         OPC_RecordNode, // #8 = $lwe
    6869             : /*16263*/         OPC_MoveParent,
    6870             : /*16264*/         OPC_MoveChild, 10,
    6871             : /*16266*/         OPC_RecordNode, // #9 = $da
    6872             : /*16267*/         OPC_MoveParent,
    6873             : /*16268*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->16313
    6874             : /*16271*/           OPC_EmitMergeInputChains1_0,
    6875             : /*16272*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6876             : /*16275*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6877             : /*16278*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6878             : /*16281*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6879             : /*16284*/           OPC_EmitInteger, MVT::i1, 0, 
    6880             : /*16287*/           OPC_EmitInteger, MVT::i1, 0, 
    6881             : /*16290*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6882             : /*16293*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6883             : /*16296*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V1_V2), 0|OPFL_Chain,
    6884             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6885             :                     // Src: (intrinsic_w_chain:f32 439:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6886             :                     // Dst: (IMAGE_GATHER4_C_CL_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6887             : /*16313*/         /*SwitchType*/ 42, MVT::v2f32,// ->16357
    6888             : /*16315*/           OPC_EmitMergeInputChains1_0,
    6889             : /*16316*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6890             : /*16319*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6891             : /*16322*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6892             : /*16325*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6893             : /*16328*/           OPC_EmitInteger, MVT::i1, 0, 
    6894             : /*16331*/           OPC_EmitInteger, MVT::i1, 0, 
    6895             : /*16334*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6896             : /*16337*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6897             : /*16340*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V2_V2), 0|OPFL_Chain,
    6898             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6899             :                     // Src: (intrinsic_w_chain:v2f32 439:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6900             :                     // Dst: (IMAGE_GATHER4_C_CL_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6901             : /*16357*/         /*SwitchType*/ 42, MVT::v4f32,// ->16401
    6902             : /*16359*/           OPC_EmitMergeInputChains1_0,
    6903             : /*16360*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6904             : /*16363*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6905             : /*16366*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6906             : /*16369*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6907             : /*16372*/           OPC_EmitInteger, MVT::i1, 0, 
    6908             : /*16375*/           OPC_EmitInteger, MVT::i1, 0, 
    6909             : /*16378*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6910             : /*16381*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6911             : /*16384*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V4_V2), 0|OPFL_Chain,
    6912             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6913             :                     // Src: (intrinsic_w_chain:v4f32 439:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6914             :                     // Dst: (IMAGE_GATHER4_C_CL_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6915             : /*16401*/         0, // EndSwitchType
    6916             : /*16402*/       /*Scope*/ 27|128,1/*155*/, /*->16559*/
    6917             : /*16404*/         OPC_CheckChild2Type, MVT::v4f32,
    6918             : /*16406*/         OPC_RecordChild3, // #2 = $rsrc
    6919             : /*16407*/         OPC_CheckChild3Type, MVT::v8i32,
    6920             : /*16409*/         OPC_RecordChild4, // #3 = $sampler
    6921             : /*16410*/         OPC_RecordChild5, // #4 = $dmask
    6922             : /*16411*/         OPC_RecordChild6, // #5 = $unorm
    6923             : /*16412*/         OPC_RecordChild7, // #6 = $glc
    6924             : /*16413*/         OPC_MoveChild, 8,
    6925             : /*16415*/         OPC_RecordNode, // #7 = $slc
    6926             : /*16416*/         OPC_MoveParent,
    6927             : /*16417*/         OPC_MoveChild, 9,
    6928             : /*16419*/         OPC_RecordNode, // #8 = $lwe
    6929             : /*16420*/         OPC_MoveParent,
    6930             : /*16421*/         OPC_MoveChild, 10,
    6931             : /*16423*/         OPC_RecordNode, // #9 = $da
    6932             : /*16424*/         OPC_MoveParent,
    6933             : /*16425*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->16470
    6934             : /*16428*/           OPC_EmitMergeInputChains1_0,
    6935             : /*16429*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6936             : /*16432*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6937             : /*16435*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6938             : /*16438*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6939             : /*16441*/           OPC_EmitInteger, MVT::i1, 0, 
    6940             : /*16444*/           OPC_EmitInteger, MVT::i1, 0, 
    6941             : /*16447*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6942             : /*16450*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6943             : /*16453*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V1_V4), 0|OPFL_Chain,
    6944             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6945             :                     // Src: (intrinsic_w_chain:f32 439:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6946             :                     // Dst: (IMAGE_GATHER4_C_CL_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6947             : /*16470*/         /*SwitchType*/ 42, MVT::v2f32,// ->16514
    6948             : /*16472*/           OPC_EmitMergeInputChains1_0,
    6949             : /*16473*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6950             : /*16476*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6951             : /*16479*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6952             : /*16482*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6953             : /*16485*/           OPC_EmitInteger, MVT::i1, 0, 
    6954             : /*16488*/           OPC_EmitInteger, MVT::i1, 0, 
    6955             : /*16491*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6956             : /*16494*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6957             : /*16497*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V2_V4), 0|OPFL_Chain,
    6958             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6959             :                     // Src: (intrinsic_w_chain:v2f32 439:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6960             :                     // Dst: (IMAGE_GATHER4_C_CL_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6961             : /*16514*/         /*SwitchType*/ 42, MVT::v4f32,// ->16558
    6962             : /*16516*/           OPC_EmitMergeInputChains1_0,
    6963             : /*16517*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6964             : /*16520*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6965             : /*16523*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6966             : /*16526*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6967             : /*16529*/           OPC_EmitInteger, MVT::i1, 0, 
    6968             : /*16532*/           OPC_EmitInteger, MVT::i1, 0, 
    6969             : /*16535*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    6970             : /*16538*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    6971             : /*16541*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V4_V4), 0|OPFL_Chain,
    6972             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    6973             :                     // Src: (intrinsic_w_chain:v4f32 439:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    6974             :                     // Dst: (IMAGE_GATHER4_C_CL_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    6975             : /*16558*/         0, // EndSwitchType
    6976             : /*16559*/       /*Scope*/ 27|128,1/*155*/, /*->16716*/
    6977             : /*16561*/         OPC_CheckChild2Type, MVT::v8f32,
    6978             : /*16563*/         OPC_RecordChild3, // #2 = $rsrc
    6979             : /*16564*/         OPC_CheckChild3Type, MVT::v8i32,
    6980             : /*16566*/         OPC_RecordChild4, // #3 = $sampler
    6981             : /*16567*/         OPC_RecordChild5, // #4 = $dmask
    6982             : /*16568*/         OPC_RecordChild6, // #5 = $unorm
    6983             : /*16569*/         OPC_RecordChild7, // #6 = $glc
    6984             : /*16570*/         OPC_MoveChild, 8,
    6985             : /*16572*/         OPC_RecordNode, // #7 = $slc
    6986             : /*16573*/         OPC_MoveParent,
    6987             : /*16574*/         OPC_MoveChild, 9,
    6988             : /*16576*/         OPC_RecordNode, // #8 = $lwe
    6989             : /*16577*/         OPC_MoveParent,
    6990             : /*16578*/         OPC_MoveChild, 10,
    6991             : /*16580*/         OPC_RecordNode, // #9 = $da
    6992             : /*16581*/         OPC_MoveParent,
    6993             : /*16582*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->16627
    6994             : /*16585*/           OPC_EmitMergeInputChains1_0,
    6995             : /*16586*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    6996             : /*16589*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    6997             : /*16592*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    6998             : /*16595*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    6999             : /*16598*/           OPC_EmitInteger, MVT::i1, 0, 
    7000             : /*16601*/           OPC_EmitInteger, MVT::i1, 0, 
    7001             : /*16604*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7002             : /*16607*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7003             : /*16610*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V1_V8), 0|OPFL_Chain,
    7004             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7005             :                     // Src: (intrinsic_w_chain:f32 439:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7006             :                     // Dst: (IMAGE_GATHER4_C_CL_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7007             : /*16627*/         /*SwitchType*/ 42, MVT::v2f32,// ->16671
    7008             : /*16629*/           OPC_EmitMergeInputChains1_0,
    7009             : /*16630*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7010             : /*16633*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7011             : /*16636*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7012             : /*16639*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7013             : /*16642*/           OPC_EmitInteger, MVT::i1, 0, 
    7014             : /*16645*/           OPC_EmitInteger, MVT::i1, 0, 
    7015             : /*16648*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7016             : /*16651*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7017             : /*16654*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V2_V8), 0|OPFL_Chain,
    7018             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7019             :                     // Src: (intrinsic_w_chain:v2f32 439:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7020             :                     // Dst: (IMAGE_GATHER4_C_CL_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7021             : /*16671*/         /*SwitchType*/ 42, MVT::v4f32,// ->16715
    7022             : /*16673*/           OPC_EmitMergeInputChains1_0,
    7023             : /*16674*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7024             : /*16677*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7025             : /*16680*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7026             : /*16683*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7027             : /*16686*/           OPC_EmitInteger, MVT::i1, 0, 
    7028             : /*16689*/           OPC_EmitInteger, MVT::i1, 0, 
    7029             : /*16692*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7030             : /*16695*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7031             : /*16698*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V4_V8), 0|OPFL_Chain,
    7032             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7033             :                     // Src: (intrinsic_w_chain:v4f32 439:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7034             :                     // Dst: (IMAGE_GATHER4_C_CL_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7035             : /*16715*/         0, // EndSwitchType
    7036             : /*16716*/       /*Scope*/ 27|128,1/*155*/, /*->16873*/
    7037             : /*16718*/         OPC_CheckChild2Type, MVT::v16f32,
    7038             : /*16720*/         OPC_RecordChild3, // #2 = $rsrc
    7039             : /*16721*/         OPC_CheckChild3Type, MVT::v8i32,
    7040             : /*16723*/         OPC_RecordChild4, // #3 = $sampler
    7041             : /*16724*/         OPC_RecordChild5, // #4 = $dmask
    7042             : /*16725*/         OPC_RecordChild6, // #5 = $unorm
    7043             : /*16726*/         OPC_RecordChild7, // #6 = $glc
    7044             : /*16727*/         OPC_MoveChild, 8,
    7045             : /*16729*/         OPC_RecordNode, // #7 = $slc
    7046             : /*16730*/         OPC_MoveParent,
    7047             : /*16731*/         OPC_MoveChild, 9,
    7048             : /*16733*/         OPC_RecordNode, // #8 = $lwe
    7049             : /*16734*/         OPC_MoveParent,
    7050             : /*16735*/         OPC_MoveChild, 10,
    7051             : /*16737*/         OPC_RecordNode, // #9 = $da
    7052             : /*16738*/         OPC_MoveParent,
    7053             : /*16739*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->16784
    7054             : /*16742*/           OPC_EmitMergeInputChains1_0,
    7055             : /*16743*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7056             : /*16746*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7057             : /*16749*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7058             : /*16752*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7059             : /*16755*/           OPC_EmitInteger, MVT::i1, 0, 
    7060             : /*16758*/           OPC_EmitInteger, MVT::i1, 0, 
    7061             : /*16761*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7062             : /*16764*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7063             : /*16767*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V1_V16), 0|OPFL_Chain,
    7064             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7065             :                     // Src: (intrinsic_w_chain:f32 439:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7066             :                     // Dst: (IMAGE_GATHER4_C_CL_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7067             : /*16784*/         /*SwitchType*/ 42, MVT::v2f32,// ->16828
    7068             : /*16786*/           OPC_EmitMergeInputChains1_0,
    7069             : /*16787*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7070             : /*16790*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7071             : /*16793*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7072             : /*16796*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7073             : /*16799*/           OPC_EmitInteger, MVT::i1, 0, 
    7074             : /*16802*/           OPC_EmitInteger, MVT::i1, 0, 
    7075             : /*16805*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7076             : /*16808*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7077             : /*16811*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V2_V16), 0|OPFL_Chain,
    7078             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7079             :                     // Src: (intrinsic_w_chain:v2f32 439:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7080             :                     // Dst: (IMAGE_GATHER4_C_CL_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7081             : /*16828*/         /*SwitchType*/ 42, MVT::v4f32,// ->16872
    7082             : /*16830*/           OPC_EmitMergeInputChains1_0,
    7083             : /*16831*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7084             : /*16834*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7085             : /*16837*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7086             : /*16840*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7087             : /*16843*/           OPC_EmitInteger, MVT::i1, 0, 
    7088             : /*16846*/           OPC_EmitInteger, MVT::i1, 0, 
    7089             : /*16849*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7090             : /*16852*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7091             : /*16855*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V4_V16), 0|OPFL_Chain,
    7092             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7093             :                     // Src: (intrinsic_w_chain:v4f32 439:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7094             :                     // Dst: (IMAGE_GATHER4_C_CL_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7095             : /*16872*/         0, // EndSwitchType
    7096             : /*16873*/       0, /*End of Scope*/
    7097             : /*16874*/     /*Scope*/ 23|128,6/*791*/, /*->17667*/
    7098             : /*16876*/       OPC_CheckChild1Integer, 57|128,3/*441*/, 
    7099             : /*16879*/       OPC_RecordChild2, // #1 = $addr
    7100             : /*16880*/       OPC_Scope, 27|128,1/*155*/, /*->17038*/ // 5 children in Scope
    7101             : /*16883*/         OPC_CheckChild2Type, MVT::f32,
    7102             : /*16885*/         OPC_RecordChild3, // #2 = $rsrc
    7103             : /*16886*/         OPC_CheckChild3Type, MVT::v8i32,
    7104             : /*16888*/         OPC_RecordChild4, // #3 = $sampler
    7105             : /*16889*/         OPC_RecordChild5, // #4 = $dmask
    7106             : /*16890*/         OPC_RecordChild6, // #5 = $unorm
    7107             : /*16891*/         OPC_RecordChild7, // #6 = $glc
    7108             : /*16892*/         OPC_MoveChild, 8,
    7109             : /*16894*/         OPC_RecordNode, // #7 = $slc
    7110             : /*16895*/         OPC_MoveParent,
    7111             : /*16896*/         OPC_MoveChild, 9,
    7112             : /*16898*/         OPC_RecordNode, // #8 = $lwe
    7113             : /*16899*/         OPC_MoveParent,
    7114             : /*16900*/         OPC_MoveChild, 10,
    7115             : /*16902*/         OPC_RecordNode, // #9 = $da
    7116             : /*16903*/         OPC_MoveParent,
    7117             : /*16904*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->16949
    7118             : /*16907*/           OPC_EmitMergeInputChains1_0,
    7119             : /*16908*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7120             : /*16911*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7121             : /*16914*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7122             : /*16917*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7123             : /*16920*/           OPC_EmitInteger, MVT::i1, 0, 
    7124             : /*16923*/           OPC_EmitInteger, MVT::i1, 0, 
    7125             : /*16926*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7126             : /*16929*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7127             : /*16932*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V1_V1), 0|OPFL_Chain,
    7128             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7129             :                     // Src: (intrinsic_w_chain:f32 441:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7130             :                     // Dst: (IMAGE_GATHER4_C_L_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7131             : /*16949*/         /*SwitchType*/ 42, MVT::v2f32,// ->16993
    7132             : /*16951*/           OPC_EmitMergeInputChains1_0,
    7133             : /*16952*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7134             : /*16955*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7135             : /*16958*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7136             : /*16961*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7137             : /*16964*/           OPC_EmitInteger, MVT::i1, 0, 
    7138             : /*16967*/           OPC_EmitInteger, MVT::i1, 0, 
    7139             : /*16970*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7140             : /*16973*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7141             : /*16976*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V2_V1), 0|OPFL_Chain,
    7142             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7143             :                     // Src: (intrinsic_w_chain:v2f32 441:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7144             :                     // Dst: (IMAGE_GATHER4_C_L_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7145             : /*16993*/         /*SwitchType*/ 42, MVT::v4f32,// ->17037
    7146             : /*16995*/           OPC_EmitMergeInputChains1_0,
    7147             : /*16996*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7148             : /*16999*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7149             : /*17002*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7150             : /*17005*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7151             : /*17008*/           OPC_EmitInteger, MVT::i1, 0, 
    7152             : /*17011*/           OPC_EmitInteger, MVT::i1, 0, 
    7153             : /*17014*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7154             : /*17017*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7155             : /*17020*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V4_V1), 0|OPFL_Chain,
    7156             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7157             :                     // Src: (intrinsic_w_chain:v4f32 441:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7158             :                     // Dst: (IMAGE_GATHER4_C_L_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7159             : /*17037*/         0, // EndSwitchType
    7160             : /*17038*/       /*Scope*/ 27|128,1/*155*/, /*->17195*/
    7161             : /*17040*/         OPC_CheckChild2Type, MVT::v2f32,
    7162             : /*17042*/         OPC_RecordChild3, // #2 = $rsrc
    7163             : /*17043*/         OPC_CheckChild3Type, MVT::v8i32,
    7164             : /*17045*/         OPC_RecordChild4, // #3 = $sampler
    7165             : /*17046*/         OPC_RecordChild5, // #4 = $dmask
    7166             : /*17047*/         OPC_RecordChild6, // #5 = $unorm
    7167             : /*17048*/         OPC_RecordChild7, // #6 = $glc
    7168             : /*17049*/         OPC_MoveChild, 8,
    7169             : /*17051*/         OPC_RecordNode, // #7 = $slc
    7170             : /*17052*/         OPC_MoveParent,
    7171             : /*17053*/         OPC_MoveChild, 9,
    7172             : /*17055*/         OPC_RecordNode, // #8 = $lwe
    7173             : /*17056*/         OPC_MoveParent,
    7174             : /*17057*/         OPC_MoveChild, 10,
    7175             : /*17059*/         OPC_RecordNode, // #9 = $da
    7176             : /*17060*/         OPC_MoveParent,
    7177             : /*17061*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->17106
    7178             : /*17064*/           OPC_EmitMergeInputChains1_0,
    7179             : /*17065*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7180             : /*17068*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7181             : /*17071*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7182             : /*17074*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7183             : /*17077*/           OPC_EmitInteger, MVT::i1, 0, 
    7184             : /*17080*/           OPC_EmitInteger, MVT::i1, 0, 
    7185             : /*17083*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7186             : /*17086*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7187             : /*17089*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V1_V2), 0|OPFL_Chain,
    7188             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7189             :                     // Src: (intrinsic_w_chain:f32 441:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7190             :                     // Dst: (IMAGE_GATHER4_C_L_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7191             : /*17106*/         /*SwitchType*/ 42, MVT::v2f32,// ->17150
    7192             : /*17108*/           OPC_EmitMergeInputChains1_0,
    7193             : /*17109*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7194             : /*17112*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7195             : /*17115*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7196             : /*17118*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7197             : /*17121*/           OPC_EmitInteger, MVT::i1, 0, 
    7198             : /*17124*/           OPC_EmitInteger, MVT::i1, 0, 
    7199             : /*17127*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7200             : /*17130*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7201             : /*17133*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V2_V2), 0|OPFL_Chain,
    7202             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7203             :                     // Src: (intrinsic_w_chain:v2f32 441:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7204             :                     // Dst: (IMAGE_GATHER4_C_L_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7205             : /*17150*/         /*SwitchType*/ 42, MVT::v4f32,// ->17194
    7206             : /*17152*/           OPC_EmitMergeInputChains1_0,
    7207             : /*17153*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7208             : /*17156*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7209             : /*17159*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7210             : /*17162*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7211             : /*17165*/           OPC_EmitInteger, MVT::i1, 0, 
    7212             : /*17168*/           OPC_EmitInteger, MVT::i1, 0, 
    7213             : /*17171*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7214             : /*17174*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7215             : /*17177*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V4_V2), 0|OPFL_Chain,
    7216             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7217             :                     // Src: (intrinsic_w_chain:v4f32 441:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7218             :                     // Dst: (IMAGE_GATHER4_C_L_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7219             : /*17194*/         0, // EndSwitchType
    7220             : /*17195*/       /*Scope*/ 27|128,1/*155*/, /*->17352*/
    7221             : /*17197*/         OPC_CheckChild2Type, MVT::v4f32,
    7222             : /*17199*/         OPC_RecordChild3, // #2 = $rsrc
    7223             : /*17200*/         OPC_CheckChild3Type, MVT::v8i32,
    7224             : /*17202*/         OPC_RecordChild4, // #3 = $sampler
    7225             : /*17203*/         OPC_RecordChild5, // #4 = $dmask
    7226             : /*17204*/         OPC_RecordChild6, // #5 = $unorm
    7227             : /*17205*/         OPC_RecordChild7, // #6 = $glc
    7228             : /*17206*/         OPC_MoveChild, 8,
    7229             : /*17208*/         OPC_RecordNode, // #7 = $slc
    7230             : /*17209*/         OPC_MoveParent,
    7231             : /*17210*/         OPC_MoveChild, 9,
    7232             : /*17212*/         OPC_RecordNode, // #8 = $lwe
    7233             : /*17213*/         OPC_MoveParent,
    7234             : /*17214*/         OPC_MoveChild, 10,
    7235             : /*17216*/         OPC_RecordNode, // #9 = $da
    7236             : /*17217*/         OPC_MoveParent,
    7237             : /*17218*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->17263
    7238             : /*17221*/           OPC_EmitMergeInputChains1_0,
    7239             : /*17222*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7240             : /*17225*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7241             : /*17228*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7242             : /*17231*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7243             : /*17234*/           OPC_EmitInteger, MVT::i1, 0, 
    7244             : /*17237*/           OPC_EmitInteger, MVT::i1, 0, 
    7245             : /*17240*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7246             : /*17243*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7247             : /*17246*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V1_V4), 0|OPFL_Chain,
    7248             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7249             :                     // Src: (intrinsic_w_chain:f32 441:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7250             :                     // Dst: (IMAGE_GATHER4_C_L_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7251             : /*17263*/         /*SwitchType*/ 42, MVT::v2f32,// ->17307
    7252             : /*17265*/           OPC_EmitMergeInputChains1_0,
    7253             : /*17266*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7254             : /*17269*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7255             : /*17272*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7256             : /*17275*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7257             : /*17278*/           OPC_EmitInteger, MVT::i1, 0, 
    7258             : /*17281*/           OPC_EmitInteger, MVT::i1, 0, 
    7259             : /*17284*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7260             : /*17287*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7261             : /*17290*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V2_V4), 0|OPFL_Chain,
    7262             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7263             :                     // Src: (intrinsic_w_chain:v2f32 441:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7264             :                     // Dst: (IMAGE_GATHER4_C_L_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7265             : /*17307*/         /*SwitchType*/ 42, MVT::v4f32,// ->17351
    7266             : /*17309*/           OPC_EmitMergeInputChains1_0,
    7267             : /*17310*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7268             : /*17313*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7269             : /*17316*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7270             : /*17319*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7271             : /*17322*/           OPC_EmitInteger, MVT::i1, 0, 
    7272             : /*17325*/           OPC_EmitInteger, MVT::i1, 0, 
    7273             : /*17328*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7274             : /*17331*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7275             : /*17334*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V4_V4), 0|OPFL_Chain,
    7276             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7277             :                     // Src: (intrinsic_w_chain:v4f32 441:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7278             :                     // Dst: (IMAGE_GATHER4_C_L_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7279             : /*17351*/         0, // EndSwitchType
    7280             : /*17352*/       /*Scope*/ 27|128,1/*155*/, /*->17509*/
    7281             : /*17354*/         OPC_CheckChild2Type, MVT::v8f32,
    7282             : /*17356*/         OPC_RecordChild3, // #2 = $rsrc
    7283             : /*17357*/         OPC_CheckChild3Type, MVT::v8i32,
    7284             : /*17359*/         OPC_RecordChild4, // #3 = $sampler
    7285             : /*17360*/         OPC_RecordChild5, // #4 = $dmask
    7286             : /*17361*/         OPC_RecordChild6, // #5 = $unorm
    7287             : /*17362*/         OPC_RecordChild7, // #6 = $glc
    7288             : /*17363*/         OPC_MoveChild, 8,
    7289             : /*17365*/         OPC_RecordNode, // #7 = $slc
    7290             : /*17366*/         OPC_MoveParent,
    7291             : /*17367*/         OPC_MoveChild, 9,
    7292             : /*17369*/         OPC_RecordNode, // #8 = $lwe
    7293             : /*17370*/         OPC_MoveParent,
    7294             : /*17371*/         OPC_MoveChild, 10,
    7295             : /*17373*/         OPC_RecordNode, // #9 = $da
    7296             : /*17374*/         OPC_MoveParent,
    7297             : /*17375*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->17420
    7298             : /*17378*/           OPC_EmitMergeInputChains1_0,
    7299             : /*17379*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7300             : /*17382*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7301             : /*17385*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7302             : /*17388*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7303             : /*17391*/           OPC_EmitInteger, MVT::i1, 0, 
    7304             : /*17394*/           OPC_EmitInteger, MVT::i1, 0, 
    7305             : /*17397*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7306             : /*17400*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7307             : /*17403*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V1_V8), 0|OPFL_Chain,
    7308             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7309             :                     // Src: (intrinsic_w_chain:f32 441:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7310             :                     // Dst: (IMAGE_GATHER4_C_L_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7311             : /*17420*/         /*SwitchType*/ 42, MVT::v2f32,// ->17464
    7312             : /*17422*/           OPC_EmitMergeInputChains1_0,
    7313             : /*17423*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7314             : /*17426*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7315             : /*17429*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7316             : /*17432*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7317             : /*17435*/           OPC_EmitInteger, MVT::i1, 0, 
    7318             : /*17438*/           OPC_EmitInteger, MVT::i1, 0, 
    7319             : /*17441*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7320             : /*17444*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7321             : /*17447*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V2_V8), 0|OPFL_Chain,
    7322             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7323             :                     // Src: (intrinsic_w_chain:v2f32 441:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7324             :                     // Dst: (IMAGE_GATHER4_C_L_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7325             : /*17464*/         /*SwitchType*/ 42, MVT::v4f32,// ->17508
    7326             : /*17466*/           OPC_EmitMergeInputChains1_0,
    7327             : /*17467*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7328             : /*17470*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7329             : /*17473*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7330             : /*17476*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7331             : /*17479*/           OPC_EmitInteger, MVT::i1, 0, 
    7332             : /*17482*/           OPC_EmitInteger, MVT::i1, 0, 
    7333             : /*17485*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7334             : /*17488*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7335             : /*17491*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V4_V8), 0|OPFL_Chain,
    7336             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7337             :                     // Src: (intrinsic_w_chain:v4f32 441:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7338             :                     // Dst: (IMAGE_GATHER4_C_L_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7339             : /*17508*/         0, // EndSwitchType
    7340             : /*17509*/       /*Scope*/ 27|128,1/*155*/, /*->17666*/
    7341             : /*17511*/         OPC_CheckChild2Type, MVT::v16f32,
    7342             : /*17513*/         OPC_RecordChild3, // #2 = $rsrc
    7343             : /*17514*/         OPC_CheckChild3Type, MVT::v8i32,
    7344             : /*17516*/         OPC_RecordChild4, // #3 = $sampler
    7345             : /*17517*/         OPC_RecordChild5, // #4 = $dmask
    7346             : /*17518*/         OPC_RecordChild6, // #5 = $unorm
    7347             : /*17519*/         OPC_RecordChild7, // #6 = $glc
    7348             : /*17520*/         OPC_MoveChild, 8,
    7349             : /*17522*/         OPC_RecordNode, // #7 = $slc
    7350             : /*17523*/         OPC_MoveParent,
    7351             : /*17524*/         OPC_MoveChild, 9,
    7352             : /*17526*/         OPC_RecordNode, // #8 = $lwe
    7353             : /*17527*/         OPC_MoveParent,
    7354             : /*17528*/         OPC_MoveChild, 10,
    7355             : /*17530*/         OPC_RecordNode, // #9 = $da
    7356             : /*17531*/         OPC_MoveParent,
    7357             : /*17532*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->17577
    7358             : /*17535*/           OPC_EmitMergeInputChains1_0,
    7359             : /*17536*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7360             : /*17539*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7361             : /*17542*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7362             : /*17545*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7363             : /*17548*/           OPC_EmitInteger, MVT::i1, 0, 
    7364             : /*17551*/           OPC_EmitInteger, MVT::i1, 0, 
    7365             : /*17554*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7366             : /*17557*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7367             : /*17560*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V1_V16), 0|OPFL_Chain,
    7368             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7369             :                     // Src: (intrinsic_w_chain:f32 441:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7370             :                     // Dst: (IMAGE_GATHER4_C_L_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7371             : /*17577*/         /*SwitchType*/ 42, MVT::v2f32,// ->17621
    7372             : /*17579*/           OPC_EmitMergeInputChains1_0,
    7373             : /*17580*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7374             : /*17583*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7375             : /*17586*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7376             : /*17589*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7377             : /*17592*/           OPC_EmitInteger, MVT::i1, 0, 
    7378             : /*17595*/           OPC_EmitInteger, MVT::i1, 0, 
    7379             : /*17598*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7380             : /*17601*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7381             : /*17604*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V2_V16), 0|OPFL_Chain,
    7382             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7383             :                     // Src: (intrinsic_w_chain:v2f32 441:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7384             :                     // Dst: (IMAGE_GATHER4_C_L_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7385             : /*17621*/         /*SwitchType*/ 42, MVT::v4f32,// ->17665
    7386             : /*17623*/           OPC_EmitMergeInputChains1_0,
    7387             : /*17624*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7388             : /*17627*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7389             : /*17630*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7390             : /*17633*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7391             : /*17636*/           OPC_EmitInteger, MVT::i1, 0, 
    7392             : /*17639*/           OPC_EmitInteger, MVT::i1, 0, 
    7393             : /*17642*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7394             : /*17645*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7395             : /*17648*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V4_V16), 0|OPFL_Chain,
    7396             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7397             :                     // Src: (intrinsic_w_chain:v4f32 441:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7398             :                     // Dst: (IMAGE_GATHER4_C_L_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7399             : /*17665*/         0, // EndSwitchType
    7400             : /*17666*/       0, /*End of Scope*/
    7401             : /*17667*/     /*Scope*/ 23|128,6/*791*/, /*->18460*/
    7402             : /*17669*/       OPC_CheckChild1Integer, 51|128,3/*435*/, 
    7403             : /*17672*/       OPC_RecordChild2, // #1 = $addr
    7404             : /*17673*/       OPC_Scope, 27|128,1/*155*/, /*->17831*/ // 5 children in Scope
    7405             : /*17676*/         OPC_CheckChild2Type, MVT::f32,
    7406             : /*17678*/         OPC_RecordChild3, // #2 = $rsrc
    7407             : /*17679*/         OPC_CheckChild3Type, MVT::v8i32,
    7408             : /*17681*/         OPC_RecordChild4, // #3 = $sampler
    7409             : /*17682*/         OPC_RecordChild5, // #4 = $dmask
    7410             : /*17683*/         OPC_RecordChild6, // #5 = $unorm
    7411             : /*17684*/         OPC_RecordChild7, // #6 = $glc
    7412             : /*17685*/         OPC_MoveChild, 8,
    7413             : /*17687*/         OPC_RecordNode, // #7 = $slc
    7414             : /*17688*/         OPC_MoveParent,
    7415             : /*17689*/         OPC_MoveChild, 9,
    7416             : /*17691*/         OPC_RecordNode, // #8 = $lwe
    7417             : /*17692*/         OPC_MoveParent,
    7418             : /*17693*/         OPC_MoveChild, 10,
    7419             : /*17695*/         OPC_RecordNode, // #9 = $da
    7420             : /*17696*/         OPC_MoveParent,
    7421             : /*17697*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->17742
    7422             : /*17700*/           OPC_EmitMergeInputChains1_0,
    7423             : /*17701*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7424             : /*17704*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7425             : /*17707*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7426             : /*17710*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7427             : /*17713*/           OPC_EmitInteger, MVT::i1, 0, 
    7428             : /*17716*/           OPC_EmitInteger, MVT::i1, 0, 
    7429             : /*17719*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7430             : /*17722*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7431             : /*17725*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V1_V1), 0|OPFL_Chain,
    7432             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7433             :                     // Src: (intrinsic_w_chain:f32 435:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7434             :                     // Dst: (IMAGE_GATHER4_C_B_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7435             : /*17742*/         /*SwitchType*/ 42, MVT::v2f32,// ->17786
    7436             : /*17744*/           OPC_EmitMergeInputChains1_0,
    7437             : /*17745*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7438             : /*17748*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7439             : /*17751*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7440             : /*17754*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7441             : /*17757*/           OPC_EmitInteger, MVT::i1, 0, 
    7442             : /*17760*/           OPC_EmitInteger, MVT::i1, 0, 
    7443             : /*17763*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7444             : /*17766*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7445             : /*17769*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V2_V1), 0|OPFL_Chain,
    7446             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7447             :                     // Src: (intrinsic_w_chain:v2f32 435:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7448             :                     // Dst: (IMAGE_GATHER4_C_B_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7449             : /*17786*/         /*SwitchType*/ 42, MVT::v4f32,// ->17830
    7450             : /*17788*/           OPC_EmitMergeInputChains1_0,
    7451             : /*17789*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7452             : /*17792*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7453             : /*17795*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7454             : /*17798*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7455             : /*17801*/           OPC_EmitInteger, MVT::i1, 0, 
    7456             : /*17804*/           OPC_EmitInteger, MVT::i1, 0, 
    7457             : /*17807*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7458             : /*17810*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7459             : /*17813*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V4_V1), 0|OPFL_Chain,
    7460             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7461             :                     // Src: (intrinsic_w_chain:v4f32 435:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7462             :                     // Dst: (IMAGE_GATHER4_C_B_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7463             : /*17830*/         0, // EndSwitchType
    7464             : /*17831*/       /*Scope*/ 27|128,1/*155*/, /*->17988*/
    7465             : /*17833*/         OPC_CheckChild2Type, MVT::v2f32,
    7466             : /*17835*/         OPC_RecordChild3, // #2 = $rsrc
    7467             : /*17836*/         OPC_CheckChild3Type, MVT::v8i32,
    7468             : /*17838*/         OPC_RecordChild4, // #3 = $sampler
    7469             : /*17839*/         OPC_RecordChild5, // #4 = $dmask
    7470             : /*17840*/         OPC_RecordChild6, // #5 = $unorm
    7471             : /*17841*/         OPC_RecordChild7, // #6 = $glc
    7472             : /*17842*/         OPC_MoveChild, 8,
    7473             : /*17844*/         OPC_RecordNode, // #7 = $slc
    7474             : /*17845*/         OPC_MoveParent,
    7475             : /*17846*/         OPC_MoveChild, 9,
    7476             : /*17848*/         OPC_RecordNode, // #8 = $lwe
    7477             : /*17849*/         OPC_MoveParent,
    7478             : /*17850*/         OPC_MoveChild, 10,
    7479             : /*17852*/         OPC_RecordNode, // #9 = $da
    7480             : /*17853*/         OPC_MoveParent,
    7481             : /*17854*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->17899
    7482             : /*17857*/           OPC_EmitMergeInputChains1_0,
    7483             : /*17858*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7484             : /*17861*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7485             : /*17864*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7486             : /*17867*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7487             : /*17870*/           OPC_EmitInteger, MVT::i1, 0, 
    7488             : /*17873*/           OPC_EmitInteger, MVT::i1, 0, 
    7489             : /*17876*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7490             : /*17879*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7491             : /*17882*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V1_V2), 0|OPFL_Chain,
    7492             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7493             :                     // Src: (intrinsic_w_chain:f32 435:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7494             :                     // Dst: (IMAGE_GATHER4_C_B_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7495             : /*17899*/         /*SwitchType*/ 42, MVT::v2f32,// ->17943
    7496             : /*17901*/           OPC_EmitMergeInputChains1_0,
    7497             : /*17902*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7498             : /*17905*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7499             : /*17908*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7500             : /*17911*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7501             : /*17914*/           OPC_EmitInteger, MVT::i1, 0, 
    7502             : /*17917*/           OPC_EmitInteger, MVT::i1, 0, 
    7503             : /*17920*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7504             : /*17923*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7505             : /*17926*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V2_V2), 0|OPFL_Chain,
    7506             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7507             :                     // Src: (intrinsic_w_chain:v2f32 435:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7508             :                     // Dst: (IMAGE_GATHER4_C_B_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7509             : /*17943*/         /*SwitchType*/ 42, MVT::v4f32,// ->17987
    7510             : /*17945*/           OPC_EmitMergeInputChains1_0,
    7511             : /*17946*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7512             : /*17949*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7513             : /*17952*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7514             : /*17955*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7515             : /*17958*/           OPC_EmitInteger, MVT::i1, 0, 
    7516             : /*17961*/           OPC_EmitInteger, MVT::i1, 0, 
    7517             : /*17964*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7518             : /*17967*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7519             : /*17970*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V4_V2), 0|OPFL_Chain,
    7520             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7521             :                     // Src: (intrinsic_w_chain:v4f32 435:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7522             :                     // Dst: (IMAGE_GATHER4_C_B_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7523             : /*17987*/         0, // EndSwitchType
    7524             : /*17988*/       /*Scope*/ 27|128,1/*155*/, /*->18145*/
    7525             : /*17990*/         OPC_CheckChild2Type, MVT::v4f32,
    7526             : /*17992*/         OPC_RecordChild3, // #2 = $rsrc
    7527             : /*17993*/         OPC_CheckChild3Type, MVT::v8i32,
    7528             : /*17995*/         OPC_RecordChild4, // #3 = $sampler
    7529             : /*17996*/         OPC_RecordChild5, // #4 = $dmask
    7530             : /*17997*/         OPC_RecordChild6, // #5 = $unorm
    7531             : /*17998*/         OPC_RecordChild7, // #6 = $glc
    7532             : /*17999*/         OPC_MoveChild, 8,
    7533             : /*18001*/         OPC_RecordNode, // #7 = $slc
    7534             : /*18002*/         OPC_MoveParent,
    7535             : /*18003*/         OPC_MoveChild, 9,
    7536             : /*18005*/         OPC_RecordNode, // #8 = $lwe
    7537             : /*18006*/         OPC_MoveParent,
    7538             : /*18007*/         OPC_MoveChild, 10,
    7539             : /*18009*/         OPC_RecordNode, // #9 = $da
    7540             : /*18010*/         OPC_MoveParent,
    7541             : /*18011*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->18056
    7542             : /*18014*/           OPC_EmitMergeInputChains1_0,
    7543             : /*18015*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7544             : /*18018*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7545             : /*18021*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7546             : /*18024*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7547             : /*18027*/           OPC_EmitInteger, MVT::i1, 0, 
    7548             : /*18030*/           OPC_EmitInteger, MVT::i1, 0, 
    7549             : /*18033*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7550             : /*18036*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7551             : /*18039*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V1_V4), 0|OPFL_Chain,
    7552             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7553             :                     // Src: (intrinsic_w_chain:f32 435:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7554             :                     // Dst: (IMAGE_GATHER4_C_B_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7555             : /*18056*/         /*SwitchType*/ 42, MVT::v2f32,// ->18100
    7556             : /*18058*/           OPC_EmitMergeInputChains1_0,
    7557             : /*18059*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7558             : /*18062*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7559             : /*18065*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7560             : /*18068*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7561             : /*18071*/           OPC_EmitInteger, MVT::i1, 0, 
    7562             : /*18074*/           OPC_EmitInteger, MVT::i1, 0, 
    7563             : /*18077*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7564             : /*18080*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7565             : /*18083*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V2_V4), 0|OPFL_Chain,
    7566             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7567             :                     // Src: (intrinsic_w_chain:v2f32 435:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7568             :                     // Dst: (IMAGE_GATHER4_C_B_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7569             : /*18100*/         /*SwitchType*/ 42, MVT::v4f32,// ->18144
    7570             : /*18102*/           OPC_EmitMergeInputChains1_0,
    7571             : /*18103*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7572             : /*18106*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7573             : /*18109*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7574             : /*18112*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7575             : /*18115*/           OPC_EmitInteger, MVT::i1, 0, 
    7576             : /*18118*/           OPC_EmitInteger, MVT::i1, 0, 
    7577             : /*18121*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7578             : /*18124*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7579             : /*18127*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V4_V4), 0|OPFL_Chain,
    7580             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7581             :                     // Src: (intrinsic_w_chain:v4f32 435:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7582             :                     // Dst: (IMAGE_GATHER4_C_B_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7583             : /*18144*/         0, // EndSwitchType
    7584             : /*18145*/       /*Scope*/ 27|128,1/*155*/, /*->18302*/
    7585             : /*18147*/         OPC_CheckChild2Type, MVT::v8f32,
    7586             : /*18149*/         OPC_RecordChild3, // #2 = $rsrc
    7587             : /*18150*/         OPC_CheckChild3Type, MVT::v8i32,
    7588             : /*18152*/         OPC_RecordChild4, // #3 = $sampler
    7589             : /*18153*/         OPC_RecordChild5, // #4 = $dmask
    7590             : /*18154*/         OPC_RecordChild6, // #5 = $unorm
    7591             : /*18155*/         OPC_RecordChild7, // #6 = $glc
    7592             : /*18156*/         OPC_MoveChild, 8,
    7593             : /*18158*/         OPC_RecordNode, // #7 = $slc
    7594             : /*18159*/         OPC_MoveParent,
    7595             : /*18160*/         OPC_MoveChild, 9,
    7596             : /*18162*/         OPC_RecordNode, // #8 = $lwe
    7597             : /*18163*/         OPC_MoveParent,
    7598             : /*18164*/         OPC_MoveChild, 10,
    7599             : /*18166*/         OPC_RecordNode, // #9 = $da
    7600             : /*18167*/         OPC_MoveParent,
    7601             : /*18168*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->18213
    7602             : /*18171*/           OPC_EmitMergeInputChains1_0,
    7603             : /*18172*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7604             : /*18175*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7605             : /*18178*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7606             : /*18181*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7607             : /*18184*/           OPC_EmitInteger, MVT::i1, 0, 
    7608             : /*18187*/           OPC_EmitInteger, MVT::i1, 0, 
    7609             : /*18190*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7610             : /*18193*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7611             : /*18196*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V1_V8), 0|OPFL_Chain,
    7612             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7613             :                     // Src: (intrinsic_w_chain:f32 435:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7614             :                     // Dst: (IMAGE_GATHER4_C_B_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7615             : /*18213*/         /*SwitchType*/ 42, MVT::v2f32,// ->18257
    7616             : /*18215*/           OPC_EmitMergeInputChains1_0,
    7617             : /*18216*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7618             : /*18219*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7619             : /*18222*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7620             : /*18225*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7621             : /*18228*/           OPC_EmitInteger, MVT::i1, 0, 
    7622             : /*18231*/           OPC_EmitInteger, MVT::i1, 0, 
    7623             : /*18234*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7624             : /*18237*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7625             : /*18240*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V2_V8), 0|OPFL_Chain,
    7626             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7627             :                     // Src: (intrinsic_w_chain:v2f32 435:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7628             :                     // Dst: (IMAGE_GATHER4_C_B_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7629             : /*18257*/         /*SwitchType*/ 42, MVT::v4f32,// ->18301
    7630             : /*18259*/           OPC_EmitMergeInputChains1_0,
    7631             : /*18260*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7632             : /*18263*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7633             : /*18266*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7634             : /*18269*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7635             : /*18272*/           OPC_EmitInteger, MVT::i1, 0, 
    7636             : /*18275*/           OPC_EmitInteger, MVT::i1, 0, 
    7637             : /*18278*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7638             : /*18281*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7639             : /*18284*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V4_V8), 0|OPFL_Chain,
    7640             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7641             :                     // Src: (intrinsic_w_chain:v4f32 435:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7642             :                     // Dst: (IMAGE_GATHER4_C_B_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7643             : /*18301*/         0, // EndSwitchType
    7644             : /*18302*/       /*Scope*/ 27|128,1/*155*/, /*->18459*/
    7645             : /*18304*/         OPC_CheckChild2Type, MVT::v16f32,
    7646             : /*18306*/         OPC_RecordChild3, // #2 = $rsrc
    7647             : /*18307*/         OPC_CheckChild3Type, MVT::v8i32,
    7648             : /*18309*/         OPC_RecordChild4, // #3 = $sampler
    7649             : /*18310*/         OPC_RecordChild5, // #4 = $dmask
    7650             : /*18311*/         OPC_RecordChild6, // #5 = $unorm
    7651             : /*18312*/         OPC_RecordChild7, // #6 = $glc
    7652             : /*18313*/         OPC_MoveChild, 8,
    7653             : /*18315*/         OPC_RecordNode, // #7 = $slc
    7654             : /*18316*/         OPC_MoveParent,
    7655             : /*18317*/         OPC_MoveChild, 9,
    7656             : /*18319*/         OPC_RecordNode, // #8 = $lwe
    7657             : /*18320*/         OPC_MoveParent,
    7658             : /*18321*/         OPC_MoveChild, 10,
    7659             : /*18323*/         OPC_RecordNode, // #9 = $da
    7660             : /*18324*/         OPC_MoveParent,
    7661             : /*18325*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->18370
    7662             : /*18328*/           OPC_EmitMergeInputChains1_0,
    7663             : /*18329*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7664             : /*18332*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7665             : /*18335*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7666             : /*18338*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7667             : /*18341*/           OPC_EmitInteger, MVT::i1, 0, 
    7668             : /*18344*/           OPC_EmitInteger, MVT::i1, 0, 
    7669             : /*18347*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7670             : /*18350*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7671             : /*18353*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V1_V16), 0|OPFL_Chain,
    7672             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7673             :                     // Src: (intrinsic_w_chain:f32 435:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7674             :                     // Dst: (IMAGE_GATHER4_C_B_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7675             : /*18370*/         /*SwitchType*/ 42, MVT::v2f32,// ->18414
    7676             : /*18372*/           OPC_EmitMergeInputChains1_0,
    7677             : /*18373*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7678             : /*18376*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7679             : /*18379*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7680             : /*18382*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7681             : /*18385*/           OPC_EmitInteger, MVT::i1, 0, 
    7682             : /*18388*/           OPC_EmitInteger, MVT::i1, 0, 
    7683             : /*18391*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7684             : /*18394*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7685             : /*18397*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V2_V16), 0|OPFL_Chain,
    7686             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7687             :                     // Src: (intrinsic_w_chain:v2f32 435:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7688             :                     // Dst: (IMAGE_GATHER4_C_B_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7689             : /*18414*/         /*SwitchType*/ 42, MVT::v4f32,// ->18458
    7690             : /*18416*/           OPC_EmitMergeInputChains1_0,
    7691             : /*18417*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7692             : /*18420*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7693             : /*18423*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7694             : /*18426*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7695             : /*18429*/           OPC_EmitInteger, MVT::i1, 0, 
    7696             : /*18432*/           OPC_EmitInteger, MVT::i1, 0, 
    7697             : /*18435*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7698             : /*18438*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7699             : /*18441*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V4_V16), 0|OPFL_Chain,
    7700             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7701             :                     // Src: (intrinsic_w_chain:v4f32 435:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7702             :                     // Dst: (IMAGE_GATHER4_C_B_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7703             : /*18458*/         0, // EndSwitchType
    7704             : /*18459*/       0, /*End of Scope*/
    7705             : /*18460*/     /*Scope*/ 23|128,6/*791*/, /*->19253*/
    7706             : /*18462*/       OPC_CheckChild1Integer, 52|128,3/*436*/, 
    7707             : /*18465*/       OPC_RecordChild2, // #1 = $addr
    7708             : /*18466*/       OPC_Scope, 27|128,1/*155*/, /*->18624*/ // 5 children in Scope
    7709             : /*18469*/         OPC_CheckChild2Type, MVT::f32,
    7710             : /*18471*/         OPC_RecordChild3, // #2 = $rsrc
    7711             : /*18472*/         OPC_CheckChild3Type, MVT::v8i32,
    7712             : /*18474*/         OPC_RecordChild4, // #3 = $sampler
    7713             : /*18475*/         OPC_RecordChild5, // #4 = $dmask
    7714             : /*18476*/         OPC_RecordChild6, // #5 = $unorm
    7715             : /*18477*/         OPC_RecordChild7, // #6 = $glc
    7716             : /*18478*/         OPC_MoveChild, 8,
    7717             : /*18480*/         OPC_RecordNode, // #7 = $slc
    7718             : /*18481*/         OPC_MoveParent,
    7719             : /*18482*/         OPC_MoveChild, 9,
    7720             : /*18484*/         OPC_RecordNode, // #8 = $lwe
    7721             : /*18485*/         OPC_MoveParent,
    7722             : /*18486*/         OPC_MoveChild, 10,
    7723             : /*18488*/         OPC_RecordNode, // #9 = $da
    7724             : /*18489*/         OPC_MoveParent,
    7725             : /*18490*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->18535
    7726             : /*18493*/           OPC_EmitMergeInputChains1_0,
    7727             : /*18494*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7728             : /*18497*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7729             : /*18500*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7730             : /*18503*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7731             : /*18506*/           OPC_EmitInteger, MVT::i1, 0, 
    7732             : /*18509*/           OPC_EmitInteger, MVT::i1, 0, 
    7733             : /*18512*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7734             : /*18515*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7735             : /*18518*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V1), 0|OPFL_Chain,
    7736             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7737             :                     // Src: (intrinsic_w_chain:f32 436:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7738             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7739             : /*18535*/         /*SwitchType*/ 42, MVT::v2f32,// ->18579
    7740             : /*18537*/           OPC_EmitMergeInputChains1_0,
    7741             : /*18538*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7742             : /*18541*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7743             : /*18544*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7744             : /*18547*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7745             : /*18550*/           OPC_EmitInteger, MVT::i1, 0, 
    7746             : /*18553*/           OPC_EmitInteger, MVT::i1, 0, 
    7747             : /*18556*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7748             : /*18559*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7749             : /*18562*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V1), 0|OPFL_Chain,
    7750             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7751             :                     // Src: (intrinsic_w_chain:v2f32 436:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7752             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7753             : /*18579*/         /*SwitchType*/ 42, MVT::v4f32,// ->18623
    7754             : /*18581*/           OPC_EmitMergeInputChains1_0,
    7755             : /*18582*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7756             : /*18585*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7757             : /*18588*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7758             : /*18591*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7759             : /*18594*/           OPC_EmitInteger, MVT::i1, 0, 
    7760             : /*18597*/           OPC_EmitInteger, MVT::i1, 0, 
    7761             : /*18600*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7762             : /*18603*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7763             : /*18606*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V1), 0|OPFL_Chain,
    7764             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7765             :                     // Src: (intrinsic_w_chain:v4f32 436:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7766             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7767             : /*18623*/         0, // EndSwitchType
    7768             : /*18624*/       /*Scope*/ 27|128,1/*155*/, /*->18781*/
    7769             : /*18626*/         OPC_CheckChild2Type, MVT::v2f32,
    7770             : /*18628*/         OPC_RecordChild3, // #2 = $rsrc
    7771             : /*18629*/         OPC_CheckChild3Type, MVT::v8i32,
    7772             : /*18631*/         OPC_RecordChild4, // #3 = $sampler
    7773             : /*18632*/         OPC_RecordChild5, // #4 = $dmask
    7774             : /*18633*/         OPC_RecordChild6, // #5 = $unorm
    7775             : /*18634*/         OPC_RecordChild7, // #6 = $glc
    7776             : /*18635*/         OPC_MoveChild, 8,
    7777             : /*18637*/         OPC_RecordNode, // #7 = $slc
    7778             : /*18638*/         OPC_MoveParent,
    7779             : /*18639*/         OPC_MoveChild, 9,
    7780             : /*18641*/         OPC_RecordNode, // #8 = $lwe
    7781             : /*18642*/         OPC_MoveParent,
    7782             : /*18643*/         OPC_MoveChild, 10,
    7783             : /*18645*/         OPC_RecordNode, // #9 = $da
    7784             : /*18646*/         OPC_MoveParent,
    7785             : /*18647*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->18692
    7786             : /*18650*/           OPC_EmitMergeInputChains1_0,
    7787             : /*18651*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7788             : /*18654*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7789             : /*18657*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7790             : /*18660*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7791             : /*18663*/           OPC_EmitInteger, MVT::i1, 0, 
    7792             : /*18666*/           OPC_EmitInteger, MVT::i1, 0, 
    7793             : /*18669*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7794             : /*18672*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7795             : /*18675*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V2), 0|OPFL_Chain,
    7796             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7797             :                     // Src: (intrinsic_w_chain:f32 436:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7798             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V1_V2:f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7799             : /*18692*/         /*SwitchType*/ 42, MVT::v2f32,// ->18736
    7800             : /*18694*/           OPC_EmitMergeInputChains1_0,
    7801             : /*18695*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7802             : /*18698*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7803             : /*18701*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7804             : /*18704*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7805             : /*18707*/           OPC_EmitInteger, MVT::i1, 0, 
    7806             : /*18710*/           OPC_EmitInteger, MVT::i1, 0, 
    7807             : /*18713*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7808             : /*18716*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7809             : /*18719*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V2), 0|OPFL_Chain,
    7810             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7811             :                     // Src: (intrinsic_w_chain:v2f32 436:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7812             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V2_V2:v2f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7813             : /*18736*/         /*SwitchType*/ 42, MVT::v4f32,// ->18780
    7814             : /*18738*/           OPC_EmitMergeInputChains1_0,
    7815             : /*18739*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7816             : /*18742*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7817             : /*18745*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7818             : /*18748*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7819             : /*18751*/           OPC_EmitInteger, MVT::i1, 0, 
    7820             : /*18754*/           OPC_EmitInteger, MVT::i1, 0, 
    7821             : /*18757*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7822             : /*18760*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7823             : /*18763*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V2), 0|OPFL_Chain,
    7824             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7825             :                     // Src: (intrinsic_w_chain:v4f32 436:iPTR, v2f32:v2f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7826             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V4_V2:v4f32 ?:v2f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7827             : /*18780*/         0, // EndSwitchType
    7828             : /*18781*/       /*Scope*/ 27|128,1/*155*/, /*->18938*/
    7829             : /*18783*/         OPC_CheckChild2Type, MVT::v4f32,
    7830             : /*18785*/         OPC_RecordChild3, // #2 = $rsrc
    7831             : /*18786*/         OPC_CheckChild3Type, MVT::v8i32,
    7832             : /*18788*/         OPC_RecordChild4, // #3 = $sampler
    7833             : /*18789*/         OPC_RecordChild5, // #4 = $dmask
    7834             : /*18790*/         OPC_RecordChild6, // #5 = $unorm
    7835             : /*18791*/         OPC_RecordChild7, // #6 = $glc
    7836             : /*18792*/         OPC_MoveChild, 8,
    7837             : /*18794*/         OPC_RecordNode, // #7 = $slc
    7838             : /*18795*/         OPC_MoveParent,
    7839             : /*18796*/         OPC_MoveChild, 9,
    7840             : /*18798*/         OPC_RecordNode, // #8 = $lwe
    7841             : /*18799*/         OPC_MoveParent,
    7842             : /*18800*/         OPC_MoveChild, 10,
    7843             : /*18802*/         OPC_RecordNode, // #9 = $da
    7844             : /*18803*/         OPC_MoveParent,
    7845             : /*18804*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->18849
    7846             : /*18807*/           OPC_EmitMergeInputChains1_0,
    7847             : /*18808*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7848             : /*18811*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7849             : /*18814*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7850             : /*18817*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7851             : /*18820*/           OPC_EmitInteger, MVT::i1, 0, 
    7852             : /*18823*/           OPC_EmitInteger, MVT::i1, 0, 
    7853             : /*18826*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7854             : /*18829*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7855             : /*18832*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V4), 0|OPFL_Chain,
    7856             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7857             :                     // Src: (intrinsic_w_chain:f32 436:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7858             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V1_V4:f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7859             : /*18849*/         /*SwitchType*/ 42, MVT::v2f32,// ->18893
    7860             : /*18851*/           OPC_EmitMergeInputChains1_0,
    7861             : /*18852*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7862             : /*18855*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7863             : /*18858*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7864             : /*18861*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7865             : /*18864*/           OPC_EmitInteger, MVT::i1, 0, 
    7866             : /*18867*/           OPC_EmitInteger, MVT::i1, 0, 
    7867             : /*18870*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7868             : /*18873*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7869             : /*18876*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4), 0|OPFL_Chain,
    7870             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7871             :                     // Src: (intrinsic_w_chain:v2f32 436:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7872             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V2_V4:v2f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7873             : /*18893*/         /*SwitchType*/ 42, MVT::v4f32,// ->18937
    7874             : /*18895*/           OPC_EmitMergeInputChains1_0,
    7875             : /*18896*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7876             : /*18899*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7877             : /*18902*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7878             : /*18905*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7879             : /*18908*/           OPC_EmitInteger, MVT::i1, 0, 
    7880             : /*18911*/           OPC_EmitInteger, MVT::i1, 0, 
    7881             : /*18914*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7882             : /*18917*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7883             : /*18920*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4), 0|OPFL_Chain,
    7884             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7885             :                     // Src: (intrinsic_w_chain:v4f32 436:iPTR, v4f32:v4f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7886             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V4_V4:v4f32 ?:v4f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7887             : /*18937*/         0, // EndSwitchType
    7888             : /*18938*/       /*Scope*/ 27|128,1/*155*/, /*->19095*/
    7889             : /*18940*/         OPC_CheckChild2Type, MVT::v8f32,
    7890             : /*18942*/         OPC_RecordChild3, // #2 = $rsrc
    7891             : /*18943*/         OPC_CheckChild3Type, MVT::v8i32,
    7892             : /*18945*/         OPC_RecordChild4, // #3 = $sampler
    7893             : /*18946*/         OPC_RecordChild5, // #4 = $dmask
    7894             : /*18947*/         OPC_RecordChild6, // #5 = $unorm
    7895             : /*18948*/         OPC_RecordChild7, // #6 = $glc
    7896             : /*18949*/         OPC_MoveChild, 8,
    7897             : /*18951*/         OPC_RecordNode, // #7 = $slc
    7898             : /*18952*/         OPC_MoveParent,
    7899             : /*18953*/         OPC_MoveChild, 9,
    7900             : /*18955*/         OPC_RecordNode, // #8 = $lwe
    7901             : /*18956*/         OPC_MoveParent,
    7902             : /*18957*/         OPC_MoveChild, 10,
    7903             : /*18959*/         OPC_RecordNode, // #9 = $da
    7904             : /*18960*/         OPC_MoveParent,
    7905             : /*18961*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->19006
    7906             : /*18964*/           OPC_EmitMergeInputChains1_0,
    7907             : /*18965*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7908             : /*18968*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7909             : /*18971*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7910             : /*18974*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7911             : /*18977*/           OPC_EmitInteger, MVT::i1, 0, 
    7912             : /*18980*/           OPC_EmitInteger, MVT::i1, 0, 
    7913             : /*18983*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7914             : /*18986*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7915             : /*18989*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V8), 0|OPFL_Chain,
    7916             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7917             :                     // Src: (intrinsic_w_chain:f32 436:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7918             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V1_V8:f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7919             : /*19006*/         /*SwitchType*/ 42, MVT::v2f32,// ->19050
    7920             : /*19008*/           OPC_EmitMergeInputChains1_0,
    7921             : /*19009*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7922             : /*19012*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7923             : /*19015*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7924             : /*19018*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7925             : /*19021*/           OPC_EmitInteger, MVT::i1, 0, 
    7926             : /*19024*/           OPC_EmitInteger, MVT::i1, 0, 
    7927             : /*19027*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7928             : /*19030*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7929             : /*19033*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8), 0|OPFL_Chain,
    7930             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7931             :                     // Src: (intrinsic_w_chain:v2f32 436:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7932             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V2_V8:v2f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7933             : /*19050*/         /*SwitchType*/ 42, MVT::v4f32,// ->19094
    7934             : /*19052*/           OPC_EmitMergeInputChains1_0,
    7935             : /*19053*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7936             : /*19056*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7937             : /*19059*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7938             : /*19062*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7939             : /*19065*/           OPC_EmitInteger, MVT::i1, 0, 
    7940             : /*19068*/           OPC_EmitInteger, MVT::i1, 0, 
    7941             : /*19071*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7942             : /*19074*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7943             : /*19077*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8), 0|OPFL_Chain,
    7944             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7945             :                     // Src: (intrinsic_w_chain:v4f32 436:iPTR, v8f32:v8f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7946             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V4_V8:v4f32 ?:v8f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7947             : /*19094*/         0, // EndSwitchType
    7948             : /*19095*/       /*Scope*/ 27|128,1/*155*/, /*->19252*/
    7949             : /*19097*/         OPC_CheckChild2Type, MVT::v16f32,
    7950             : /*19099*/         OPC_RecordChild3, // #2 = $rsrc
    7951             : /*19100*/         OPC_CheckChild3Type, MVT::v8i32,
    7952             : /*19102*/         OPC_RecordChild4, // #3 = $sampler
    7953             : /*19103*/         OPC_RecordChild5, // #4 = $dmask
    7954             : /*19104*/         OPC_RecordChild6, // #5 = $unorm
    7955             : /*19105*/         OPC_RecordChild7, // #6 = $glc
    7956             : /*19106*/         OPC_MoveChild, 8,
    7957             : /*19108*/         OPC_RecordNode, // #7 = $slc
    7958             : /*19109*/         OPC_MoveParent,
    7959             : /*19110*/         OPC_MoveChild, 9,
    7960             : /*19112*/         OPC_RecordNode, // #8 = $lwe
    7961             : /*19113*/         OPC_MoveParent,
    7962             : /*19114*/         OPC_MoveChild, 10,
    7963             : /*19116*/         OPC_RecordNode, // #9 = $da
    7964             : /*19117*/         OPC_MoveParent,
    7965             : /*19118*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->19163
    7966             : /*19121*/           OPC_EmitMergeInputChains1_0,
    7967             : /*19122*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7968             : /*19125*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7969             : /*19128*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7970             : /*19131*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7971             : /*19134*/           OPC_EmitInteger, MVT::i1, 0, 
    7972             : /*19137*/           OPC_EmitInteger, MVT::i1, 0, 
    7973             : /*19140*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7974             : /*19143*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7975             : /*19146*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V16), 0|OPFL_Chain,
    7976             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7977             :                     // Src: (intrinsic_w_chain:f32 436:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7978             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V1_V16:f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7979             : /*19163*/         /*SwitchType*/ 42, MVT::v2f32,// ->19207
    7980             : /*19165*/           OPC_EmitMergeInputChains1_0,
    7981             : /*19166*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7982             : /*19169*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7983             : /*19172*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7984             : /*19175*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7985             : /*19178*/           OPC_EmitInteger, MVT::i1, 0, 
    7986             : /*19181*/           OPC_EmitInteger, MVT::i1, 0, 
    7987             : /*19184*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    7988             : /*19187*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    7989             : /*19190*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V16), 0|OPFL_Chain,
    7990             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    7991             :                     // Src: (intrinsic_w_chain:v2f32 436:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    7992             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V2_V16:v2f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    7993             : /*19207*/         /*SwitchType*/ 42, MVT::v4f32,// ->19251
    7994             : /*19209*/           OPC_EmitMergeInputChains1_0,
    7995             : /*19210*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    7996             : /*19213*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    7997             : /*19216*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    7998             : /*19219*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    7999             : /*19222*/           OPC_EmitInteger, MVT::i1, 0, 
    8000             : /*19225*/           OPC_EmitInteger, MVT::i1, 0, 
    8001             : /*19228*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    8002             : /*19231*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    8003             : /*19234*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V16), 0|OPFL_Chain,
    8004             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    8005             :                     // Src: (intrinsic_w_chain:v4f32 436:iPTR, v16f32:v16f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    8006             :                     // Dst: (IMAGE_GATHER4_C_B_CL_V4_V16:v4f32 ?:v16f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    8007             : /*19251*/         0, // EndSwitchType
    8008             : /*19252*/       0, /*End of Scope*/
    8009             : /*19253*/     /*Scope*/ 23|128,6/*791*/, /*->20046*/
    8010             : /*19255*/       OPC_CheckChild1Integer, 59|128,3/*443*/, 
    8011             : /*19258*/       OPC_RecordChild2, // #1 = $addr
    8012             : /*19259*/       OPC_Scope, 27|128,1/*155*/, /*->19417*/ // 5 children in Scope
    8013             : /*19262*/         OPC_CheckChild2Type, MVT::f32,
    8014             : /*19264*/         OPC_RecordChild3, // #2 = $rsrc
    8015             : /*19265*/         OPC_CheckChild3Type, MVT::v8i32,
    8016             : /*19267*/         OPC_RecordChild4, // #3 = $sampler
    8017             : /*19268*/         OPC_RecordChild5, // #4 = $dmask
    8018             : /*19269*/         OPC_RecordChild6, // #5 = $unorm
    8019             : /*19270*/         OPC_RecordChild7, // #6 = $glc
    8020             : /*19271*/         OPC_MoveChild, 8,
    8021             : /*19273*/         OPC_RecordNode, // #7 = $slc
    8022             : /*19274*/         OPC_MoveParent,
    8023             : /*19275*/         OPC_MoveChild, 9,
    8024             : /*19277*/         OPC_RecordNode, // #8 = $lwe
    8025             : /*19278*/         OPC_MoveParent,
    8026             : /*19279*/         OPC_MoveChild, 10,
    8027             : /*19281*/         OPC_RecordNode, // #9 = $da
    8028             : /*19282*/         OPC_MoveParent,
    8029             : /*19283*/         OPC_SwitchType /*3 cases */, 42, MVT::f32,// ->19328
    8030             : /*19286*/           OPC_EmitMergeInputChains1_0,
    8031             : /*19287*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    8032             : /*19290*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    8033             : /*19293*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    8034             : /*19296*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    8035             : /*19299*/           OPC_EmitInteger, MVT::i1, 0, 
    8036             : /*19302*/           OPC_EmitInteger, MVT::i1, 0, 
    8037             : /*19305*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    8038             : /*19308*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    8039             : /*19311*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_LZ_V1_V1), 0|OPFL_Chain,
    8040             :                         MVT::f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    8041             :                     // Src: (intrinsic_w_chain:f32 443:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    8042             :                     // Dst: (IMAGE_GATHER4_C_LZ_V1_V1:f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    8043             : /*19328*/         /*SwitchType*/ 42, MVT::v2f32,// ->19372
    8044             : /*19330*/           OPC_EmitMergeInputChains1_0,
    8045             : /*19331*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    8046             : /*19334*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    8047             : /*19337*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    8048             : /*19340*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    8049             : /*19343*/           OPC_EmitInteger, MVT::i1, 0, 
    8050             : /*19346*/           OPC_EmitInteger, MVT::i1, 0, 
    8051             : /*19349*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    8052             : /*19352*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    8053             : /*19355*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_LZ_V2_V1), 0|OPFL_Chain,
    8054             :                         MVT::v2f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    8055             :                     // Src: (intrinsic_w_chain:v2f32 443:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    8056             :                     // Dst: (IMAGE_GATHER4_C_LZ_V2_V1:v2f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    8057             : /*19372*/         /*SwitchType*/ 42, MVT::v4f32,// ->19416
    8058             : /*19374*/           OPC_EmitMergeInputChains1_0,
    8059             : /*19375*/           OPC_EmitNodeXForm, 2, 4, // as_i32imm
    8060             : /*19378*/           OPC_EmitNodeXForm, 1, 5, // as_i1imm
    8061             : /*19381*/           OPC_EmitNodeXForm, 1, 6, // as_i1imm
    8062             : /*19384*/           OPC_EmitNodeXForm, 1, 7, // as_i1imm
    8063             : /*19387*/           OPC_EmitInteger, MVT::i1, 0, 
    8064             : /*19390*/           OPC_EmitInteger, MVT::i1, 0, 
    8065             : /*19393*/           OPC_EmitNodeXForm, 1, 8, // as_i1imm
    8066             : /*19396*/           OPC_EmitNodeXForm, 1, 9, // as_i1imm
    8067             : /*19399*/           OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_LZ_V4_V1), 0|OPFL_Chain,
    8068             :                         MVT::v4f32, 11/*#Ops*/, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 
    8069             :                     // Src: (intrinsic_w_chain:v4f32 443:iPTR, f32:f32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i1:i1:$unorm, i1:i1:$glc, i1:i1:$slc, i1:i1:$lwe, i1:i1:$da) - Complexity = 8
    8070             :                     // Dst: (IMAGE_GATHER4_C_LZ_V4_V1:v4f32 ?:f32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler, (as_i32imm:i16 ?:i32:$dmask), (as_i1imm:i1 ?:i1:$unorm), (as_i1imm:i1 ?:i1:$glc), (as_i1imm:i1 ?:i1:$slc), 0:i1, 0:i1, (as_i1imm:i1 ?:i1:$lwe), (as_i1imm:i1 ?:i1:$da))
    8071             : /*19416*/         0, // EndSwitchType
    8072             : /*19417*/       /*Scope*/ 27|128,1/*155*/, /*->19574*/
    8073             : /*19419*/         OPC_CheckChild2Type, MVT::v2f32,
    8074             : /*19421*/         OPC_RecordChild3, // #2 = $rsrc
    8075             : /*19422*/         OPC_CheckChild3Type, MVT::v8i32,
    8076             : /*19424*/         OPC_RecordChild4, // #3 = $sampler
    8077             : /*19425*/         OPC_RecordChild5, // #4 = $dmask
    8078             : /*19426*/         OPC_RecordChild6, // #5 = $unorm
    8079             : /*19427*/         OPC_RecordChild7, // #6 = $glc
    8080             : /*19428*/         OPC_MoveChild, 8,
    8081             : /*19430*/         OPC_RecordNode, // #7 = $slc
    8082             : /*19431*/         OPC_MoveParent,
    8083             : /*19432*/         OPC_MoveChild, 9,
    8084             : /*19434*/         OPC_RecordNode, // #8 = $lwe
    8085             : /*19435*/         OPC_MoveParent,