LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 326 370 88.1 %
Date: 2017-09-14 15:23:50 Functions: 13 17 76.5 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace AMDGPU {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     REG_SEQUENCE        = 13,
      29             :     COPY        = 14,
      30             :     BUNDLE      = 15,
      31             :     LIFETIME_START      = 16,
      32             :     LIFETIME_END        = 17,
      33             :     STACKMAP    = 18,
      34             :     FENTRY_CALL = 19,
      35             :     PATCHPOINT  = 20,
      36             :     LOAD_STACK_GUARD    = 21,
      37             :     STATEPOINT  = 22,
      38             :     LOCAL_ESCAPE        = 23,
      39             :     FAULTING_OP = 24,
      40             :     PATCHABLE_OP        = 25,
      41             :     PATCHABLE_FUNCTION_ENTER    = 26,
      42             :     PATCHABLE_RET       = 27,
      43             :     PATCHABLE_FUNCTION_EXIT     = 28,
      44             :     PATCHABLE_TAIL_CALL = 29,
      45             :     PATCHABLE_EVENT_CALL        = 30,
      46             :     G_ADD       = 31,
      47             :     G_SUB       = 32,
      48             :     G_MUL       = 33,
      49             :     G_SDIV      = 34,
      50             :     G_UDIV      = 35,
      51             :     G_SREM      = 36,
      52             :     G_UREM      = 37,
      53             :     G_AND       = 38,
      54             :     G_OR        = 39,
      55             :     G_XOR       = 40,
      56             :     G_IMPLICIT_DEF      = 41,
      57             :     G_PHI       = 42,
      58             :     G_FRAME_INDEX       = 43,
      59             :     G_GLOBAL_VALUE      = 44,
      60             :     G_EXTRACT   = 45,
      61             :     G_UNMERGE_VALUES    = 46,
      62             :     G_INSERT    = 47,
      63             :     G_MERGE_VALUES      = 48,
      64             :     G_PTRTOINT  = 49,
      65             :     G_INTTOPTR  = 50,
      66             :     G_BITCAST   = 51,
      67             :     G_LOAD      = 52,
      68             :     G_STORE     = 53,
      69             :     G_BRCOND    = 54,
      70             :     G_BRINDIRECT        = 55,
      71             :     G_INTRINSIC = 56,
      72             :     G_INTRINSIC_W_SIDE_EFFECTS  = 57,
      73             :     G_ANYEXT    = 58,
      74             :     G_TRUNC     = 59,
      75             :     G_CONSTANT  = 60,
      76             :     G_FCONSTANT = 61,
      77             :     G_VASTART   = 62,
      78             :     G_VAARG     = 63,
      79             :     G_SEXT      = 64,
      80             :     G_ZEXT      = 65,
      81             :     G_SHL       = 66,
      82             :     G_LSHR      = 67,
      83             :     G_ASHR      = 68,
      84             :     G_ICMP      = 69,
      85             :     G_FCMP      = 70,
      86             :     G_SELECT    = 71,
      87             :     G_UADDE     = 72,
      88             :     G_USUBE     = 73,
      89             :     G_SADDO     = 74,
      90             :     G_SSUBO     = 75,
      91             :     G_UMULO     = 76,
      92             :     G_SMULO     = 77,
      93             :     G_UMULH     = 78,
      94             :     G_SMULH     = 79,
      95             :     G_FADD      = 80,
      96             :     G_FSUB      = 81,
      97             :     G_FMUL      = 82,
      98             :     G_FMA       = 83,
      99             :     G_FDIV      = 84,
     100             :     G_FREM      = 85,
     101             :     G_FPOW      = 86,
     102             :     G_FEXP      = 87,
     103             :     G_FEXP2     = 88,
     104             :     G_FLOG      = 89,
     105             :     G_FLOG2     = 90,
     106             :     G_FNEG      = 91,
     107             :     G_FPEXT     = 92,
     108             :     G_FPTRUNC   = 93,
     109             :     G_FPTOSI    = 94,
     110             :     G_FPTOUI    = 95,
     111             :     G_SITOFP    = 96,
     112             :     G_UITOFP    = 97,
     113             :     G_GEP       = 98,
     114             :     G_PTR_MASK  = 99,
     115             :     G_BR        = 100,
     116             :     G_INSERT_VECTOR_ELT = 101,
     117             :     G_EXTRACT_VECTOR_ELT        = 102,
     118             :     G_SHUFFLE_VECTOR    = 103,
     119             :     ADD = 104,
     120             :     ADDC_UINT   = 105,
     121             :     ADD_INT     = 106,
     122             :     ADJCALLSTACKDOWN    = 107,
     123             :     ADJCALLSTACKUP      = 108,
     124             :     ALU_CLAUSE  = 109,
     125             :     AND_INT     = 110,
     126             :     ASHR_eg     = 111,
     127             :     ASHR_r600   = 112,
     128             :     ATOMIC_FENCE        = 113,
     129             :     BCNT_INT    = 114,
     130             :     BFE_INT_eg  = 115,
     131             :     BFE_UINT_eg = 116,
     132             :     BFI_INT_eg  = 117,
     133             :     BFM_INT_eg  = 118,
     134             :     BIT_ALIGN_INT_eg    = 119,
     135             :     BRANCH      = 120,
     136             :     BRANCH_COND_f32     = 121,
     137             :     BRANCH_COND_i32     = 122,
     138             :     BREAK       = 123,
     139             :     BREAKC_f32  = 124,
     140             :     BREAKC_i32  = 125,
     141             :     BREAK_LOGICALNZ_f32 = 126,
     142             :     BREAK_LOGICALNZ_i32 = 127,
     143             :     BREAK_LOGICALZ_f32  = 128,
     144             :     BREAK_LOGICALZ_i32  = 129,
     145             :     BUFFER_ATOMIC_ADD_ADDR64    = 130,
     146             :     BUFFER_ATOMIC_ADD_ADDR64_RTN        = 131,
     147             :     BUFFER_ATOMIC_ADD_ADDR64_RTN_si     = 132,
     148             :     BUFFER_ATOMIC_ADD_ADDR64_si = 133,
     149             :     BUFFER_ATOMIC_ADD_BOTHEN    = 134,
     150             :     BUFFER_ATOMIC_ADD_BOTHEN_RTN        = 135,
     151             :     BUFFER_ATOMIC_ADD_BOTHEN_RTN_si     = 136,
     152             :     BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi     = 137,
     153             :     BUFFER_ATOMIC_ADD_BOTHEN_si = 138,
     154             :     BUFFER_ATOMIC_ADD_BOTHEN_vi = 139,
     155             :     BUFFER_ATOMIC_ADD_IDXEN     = 140,
     156             :     BUFFER_ATOMIC_ADD_IDXEN_RTN = 141,
     157             :     BUFFER_ATOMIC_ADD_IDXEN_RTN_si      = 142,
     158             :     BUFFER_ATOMIC_ADD_IDXEN_RTN_vi      = 143,
     159             :     BUFFER_ATOMIC_ADD_IDXEN_si  = 144,
     160             :     BUFFER_ATOMIC_ADD_IDXEN_vi  = 145,
     161             :     BUFFER_ATOMIC_ADD_OFFEN     = 146,
     162             :     BUFFER_ATOMIC_ADD_OFFEN_RTN = 147,
     163             :     BUFFER_ATOMIC_ADD_OFFEN_RTN_si      = 148,
     164             :     BUFFER_ATOMIC_ADD_OFFEN_RTN_vi      = 149,
     165             :     BUFFER_ATOMIC_ADD_OFFEN_si  = 150,
     166             :     BUFFER_ATOMIC_ADD_OFFEN_vi  = 151,
     167             :     BUFFER_ATOMIC_ADD_OFFSET    = 152,
     168             :     BUFFER_ATOMIC_ADD_OFFSET_RTN        = 153,
     169             :     BUFFER_ATOMIC_ADD_OFFSET_RTN_si     = 154,
     170             :     BUFFER_ATOMIC_ADD_OFFSET_RTN_vi     = 155,
     171             :     BUFFER_ATOMIC_ADD_OFFSET_si = 156,
     172             :     BUFFER_ATOMIC_ADD_OFFSET_vi = 157,
     173             :     BUFFER_ATOMIC_ADD_X2_ADDR64 = 158,
     174             :     BUFFER_ATOMIC_ADD_X2_ADDR64_RTN     = 159,
     175             :     BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_si  = 160,
     176             :     BUFFER_ATOMIC_ADD_X2_ADDR64_si      = 161,
     177             :     BUFFER_ATOMIC_ADD_X2_BOTHEN = 162,
     178             :     BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN     = 163,
     179             :     BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_si  = 164,
     180             :     BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi  = 165,
     181             :     BUFFER_ATOMIC_ADD_X2_BOTHEN_si      = 166,
     182             :     BUFFER_ATOMIC_ADD_X2_BOTHEN_vi      = 167,
     183             :     BUFFER_ATOMIC_ADD_X2_IDXEN  = 168,
     184             :     BUFFER_ATOMIC_ADD_X2_IDXEN_RTN      = 169,
     185             :     BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_si   = 170,
     186             :     BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi   = 171,
     187             :     BUFFER_ATOMIC_ADD_X2_IDXEN_si       = 172,
     188             :     BUFFER_ATOMIC_ADD_X2_IDXEN_vi       = 173,
     189             :     BUFFER_ATOMIC_ADD_X2_OFFEN  = 174,
     190             :     BUFFER_ATOMIC_ADD_X2_OFFEN_RTN      = 175,
     191             :     BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_si   = 176,
     192             :     BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi   = 177,
     193             :     BUFFER_ATOMIC_ADD_X2_OFFEN_si       = 178,
     194             :     BUFFER_ATOMIC_ADD_X2_OFFEN_vi       = 179,
     195             :     BUFFER_ATOMIC_ADD_X2_OFFSET = 180,
     196             :     BUFFER_ATOMIC_ADD_X2_OFFSET_RTN     = 181,
     197             :     BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_si  = 182,
     198             :     BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi  = 183,
     199             :     BUFFER_ATOMIC_ADD_X2_OFFSET_si      = 184,
     200             :     BUFFER_ATOMIC_ADD_X2_OFFSET_vi      = 185,
     201             :     BUFFER_ATOMIC_AND_ADDR64    = 186,
     202             :     BUFFER_ATOMIC_AND_ADDR64_RTN        = 187,
     203             :     BUFFER_ATOMIC_AND_ADDR64_RTN_si     = 188,
     204             :     BUFFER_ATOMIC_AND_ADDR64_si = 189,
     205             :     BUFFER_ATOMIC_AND_BOTHEN    = 190,
     206             :     BUFFER_ATOMIC_AND_BOTHEN_RTN        = 191,
     207             :     BUFFER_ATOMIC_AND_BOTHEN_RTN_si     = 192,
     208             :     BUFFER_ATOMIC_AND_BOTHEN_RTN_vi     = 193,
     209             :     BUFFER_ATOMIC_AND_BOTHEN_si = 194,
     210             :     BUFFER_ATOMIC_AND_BOTHEN_vi = 195,
     211             :     BUFFER_ATOMIC_AND_IDXEN     = 196,
     212             :     BUFFER_ATOMIC_AND_IDXEN_RTN = 197,
     213             :     BUFFER_ATOMIC_AND_IDXEN_RTN_si      = 198,
     214             :     BUFFER_ATOMIC_AND_IDXEN_RTN_vi      = 199,
     215             :     BUFFER_ATOMIC_AND_IDXEN_si  = 200,
     216             :     BUFFER_ATOMIC_AND_IDXEN_vi  = 201,
     217             :     BUFFER_ATOMIC_AND_OFFEN     = 202,
     218             :     BUFFER_ATOMIC_AND_OFFEN_RTN = 203,
     219             :     BUFFER_ATOMIC_AND_OFFEN_RTN_si      = 204,
     220             :     BUFFER_ATOMIC_AND_OFFEN_RTN_vi      = 205,
     221             :     BUFFER_ATOMIC_AND_OFFEN_si  = 206,
     222             :     BUFFER_ATOMIC_AND_OFFEN_vi  = 207,
     223             :     BUFFER_ATOMIC_AND_OFFSET    = 208,
     224             :     BUFFER_ATOMIC_AND_OFFSET_RTN        = 209,
     225             :     BUFFER_ATOMIC_AND_OFFSET_RTN_si     = 210,
     226             :     BUFFER_ATOMIC_AND_OFFSET_RTN_vi     = 211,
     227             :     BUFFER_ATOMIC_AND_OFFSET_si = 212,
     228             :     BUFFER_ATOMIC_AND_OFFSET_vi = 213,
     229             :     BUFFER_ATOMIC_AND_X2_ADDR64 = 214,
     230             :     BUFFER_ATOMIC_AND_X2_ADDR64_RTN     = 215,
     231             :     BUFFER_ATOMIC_AND_X2_ADDR64_RTN_si  = 216,
     232             :     BUFFER_ATOMIC_AND_X2_ADDR64_si      = 217,
     233             :     BUFFER_ATOMIC_AND_X2_BOTHEN = 218,
     234             :     BUFFER_ATOMIC_AND_X2_BOTHEN_RTN     = 219,
     235             :     BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_si  = 220,
     236             :     BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi  = 221,
     237             :     BUFFER_ATOMIC_AND_X2_BOTHEN_si      = 222,
     238             :     BUFFER_ATOMIC_AND_X2_BOTHEN_vi      = 223,
     239             :     BUFFER_ATOMIC_AND_X2_IDXEN  = 224,
     240             :     BUFFER_ATOMIC_AND_X2_IDXEN_RTN      = 225,
     241             :     BUFFER_ATOMIC_AND_X2_IDXEN_RTN_si   = 226,
     242             :     BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi   = 227,
     243             :     BUFFER_ATOMIC_AND_X2_IDXEN_si       = 228,
     244             :     BUFFER_ATOMIC_AND_X2_IDXEN_vi       = 229,
     245             :     BUFFER_ATOMIC_AND_X2_OFFEN  = 230,
     246             :     BUFFER_ATOMIC_AND_X2_OFFEN_RTN      = 231,
     247             :     BUFFER_ATOMIC_AND_X2_OFFEN_RTN_si   = 232,
     248             :     BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi   = 233,
     249             :     BUFFER_ATOMIC_AND_X2_OFFEN_si       = 234,
     250             :     BUFFER_ATOMIC_AND_X2_OFFEN_vi       = 235,
     251             :     BUFFER_ATOMIC_AND_X2_OFFSET = 236,
     252             :     BUFFER_ATOMIC_AND_X2_OFFSET_RTN     = 237,
     253             :     BUFFER_ATOMIC_AND_X2_OFFSET_RTN_si  = 238,
     254             :     BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi  = 239,
     255             :     BUFFER_ATOMIC_AND_X2_OFFSET_si      = 240,
     256             :     BUFFER_ATOMIC_AND_X2_OFFSET_vi      = 241,
     257             :     BUFFER_ATOMIC_CMPSWAP_ADDR64        = 242,
     258             :     BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN    = 243,
     259             :     BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_si = 244,
     260             :     BUFFER_ATOMIC_CMPSWAP_ADDR64_si     = 245,
     261             :     BUFFER_ATOMIC_CMPSWAP_BOTHEN        = 246,
     262             :     BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN    = 247,
     263             :     BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_si = 248,
     264             :     BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi = 249,
     265             :     BUFFER_ATOMIC_CMPSWAP_BOTHEN_si     = 250,
     266             :     BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi     = 251,
     267             :     BUFFER_ATOMIC_CMPSWAP_IDXEN = 252,
     268             :     BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN     = 253,
     269             :     BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_si  = 254,
     270             :     BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi  = 255,
     271             :     BUFFER_ATOMIC_CMPSWAP_IDXEN_si      = 256,
     272             :     BUFFER_ATOMIC_CMPSWAP_IDXEN_vi      = 257,
     273             :     BUFFER_ATOMIC_CMPSWAP_OFFEN = 258,
     274             :     BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN     = 259,
     275             :     BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_si  = 260,
     276             :     BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi  = 261,
     277             :     BUFFER_ATOMIC_CMPSWAP_OFFEN_si      = 262,
     278             :     BUFFER_ATOMIC_CMPSWAP_OFFEN_vi      = 263,
     279             :     BUFFER_ATOMIC_CMPSWAP_OFFSET        = 264,
     280             :     BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN    = 265,
     281             :     BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_si = 266,
     282             :     BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi = 267,
     283             :     BUFFER_ATOMIC_CMPSWAP_OFFSET_si     = 268,
     284             :     BUFFER_ATOMIC_CMPSWAP_OFFSET_vi     = 269,
     285             :     BUFFER_ATOMIC_CMPSWAP_X2_ADDR64     = 270,
     286             :     BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN = 271,
     287             :     BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_si      = 272,
     288             :     BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_si  = 273,
     289             :     BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN     = 274,
     290             :     BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN = 275,
     291             :     BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_si      = 276,
     292             :     BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi      = 277,
     293             :     BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_si  = 278,
     294             :     BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi  = 279,
     295             :     BUFFER_ATOMIC_CMPSWAP_X2_IDXEN      = 280,
     296             :     BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN  = 281,
     297             :     BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_si       = 282,
     298             :     BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi       = 283,
     299             :     BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_si   = 284,
     300             :     BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi   = 285,
     301             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFEN      = 286,
     302             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN  = 287,
     303             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_si       = 288,
     304             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi       = 289,
     305             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_si   = 290,
     306             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi   = 291,
     307             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFSET     = 292,
     308             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN = 293,
     309             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_si      = 294,
     310             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi      = 295,
     311             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_si  = 296,
     312             :     BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi  = 297,
     313             :     BUFFER_ATOMIC_DEC_ADDR64    = 298,
     314             :     BUFFER_ATOMIC_DEC_ADDR64_RTN        = 299,
     315             :     BUFFER_ATOMIC_DEC_ADDR64_RTN_si     = 300,
     316             :     BUFFER_ATOMIC_DEC_ADDR64_si = 301,
     317             :     BUFFER_ATOMIC_DEC_BOTHEN    = 302,
     318             :     BUFFER_ATOMIC_DEC_BOTHEN_RTN        = 303,
     319             :     BUFFER_ATOMIC_DEC_BOTHEN_RTN_si     = 304,
     320             :     BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi     = 305,
     321             :     BUFFER_ATOMIC_DEC_BOTHEN_si = 306,
     322             :     BUFFER_ATOMIC_DEC_BOTHEN_vi = 307,
     323             :     BUFFER_ATOMIC_DEC_IDXEN     = 308,
     324             :     BUFFER_ATOMIC_DEC_IDXEN_RTN = 309,
     325             :     BUFFER_ATOMIC_DEC_IDXEN_RTN_si      = 310,
     326             :     BUFFER_ATOMIC_DEC_IDXEN_RTN_vi      = 311,
     327             :     BUFFER_ATOMIC_DEC_IDXEN_si  = 312,
     328             :     BUFFER_ATOMIC_DEC_IDXEN_vi  = 313,
     329             :     BUFFER_ATOMIC_DEC_OFFEN     = 314,
     330             :     BUFFER_ATOMIC_DEC_OFFEN_RTN = 315,
     331             :     BUFFER_ATOMIC_DEC_OFFEN_RTN_si      = 316,
     332             :     BUFFER_ATOMIC_DEC_OFFEN_RTN_vi      = 317,
     333             :     BUFFER_ATOMIC_DEC_OFFEN_si  = 318,
     334             :     BUFFER_ATOMIC_DEC_OFFEN_vi  = 319,
     335             :     BUFFER_ATOMIC_DEC_OFFSET    = 320,
     336             :     BUFFER_ATOMIC_DEC_OFFSET_RTN        = 321,
     337             :     BUFFER_ATOMIC_DEC_OFFSET_RTN_si     = 322,
     338             :     BUFFER_ATOMIC_DEC_OFFSET_RTN_vi     = 323,
     339             :     BUFFER_ATOMIC_DEC_OFFSET_si = 324,
     340             :     BUFFER_ATOMIC_DEC_OFFSET_vi = 325,
     341             :     BUFFER_ATOMIC_DEC_X2_ADDR64 = 326,
     342             :     BUFFER_ATOMIC_DEC_X2_ADDR64_RTN     = 327,
     343             :     BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_si  = 328,
     344             :     BUFFER_ATOMIC_DEC_X2_ADDR64_si      = 329,
     345             :     BUFFER_ATOMIC_DEC_X2_BOTHEN = 330,
     346             :     BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN     = 331,
     347             :     BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_si  = 332,
     348             :     BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi  = 333,
     349             :     BUFFER_ATOMIC_DEC_X2_BOTHEN_si      = 334,
     350             :     BUFFER_ATOMIC_DEC_X2_BOTHEN_vi      = 335,
     351             :     BUFFER_ATOMIC_DEC_X2_IDXEN  = 336,
     352             :     BUFFER_ATOMIC_DEC_X2_IDXEN_RTN      = 337,
     353             :     BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_si   = 338,
     354             :     BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi   = 339,
     355             :     BUFFER_ATOMIC_DEC_X2_IDXEN_si       = 340,
     356             :     BUFFER_ATOMIC_DEC_X2_IDXEN_vi       = 341,
     357             :     BUFFER_ATOMIC_DEC_X2_OFFEN  = 342,
     358             :     BUFFER_ATOMIC_DEC_X2_OFFEN_RTN      = 343,
     359             :     BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_si   = 344,
     360             :     BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi   = 345,
     361             :     BUFFER_ATOMIC_DEC_X2_OFFEN_si       = 346,
     362             :     BUFFER_ATOMIC_DEC_X2_OFFEN_vi       = 347,
     363             :     BUFFER_ATOMIC_DEC_X2_OFFSET = 348,
     364             :     BUFFER_ATOMIC_DEC_X2_OFFSET_RTN     = 349,
     365             :     BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_si  = 350,
     366             :     BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi  = 351,
     367             :     BUFFER_ATOMIC_DEC_X2_OFFSET_si      = 352,
     368             :     BUFFER_ATOMIC_DEC_X2_OFFSET_vi      = 353,
     369             :     BUFFER_ATOMIC_INC_ADDR64    = 354,
     370             :     BUFFER_ATOMIC_INC_ADDR64_RTN        = 355,
     371             :     BUFFER_ATOMIC_INC_ADDR64_RTN_si     = 356,
     372             :     BUFFER_ATOMIC_INC_ADDR64_si = 357,
     373             :     BUFFER_ATOMIC_INC_BOTHEN    = 358,
     374             :     BUFFER_ATOMIC_INC_BOTHEN_RTN        = 359,
     375             :     BUFFER_ATOMIC_INC_BOTHEN_RTN_si     = 360,
     376             :     BUFFER_ATOMIC_INC_BOTHEN_RTN_vi     = 361,
     377             :     BUFFER_ATOMIC_INC_BOTHEN_si = 362,
     378             :     BUFFER_ATOMIC_INC_BOTHEN_vi = 363,
     379             :     BUFFER_ATOMIC_INC_IDXEN     = 364,
     380             :     BUFFER_ATOMIC_INC_IDXEN_RTN = 365,
     381             :     BUFFER_ATOMIC_INC_IDXEN_RTN_si      = 366,
     382             :     BUFFER_ATOMIC_INC_IDXEN_RTN_vi      = 367,
     383             :     BUFFER_ATOMIC_INC_IDXEN_si  = 368,
     384             :     BUFFER_ATOMIC_INC_IDXEN_vi  = 369,
     385             :     BUFFER_ATOMIC_INC_OFFEN     = 370,
     386             :     BUFFER_ATOMIC_INC_OFFEN_RTN = 371,
     387             :     BUFFER_ATOMIC_INC_OFFEN_RTN_si      = 372,
     388             :     BUFFER_ATOMIC_INC_OFFEN_RTN_vi      = 373,
     389             :     BUFFER_ATOMIC_INC_OFFEN_si  = 374,
     390             :     BUFFER_ATOMIC_INC_OFFEN_vi  = 375,
     391             :     BUFFER_ATOMIC_INC_OFFSET    = 376,
     392             :     BUFFER_ATOMIC_INC_OFFSET_RTN        = 377,
     393             :     BUFFER_ATOMIC_INC_OFFSET_RTN_si     = 378,
     394             :     BUFFER_ATOMIC_INC_OFFSET_RTN_vi     = 379,
     395             :     BUFFER_ATOMIC_INC_OFFSET_si = 380,
     396             :     BUFFER_ATOMIC_INC_OFFSET_vi = 381,
     397             :     BUFFER_ATOMIC_INC_X2_ADDR64 = 382,
     398             :     BUFFER_ATOMIC_INC_X2_ADDR64_RTN     = 383,
     399             :     BUFFER_ATOMIC_INC_X2_ADDR64_RTN_si  = 384,
     400             :     BUFFER_ATOMIC_INC_X2_ADDR64_si      = 385,
     401             :     BUFFER_ATOMIC_INC_X2_BOTHEN = 386,
     402             :     BUFFER_ATOMIC_INC_X2_BOTHEN_RTN     = 387,
     403             :     BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_si  = 388,
     404             :     BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi  = 389,
     405             :     BUFFER_ATOMIC_INC_X2_BOTHEN_si      = 390,
     406             :     BUFFER_ATOMIC_INC_X2_BOTHEN_vi      = 391,
     407             :     BUFFER_ATOMIC_INC_X2_IDXEN  = 392,
     408             :     BUFFER_ATOMIC_INC_X2_IDXEN_RTN      = 393,
     409             :     BUFFER_ATOMIC_INC_X2_IDXEN_RTN_si   = 394,
     410             :     BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi   = 395,
     411             :     BUFFER_ATOMIC_INC_X2_IDXEN_si       = 396,
     412             :     BUFFER_ATOMIC_INC_X2_IDXEN_vi       = 397,
     413             :     BUFFER_ATOMIC_INC_X2_OFFEN  = 398,
     414             :     BUFFER_ATOMIC_INC_X2_OFFEN_RTN      = 399,
     415             :     BUFFER_ATOMIC_INC_X2_OFFEN_RTN_si   = 400,
     416             :     BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi   = 401,
     417             :     BUFFER_ATOMIC_INC_X2_OFFEN_si       = 402,
     418             :     BUFFER_ATOMIC_INC_X2_OFFEN_vi       = 403,
     419             :     BUFFER_ATOMIC_INC_X2_OFFSET = 404,
     420             :     BUFFER_ATOMIC_INC_X2_OFFSET_RTN     = 405,
     421             :     BUFFER_ATOMIC_INC_X2_OFFSET_RTN_si  = 406,
     422             :     BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi  = 407,
     423             :     BUFFER_ATOMIC_INC_X2_OFFSET_si      = 408,
     424             :     BUFFER_ATOMIC_INC_X2_OFFSET_vi      = 409,
     425             :     BUFFER_ATOMIC_OR_ADDR64     = 410,
     426             :     BUFFER_ATOMIC_OR_ADDR64_RTN = 411,
     427             :     BUFFER_ATOMIC_OR_ADDR64_RTN_si      = 412,
     428             :     BUFFER_ATOMIC_OR_ADDR64_si  = 413,
     429             :     BUFFER_ATOMIC_OR_BOTHEN     = 414,
     430             :     BUFFER_ATOMIC_OR_BOTHEN_RTN = 415,
     431             :     BUFFER_ATOMIC_OR_BOTHEN_RTN_si      = 416,
     432             :     BUFFER_ATOMIC_OR_BOTHEN_RTN_vi      = 417,
     433             :     BUFFER_ATOMIC_OR_BOTHEN_si  = 418,
     434             :     BUFFER_ATOMIC_OR_BOTHEN_vi  = 419,
     435             :     BUFFER_ATOMIC_OR_IDXEN      = 420,
     436             :     BUFFER_ATOMIC_OR_IDXEN_RTN  = 421,
     437             :     BUFFER_ATOMIC_OR_IDXEN_RTN_si       = 422,
     438             :     BUFFER_ATOMIC_OR_IDXEN_RTN_vi       = 423,
     439             :     BUFFER_ATOMIC_OR_IDXEN_si   = 424,
     440             :     BUFFER_ATOMIC_OR_IDXEN_vi   = 425,
     441             :     BUFFER_ATOMIC_OR_OFFEN      = 426,
     442             :     BUFFER_ATOMIC_OR_OFFEN_RTN  = 427,
     443             :     BUFFER_ATOMIC_OR_OFFEN_RTN_si       = 428,
     444             :     BUFFER_ATOMIC_OR_OFFEN_RTN_vi       = 429,
     445             :     BUFFER_ATOMIC_OR_OFFEN_si   = 430,
     446             :     BUFFER_ATOMIC_OR_OFFEN_vi   = 431,
     447             :     BUFFER_ATOMIC_OR_OFFSET     = 432,
     448             :     BUFFER_ATOMIC_OR_OFFSET_RTN = 433,
     449             :     BUFFER_ATOMIC_OR_OFFSET_RTN_si      = 434,
     450             :     BUFFER_ATOMIC_OR_OFFSET_RTN_vi      = 435,
     451             :     BUFFER_ATOMIC_OR_OFFSET_si  = 436,
     452             :     BUFFER_ATOMIC_OR_OFFSET_vi  = 437,
     453             :     BUFFER_ATOMIC_OR_X2_ADDR64  = 438,
     454             :     BUFFER_ATOMIC_OR_X2_ADDR64_RTN      = 439,
     455             :     BUFFER_ATOMIC_OR_X2_ADDR64_RTN_si   = 440,
     456             :     BUFFER_ATOMIC_OR_X2_ADDR64_si       = 441,
     457             :     BUFFER_ATOMIC_OR_X2_BOTHEN  = 442,
     458             :     BUFFER_ATOMIC_OR_X2_BOTHEN_RTN      = 443,
     459             :     BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_si   = 444,
     460             :     BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi   = 445,
     461             :     BUFFER_ATOMIC_OR_X2_BOTHEN_si       = 446,
     462             :     BUFFER_ATOMIC_OR_X2_BOTHEN_vi       = 447,
     463             :     BUFFER_ATOMIC_OR_X2_IDXEN   = 448,
     464             :     BUFFER_ATOMIC_OR_X2_IDXEN_RTN       = 449,
     465             :     BUFFER_ATOMIC_OR_X2_IDXEN_RTN_si    = 450,
     466             :     BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi    = 451,
     467             :     BUFFER_ATOMIC_OR_X2_IDXEN_si        = 452,
     468             :     BUFFER_ATOMIC_OR_X2_IDXEN_vi        = 453,
     469             :     BUFFER_ATOMIC_OR_X2_OFFEN   = 454,
     470             :     BUFFER_ATOMIC_OR_X2_OFFEN_RTN       = 455,
     471             :     BUFFER_ATOMIC_OR_X2_OFFEN_RTN_si    = 456,
     472             :     BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi    = 457,
     473             :     BUFFER_ATOMIC_OR_X2_OFFEN_si        = 458,
     474             :     BUFFER_ATOMIC_OR_X2_OFFEN_vi        = 459,
     475             :     BUFFER_ATOMIC_OR_X2_OFFSET  = 460,
     476             :     BUFFER_ATOMIC_OR_X2_OFFSET_RTN      = 461,
     477             :     BUFFER_ATOMIC_OR_X2_OFFSET_RTN_si   = 462,
     478             :     BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi   = 463,
     479             :     BUFFER_ATOMIC_OR_X2_OFFSET_si       = 464,
     480             :     BUFFER_ATOMIC_OR_X2_OFFSET_vi       = 465,
     481             :     BUFFER_ATOMIC_SMAX_ADDR64   = 466,
     482             :     BUFFER_ATOMIC_SMAX_ADDR64_RTN       = 467,
     483             :     BUFFER_ATOMIC_SMAX_ADDR64_RTN_si    = 468,
     484             :     BUFFER_ATOMIC_SMAX_ADDR64_si        = 469,
     485             :     BUFFER_ATOMIC_SMAX_BOTHEN   = 470,
     486             :     BUFFER_ATOMIC_SMAX_BOTHEN_RTN       = 471,
     487             :     BUFFER_ATOMIC_SMAX_BOTHEN_RTN_si    = 472,
     488             :     BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi    = 473,
     489             :     BUFFER_ATOMIC_SMAX_BOTHEN_si        = 474,
     490             :     BUFFER_ATOMIC_SMAX_BOTHEN_vi        = 475,
     491             :     BUFFER_ATOMIC_SMAX_IDXEN    = 476,
     492             :     BUFFER_ATOMIC_SMAX_IDXEN_RTN        = 477,
     493             :     BUFFER_ATOMIC_SMAX_IDXEN_RTN_si     = 478,
     494             :     BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi     = 479,
     495             :     BUFFER_ATOMIC_SMAX_IDXEN_si = 480,
     496             :     BUFFER_ATOMIC_SMAX_IDXEN_vi = 481,
     497             :     BUFFER_ATOMIC_SMAX_OFFEN    = 482,
     498             :     BUFFER_ATOMIC_SMAX_OFFEN_RTN        = 483,
     499             :     BUFFER_ATOMIC_SMAX_OFFEN_RTN_si     = 484,
     500             :     BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi     = 485,
     501             :     BUFFER_ATOMIC_SMAX_OFFEN_si = 486,
     502             :     BUFFER_ATOMIC_SMAX_OFFEN_vi = 487,
     503             :     BUFFER_ATOMIC_SMAX_OFFSET   = 488,
     504             :     BUFFER_ATOMIC_SMAX_OFFSET_RTN       = 489,
     505             :     BUFFER_ATOMIC_SMAX_OFFSET_RTN_si    = 490,
     506             :     BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi    = 491,
     507             :     BUFFER_ATOMIC_SMAX_OFFSET_si        = 492,
     508             :     BUFFER_ATOMIC_SMAX_OFFSET_vi        = 493,
     509             :     BUFFER_ATOMIC_SMAX_X2_ADDR64        = 494,
     510             :     BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN    = 495,
     511             :     BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_si = 496,
     512             :     BUFFER_ATOMIC_SMAX_X2_ADDR64_si     = 497,
     513             :     BUFFER_ATOMIC_SMAX_X2_BOTHEN        = 498,
     514             :     BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN    = 499,
     515             :     BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_si = 500,
     516             :     BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi = 501,
     517             :     BUFFER_ATOMIC_SMAX_X2_BOTHEN_si     = 502,
     518             :     BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi     = 503,
     519             :     BUFFER_ATOMIC_SMAX_X2_IDXEN = 504,
     520             :     BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN     = 505,
     521             :     BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_si  = 506,
     522             :     BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi  = 507,
     523             :     BUFFER_ATOMIC_SMAX_X2_IDXEN_si      = 508,
     524             :     BUFFER_ATOMIC_SMAX_X2_IDXEN_vi      = 509,
     525             :     BUFFER_ATOMIC_SMAX_X2_OFFEN = 510,
     526             :     BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN     = 511,
     527             :     BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_si  = 512,
     528             :     BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi  = 513,
     529             :     BUFFER_ATOMIC_SMAX_X2_OFFEN_si      = 514,
     530             :     BUFFER_ATOMIC_SMAX_X2_OFFEN_vi      = 515,
     531             :     BUFFER_ATOMIC_SMAX_X2_OFFSET        = 516,
     532             :     BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN    = 517,
     533             :     BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_si = 518,
     534             :     BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi = 519,
     535             :     BUFFER_ATOMIC_SMAX_X2_OFFSET_si     = 520,
     536             :     BUFFER_ATOMIC_SMAX_X2_OFFSET_vi     = 521,
     537             :     BUFFER_ATOMIC_SMIN_ADDR64   = 522,
     538             :     BUFFER_ATOMIC_SMIN_ADDR64_RTN       = 523,
     539             :     BUFFER_ATOMIC_SMIN_ADDR64_RTN_si    = 524,
     540             :     BUFFER_ATOMIC_SMIN_ADDR64_si        = 525,
     541             :     BUFFER_ATOMIC_SMIN_BOTHEN   = 526,
     542             :     BUFFER_ATOMIC_SMIN_BOTHEN_RTN       = 527,
     543             :     BUFFER_ATOMIC_SMIN_BOTHEN_RTN_si    = 528,
     544             :     BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi    = 529,
     545             :     BUFFER_ATOMIC_SMIN_BOTHEN_si        = 530,
     546             :     BUFFER_ATOMIC_SMIN_BOTHEN_vi        = 531,
     547             :     BUFFER_ATOMIC_SMIN_IDXEN    = 532,
     548             :     BUFFER_ATOMIC_SMIN_IDXEN_RTN        = 533,
     549             :     BUFFER_ATOMIC_SMIN_IDXEN_RTN_si     = 534,
     550             :     BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi     = 535,
     551             :     BUFFER_ATOMIC_SMIN_IDXEN_si = 536,
     552             :     BUFFER_ATOMIC_SMIN_IDXEN_vi = 537,
     553             :     BUFFER_ATOMIC_SMIN_OFFEN    = 538,
     554             :     BUFFER_ATOMIC_SMIN_OFFEN_RTN        = 539,
     555             :     BUFFER_ATOMIC_SMIN_OFFEN_RTN_si     = 540,
     556             :     BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi     = 541,
     557             :     BUFFER_ATOMIC_SMIN_OFFEN_si = 542,
     558             :     BUFFER_ATOMIC_SMIN_OFFEN_vi = 543,
     559             :     BUFFER_ATOMIC_SMIN_OFFSET   = 544,
     560             :     BUFFER_ATOMIC_SMIN_OFFSET_RTN       = 545,
     561             :     BUFFER_ATOMIC_SMIN_OFFSET_RTN_si    = 546,
     562             :     BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi    = 547,
     563             :     BUFFER_ATOMIC_SMIN_OFFSET_si        = 548,
     564             :     BUFFER_ATOMIC_SMIN_OFFSET_vi        = 549,
     565             :     BUFFER_ATOMIC_SMIN_X2_ADDR64        = 550,
     566             :     BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN    = 551,
     567             :     BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_si = 552,
     568             :     BUFFER_ATOMIC_SMIN_X2_ADDR64_si     = 553,
     569             :     BUFFER_ATOMIC_SMIN_X2_BOTHEN        = 554,
     570             :     BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN    = 555,
     571             :     BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_si = 556,
     572             :     BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi = 557,
     573             :     BUFFER_ATOMIC_SMIN_X2_BOTHEN_si     = 558,
     574             :     BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi     = 559,
     575             :     BUFFER_ATOMIC_SMIN_X2_IDXEN = 560,
     576             :     BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN     = 561,
     577             :     BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_si  = 562,
     578             :     BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi  = 563,
     579             :     BUFFER_ATOMIC_SMIN_X2_IDXEN_si      = 564,
     580             :     BUFFER_ATOMIC_SMIN_X2_IDXEN_vi      = 565,
     581             :     BUFFER_ATOMIC_SMIN_X2_OFFEN = 566,
     582             :     BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN     = 567,
     583             :     BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_si  = 568,
     584             :     BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi  = 569,
     585             :     BUFFER_ATOMIC_SMIN_X2_OFFEN_si      = 570,
     586             :     BUFFER_ATOMIC_SMIN_X2_OFFEN_vi      = 571,
     587             :     BUFFER_ATOMIC_SMIN_X2_OFFSET        = 572,
     588             :     BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN    = 573,
     589             :     BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_si = 574,
     590             :     BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi = 575,
     591             :     BUFFER_ATOMIC_SMIN_X2_OFFSET_si     = 576,
     592             :     BUFFER_ATOMIC_SMIN_X2_OFFSET_vi     = 577,
     593             :     BUFFER_ATOMIC_SUB_ADDR64    = 578,
     594             :     BUFFER_ATOMIC_SUB_ADDR64_RTN        = 579,
     595             :     BUFFER_ATOMIC_SUB_ADDR64_RTN_si     = 580,
     596             :     BUFFER_ATOMIC_SUB_ADDR64_si = 581,
     597             :     BUFFER_ATOMIC_SUB_BOTHEN    = 582,
     598             :     BUFFER_ATOMIC_SUB_BOTHEN_RTN        = 583,
     599             :     BUFFER_ATOMIC_SUB_BOTHEN_RTN_si     = 584,
     600             :     BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi     = 585,
     601             :     BUFFER_ATOMIC_SUB_BOTHEN_si = 586,
     602             :     BUFFER_ATOMIC_SUB_BOTHEN_vi = 587,
     603             :     BUFFER_ATOMIC_SUB_IDXEN     = 588,
     604             :     BUFFER_ATOMIC_SUB_IDXEN_RTN = 589,
     605             :     BUFFER_ATOMIC_SUB_IDXEN_RTN_si      = 590,
     606             :     BUFFER_ATOMIC_SUB_IDXEN_RTN_vi      = 591,
     607             :     BUFFER_ATOMIC_SUB_IDXEN_si  = 592,
     608             :     BUFFER_ATOMIC_SUB_IDXEN_vi  = 593,
     609             :     BUFFER_ATOMIC_SUB_OFFEN     = 594,
     610             :     BUFFER_ATOMIC_SUB_OFFEN_RTN = 595,
     611             :     BUFFER_ATOMIC_SUB_OFFEN_RTN_si      = 596,
     612             :     BUFFER_ATOMIC_SUB_OFFEN_RTN_vi      = 597,
     613             :     BUFFER_ATOMIC_SUB_OFFEN_si  = 598,
     614             :     BUFFER_ATOMIC_SUB_OFFEN_vi  = 599,
     615             :     BUFFER_ATOMIC_SUB_OFFSET    = 600,
     616             :     BUFFER_ATOMIC_SUB_OFFSET_RTN        = 601,
     617             :     BUFFER_ATOMIC_SUB_OFFSET_RTN_si     = 602,
     618             :     BUFFER_ATOMIC_SUB_OFFSET_RTN_vi     = 603,
     619             :     BUFFER_ATOMIC_SUB_OFFSET_si = 604,
     620             :     BUFFER_ATOMIC_SUB_OFFSET_vi = 605,
     621             :     BUFFER_ATOMIC_SUB_X2_ADDR64 = 606,
     622             :     BUFFER_ATOMIC_SUB_X2_ADDR64_RTN     = 607,
     623             :     BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_si  = 608,
     624             :     BUFFER_ATOMIC_SUB_X2_ADDR64_si      = 609,
     625             :     BUFFER_ATOMIC_SUB_X2_BOTHEN = 610,
     626             :     BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN     = 611,
     627             :     BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_si  = 612,
     628             :     BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi  = 613,
     629             :     BUFFER_ATOMIC_SUB_X2_BOTHEN_si      = 614,
     630             :     BUFFER_ATOMIC_SUB_X2_BOTHEN_vi      = 615,
     631             :     BUFFER_ATOMIC_SUB_X2_IDXEN  = 616,
     632             :     BUFFER_ATOMIC_SUB_X2_IDXEN_RTN      = 617,
     633             :     BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_si   = 618,
     634             :     BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi   = 619,
     635             :     BUFFER_ATOMIC_SUB_X2_IDXEN_si       = 620,
     636             :     BUFFER_ATOMIC_SUB_X2_IDXEN_vi       = 621,
     637             :     BUFFER_ATOMIC_SUB_X2_OFFEN  = 622,
     638             :     BUFFER_ATOMIC_SUB_X2_OFFEN_RTN      = 623,
     639             :     BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_si   = 624,
     640             :     BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi   = 625,
     641             :     BUFFER_ATOMIC_SUB_X2_OFFEN_si       = 626,
     642             :     BUFFER_ATOMIC_SUB_X2_OFFEN_vi       = 627,
     643             :     BUFFER_ATOMIC_SUB_X2_OFFSET = 628,
     644             :     BUFFER_ATOMIC_SUB_X2_OFFSET_RTN     = 629,
     645             :     BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_si  = 630,
     646             :     BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi  = 631,
     647             :     BUFFER_ATOMIC_SUB_X2_OFFSET_si      = 632,
     648             :     BUFFER_ATOMIC_SUB_X2_OFFSET_vi      = 633,
     649             :     BUFFER_ATOMIC_SWAP_ADDR64   = 634,
     650             :     BUFFER_ATOMIC_SWAP_ADDR64_RTN       = 635,
     651             :     BUFFER_ATOMIC_SWAP_ADDR64_RTN_si    = 636,
     652             :     BUFFER_ATOMIC_SWAP_ADDR64_si        = 637,
     653             :     BUFFER_ATOMIC_SWAP_BOTHEN   = 638,
     654             :     BUFFER_ATOMIC_SWAP_BOTHEN_RTN       = 639,
     655             :     BUFFER_ATOMIC_SWAP_BOTHEN_RTN_si    = 640,
     656             :     BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi    = 641,
     657             :     BUFFER_ATOMIC_SWAP_BOTHEN_si        = 642,
     658             :     BUFFER_ATOMIC_SWAP_BOTHEN_vi        = 643,
     659             :     BUFFER_ATOMIC_SWAP_IDXEN    = 644,
     660             :     BUFFER_ATOMIC_SWAP_IDXEN_RTN        = 645,
     661             :     BUFFER_ATOMIC_SWAP_IDXEN_RTN_si     = 646,
     662             :     BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi     = 647,
     663             :     BUFFER_ATOMIC_SWAP_IDXEN_si = 648,
     664             :     BUFFER_ATOMIC_SWAP_IDXEN_vi = 649,
     665             :     BUFFER_ATOMIC_SWAP_OFFEN    = 650,
     666             :     BUFFER_ATOMIC_SWAP_OFFEN_RTN        = 651,
     667             :     BUFFER_ATOMIC_SWAP_OFFEN_RTN_si     = 652,
     668             :     BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi     = 653,
     669             :     BUFFER_ATOMIC_SWAP_OFFEN_si = 654,
     670             :     BUFFER_ATOMIC_SWAP_OFFEN_vi = 655,
     671             :     BUFFER_ATOMIC_SWAP_OFFSET   = 656,
     672             :     BUFFER_ATOMIC_SWAP_OFFSET_RTN       = 657,
     673             :     BUFFER_ATOMIC_SWAP_OFFSET_RTN_si    = 658,
     674             :     BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi    = 659,
     675             :     BUFFER_ATOMIC_SWAP_OFFSET_si        = 660,
     676             :     BUFFER_ATOMIC_SWAP_OFFSET_vi        = 661,
     677             :     BUFFER_ATOMIC_SWAP_X2_ADDR64        = 662,
     678             :     BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN    = 663,
     679             :     BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_si = 664,
     680             :     BUFFER_ATOMIC_SWAP_X2_ADDR64_si     = 665,
     681             :     BUFFER_ATOMIC_SWAP_X2_BOTHEN        = 666,
     682             :     BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN    = 667,
     683             :     BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_si = 668,
     684             :     BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi = 669,
     685             :     BUFFER_ATOMIC_SWAP_X2_BOTHEN_si     = 670,
     686             :     BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi     = 671,
     687             :     BUFFER_ATOMIC_SWAP_X2_IDXEN = 672,
     688             :     BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN     = 673,
     689             :     BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_si  = 674,
     690             :     BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi  = 675,
     691             :     BUFFER_ATOMIC_SWAP_X2_IDXEN_si      = 676,
     692             :     BUFFER_ATOMIC_SWAP_X2_IDXEN_vi      = 677,
     693             :     BUFFER_ATOMIC_SWAP_X2_OFFEN = 678,
     694             :     BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN     = 679,
     695             :     BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_si  = 680,
     696             :     BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi  = 681,
     697             :     BUFFER_ATOMIC_SWAP_X2_OFFEN_si      = 682,
     698             :     BUFFER_ATOMIC_SWAP_X2_OFFEN_vi      = 683,
     699             :     BUFFER_ATOMIC_SWAP_X2_OFFSET        = 684,
     700             :     BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN    = 685,
     701             :     BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_si = 686,
     702             :     BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi = 687,
     703             :     BUFFER_ATOMIC_SWAP_X2_OFFSET_si     = 688,
     704             :     BUFFER_ATOMIC_SWAP_X2_OFFSET_vi     = 689,
     705             :     BUFFER_ATOMIC_UMAX_ADDR64   = 690,
     706             :     BUFFER_ATOMIC_UMAX_ADDR64_RTN       = 691,
     707             :     BUFFER_ATOMIC_UMAX_ADDR64_RTN_si    = 692,
     708             :     BUFFER_ATOMIC_UMAX_ADDR64_si        = 693,
     709             :     BUFFER_ATOMIC_UMAX_BOTHEN   = 694,
     710             :     BUFFER_ATOMIC_UMAX_BOTHEN_RTN       = 695,
     711             :     BUFFER_ATOMIC_UMAX_BOTHEN_RTN_si    = 696,
     712             :     BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi    = 697,
     713             :     BUFFER_ATOMIC_UMAX_BOTHEN_si        = 698,
     714             :     BUFFER_ATOMIC_UMAX_BOTHEN_vi        = 699,
     715             :     BUFFER_ATOMIC_UMAX_IDXEN    = 700,
     716             :     BUFFER_ATOMIC_UMAX_IDXEN_RTN        = 701,
     717             :     BUFFER_ATOMIC_UMAX_IDXEN_RTN_si     = 702,
     718             :     BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi     = 703,
     719             :     BUFFER_ATOMIC_UMAX_IDXEN_si = 704,
     720             :     BUFFER_ATOMIC_UMAX_IDXEN_vi = 705,
     721             :     BUFFER_ATOMIC_UMAX_OFFEN    = 706,
     722             :     BUFFER_ATOMIC_UMAX_OFFEN_RTN        = 707,
     723             :     BUFFER_ATOMIC_UMAX_OFFEN_RTN_si     = 708,
     724             :     BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi     = 709,
     725             :     BUFFER_ATOMIC_UMAX_OFFEN_si = 710,
     726             :     BUFFER_ATOMIC_UMAX_OFFEN_vi = 711,
     727             :     BUFFER_ATOMIC_UMAX_OFFSET   = 712,
     728             :     BUFFER_ATOMIC_UMAX_OFFSET_RTN       = 713,
     729             :     BUFFER_ATOMIC_UMAX_OFFSET_RTN_si    = 714,
     730             :     BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi    = 715,
     731             :     BUFFER_ATOMIC_UMAX_OFFSET_si        = 716,
     732             :     BUFFER_ATOMIC_UMAX_OFFSET_vi        = 717,
     733             :     BUFFER_ATOMIC_UMAX_X2_ADDR64        = 718,
     734             :     BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN    = 719,
     735             :     BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_si = 720,
     736             :     BUFFER_ATOMIC_UMAX_X2_ADDR64_si     = 721,
     737             :     BUFFER_ATOMIC_UMAX_X2_BOTHEN        = 722,
     738             :     BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN    = 723,
     739             :     BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_si = 724,
     740             :     BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi = 725,
     741             :     BUFFER_ATOMIC_UMAX_X2_BOTHEN_si     = 726,
     742             :     BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi     = 727,
     743             :     BUFFER_ATOMIC_UMAX_X2_IDXEN = 728,
     744             :     BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN     = 729,
     745             :     BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_si  = 730,
     746             :     BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi  = 731,
     747             :     BUFFER_ATOMIC_UMAX_X2_IDXEN_si      = 732,
     748             :     BUFFER_ATOMIC_UMAX_X2_IDXEN_vi      = 733,
     749             :     BUFFER_ATOMIC_UMAX_X2_OFFEN = 734,
     750             :     BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN     = 735,
     751             :     BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_si  = 736,
     752             :     BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi  = 737,
     753             :     BUFFER_ATOMIC_UMAX_X2_OFFEN_si      = 738,
     754             :     BUFFER_ATOMIC_UMAX_X2_OFFEN_vi      = 739,
     755             :     BUFFER_ATOMIC_UMAX_X2_OFFSET        = 740,
     756             :     BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN    = 741,
     757             :     BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_si = 742,
     758             :     BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi = 743,
     759             :     BUFFER_ATOMIC_UMAX_X2_OFFSET_si     = 744,
     760             :     BUFFER_ATOMIC_UMAX_X2_OFFSET_vi     = 745,
     761             :     BUFFER_ATOMIC_UMIN_ADDR64   = 746,
     762             :     BUFFER_ATOMIC_UMIN_ADDR64_RTN       = 747,
     763             :     BUFFER_ATOMIC_UMIN_ADDR64_RTN_si    = 748,
     764             :     BUFFER_ATOMIC_UMIN_ADDR64_si        = 749,
     765             :     BUFFER_ATOMIC_UMIN_BOTHEN   = 750,
     766             :     BUFFER_ATOMIC_UMIN_BOTHEN_RTN       = 751,
     767             :     BUFFER_ATOMIC_UMIN_BOTHEN_RTN_si    = 752,
     768             :     BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi    = 753,
     769             :     BUFFER_ATOMIC_UMIN_BOTHEN_si        = 754,
     770             :     BUFFER_ATOMIC_UMIN_BOTHEN_vi        = 755,
     771             :     BUFFER_ATOMIC_UMIN_IDXEN    = 756,
     772             :     BUFFER_ATOMIC_UMIN_IDXEN_RTN        = 757,
     773             :     BUFFER_ATOMIC_UMIN_IDXEN_RTN_si     = 758,
     774             :     BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi     = 759,
     775             :     BUFFER_ATOMIC_UMIN_IDXEN_si = 760,
     776             :     BUFFER_ATOMIC_UMIN_IDXEN_vi = 761,
     777             :     BUFFER_ATOMIC_UMIN_OFFEN    = 762,
     778             :     BUFFER_ATOMIC_UMIN_OFFEN_RTN        = 763,
     779             :     BUFFER_ATOMIC_UMIN_OFFEN_RTN_si     = 764,
     780             :     BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi     = 765,
     781             :     BUFFER_ATOMIC_UMIN_OFFEN_si = 766,
     782             :     BUFFER_ATOMIC_UMIN_OFFEN_vi = 767,
     783             :     BUFFER_ATOMIC_UMIN_OFFSET   = 768,
     784             :     BUFFER_ATOMIC_UMIN_OFFSET_RTN       = 769,
     785             :     BUFFER_ATOMIC_UMIN_OFFSET_RTN_si    = 770,
     786             :     BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi    = 771,
     787             :     BUFFER_ATOMIC_UMIN_OFFSET_si        = 772,
     788             :     BUFFER_ATOMIC_UMIN_OFFSET_vi        = 773,
     789             :     BUFFER_ATOMIC_UMIN_X2_ADDR64        = 774,
     790             :     BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN    = 775,
     791             :     BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_si = 776,
     792             :     BUFFER_ATOMIC_UMIN_X2_ADDR64_si     = 777,
     793             :     BUFFER_ATOMIC_UMIN_X2_BOTHEN        = 778,
     794             :     BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN    = 779,
     795             :     BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_si = 780,
     796             :     BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi = 781,
     797             :     BUFFER_ATOMIC_UMIN_X2_BOTHEN_si     = 782,
     798             :     BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi     = 783,
     799             :     BUFFER_ATOMIC_UMIN_X2_IDXEN = 784,
     800             :     BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN     = 785,
     801             :     BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_si  = 786,
     802             :     BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi  = 787,
     803             :     BUFFER_ATOMIC_UMIN_X2_IDXEN_si      = 788,
     804             :     BUFFER_ATOMIC_UMIN_X2_IDXEN_vi      = 789,
     805             :     BUFFER_ATOMIC_UMIN_X2_OFFEN = 790,
     806             :     BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN     = 791,
     807             :     BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_si  = 792,
     808             :     BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi  = 793,
     809             :     BUFFER_ATOMIC_UMIN_X2_OFFEN_si      = 794,
     810             :     BUFFER_ATOMIC_UMIN_X2_OFFEN_vi      = 795,
     811             :     BUFFER_ATOMIC_UMIN_X2_OFFSET        = 796,
     812             :     BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN    = 797,
     813             :     BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_si = 798,
     814             :     BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi = 799,
     815             :     BUFFER_ATOMIC_UMIN_X2_OFFSET_si     = 800,
     816             :     BUFFER_ATOMIC_UMIN_X2_OFFSET_vi     = 801,
     817             :     BUFFER_ATOMIC_XOR_ADDR64    = 802,
     818             :     BUFFER_ATOMIC_XOR_ADDR64_RTN        = 803,
     819             :     BUFFER_ATOMIC_XOR_ADDR64_RTN_si     = 804,
     820             :     BUFFER_ATOMIC_XOR_ADDR64_si = 805,
     821             :     BUFFER_ATOMIC_XOR_BOTHEN    = 806,
     822             :     BUFFER_ATOMIC_XOR_BOTHEN_RTN        = 807,
     823             :     BUFFER_ATOMIC_XOR_BOTHEN_RTN_si     = 808,
     824             :     BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi     = 809,
     825             :     BUFFER_ATOMIC_XOR_BOTHEN_si = 810,
     826             :     BUFFER_ATOMIC_XOR_BOTHEN_vi = 811,
     827             :     BUFFER_ATOMIC_XOR_IDXEN     = 812,
     828             :     BUFFER_ATOMIC_XOR_IDXEN_RTN = 813,
     829             :     BUFFER_ATOMIC_XOR_IDXEN_RTN_si      = 814,
     830             :     BUFFER_ATOMIC_XOR_IDXEN_RTN_vi      = 815,
     831             :     BUFFER_ATOMIC_XOR_IDXEN_si  = 816,
     832             :     BUFFER_ATOMIC_XOR_IDXEN_vi  = 817,
     833             :     BUFFER_ATOMIC_XOR_OFFEN     = 818,
     834             :     BUFFER_ATOMIC_XOR_OFFEN_RTN = 819,
     835             :     BUFFER_ATOMIC_XOR_OFFEN_RTN_si      = 820,
     836             :     BUFFER_ATOMIC_XOR_OFFEN_RTN_vi      = 821,
     837             :     BUFFER_ATOMIC_XOR_OFFEN_si  = 822,
     838             :     BUFFER_ATOMIC_XOR_OFFEN_vi  = 823,
     839             :     BUFFER_ATOMIC_XOR_OFFSET    = 824,
     840             :     BUFFER_ATOMIC_XOR_OFFSET_RTN        = 825,
     841             :     BUFFER_ATOMIC_XOR_OFFSET_RTN_si     = 826,
     842             :     BUFFER_ATOMIC_XOR_OFFSET_RTN_vi     = 827,
     843             :     BUFFER_ATOMIC_XOR_OFFSET_si = 828,
     844             :     BUFFER_ATOMIC_XOR_OFFSET_vi = 829,
     845             :     BUFFER_ATOMIC_XOR_X2_ADDR64 = 830,
     846             :     BUFFER_ATOMIC_XOR_X2_ADDR64_RTN     = 831,
     847             :     BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_si  = 832,
     848             :     BUFFER_ATOMIC_XOR_X2_ADDR64_si      = 833,
     849             :     BUFFER_ATOMIC_XOR_X2_BOTHEN = 834,
     850             :     BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN     = 835,
     851             :     BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_si  = 836,
     852             :     BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi  = 837,
     853             :     BUFFER_ATOMIC_XOR_X2_BOTHEN_si      = 838,
     854             :     BUFFER_ATOMIC_XOR_X2_BOTHEN_vi      = 839,
     855             :     BUFFER_ATOMIC_XOR_X2_IDXEN  = 840,
     856             :     BUFFER_ATOMIC_XOR_X2_IDXEN_RTN      = 841,
     857             :     BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_si   = 842,
     858             :     BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi   = 843,
     859             :     BUFFER_ATOMIC_XOR_X2_IDXEN_si       = 844,
     860             :     BUFFER_ATOMIC_XOR_X2_IDXEN_vi       = 845,
     861             :     BUFFER_ATOMIC_XOR_X2_OFFEN  = 846,
     862             :     BUFFER_ATOMIC_XOR_X2_OFFEN_RTN      = 847,
     863             :     BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_si   = 848,
     864             :     BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi   = 849,
     865             :     BUFFER_ATOMIC_XOR_X2_OFFEN_si       = 850,
     866             :     BUFFER_ATOMIC_XOR_X2_OFFEN_vi       = 851,
     867             :     BUFFER_ATOMIC_XOR_X2_OFFSET = 852,
     868             :     BUFFER_ATOMIC_XOR_X2_OFFSET_RTN     = 853,
     869             :     BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_si  = 854,
     870             :     BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi  = 855,
     871             :     BUFFER_ATOMIC_XOR_X2_OFFSET_si      = 856,
     872             :     BUFFER_ATOMIC_XOR_X2_OFFSET_vi      = 857,
     873             :     BUFFER_LOAD_DWORDX2_ADDR64  = 858,
     874             :     BUFFER_LOAD_DWORDX2_ADDR64_si       = 859,
     875             :     BUFFER_LOAD_DWORDX2_BOTHEN  = 860,
     876             :     BUFFER_LOAD_DWORDX2_BOTHEN_exact    = 861,
     877             :     BUFFER_LOAD_DWORDX2_BOTHEN_si       = 862,
     878             :     BUFFER_LOAD_DWORDX2_BOTHEN_vi       = 863,
     879             :     BUFFER_LOAD_DWORDX2_IDXEN   = 864,
     880             :     BUFFER_LOAD_DWORDX2_IDXEN_exact     = 865,
     881             :     BUFFER_LOAD_DWORDX2_IDXEN_si        = 866,
     882             :     BUFFER_LOAD_DWORDX2_IDXEN_vi        = 867,
     883             :     BUFFER_LOAD_DWORDX2_OFFEN   = 868,
     884             :     BUFFER_LOAD_DWORDX2_OFFEN_exact     = 869,
     885             :     BUFFER_LOAD_DWORDX2_OFFEN_si        = 870,
     886             :     BUFFER_LOAD_DWORDX2_OFFEN_vi        = 871,
     887             :     BUFFER_LOAD_DWORDX2_OFFSET  = 872,
     888             :     BUFFER_LOAD_DWORDX2_OFFSET_exact    = 873,
     889             :     BUFFER_LOAD_DWORDX2_OFFSET_si       = 874,
     890             :     BUFFER_LOAD_DWORDX2_OFFSET_vi       = 875,
     891             :     BUFFER_LOAD_DWORDX3_ADDR64  = 876,
     892             :     BUFFER_LOAD_DWORDX3_ADDR64_si       = 877,
     893             :     BUFFER_LOAD_DWORDX3_BOTHEN  = 878,
     894             :     BUFFER_LOAD_DWORDX3_BOTHEN_exact    = 879,
     895             :     BUFFER_LOAD_DWORDX3_BOTHEN_si       = 880,
     896             :     BUFFER_LOAD_DWORDX3_BOTHEN_vi       = 881,
     897             :     BUFFER_LOAD_DWORDX3_IDXEN   = 882,
     898             :     BUFFER_LOAD_DWORDX3_IDXEN_exact     = 883,
     899             :     BUFFER_LOAD_DWORDX3_IDXEN_si        = 884,
     900             :     BUFFER_LOAD_DWORDX3_IDXEN_vi        = 885,
     901             :     BUFFER_LOAD_DWORDX3_OFFEN   = 886,
     902             :     BUFFER_LOAD_DWORDX3_OFFEN_exact     = 887,
     903             :     BUFFER_LOAD_DWORDX3_OFFEN_si        = 888,
     904             :     BUFFER_LOAD_DWORDX3_OFFEN_vi        = 889,
     905             :     BUFFER_LOAD_DWORDX3_OFFSET  = 890,
     906             :     BUFFER_LOAD_DWORDX3_OFFSET_exact    = 891,
     907             :     BUFFER_LOAD_DWORDX3_OFFSET_si       = 892,
     908             :     BUFFER_LOAD_DWORDX3_OFFSET_vi       = 893,
     909             :     BUFFER_LOAD_DWORDX4_ADDR64  = 894,
     910             :     BUFFER_LOAD_DWORDX4_ADDR64_si       = 895,
     911             :     BUFFER_LOAD_DWORDX4_BOTHEN  = 896,
     912             :     BUFFER_LOAD_DWORDX4_BOTHEN_exact    = 897,
     913             :     BUFFER_LOAD_DWORDX4_BOTHEN_si       = 898,
     914             :     BUFFER_LOAD_DWORDX4_BOTHEN_vi       = 899,
     915             :     BUFFER_LOAD_DWORDX4_IDXEN   = 900,
     916             :     BUFFER_LOAD_DWORDX4_IDXEN_exact     = 901,
     917             :     BUFFER_LOAD_DWORDX4_IDXEN_si        = 902,
     918             :     BUFFER_LOAD_DWORDX4_IDXEN_vi        = 903,
     919             :     BUFFER_LOAD_DWORDX4_OFFEN   = 904,
     920             :     BUFFER_LOAD_DWORDX4_OFFEN_exact     = 905,
     921             :     BUFFER_LOAD_DWORDX4_OFFEN_si        = 906,
     922             :     BUFFER_LOAD_DWORDX4_OFFEN_vi        = 907,
     923             :     BUFFER_LOAD_DWORDX4_OFFSET  = 908,
     924             :     BUFFER_LOAD_DWORDX4_OFFSET_exact    = 909,
     925             :     BUFFER_LOAD_DWORDX4_OFFSET_si       = 910,
     926             :     BUFFER_LOAD_DWORDX4_OFFSET_vi       = 911,
     927             :     BUFFER_LOAD_DWORD_ADDR64    = 912,
     928             :     BUFFER_LOAD_DWORD_ADDR64_si = 913,
     929             :     BUFFER_LOAD_DWORD_BOTHEN    = 914,
     930             :     BUFFER_LOAD_DWORD_BOTHEN_exact      = 915,
     931             :     BUFFER_LOAD_DWORD_BOTHEN_si = 916,
     932             :     BUFFER_LOAD_DWORD_BOTHEN_vi = 917,
     933             :     BUFFER_LOAD_DWORD_IDXEN     = 918,
     934             :     BUFFER_LOAD_DWORD_IDXEN_exact       = 919,
     935             :     BUFFER_LOAD_DWORD_IDXEN_si  = 920,
     936             :     BUFFER_LOAD_DWORD_IDXEN_vi  = 921,
     937             :     BUFFER_LOAD_DWORD_OFFEN     = 922,
     938             :     BUFFER_LOAD_DWORD_OFFEN_exact       = 923,
     939             :     BUFFER_LOAD_DWORD_OFFEN_si  = 924,
     940             :     BUFFER_LOAD_DWORD_OFFEN_vi  = 925,
     941             :     BUFFER_LOAD_DWORD_OFFSET    = 926,
     942             :     BUFFER_LOAD_DWORD_OFFSET_exact      = 927,
     943             :     BUFFER_LOAD_DWORD_OFFSET_si = 928,
     944             :     BUFFER_LOAD_DWORD_OFFSET_vi = 929,
     945             :     BUFFER_LOAD_FORMAT_XYZW_ADDR64      = 930,
     946             :     BUFFER_LOAD_FORMAT_XYZW_ADDR64_si   = 931,
     947             :     BUFFER_LOAD_FORMAT_XYZW_BOTHEN      = 932,
     948             :     BUFFER_LOAD_FORMAT_XYZW_BOTHEN_exact        = 933,
     949             :     BUFFER_LOAD_FORMAT_XYZW_BOTHEN_si   = 934,
     950             :     BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi   = 935,
     951             :     BUFFER_LOAD_FORMAT_XYZW_IDXEN       = 936,
     952             :     BUFFER_LOAD_FORMAT_XYZW_IDXEN_exact = 937,
     953             :     BUFFER_LOAD_FORMAT_XYZW_IDXEN_si    = 938,
     954             :     BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi    = 939,
     955             :     BUFFER_LOAD_FORMAT_XYZW_OFFEN       = 940,
     956             :     BUFFER_LOAD_FORMAT_XYZW_OFFEN_exact = 941,
     957             :     BUFFER_LOAD_FORMAT_XYZW_OFFEN_si    = 942,
     958             :     BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi    = 943,
     959             :     BUFFER_LOAD_FORMAT_XYZW_OFFSET      = 944,
     960             :     BUFFER_LOAD_FORMAT_XYZW_OFFSET_exact        = 945,
     961             :     BUFFER_LOAD_FORMAT_XYZW_OFFSET_si   = 946,
     962             :     BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi   = 947,
     963             :     BUFFER_LOAD_FORMAT_XYZ_ADDR64       = 948,
     964             :     BUFFER_LOAD_FORMAT_XYZ_ADDR64_si    = 949,
     965             :     BUFFER_LOAD_FORMAT_XYZ_BOTHEN       = 950,
     966             :     BUFFER_LOAD_FORMAT_XYZ_BOTHEN_exact = 951,
     967             :     BUFFER_LOAD_FORMAT_XYZ_BOTHEN_si    = 952,
     968             :     BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi    = 953,
     969             :     BUFFER_LOAD_FORMAT_XYZ_IDXEN        = 954,
     970             :     BUFFER_LOAD_FORMAT_XYZ_IDXEN_exact  = 955,
     971             :     BUFFER_LOAD_FORMAT_XYZ_IDXEN_si     = 956,
     972             :     BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi     = 957,
     973             :     BUFFER_LOAD_FORMAT_XYZ_OFFEN        = 958,
     974             :     BUFFER_LOAD_FORMAT_XYZ_OFFEN_exact  = 959,
     975             :     BUFFER_LOAD_FORMAT_XYZ_OFFEN_si     = 960,
     976             :     BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi     = 961,
     977             :     BUFFER_LOAD_FORMAT_XYZ_OFFSET       = 962,
     978             :     BUFFER_LOAD_FORMAT_XYZ_OFFSET_exact = 963,
     979             :     BUFFER_LOAD_FORMAT_XYZ_OFFSET_si    = 964,
     980             :     BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi    = 965,
     981             :     BUFFER_LOAD_FORMAT_XY_ADDR64        = 966,
     982             :     BUFFER_LOAD_FORMAT_XY_ADDR64_si     = 967,
     983             :     BUFFER_LOAD_FORMAT_XY_BOTHEN        = 968,
     984             :     BUFFER_LOAD_FORMAT_XY_BOTHEN_exact  = 969,
     985             :     BUFFER_LOAD_FORMAT_XY_BOTHEN_si     = 970,
     986             :     BUFFER_LOAD_FORMAT_XY_BOTHEN_vi     = 971,
     987             :     BUFFER_LOAD_FORMAT_XY_IDXEN = 972,
     988             :     BUFFER_LOAD_FORMAT_XY_IDXEN_exact   = 973,
     989             :     BUFFER_LOAD_FORMAT_XY_IDXEN_si      = 974,
     990             :     BUFFER_LOAD_FORMAT_XY_IDXEN_vi      = 975,
     991             :     BUFFER_LOAD_FORMAT_XY_OFFEN = 976,
     992             :     BUFFER_LOAD_FORMAT_XY_OFFEN_exact   = 977,
     993             :     BUFFER_LOAD_FORMAT_XY_OFFEN_si      = 978,
     994             :     BUFFER_LOAD_FORMAT_XY_OFFEN_vi      = 979,
     995             :     BUFFER_LOAD_FORMAT_XY_OFFSET        = 980,
     996             :     BUFFER_LOAD_FORMAT_XY_OFFSET_exact  = 981,
     997             :     BUFFER_LOAD_FORMAT_XY_OFFSET_si     = 982,
     998             :     BUFFER_LOAD_FORMAT_XY_OFFSET_vi     = 983,
     999             :     BUFFER_LOAD_FORMAT_X_ADDR64 = 984,
    1000             :     BUFFER_LOAD_FORMAT_X_ADDR64_si      = 985,
    1001             :     BUFFER_LOAD_FORMAT_X_BOTHEN = 986,
    1002             :     BUFFER_LOAD_FORMAT_X_BOTHEN_exact   = 987,
    1003             :     BUFFER_LOAD_FORMAT_X_BOTHEN_si      = 988,
    1004             :     BUFFER_LOAD_FORMAT_X_BOTHEN_vi      = 989,
    1005             :     BUFFER_LOAD_FORMAT_X_IDXEN  = 990,
    1006             :     BUFFER_LOAD_FORMAT_X_IDXEN_exact    = 991,
    1007             :     BUFFER_LOAD_FORMAT_X_IDXEN_si       = 992,
    1008             :     BUFFER_LOAD_FORMAT_X_IDXEN_vi       = 993,
    1009             :     BUFFER_LOAD_FORMAT_X_OFFEN  = 994,
    1010             :     BUFFER_LOAD_FORMAT_X_OFFEN_exact    = 995,
    1011             :     BUFFER_LOAD_FORMAT_X_OFFEN_si       = 996,
    1012             :     BUFFER_LOAD_FORMAT_X_OFFEN_vi       = 997,
    1013             :     BUFFER_LOAD_FORMAT_X_OFFSET = 998,
    1014             :     BUFFER_LOAD_FORMAT_X_OFFSET_exact   = 999,
    1015             :     BUFFER_LOAD_FORMAT_X_OFFSET_si      = 1000,
    1016             :     BUFFER_LOAD_FORMAT_X_OFFSET_vi      = 1001,
    1017             :     BUFFER_LOAD_SBYTE_ADDR64    = 1002,
    1018             :     BUFFER_LOAD_SBYTE_ADDR64_si = 1003,
    1019             :     BUFFER_LOAD_SBYTE_BOTHEN    = 1004,
    1020             :     BUFFER_LOAD_SBYTE_BOTHEN_exact      = 1005,
    1021             :     BUFFER_LOAD_SBYTE_BOTHEN_si = 1006,
    1022             :     BUFFER_LOAD_SBYTE_BOTHEN_vi = 1007,
    1023             :     BUFFER_LOAD_SBYTE_D16_ADDR64        = 1008,
    1024             :     BUFFER_LOAD_SBYTE_D16_BOTHEN        = 1009,
    1025             :     BUFFER_LOAD_SBYTE_D16_BOTHEN_exact  = 1010,
    1026             :     BUFFER_LOAD_SBYTE_D16_BOTHEN_vi     = 1011,
    1027             :     BUFFER_LOAD_SBYTE_D16_HI_ADDR64     = 1012,
    1028             :     BUFFER_LOAD_SBYTE_D16_HI_BOTHEN     = 1013,
    1029             :     BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_exact       = 1014,
    1030             :     BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi  = 1015,
    1031             :     BUFFER_LOAD_SBYTE_D16_HI_IDXEN      = 1016,
    1032             :     BUFFER_LOAD_SBYTE_D16_HI_IDXEN_exact        = 1017,
    1033             :     BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi   = 1018,
    1034             :     BUFFER_LOAD_SBYTE_D16_HI_OFFEN      = 1019,
    1035             :     BUFFER_LOAD_SBYTE_D16_HI_OFFEN_exact        = 1020,
    1036             :     BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi   = 1021,
    1037             :     BUFFER_LOAD_SBYTE_D16_HI_OFFSET     = 1022,
    1038             :     BUFFER_LOAD_SBYTE_D16_HI_OFFSET_exact       = 1023,
    1039             :     BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi  = 1024,
    1040             :     BUFFER_LOAD_SBYTE_D16_IDXEN = 1025,
    1041             :     BUFFER_LOAD_SBYTE_D16_IDXEN_exact   = 1026,
    1042             :     BUFFER_LOAD_SBYTE_D16_IDXEN_vi      = 1027,
    1043             :     BUFFER_LOAD_SBYTE_D16_OFFEN = 1028,
    1044             :     BUFFER_LOAD_SBYTE_D16_OFFEN_exact   = 1029,
    1045             :     BUFFER_LOAD_SBYTE_D16_OFFEN_vi      = 1030,
    1046             :     BUFFER_LOAD_SBYTE_D16_OFFSET        = 1031,
    1047             :     BUFFER_LOAD_SBYTE_D16_OFFSET_exact  = 1032,
    1048             :     BUFFER_LOAD_SBYTE_D16_OFFSET_vi     = 1033,
    1049             :     BUFFER_LOAD_SBYTE_IDXEN     = 1034,
    1050             :     BUFFER_LOAD_SBYTE_IDXEN_exact       = 1035,
    1051             :     BUFFER_LOAD_SBYTE_IDXEN_si  = 1036,
    1052             :     BUFFER_LOAD_SBYTE_IDXEN_vi  = 1037,
    1053             :     BUFFER_LOAD_SBYTE_OFFEN     = 1038,
    1054             :     BUFFER_LOAD_SBYTE_OFFEN_exact       = 1039,
    1055             :     BUFFER_LOAD_SBYTE_OFFEN_si  = 1040,
    1056             :     BUFFER_LOAD_SBYTE_OFFEN_vi  = 1041,
    1057             :     BUFFER_LOAD_SBYTE_OFFSET    = 1042,
    1058             :     BUFFER_LOAD_SBYTE_OFFSET_exact      = 1043,
    1059             :     BUFFER_LOAD_SBYTE_OFFSET_si = 1044,
    1060             :     BUFFER_LOAD_SBYTE_OFFSET_vi = 1045,
    1061             :     BUFFER_LOAD_SHORT_D16_ADDR64        = 1046,
    1062             :     BUFFER_LOAD_SHORT_D16_BOTHEN        = 1047,
    1063             :     BUFFER_LOAD_SHORT_D16_BOTHEN_exact  = 1048,
    1064             :     BUFFER_LOAD_SHORT_D16_BOTHEN_vi     = 1049,
    1065             :     BUFFER_LOAD_SHORT_D16_HI_ADDR64     = 1050,
    1066             :     BUFFER_LOAD_SHORT_D16_HI_BOTHEN     = 1051,
    1067             :     BUFFER_LOAD_SHORT_D16_HI_BOTHEN_exact       = 1052,
    1068             :     BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi  = 1053,
    1069             :     BUFFER_LOAD_SHORT_D16_HI_IDXEN      = 1054,
    1070             :     BUFFER_LOAD_SHORT_D16_HI_IDXEN_exact        = 1055,
    1071             :     BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi   = 1056,
    1072             :     BUFFER_LOAD_SHORT_D16_HI_OFFEN      = 1057,
    1073             :     BUFFER_LOAD_SHORT_D16_HI_OFFEN_exact        = 1058,
    1074             :     BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi   = 1059,
    1075             :     BUFFER_LOAD_SHORT_D16_HI_OFFSET     = 1060,
    1076             :     BUFFER_LOAD_SHORT_D16_HI_OFFSET_exact       = 1061,
    1077             :     BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi  = 1062,
    1078             :     BUFFER_LOAD_SHORT_D16_IDXEN = 1063,
    1079             :     BUFFER_LOAD_SHORT_D16_IDXEN_exact   = 1064,
    1080             :     BUFFER_LOAD_SHORT_D16_IDXEN_vi      = 1065,
    1081             :     BUFFER_LOAD_SHORT_D16_OFFEN = 1066,
    1082             :     BUFFER_LOAD_SHORT_D16_OFFEN_exact   = 1067,
    1083             :     BUFFER_LOAD_SHORT_D16_OFFEN_vi      = 1068,
    1084             :     BUFFER_LOAD_SHORT_D16_OFFSET        = 1069,
    1085             :     BUFFER_LOAD_SHORT_D16_OFFSET_exact  = 1070,
    1086             :     BUFFER_LOAD_SHORT_D16_OFFSET_vi     = 1071,
    1087             :     BUFFER_LOAD_SSHORT_ADDR64   = 1072,
    1088             :     BUFFER_LOAD_SSHORT_ADDR64_si        = 1073,
    1089             :     BUFFER_LOAD_SSHORT_BOTHEN   = 1074,
    1090             :     BUFFER_LOAD_SSHORT_BOTHEN_exact     = 1075,
    1091             :     BUFFER_LOAD_SSHORT_BOTHEN_si        = 1076,
    1092             :     BUFFER_LOAD_SSHORT_BOTHEN_vi        = 1077,
    1093             :     BUFFER_LOAD_SSHORT_IDXEN    = 1078,
    1094             :     BUFFER_LOAD_SSHORT_IDXEN_exact      = 1079,
    1095             :     BUFFER_LOAD_SSHORT_IDXEN_si = 1080,
    1096             :     BUFFER_LOAD_SSHORT_IDXEN_vi = 1081,
    1097             :     BUFFER_LOAD_SSHORT_OFFEN    = 1082,
    1098             :     BUFFER_LOAD_SSHORT_OFFEN_exact      = 1083,
    1099             :     BUFFER_LOAD_SSHORT_OFFEN_si = 1084,
    1100             :     BUFFER_LOAD_SSHORT_OFFEN_vi = 1085,
    1101             :     BUFFER_LOAD_SSHORT_OFFSET   = 1086,
    1102             :     BUFFER_LOAD_SSHORT_OFFSET_exact     = 1087,
    1103             :     BUFFER_LOAD_SSHORT_OFFSET_si        = 1088,
    1104             :     BUFFER_LOAD_SSHORT_OFFSET_vi        = 1089,
    1105             :     BUFFER_LOAD_UBYTE_ADDR64    = 1090,
    1106             :     BUFFER_LOAD_UBYTE_ADDR64_si = 1091,
    1107             :     BUFFER_LOAD_UBYTE_BOTHEN    = 1092,
    1108             :     BUFFER_LOAD_UBYTE_BOTHEN_exact      = 1093,
    1109             :     BUFFER_LOAD_UBYTE_BOTHEN_si = 1094,
    1110             :     BUFFER_LOAD_UBYTE_BOTHEN_vi = 1095,
    1111             :     BUFFER_LOAD_UBYTE_D16_ADDR64        = 1096,
    1112             :     BUFFER_LOAD_UBYTE_D16_BOTHEN        = 1097,
    1113             :     BUFFER_LOAD_UBYTE_D16_BOTHEN_exact  = 1098,
    1114             :     BUFFER_LOAD_UBYTE_D16_BOTHEN_vi     = 1099,
    1115             :     BUFFER_LOAD_UBYTE_D16_HI_ADDR64     = 1100,
    1116             :     BUFFER_LOAD_UBYTE_D16_HI_BOTHEN     = 1101,
    1117             :     BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_exact       = 1102,
    1118             :     BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi  = 1103,
    1119             :     BUFFER_LOAD_UBYTE_D16_HI_IDXEN      = 1104,
    1120             :     BUFFER_LOAD_UBYTE_D16_HI_IDXEN_exact        = 1105,
    1121             :     BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi   = 1106,
    1122             :     BUFFER_LOAD_UBYTE_D16_HI_OFFEN      = 1107,
    1123             :     BUFFER_LOAD_UBYTE_D16_HI_OFFEN_exact        = 1108,
    1124             :     BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi   = 1109,
    1125             :     BUFFER_LOAD_UBYTE_D16_HI_OFFSET     = 1110,
    1126             :     BUFFER_LOAD_UBYTE_D16_HI_OFFSET_exact       = 1111,
    1127             :     BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi  = 1112,
    1128             :     BUFFER_LOAD_UBYTE_D16_IDXEN = 1113,
    1129             :     BUFFER_LOAD_UBYTE_D16_IDXEN_exact   = 1114,
    1130             :     BUFFER_LOAD_UBYTE_D16_IDXEN_vi      = 1115,
    1131             :     BUFFER_LOAD_UBYTE_D16_OFFEN = 1116,
    1132             :     BUFFER_LOAD_UBYTE_D16_OFFEN_exact   = 1117,
    1133             :     BUFFER_LOAD_UBYTE_D16_OFFEN_vi      = 1118,
    1134             :     BUFFER_LOAD_UBYTE_D16_OFFSET        = 1119,
    1135             :     BUFFER_LOAD_UBYTE_D16_OFFSET_exact  = 1120,
    1136             :     BUFFER_LOAD_UBYTE_D16_OFFSET_vi     = 1121,
    1137             :     BUFFER_LOAD_UBYTE_IDXEN     = 1122,
    1138             :     BUFFER_LOAD_UBYTE_IDXEN_exact       = 1123,
    1139             :     BUFFER_LOAD_UBYTE_IDXEN_si  = 1124,
    1140             :     BUFFER_LOAD_UBYTE_IDXEN_vi  = 1125,
    1141             :     BUFFER_LOAD_UBYTE_OFFEN     = 1126,
    1142             :     BUFFER_LOAD_UBYTE_OFFEN_exact       = 1127,
    1143             :     BUFFER_LOAD_UBYTE_OFFEN_si  = 1128,
    1144             :     BUFFER_LOAD_UBYTE_OFFEN_vi  = 1129,
    1145             :     BUFFER_LOAD_UBYTE_OFFSET    = 1130,
    1146             :     BUFFER_LOAD_UBYTE_OFFSET_exact      = 1131,
    1147             :     BUFFER_LOAD_UBYTE_OFFSET_si = 1132,
    1148             :     BUFFER_LOAD_UBYTE_OFFSET_vi = 1133,
    1149             :     BUFFER_LOAD_USHORT_ADDR64   = 1134,
    1150             :     BUFFER_LOAD_USHORT_ADDR64_si        = 1135,
    1151             :     BUFFER_LOAD_USHORT_BOTHEN   = 1136,
    1152             :     BUFFER_LOAD_USHORT_BOTHEN_exact     = 1137,
    1153             :     BUFFER_LOAD_USHORT_BOTHEN_si        = 1138,
    1154             :     BUFFER_LOAD_USHORT_BOTHEN_vi        = 1139,
    1155             :     BUFFER_LOAD_USHORT_IDXEN    = 1140,
    1156             :     BUFFER_LOAD_USHORT_IDXEN_exact      = 1141,
    1157             :     BUFFER_LOAD_USHORT_IDXEN_si = 1142,
    1158             :     BUFFER_LOAD_USHORT_IDXEN_vi = 1143,
    1159             :     BUFFER_LOAD_USHORT_OFFEN    = 1144,
    1160             :     BUFFER_LOAD_USHORT_OFFEN_exact      = 1145,
    1161             :     BUFFER_LOAD_USHORT_OFFEN_si = 1146,
    1162             :     BUFFER_LOAD_USHORT_OFFEN_vi = 1147,
    1163             :     BUFFER_LOAD_USHORT_OFFSET   = 1148,
    1164             :     BUFFER_LOAD_USHORT_OFFSET_exact     = 1149,
    1165             :     BUFFER_LOAD_USHORT_OFFSET_si        = 1150,
    1166             :     BUFFER_LOAD_USHORT_OFFSET_vi        = 1151,
    1167             :     BUFFER_STORE_BYTE_ADDR64    = 1152,
    1168             :     BUFFER_STORE_BYTE_ADDR64_si = 1153,
    1169             :     BUFFER_STORE_BYTE_BOTHEN    = 1154,
    1170             :     BUFFER_STORE_BYTE_BOTHEN_exact      = 1155,
    1171             :     BUFFER_STORE_BYTE_BOTHEN_si = 1156,
    1172             :     BUFFER_STORE_BYTE_BOTHEN_vi = 1157,
    1173             :     BUFFER_STORE_BYTE_D16_HI_ADDR64     = 1158,
    1174             :     BUFFER_STORE_BYTE_D16_HI_BOTHEN     = 1159,
    1175             :     BUFFER_STORE_BYTE_D16_HI_BOTHEN_exact       = 1160,
    1176             :     BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi  = 1161,
    1177             :     BUFFER_STORE_BYTE_D16_HI_IDXEN      = 1162,
    1178             :     BUFFER_STORE_BYTE_D16_HI_IDXEN_exact        = 1163,
    1179             :     BUFFER_STORE_BYTE_D16_HI_IDXEN_vi   = 1164,
    1180             :     BUFFER_STORE_BYTE_D16_HI_OFFEN      = 1165,
    1181             :     BUFFER_STORE_BYTE_D16_HI_OFFEN_exact        = 1166,
    1182             :     BUFFER_STORE_BYTE_D16_HI_OFFEN_vi   = 1167,
    1183             :     BUFFER_STORE_BYTE_D16_HI_OFFSET     = 1168,
    1184             :     BUFFER_STORE_BYTE_D16_HI_OFFSET_exact       = 1169,
    1185             :     BUFFER_STORE_BYTE_D16_HI_OFFSET_vi  = 1170,
    1186             :     BUFFER_STORE_BYTE_IDXEN     = 1171,
    1187             :     BUFFER_STORE_BYTE_IDXEN_exact       = 1172,
    1188             :     BUFFER_STORE_BYTE_IDXEN_si  = 1173,
    1189             :     BUFFER_STORE_BYTE_IDXEN_vi  = 1174,
    1190             :     BUFFER_STORE_BYTE_OFFEN     = 1175,
    1191             :     BUFFER_STORE_BYTE_OFFEN_exact       = 1176,
    1192             :     BUFFER_STORE_BYTE_OFFEN_si  = 1177,
    1193             :     BUFFER_STORE_BYTE_OFFEN_vi  = 1178,
    1194             :     BUFFER_STORE_BYTE_OFFSET    = 1179,
    1195             :     BUFFER_STORE_BYTE_OFFSET_exact      = 1180,
    1196             :     BUFFER_STORE_BYTE_OFFSET_si = 1181,
    1197             :     BUFFER_STORE_BYTE_OFFSET_vi = 1182,
    1198             :     BUFFER_STORE_DWORDX2_ADDR64 = 1183,
    1199             :     BUFFER_STORE_DWORDX2_ADDR64_si      = 1184,
    1200             :     BUFFER_STORE_DWORDX2_BOTHEN = 1185,
    1201             :     BUFFER_STORE_DWORDX2_BOTHEN_exact   = 1186,
    1202             :     BUFFER_STORE_DWORDX2_BOTHEN_si      = 1187,
    1203             :     BUFFER_STORE_DWORDX2_BOTHEN_vi      = 1188,
    1204             :     BUFFER_STORE_DWORDX2_IDXEN  = 1189,
    1205             :     BUFFER_STORE_DWORDX2_IDXEN_exact    = 1190,
    1206             :     BUFFER_STORE_DWORDX2_IDXEN_si       = 1191,
    1207             :     BUFFER_STORE_DWORDX2_IDXEN_vi       = 1192,
    1208             :     BUFFER_STORE_DWORDX2_OFFEN  = 1193,
    1209             :     BUFFER_STORE_DWORDX2_OFFEN_exact    = 1194,
    1210             :     BUFFER_STORE_DWORDX2_OFFEN_si       = 1195,
    1211             :     BUFFER_STORE_DWORDX2_OFFEN_vi       = 1196,
    1212             :     BUFFER_STORE_DWORDX2_OFFSET = 1197,
    1213             :     BUFFER_STORE_DWORDX2_OFFSET_exact   = 1198,
    1214             :     BUFFER_STORE_DWORDX2_OFFSET_si      = 1199,
    1215             :     BUFFER_STORE_DWORDX2_OFFSET_vi      = 1200,
    1216             :     BUFFER_STORE_DWORDX3_ADDR64 = 1201,
    1217             :     BUFFER_STORE_DWORDX3_ADDR64_si      = 1202,
    1218             :     BUFFER_STORE_DWORDX3_BOTHEN = 1203,
    1219             :     BUFFER_STORE_DWORDX3_BOTHEN_exact   = 1204,
    1220             :     BUFFER_STORE_DWORDX3_BOTHEN_si      = 1205,
    1221             :     BUFFER_STORE_DWORDX3_BOTHEN_vi      = 1206,
    1222             :     BUFFER_STORE_DWORDX3_IDXEN  = 1207,
    1223             :     BUFFER_STORE_DWORDX3_IDXEN_exact    = 1208,
    1224             :     BUFFER_STORE_DWORDX3_IDXEN_si       = 1209,
    1225             :     BUFFER_STORE_DWORDX3_IDXEN_vi       = 1210,
    1226             :     BUFFER_STORE_DWORDX3_OFFEN  = 1211,
    1227             :     BUFFER_STORE_DWORDX3_OFFEN_exact    = 1212,
    1228             :     BUFFER_STORE_DWORDX3_OFFEN_si       = 1213,
    1229             :     BUFFER_STORE_DWORDX3_OFFEN_vi       = 1214,
    1230             :     BUFFER_STORE_DWORDX3_OFFSET = 1215,
    1231             :     BUFFER_STORE_DWORDX3_OFFSET_exact   = 1216,
    1232             :     BUFFER_STORE_DWORDX3_OFFSET_si      = 1217,
    1233             :     BUFFER_STORE_DWORDX3_OFFSET_vi      = 1218,
    1234             :     BUFFER_STORE_DWORDX4_ADDR64 = 1219,
    1235             :     BUFFER_STORE_DWORDX4_ADDR64_si      = 1220,
    1236             :     BUFFER_STORE_DWORDX4_BOTHEN = 1221,
    1237             :     BUFFER_STORE_DWORDX4_BOTHEN_exact   = 1222,
    1238             :     BUFFER_STORE_DWORDX4_BOTHEN_si      = 1223,
    1239             :     BUFFER_STORE_DWORDX4_BOTHEN_vi      = 1224,
    1240             :     BUFFER_STORE_DWORDX4_IDXEN  = 1225,
    1241             :     BUFFER_STORE_DWORDX4_IDXEN_exact    = 1226,
    1242             :     BUFFER_STORE_DWORDX4_IDXEN_si       = 1227,
    1243             :     BUFFER_STORE_DWORDX4_IDXEN_vi       = 1228,
    1244             :     BUFFER_STORE_DWORDX4_OFFEN  = 1229,
    1245             :     BUFFER_STORE_DWORDX4_OFFEN_exact    = 1230,
    1246             :     BUFFER_STORE_DWORDX4_OFFEN_si       = 1231,
    1247             :     BUFFER_STORE_DWORDX4_OFFEN_vi       = 1232,
    1248             :     BUFFER_STORE_DWORDX4_OFFSET = 1233,
    1249             :     BUFFER_STORE_DWORDX4_OFFSET_exact   = 1234,
    1250             :     BUFFER_STORE_DWORDX4_OFFSET_si      = 1235,
    1251             :     BUFFER_STORE_DWORDX4_OFFSET_vi      = 1236,
    1252             :     BUFFER_STORE_DWORD_ADDR64   = 1237,
    1253             :     BUFFER_STORE_DWORD_ADDR64_si        = 1238,
    1254             :     BUFFER_STORE_DWORD_BOTHEN   = 1239,
    1255             :     BUFFER_STORE_DWORD_BOTHEN_exact     = 1240,
    1256             :     BUFFER_STORE_DWORD_BOTHEN_si        = 1241,
    1257             :     BUFFER_STORE_DWORD_BOTHEN_vi        = 1242,
    1258             :     BUFFER_STORE_DWORD_IDXEN    = 1243,
    1259             :     BUFFER_STORE_DWORD_IDXEN_exact      = 1244,
    1260             :     BUFFER_STORE_DWORD_IDXEN_si = 1245,
    1261             :     BUFFER_STORE_DWORD_IDXEN_vi = 1246,
    1262             :     BUFFER_STORE_DWORD_OFFEN    = 1247,
    1263             :     BUFFER_STORE_DWORD_OFFEN_exact      = 1248,
    1264             :     BUFFER_STORE_DWORD_OFFEN_si = 1249,
    1265             :     BUFFER_STORE_DWORD_OFFEN_vi = 1250,
    1266             :     BUFFER_STORE_DWORD_OFFSET   = 1251,
    1267             :     BUFFER_STORE_DWORD_OFFSET_exact     = 1252,
    1268             :     BUFFER_STORE_DWORD_OFFSET_si        = 1253,
    1269             :     BUFFER_STORE_DWORD_OFFSET_vi        = 1254,
    1270             :     BUFFER_STORE_FORMAT_XYZW_ADDR64     = 1255,
    1271             :     BUFFER_STORE_FORMAT_XYZW_ADDR64_si  = 1256,
    1272             :     BUFFER_STORE_FORMAT_XYZW_BOTHEN     = 1257,
    1273             :     BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact       = 1258,
    1274             :     BUFFER_STORE_FORMAT_XYZW_BOTHEN_si  = 1259,
    1275             :     BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi  = 1260,
    1276             :     BUFFER_STORE_FORMAT_XYZW_IDXEN      = 1261,
    1277             :     BUFFER_STORE_FORMAT_XYZW_IDXEN_exact        = 1262,
    1278             :     BUFFER_STORE_FORMAT_XYZW_IDXEN_si   = 1263,
    1279             :     BUFFER_STORE_FORMAT_XYZW_IDXEN_vi   = 1264,
    1280             :     BUFFER_STORE_FORMAT_XYZW_OFFEN      = 1265,
    1281             :     BUFFER_STORE_FORMAT_XYZW_OFFEN_exact        = 1266,
    1282             :     BUFFER_STORE_FORMAT_XYZW_OFFEN_si   = 1267,
    1283             :     BUFFER_STORE_FORMAT_XYZW_OFFEN_vi   = 1268,
    1284             :     BUFFER_STORE_FORMAT_XYZW_OFFSET     = 1269,
    1285             :     BUFFER_STORE_FORMAT_XYZW_OFFSET_exact       = 1270,
    1286             :     BUFFER_STORE_FORMAT_XYZW_OFFSET_si  = 1271,
    1287             :     BUFFER_STORE_FORMAT_XYZW_OFFSET_vi  = 1272,
    1288             :     BUFFER_STORE_FORMAT_XYZ_ADDR64      = 1273,
    1289             :     BUFFER_STORE_FORMAT_XYZ_ADDR64_si   = 1274,
    1290             :     BUFFER_STORE_FORMAT_XYZ_BOTHEN      = 1275,
    1291             :     BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact        = 1276,
    1292             :     BUFFER_STORE_FORMAT_XYZ_BOTHEN_si   = 1277,
    1293             :     BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi   = 1278,
    1294             :     BUFFER_STORE_FORMAT_XYZ_IDXEN       = 1279,
    1295             :     BUFFER_STORE_FORMAT_XYZ_IDXEN_exact = 1280,
    1296             :     BUFFER_STORE_FORMAT_XYZ_IDXEN_si    = 1281,
    1297             :     BUFFER_STORE_FORMAT_XYZ_IDXEN_vi    = 1282,
    1298             :     BUFFER_STORE_FORMAT_XYZ_OFFEN       = 1283,
    1299             :     BUFFER_STORE_FORMAT_XYZ_OFFEN_exact = 1284,
    1300             :     BUFFER_STORE_FORMAT_XYZ_OFFEN_si    = 1285,
    1301             :     BUFFER_STORE_FORMAT_XYZ_OFFEN_vi    = 1286,
    1302             :     BUFFER_STORE_FORMAT_XYZ_OFFSET      = 1287,
    1303             :     BUFFER_STORE_FORMAT_XYZ_OFFSET_exact        = 1288,
    1304             :     BUFFER_STORE_FORMAT_XYZ_OFFSET_si   = 1289,
    1305             :     BUFFER_STORE_FORMAT_XYZ_OFFSET_vi   = 1290,
    1306             :     BUFFER_STORE_FORMAT_XY_ADDR64       = 1291,
    1307             :     BUFFER_STORE_FORMAT_XY_ADDR64_si    = 1292,
    1308             :     BUFFER_STORE_FORMAT_XY_BOTHEN       = 1293,
    1309             :     BUFFER_STORE_FORMAT_XY_BOTHEN_exact = 1294,
    1310             :     BUFFER_STORE_FORMAT_XY_BOTHEN_si    = 1295,
    1311             :     BUFFER_STORE_FORMAT_XY_BOTHEN_vi    = 1296,
    1312             :     BUFFER_STORE_FORMAT_XY_IDXEN        = 1297,
    1313             :     BUFFER_STORE_FORMAT_XY_IDXEN_exact  = 1298,
    1314             :     BUFFER_STORE_FORMAT_XY_IDXEN_si     = 1299,
    1315             :     BUFFER_STORE_FORMAT_XY_IDXEN_vi     = 1300,
    1316             :     BUFFER_STORE_FORMAT_XY_OFFEN        = 1301,
    1317             :     BUFFER_STORE_FORMAT_XY_OFFEN_exact  = 1302,
    1318             :     BUFFER_STORE_FORMAT_XY_OFFEN_si     = 1303,
    1319             :     BUFFER_STORE_FORMAT_XY_OFFEN_vi     = 1304,
    1320             :     BUFFER_STORE_FORMAT_XY_OFFSET       = 1305,
    1321             :     BUFFER_STORE_FORMAT_XY_OFFSET_exact = 1306,
    1322             :     BUFFER_STORE_FORMAT_XY_OFFSET_si    = 1307,
    1323             :     BUFFER_STORE_FORMAT_XY_OFFSET_vi    = 1308,
    1324             :     BUFFER_STORE_FORMAT_X_ADDR64        = 1309,
    1325             :     BUFFER_STORE_FORMAT_X_ADDR64_si     = 1310,
    1326             :     BUFFER_STORE_FORMAT_X_BOTHEN        = 1311,
    1327             :     BUFFER_STORE_FORMAT_X_BOTHEN_exact  = 1312,
    1328             :     BUFFER_STORE_FORMAT_X_BOTHEN_si     = 1313,
    1329             :     BUFFER_STORE_FORMAT_X_BOTHEN_vi     = 1314,
    1330             :     BUFFER_STORE_FORMAT_X_IDXEN = 1315,
    1331             :     BUFFER_STORE_FORMAT_X_IDXEN_exact   = 1316,
    1332             :     BUFFER_STORE_FORMAT_X_IDXEN_si      = 1317,
    1333             :     BUFFER_STORE_FORMAT_X_IDXEN_vi      = 1318,
    1334             :     BUFFER_STORE_FORMAT_X_OFFEN = 1319,
    1335             :     BUFFER_STORE_FORMAT_X_OFFEN_exact   = 1320,
    1336             :     BUFFER_STORE_FORMAT_X_OFFEN_si      = 1321,
    1337             :     BUFFER_STORE_FORMAT_X_OFFEN_vi      = 1322,
    1338             :     BUFFER_STORE_FORMAT_X_OFFSET        = 1323,
    1339             :     BUFFER_STORE_FORMAT_X_OFFSET_exact  = 1324,
    1340             :     BUFFER_STORE_FORMAT_X_OFFSET_si     = 1325,
    1341             :     BUFFER_STORE_FORMAT_X_OFFSET_vi     = 1326,
    1342             :     BUFFER_STORE_SHORT_ADDR64   = 1327,
    1343             :     BUFFER_STORE_SHORT_ADDR64_si        = 1328,
    1344             :     BUFFER_STORE_SHORT_BOTHEN   = 1329,
    1345             :     BUFFER_STORE_SHORT_BOTHEN_exact     = 1330,
    1346             :     BUFFER_STORE_SHORT_BOTHEN_si        = 1331,
    1347             :     BUFFER_STORE_SHORT_BOTHEN_vi        = 1332,
    1348             :     BUFFER_STORE_SHORT_D16_HI_ADDR64    = 1333,
    1349             :     BUFFER_STORE_SHORT_D16_HI_BOTHEN    = 1334,
    1350             :     BUFFER_STORE_SHORT_D16_HI_BOTHEN_exact      = 1335,
    1351             :     BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi = 1336,
    1352             :     BUFFER_STORE_SHORT_D16_HI_IDXEN     = 1337,
    1353             :     BUFFER_STORE_SHORT_D16_HI_IDXEN_exact       = 1338,
    1354             :     BUFFER_STORE_SHORT_D16_HI_IDXEN_vi  = 1339,
    1355             :     BUFFER_STORE_SHORT_D16_HI_OFFEN     = 1340,
    1356             :     BUFFER_STORE_SHORT_D16_HI_OFFEN_exact       = 1341,
    1357             :     BUFFER_STORE_SHORT_D16_HI_OFFEN_vi  = 1342,
    1358             :     BUFFER_STORE_SHORT_D16_HI_OFFSET    = 1343,
    1359             :     BUFFER_STORE_SHORT_D16_HI_OFFSET_exact      = 1344,
    1360             :     BUFFER_STORE_SHORT_D16_HI_OFFSET_vi = 1345,
    1361             :     BUFFER_STORE_SHORT_IDXEN    = 1346,
    1362             :     BUFFER_STORE_SHORT_IDXEN_exact      = 1347,
    1363             :     BUFFER_STORE_SHORT_IDXEN_si = 1348,
    1364             :     BUFFER_STORE_SHORT_IDXEN_vi = 1349,
    1365             :     BUFFER_STORE_SHORT_OFFEN    = 1350,
    1366             :     BUFFER_STORE_SHORT_OFFEN_exact      = 1351,
    1367             :     BUFFER_STORE_SHORT_OFFEN_si = 1352,
    1368             :     BUFFER_STORE_SHORT_OFFEN_vi = 1353,
    1369             :     BUFFER_STORE_SHORT_OFFSET   = 1354,
    1370             :     BUFFER_STORE_SHORT_OFFSET_exact     = 1355,
    1371             :     BUFFER_STORE_SHORT_OFFSET_si        = 1356,
    1372             :     BUFFER_STORE_SHORT_OFFSET_vi        = 1357,
    1373             :     BUFFER_WBINVL1      = 1358,
    1374             :     BUFFER_WBINVL1_SC   = 1359,
    1375             :     BUFFER_WBINVL1_SC_si        = 1360,
    1376             :     BUFFER_WBINVL1_VOL  = 1361,
    1377             :     BUFFER_WBINVL1_VOL_ci       = 1362,
    1378             :     BUFFER_WBINVL1_VOL_vi       = 1363,
    1379             :     BUFFER_WBINVL1_si   = 1364,
    1380             :     BUFFER_WBINVL1_vi   = 1365,
    1381             :     CEIL        = 1366,
    1382             :     CF_ALU      = 1367,
    1383             :     CF_ALU_BREAK        = 1368,
    1384             :     CF_ALU_CONTINUE     = 1369,
    1385             :     CF_ALU_ELSE_AFTER   = 1370,
    1386             :     CF_ALU_POP_AFTER    = 1371,
    1387             :     CF_ALU_PUSH_BEFORE  = 1372,
    1388             :     CF_CALL_FS_EG       = 1373,
    1389             :     CF_CALL_FS_R600     = 1374,
    1390             :     CF_CONTINUE_EG      = 1375,
    1391             :     CF_CONTINUE_R600    = 1376,
    1392             :     CF_ELSE_EG  = 1377,
    1393             :     CF_ELSE_R600        = 1378,
    1394             :     CF_END_CM   = 1379,
    1395             :     CF_END_EG   = 1380,
    1396             :     CF_END_R600 = 1381,
    1397             :     CF_JUMP_EG  = 1382,
    1398             :     CF_JUMP_R600        = 1383,
    1399             :     CF_PUSH_EG  = 1384,
    1400             :     CF_PUSH_ELSE_R600   = 1385,
    1401             :     CF_TC_EG    = 1386,
    1402             :     CF_TC_R600  = 1387,
    1403             :     CF_VC_EG    = 1388,
    1404             :     CF_VC_R600  = 1389,
    1405             :     CLAMP_R600  = 1390,
    1406             :     CNDE_INT    = 1391,
    1407             :     CNDE_eg     = 1392,
    1408             :     CNDE_r600   = 1393,
    1409             :     CNDGE_INT   = 1394,
    1410             :     CNDGE_eg    = 1395,
    1411             :     CNDGE_r600  = 1396,
    1412             :     CNDGT_INT   = 1397,
    1413             :     CNDGT_eg    = 1398,
    1414             :     CNDGT_r600  = 1399,
    1415             :     CONST_COPY  = 1400,
    1416             :     CONTINUE    = 1401,
    1417             :     CONTINUEC_f32       = 1402,
    1418             :     CONTINUEC_i32       = 1403,
    1419             :     CONTINUE_LOGICALNZ_f32      = 1404,
    1420             :     CONTINUE_LOGICALNZ_i32      = 1405,
    1421             :     CONTINUE_LOGICALZ_f32       = 1406,
    1422             :     CONTINUE_LOGICALZ_i32       = 1407,
    1423             :     COS_cm      = 1408,
    1424             :     COS_eg      = 1409,
    1425             :     COS_r600    = 1410,
    1426             :     COS_r700    = 1411,
    1427             :     CUBE_eg_pseudo      = 1412,
    1428             :     CUBE_eg_real        = 1413,
    1429             :     CUBE_r600_pseudo    = 1414,
    1430             :     CUBE_r600_real      = 1415,
    1431             :     DEFAULT     = 1416,
    1432             :     DOT4_eg     = 1417,
    1433             :     DOT4_r600   = 1418,
    1434             :     DOT_4       = 1419,
    1435             :     DS_ADD_F32  = 1420,
    1436             :     DS_ADD_F32_vi       = 1421,
    1437             :     DS_ADD_RTN_F32      = 1422,
    1438             :     DS_ADD_RTN_F32_vi   = 1423,
    1439             :     DS_ADD_RTN_U32      = 1424,
    1440             :     DS_ADD_RTN_U32_si   = 1425,
    1441             :     DS_ADD_RTN_U32_vi   = 1426,
    1442             :     DS_ADD_RTN_U64      = 1427,
    1443             :     DS_ADD_RTN_U64_si   = 1428,
    1444             :     DS_ADD_RTN_U64_vi   = 1429,
    1445             :     DS_ADD_SRC2_U32     = 1430,
    1446             :     DS_ADD_SRC2_U32_si  = 1431,
    1447             :     DS_ADD_SRC2_U32_vi  = 1432,
    1448             :     DS_ADD_SRC2_U64     = 1433,
    1449             :     DS_ADD_SRC2_U64_si  = 1434,
    1450             :     DS_ADD_SRC2_U64_vi  = 1435,
    1451             :     DS_ADD_U32  = 1436,
    1452             :     DS_ADD_U32_si       = 1437,
    1453             :     DS_ADD_U32_vi       = 1438,
    1454             :     DS_ADD_U64  = 1439,
    1455             :     DS_ADD_U64_si       = 1440,
    1456             :     DS_ADD_U64_vi       = 1441,
    1457             :     DS_AND_B32  = 1442,
    1458             :     DS_AND_B32_si       = 1443,
    1459             :     DS_AND_B32_vi       = 1444,
    1460             :     DS_AND_B64  = 1445,
    1461             :     DS_AND_B64_si       = 1446,
    1462             :     DS_AND_B64_vi       = 1447,
    1463             :     DS_AND_RTN_B32      = 1448,
    1464             :     DS_AND_RTN_B32_si   = 1449,
    1465             :     DS_AND_RTN_B32_vi   = 1450,
    1466             :     DS_AND_RTN_B64      = 1451,
    1467             :     DS_AND_RTN_B64_si   = 1452,
    1468             :     DS_AND_RTN_B64_vi   = 1453,
    1469             :     DS_AND_SRC2_B32     = 1454,
    1470             :     DS_AND_SRC2_B32_si  = 1455,
    1471             :     DS_AND_SRC2_B32_vi  = 1456,
    1472             :     DS_AND_SRC2_B64     = 1457,
    1473             :     DS_AND_SRC2_B64_si  = 1458,
    1474             :     DS_AND_SRC2_B64_vi  = 1459,
    1475             :     DS_APPEND   = 1460,
    1476             :     DS_APPEND_si        = 1461,
    1477             :     DS_APPEND_vi        = 1462,
    1478             :     DS_BPERMUTE_B32     = 1463,
    1479             :     DS_BPERMUTE_B32_vi  = 1464,
    1480             :     DS_CMPST_B32        = 1465,
    1481             :     DS_CMPST_B32_si     = 1466,
    1482             :     DS_CMPST_B32_vi     = 1467,
    1483             :     DS_CMPST_B64        = 1468,
    1484             :     DS_CMPST_B64_si     = 1469,
    1485             :     DS_CMPST_B64_vi     = 1470,
    1486             :     DS_CMPST_F32        = 1471,
    1487             :     DS_CMPST_F32_si     = 1472,
    1488             :     DS_CMPST_F32_vi     = 1473,
    1489             :     DS_CMPST_F64        = 1474,
    1490             :     DS_CMPST_F64_si     = 1475,
    1491             :     DS_CMPST_F64_vi     = 1476,
    1492             :     DS_CMPST_RTN_B32    = 1477,
    1493             :     DS_CMPST_RTN_B32_si = 1478,
    1494             :     DS_CMPST_RTN_B32_vi = 1479,
    1495             :     DS_CMPST_RTN_B64    = 1480,
    1496             :     DS_CMPST_RTN_B64_si = 1481,
    1497             :     DS_CMPST_RTN_B64_vi = 1482,
    1498             :     DS_CMPST_RTN_F32    = 1483,
    1499             :     DS_CMPST_RTN_F32_si = 1484,
    1500             :     DS_CMPST_RTN_F32_vi = 1485,
    1501             :     DS_CMPST_RTN_F64    = 1486,
    1502             :     DS_CMPST_RTN_F64_si = 1487,
    1503             :     DS_CMPST_RTN_F64_vi = 1488,
    1504             :     DS_CONDXCHG32_RTN_B64       = 1489,
    1505             :     DS_CONDXCHG32_RTN_B64_si    = 1490,
    1506             :     DS_CONDXCHG32_RTN_B64_vi    = 1491,
    1507             :     DS_CONSUME  = 1492,
    1508             :     DS_CONSUME_si       = 1493,
    1509             :     DS_CONSUME_vi       = 1494,
    1510             :     DS_DEC_RTN_U32      = 1495,
    1511             :     DS_DEC_RTN_U32_si   = 1496,
    1512             :     DS_DEC_RTN_U32_vi   = 1497,
    1513             :     DS_DEC_RTN_U64      = 1498,
    1514             :     DS_DEC_RTN_U64_si   = 1499,
    1515             :     DS_DEC_RTN_U64_vi   = 1500,
    1516             :     DS_DEC_SRC2_U32     = 1501,
    1517             :     DS_DEC_SRC2_U32_si  = 1502,
    1518             :     DS_DEC_SRC2_U32_vi  = 1503,
    1519             :     DS_DEC_SRC2_U64     = 1504,
    1520             :     DS_DEC_SRC2_U64_si  = 1505,
    1521             :     DS_DEC_SRC2_U64_vi  = 1506,
    1522             :     DS_DEC_U32  = 1507,
    1523             :     DS_DEC_U32_si       = 1508,
    1524             :     DS_DEC_U32_vi       = 1509,
    1525             :     DS_DEC_U64  = 1510,
    1526             :     DS_DEC_U64_si       = 1511,
    1527             :     DS_DEC_U64_vi       = 1512,
    1528             :     DS_GWS_BARRIER      = 1513,
    1529             :     DS_GWS_BARRIER_si   = 1514,
    1530             :     DS_GWS_BARRIER_vi   = 1515,
    1531             :     DS_GWS_INIT = 1516,
    1532             :     DS_GWS_INIT_si      = 1517,
    1533             :     DS_GWS_INIT_vi      = 1518,
    1534             :     DS_GWS_SEMA_BR      = 1519,
    1535             :     DS_GWS_SEMA_BR_si   = 1520,
    1536             :     DS_GWS_SEMA_BR_vi   = 1521,
    1537             :     DS_GWS_SEMA_P       = 1522,
    1538             :     DS_GWS_SEMA_P_si    = 1523,
    1539             :     DS_GWS_SEMA_P_vi    = 1524,
    1540             :     DS_GWS_SEMA_RELEASE_ALL     = 1525,
    1541             :     DS_GWS_SEMA_RELEASE_ALL_si  = 1526,
    1542             :     DS_GWS_SEMA_RELEASE_ALL_vi  = 1527,
    1543             :     DS_GWS_SEMA_V       = 1528,
    1544             :     DS_GWS_SEMA_V_si    = 1529,
    1545             :     DS_GWS_SEMA_V_vi    = 1530,
    1546             :     DS_INC_RTN_U32      = 1531,
    1547             :     DS_INC_RTN_U32_si   = 1532,
    1548             :     DS_INC_RTN_U32_vi   = 1533,
    1549             :     DS_INC_RTN_U64      = 1534,
    1550             :     DS_INC_RTN_U64_si   = 1535,
    1551             :     DS_INC_RTN_U64_vi   = 1536,
    1552             :     DS_INC_SRC2_U32     = 1537,
    1553             :     DS_INC_SRC2_U32_si  = 1538,
    1554             :     DS_INC_SRC2_U32_vi  = 1539,
    1555             :     DS_INC_SRC2_U64     = 1540,
    1556             :     DS_INC_SRC2_U64_si  = 1541,
    1557             :     DS_INC_SRC2_U64_vi  = 1542,
    1558             :     DS_INC_U32  = 1543,
    1559             :     DS_INC_U32_si       = 1544,
    1560             :     DS_INC_U32_vi       = 1545,
    1561             :     DS_INC_U64  = 1546,
    1562             :     DS_INC_U64_si       = 1547,
    1563             :     DS_INC_U64_vi       = 1548,
    1564             :     DS_MAX_F32  = 1549,
    1565             :     DS_MAX_F32_si       = 1550,
    1566             :     DS_MAX_F32_vi       = 1551,
    1567             :     DS_MAX_F64  = 1552,
    1568             :     DS_MAX_F64_si       = 1553,
    1569             :     DS_MAX_F64_vi       = 1554,
    1570             :     DS_MAX_I32  = 1555,
    1571             :     DS_MAX_I32_si       = 1556,
    1572             :     DS_MAX_I32_vi       = 1557,
    1573             :     DS_MAX_I64  = 1558,
    1574             :     DS_MAX_I64_si       = 1559,
    1575             :     DS_MAX_I64_vi       = 1560,
    1576             :     DS_MAX_RTN_F32      = 1561,
    1577             :     DS_MAX_RTN_F32_si   = 1562,
    1578             :     DS_MAX_RTN_F32_vi   = 1563,
    1579             :     DS_MAX_RTN_F64      = 1564,
    1580             :     DS_MAX_RTN_F64_si   = 1565,
    1581             :     DS_MAX_RTN_F64_vi   = 1566,
    1582             :     DS_MAX_RTN_I32      = 1567,
    1583             :     DS_MAX_RTN_I32_si   = 1568,
    1584             :     DS_MAX_RTN_I32_vi   = 1569,
    1585             :     DS_MAX_RTN_I64      = 1570,
    1586             :     DS_MAX_RTN_I64_si   = 1571,
    1587             :     DS_MAX_RTN_I64_vi   = 1572,
    1588             :     DS_MAX_RTN_U32      = 1573,
    1589             :     DS_MAX_RTN_U32_si   = 1574,
    1590             :     DS_MAX_RTN_U32_vi   = 1575,
    1591             :     DS_MAX_RTN_U64      = 1576,
    1592             :     DS_MAX_RTN_U64_si   = 1577,
    1593             :     DS_MAX_RTN_U64_vi   = 1578,
    1594             :     DS_MAX_SRC2_F32     = 1579,
    1595             :     DS_MAX_SRC2_F32_si  = 1580,
    1596             :     DS_MAX_SRC2_F32_vi  = 1581,
    1597             :     DS_MAX_SRC2_F64     = 1582,
    1598             :     DS_MAX_SRC2_F64_si  = 1583,
    1599             :     DS_MAX_SRC2_F64_vi  = 1584,
    1600             :     DS_MAX_SRC2_I32     = 1585,
    1601             :     DS_MAX_SRC2_I32_si  = 1586,
    1602             :     DS_MAX_SRC2_I32_vi  = 1587,
    1603             :     DS_MAX_SRC2_I64     = 1588,
    1604             :     DS_MAX_SRC2_I64_si  = 1589,
    1605             :     DS_MAX_SRC2_I64_vi  = 1590,
    1606             :     DS_MAX_SRC2_U32     = 1591,
    1607             :     DS_MAX_SRC2_U32_si  = 1592,
    1608             :     DS_MAX_SRC2_U32_vi  = 1593,
    1609             :     DS_MAX_SRC2_U64     = 1594,
    1610             :     DS_MAX_SRC2_U64_si  = 1595,
    1611             :     DS_MAX_SRC2_U64_vi  = 1596,
    1612             :     DS_MAX_U32  = 1597,
    1613             :     DS_MAX_U32_si       = 1598,
    1614             :     DS_MAX_U32_vi       = 1599,
    1615             :     DS_MAX_U64  = 1600,
    1616             :     DS_MAX_U64_si       = 1601,
    1617             :     DS_MAX_U64_vi       = 1602,
    1618             :     DS_MIN_F32  = 1603,
    1619             :     DS_MIN_F32_si       = 1604,
    1620             :     DS_MIN_F32_vi       = 1605,
    1621             :     DS_MIN_F64  = 1606,
    1622             :     DS_MIN_F64_si       = 1607,
    1623             :     DS_MIN_F64_vi       = 1608,
    1624             :     DS_MIN_I32  = 1609,
    1625             :     DS_MIN_I32_si       = 1610,
    1626             :     DS_MIN_I32_vi       = 1611,
    1627             :     DS_MIN_I64  = 1612,
    1628             :     DS_MIN_I64_si       = 1613,
    1629             :     DS_MIN_I64_vi       = 1614,
    1630             :     DS_MIN_RTN_F32      = 1615,
    1631             :     DS_MIN_RTN_F32_si   = 1616,
    1632             :     DS_MIN_RTN_F32_vi   = 1617,
    1633             :     DS_MIN_RTN_F64      = 1618,
    1634             :     DS_MIN_RTN_F64_si   = 1619,
    1635             :     DS_MIN_RTN_F64_vi   = 1620,
    1636             :     DS_MIN_RTN_I32      = 1621,
    1637             :     DS_MIN_RTN_I32_si   = 1622,
    1638             :     DS_MIN_RTN_I32_vi   = 1623,
    1639             :     DS_MIN_RTN_I64      = 1624,
    1640             :     DS_MIN_RTN_I64_si   = 1625,
    1641             :     DS_MIN_RTN_I64_vi   = 1626,
    1642             :     DS_MIN_RTN_U32      = 1627,
    1643             :     DS_MIN_RTN_U32_si   = 1628,
    1644             :     DS_MIN_RTN_U32_vi   = 1629,
    1645             :     DS_MIN_RTN_U64      = 1630,
    1646             :     DS_MIN_RTN_U64_si   = 1631,
    1647             :     DS_MIN_RTN_U64_vi   = 1632,
    1648             :     DS_MIN_SRC2_F32     = 1633,
    1649             :     DS_MIN_SRC2_F32_si  = 1634,
    1650             :     DS_MIN_SRC2_F32_vi  = 1635,
    1651             :     DS_MIN_SRC2_F64     = 1636,
    1652             :     DS_MIN_SRC2_F64_si  = 1637,
    1653             :     DS_MIN_SRC2_F64_vi  = 1638,
    1654             :     DS_MIN_SRC2_I32     = 1639,
    1655             :     DS_MIN_SRC2_I32_si  = 1640,
    1656             :     DS_MIN_SRC2_I32_vi  = 1641,
    1657             :     DS_MIN_SRC2_I64     = 1642,
    1658             :     DS_MIN_SRC2_I64_si  = 1643,
    1659             :     DS_MIN_SRC2_I64_vi  = 1644,
    1660             :     DS_MIN_SRC2_U32     = 1645,
    1661             :     DS_MIN_SRC2_U32_si  = 1646,
    1662             :     DS_MIN_SRC2_U32_vi  = 1647,
    1663             :     DS_MIN_SRC2_U64     = 1648,
    1664             :     DS_MIN_SRC2_U64_si  = 1649,
    1665             :     DS_MIN_SRC2_U64_vi  = 1650,
    1666             :     DS_MIN_U32  = 1651,
    1667             :     DS_MIN_U32_si       = 1652,
    1668             :     DS_MIN_U32_vi       = 1653,
    1669             :     DS_MIN_U64  = 1654,
    1670             :     DS_MIN_U64_si       = 1655,
    1671             :     DS_MIN_U64_vi       = 1656,
    1672             :     DS_MSKOR_B32        = 1657,
    1673             :     DS_MSKOR_B32_si     = 1658,
    1674             :     DS_MSKOR_B32_vi     = 1659,
    1675             :     DS_MSKOR_B64        = 1660,
    1676             :     DS_MSKOR_B64_si     = 1661,
    1677             :     DS_MSKOR_B64_vi     = 1662,
    1678             :     DS_MSKOR_RTN_B32    = 1663,
    1679             :     DS_MSKOR_RTN_B32_si = 1664,
    1680             :     DS_MSKOR_RTN_B32_vi = 1665,
    1681             :     DS_MSKOR_RTN_B64    = 1666,
    1682             :     DS_MSKOR_RTN_B64_si = 1667,
    1683             :     DS_MSKOR_RTN_B64_vi = 1668,
    1684             :     DS_NOP      = 1669,
    1685             :     DS_NOP_si   = 1670,
    1686             :     DS_NOP_vi   = 1671,
    1687             :     DS_ORDERED_COUNT    = 1672,
    1688             :     DS_ORDERED_COUNT_si = 1673,
    1689             :     DS_ORDERED_COUNT_vi = 1674,
    1690             :     DS_OR_B32   = 1675,
    1691             :     DS_OR_B32_si        = 1676,
    1692             :     DS_OR_B32_vi        = 1677,
    1693             :     DS_OR_B64   = 1678,
    1694             :     DS_OR_B64_si        = 1679,
    1695             :     DS_OR_B64_vi        = 1680,
    1696             :     DS_OR_RTN_B32       = 1681,
    1697             :     DS_OR_RTN_B32_si    = 1682,
    1698             :     DS_OR_RTN_B32_vi    = 1683,
    1699             :     DS_OR_RTN_B64       = 1684,
    1700             :     DS_OR_RTN_B64_si    = 1685,
    1701             :     DS_OR_RTN_B64_vi    = 1686,
    1702             :     DS_OR_SRC2_B32      = 1687,
    1703             :     DS_OR_SRC2_B32_si   = 1688,
    1704             :     DS_OR_SRC2_B32_vi   = 1689,
    1705             :     DS_OR_SRC2_B64      = 1690,
    1706             :     DS_OR_SRC2_B64_si   = 1691,
    1707             :     DS_OR_SRC2_B64_vi   = 1692,
    1708             :     DS_PERMUTE_B32      = 1693,
    1709             :     DS_PERMUTE_B32_vi   = 1694,
    1710             :     DS_READ2ST64_B32    = 1695,
    1711             :     DS_READ2ST64_B32_si = 1696,
    1712             :     DS_READ2ST64_B32_vi = 1697,
    1713             :     DS_READ2ST64_B64    = 1698,
    1714             :     DS_READ2ST64_B64_si = 1699,
    1715             :     DS_READ2ST64_B64_vi = 1700,
    1716             :     DS_READ2_B32        = 1701,
    1717             :     DS_READ2_B32_si     = 1702,
    1718             :     DS_READ2_B32_vi     = 1703,
    1719             :     DS_READ2_B64        = 1704,
    1720             :     DS_READ2_B64_si     = 1705,
    1721             :     DS_READ2_B64_vi     = 1706,
    1722             :     DS_READ_ADDTID_B32  = 1707,
    1723             :     DS_READ_ADDTID_B32_vi       = 1708,
    1724             :     DS_READ_B128        = 1709,
    1725             :     DS_READ_B128_si     = 1710,
    1726             :     DS_READ_B128_vi     = 1711,
    1727             :     DS_READ_B32 = 1712,
    1728             :     DS_READ_B32_si      = 1713,
    1729             :     DS_READ_B32_vi      = 1714,
    1730             :     DS_READ_B64 = 1715,
    1731             :     DS_READ_B64_si      = 1716,
    1732             :     DS_READ_B64_vi      = 1717,
    1733             :     DS_READ_B96 = 1718,
    1734             :     DS_READ_B96_si      = 1719,
    1735             :     DS_READ_B96_vi      = 1720,
    1736             :     DS_READ_I16 = 1721,
    1737             :     DS_READ_I16_si      = 1722,
    1738             :     DS_READ_I16_vi      = 1723,
    1739             :     DS_READ_I8  = 1724,
    1740             :     DS_READ_I8_D16      = 1725,
    1741             :     DS_READ_I8_D16_HI   = 1726,
    1742             :     DS_READ_I8_D16_HI_vi        = 1727,
    1743             :     DS_READ_I8_D16_vi   = 1728,
    1744             :     DS_READ_I8_si       = 1729,
    1745             :     DS_READ_I8_vi       = 1730,
    1746             :     DS_READ_U16 = 1731,
    1747             :     DS_READ_U16_D16     = 1732,
    1748             :     DS_READ_U16_D16_HI  = 1733,
    1749             :     DS_READ_U16_D16_HI_vi       = 1734,
    1750             :     DS_READ_U16_D16_vi  = 1735,
    1751             :     DS_READ_U16_si      = 1736,
    1752             :     DS_READ_U16_vi      = 1737,
    1753             :     DS_READ_U8  = 1738,
    1754             :     DS_READ_U8_D16      = 1739,
    1755             :     DS_READ_U8_D16_HI   = 1740,
    1756             :     DS_READ_U8_D16_HI_vi        = 1741,
    1757             :     DS_READ_U8_D16_vi   = 1742,
    1758             :     DS_READ_U8_si       = 1743,
    1759             :     DS_READ_U8_vi       = 1744,
    1760             :     DS_RSUB_RTN_U32     = 1745,
    1761             :     DS_RSUB_RTN_U32_si  = 1746,
    1762             :     DS_RSUB_RTN_U32_vi  = 1747,
    1763             :     DS_RSUB_RTN_U64     = 1748,
    1764             :     DS_RSUB_RTN_U64_si  = 1749,
    1765             :     DS_RSUB_RTN_U64_vi  = 1750,
    1766             :     DS_RSUB_SRC2_U32    = 1751,
    1767             :     DS_RSUB_SRC2_U32_si = 1752,
    1768             :     DS_RSUB_SRC2_U32_vi = 1753,
    1769             :     DS_RSUB_SRC2_U64    = 1754,
    1770             :     DS_RSUB_SRC2_U64_si = 1755,
    1771             :     DS_RSUB_SRC2_U64_vi = 1756,
    1772             :     DS_RSUB_U32 = 1757,
    1773             :     DS_RSUB_U32_si      = 1758,
    1774             :     DS_RSUB_U32_vi      = 1759,
    1775             :     DS_RSUB_U64 = 1760,
    1776             :     DS_RSUB_U64_si      = 1761,
    1777             :     DS_RSUB_U64_vi      = 1762,
    1778             :     DS_SUB_RTN_U32      = 1763,
    1779             :     DS_SUB_RTN_U32_si   = 1764,
    1780             :     DS_SUB_RTN_U32_vi   = 1765,
    1781             :     DS_SUB_RTN_U64      = 1766,
    1782             :     DS_SUB_RTN_U64_si   = 1767,
    1783             :     DS_SUB_RTN_U64_vi   = 1768,
    1784             :     DS_SUB_SRC2_U32     = 1769,
    1785             :     DS_SUB_SRC2_U32_si  = 1770,
    1786             :     DS_SUB_SRC2_U32_vi  = 1771,
    1787             :     DS_SUB_SRC2_U64     = 1772,
    1788             :     DS_SUB_SRC2_U64_si  = 1773,
    1789             :     DS_SUB_SRC2_U64_vi  = 1774,
    1790             :     DS_SUB_U32  = 1775,
    1791             :     DS_SUB_U32_si       = 1776,
    1792             :     DS_SUB_U32_vi       = 1777,
    1793             :     DS_SUB_U64  = 1778,
    1794             :     DS_SUB_U64_si       = 1779,
    1795             :     DS_SUB_U64_vi       = 1780,
    1796             :     DS_SWIZZLE_B32      = 1781,
    1797             :     DS_SWIZZLE_B32_si   = 1782,
    1798             :     DS_SWIZZLE_B32_vi   = 1783,
    1799             :     DS_WRAP_RTN_B32     = 1784,
    1800             :     DS_WRAP_RTN_B32_si  = 1785,
    1801             :     DS_WRAP_RTN_B32_vi  = 1786,
    1802             :     DS_WRITE2ST64_B32   = 1787,
    1803             :     DS_WRITE2ST64_B32_si        = 1788,
    1804             :     DS_WRITE2ST64_B32_vi        = 1789,
    1805             :     DS_WRITE2ST64_B64   = 1790,
    1806             :     DS_WRITE2ST64_B64_si        = 1791,
    1807             :     DS_WRITE2ST64_B64_vi        = 1792,
    1808             :     DS_WRITE2_B32       = 1793,
    1809             :     DS_WRITE2_B32_si    = 1794,
    1810             :     DS_WRITE2_B32_vi    = 1795,
    1811             :     DS_WRITE2_B64       = 1796,
    1812             :     DS_WRITE2_B64_si    = 1797,
    1813             :     DS_WRITE2_B64_vi    = 1798,
    1814             :     DS_WRITE_ADDTID_B32 = 1799,
    1815             :     DS_WRITE_ADDTID_B32_vi      = 1800,
    1816             :     DS_WRITE_B128       = 1801,
    1817             :     DS_WRITE_B128_si    = 1802,
    1818             :     DS_WRITE_B128_vi    = 1803,
    1819             :     DS_WRITE_B16        = 1804,
    1820             :     DS_WRITE_B16_D16_HI = 1805,
    1821             :     DS_WRITE_B16_D16_HI_vi      = 1806,
    1822             :     DS_WRITE_B16_si     = 1807,
    1823             :     DS_WRITE_B16_vi     = 1808,
    1824             :     DS_WRITE_B32        = 1809,
    1825             :     DS_WRITE_B32_si     = 1810,
    1826             :     DS_WRITE_B32_vi     = 1811,
    1827             :     DS_WRITE_B64        = 1812,
    1828             :     DS_WRITE_B64_si     = 1813,
    1829             :     DS_WRITE_B64_vi     = 1814,
    1830             :     DS_WRITE_B8 = 1815,
    1831             :     DS_WRITE_B8_D16_HI  = 1816,
    1832             :     DS_WRITE_B8_D16_HI_vi       = 1817,
    1833             :     DS_WRITE_B8_si      = 1818,
    1834             :     DS_WRITE_B8_vi      = 1819,
    1835             :     DS_WRITE_B96        = 1820,
    1836             :     DS_WRITE_B96_si     = 1821,
    1837             :     DS_WRITE_B96_vi     = 1822,
    1838             :     DS_WRITE_SRC2_B32   = 1823,
    1839             :     DS_WRITE_SRC2_B32_si        = 1824,
    1840             :     DS_WRITE_SRC2_B32_vi        = 1825,
    1841             :     DS_WRITE_SRC2_B64   = 1826,
    1842             :     DS_WRITE_SRC2_B64_si        = 1827,
    1843             :     DS_WRITE_SRC2_B64_vi        = 1828,
    1844             :     DS_WRXCHG2ST64_RTN_B32      = 1829,
    1845             :     DS_WRXCHG2ST64_RTN_B32_si   = 1830,
    1846             :     DS_WRXCHG2ST64_RTN_B32_vi   = 1831,
    1847             :     DS_WRXCHG2ST64_RTN_B64      = 1832,
    1848             :     DS_WRXCHG2ST64_RTN_B64_si   = 1833,
    1849             :     DS_WRXCHG2ST64_RTN_B64_vi   = 1834,
    1850             :     DS_WRXCHG2_RTN_B32  = 1835,
    1851             :     DS_WRXCHG2_RTN_B32_si       = 1836,
    1852             :     DS_WRXCHG2_RTN_B32_vi       = 1837,
    1853             :     DS_WRXCHG2_RTN_B64  = 1838,
    1854             :     DS_WRXCHG2_RTN_B64_si       = 1839,
    1855             :     DS_WRXCHG2_RTN_B64_vi       = 1840,
    1856             :     DS_WRXCHG_RTN_B32   = 1841,
    1857             :     DS_WRXCHG_RTN_B32_si        = 1842,
    1858             :     DS_WRXCHG_RTN_B32_vi        = 1843,
    1859             :     DS_WRXCHG_RTN_B64   = 1844,
    1860             :     DS_WRXCHG_RTN_B64_si        = 1845,
    1861             :     DS_WRXCHG_RTN_B64_vi        = 1846,
    1862             :     DS_XOR_B32  = 1847,
    1863             :     DS_XOR_B32_si       = 1848,
    1864             :     DS_XOR_B32_vi       = 1849,
    1865             :     DS_XOR_B64  = 1850,
    1866             :     DS_XOR_B64_si       = 1851,
    1867             :     DS_XOR_B64_vi       = 1852,
    1868             :     DS_XOR_RTN_B32      = 1853,
    1869             :     DS_XOR_RTN_B32_si   = 1854,
    1870             :     DS_XOR_RTN_B32_vi   = 1855,
    1871             :     DS_XOR_RTN_B64      = 1856,
    1872             :     DS_XOR_RTN_B64_si   = 1857,
    1873             :     DS_XOR_RTN_B64_vi   = 1858,
    1874             :     DS_XOR_SRC2_B32     = 1859,
    1875             :     DS_XOR_SRC2_B32_si  = 1860,
    1876             :     DS_XOR_SRC2_B32_vi  = 1861,
    1877             :     DS_XOR_SRC2_B64     = 1862,
    1878             :     DS_XOR_SRC2_B64_si  = 1863,
    1879             :     DS_XOR_SRC2_B64_vi  = 1864,
    1880             :     DUMMY_CHAIN = 1865,
    1881             :     EG_ExportBuf        = 1866,
    1882             :     EG_ExportSwz        = 1867,
    1883             :     ELSE        = 1868,
    1884             :     END = 1869,
    1885             :     ENDFUNC     = 1870,
    1886             :     ENDIF       = 1871,
    1887             :     ENDLOOP     = 1872,
    1888             :     ENDMAIN     = 1873,
    1889             :     ENDSWITCH   = 1874,
    1890             :     END_LOOP_EG = 1875,
    1891             :     END_LOOP_R600       = 1876,
    1892             :     EXIT_WWM    = 1877,
    1893             :     EXP = 1878,
    1894             :     EXP_DONE    = 1879,
    1895             :     EXP_DONE_si = 1880,
    1896             :     EXP_DONE_vi = 1881,
    1897             :     EXP_IEEE_cm = 1882,
    1898             :     EXP_IEEE_eg = 1883,
    1899             :     EXP_IEEE_r600       = 1884,
    1900             :     EXP_si      = 1885,
    1901             :     EXP_vi      = 1886,
    1902             :     FABS_R600   = 1887,
    1903             :     FETCH_CLAUSE        = 1888,
    1904             :     FFBH_UINT   = 1889,
    1905             :     FFBL_INT    = 1890,
    1906             :     FLAT_ATOMIC_ADD     = 1891,
    1907             :     FLAT_ATOMIC_ADD_RTN = 1892,
    1908             :     FLAT_ATOMIC_ADD_RTN_ci      = 1893,
    1909             :     FLAT_ATOMIC_ADD_RTN_vi      = 1894,
    1910             :     FLAT_ATOMIC_ADD_X2  = 1895,
    1911             :     FLAT_ATOMIC_ADD_X2_RTN      = 1896,
    1912             :     FLAT_ATOMIC_ADD_X2_RTN_ci   = 1897,
    1913             :     FLAT_ATOMIC_ADD_X2_RTN_vi   = 1898,
    1914             :     FLAT_ATOMIC_ADD_X2_ci       = 1899,
    1915             :     FLAT_ATOMIC_ADD_X2_vi       = 1900,
    1916             :     FLAT_ATOMIC_ADD_ci  = 1901,
    1917             :     FLAT_ATOMIC_ADD_vi  = 1902,
    1918             :     FLAT_ATOMIC_AND     = 1903,
    1919             :     FLAT_ATOMIC_AND_RTN = 1904,
    1920             :     FLAT_ATOMIC_AND_RTN_ci      = 1905,
    1921             :     FLAT_ATOMIC_AND_RTN_vi      = 1906,
    1922             :     FLAT_ATOMIC_AND_X2  = 1907,
    1923             :     FLAT_ATOMIC_AND_X2_RTN      = 1908,
    1924             :     FLAT_ATOMIC_AND_X2_RTN_ci   = 1909,
    1925             :     FLAT_ATOMIC_AND_X2_RTN_vi   = 1910,
    1926             :     FLAT_ATOMIC_AND_X2_ci       = 1911,
    1927             :     FLAT_ATOMIC_AND_X2_vi       = 1912,
    1928             :     FLAT_ATOMIC_AND_ci  = 1913,
    1929             :     FLAT_ATOMIC_AND_vi  = 1914,
    1930             :     FLAT_ATOMIC_CMPSWAP = 1915,
    1931             :     FLAT_ATOMIC_CMPSWAP_RTN     = 1916,
    1932             :     FLAT_ATOMIC_CMPSWAP_RTN_ci  = 1917,
    1933             :     FLAT_ATOMIC_CMPSWAP_RTN_vi  = 1918,
    1934             :     FLAT_ATOMIC_CMPSWAP_X2      = 1919,
    1935             :     FLAT_ATOMIC_CMPSWAP_X2_RTN  = 1920,
    1936             :     FLAT_ATOMIC_CMPSWAP_X2_RTN_ci       = 1921,
    1937             :     FLAT_ATOMIC_CMPSWAP_X2_RTN_vi       = 1922,
    1938             :     FLAT_ATOMIC_CMPSWAP_X2_ci   = 1923,
    1939             :     FLAT_ATOMIC_CMPSWAP_X2_vi   = 1924,
    1940             :     FLAT_ATOMIC_CMPSWAP_ci      = 1925,
    1941             :     FLAT_ATOMIC_CMPSWAP_vi      = 1926,
    1942             :     FLAT_ATOMIC_DEC     = 1927,
    1943             :     FLAT_ATOMIC_DEC_RTN = 1928,
    1944             :     FLAT_ATOMIC_DEC_RTN_ci      = 1929,
    1945             :     FLAT_ATOMIC_DEC_RTN_vi      = 1930,
    1946             :     FLAT_ATOMIC_DEC_X2  = 1931,
    1947             :     FLAT_ATOMIC_DEC_X2_RTN      = 1932,
    1948             :     FLAT_ATOMIC_DEC_X2_RTN_ci   = 1933,
    1949             :     FLAT_ATOMIC_DEC_X2_RTN_vi   = 1934,
    1950             :     FLAT_ATOMIC_DEC_X2_ci       = 1935,
    1951             :     FLAT_ATOMIC_DEC_X2_vi       = 1936,
    1952             :     FLAT_ATOMIC_DEC_ci  = 1937,
    1953             :     FLAT_ATOMIC_DEC_vi  = 1938,
    1954             :     FLAT_ATOMIC_FCMPSWAP        = 1939,
    1955             :     FLAT_ATOMIC_FCMPSWAP_RTN    = 1940,
    1956             :     FLAT_ATOMIC_FCMPSWAP_RTN_ci = 1941,
    1957             :     FLAT_ATOMIC_FCMPSWAP_X2     = 1942,
    1958             :     FLAT_ATOMIC_FCMPSWAP_X2_RTN = 1943,
    1959             :     FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci      = 1944,
    1960             :     FLAT_ATOMIC_FCMPSWAP_X2_ci  = 1945,
    1961             :     FLAT_ATOMIC_FCMPSWAP_ci     = 1946,
    1962             :     FLAT_ATOMIC_FMAX    = 1947,
    1963             :     FLAT_ATOMIC_FMAX_RTN        = 1948,
    1964             :     FLAT_ATOMIC_FMAX_RTN_ci     = 1949,
    1965             :     FLAT_ATOMIC_FMAX_X2 = 1950,
    1966             :     FLAT_ATOMIC_FMAX_X2_RTN     = 1951,
    1967             :     FLAT_ATOMIC_FMAX_X2_RTN_ci  = 1952,
    1968             :     FLAT_ATOMIC_FMAX_X2_ci      = 1953,
    1969             :     FLAT_ATOMIC_FMAX_ci = 1954,
    1970             :     FLAT_ATOMIC_FMIN    = 1955,
    1971             :     FLAT_ATOMIC_FMIN_RTN        = 1956,
    1972             :     FLAT_ATOMIC_FMIN_RTN_ci     = 1957,
    1973             :     FLAT_ATOMIC_FMIN_X2 = 1958,
    1974             :     FLAT_ATOMIC_FMIN_X2_RTN     = 1959,
    1975             :     FLAT_ATOMIC_FMIN_X2_RTN_ci  = 1960,
    1976             :     FLAT_ATOMIC_FMIN_X2_ci      = 1961,
    1977             :     FLAT_ATOMIC_FMIN_ci = 1962,
    1978             :     FLAT_ATOMIC_INC     = 1963,
    1979             :     FLAT_ATOMIC_INC_RTN = 1964,
    1980             :     FLAT_ATOMIC_INC_RTN_ci      = 1965,
    1981             :     FLAT_ATOMIC_INC_RTN_vi      = 1966,
    1982             :     FLAT_ATOMIC_INC_X2  = 1967,
    1983             :     FLAT_ATOMIC_INC_X2_RTN      = 1968,
    1984             :     FLAT_ATOMIC_INC_X2_RTN_ci   = 1969,
    1985             :     FLAT_ATOMIC_INC_X2_RTN_vi   = 1970,
    1986             :     FLAT_ATOMIC_INC_X2_ci       = 1971,
    1987             :     FLAT_ATOMIC_INC_X2_vi       = 1972,
    1988             :     FLAT_ATOMIC_INC_ci  = 1973,
    1989             :     FLAT_ATOMIC_INC_vi  = 1974,
    1990             :     FLAT_ATOMIC_OR      = 1975,
    1991             :     FLAT_ATOMIC_OR_RTN  = 1976,
    1992             :     FLAT_ATOMIC_OR_RTN_ci       = 1977,
    1993             :     FLAT_ATOMIC_OR_RTN_vi       = 1978,
    1994             :     FLAT_ATOMIC_OR_X2   = 1979,
    1995             :     FLAT_ATOMIC_OR_X2_RTN       = 1980,
    1996             :     FLAT_ATOMIC_OR_X2_RTN_ci    = 1981,
    1997             :     FLAT_ATOMIC_OR_X2_RTN_vi    = 1982,
    1998             :     FLAT_ATOMIC_OR_X2_ci        = 1983,
    1999             :     FLAT_ATOMIC_OR_X2_vi        = 1984,
    2000             :     FLAT_ATOMIC_OR_ci   = 1985,
    2001             :     FLAT_ATOMIC_OR_vi   = 1986,
    2002             :     FLAT_ATOMIC_SMAX    = 1987,
    2003             :     FLAT_ATOMIC_SMAX_RTN        = 1988,
    2004             :     FLAT_ATOMIC_SMAX_RTN_ci     = 1989,
    2005             :     FLAT_ATOMIC_SMAX_RTN_vi     = 1990,
    2006             :     FLAT_ATOMIC_SMAX_X2 = 1991,
    2007             :     FLAT_ATOMIC_SMAX_X2_RTN     = 1992,
    2008             :     FLAT_ATOMIC_SMAX_X2_RTN_ci  = 1993,
    2009             :     FLAT_ATOMIC_SMAX_X2_RTN_vi  = 1994,
    2010             :     FLAT_ATOMIC_SMAX_X2_ci      = 1995,
    2011             :     FLAT_ATOMIC_SMAX_X2_vi      = 1996,
    2012             :     FLAT_ATOMIC_SMAX_ci = 1997,
    2013             :     FLAT_ATOMIC_SMAX_vi = 1998,
    2014             :     FLAT_ATOMIC_SMIN    = 1999,
    2015             :     FLAT_ATOMIC_SMIN_RTN        = 2000,
    2016             :     FLAT_ATOMIC_SMIN_RTN_ci     = 2001,
    2017             :     FLAT_ATOMIC_SMIN_RTN_vi     = 2002,
    2018             :     FLAT_ATOMIC_SMIN_X2 = 2003,
    2019             :     FLAT_ATOMIC_SMIN_X2_RTN     = 2004,
    2020             :     FLAT_ATOMIC_SMIN_X2_RTN_ci  = 2005,
    2021             :     FLAT_ATOMIC_SMIN_X2_RTN_vi  = 2006,
    2022             :     FLAT_ATOMIC_SMIN_X2_ci      = 2007,
    2023             :     FLAT_ATOMIC_SMIN_X2_vi      = 2008,
    2024             :     FLAT_ATOMIC_SMIN_ci = 2009,
    2025             :     FLAT_ATOMIC_SMIN_vi = 2010,
    2026             :     FLAT_ATOMIC_SUB     = 2011,
    2027             :     FLAT_ATOMIC_SUB_RTN = 2012,
    2028             :     FLAT_ATOMIC_SUB_RTN_ci      = 2013,
    2029             :     FLAT_ATOMIC_SUB_RTN_vi      = 2014,
    2030             :     FLAT_ATOMIC_SUB_X2  = 2015,
    2031             :     FLAT_ATOMIC_SUB_X2_RTN      = 2016,
    2032             :     FLAT_ATOMIC_SUB_X2_RTN_ci   = 2017,
    2033             :     FLAT_ATOMIC_SUB_X2_RTN_vi   = 2018,
    2034             :     FLAT_ATOMIC_SUB_X2_ci       = 2019,
    2035             :     FLAT_ATOMIC_SUB_X2_vi       = 2020,
    2036             :     FLAT_ATOMIC_SUB_ci  = 2021,
    2037             :     FLAT_ATOMIC_SUB_vi  = 2022,
    2038             :     FLAT_ATOMIC_SWAP    = 2023,
    2039             :     FLAT_ATOMIC_SWAP_RTN        = 2024,
    2040             :     FLAT_ATOMIC_SWAP_RTN_ci     = 2025,
    2041             :     FLAT_ATOMIC_SWAP_RTN_vi     = 2026,
    2042             :     FLAT_ATOMIC_SWAP_X2 = 2027,
    2043             :     FLAT_ATOMIC_SWAP_X2_RTN     = 2028,
    2044             :     FLAT_ATOMIC_SWAP_X2_RTN_ci  = 2029,
    2045             :     FLAT_ATOMIC_SWAP_X2_RTN_vi  = 2030,
    2046             :     FLAT_ATOMIC_SWAP_X2_ci      = 2031,
    2047             :     FLAT_ATOMIC_SWAP_X2_vi      = 2032,
    2048             :     FLAT_ATOMIC_SWAP_ci = 2033,
    2049             :     FLAT_ATOMIC_SWAP_vi = 2034,
    2050             :     FLAT_ATOMIC_UMAX    = 2035,
    2051             :     FLAT_ATOMIC_UMAX_RTN        = 2036,
    2052             :     FLAT_ATOMIC_UMAX_RTN_ci     = 2037,
    2053             :     FLAT_ATOMIC_UMAX_RTN_vi     = 2038,
    2054             :     FLAT_ATOMIC_UMAX_X2 = 2039,
    2055             :     FLAT_ATOMIC_UMAX_X2_RTN     = 2040,
    2056             :     FLAT_ATOMIC_UMAX_X2_RTN_ci  = 2041,
    2057             :     FLAT_ATOMIC_UMAX_X2_RTN_vi  = 2042,
    2058             :     FLAT_ATOMIC_UMAX_X2_ci      = 2043,
    2059             :     FLAT_ATOMIC_UMAX_X2_vi      = 2044,
    2060             :     FLAT_ATOMIC_UMAX_ci = 2045,
    2061             :     FLAT_ATOMIC_UMAX_vi = 2046,
    2062             :     FLAT_ATOMIC_UMIN    = 2047,
    2063             :     FLAT_ATOMIC_UMIN_RTN        = 2048,
    2064             :     FLAT_ATOMIC_UMIN_RTN_ci     = 2049,
    2065             :     FLAT_ATOMIC_UMIN_RTN_vi     = 2050,
    2066             :     FLAT_ATOMIC_UMIN_X2 = 2051,
    2067             :     FLAT_ATOMIC_UMIN_X2_RTN     = 2052,
    2068             :     FLAT_ATOMIC_UMIN_X2_RTN_ci  = 2053,
    2069             :     FLAT_ATOMIC_UMIN_X2_RTN_vi  = 2054,
    2070             :     FLAT_ATOMIC_UMIN_X2_ci      = 2055,
    2071             :     FLAT_ATOMIC_UMIN_X2_vi      = 2056,
    2072             :     FLAT_ATOMIC_UMIN_ci = 2057,
    2073             :     FLAT_ATOMIC_UMIN_vi = 2058,
    2074             :     FLAT_ATOMIC_XOR     = 2059,
    2075             :     FLAT_ATOMIC_XOR_RTN = 2060,
    2076             :     FLAT_ATOMIC_XOR_RTN_ci      = 2061,
    2077             :     FLAT_ATOMIC_XOR_RTN_vi      = 2062,
    2078             :     FLAT_ATOMIC_XOR_X2  = 2063,
    2079             :     FLAT_ATOMIC_XOR_X2_RTN      = 2064,
    2080             :     FLAT_ATOMIC_XOR_X2_RTN_ci   = 2065,
    2081             :     FLAT_ATOMIC_XOR_X2_RTN_vi   = 2066,
    2082             :     FLAT_ATOMIC_XOR_X2_ci       = 2067,
    2083             :     FLAT_ATOMIC_XOR_X2_vi       = 2068,
    2084             :     FLAT_ATOMIC_XOR_ci  = 2069,
    2085             :     FLAT_ATOMIC_XOR_vi  = 2070,
    2086             :     FLAT_LOAD_DWORD     = 2071,
    2087             :     FLAT_LOAD_DWORDX2   = 2072,
    2088             :     FLAT_LOAD_DWORDX2_ci        = 2073,
    2089             :     FLAT_LOAD_DWORDX2_vi        = 2074,
    2090             :     FLAT_LOAD_DWORDX3   = 2075,
    2091             :     FLAT_LOAD_DWORDX3_ci        = 2076,
    2092             :     FLAT_LOAD_DWORDX3_vi        = 2077,
    2093             :     FLAT_LOAD_DWORDX4   = 2078,
    2094             :     FLAT_LOAD_DWORDX4_ci        = 2079,
    2095             :     FLAT_LOAD_DWORDX4_vi        = 2080,
    2096             :     FLAT_LOAD_DWORD_ci  = 2081,
    2097             :     FLAT_LOAD_DWORD_vi  = 2082,
    2098             :     FLAT_LOAD_SBYTE     = 2083,
    2099             :     FLAT_LOAD_SBYTE_D16 = 2084,
    2100             :     FLAT_LOAD_SBYTE_D16_HI      = 2085,
    2101             :     FLAT_LOAD_SBYTE_D16_HI_vi   = 2086,
    2102             :     FLAT_LOAD_SBYTE_D16_vi      = 2087,
    2103             :     FLAT_LOAD_SBYTE_ci  = 2088,
    2104             :     FLAT_LOAD_SBYTE_vi  = 2089,
    2105             :     FLAT_LOAD_SHORT_D16 = 2090,
    2106             :     FLAT_LOAD_SHORT_D16_HI      = 2091,
    2107             :     FLAT_LOAD_SHORT_D16_HI_vi   = 2092,
    2108             :     FLAT_LOAD_SHORT_D16_vi      = 2093,
    2109             :     FLAT_LOAD_SSHORT    = 2094,
    2110             :     FLAT_LOAD_SSHORT_ci = 2095,
    2111             :     FLAT_LOAD_SSHORT_vi = 2096,
    2112             :     FLAT_LOAD_UBYTE     = 2097,
    2113             :     FLAT_LOAD_UBYTE_D16 = 2098,
    2114             :     FLAT_LOAD_UBYTE_D16_HI      = 2099,
    2115             :     FLAT_LOAD_UBYTE_D16_HI_vi   = 2100,
    2116             :     FLAT_LOAD_UBYTE_D16_vi      = 2101,
    2117             :     FLAT_LOAD_UBYTE_ci  = 2102,
    2118             :     FLAT_LOAD_UBYTE_vi  = 2103,
    2119             :     FLAT_LOAD_USHORT    = 2104,
    2120             :     FLAT_LOAD_USHORT_ci = 2105,
    2121             :     FLAT_LOAD_USHORT_vi = 2106,
    2122             :     FLAT_STORE_BYTE     = 2107,
    2123             :     FLAT_STORE_BYTE_D16_HI      = 2108,
    2124             :     FLAT_STORE_BYTE_D16_HI_vi   = 2109,
    2125             :     FLAT_STORE_BYTE_ci  = 2110,
    2126             :     FLAT_STORE_BYTE_vi  = 2111,
    2127             :     FLAT_STORE_DWORD    = 2112,
    2128             :     FLAT_STORE_DWORDX2  = 2113,
    2129             :     FLAT_STORE_DWORDX2_ci       = 2114,
    2130             :     FLAT_STORE_DWORDX2_vi       = 2115,
    2131             :     FLAT_STORE_DWORDX3  = 2116,
    2132             :     FLAT_STORE_DWORDX3_ci       = 2117,
    2133             :     FLAT_STORE_DWORDX3_vi       = 2118,
    2134             :     FLAT_STORE_DWORDX4  = 2119,
    2135             :     FLAT_STORE_DWORDX4_ci       = 2120,
    2136             :     FLAT_STORE_DWORDX4_vi       = 2121,
    2137             :     FLAT_STORE_DWORD_ci = 2122,
    2138             :     FLAT_STORE_DWORD_vi = 2123,
    2139             :     FLAT_STORE_SHORT    = 2124,
    2140             :     FLAT_STORE_SHORT_D16_HI     = 2125,
    2141             :     FLAT_STORE_SHORT_D16_HI_vi  = 2126,
    2142             :     FLAT_STORE_SHORT_ci = 2127,
    2143             :     FLAT_STORE_SHORT_vi = 2128,
    2144             :     FLOOR       = 2129,
    2145             :     FLT16_TO_FLT32      = 2130,
    2146             :     FLT32_TO_FLT16      = 2131,
    2147             :     FLT_TO_INT_eg       = 2132,
    2148             :     FLT_TO_INT_r600     = 2133,
    2149             :     FLT_TO_UINT_eg      = 2134,
    2150             :     FLT_TO_UINT_r600    = 2135,
    2151             :     FMA_eg      = 2136,
    2152             :     FNEG_R600   = 2137,
    2153             :     FRACT       = 2138,
    2154             :     FUNC        = 2139,
    2155             :     GET_GROUPSTATICSIZE = 2140,
    2156             :     GLOBAL_ATOMIC_ADD   = 2141,
    2157             :     GLOBAL_ATOMIC_ADD_RTN       = 2142,
    2158             :     GLOBAL_ATOMIC_ADD_RTN_vi    = 2143,
    2159             :     GLOBAL_ATOMIC_ADD_SADDR     = 2144,
    2160             :     GLOBAL_ATOMIC_ADD_SADDR_RTN = 2145,
    2161             :     GLOBAL_ATOMIC_ADD_SADDR_RTN_vi      = 2146,
    2162             :     GLOBAL_ATOMIC_ADD_SADDR_vi  = 2147,
    2163             :     GLOBAL_ATOMIC_ADD_X2        = 2148,
    2164             :     GLOBAL_ATOMIC_ADD_X2_RTN    = 2149,
    2165             :     GLOBAL_ATOMIC_ADD_X2_RTN_vi = 2150,
    2166             :     GLOBAL_ATOMIC_ADD_X2_SADDR  = 2151,
    2167             :     GLOBAL_ATOMIC_ADD_X2_SADDR_RTN      = 2152,
    2168             :     GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi   = 2153,
    2169             :     GLOBAL_ATOMIC_ADD_X2_SADDR_vi       = 2154,
    2170             :     GLOBAL_ATOMIC_ADD_X2_vi     = 2155,
    2171             :     GLOBAL_ATOMIC_ADD_vi        = 2156,
    2172             :     GLOBAL_ATOMIC_AND   = 2157,
    2173             :     GLOBAL_ATOMIC_AND_RTN       = 2158,
    2174             :     GLOBAL_ATOMIC_AND_RTN_vi    = 2159,
    2175             :     GLOBAL_ATOMIC_AND_SADDR     = 2160,
    2176             :     GLOBAL_ATOMIC_AND_SADDR_RTN = 2161,
    2177             :     GLOBAL_ATOMIC_AND_SADDR_RTN_vi      = 2162,
    2178             :     GLOBAL_ATOMIC_AND_SADDR_vi  = 2163,
    2179             :     GLOBAL_ATOMIC_AND_X2        = 2164,
    2180             :     GLOBAL_ATOMIC_AND_X2_RTN    = 2165,
    2181             :     GLOBAL_ATOMIC_AND_X2_RTN_vi = 2166,
    2182             :     GLOBAL_ATOMIC_AND_X2_SADDR  = 2167,
    2183             :     GLOBAL_ATOMIC_AND_X2_SADDR_RTN      = 2168,
    2184             :     GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi   = 2169,
    2185             :     GLOBAL_ATOMIC_AND_X2_SADDR_vi       = 2170,
    2186             :     GLOBAL_ATOMIC_AND_X2_vi     = 2171,
    2187             :     GLOBAL_ATOMIC_AND_vi        = 2172,
    2188             :     GLOBAL_ATOMIC_CMPSWAP       = 2173,
    2189             :     GLOBAL_ATOMIC_CMPSWAP_RTN   = 2174,
    2190             :     GLOBAL_ATOMIC_CMPSWAP_RTN_vi        = 2175,
    2191             :     GLOBAL_ATOMIC_CMPSWAP_SADDR = 2176,
    2192             :     GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN     = 2177,
    2193             :     GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi  = 2178,
    2194             :     GLOBAL_ATOMIC_CMPSWAP_SADDR_vi      = 2179,
    2195             :     GLOBAL_ATOMIC_CMPSWAP_X2    = 2180,
    2196             :     GLOBAL_ATOMIC_CMPSWAP_X2_RTN        = 2181,
    2197             :     GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi     = 2182,
    2198             :     GLOBAL_ATOMIC_CMPSWAP_X2_SADDR      = 2183,
    2199             :     GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN  = 2184,
    2200             :     GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi       = 2185,
    2201             :     GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi   = 2186,
    2202             :     GLOBAL_ATOMIC_CMPSWAP_X2_vi = 2187,
    2203             :     GLOBAL_ATOMIC_CMPSWAP_vi    = 2188,
    2204             :     GLOBAL_ATOMIC_DEC   = 2189,
    2205             :     GLOBAL_ATOMIC_DEC_RTN       = 2190,
    2206             :     GLOBAL_ATOMIC_DEC_RTN_vi    = 2191,
    2207             :     GLOBAL_ATOMIC_DEC_SADDR     = 2192,
    2208             :     GLOBAL_ATOMIC_DEC_SADDR_RTN = 2193,
    2209             :     GLOBAL_ATOMIC_DEC_SADDR_RTN_vi      = 2194,
    2210             :     GLOBAL_ATOMIC_DEC_SADDR_vi  = 2195,
    2211             :     GLOBAL_ATOMIC_DEC_X2        = 2196,
    2212             :     GLOBAL_ATOMIC_DEC_X2_RTN    = 2197,
    2213             :     GLOBAL_ATOMIC_DEC_X2_RTN_vi = 2198,
    2214             :     GLOBAL_ATOMIC_DEC_X2_SADDR  = 2199,
    2215             :     GLOBAL_ATOMIC_DEC_X2_SADDR_RTN      = 2200,
    2216             :     GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi   = 2201,
    2217             :     GLOBAL_ATOMIC_DEC_X2_SADDR_vi       = 2202,
    2218             :     GLOBAL_ATOMIC_DEC_X2_vi     = 2203,
    2219             :     GLOBAL_ATOMIC_DEC_vi        = 2204,
    2220             :     GLOBAL_ATOMIC_INC   = 2205,
    2221             :     GLOBAL_ATOMIC_INC_RTN       = 2206,
    2222             :     GLOBAL_ATOMIC_INC_RTN_vi    = 2207,
    2223             :     GLOBAL_ATOMIC_INC_SADDR     = 2208,
    2224             :     GLOBAL_ATOMIC_INC_SADDR_RTN = 2209,
    2225             :     GLOBAL_ATOMIC_INC_SADDR_RTN_vi      = 2210,
    2226             :     GLOBAL_ATOMIC_INC_SADDR_vi  = 2211,
    2227             :     GLOBAL_ATOMIC_INC_X2        = 2212,
    2228             :     GLOBAL_ATOMIC_INC_X2_RTN    = 2213,
    2229             :     GLOBAL_ATOMIC_INC_X2_RTN_vi = 2214,
    2230             :     GLOBAL_ATOMIC_INC_X2_SADDR  = 2215,
    2231             :     GLOBAL_ATOMIC_INC_X2_SADDR_RTN      = 2216,
    2232             :     GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi   = 2217,
    2233             :     GLOBAL_ATOMIC_INC_X2_SADDR_vi       = 2218,
    2234             :     GLOBAL_ATOMIC_INC_X2_vi     = 2219,
    2235             :     GLOBAL_ATOMIC_INC_vi        = 2220,
    2236             :     GLOBAL_ATOMIC_OR    = 2221,
    2237             :     GLOBAL_ATOMIC_OR_RTN        = 2222,
    2238             :     GLOBAL_ATOMIC_OR_RTN_vi     = 2223,
    2239             :     GLOBAL_ATOMIC_OR_SADDR      = 2224,
    2240             :     GLOBAL_ATOMIC_OR_SADDR_RTN  = 2225,
    2241             :     GLOBAL_ATOMIC_OR_SADDR_RTN_vi       = 2226,
    2242             :     GLOBAL_ATOMIC_OR_SADDR_vi   = 2227,
    2243             :     GLOBAL_ATOMIC_OR_X2 = 2228,
    2244             :     GLOBAL_ATOMIC_OR_X2_RTN     = 2229,
    2245             :     GLOBAL_ATOMIC_OR_X2_RTN_vi  = 2230,
    2246             :     GLOBAL_ATOMIC_OR_X2_SADDR   = 2231,
    2247             :     GLOBAL_ATOMIC_OR_X2_SADDR_RTN       = 2232,
    2248             :     GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi    = 2233,
    2249             :     GLOBAL_ATOMIC_OR_X2_SADDR_vi        = 2234,
    2250             :     GLOBAL_ATOMIC_OR_X2_vi      = 2235,
    2251             :     GLOBAL_ATOMIC_OR_vi = 2236,
    2252             :     GLOBAL_ATOMIC_SMAX  = 2237,
    2253             :     GLOBAL_ATOMIC_SMAX_RTN      = 2238,
    2254             :     GLOBAL_ATOMIC_SMAX_RTN_vi   = 2239,
    2255             :     GLOBAL_ATOMIC_SMAX_SADDR    = 2240,
    2256             :     GLOBAL_ATOMIC_SMAX_SADDR_RTN        = 2241,
    2257             :     GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi     = 2242,
    2258             :     GLOBAL_ATOMIC_SMAX_SADDR_vi = 2243,
    2259             :     GLOBAL_ATOMIC_SMAX_X2       = 2244,
    2260             :     GLOBAL_ATOMIC_SMAX_X2_RTN   = 2245,
    2261             :     GLOBAL_ATOMIC_SMAX_X2_RTN_vi        = 2246,
    2262             :     GLOBAL_ATOMIC_SMAX_X2_SADDR = 2247,
    2263             :     GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN     = 2248,
    2264             :     GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi  = 2249,
    2265             :     GLOBAL_ATOMIC_SMAX_X2_SADDR_vi      = 2250,
    2266             :     GLOBAL_ATOMIC_SMAX_X2_vi    = 2251,
    2267             :     GLOBAL_ATOMIC_SMAX_vi       = 2252,
    2268             :     GLOBAL_ATOMIC_SMIN  = 2253,
    2269             :     GLOBAL_ATOMIC_SMIN_RTN      = 2254,
    2270             :     GLOBAL_ATOMIC_SMIN_RTN_vi   = 2255,
    2271             :     GLOBAL_ATOMIC_SMIN_SADDR    = 2256,
    2272             :     GLOBAL_ATOMIC_SMIN_SADDR_RTN        = 2257,
    2273             :     GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi     = 2258,
    2274             :     GLOBAL_ATOMIC_SMIN_SADDR_vi = 2259,
    2275             :     GLOBAL_ATOMIC_SMIN_X2       = 2260,
    2276             :     GLOBAL_ATOMIC_SMIN_X2_RTN   = 2261,
    2277             :     GLOBAL_ATOMIC_SMIN_X2_RTN_vi        = 2262,
    2278             :     GLOBAL_ATOMIC_SMIN_X2_SADDR = 2263,
    2279             :     GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN     = 2264,
    2280             :     GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi  = 2265,
    2281             :     GLOBAL_ATOMIC_SMIN_X2_SADDR_vi      = 2266,
    2282             :     GLOBAL_ATOMIC_SMIN_X2_vi    = 2267,
    2283             :     GLOBAL_ATOMIC_SMIN_vi       = 2268,
    2284             :     GLOBAL_ATOMIC_SUB   = 2269,
    2285             :     GLOBAL_ATOMIC_SUB_RTN       = 2270,
    2286             :     GLOBAL_ATOMIC_SUB_RTN_vi    = 2271,
    2287             :     GLOBAL_ATOMIC_SUB_SADDR     = 2272,
    2288             :     GLOBAL_ATOMIC_SUB_SADDR_RTN = 2273,
    2289             :     GLOBAL_ATOMIC_SUB_SADDR_RTN_vi      = 2274,
    2290             :     GLOBAL_ATOMIC_SUB_SADDR_vi  = 2275,
    2291             :     GLOBAL_ATOMIC_SUB_X2        = 2276,
    2292             :     GLOBAL_ATOMIC_SUB_X2_RTN    = 2277,
    2293             :     GLOBAL_ATOMIC_SUB_X2_RTN_vi = 2278,
    2294             :     GLOBAL_ATOMIC_SUB_X2_SADDR  = 2279,
    2295             :     GLOBAL_ATOMIC_SUB_X2_SADDR_RTN      = 2280,
    2296             :     GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi   = 2281,
    2297             :     GLOBAL_ATOMIC_SUB_X2_SADDR_vi       = 2282,
    2298             :     GLOBAL_ATOMIC_SUB_X2_vi     = 2283,
    2299             :     GLOBAL_ATOMIC_SUB_vi        = 2284,
    2300             :     GLOBAL_ATOMIC_SWAP  = 2285,
    2301             :     GLOBAL_ATOMIC_SWAP_RTN      = 2286,
    2302             :     GLOBAL_ATOMIC_SWAP_RTN_vi   = 2287,
    2303             :     GLOBAL_ATOMIC_SWAP_SADDR    = 2288,
    2304             :     GLOBAL_ATOMIC_SWAP_SADDR_RTN        = 2289,
    2305             :     GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi     = 2290,
    2306             :     GLOBAL_ATOMIC_SWAP_SADDR_vi = 2291,
    2307             :     GLOBAL_ATOMIC_SWAP_X2       = 2292,
    2308             :     GLOBAL_ATOMIC_SWAP_X2_RTN   = 2293,
    2309             :     GLOBAL_ATOMIC_SWAP_X2_RTN_vi        = 2294,
    2310             :     GLOBAL_ATOMIC_SWAP_X2_SADDR = 2295,
    2311             :     GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN     = 2296,
    2312             :     GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi  = 2297,
    2313             :     GLOBAL_ATOMIC_SWAP_X2_SADDR_vi      = 2298,
    2314             :     GLOBAL_ATOMIC_SWAP_X2_vi    = 2299,
    2315             :     GLOBAL_ATOMIC_SWAP_vi       = 2300,
    2316             :     GLOBAL_ATOMIC_UMAX  = 2301,
    2317             :     GLOBAL_ATOMIC_UMAX_RTN      = 2302,
    2318             :     GLOBAL_ATOMIC_UMAX_RTN_vi   = 2303,
    2319             :     GLOBAL_ATOMIC_UMAX_SADDR    = 2304,
    2320             :     GLOBAL_ATOMIC_UMAX_SADDR_RTN        = 2305,
    2321             :     GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi     = 2306,
    2322             :     GLOBAL_ATOMIC_UMAX_SADDR_vi = 2307,
    2323             :     GLOBAL_ATOMIC_UMAX_X2       = 2308,
    2324             :     GLOBAL_ATOMIC_UMAX_X2_RTN   = 2309,
    2325             :     GLOBAL_ATOMIC_UMAX_X2_RTN_vi        = 2310,
    2326             :     GLOBAL_ATOMIC_UMAX_X2_SADDR = 2311,
    2327             :     GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN     = 2312,
    2328             :     GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi  = 2313,
    2329             :     GLOBAL_ATOMIC_UMAX_X2_SADDR_vi      = 2314,
    2330             :     GLOBAL_ATOMIC_UMAX_X2_vi    = 2315,
    2331             :     GLOBAL_ATOMIC_UMAX_vi       = 2316,
    2332             :     GLOBAL_ATOMIC_UMIN  = 2317,
    2333             :     GLOBAL_ATOMIC_UMIN_RTN      = 2318,
    2334             :     GLOBAL_ATOMIC_UMIN_RTN_vi   = 2319,
    2335             :     GLOBAL_ATOMIC_UMIN_SADDR    = 2320,
    2336             :     GLOBAL_ATOMIC_UMIN_SADDR_RTN        = 2321,
    2337             :     GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi     = 2322,
    2338             :     GLOBAL_ATOMIC_UMIN_SADDR_vi = 2323,
    2339             :     GLOBAL_ATOMIC_UMIN_X2       = 2324,
    2340             :     GLOBAL_ATOMIC_UMIN_X2_RTN   = 2325,
    2341             :     GLOBAL_ATOMIC_UMIN_X2_RTN_vi        = 2326,
    2342             :     GLOBAL_ATOMIC_UMIN_X2_SADDR = 2327,
    2343             :     GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN     = 2328,
    2344             :     GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi  = 2329,
    2345             :     GLOBAL_ATOMIC_UMIN_X2_SADDR_vi      = 2330,
    2346             :     GLOBAL_ATOMIC_UMIN_X2_vi    = 2331,
    2347             :     GLOBAL_ATOMIC_UMIN_vi       = 2332,
    2348             :     GLOBAL_ATOMIC_XOR   = 2333,
    2349             :     GLOBAL_ATOMIC_XOR_RTN       = 2334,
    2350             :     GLOBAL_ATOMIC_XOR_RTN_vi    = 2335,
    2351             :     GLOBAL_ATOMIC_XOR_SADDR     = 2336,
    2352             :     GLOBAL_ATOMIC_XOR_SADDR_RTN = 2337,
    2353             :     GLOBAL_ATOMIC_XOR_SADDR_RTN_vi      = 2338,
    2354             :     GLOBAL_ATOMIC_XOR_SADDR_vi  = 2339,
    2355             :     GLOBAL_ATOMIC_XOR_X2        = 2340,
    2356             :     GLOBAL_ATOMIC_XOR_X2_RTN    = 2341,
    2357             :     GLOBAL_ATOMIC_XOR_X2_RTN_vi = 2342,
    2358             :     GLOBAL_ATOMIC_XOR_X2_SADDR  = 2343,
    2359             :     GLOBAL_ATOMIC_XOR_X2_SADDR_RTN      = 2344,
    2360             :     GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi   = 2345,
    2361             :     GLOBAL_ATOMIC_XOR_X2_SADDR_vi       = 2346,
    2362             :     GLOBAL_ATOMIC_XOR_X2_vi     = 2347,
    2363             :     GLOBAL_ATOMIC_XOR_vi        = 2348,
    2364             :     GLOBAL_LOAD_DWORD   = 2349,
    2365             :     GLOBAL_LOAD_DWORDX2 = 2350,
    2366             :     GLOBAL_LOAD_DWORDX2_SADDR   = 2351,
    2367             :     GLOBAL_LOAD_DWORDX2_SADDR_vi        = 2352,
    2368             :     GLOBAL_LOAD_DWORDX2_vi      = 2353,
    2369             :     GLOBAL_LOAD_DWORDX3 = 2354,
    2370             :     GLOBAL_LOAD_DWORDX3_SADDR   = 2355,
    2371             :     GLOBAL_LOAD_DWORDX3_SADDR_vi        = 2356,
    2372             :     GLOBAL_LOAD_DWORDX3_vi      = 2357,
    2373             :     GLOBAL_LOAD_DWORDX4 = 2358,
    2374             :     GLOBAL_LOAD_DWORDX4_SADDR   = 2359,
    2375             :     GLOBAL_LOAD_DWORDX4_SADDR_vi        = 2360,
    2376             :     GLOBAL_LOAD_DWORDX4_vi      = 2361,
    2377             :     GLOBAL_LOAD_DWORD_SADDR     = 2362,
    2378             :     GLOBAL_LOAD_DWORD_SADDR_vi  = 2363,
    2379             :     GLOBAL_LOAD_DWORD_vi        = 2364,
    2380             :     GLOBAL_LOAD_SBYTE   = 2365,
    2381             :     GLOBAL_LOAD_SBYTE_D16       = 2366,
    2382             :     GLOBAL_LOAD_SBYTE_D16_HI    = 2367,
    2383             :     GLOBAL_LOAD_SBYTE_D16_HI_SADDR      = 2368,
    2384             :     GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi   = 2369,
    2385             :     GLOBAL_LOAD_SBYTE_D16_HI_vi = 2370,
    2386             :     GLOBAL_LOAD_SBYTE_D16_SADDR = 2371,
    2387             :     GLOBAL_LOAD_SBYTE_D16_SADDR_vi      = 2372,
    2388             :     GLOBAL_LOAD_SBYTE_D16_vi    = 2373,
    2389             :     GLOBAL_LOAD_SBYTE_SADDR     = 2374,
    2390             :     GLOBAL_LOAD_SBYTE_SADDR_vi  = 2375,
    2391             :     GLOBAL_LOAD_SBYTE_vi        = 2376,
    2392             :     GLOBAL_LOAD_SHORT_D16       = 2377,
    2393             :     GLOBAL_LOAD_SHORT_D16_HI    = 2378,
    2394             :     GLOBAL_LOAD_SHORT_D16_HI_SADDR      = 2379,
    2395             :     GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi   = 2380,
    2396             :     GLOBAL_LOAD_SHORT_D16_HI_vi = 2381,
    2397             :     GLOBAL_LOAD_SHORT_D16_SADDR = 2382,
    2398             :     GLOBAL_LOAD_SHORT_D16_SADDR_vi      = 2383,
    2399             :     GLOBAL_LOAD_SHORT_D16_vi    = 2384,
    2400             :     GLOBAL_LOAD_SSHORT  = 2385,
    2401             :     GLOBAL_LOAD_SSHORT_SADDR    = 2386,
    2402             :     GLOBAL_LOAD_SSHORT_SADDR_vi = 2387,
    2403             :     GLOBAL_LOAD_SSHORT_vi       = 2388,
    2404             :     GLOBAL_LOAD_UBYTE   = 2389,
    2405             :     GLOBAL_LOAD_UBYTE_D16       = 2390,
    2406             :     GLOBAL_LOAD_UBYTE_D16_HI    = 2391,
    2407             :     GLOBAL_LOAD_UBYTE_D16_HI_SADDR      = 2392,
    2408             :     GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi   = 2393,
    2409             :     GLOBAL_LOAD_UBYTE_D16_HI_vi = 2394,
    2410             :     GLOBAL_LOAD_UBYTE_D16_SADDR = 2395,
    2411             :     GLOBAL_LOAD_UBYTE_D16_SADDR_vi      = 2396,
    2412             :     GLOBAL_LOAD_UBYTE_D16_vi    = 2397,
    2413             :     GLOBAL_LOAD_UBYTE_SADDR     = 2398,
    2414             :     GLOBAL_LOAD_UBYTE_SADDR_vi  = 2399,
    2415             :     GLOBAL_LOAD_UBYTE_vi        = 2400,
    2416             :     GLOBAL_LOAD_USHORT  = 2401,
    2417             :     GLOBAL_LOAD_USHORT_SADDR    = 2402,
    2418             :     GLOBAL_LOAD_USHORT_SADDR_vi = 2403,
    2419             :     GLOBAL_LOAD_USHORT_vi       = 2404,
    2420             :     GLOBAL_STORE_BYTE   = 2405,
    2421             :     GLOBAL_STORE_BYTE_D16_HI    = 2406,
    2422             :     GLOBAL_STORE_BYTE_D16_HI_SADDR      = 2407,
    2423             :     GLOBAL_STORE_BYTE_D16_HI_SADDR_vi   = 2408,
    2424             :     GLOBAL_STORE_BYTE_D16_HI_vi = 2409,
    2425             :     GLOBAL_STORE_BYTE_SADDR     = 2410,
    2426             :     GLOBAL_STORE_BYTE_SADDR_vi  = 2411,
    2427             :     GLOBAL_STORE_BYTE_vi        = 2412,
    2428             :     GLOBAL_STORE_DWORD  = 2413,
    2429             :     GLOBAL_STORE_DWORDX2        = 2414,
    2430             :     GLOBAL_STORE_DWORDX2_SADDR  = 2415,
    2431             :     GLOBAL_STORE_DWORDX2_SADDR_vi       = 2416,
    2432             :     GLOBAL_STORE_DWORDX2_vi     = 2417,
    2433             :     GLOBAL_STORE_DWORDX3        = 2418,
    2434             :     GLOBAL_STORE_DWORDX3_SADDR  = 2419,
    2435             :     GLOBAL_STORE_DWORDX3_SADDR_vi       = 2420,
    2436             :     GLOBAL_STORE_DWORDX3_vi     = 2421,
    2437             :     GLOBAL_STORE_DWORDX4        = 2422,
    2438             :     GLOBAL_STORE_DWORDX4_SADDR  = 2423,
    2439             :     GLOBAL_STORE_DWORDX4_SADDR_vi       = 2424,
    2440             :     GLOBAL_STORE_DWORDX4_vi     = 2425,
    2441             :     GLOBAL_STORE_DWORD_SADDR    = 2426,
    2442             :     GLOBAL_STORE_DWORD_SADDR_vi = 2427,
    2443             :     GLOBAL_STORE_DWORD_vi       = 2428,
    2444             :     GLOBAL_STORE_SHORT  = 2429,
    2445             :     GLOBAL_STORE_SHORT_D16_HI   = 2430,
    2446             :     GLOBAL_STORE_SHORT_D16_HI_SADDR     = 2431,
    2447             :     GLOBAL_STORE_SHORT_D16_HI_SADDR_vi  = 2432,
    2448             :     GLOBAL_STORE_SHORT_D16_HI_vi        = 2433,
    2449             :     GLOBAL_STORE_SHORT_SADDR    = 2434,
    2450             :     GLOBAL_STORE_SHORT_SADDR_vi = 2435,
    2451             :     GLOBAL_STORE_SHORT_vi       = 2436,
    2452             :     GROUP_BARRIER       = 2437,
    2453             :     IFC_f32     = 2438,
    2454             :     IFC_i32     = 2439,
    2455             :     IF_LOGICALNZ_f32    = 2440,
    2456             :     IF_LOGICALNZ_i32    = 2441,
    2457             :     IF_LOGICALZ_f32     = 2442,
    2458             :     IF_LOGICALZ_i32     = 2443,
    2459             :     IF_PREDICATE_SET    = 2444,
    2460             :     IMAGE_ATOMIC_ADD_V1 = 2445,
    2461             :     IMAGE_ATOMIC_ADD_V1_si      = 2446,
    2462             :     IMAGE_ATOMIC_ADD_V1_vi      = 2447,
    2463             :     IMAGE_ATOMIC_ADD_V2 = 2448,
    2464             :     IMAGE_ATOMIC_ADD_V2_si      = 2449,
    2465             :     IMAGE_ATOMIC_ADD_V2_vi      = 2450,
    2466             :     IMAGE_ATOMIC_ADD_V4 = 2451,
    2467             :     IMAGE_ATOMIC_ADD_V4_si      = 2452,
    2468             :     IMAGE_ATOMIC_ADD_V4_vi      = 2453,
    2469             :     IMAGE_ATOMIC_AND_V1 = 2454,
    2470             :     IMAGE_ATOMIC_AND_V1_si      = 2455,
    2471             :     IMAGE_ATOMIC_AND_V1_vi      = 2456,
    2472             :     IMAGE_ATOMIC_AND_V2 = 2457,
    2473             :     IMAGE_ATOMIC_AND_V2_si      = 2458,
    2474             :     IMAGE_ATOMIC_AND_V2_vi      = 2459,
    2475             :     IMAGE_ATOMIC_AND_V4 = 2460,
    2476             :     IMAGE_ATOMIC_AND_V4_si      = 2461,
    2477             :     IMAGE_ATOMIC_AND_V4_vi      = 2462,
    2478             :     IMAGE_ATOMIC_CMPSWAP_V1     = 2463,
    2479             :     IMAGE_ATOMIC_CMPSWAP_V1_si  = 2464,
    2480             :     IMAGE_ATOMIC_CMPSWAP_V1_vi  = 2465,
    2481             :     IMAGE_ATOMIC_CMPSWAP_V2     = 2466,
    2482             :     IMAGE_ATOMIC_CMPSWAP_V2_si  = 2467,
    2483             :     IMAGE_ATOMIC_CMPSWAP_V2_vi  = 2468,
    2484             :     IMAGE_ATOMIC_CMPSWAP_V4     = 2469,
    2485             :     IMAGE_ATOMIC_CMPSWAP_V4_si  = 2470,
    2486             :     IMAGE_ATOMIC_CMPSWAP_V4_vi  = 2471,
    2487             :     IMAGE_ATOMIC_DEC_V1 = 2472,
    2488             :     IMAGE_ATOMIC_DEC_V1_si      = 2473,
    2489             :     IMAGE_ATOMIC_DEC_V1_vi      = 2474,
    2490             :     IMAGE_ATOMIC_DEC_V2 = 2475,
    2491             :     IMAGE_ATOMIC_DEC_V2_si      = 2476,
    2492             :     IMAGE_ATOMIC_DEC_V2_vi      = 2477,
    2493             :     IMAGE_ATOMIC_DEC_V4 = 2478,
    2494             :     IMAGE_ATOMIC_DEC_V4_si      = 2479,
    2495             :     IMAGE_ATOMIC_DEC_V4_vi      = 2480,
    2496             :     IMAGE_ATOMIC_INC_V1 = 2481,
    2497             :     IMAGE_ATOMIC_INC_V1_si      = 2482,
    2498             :     IMAGE_ATOMIC_INC_V1_vi      = 2483,
    2499             :     IMAGE_ATOMIC_INC_V2 = 2484,
    2500             :     IMAGE_ATOMIC_INC_V2_si      = 2485,
    2501             :     IMAGE_ATOMIC_INC_V2_vi      = 2486,
    2502             :     IMAGE_ATOMIC_INC_V4 = 2487,
    2503             :     IMAGE_ATOMIC_INC_V4_si      = 2488,
    2504             :     IMAGE_ATOMIC_INC_V4_vi      = 2489,
    2505             :     IMAGE_ATOMIC_OR_V1  = 2490,
    2506             :     IMAGE_ATOMIC_OR_V1_si       = 2491,
    2507             :     IMAGE_ATOMIC_OR_V1_vi       = 2492,
    2508             :     IMAGE_ATOMIC_OR_V2  = 2493,
    2509             :     IMAGE_ATOMIC_OR_V2_si       = 2494,
    2510             :     IMAGE_ATOMIC_OR_V2_vi       = 2495,
    2511             :     IMAGE_ATOMIC_OR_V4  = 2496,
    2512             :     IMAGE_ATOMIC_OR_V4_si       = 2497,
    2513             :     IMAGE_ATOMIC_OR_V4_vi       = 2498,
    2514             :     IMAGE_ATOMIC_SMAX_V1        = 2499,
    2515             :     IMAGE_ATOMIC_SMAX_V1_si     = 2500,
    2516             :     IMAGE_ATOMIC_SMAX_V1_vi     = 2501,
    2517             :     IMAGE_ATOMIC_SMAX_V2        = 2502,
    2518             :     IMAGE_ATOMIC_SMAX_V2_si     = 2503,
    2519             :     IMAGE_ATOMIC_SMAX_V2_vi     = 2504,
    2520             :     IMAGE_ATOMIC_SMAX_V4        = 2505,
    2521             :     IMAGE_ATOMIC_SMAX_V4_si     = 2506,
    2522             :     IMAGE_ATOMIC_SMAX_V4_vi     = 2507,
    2523             :     IMAGE_ATOMIC_SMIN_V1        = 2508,
    2524             :     IMAGE_ATOMIC_SMIN_V1_si     = 2509,
    2525             :     IMAGE_ATOMIC_SMIN_V1_vi     = 2510,
    2526             :     IMAGE_ATOMIC_SMIN_V2        = 2511,
    2527             :     IMAGE_ATOMIC_SMIN_V2_si     = 2512,
    2528             :     IMAGE_ATOMIC_SMIN_V2_vi     = 2513,
    2529             :     IMAGE_ATOMIC_SMIN_V4        = 2514,
    2530             :     IMAGE_ATOMIC_SMIN_V4_si     = 2515,
    2531             :     IMAGE_ATOMIC_SMIN_V4_vi     = 2516,
    2532             :     IMAGE_ATOMIC_SUB_V1 = 2517,
    2533             :     IMAGE_ATOMIC_SUB_V1_si      = 2518,
    2534             :     IMAGE_ATOMIC_SUB_V1_vi      = 2519,
    2535             :     IMAGE_ATOMIC_SUB_V2 = 2520,
    2536             :     IMAGE_ATOMIC_SUB_V2_si      = 2521,
    2537             :     IMAGE_ATOMIC_SUB_V2_vi      = 2522,
    2538             :     IMAGE_ATOMIC_SUB_V4 = 2523,
    2539             :     IMAGE_ATOMIC_SUB_V4_si      = 2524,
    2540             :     IMAGE_ATOMIC_SUB_V4_vi      = 2525,
    2541             :     IMAGE_ATOMIC_SWAP_V1        = 2526,
    2542             :     IMAGE_ATOMIC_SWAP_V1_si     = 2527,
    2543             :     IMAGE_ATOMIC_SWAP_V1_vi     = 2528,
    2544             :     IMAGE_ATOMIC_SWAP_V2        = 2529,
    2545             :     IMAGE_ATOMIC_SWAP_V2_si     = 2530,
    2546             :     IMAGE_ATOMIC_SWAP_V2_vi     = 2531,
    2547             :     IMAGE_ATOMIC_SWAP_V4        = 2532,
    2548             :     IMAGE_ATOMIC_SWAP_V4_si     = 2533,
    2549             :     IMAGE_ATOMIC_SWAP_V4_vi     = 2534,
    2550             :     IMAGE_ATOMIC_UMAX_V1        = 2535,
    2551             :     IMAGE_ATOMIC_UMAX_V1_si     = 2536,
    2552             :     IMAGE_ATOMIC_UMAX_V1_vi     = 2537,
    2553             :     IMAGE_ATOMIC_UMAX_V2        = 2538,
    2554             :     IMAGE_ATOMIC_UMAX_V2_si     = 2539,
    2555             :     IMAGE_ATOMIC_UMAX_V2_vi     = 2540,
    2556             :     IMAGE_ATOMIC_UMAX_V4        = 2541,
    2557             :     IMAGE_ATOMIC_UMAX_V4_si     = 2542,
    2558             :     IMAGE_ATOMIC_UMAX_V4_vi     = 2543,
    2559             :     IMAGE_ATOMIC_UMIN_V1        = 2544,
    2560             :     IMAGE_ATOMIC_UMIN_V1_si     = 2545,
    2561             :     IMAGE_ATOMIC_UMIN_V1_vi     = 2546,
    2562             :     IMAGE_ATOMIC_UMIN_V2        = 2547,
    2563             :     IMAGE_ATOMIC_UMIN_V2_si     = 2548,
    2564             :     IMAGE_ATOMIC_UMIN_V2_vi     = 2549,
    2565             :     IMAGE_ATOMIC_UMIN_V4        = 2550,
    2566             :     IMAGE_ATOMIC_UMIN_V4_si     = 2551,
    2567             :     IMAGE_ATOMIC_UMIN_V4_vi     = 2552,
    2568             :     IMAGE_ATOMIC_XOR_V1 = 2553,
    2569             :     IMAGE_ATOMIC_XOR_V1_si      = 2554,
    2570             :     IMAGE_ATOMIC_XOR_V1_vi      = 2555,
    2571             :     IMAGE_ATOMIC_XOR_V2 = 2556,
    2572             :     IMAGE_ATOMIC_XOR_V2_si      = 2557,
    2573             :     IMAGE_ATOMIC_XOR_V2_vi      = 2558,
    2574             :     IMAGE_ATOMIC_XOR_V4 = 2559,
    2575             :     IMAGE_ATOMIC_XOR_V4_si      = 2560,
    2576             :     IMAGE_ATOMIC_XOR_V4_vi      = 2561,
    2577             :     IMAGE_GATHER4_B_CL_O_V1_V1  = 2562,
    2578             :     IMAGE_GATHER4_B_CL_O_V1_V16 = 2563,
    2579             :     IMAGE_GATHER4_B_CL_O_V1_V2  = 2564,
    2580             :     IMAGE_GATHER4_B_CL_O_V1_V4  = 2565,
    2581             :     IMAGE_GATHER4_B_CL_O_V1_V8  = 2566,
    2582             :     IMAGE_GATHER4_B_CL_O_V2_V1  = 2567,
    2583             :     IMAGE_GATHER4_B_CL_O_V2_V16 = 2568,
    2584             :     IMAGE_GATHER4_B_CL_O_V2_V2  = 2569,
    2585             :     IMAGE_GATHER4_B_CL_O_V2_V4  = 2570,
    2586             :     IMAGE_GATHER4_B_CL_O_V2_V8  = 2571,
    2587             :     IMAGE_GATHER4_B_CL_O_V3_V1  = 2572,
    2588             :     IMAGE_GATHER4_B_CL_O_V3_V16 = 2573,
    2589             :     IMAGE_GATHER4_B_CL_O_V3_V2  = 2574,
    2590             :     IMAGE_GATHER4_B_CL_O_V3_V4  = 2575,
    2591             :     IMAGE_GATHER4_B_CL_O_V3_V8  = 2576,
    2592             :     IMAGE_GATHER4_B_CL_O_V4_V1  = 2577,
    2593             :     IMAGE_GATHER4_B_CL_O_V4_V16 = 2578,
    2594             :     IMAGE_GATHER4_B_CL_O_V4_V2  = 2579,
    2595             :     IMAGE_GATHER4_B_CL_O_V4_V4  = 2580,
    2596             :     IMAGE_GATHER4_B_CL_O_V4_V8  = 2581,
    2597             :     IMAGE_GATHER4_B_CL_V1_V1    = 2582,
    2598             :     IMAGE_GATHER4_B_CL_V1_V16   = 2583,
    2599             :     IMAGE_GATHER4_B_CL_V1_V2    = 2584,
    2600             :     IMAGE_GATHER4_B_CL_V1_V4    = 2585,
    2601             :     IMAGE_GATHER4_B_CL_V1_V8    = 2586,
    2602             :     IMAGE_GATHER4_B_CL_V2_V1    = 2587,
    2603             :     IMAGE_GATHER4_B_CL_V2_V16   = 2588,
    2604             :     IMAGE_GATHER4_B_CL_V2_V2    = 2589,
    2605             :     IMAGE_GATHER4_B_CL_V2_V4    = 2590,
    2606             :     IMAGE_GATHER4_B_CL_V2_V8    = 2591,
    2607             :     IMAGE_GATHER4_B_CL_V3_V1    = 2592,
    2608             :     IMAGE_GATHER4_B_CL_V3_V16   = 2593,
    2609             :     IMAGE_GATHER4_B_CL_V3_V2    = 2594,
    2610             :     IMAGE_GATHER4_B_CL_V3_V4    = 2595,
    2611             :     IMAGE_GATHER4_B_CL_V3_V8    = 2596,
    2612             :     IMAGE_GATHER4_B_CL_V4_V1    = 2597,
    2613             :     IMAGE_GATHER4_B_CL_V4_V16   = 2598,
    2614             :     IMAGE_GATHER4_B_CL_V4_V2    = 2599,
    2615             :     IMAGE_GATHER4_B_CL_V4_V4    = 2600,
    2616             :     IMAGE_GATHER4_B_CL_V4_V8    = 2601,
    2617             :     IMAGE_GATHER4_B_O_V1_V1     = 2602,
    2618             :     IMAGE_GATHER4_B_O_V1_V16    = 2603,
    2619             :     IMAGE_GATHER4_B_O_V1_V2     = 2604,
    2620             :     IMAGE_GATHER4_B_O_V1_V4     = 2605,
    2621             :     IMAGE_GATHER4_B_O_V1_V8     = 2606,
    2622             :     IMAGE_GATHER4_B_O_V2_V1     = 2607,
    2623             :     IMAGE_GATHER4_B_O_V2_V16    = 2608,
    2624             :     IMAGE_GATHER4_B_O_V2_V2     = 2609,
    2625             :     IMAGE_GATHER4_B_O_V2_V4     = 2610,
    2626             :     IMAGE_GATHER4_B_O_V2_V8     = 2611,
    2627             :     IMAGE_GATHER4_B_O_V3_V1     = 2612,
    2628             :     IMAGE_GATHER4_B_O_V3_V16    = 2613,
    2629             :     IMAGE_GATHER4_B_O_V3_V2     = 2614,
    2630             :     IMAGE_GATHER4_B_O_V3_V4     = 2615,
    2631             :     IMAGE_GATHER4_B_O_V3_V8     = 2616,
    2632             :     IMAGE_GATHER4_B_O_V4_V1     = 2617,
    2633             :     IMAGE_GATHER4_B_O_V4_V16    = 2618,
    2634             :     IMAGE_GATHER4_B_O_V4_V2     = 2619,
    2635             :     IMAGE_GATHER4_B_O_V4_V4     = 2620,
    2636             :     IMAGE_GATHER4_B_O_V4_V8     = 2621,
    2637             :     IMAGE_GATHER4_B_V1_V1       = 2622,
    2638             :     IMAGE_GATHER4_B_V1_V16      = 2623,
    2639             :     IMAGE_GATHER4_B_V1_V2       = 2624,
    2640             :     IMAGE_GATHER4_B_V1_V4       = 2625,
    2641             :     IMAGE_GATHER4_B_V1_V8       = 2626,
    2642             :     IMAGE_GATHER4_B_V2_V1       = 2627,
    2643             :     IMAGE_GATHER4_B_V2_V16      = 2628,
    2644             :     IMAGE_GATHER4_B_V2_V2       = 2629,
    2645             :     IMAGE_GATHER4_B_V2_V4       = 2630,
    2646             :     IMAGE_GATHER4_B_V2_V8       = 2631,
    2647             :     IMAGE_GATHER4_B_V3_V1       = 2632,
    2648             :     IMAGE_GATHER4_B_V3_V16      = 2633,
    2649             :     IMAGE_GATHER4_B_V3_V2       = 2634,
    2650             :     IMAGE_GATHER4_B_V3_V4       = 2635,
    2651             :     IMAGE_GATHER4_B_V3_V8       = 2636,
    2652             :     IMAGE_GATHER4_B_V4_V1       = 2637,
    2653             :     IMAGE_GATHER4_B_V4_V16      = 2638,
    2654             :     IMAGE_GATHER4_B_V4_V2       = 2639,
    2655             :     IMAGE_GATHER4_B_V4_V4       = 2640,
    2656             :     IMAGE_GATHER4_B_V4_V8       = 2641,
    2657             :     IMAGE_GATHER4_CL_O_V1_V1    = 2642,
    2658             :     IMAGE_GATHER4_CL_O_V1_V16   = 2643,
    2659             :     IMAGE_GATHER4_CL_O_V1_V2    = 2644,
    2660             :     IMAGE_GATHER4_CL_O_V1_V4    = 2645,
    2661             :     IMAGE_GATHER4_CL_O_V1_V8    = 2646,
    2662             :     IMAGE_GATHER4_CL_O_V2_V1    = 2647,
    2663             :     IMAGE_GATHER4_CL_O_V2_V16   = 2648,
    2664             :     IMAGE_GATHER4_CL_O_V2_V2    = 2649,
    2665             :     IMAGE_GATHER4_CL_O_V2_V4    = 2650,
    2666             :     IMAGE_GATHER4_CL_O_V2_V8    = 2651,
    2667             :     IMAGE_GATHER4_CL_O_V3_V1    = 2652,
    2668             :     IMAGE_GATHER4_CL_O_V3_V16   = 2653,
    2669             :     IMAGE_GATHER4_CL_O_V3_V2    = 2654,
    2670             :     IMAGE_GATHER4_CL_O_V3_V4    = 2655,
    2671             :     IMAGE_GATHER4_CL_O_V3_V8    = 2656,
    2672             :     IMAGE_GATHER4_CL_O_V4_V1    = 2657,
    2673             :     IMAGE_GATHER4_CL_O_V4_V16   = 2658,
    2674             :     IMAGE_GATHER4_CL_O_V4_V2    = 2659,
    2675             :     IMAGE_GATHER4_CL_O_V4_V4    = 2660,
    2676             :     IMAGE_GATHER4_CL_O_V4_V8    = 2661,
    2677             :     IMAGE_GATHER4_CL_V1_V1      = 2662,
    2678             :     IMAGE_GATHER4_CL_V1_V16     = 2663,
    2679             :     IMAGE_GATHER4_CL_V1_V2      = 2664,
    2680             :     IMAGE_GATHER4_CL_V1_V4      = 2665,
    2681             :     IMAGE_GATHER4_CL_V1_V8      = 2666,
    2682             :     IMAGE_GATHER4_CL_V2_V1      = 2667,
    2683             :     IMAGE_GATHER4_CL_V2_V16     = 2668,
    2684             :     IMAGE_GATHER4_CL_V2_V2      = 2669,
    2685             :     IMAGE_GATHER4_CL_V2_V4      = 2670,
    2686             :     IMAGE_GATHER4_CL_V2_V8      = 2671,
    2687             :     IMAGE_GATHER4_CL_V3_V1      = 2672,
    2688             :     IMAGE_GATHER4_CL_V3_V16     = 2673,
    2689             :     IMAGE_GATHER4_CL_V3_V2      = 2674,
    2690             :     IMAGE_GATHER4_CL_V3_V4      = 2675,
    2691             :     IMAGE_GATHER4_CL_V3_V8      = 2676,
    2692             :     IMAGE_GATHER4_CL_V4_V1      = 2677,
    2693             :     IMAGE_GATHER4_CL_V4_V16     = 2678,
    2694             :     IMAGE_GATHER4_CL_V4_V2      = 2679,
    2695             :     IMAGE_GATHER4_CL_V4_V4      = 2680,
    2696             :     IMAGE_GATHER4_CL_V4_V8      = 2681,
    2697             :     IMAGE_GATHER4_C_B_CL_O_V1_V1        = 2682,
    2698             :     IMAGE_GATHER4_C_B_CL_O_V1_V16       = 2683,
    2699             :     IMAGE_GATHER4_C_B_CL_O_V1_V2        = 2684,
    2700             :     IMAGE_GATHER4_C_B_CL_O_V1_V4        = 2685,
    2701             :     IMAGE_GATHER4_C_B_CL_O_V1_V8        = 2686,
    2702             :     IMAGE_GATHER4_C_B_CL_O_V2_V1        = 2687,
    2703             :     IMAGE_GATHER4_C_B_CL_O_V2_V16       = 2688,
    2704             :     IMAGE_GATHER4_C_B_CL_O_V2_V2        = 2689,
    2705             :     IMAGE_GATHER4_C_B_CL_O_V2_V4        = 2690,
    2706             :     IMAGE_GATHER4_C_B_CL_O_V2_V8        = 2691,
    2707             :     IMAGE_GATHER4_C_B_CL_O_V3_V1        = 2692,
    2708             :     IMAGE_GATHER4_C_B_CL_O_V3_V16       = 2693,
    2709             :     IMAGE_GATHER4_C_B_CL_O_V3_V2        = 2694,
    2710             :     IMAGE_GATHER4_C_B_CL_O_V3_V4        = 2695,
    2711             :     IMAGE_GATHER4_C_B_CL_O_V3_V8        = 2696,
    2712             :     IMAGE_GATHER4_C_B_CL_O_V4_V1        = 2697,
    2713             :     IMAGE_GATHER4_C_B_CL_O_V4_V16       = 2698,
    2714             :     IMAGE_GATHER4_C_B_CL_O_V4_V2        = 2699,
    2715             :     IMAGE_GATHER4_C_B_CL_O_V4_V4        = 2700,
    2716             :     IMAGE_GATHER4_C_B_CL_O_V4_V8        = 2701,
    2717             :     IMAGE_GATHER4_C_B_CL_V1_V1  = 2702,
    2718             :     IMAGE_GATHER4_C_B_CL_V1_V16 = 2703,
    2719             :     IMAGE_GATHER4_C_B_CL_V1_V2  = 2704,
    2720             :     IMAGE_GATHER4_C_B_CL_V1_V4  = 2705,
    2721             :     IMAGE_GATHER4_C_B_CL_V1_V8  = 2706,
    2722             :     IMAGE_GATHER4_C_B_CL_V2_V1  = 2707,
    2723             :     IMAGE_GATHER4_C_B_CL_V2_V16 = 2708,
    2724             :     IMAGE_GATHER4_C_B_CL_V2_V2  = 2709,
    2725             :     IMAGE_GATHER4_C_B_CL_V2_V4  = 2710,
    2726             :     IMAGE_GATHER4_C_B_CL_V2_V8  = 2711,
    2727             :     IMAGE_GATHER4_C_B_CL_V3_V1  = 2712,
    2728             :     IMAGE_GATHER4_C_B_CL_V3_V16 = 2713,
    2729             :     IMAGE_GATHER4_C_B_CL_V3_V2  = 2714,
    2730             :     IMAGE_GATHER4_C_B_CL_V3_V4  = 2715,
    2731             :     IMAGE_GATHER4_C_B_CL_V3_V8  = 2716,
    2732             :     IMAGE_GATHER4_C_B_CL_V4_V1  = 2717,
    2733             :     IMAGE_GATHER4_C_B_CL_V4_V16 = 2718,
    2734             :     IMAGE_GATHER4_C_B_CL_V4_V2  = 2719,
    2735             :     IMAGE_GATHER4_C_B_CL_V4_V4  = 2720,
    2736             :     IMAGE_GATHER4_C_B_CL_V4_V8  = 2721,
    2737             :     IMAGE_GATHER4_C_B_O_V1_V1   = 2722,
    2738             :     IMAGE_GATHER4_C_B_O_V1_V16  = 2723,
    2739             :     IMAGE_GATHER4_C_B_O_V1_V2   = 2724,
    2740             :     IMAGE_GATHER4_C_B_O_V1_V4   = 2725,
    2741             :     IMAGE_GATHER4_C_B_O_V1_V8   = 2726,
    2742             :     IMAGE_GATHER4_C_B_O_V2_V1   = 2727,
    2743             :     IMAGE_GATHER4_C_B_O_V2_V16  = 2728,
    2744             :     IMAGE_GATHER4_C_B_O_V2_V2   = 2729,
    2745             :     IMAGE_GATHER4_C_B_O_V2_V4   = 2730,
    2746             :     IMAGE_GATHER4_C_B_O_V2_V8   = 2731,
    2747             :     IMAGE_GATHER4_C_B_O_V3_V1   = 2732,
    2748             :     IMAGE_GATHER4_C_B_O_V3_V16  = 2733,
    2749             :     IMAGE_GATHER4_C_B_O_V3_V2   = 2734,
    2750             :     IMAGE_GATHER4_C_B_O_V3_V4   = 2735,
    2751             :     IMAGE_GATHER4_C_B_O_V3_V8   = 2736,
    2752             :     IMAGE_GATHER4_C_B_O_V4_V1   = 2737,
    2753             :     IMAGE_GATHER4_C_B_O_V4_V16  = 2738,
    2754             :     IMAGE_GATHER4_C_B_O_V4_V2   = 2739,
    2755             :     IMAGE_GATHER4_C_B_O_V4_V4   = 2740,
    2756             :     IMAGE_GATHER4_C_B_O_V4_V8   = 2741,
    2757             :     IMAGE_GATHER4_C_B_V1_V1     = 2742,
    2758             :     IMAGE_GATHER4_C_B_V1_V16    = 2743,
    2759             :     IMAGE_GATHER4_C_B_V1_V2     = 2744,
    2760             :     IMAGE_GATHER4_C_B_V1_V4     = 2745,
    2761             :     IMAGE_GATHER4_C_B_V1_V8     = 2746,
    2762             :     IMAGE_GATHER4_C_B_V2_V1     = 2747,
    2763             :     IMAGE_GATHER4_C_B_V2_V16    = 2748,
    2764             :     IMAGE_GATHER4_C_B_V2_V2     = 2749,
    2765             :     IMAGE_GATHER4_C_B_V2_V4     = 2750,
    2766             :     IMAGE_GATHER4_C_B_V2_V8     = 2751,
    2767             :     IMAGE_GATHER4_C_B_V3_V1     = 2752,
    2768             :     IMAGE_GATHER4_C_B_V3_V16    = 2753,
    2769             :     IMAGE_GATHER4_C_B_V3_V2     = 2754,
    2770             :     IMAGE_GATHER4_C_B_V3_V4     = 2755,
    2771             :     IMAGE_GATHER4_C_B_V3_V8     = 2756,
    2772             :     IMAGE_GATHER4_C_B_V4_V1     = 2757,
    2773             :     IMAGE_GATHER4_C_B_V4_V16    = 2758,
    2774             :     IMAGE_GATHER4_C_B_V4_V2     = 2759,
    2775             :     IMAGE_GATHER4_C_B_V4_V4     = 2760,
    2776             :     IMAGE_GATHER4_C_B_V4_V8     = 2761,
    2777             :     IMAGE_GATHER4_C_CL_O_V1_V1  = 2762,
    2778             :     IMAGE_GATHER4_C_CL_O_V1_V16 = 2763,
    2779             :     IMAGE_GATHER4_C_CL_O_V1_V2  = 2764,
    2780             :     IMAGE_GATHER4_C_CL_O_V1_V4  = 2765,
    2781             :     IMAGE_GATHER4_C_CL_O_V1_V8  = 2766,
    2782             :     IMAGE_GATHER4_C_CL_O_V2_V1  = 2767,
    2783             :     IMAGE_GATHER4_C_CL_O_V2_V16 = 2768,
    2784             :     IMAGE_GATHER4_C_CL_O_V2_V2  = 2769,
    2785             :     IMAGE_GATHER4_C_CL_O_V2_V4  = 2770,
    2786             :     IMAGE_GATHER4_C_CL_O_V2_V8  = 2771,
    2787             :     IMAGE_GATHER4_C_CL_O_V3_V1  = 2772,
    2788             :     IMAGE_GATHER4_C_CL_O_V3_V16 = 2773,
    2789             :     IMAGE_GATHER4_C_CL_O_V3_V2  = 2774,
    2790             :     IMAGE_GATHER4_C_CL_O_V3_V4  = 2775,
    2791             :     IMAGE_GATHER4_C_CL_O_V3_V8  = 2776,
    2792             :     IMAGE_GATHER4_C_CL_O_V4_V1  = 2777,
    2793             :     IMAGE_GATHER4_C_CL_O_V4_V16 = 2778,
    2794             :     IMAGE_GATHER4_C_CL_O_V4_V2  = 2779,
    2795             :     IMAGE_GATHER4_C_CL_O_V4_V4  = 2780,
    2796             :     IMAGE_GATHER4_C_CL_O_V4_V8  = 2781,
    2797             :     IMAGE_GATHER4_C_CL_V1_V1    = 2782,
    2798             :     IMAGE_GATHER4_C_CL_V1_V16   = 2783,
    2799             :     IMAGE_GATHER4_C_CL_V1_V2    = 2784,
    2800             :     IMAGE_GATHER4_C_CL_V1_V4    = 2785,
    2801             :     IMAGE_GATHER4_C_CL_V1_V8    = 2786,
    2802             :     IMAGE_GATHER4_C_CL_V2_V1    = 2787,
    2803             :     IMAGE_GATHER4_C_CL_V2_V16   = 2788,
    2804             :     IMAGE_GATHER4_C_CL_V2_V2    = 2789,
    2805             :     IMAGE_GATHER4_C_CL_V2_V4    = 2790,
    2806             :     IMAGE_GATHER4_C_CL_V2_V8    = 2791,
    2807             :     IMAGE_GATHER4_C_CL_V3_V1    = 2792,
    2808             :     IMAGE_GATHER4_C_CL_V3_V16   = 2793,
    2809             :     IMAGE_GATHER4_C_CL_V3_V2    = 2794,
    2810             :     IMAGE_GATHER4_C_CL_V3_V4    = 2795,
    2811             :     IMAGE_GATHER4_C_CL_V3_V8    = 2796,
    2812             :     IMAGE_GATHER4_C_CL_V4_V1    = 2797,
    2813             :     IMAGE_GATHER4_C_CL_V4_V16   = 2798,
    2814             :     IMAGE_GATHER4_C_CL_V4_V2    = 2799,
    2815             :     IMAGE_GATHER4_C_CL_V4_V4    = 2800,
    2816             :     IMAGE_GATHER4_C_CL_V4_V8    = 2801,
    2817             :     IMAGE_GATHER4_C_LZ_O_V1_V1  = 2802,
    2818             :     IMAGE_GATHER4_C_LZ_O_V1_V16 = 2803,
    2819             :     IMAGE_GATHER4_C_LZ_O_V1_V2  = 2804,
    2820             :     IMAGE_GATHER4_C_LZ_O_V1_V4  = 2805,
    2821             :     IMAGE_GATHER4_C_LZ_O_V1_V8  = 2806,
    2822             :     IMAGE_GATHER4_C_LZ_O_V2_V1  = 2807,
    2823             :     IMAGE_GATHER4_C_LZ_O_V2_V16 = 2808,
    2824             :     IMAGE_GATHER4_C_LZ_O_V2_V2  = 2809,
    2825             :     IMAGE_GATHER4_C_LZ_O_V2_V4  = 2810,
    2826             :     IMAGE_GATHER4_C_LZ_O_V2_V8  = 2811,
    2827             :     IMAGE_GATHER4_C_LZ_O_V3_V1  = 2812,
    2828             :     IMAGE_GATHER4_C_LZ_O_V3_V16 = 2813,
    2829             :     IMAGE_GATHER4_C_LZ_O_V3_V2  = 2814,
    2830             :     IMAGE_GATHER4_C_LZ_O_V3_V4  = 2815,
    2831             :     IMAGE_GATHER4_C_LZ_O_V3_V8  = 2816,
    2832             :     IMAGE_GATHER4_C_LZ_O_V4_V1  = 2817,
    2833             :     IMAGE_GATHER4_C_LZ_O_V4_V16 = 2818,
    2834             :     IMAGE_GATHER4_C_LZ_O_V4_V2  = 2819,
    2835             :     IMAGE_GATHER4_C_LZ_O_V4_V4  = 2820,
    2836             :     IMAGE_GATHER4_C_LZ_O_V4_V8  = 2821,
    2837             :     IMAGE_GATHER4_C_LZ_V1_V1    = 2822,
    2838             :     IMAGE_GATHER4_C_LZ_V1_V16   = 2823,
    2839             :     IMAGE_GATHER4_C_LZ_V1_V2    = 2824,
    2840             :     IMAGE_GATHER4_C_LZ_V1_V4    = 2825,
    2841             :     IMAGE_GATHER4_C_LZ_V1_V8    = 2826,
    2842             :     IMAGE_GATHER4_C_LZ_V2_V1    = 2827,
    2843             :     IMAGE_GATHER4_C_LZ_V2_V16   = 2828,
    2844             :     IMAGE_GATHER4_C_LZ_V2_V2    = 2829,
    2845             :     IMAGE_GATHER4_C_LZ_V2_V4    = 2830,
    2846             :     IMAGE_GATHER4_C_LZ_V2_V8    = 2831,
    2847             :     IMAGE_GATHER4_C_LZ_V3_V1    = 2832,
    2848             :     IMAGE_GATHER4_C_LZ_V3_V16   = 2833,
    2849             :     IMAGE_GATHER4_C_LZ_V3_V2    = 2834,
    2850             :     IMAGE_GATHER4_C_LZ_V3_V4    = 2835,
    2851             :     IMAGE_GATHER4_C_LZ_V3_V8    = 2836,
    2852             :     IMAGE_GATHER4_C_LZ_V4_V1    = 2837,
    2853             :     IMAGE_GATHER4_C_LZ_V4_V16   = 2838,
    2854             :     IMAGE_GATHER4_C_LZ_V4_V2    = 2839,
    2855             :     IMAGE_GATHER4_C_LZ_V4_V4    = 2840,
    2856             :     IMAGE_GATHER4_C_LZ_V4_V8    = 2841,
    2857             :     IMAGE_GATHER4_C_L_O_V1_V1   = 2842,
    2858             :     IMAGE_GATHER4_C_L_O_V1_V16  = 2843,
    2859             :     IMAGE_GATHER4_C_L_O_V1_V2   = 2844,
    2860             :     IMAGE_GATHER4_C_L_O_V1_V4   = 2845,
    2861             :     IMAGE_GATHER4_C_L_O_V1_V8   = 2846,
    2862             :     IMAGE_GATHER4_C_L_O_V2_V1   = 2847,
    2863             :     IMAGE_GATHER4_C_L_O_V2_V16  = 2848,
    2864             :     IMAGE_GATHER4_C_L_O_V2_V2   = 2849,
    2865             :     IMAGE_GATHER4_C_L_O_V2_V4   = 2850,
    2866             :     IMAGE_GATHER4_C_L_O_V2_V8   = 2851,
    2867             :     IMAGE_GATHER4_C_L_O_V3_V1   = 2852,
    2868             :     IMAGE_GATHER4_C_L_O_V3_V16  = 2853,
    2869             :     IMAGE_GATHER4_C_L_O_V3_V2   = 2854,
    2870             :     IMAGE_GATHER4_C_L_O_V3_V4   = 2855,
    2871             :     IMAGE_GATHER4_C_L_O_V3_V8   = 2856,
    2872             :     IMAGE_GATHER4_C_L_O_V4_V1   = 2857,
    2873             :     IMAGE_GATHER4_C_L_O_V4_V16  = 2858,
    2874             :     IMAGE_GATHER4_C_L_O_V4_V2   = 2859,
    2875             :     IMAGE_GATHER4_C_L_O_V4_V4   = 2860,
    2876             :     IMAGE_GATHER4_C_L_O_V4_V8   = 2861,
    2877             :     IMAGE_GATHER4_C_L_V1_V1     = 2862,
    2878             :     IMAGE_GATHER4_C_L_V1_V16    = 2863,
    2879             :     IMAGE_GATHER4_C_L_V1_V2     = 2864,
    2880             :     IMAGE_GATHER4_C_L_V1_V4     = 2865,
    2881             :     IMAGE_GATHER4_C_L_V1_V8     = 2866,
    2882             :     IMAGE_GATHER4_C_L_V2_V1     = 2867,
    2883             :     IMAGE_GATHER4_C_L_V2_V16    = 2868,
    2884             :     IMAGE_GATHER4_C_L_V2_V2     = 2869,
    2885             :     IMAGE_GATHER4_C_L_V2_V4     = 2870,
    2886             :     IMAGE_GATHER4_C_L_V2_V8     = 2871,
    2887             :     IMAGE_GATHER4_C_L_V3_V1     = 2872,
    2888             :     IMAGE_GATHER4_C_L_V3_V16    = 2873,
    2889             :     IMAGE_GATHER4_C_L_V3_V2     = 2874,
    2890             :     IMAGE_GATHER4_C_L_V3_V4     = 2875,
    2891             :     IMAGE_GATHER4_C_L_V3_V8     = 2876,
    2892             :     IMAGE_GATHER4_C_L_V4_V1     = 2877,
    2893             :     IMAGE_GATHER4_C_L_V4_V16    = 2878,
    2894             :     IMAGE_GATHER4_C_L_V4_V2     = 2879,
    2895             :     IMAGE_GATHER4_C_L_V4_V4     = 2880,
    2896             :     IMAGE_GATHER4_C_L_V4_V8     = 2881,
    2897             :     IMAGE_GATHER4_C_O_V1_V1     = 2882,
    2898             :     IMAGE_GATHER4_C_O_V1_V16    = 2883,
    2899             :     IMAGE_GATHER4_C_O_V1_V2     = 2884,
    2900             :     IMAGE_GATHER4_C_O_V1_V4     = 2885,
    2901             :     IMAGE_GATHER4_C_O_V1_V8     = 2886,
    2902             :     IMAGE_GATHER4_C_O_V2_V1     = 2887,
    2903             :     IMAGE_GATHER4_C_O_V2_V16    = 2888,
    2904             :     IMAGE_GATHER4_C_O_V2_V2     = 2889,
    2905             :     IMAGE_GATHER4_C_O_V2_V4     = 2890,
    2906             :     IMAGE_GATHER4_C_O_V2_V8     = 2891,
    2907             :     IMAGE_GATHER4_C_O_V3_V1     = 2892,
    2908             :     IMAGE_GATHER4_C_O_V3_V16    = 2893,
    2909             :     IMAGE_GATHER4_C_O_V3_V2     = 2894,
    2910             :     IMAGE_GATHER4_C_O_V3_V4     = 2895,
    2911             :     IMAGE_GATHER4_C_O_V3_V8     = 2896,
    2912             :     IMAGE_GATHER4_C_O_V4_V1     = 2897,
    2913             :     IMAGE_GATHER4_C_O_V4_V16    = 2898,
    2914             :     IMAGE_GATHER4_C_O_V4_V2     = 2899,
    2915             :     IMAGE_GATHER4_C_O_V4_V4     = 2900,
    2916             :     IMAGE_GATHER4_C_O_V4_V8     = 2901,
    2917             :     IMAGE_GATHER4_C_V1_V1       = 2902,
    2918             :     IMAGE_GATHER4_C_V1_V16      = 2903,
    2919             :     IMAGE_GATHER4_C_V1_V2       = 2904,
    2920             :     IMAGE_GATHER4_C_V1_V4       = 2905,
    2921             :     IMAGE_GATHER4_C_V1_V8       = 2906,
    2922             :     IMAGE_GATHER4_C_V2_V1       = 2907,
    2923             :     IMAGE_GATHER4_C_V2_V16      = 2908,
    2924             :     IMAGE_GATHER4_C_V2_V2       = 2909,
    2925             :     IMAGE_GATHER4_C_V2_V4       = 2910,
    2926             :     IMAGE_GATHER4_C_V2_V8       = 2911,
    2927             :     IMAGE_GATHER4_C_V3_V1       = 2912,
    2928             :     IMAGE_GATHER4_C_V3_V16      = 2913,
    2929             :     IMAGE_GATHER4_C_V3_V2       = 2914,
    2930             :     IMAGE_GATHER4_C_V3_V4       = 2915,
    2931             :     IMAGE_GATHER4_C_V3_V8       = 2916,
    2932             :     IMAGE_GATHER4_C_V4_V1       = 2917,
    2933             :     IMAGE_GATHER4_C_V4_V16      = 2918,
    2934             :     IMAGE_GATHER4_C_V4_V2       = 2919,
    2935             :     IMAGE_GATHER4_C_V4_V4       = 2920,
    2936             :     IMAGE_GATHER4_C_V4_V8       = 2921,
    2937             :     IMAGE_GATHER4_LZ_O_V1_V1    = 2922,
    2938             :     IMAGE_GATHER4_LZ_O_V1_V16   = 2923,
    2939             :     IMAGE_GATHER4_LZ_O_V1_V2    = 2924,
    2940             :     IMAGE_GATHER4_LZ_O_V1_V4    = 2925,
    2941             :     IMAGE_GATHER4_LZ_O_V1_V8    = 2926,
    2942             :     IMAGE_GATHER4_LZ_O_V2_V1    = 2927,
    2943             :     IMAGE_GATHER4_LZ_O_V2_V16   = 2928,
    2944             :     IMAGE_GATHER4_LZ_O_V2_V2    = 2929,
    2945             :     IMAGE_GATHER4_LZ_O_V2_V4    = 2930,
    2946             :     IMAGE_GATHER4_LZ_O_V2_V8    = 2931,
    2947             :     IMAGE_GATHER4_LZ_O_V3_V1    = 2932,
    2948             :     IMAGE_GATHER4_LZ_O_V3_V16   = 2933,
    2949             :     IMAGE_GATHER4_LZ_O_V3_V2    = 2934,
    2950             :     IMAGE_GATHER4_LZ_O_V3_V4    = 2935,
    2951             :     IMAGE_GATHER4_LZ_O_V3_V8    = 2936,
    2952             :     IMAGE_GATHER4_LZ_O_V4_V1    = 2937,
    2953             :     IMAGE_GATHER4_LZ_O_V4_V16   = 2938,
    2954             :     IMAGE_GATHER4_LZ_O_V4_V2    = 2939,
    2955             :     IMAGE_GATHER4_LZ_O_V4_V4    = 2940,
    2956             :     IMAGE_GATHER4_LZ_O_V4_V8    = 2941,
    2957             :     IMAGE_GATHER4_LZ_V1_V1      = 2942,
    2958             :     IMAGE_GATHER4_LZ_V1_V16     = 2943,
    2959             :     IMAGE_GATHER4_LZ_V1_V2      = 2944,
    2960             :     IMAGE_GATHER4_LZ_V1_V4      = 2945,
    2961             :     IMAGE_GATHER4_LZ_V1_V8      = 2946,
    2962             :     IMAGE_GATHER4_LZ_V2_V1      = 2947,
    2963             :     IMAGE_GATHER4_LZ_V2_V16     = 2948,
    2964             :     IMAGE_GATHER4_LZ_V2_V2      = 2949,
    2965             :     IMAGE_GATHER4_LZ_V2_V4      = 2950,
    2966             :     IMAGE_GATHER4_LZ_V2_V8      = 2951,
    2967             :     IMAGE_GATHER4_LZ_V3_V1      = 2952,
    2968             :     IMAGE_GATHER4_LZ_V3_V16     = 2953,
    2969             :     IMAGE_GATHER4_LZ_V3_V2      = 2954,
    2970             :     IMAGE_GATHER4_LZ_V3_V4      = 2955,
    2971             :     IMAGE_GATHER4_LZ_V3_V8      = 2956,
    2972             :     IMAGE_GATHER4_LZ_V4_V1      = 2957,
    2973             :     IMAGE_GATHER4_LZ_V4_V16     = 2958,
    2974             :     IMAGE_GATHER4_LZ_V4_V2      = 2959,
    2975             :     IMAGE_GATHER4_LZ_V4_V4      = 2960,
    2976             :     IMAGE_GATHER4_LZ_V4_V8      = 2961,
    2977             :     IMAGE_GATHER4_L_O_V1_V1     = 2962,
    2978             :     IMAGE_GATHER4_L_O_V1_V16    = 2963,
    2979             :     IMAGE_GATHER4_L_O_V1_V2     = 2964,
    2980             :     IMAGE_GATHER4_L_O_V1_V4     = 2965,
    2981             :     IMAGE_GATHER4_L_O_V1_V8     = 2966,
    2982             :     IMAGE_GATHER4_L_O_V2_V1     = 2967,
    2983             :     IMAGE_GATHER4_L_O_V2_V16    = 2968,
    2984             :     IMAGE_GATHER4_L_O_V2_V2     = 2969,
    2985             :     IMAGE_GATHER4_L_O_V2_V4     = 2970,
    2986             :     IMAGE_GATHER4_L_O_V2_V8     = 2971,
    2987             :     IMAGE_GATHER4_L_O_V3_V1     = 2972,
    2988             :     IMAGE_GATHER4_L_O_V3_V16    = 2973,
    2989             :     IMAGE_GATHER4_L_O_V3_V2     = 2974,
    2990             :     IMAGE_GATHER4_L_O_V3_V4     = 2975,
    2991             :     IMAGE_GATHER4_L_O_V3_V8     = 2976,
    2992             :     IMAGE_GATHER4_L_O_V4_V1     = 2977,
    2993             :     IMAGE_GATHER4_L_O_V4_V16    = 2978,
    2994             :     IMAGE_GATHER4_L_O_V4_V2     = 2979,
    2995             :     IMAGE_GATHER4_L_O_V4_V4     = 2980,
    2996             :     IMAGE_GATHER4_L_O_V4_V8     = 2981,
    2997             :     IMAGE_GATHER4_L_V1_V1       = 2982,
    2998             :     IMAGE_GATHER4_L_V1_V16      = 2983,
    2999             :     IMAGE_GATHER4_L_V1_V2       = 2984,
    3000             :     IMAGE_GATHER4_L_V1_V4       = 2985,
    3001             :     IMAGE_GATHER4_L_V1_V8       = 2986,
    3002             :     IMAGE_GATHER4_L_V2_V1       = 2987,
    3003             :     IMAGE_GATHER4_L_V2_V16      = 2988,
    3004             :     IMAGE_GATHER4_L_V2_V2       = 2989,
    3005             :     IMAGE_GATHER4_L_V2_V4       = 2990,
    3006             :     IMAGE_GATHER4_L_V2_V8       = 2991,
    3007             :     IMAGE_GATHER4_L_V3_V1       = 2992,
    3008             :     IMAGE_GATHER4_L_V3_V16      = 2993,
    3009             :     IMAGE_GATHER4_L_V3_V2       = 2994,
    3010             :     IMAGE_GATHER4_L_V3_V4       = 2995,
    3011             :     IMAGE_GATHER4_L_V3_V8       = 2996,
    3012             :     IMAGE_GATHER4_L_V4_V1       = 2997,
    3013             :     IMAGE_GATHER4_L_V4_V16      = 2998,
    3014             :     IMAGE_GATHER4_L_V4_V2       = 2999,
    3015             :     IMAGE_GATHER4_L_V4_V4       = 3000,
    3016             :     IMAGE_GATHER4_L_V4_V8       = 3001,
    3017             :     IMAGE_GATHER4_O_V1_V1       = 3002,
    3018             :     IMAGE_GATHER4_O_V1_V16      = 3003,
    3019             :     IMAGE_GATHER4_O_V1_V2       = 3004,
    3020             :     IMAGE_GATHER4_O_V1_V4       = 3005,
    3021             :     IMAGE_GATHER4_O_V1_V8       = 3006,
    3022             :     IMAGE_GATHER4_O_V2_V1       = 3007,
    3023             :     IMAGE_GATHER4_O_V2_V16      = 3008,
    3024             :     IMAGE_GATHER4_O_V2_V2       = 3009,
    3025             :     IMAGE_GATHER4_O_V2_V4       = 3010,
    3026             :     IMAGE_GATHER4_O_V2_V8       = 3011,
    3027             :     IMAGE_GATHER4_O_V3_V1       = 3012,
    3028             :     IMAGE_GATHER4_O_V3_V16      = 3013,
    3029             :     IMAGE_GATHER4_O_V3_V2       = 3014,
    3030             :     IMAGE_GATHER4_O_V3_V4       = 3015,
    3031             :     IMAGE_GATHER4_O_V3_V8       = 3016,
    3032             :     IMAGE_GATHER4_O_V4_V1       = 3017,
    3033             :     IMAGE_GATHER4_O_V4_V16      = 3018,
    3034             :     IMAGE_GATHER4_O_V4_V2       = 3019,
    3035             :     IMAGE_GATHER4_O_V4_V4       = 3020,
    3036             :     IMAGE_GATHER4_O_V4_V8       = 3021,
    3037             :     IMAGE_GATHER4_V1_V1 = 3022,
    3038             :     IMAGE_GATHER4_V1_V16        = 3023,
    3039             :     IMAGE_GATHER4_V1_V2 = 3024,
    3040             :     IMAGE_GATHER4_V1_V4 = 3025,
    3041             :     IMAGE_GATHER4_V1_V8 = 3026,
    3042             :     IMAGE_GATHER4_V2_V1 = 3027,
    3043             :     IMAGE_GATHER4_V2_V16        = 3028,
    3044             :     IMAGE_GATHER4_V2_V2 = 3029,
    3045             :     IMAGE_GATHER4_V2_V4 = 3030,
    3046             :     IMAGE_GATHER4_V2_V8 = 3031,
    3047             :     IMAGE_GATHER4_V3_V1 = 3032,
    3048             :     IMAGE_GATHER4_V3_V16        = 3033,
    3049             :     IMAGE_GATHER4_V3_V2 = 3034,
    3050             :     IMAGE_GATHER4_V3_V4 = 3035,
    3051             :     IMAGE_GATHER4_V3_V8 = 3036,
    3052             :     IMAGE_GATHER4_V4_V1 = 3037,
    3053             :     IMAGE_GATHER4_V4_V16        = 3038,
    3054             :     IMAGE_GATHER4_V4_V2 = 3039,
    3055             :     IMAGE_GATHER4_V4_V4 = 3040,
    3056             :     IMAGE_GATHER4_V4_V8 = 3041,
    3057             :     IMAGE_GET_LOD_V1_V1 = 3042,
    3058             :     IMAGE_GET_LOD_V1_V16        = 3043,
    3059             :     IMAGE_GET_LOD_V1_V2 = 3044,
    3060             :     IMAGE_GET_LOD_V1_V4 = 3045,
    3061             :     IMAGE_GET_LOD_V1_V8 = 3046,
    3062             :     IMAGE_GET_LOD_V2_V1 = 3047,
    3063             :     IMAGE_GET_LOD_V2_V16        = 3048,
    3064             :     IMAGE_GET_LOD_V2_V2 = 3049,
    3065             :     IMAGE_GET_LOD_V2_V4 = 3050,
    3066             :     IMAGE_GET_LOD_V2_V8 = 3051,
    3067             :     IMAGE_GET_LOD_V3_V1 = 3052,
    3068             :     IMAGE_GET_LOD_V3_V16        = 3053,
    3069             :     IMAGE_GET_LOD_V3_V2 = 3054,
    3070             :     IMAGE_GET_LOD_V3_V4 = 3055,
    3071             :     IMAGE_GET_LOD_V3_V8 = 3056,
    3072             :     IMAGE_GET_LOD_V4_V1 = 3057,
    3073             :     IMAGE_GET_LOD_V4_V16        = 3058,
    3074             :     IMAGE_GET_LOD_V4_V2 = 3059,
    3075             :     IMAGE_GET_LOD_V4_V4 = 3060,
    3076             :     IMAGE_GET_LOD_V4_V8 = 3061,
    3077             :     IMAGE_GET_RESINFO_V1_V1     = 3062,
    3078             :     IMAGE_GET_RESINFO_V1_V2     = 3063,
    3079             :     IMAGE_GET_RESINFO_V1_V4     = 3064,
    3080             :     IMAGE_GET_RESINFO_V2_V1     = 3065,
    3081             :     IMAGE_GET_RESINFO_V2_V2     = 3066,
    3082             :     IMAGE_GET_RESINFO_V2_V4     = 3067,
    3083             :     IMAGE_GET_RESINFO_V3_V1     = 3068,
    3084             :     IMAGE_GET_RESINFO_V3_V2     = 3069,
    3085             :     IMAGE_GET_RESINFO_V3_V4     = 3070,
    3086             :     IMAGE_GET_RESINFO_V4_V1     = 3071,
    3087             :     IMAGE_GET_RESINFO_V4_V2     = 3072,
    3088             :     IMAGE_GET_RESINFO_V4_V4     = 3073,
    3089             :     IMAGE_LOAD_MIP_V1_V1        = 3074,
    3090             :     IMAGE_LOAD_MIP_V1_V2        = 3075,
    3091             :     IMAGE_LOAD_MIP_V1_V4        = 3076,
    3092             :     IMAGE_LOAD_MIP_V2_V1        = 3077,
    3093             :     IMAGE_LOAD_MIP_V2_V2        = 3078,
    3094             :     IMAGE_LOAD_MIP_V2_V4        = 3079,
    3095             :     IMAGE_LOAD_MIP_V3_V1        = 3080,
    3096             :     IMAGE_LOAD_MIP_V3_V2        = 3081,
    3097             :     IMAGE_LOAD_MIP_V3_V4        = 3082,
    3098             :     IMAGE_LOAD_MIP_V4_V1        = 3083,
    3099             :     IMAGE_LOAD_MIP_V4_V2        = 3084,
    3100             :     IMAGE_LOAD_MIP_V4_V4        = 3085,
    3101             :     IMAGE_LOAD_V1_V1    = 3086,
    3102             :     IMAGE_LOAD_V1_V2    = 3087,
    3103             :     IMAGE_LOAD_V1_V4    = 3088,
    3104             :     IMAGE_LOAD_V2_V1    = 3089,
    3105             :     IMAGE_LOAD_V2_V2    = 3090,
    3106             :     IMAGE_LOAD_V2_V4    = 3091,
    3107             :     IMAGE_LOAD_V3_V1    = 3092,
    3108             :     IMAGE_LOAD_V3_V2    = 3093,
    3109             :     IMAGE_LOAD_V3_V4    = 3094,
    3110             :     IMAGE_LOAD_V4_V1    = 3095,
    3111             :     IMAGE_LOAD_V4_V2    = 3096,
    3112             :     IMAGE_LOAD_V4_V4    = 3097,
    3113             :     IMAGE_SAMPLE_B_CL_O_V1_V1   = 3098,
    3114             :     IMAGE_SAMPLE_B_CL_O_V1_V16  = 3099,
    3115             :     IMAGE_SAMPLE_B_CL_O_V1_V2   = 3100,
    3116             :     IMAGE_SAMPLE_B_CL_O_V1_V4   = 3101,
    3117             :     IMAGE_SAMPLE_B_CL_O_V1_V8   = 3102,
    3118             :     IMAGE_SAMPLE_B_CL_O_V2_V1   = 3103,
    3119             :     IMAGE_SAMPLE_B_CL_O_V2_V16  = 3104,
    3120             :     IMAGE_SAMPLE_B_CL_O_V2_V2   = 3105,
    3121             :     IMAGE_SAMPLE_B_CL_O_V2_V4   = 3106,
    3122             :     IMAGE_SAMPLE_B_CL_O_V2_V8   = 3107,
    3123             :     IMAGE_SAMPLE_B_CL_O_V3_V1   = 3108,
    3124             :     IMAGE_SAMPLE_B_CL_O_V3_V16  = 3109,
    3125             :     IMAGE_SAMPLE_B_CL_O_V3_V2   = 3110,
    3126             :     IMAGE_SAMPLE_B_CL_O_V3_V4   = 3111,
    3127             :     IMAGE_SAMPLE_B_CL_O_V3_V8   = 3112,
    3128             :     IMAGE_SAMPLE_B_CL_O_V4_V1   = 3113,
    3129             :     IMAGE_SAMPLE_B_CL_O_V4_V16  = 3114,
    3130             :     IMAGE_SAMPLE_B_CL_O_V4_V2   = 3115,
    3131             :     IMAGE_SAMPLE_B_CL_O_V4_V4   = 3116,
    3132             :     IMAGE_SAMPLE_B_CL_O_V4_V8   = 3117,
    3133             :     IMAGE_SAMPLE_B_CL_V1_V1     = 3118,
    3134             :     IMAGE_SAMPLE_B_CL_V1_V16    = 3119,
    3135             :     IMAGE_SAMPLE_B_CL_V1_V2     = 3120,
    3136             :     IMAGE_SAMPLE_B_CL_V1_V4     = 3121,
    3137             :     IMAGE_SAMPLE_B_CL_V1_V8     = 3122,
    3138             :     IMAGE_SAMPLE_B_CL_V2_V1     = 3123,
    3139             :     IMAGE_SAMPLE_B_CL_V2_V16    = 3124,
    3140             :     IMAGE_SAMPLE_B_CL_V2_V2     = 3125,
    3141             :     IMAGE_SAMPLE_B_CL_V2_V4     = 3126,
    3142             :     IMAGE_SAMPLE_B_CL_V2_V8     = 3127,
    3143             :     IMAGE_SAMPLE_B_CL_V3_V1     = 3128,
    3144             :     IMAGE_SAMPLE_B_CL_V3_V16    = 3129,
    3145             :     IMAGE_SAMPLE_B_CL_V3_V2     = 3130,
    3146             :     IMAGE_SAMPLE_B_CL_V3_V4     = 3131,
    3147             :     IMAGE_SAMPLE_B_CL_V3_V8     = 3132,
    3148             :     IMAGE_SAMPLE_B_CL_V4_V1     = 3133,
    3149             :     IMAGE_SAMPLE_B_CL_V4_V16    = 3134,
    3150             :     IMAGE_SAMPLE_B_CL_V4_V2     = 3135,
    3151             :     IMAGE_SAMPLE_B_CL_V4_V4     = 3136,
    3152             :     IMAGE_SAMPLE_B_CL_V4_V8     = 3137,
    3153             :     IMAGE_SAMPLE_B_O_V1_V1      = 3138,
    3154             :     IMAGE_SAMPLE_B_O_V1_V16     = 3139,
    3155             :     IMAGE_SAMPLE_B_O_V1_V2      = 3140,
    3156             :     IMAGE_SAMPLE_B_O_V1_V4      = 3141,
    3157             :     IMAGE_SAMPLE_B_O_V1_V8      = 3142,
    3158             :     IMAGE_SAMPLE_B_O_V2_V1      = 3143,
    3159             :     IMAGE_SAMPLE_B_O_V2_V16     = 3144,
    3160             :     IMAGE_SAMPLE_B_O_V2_V2      = 3145,
    3161             :     IMAGE_SAMPLE_B_O_V2_V4      = 3146,
    3162             :     IMAGE_SAMPLE_B_O_V2_V8      = 3147,
    3163             :     IMAGE_SAMPLE_B_O_V3_V1      = 3148,
    3164             :     IMAGE_SAMPLE_B_O_V3_V16     = 3149,
    3165             :     IMAGE_SAMPLE_B_O_V3_V2      = 3150,
    3166             :     IMAGE_SAMPLE_B_O_V3_V4      = 3151,
    3167             :     IMAGE_SAMPLE_B_O_V3_V8      = 3152,
    3168             :     IMAGE_SAMPLE_B_O_V4_V1      = 3153,
    3169             :     IMAGE_SAMPLE_B_O_V4_V16     = 3154,
    3170             :     IMAGE_SAMPLE_B_O_V4_V2      = 3155,
    3171             :     IMAGE_SAMPLE_B_O_V4_V4      = 3156,
    3172             :     IMAGE_SAMPLE_B_O_V4_V8      = 3157,
    3173             :     IMAGE_SAMPLE_B_V1_V1        = 3158,
    3174             :     IMAGE_SAMPLE_B_V1_V16       = 3159,
    3175             :     IMAGE_SAMPLE_B_V1_V2        = 3160,
    3176             :     IMAGE_SAMPLE_B_V1_V4        = 3161,
    3177             :     IMAGE_SAMPLE_B_V1_V8        = 3162,
    3178             :     IMAGE_SAMPLE_B_V2_V1        = 3163,
    3179             :     IMAGE_SAMPLE_B_V2_V16       = 3164,
    3180             :     IMAGE_SAMPLE_B_V2_V2        = 3165,
    3181             :     IMAGE_SAMPLE_B_V2_V4        = 3166,
    3182             :     IMAGE_SAMPLE_B_V2_V8        = 3167,
    3183             :     IMAGE_SAMPLE_B_V3_V1        = 3168,
    3184             :     IMAGE_SAMPLE_B_V3_V16       = 3169,
    3185             :     IMAGE_SAMPLE_B_V3_V2        = 3170,
    3186             :     IMAGE_SAMPLE_B_V3_V4        = 3171,
    3187             :     IMAGE_SAMPLE_B_V3_V8        = 3172,
    3188             :     IMAGE_SAMPLE_B_V4_V1        = 3173,
    3189             :     IMAGE_SAMPLE_B_V4_V16       = 3174,
    3190             :     IMAGE_SAMPLE_B_V4_V2        = 3175,
    3191             :     IMAGE_SAMPLE_B_V4_V4        = 3176,
    3192             :     IMAGE_SAMPLE_B_V4_V8        = 3177,
    3193             :     IMAGE_SAMPLE_CD_CL_O_V1_V1  = 3178,
    3194             :     IMAGE_SAMPLE_CD_CL_O_V1_V16 = 3179,
    3195             :     IMAGE_SAMPLE_CD_CL_O_V1_V2  = 3180,
    3196             :     IMAGE_SAMPLE_CD_CL_O_V1_V4  = 3181,
    3197             :     IMAGE_SAMPLE_CD_CL_O_V1_V8  = 3182,
    3198             :     IMAGE_SAMPLE_CD_CL_O_V2_V1  = 3183,
    3199             :     IMAGE_SAMPLE_CD_CL_O_V2_V16 = 3184,
    3200             :     IMAGE_SAMPLE_CD_CL_O_V2_V2  = 3185,
    3201             :     IMAGE_SAMPLE_CD_CL_O_V2_V4  = 3186,
    3202             :     IMAGE_SAMPLE_CD_CL_O_V2_V8  = 3187,
    3203             :     IMAGE_SAMPLE_CD_CL_O_V3_V1  = 3188,
    3204             :     IMAGE_SAMPLE_CD_CL_O_V3_V16 = 3189,
    3205             :     IMAGE_SAMPLE_CD_CL_O_V3_V2  = 3190,
    3206             :     IMAGE_SAMPLE_CD_CL_O_V3_V4  = 3191,
    3207             :     IMAGE_SAMPLE_CD_CL_O_V3_V8  = 3192,
    3208             :     IMAGE_SAMPLE_CD_CL_O_V4_V1  = 3193,
    3209             :     IMAGE_SAMPLE_CD_CL_O_V4_V16 = 3194,
    3210             :     IMAGE_SAMPLE_CD_CL_O_V4_V2  = 3195,
    3211             :     IMAGE_SAMPLE_CD_CL_O_V4_V4  = 3196,
    3212             :     IMAGE_SAMPLE_CD_CL_O_V4_V8  = 3197,
    3213             :     IMAGE_SAMPLE_CD_CL_V1_V1    = 3198,
    3214             :     IMAGE_SAMPLE_CD_CL_V1_V16   = 3199,
    3215             :     IMAGE_SAMPLE_CD_CL_V1_V2    = 3200,
    3216             :     IMAGE_SAMPLE_CD_CL_V1_V4    = 3201,
    3217             :     IMAGE_SAMPLE_CD_CL_V1_V8    = 3202,
    3218             :     IMAGE_SAMPLE_CD_CL_V2_V1    = 3203,
    3219             :     IMAGE_SAMPLE_CD_CL_V2_V16   = 3204,
    3220             :     IMAGE_SAMPLE_CD_CL_V2_V2    = 3205,
    3221             :     IMAGE_SAMPLE_CD_CL_V2_V4    = 3206,
    3222             :     IMAGE_SAMPLE_CD_CL_V2_V8    = 3207,
    3223             :     IMAGE_SAMPLE_CD_CL_V3_V1    = 3208,
    3224             :     IMAGE_SAMPLE_CD_CL_V3_V16   = 3209,
    3225             :     IMAGE_SAMPLE_CD_CL_V3_V2    = 3210,
    3226             :     IMAGE_SAMPLE_CD_CL_V3_V4    = 3211,
    3227             :     IMAGE_SAMPLE_CD_CL_V3_V8    = 3212,
    3228             :     IMAGE_SAMPLE_CD_CL_V4_V1    = 3213,
    3229             :     IMAGE_SAMPLE_CD_CL_V4_V16   = 3214,
    3230             :     IMAGE_SAMPLE_CD_CL_V4_V2    = 3215,
    3231             :     IMAGE_SAMPLE_CD_CL_V4_V4    = 3216,
    3232             :     IMAGE_SAMPLE_CD_CL_V4_V8    = 3217,
    3233             :     IMAGE_SAMPLE_CD_O_V1_V1     = 3218,
    3234             :     IMAGE_SAMPLE_CD_O_V1_V16    = 3219,
    3235             :     IMAGE_SAMPLE_CD_O_V1_V2     = 3220,
    3236             :     IMAGE_SAMPLE_CD_O_V1_V4     = 3221,
    3237             :     IMAGE_SAMPLE_CD_O_V1_V8     = 3222,
    3238             :     IMAGE_SAMPLE_CD_O_V2_V1     = 3223,
    3239             :     IMAGE_SAMPLE_CD_O_V2_V16    = 3224,
    3240             :     IMAGE_SAMPLE_CD_O_V2_V2     = 3225,
    3241             :     IMAGE_SAMPLE_CD_O_V2_V4     = 3226,
    3242             :     IMAGE_SAMPLE_CD_O_V2_V8     = 3227,
    3243             :     IMAGE_SAMPLE_CD_O_V3_V1     = 3228,
    3244             :     IMAGE_SAMPLE_CD_O_V3_V16    = 3229,
    3245             :     IMAGE_SAMPLE_CD_O_V3_V2     = 3230,
    3246             :     IMAGE_SAMPLE_CD_O_V3_V4     = 3231,
    3247             :     IMAGE_SAMPLE_CD_O_V3_V8     = 3232,
    3248             :     IMAGE_SAMPLE_CD_O_V4_V1     = 3233,
    3249             :     IMAGE_SAMPLE_CD_O_V4_V16    = 3234,
    3250             :     IMAGE_SAMPLE_CD_O_V4_V2     = 3235,
    3251             :     IMAGE_SAMPLE_CD_O_V4_V4     = 3236,
    3252             :     IMAGE_SAMPLE_CD_O_V4_V8     = 3237,
    3253             :     IMAGE_SAMPLE_CD_V1_V1       = 3238,
    3254             :     IMAGE_SAMPLE_CD_V1_V16      = 3239,
    3255             :     IMAGE_SAMPLE_CD_V1_V2       = 3240,
    3256             :     IMAGE_SAMPLE_CD_V1_V4       = 3241,
    3257             :     IMAGE_SAMPLE_CD_V1_V8       = 3242,
    3258             :     IMAGE_SAMPLE_CD_V2_V1       = 3243,
    3259             :     IMAGE_SAMPLE_CD_V2_V16      = 3244,
    3260             :     IMAGE_SAMPLE_CD_V2_V2       = 3245,
    3261             :     IMAGE_SAMPLE_CD_V2_V4       = 3246,
    3262             :     IMAGE_SAMPLE_CD_V2_V8       = 3247,
    3263             :     IMAGE_SAMPLE_CD_V3_V1       = 3248,
    3264             :     IMAGE_SAMPLE_CD_V3_V16      = 3249,
    3265             :     IMAGE_SAMPLE_CD_V3_V2       = 3250,
    3266             :     IMAGE_SAMPLE_CD_V3_V4       = 3251,
    3267             :     IMAGE_SAMPLE_CD_V3_V8       = 3252,
    3268             :     IMAGE_SAMPLE_CD_V4_V1       = 3253,
    3269             :     IMAGE_SAMPLE_CD_V4_V16      = 3254,
    3270             :     IMAGE_SAMPLE_CD_V4_V2       = 3255,
    3271             :     IMAGE_SAMPLE_CD_V4_V4       = 3256,
    3272             :     IMAGE_SAMPLE_CD_V4_V8       = 3257,
    3273             :     IMAGE_SAMPLE_CL_O_V1_V1     = 3258,
    3274             :     IMAGE_SAMPLE_CL_O_V1_V16    = 3259,
    3275             :     IMAGE_SAMPLE_CL_O_V1_V2     = 3260,
    3276             :     IMAGE_SAMPLE_CL_O_V1_V4     = 3261,
    3277             :     IMAGE_SAMPLE_CL_O_V1_V8     = 3262,
    3278             :     IMAGE_SAMPLE_CL_O_V2_V1     = 3263,
    3279             :     IMAGE_SAMPLE_CL_O_V2_V16    = 3264,
    3280             :     IMAGE_SAMPLE_CL_O_V2_V2     = 3265,
    3281             :     IMAGE_SAMPLE_CL_O_V2_V4     = 3266,
    3282             :     IMAGE_SAMPLE_CL_O_V2_V8     = 3267,
    3283             :     IMAGE_SAMPLE_CL_O_V3_V1     = 3268,
    3284             :     IMAGE_SAMPLE_CL_O_V3_V16    = 3269,
    3285             :     IMAGE_SAMPLE_CL_O_V3_V2     = 3270,
    3286             :     IMAGE_SAMPLE_CL_O_V3_V4     = 3271,
    3287             :     IMAGE_SAMPLE_CL_O_V3_V8     = 3272,
    3288             :     IMAGE_SAMPLE_CL_O_V4_V1     = 3273,
    3289             :     IMAGE_SAMPLE_CL_O_V4_V16    = 3274,
    3290             :     IMAGE_SAMPLE_CL_O_V4_V2     = 3275,
    3291             :     IMAGE_SAMPLE_CL_O_V4_V4     = 3276,
    3292             :     IMAGE_SAMPLE_CL_O_V4_V8     = 3277,
    3293             :     IMAGE_SAMPLE_CL_V1_V1       = 3278,
    3294             :     IMAGE_SAMPLE_CL_V1_V16      = 3279,
    3295             :     IMAGE_SAMPLE_CL_V1_V2       = 3280,
    3296             :     IMAGE_SAMPLE_CL_V1_V4       = 3281,
    3297             :     IMAGE_SAMPLE_CL_V1_V8       = 3282,
    3298             :     IMAGE_SAMPLE_CL_V2_V1       = 3283,
    3299             :     IMAGE_SAMPLE_CL_V2_V16      = 3284,
    3300             :     IMAGE_SAMPLE_CL_V2_V2       = 3285,
    3301             :     IMAGE_SAMPLE_CL_V2_V4       = 3286,
    3302             :     IMAGE_SAMPLE_CL_V2_V8       = 3287,
    3303             :     IMAGE_SAMPLE_CL_V3_V1       = 3288,
    3304             :     IMAGE_SAMPLE_CL_V3_V16      = 3289,
    3305             :     IMAGE_SAMPLE_CL_V3_V2       = 3290,
    3306             :     IMAGE_SAMPLE_CL_V3_V4       = 3291,
    3307             :     IMAGE_SAMPLE_CL_V3_V8       = 3292,
    3308             :     IMAGE_SAMPLE_CL_V4_V1       = 3293,
    3309             :     IMAGE_SAMPLE_CL_V4_V16      = 3294,
    3310             :     IMAGE_SAMPLE_CL_V4_V2       = 3295,
    3311             :     IMAGE_SAMPLE_CL_V4_V4       = 3296,
    3312             :     IMAGE_SAMPLE_CL_V4_V8       = 3297,
    3313             :     IMAGE_SAMPLE_C_B_CL_O_V1_V1 = 3298,
    3314             :     IMAGE_SAMPLE_C_B_CL_O_V1_V16        = 3299,
    3315             :     IMAGE_SAMPLE_C_B_CL_O_V1_V2 = 3300,
    3316             :     IMAGE_SAMPLE_C_B_CL_O_V1_V4 = 3301,
    3317             :     IMAGE_SAMPLE_C_B_CL_O_V1_V8 = 3302,
    3318             :     IMAGE_SAMPLE_C_B_CL_O_V2_V1 = 3303,
    3319             :     IMAGE_SAMPLE_C_B_CL_O_V2_V16        = 3304,
    3320             :     IMAGE_SAMPLE_C_B_CL_O_V2_V2 = 3305,
    3321             :     IMAGE_SAMPLE_C_B_CL_O_V2_V4 = 3306,
    3322             :     IMAGE_SAMPLE_C_B_CL_O_V2_V8 = 3307,
    3323             :     IMAGE_SAMPLE_C_B_CL_O_V3_V1 = 3308,
    3324             :     IMAGE_SAMPLE_C_B_CL_O_V3_V16        = 3309,
    3325             :     IMAGE_SAMPLE_C_B_CL_O_V3_V2 = 3310,
    3326             :     IMAGE_SAMPLE_C_B_CL_O_V3_V4 = 3311,
    3327             :     IMAGE_SAMPLE_C_B_CL_O_V3_V8 = 3312,
    3328             :     IMAGE_SAMPLE_C_B_CL_O_V4_V1 = 3313,
    3329             :     IMAGE_SAMPLE_C_B_CL_O_V4_V16        = 3314,
    3330             :     IMAGE_SAMPLE_C_B_CL_O_V4_V2 = 3315,
    3331             :     IMAGE_SAMPLE_C_B_CL_O_V4_V4 = 3316,
    3332             :     IMAGE_SAMPLE_C_B_CL_O_V4_V8 = 3317,
    3333             :     IMAGE_SAMPLE_C_B_CL_V1_V1   = 3318,
    3334             :     IMAGE_SAMPLE_C_B_CL_V1_V16  = 3319,
    3335             :     IMAGE_SAMPLE_C_B_CL_V1_V2   = 3320,
    3336             :     IMAGE_SAMPLE_C_B_CL_V1_V4   = 3321,
    3337             :     IMAGE_SAMPLE_C_B_CL_V1_V8   = 3322,
    3338             :     IMAGE_SAMPLE_C_B_CL_V2_V1   = 3323,
    3339             :     IMAGE_SAMPLE_C_B_CL_V2_V16  = 3324,
    3340             :     IMAGE_SAMPLE_C_B_CL_V2_V2   = 3325,
    3341             :     IMAGE_SAMPLE_C_B_CL_V2_V4   = 3326,
    3342             :     IMAGE_SAMPLE_C_B_CL_V2_V8   = 3327,
    3343             :     IMAGE_SAMPLE_C_B_CL_V3_V1   = 3328,
    3344             :     IMAGE_SAMPLE_C_B_CL_V3_V16  = 3329,
    3345             :     IMAGE_SAMPLE_C_B_CL_V3_V2   = 3330,
    3346             :     IMAGE_SAMPLE_C_B_CL_V3_V4   = 3331,
    3347             :     IMAGE_SAMPLE_C_B_CL_V3_V8   = 3332,
    3348             :     IMAGE_SAMPLE_C_B_CL_V4_V1   = 3333,
    3349             :     IMAGE_SAMPLE_C_B_CL_V4_V16  = 3334,
    3350             :     IMAGE_SAMPLE_C_B_CL_V4_V2   = 3335,
    3351             :     IMAGE_SAMPLE_C_B_CL_V4_V4   = 3336,
    3352             :     IMAGE_SAMPLE_C_B_CL_V4_V8   = 3337,
    3353             :     IMAGE_SAMPLE_C_B_O_V1_V1    = 3338,
    3354             :     IMAGE_SAMPLE_C_B_O_V1_V16   = 3339,
    3355             :     IMAGE_SAMPLE_C_B_O_V1_V2    = 3340,
    3356             :     IMAGE_SAMPLE_C_B_O_V1_V4    = 3341,
    3357             :     IMAGE_SAMPLE_C_B_O_V1_V8    = 3342,
    3358             :     IMAGE_SAMPLE_C_B_O_V2_V1    = 3343,
    3359             :     IMAGE_SAMPLE_C_B_O_V2_V16   = 3344,
    3360             :     IMAGE_SAMPLE_C_B_O_V2_V2    = 3345,
    3361             :     IMAGE_SAMPLE_C_B_O_V2_V4    = 3346,
    3362             :     IMAGE_SAMPLE_C_B_O_V2_V8    = 3347,
    3363             :     IMAGE_SAMPLE_C_B_O_V3_V1    = 3348,
    3364             :     IMAGE_SAMPLE_C_B_O_V3_V16   = 3349,
    3365             :     IMAGE_SAMPLE_C_B_O_V3_V2    = 3350,
    3366             :     IMAGE_SAMPLE_C_B_O_V3_V4    = 3351,
    3367             :     IMAGE_SAMPLE_C_B_O_V3_V8    = 3352,
    3368             :     IMAGE_SAMPLE_C_B_O_V4_V1    = 3353,
    3369             :     IMAGE_SAMPLE_C_B_O_V4_V16   = 3354,
    3370             :     IMAGE_SAMPLE_C_B_O_V4_V2    = 3355,
    3371             :     IMAGE_SAMPLE_C_B_O_V4_V4    = 3356,
    3372             :     IMAGE_SAMPLE_C_B_O_V4_V8    = 3357,
    3373             :     IMAGE_SAMPLE_C_B_V1_V1      = 3358,
    3374             :     IMAGE_SAMPLE_C_B_V1_V16     = 3359,
    3375             :     IMAGE_SAMPLE_C_B_V1_V2      = 3360,
    3376             :     IMAGE_SAMPLE_C_B_V1_V4      = 3361,
    3377             :     IMAGE_SAMPLE_C_B_V1_V8      = 3362,
    3378             :     IMAGE_SAMPLE_C_B_V2_V1      = 3363,
    3379             :     IMAGE_SAMPLE_C_B_V2_V16     = 3364,
    3380             :     IMAGE_SAMPLE_C_B_V2_V2      = 3365,
    3381             :     IMAGE_SAMPLE_C_B_V2_V4      = 3366,
    3382             :     IMAGE_SAMPLE_C_B_V2_V8      = 3367,
    3383             :     IMAGE_SAMPLE_C_B_V3_V1      = 3368,
    3384             :     IMAGE_SAMPLE_C_B_V3_V16     = 3369,
    3385             :     IMAGE_SAMPLE_C_B_V3_V2      = 3370,
    3386             :     IMAGE_SAMPLE_C_B_V3_V4      = 3371,
    3387             :     IMAGE_SAMPLE_C_B_V3_V8      = 3372,
    3388             :     IMAGE_SAMPLE_C_B_V4_V1      = 3373,
    3389             :     IMAGE_SAMPLE_C_B_V4_V16     = 3374,
    3390             :     IMAGE_SAMPLE_C_B_V4_V2      = 3375,
    3391             :     IMAGE_SAMPLE_C_B_V4_V4      = 3376,
    3392             :     IMAGE_SAMPLE_C_B_V4_V8      = 3377,
    3393             :     IMAGE_SAMPLE_C_CD_CL_O_V1_V1        = 3378,
    3394             :     IMAGE_SAMPLE_C_CD_CL_O_V1_V16       = 3379,
    3395             :     IMAGE_SAMPLE_C_CD_CL_O_V1_V2        = 3380,
    3396             :     IMAGE_SAMPLE_C_CD_CL_O_V1_V4        = 3381,
    3397             :     IMAGE_SAMPLE_C_CD_CL_O_V1_V8        = 3382,
    3398             :     IMAGE_SAMPLE_C_CD_CL_O_V2_V1        = 3383,
    3399             :     IMAGE_SAMPLE_C_CD_CL_O_V2_V16       = 3384,
    3400             :     IMAGE_SAMPLE_C_CD_CL_O_V2_V2        = 3385,
    3401             :     IMAGE_SAMPLE_C_CD_CL_O_V2_V4        = 3386,
    3402             :     IMAGE_SAMPLE_C_CD_CL_O_V2_V8        = 3387,
    3403             :     IMAGE_SAMPLE_C_CD_CL_O_V3_V1        = 3388,
    3404             :     IMAGE_SAMPLE_C_CD_CL_O_V3_V16       = 3389,
    3405             :     IMAGE_SAMPLE_C_CD_CL_O_V3_V2        = 3390,
    3406             :     IMAGE_SAMPLE_C_CD_CL_O_V3_V4        = 3391,
    3407             :     IMAGE_SAMPLE_C_CD_CL_O_V3_V8        = 3392,
    3408             :     IMAGE_SAMPLE_C_CD_CL_O_V4_V1        = 3393,
    3409             :     IMAGE_SAMPLE_C_CD_CL_O_V4_V16       = 3394,
    3410             :     IMAGE_SAMPLE_C_CD_CL_O_V4_V2        = 3395,
    3411             :     IMAGE_SAMPLE_C_CD_CL_O_V4_V4        = 3396,
    3412             :     IMAGE_SAMPLE_C_CD_CL_O_V4_V8        = 3397,
    3413             :     IMAGE_SAMPLE_C_CD_CL_V1_V1  = 3398,
    3414             :     IMAGE_SAMPLE_C_CD_CL_V1_V16 = 3399,
    3415             :     IMAGE_SAMPLE_C_CD_CL_V1_V2  = 3400,
    3416             :     IMAGE_SAMPLE_C_CD_CL_V1_V4  = 3401,
    3417             :     IMAGE_SAMPLE_C_CD_CL_V1_V8  = 3402,
    3418             :     IMAGE_SAMPLE_C_CD_CL_V2_V1  = 3403,
    3419             :     IMAGE_SAMPLE_C_CD_CL_V2_V16 = 3404,
    3420             :     IMAGE_SAMPLE_C_CD_CL_V2_V2  = 3405,
    3421             :     IMAGE_SAMPLE_C_CD_CL_V2_V4  = 3406,
    3422             :     IMAGE_SAMPLE_C_CD_CL_V2_V8  = 3407,
    3423             :     IMAGE_SAMPLE_C_CD_CL_V3_V1  = 3408,
    3424             :     IMAGE_SAMPLE_C_CD_CL_V3_V16 = 3409,
    3425             :     IMAGE_SAMPLE_C_CD_CL_V3_V2  = 3410,
    3426             :     IMAGE_SAMPLE_C_CD_CL_V3_V4  = 3411,
    3427             :     IMAGE_SAMPLE_C_CD_CL_V3_V8  = 3412,
    3428             :     IMAGE_SAMPLE_C_CD_CL_V4_V1  = 3413,
    3429             :     IMAGE_SAMPLE_C_CD_CL_V4_V16 = 3414,
    3430             :     IMAGE_SAMPLE_C_CD_CL_V4_V2  = 3415,
    3431             :     IMAGE_SAMPLE_C_CD_CL_V4_V4  = 3416,
    3432             :     IMAGE_SAMPLE_C_CD_CL_V4_V8  = 3417,
    3433             :     IMAGE_SAMPLE_C_CD_O_V1_V1   = 3418,
    3434             :     IMAGE_SAMPLE_C_CD_O_V1_V16  = 3419,
    3435             :     IMAGE_SAMPLE_C_CD_O_V1_V2   = 3420,
    3436             :     IMAGE_SAMPLE_C_CD_O_V1_V4   = 3421,
    3437             :     IMAGE_SAMPLE_C_CD_O_V1_V8   = 3422,
    3438             :     IMAGE_SAMPLE_C_CD_O_V2_V1   = 3423,
    3439             :     IMAGE_SAMPLE_C_CD_O_V2_V16  = 3424,
    3440             :     IMAGE_SAMPLE_C_CD_O_V2_V2   = 3425,
    3441             :     IMAGE_SAMPLE_C_CD_O_V2_V4   = 3426,
    3442             :     IMAGE_SAMPLE_C_CD_O_V2_V8   = 3427,
    3443             :     IMAGE_SAMPLE_C_CD_O_V3_V1   = 3428,
    3444             :     IMAGE_SAMPLE_C_CD_O_V3_V16  = 3429,
    3445             :     IMAGE_SAMPLE_C_CD_O_V3_V2   = 3430,
    3446             :     IMAGE_SAMPLE_C_CD_O_V3_V4   = 3431,
    3447             :     IMAGE_SAMPLE_C_CD_O_V3_V8   = 3432,
    3448             :     IMAGE_SAMPLE_C_CD_O_V4_V1   = 3433,
    3449             :     IMAGE_SAMPLE_C_CD_O_V4_V16  = 3434,
    3450             :     IMAGE_SAMPLE_C_CD_O_V4_V2   = 3435,
    3451             :     IMAGE_SAMPLE_C_CD_O_V4_V4   = 3436,
    3452             :     IMAGE_SAMPLE_C_CD_O_V4_V8   = 3437,
    3453             :     IMAGE_SAMPLE_C_CD_V1_V1     = 3438,
    3454             :     IMAGE_SAMPLE_C_CD_V1_V16    = 3439,
    3455             :     IMAGE_SAMPLE_C_CD_V1_V2     = 3440,
    3456             :     IMAGE_SAMPLE_C_CD_V1_V4     = 3441,
    3457             :     IMAGE_SAMPLE_C_CD_V1_V8     = 3442,
    3458             :     IMAGE_SAMPLE_C_CD_V2_V1     = 3443,
    3459             :     IMAGE_SAMPLE_C_CD_V2_V16    = 3444,
    3460             :     IMAGE_SAMPLE_C_CD_V2_V2     = 3445,
    3461             :     IMAGE_SAMPLE_C_CD_V2_V4     = 3446,
    3462             :     IMAGE_SAMPLE_C_CD_V2_V8     = 3447,
    3463             :     IMAGE_SAMPLE_C_CD_V3_V1     = 3448,
    3464             :     IMAGE_SAMPLE_C_CD_V3_V16    = 3449,
    3465             :     IMAGE_SAMPLE_C_CD_V3_V2     = 3450,
    3466             :     IMAGE_SAMPLE_C_CD_V3_V4     = 3451,
    3467             :     IMAGE_SAMPLE_C_CD_V3_V8     = 3452,
    3468             :     IMAGE_SAMPLE_C_CD_V4_V1     = 3453,
    3469             :     IMAGE_SAMPLE_C_CD_V4_V16    = 3454,
    3470             :     IMAGE_SAMPLE_C_CD_V4_V2     = 3455,
    3471             :     IMAGE_SAMPLE_C_CD_V4_V4     = 3456,
    3472             :     IMAGE_SAMPLE_C_CD_V4_V8     = 3457,
    3473             :     IMAGE_SAMPLE_C_CL_O_V1_V1   = 3458,
    3474             :     IMAGE_SAMPLE_C_CL_O_V1_V16  = 3459,
    3475             :     IMAGE_SAMPLE_C_CL_O_V1_V2   = 3460,
    3476             :     IMAGE_SAMPLE_C_CL_O_V1_V4   = 3461,
    3477             :     IMAGE_SAMPLE_C_CL_O_V1_V8   = 3462,
    3478             :     IMAGE_SAMPLE_C_CL_O_V2_V1   = 3463,
    3479             :     IMAGE_SAMPLE_C_CL_O_V2_V16  = 3464,
    3480             :     IMAGE_SAMPLE_C_CL_O_V2_V2   = 3465,
    3481             :     IMAGE_SAMPLE_C_CL_O_V2_V4   = 3466,
    3482             :     IMAGE_SAMPLE_C_CL_O_V2_V8   = 3467,
    3483             :     IMAGE_SAMPLE_C_CL_O_V3_V1   = 3468,
    3484             :     IMAGE_SAMPLE_C_CL_O_V3_V16  = 3469,
    3485             :     IMAGE_SAMPLE_C_CL_O_V3_V2   = 3470,
    3486             :     IMAGE_SAMPLE_C_CL_O_V3_V4   = 3471,
    3487             :     IMAGE_SAMPLE_C_CL_O_V3_V8   = 3472,
    3488             :     IMAGE_SAMPLE_C_CL_O_V4_V1   = 3473,
    3489             :     IMAGE_SAMPLE_C_CL_O_V4_V16  = 3474,
    3490             :     IMAGE_SAMPLE_C_CL_O_V4_V2   = 3475,
    3491             :     IMAGE_SAMPLE_C_CL_O_V4_V4   = 3476,
    3492             :     IMAGE_SAMPLE_C_CL_O_V4_V8   = 3477,
    3493             :     IMAGE_SAMPLE_C_CL_V1_V1     = 3478,
    3494             :     IMAGE_SAMPLE_C_CL_V1_V16    = 3479,
    3495             :     IMAGE_SAMPLE_C_CL_V1_V2     = 3480,
    3496             :     IMAGE_SAMPLE_C_CL_V1_V4     = 3481,
    3497             :     IMAGE_SAMPLE_C_CL_V1_V8     = 3482,
    3498             :     IMAGE_SAMPLE_C_CL_V2_V1     = 3483,
    3499             :     IMAGE_SAMPLE_C_CL_V2_V16    = 3484,
    3500             :     IMAGE_SAMPLE_C_CL_V2_V2     = 3485,
    3501             :     IMAGE_SAMPLE_C_CL_V2_V4     = 3486,
    3502             :     IMAGE_SAMPLE_C_CL_V2_V8     = 3487,
    3503             :     IMAGE_SAMPLE_C_CL_V3_V1     = 3488,
    3504             :     IMAGE_SAMPLE_C_CL_V3_V16    = 3489,
    3505             :     IMAGE_SAMPLE_C_CL_V3_V2     = 3490,
    3506             :     IMAGE_SAMPLE_C_CL_V3_V4     = 3491,
    3507             :     IMAGE_SAMPLE_C_CL_V3_V8     = 3492,
    3508             :     IMAGE_SAMPLE_C_CL_V4_V1     = 3493,
    3509             :     IMAGE_SAMPLE_C_CL_V4_V16    = 3494,
    3510             :     IMAGE_SAMPLE_C_CL_V4_V2     = 3495,
    3511             :     IMAGE_SAMPLE_C_CL_V4_V4     = 3496,
    3512             :     IMAGE_SAMPLE_C_CL_V4_V8     = 3497,
    3513             :     IMAGE_SAMPLE_C_D_CL_O_V1_V1 = 3498,
    3514             :     IMAGE_SAMPLE_C_D_CL_O_V1_V16        = 3499,
    3515             :     IMAGE_SAMPLE_C_D_CL_O_V1_V2 = 3500,
    3516             :     IMAGE_SAMPLE_C_D_CL_O_V1_V4 = 3501,
    3517             :     IMAGE_SAMPLE_C_D_CL_O_V1_V8 = 3502,
    3518             :     IMAGE_SAMPLE_C_D_CL_O_V2_V1 = 3503,
    3519             :     IMAGE_SAMPLE_C_D_CL_O_V2_V16        = 3504,
    3520             :     IMAGE_SAMPLE_C_D_CL_O_V2_V2 = 3505,
    3521             :     IMAGE_SAMPLE_C_D_CL_O_V2_V4 = 3506,
    3522             :     IMAGE_SAMPLE_C_D_CL_O_V2_V8 = 3507,
    3523             :     IMAGE_SAMPLE_C_D_CL_O_V3_V1 = 3508,
    3524             :     IMAGE_SAMPLE_C_D_CL_O_V3_V16        = 3509,
    3525             :     IMAGE_SAMPLE_C_D_CL_O_V3_V2 = 3510,
    3526             :     IMAGE_SAMPLE_C_D_CL_O_V3_V4 = 3511,
    3527             :     IMAGE_SAMPLE_C_D_CL_O_V3_V8 = 3512,
    3528             :     IMAGE_SAMPLE_C_D_CL_O_V4_V1 = 3513,
    3529             :     IMAGE_SAMPLE_C_D_CL_O_V4_V16        = 3514,
    3530             :     IMAGE_SAMPLE_C_D_CL_O_V4_V2 = 3515,
    3531             :     IMAGE_SAMPLE_C_D_CL_O_V4_V4 = 3516,
    3532             :     IMAGE_SAMPLE_C_D_CL_O_V4_V8 = 3517,
    3533             :     IMAGE_SAMPLE_C_D_CL_V1_V1   = 3518,
    3534             :     IMAGE_SAMPLE_C_D_CL_V1_V16  = 3519,
    3535             :     IMAGE_SAMPLE_C_D_CL_V1_V2   = 3520,
    3536             :     IMAGE_SAMPLE_C_D_CL_V1_V4   = 3521,
    3537             :     IMAGE_SAMPLE_C_D_CL_V1_V8   = 3522,
    3538             :     IMAGE_SAMPLE_C_D_CL_V2_V1   = 3523,
    3539             :     IMAGE_SAMPLE_C_D_CL_V2_V16  = 3524,
    3540             :     IMAGE_SAMPLE_C_D_CL_V2_V2   = 3525,
    3541             :     IMAGE_SAMPLE_C_D_CL_V2_V4   = 3526,
    3542             :     IMAGE_SAMPLE_C_D_CL_V2_V8   = 3527,
    3543             :     IMAGE_SAMPLE_C_D_CL_V3_V1   = 3528,
    3544             :     IMAGE_SAMPLE_C_D_CL_V3_V16  = 3529,
    3545             :     IMAGE_SAMPLE_C_D_CL_V3_V2   = 3530,
    3546             :     IMAGE_SAMPLE_C_D_CL_V3_V4   = 3531,
    3547             :     IMAGE_SAMPLE_C_D_CL_V3_V8   = 3532,
    3548             :     IMAGE_SAMPLE_C_D_CL_V4_V1   = 3533,
    3549             :     IMAGE_SAMPLE_C_D_CL_V4_V16  = 3534,
    3550             :     IMAGE_SAMPLE_C_D_CL_V4_V2   = 3535,
    3551             :     IMAGE_SAMPLE_C_D_CL_V4_V4   = 3536,
    3552             :     IMAGE_SAMPLE_C_D_CL_V4_V8   = 3537,
    3553             :     IMAGE_SAMPLE_C_D_O_V1_V1    = 3538,
    3554             :     IMAGE_SAMPLE_C_D_O_V1_V16   = 3539,
    3555             :     IMAGE_SAMPLE_C_D_O_V1_V2    = 3540,
    3556             :     IMAGE_SAMPLE_C_D_O_V1_V4    = 3541,
    3557             :     IMAGE_SAMPLE_C_D_O_V1_V8    = 3542,
    3558             :     IMAGE_SAMPLE_C_D_O_V2_V1    = 3543,
    3559             :     IMAGE_SAMPLE_C_D_O_V2_V16   = 3544,
    3560             :     IMAGE_SAMPLE_C_D_O_V2_V2    = 3545,
    3561             :     IMAGE_SAMPLE_C_D_O_V2_V4    = 3546,
    3562             :     IMAGE_SAMPLE_C_D_O_V2_V8    = 3547,
    3563             :     IMAGE_SAMPLE_C_D_O_V3_V1    = 3548,
    3564             :     IMAGE_SAMPLE_C_D_O_V3_V16   = 3549,
    3565             :     IMAGE_SAMPLE_C_D_O_V3_V2    = 3550,
    3566             :     IMAGE_SAMPLE_C_D_O_V3_V4    = 3551,
    3567             :     IMAGE_SAMPLE_C_D_O_V3_V8    = 3552,
    3568             :     IMAGE_SAMPLE_C_D_O_V4_V1    = 3553,
    3569             :     IMAGE_SAMPLE_C_D_O_V4_V16   = 3554,
    3570             :     IMAGE_SAMPLE_C_D_O_V4_V2    = 3555,
    3571             :     IMAGE_SAMPLE_C_D_O_V4_V4    = 3556,
    3572             :     IMAGE_SAMPLE_C_D_O_V4_V8    = 3557,
    3573             :     IMAGE_SAMPLE_C_D_V1_V1      = 3558,
    3574             :     IMAGE_SAMPLE_C_D_V1_V16     = 3559,
    3575             :     IMAGE_SAMPLE_C_D_V1_V2      = 3560,
    3576             :     IMAGE_SAMPLE_C_D_V1_V4      = 3561,
    3577             :     IMAGE_SAMPLE_C_D_V1_V8      = 3562,
    3578             :     IMAGE_SAMPLE_C_D_V2_V1      = 3563,
    3579             :     IMAGE_SAMPLE_C_D_V2_V16     = 3564,
    3580             :     IMAGE_SAMPLE_C_D_V2_V2      = 3565,
    3581             :     IMAGE_SAMPLE_C_D_V2_V4      = 3566,
    3582             :     IMAGE_SAMPLE_C_D_V2_V8      = 3567,
    3583             :     IMAGE_SAMPLE_C_D_V3_V1      = 3568,
    3584             :     IMAGE_SAMPLE_C_D_V3_V16     = 3569,
    3585             :     IMAGE_SAMPLE_C_D_V3_V2      = 3570,
    3586             :     IMAGE_SAMPLE_C_D_V3_V4      = 3571,
    3587             :     IMAGE_SAMPLE_C_D_V3_V8      = 3572,
    3588             :     IMAGE_SAMPLE_C_D_V4_V1      = 3573,
    3589             :     IMAGE_SAMPLE_C_D_V4_V16     = 3574,
    3590             :     IMAGE_SAMPLE_C_D_V4_V2      = 3575,
    3591             :     IMAGE_SAMPLE_C_D_V4_V4      = 3576,
    3592             :     IMAGE_SAMPLE_C_D_V4_V8      = 3577,
    3593             :     IMAGE_SAMPLE_C_LZ_O_V1_V1   = 3578,
    3594             :     IMAGE_SAMPLE_C_LZ_O_V1_V16  = 3579,
    3595             :     IMAGE_SAMPLE_C_LZ_O_V1_V2   = 3580,
    3596             :     IMAGE_SAMPLE_C_LZ_O_V1_V4   = 3581,
    3597             :     IMAGE_SAMPLE_C_LZ_O_V1_V8   = 3582,
    3598             :     IMAGE_SAMPLE_C_LZ_O_V2_V1   = 3583,
    3599             :     IMAGE_SAMPLE_C_LZ_O_V2_V16  = 3584,
    3600             :     IMAGE_SAMPLE_C_LZ_O_V2_V2   = 3585,
    3601             :     IMAGE_SAMPLE_C_LZ_O_V2_V4   = 3586,
    3602             :     IMAGE_SAMPLE_C_LZ_O_V2_V8   = 3587,
    3603             :     IMAGE_SAMPLE_C_LZ_O_V3_V1   = 3588,
    3604             :     IMAGE_SAMPLE_C_LZ_O_V3_V16  = 3589,
    3605             :     IMAGE_SAMPLE_C_LZ_O_V3_V2   = 3590,
    3606             :     IMAGE_SAMPLE_C_LZ_O_V3_V4   = 3591,
    3607             :     IMAGE_SAMPLE_C_LZ_O_V3_V8   = 3592,
    3608             :     IMAGE_SAMPLE_C_LZ_O_V4_V1   = 3593,
    3609             :     IMAGE_SAMPLE_C_LZ_O_V4_V16  = 3594,
    3610             :     IMAGE_SAMPLE_C_LZ_O_V4_V2   = 3595,
    3611             :     IMAGE_SAMPLE_C_LZ_O_V4_V4   = 3596,
    3612             :     IMAGE_SAMPLE_C_LZ_O_V4_V8   = 3597,
    3613             :     IMAGE_SAMPLE_C_LZ_V1_V1     = 3598,
    3614             :     IMAGE_SAMPLE_C_LZ_V1_V16    = 3599,
    3615             :     IMAGE_SAMPLE_C_LZ_V1_V2     = 3600,
    3616             :     IMAGE_SAMPLE_C_LZ_V1_V4     = 3601,
    3617             :     IMAGE_SAMPLE_C_LZ_V1_V8     = 3602,
    3618             :     IMAGE_SAMPLE_C_LZ_V2_V1     = 3603,
    3619             :     IMAGE_SAMPLE_C_LZ_V2_V16    = 3604,
    3620             :     IMAGE_SAMPLE_C_LZ_V2_V2     = 3605,
    3621             :     IMAGE_SAMPLE_C_LZ_V2_V4     = 3606,
    3622             :     IMAGE_SAMPLE_C_LZ_V2_V8     = 3607,
    3623             :     IMAGE_SAMPLE_C_LZ_V3_V1     = 3608,
    3624             :     IMAGE_SAMPLE_C_LZ_V3_V16    = 3609,
    3625             :     IMAGE_SAMPLE_C_LZ_V3_V2     = 3610,
    3626             :     IMAGE_SAMPLE_C_LZ_V3_V4     = 3611,
    3627             :     IMAGE_SAMPLE_C_LZ_V3_V8     = 3612,
    3628             :     IMAGE_SAMPLE_C_LZ_V4_V1     = 3613,
    3629             :     IMAGE_SAMPLE_C_LZ_V4_V16    = 3614,
    3630             :     IMAGE_SAMPLE_C_LZ_V4_V2     = 3615,
    3631             :     IMAGE_SAMPLE_C_LZ_V4_V4     = 3616,
    3632             :     IMAGE_SAMPLE_C_LZ_V4_V8     = 3617,
    3633             :     IMAGE_SAMPLE_C_L_O_V1_V1    = 3618,
    3634             :     IMAGE_SAMPLE_C_L_O_V1_V16   = 3619,
    3635             :     IMAGE_SAMPLE_C_L_O_V1_V2    = 3620,
    3636             :     IMAGE_SAMPLE_C_L_O_V1_V4    = 3621,
    3637             :     IMAGE_SAMPLE_C_L_O_V1_V8    = 3622,
    3638             :     IMAGE_SAMPLE_C_L_O_V2_V1    = 3623,
    3639             :     IMAGE_SAMPLE_C_L_O_V2_V16   = 3624,
    3640             :     IMAGE_SAMPLE_C_L_O_V2_V2    = 3625,
    3641             :     IMAGE_SAMPLE_C_L_O_V2_V4    = 3626,
    3642             :     IMAGE_SAMPLE_C_L_O_V2_V8    = 3627,
    3643             :     IMAGE_SAMPLE_C_L_O_V3_V1    = 3628,
    3644             :     IMAGE_SAMPLE_C_L_O_V3_V16   = 3629,
    3645             :     IMAGE_SAMPLE_C_L_O_V3_V2    = 3630,
    3646             :     IMAGE_SAMPLE_C_L_O_V3_V4    = 3631,
    3647             :     IMAGE_SAMPLE_C_L_O_V3_V8    = 3632,
    3648             :     IMAGE_SAMPLE_C_L_O_V4_V1    = 3633,
    3649             :     IMAGE_SAMPLE_C_L_O_V4_V16   = 3634,
    3650             :     IMAGE_SAMPLE_C_L_O_V4_V2    = 3635,
    3651             :     IMAGE_SAMPLE_C_L_O_V4_V4    = 3636,
    3652             :     IMAGE_SAMPLE_C_L_O_V4_V8    = 3637,
    3653             :     IMAGE_SAMPLE_C_L_V1_V1      = 3638,
    3654             :     IMAGE_SAMPLE_C_L_V1_V16     = 3639,
    3655             :     IMAGE_SAMPLE_C_L_V1_V2      = 3640,
    3656             :     IMAGE_SAMPLE_C_L_V1_V4      = 3641,
    3657             :     IMAGE_SAMPLE_C_L_V1_V8      = 3642,
    3658             :     IMAGE_SAMPLE_C_L_V2_V1      = 3643,
    3659             :     IMAGE_SAMPLE_C_L_V2_V16     = 3644,
    3660             :     IMAGE_SAMPLE_C_L_V2_V2      = 3645,
    3661             :     IMAGE_SAMPLE_C_L_V2_V4      = 3646,
    3662             :     IMAGE_SAMPLE_C_L_V2_V8      = 3647,
    3663             :     IMAGE_SAMPLE_C_L_V3_V1      = 3648,
    3664             :     IMAGE_SAMPLE_C_L_V3_V16     = 3649,
    3665             :     IMAGE_SAMPLE_C_L_V3_V2      = 3650,
    3666             :     IMAGE_SAMPLE_C_L_V3_V4      = 3651,
    3667             :     IMAGE_SAMPLE_C_L_V3_V8      = 3652,
    3668             :     IMAGE_SAMPLE_C_L_V4_V1      = 3653,
    3669             :     IMAGE_SAMPLE_C_L_V4_V16     = 3654,
    3670             :     IMAGE_SAMPLE_C_L_V4_V2      = 3655,
    3671             :     IMAGE_SAMPLE_C_L_V4_V4      = 3656,
    3672             :     IMAGE_SAMPLE_C_L_V4_V8      = 3657,
    3673             :     IMAGE_SAMPLE_C_O_V1_V1      = 3658,
    3674             :     IMAGE_SAMPLE_C_O_V1_V16     = 3659,
    3675             :     IMAGE_SAMPLE_C_O_V1_V2      = 3660,
    3676             :     IMAGE_SAMPLE_C_O_V1_V4      = 3661,
    3677             :     IMAGE_SAMPLE_C_O_V1_V8      = 3662,
    3678             :     IMAGE_SAMPLE_C_O_V2_V1      = 3663,
    3679             :     IMAGE_SAMPLE_C_O_V2_V16     = 3664,
    3680             :     IMAGE_SAMPLE_C_O_V2_V2      = 3665,
    3681             :     IMAGE_SAMPLE_C_O_V2_V4      = 3666,
    3682             :     IMAGE_SAMPLE_C_O_V2_V8      = 3667,
    3683             :     IMAGE_SAMPLE_C_O_V3_V1      = 3668,
    3684             :     IMAGE_SAMPLE_C_O_V3_V16     = 3669,
    3685             :     IMAGE_SAMPLE_C_O_V3_V2      = 3670,
    3686             :     IMAGE_SAMPLE_C_O_V3_V4      = 3671,
    3687             :     IMAGE_SAMPLE_C_O_V3_V8      = 3672,
    3688             :     IMAGE_SAMPLE_C_O_V4_V1      = 3673,
    3689             :     IMAGE_SAMPLE_C_O_V4_V16     = 3674,
    3690             :     IMAGE_SAMPLE_C_O_V4_V2      = 3675,
    3691             :     IMAGE_SAMPLE_C_O_V4_V4      = 3676,
    3692             :     IMAGE_SAMPLE_C_O_V4_V8      = 3677,
    3693             :     IMAGE_SAMPLE_C_V1_V1        = 3678,
    3694             :     IMAGE_SAMPLE_C_V1_V16       = 3679,
    3695             :     IMAGE_SAMPLE_C_V1_V2        = 3680,
    3696             :     IMAGE_SAMPLE_C_V1_V4        = 3681,
    3697             :     IMAGE_SAMPLE_C_V1_V8        = 3682,
    3698             :     IMAGE_SAMPLE_C_V2_V1        = 3683,
    3699             :     IMAGE_SAMPLE_C_V2_V16       = 3684,
    3700             :     IMAGE_SAMPLE_C_V2_V2        = 3685,
    3701             :     IMAGE_SAMPLE_C_V2_V4        = 3686,
    3702             :     IMAGE_SAMPLE_C_V2_V8        = 3687,
    3703             :     IMAGE_SAMPLE_C_V3_V1        = 3688,
    3704             :     IMAGE_SAMPLE_C_V3_V16       = 3689,
    3705             :     IMAGE_SAMPLE_C_V3_V2        = 3690,
    3706             :     IMAGE_SAMPLE_C_V3_V4        = 3691,
    3707             :     IMAGE_SAMPLE_C_V3_V8        = 3692,
    3708             :     IMAGE_SAMPLE_C_V4_V1        = 3693,
    3709             :     IMAGE_SAMPLE_C_V4_V16       = 3694,
    3710             :     IMAGE_SAMPLE_C_V4_V2        = 3695,
    3711             :     IMAGE_SAMPLE_C_V4_V4        = 3696,
    3712             :     IMAGE_SAMPLE_C_V4_V8        = 3697,
    3713             :     IMAGE_SAMPLE_D_CL_O_V1_V1   = 3698,
    3714             :     IMAGE_SAMPLE_D_CL_O_V1_V16  = 3699,
    3715             :     IMAGE_SAMPLE_D_CL_O_V1_V2   = 3700,
    3716             :     IMAGE_SAMPLE_D_CL_O_V1_V4   = 3701,
    3717             :     IMAGE_SAMPLE_D_CL_O_V1_V8   = 3702,
    3718             :     IMAGE_SAMPLE_D_CL_O_V2_V1   = 3703,
    3719             :     IMAGE_SAMPLE_D_CL_O_V2_V16  = 3704,
    3720             :     IMAGE_SAMPLE_D_CL_O_V2_V2   = 3705,
    3721             :     IMAGE_SAMPLE_D_CL_O_V2_V4   = 3706,
    3722             :     IMAGE_SAMPLE_D_CL_O_V2_V8   = 3707,
    3723             :     IMAGE_SAMPLE_D_CL_O_V3_V1   = 3708,
    3724             :     IMAGE_SAMPLE_D_CL_O_V3_V16  = 3709,
    3725             :     IMAGE_SAMPLE_D_CL_O_V3_V2   = 3710,
    3726             :     IMAGE_SAMPLE_D_CL_O_V3_V4   = 3711,
    3727             :     IMAGE_SAMPLE_D_CL_O_V3_V8   = 3712,
    3728             :     IMAGE_SAMPLE_D_CL_O_V4_V1   = 3713,
    3729             :     IMAGE_SAMPLE_D_CL_O_V4_V16  = 3714,
    3730             :     IMAGE_SAMPLE_D_CL_O_V4_V2   = 3715,
    3731             :     IMAGE_SAMPLE_D_CL_O_V4_V4   = 3716,
    3732             :     IMAGE_SAMPLE_D_CL_O_V4_V8   = 3717,
    3733             :     IMAGE_SAMPLE_D_CL_V1_V1     = 3718,
    3734             :     IMAGE_SAMPLE_D_CL_V1_V16    = 3719,
    3735             :     IMAGE_SAMPLE_D_CL_V1_V2     = 3720,
    3736             :     IMAGE_SAMPLE_D_CL_V1_V4     = 3721,
    3737             :     IMAGE_SAMPLE_D_CL_V1_V8     = 3722,
    3738             :     IMAGE_SAMPLE_D_CL_V2_V1     = 3723,
    3739             :     IMAGE_SAMPLE_D_CL_V2_V16    = 3724,
    3740             :     IMAGE_SAMPLE_D_CL_V2_V2     = 3725,
    3741             :     IMAGE_SAMPLE_D_CL_V2_V4     = 3726,
    3742             :     IMAGE_SAMPLE_D_CL_V2_V8     = 3727,
    3743             :     IMAGE_SAMPLE_D_CL_V3_V1     = 3728,
    3744             :     IMAGE_SAMPLE_D_CL_V3_V16    = 3729,
    3745             :     IMAGE_SAMPLE_D_CL_V3_V2     = 3730,
    3746             :     IMAGE_SAMPLE_D_CL_V3_V4     = 3731,
    3747             :     IMAGE_SAMPLE_D_CL_V3_V8     = 3732,
    3748             :     IMAGE_SAMPLE_D_CL_V4_V1     = 3733,
    3749             :     IMAGE_SAMPLE_D_CL_V4_V16    = 3734,
    3750             :     IMAGE_SAMPLE_D_CL_V4_V2     = 3735,
    3751             :     IMAGE_SAMPLE_D_CL_V4_V4     = 3736,
    3752             :     IMAGE_SAMPLE_D_CL_V4_V8     = 3737,
    3753             :     IMAGE_SAMPLE_D_O_V1_V1      = 3738,
    3754             :     IMAGE_SAMPLE_D_O_V1_V16     = 3739,
    3755             :     IMAGE_SAMPLE_D_O_V1_V2      = 3740,
    3756             :     IMAGE_SAMPLE_D_O_V1_V4      = 3741,
    3757             :     IMAGE_SAMPLE_D_O_V1_V8      = 3742,
    3758             :     IMAGE_SAMPLE_D_O_V2_V1      = 3743,
    3759             :     IMAGE_SAMPLE_D_O_V2_V16     = 3744,
    3760             :     IMAGE_SAMPLE_D_O_V2_V2      = 3745,
    3761             :     IMAGE_SAMPLE_D_O_V2_V4      = 3746,
    3762             :     IMAGE_SAMPLE_D_O_V2_V8      = 3747,
    3763             :     IMAGE_SAMPLE_D_O_V3_V1      = 3748,
    3764             :     IMAGE_SAMPLE_D_O_V3_V16     = 3749,
    3765             :     IMAGE_SAMPLE_D_O_V3_V2      = 3750,
    3766             :     IMAGE_SAMPLE_D_O_V3_V4      = 3751,
    3767             :     IMAGE_SAMPLE_D_O_V3_V8      = 3752,
    3768             :     IMAGE_SAMPLE_D_O_V4_V1      = 3753,
    3769             :     IMAGE_SAMPLE_D_O_V4_V16     = 3754,
    3770             :     IMAGE_SAMPLE_D_O_V4_V2      = 3755,
    3771             :     IMAGE_SAMPLE_D_O_V4_V4      = 3756,
    3772             :     IMAGE_SAMPLE_D_O_V4_V8      = 3757,
    3773             :     IMAGE_SAMPLE_D_V1_V1        = 3758,
    3774             :     IMAGE_SAMPLE_D_V1_V16       = 3759,
    3775             :     IMAGE_SAMPLE_D_V1_V2        = 3760,
    3776             :     IMAGE_SAMPLE_D_V1_V4        = 3761,
    3777             :     IMAGE_SAMPLE_D_V1_V8        = 3762,
    3778             :     IMAGE_SAMPLE_D_V2_V1        = 3763,
    3779             :     IMAGE_SAMPLE_D_V2_V16       = 3764,
    3780             :     IMAGE_SAMPLE_D_V2_V2        = 3765,
    3781             :     IMAGE_SAMPLE_D_V2_V4        = 3766,
    3782             :     IMAGE_SAMPLE_D_V2_V8        = 3767,
    3783             :     IMAGE_SAMPLE_D_V3_V1        = 3768,
    3784             :     IMAGE_SAMPLE_D_V3_V16       = 3769,
    3785             :     IMAGE_SAMPLE_D_V3_V2        = 3770,
    3786             :     IMAGE_SAMPLE_D_V3_V4        = 3771,
    3787             :     IMAGE_SAMPLE_D_V3_V8        = 3772,
    3788             :     IMAGE_SAMPLE_D_V4_V1        = 3773,
    3789             :     IMAGE_SAMPLE_D_V4_V16       = 3774,
    3790             :     IMAGE_SAMPLE_D_V4_V2        = 3775,
    3791             :     IMAGE_SAMPLE_D_V4_V4        = 3776,
    3792             :     IMAGE_SAMPLE_D_V4_V8        = 3777,
    3793             :     IMAGE_SAMPLE_LZ_O_V1_V1     = 3778,
    3794             :     IMAGE_SAMPLE_LZ_O_V1_V16    = 3779,
    3795             :     IMAGE_SAMPLE_LZ_O_V1_V2     = 3780,
    3796             :     IMAGE_SAMPLE_LZ_O_V1_V4     = 3781,
    3797             :     IMAGE_SAMPLE_LZ_O_V1_V8     = 3782,
    3798             :     IMAGE_SAMPLE_LZ_O_V2_V1     = 3783,
    3799             :     IMAGE_SAMPLE_LZ_O_V2_V16    = 3784,
    3800             :     IMAGE_SAMPLE_LZ_O_V2_V2     = 3785,
    3801             :     IMAGE_SAMPLE_LZ_O_V2_V4     = 3786,
    3802             :     IMAGE_SAMPLE_LZ_O_V2_V8     = 3787,
    3803             :     IMAGE_SAMPLE_LZ_O_V3_V1     = 3788,
    3804             :     IMAGE_SAMPLE_LZ_O_V3_V16    = 3789,
    3805             :     IMAGE_SAMPLE_LZ_O_V3_V2     = 3790,
    3806             :     IMAGE_SAMPLE_LZ_O_V3_V4     = 3791,
    3807             :     IMAGE_SAMPLE_LZ_O_V3_V8     = 3792,
    3808             :     IMAGE_SAMPLE_LZ_O_V4_V1     = 3793,
    3809             :     IMAGE_SAMPLE_LZ_O_V4_V16    = 3794,
    3810             :     IMAGE_SAMPLE_LZ_O_V4_V2     = 3795,
    3811             :     IMAGE_SAMPLE_LZ_O_V4_V4     = 3796,
    3812             :     IMAGE_SAMPLE_LZ_O_V4_V8     = 3797,
    3813             :     IMAGE_SAMPLE_LZ_V1_V1       = 3798,
    3814             :     IMAGE_SAMPLE_LZ_V1_V16      = 3799,
    3815             :     IMAGE_SAMPLE_LZ_V1_V2       = 3800,
    3816             :     IMAGE_SAMPLE_LZ_V1_V4       = 3801,
    3817             :     IMAGE_SAMPLE_LZ_V1_V8       = 3802,
    3818             :     IMAGE_SAMPLE_LZ_V2_V1       = 3803,
    3819             :     IMAGE_SAMPLE_LZ_V2_V16      = 3804,
    3820             :     IMAGE_SAMPLE_LZ_V2_V2       = 3805,
    3821             :     IMAGE_SAMPLE_LZ_V2_V4       = 3806,
    3822             :     IMAGE_SAMPLE_LZ_V2_V8       = 3807,
    3823             :     IMAGE_SAMPLE_LZ_V3_V1       = 3808,
    3824             :     IMAGE_SAMPLE_LZ_V3_V16      = 3809,
    3825             :     IMAGE_SAMPLE_LZ_V3_V2       = 3810,
    3826             :     IMAGE_SAMPLE_LZ_V3_V4       = 3811,
    3827             :     IMAGE_SAMPLE_LZ_V3_V8       = 3812,
    3828             :     IMAGE_SAMPLE_LZ_V4_V1       = 3813,
    3829             :     IMAGE_SAMPLE_LZ_V4_V16      = 3814,
    3830             :     IMAGE_SAMPLE_LZ_V4_V2       = 3815,
    3831             :     IMAGE_SAMPLE_LZ_V4_V4       = 3816,
    3832             :     IMAGE_SAMPLE_LZ_V4_V8       = 3817,
    3833             :     IMAGE_SAMPLE_L_O_V1_V1      = 3818,
    3834             :     IMAGE_SAMPLE_L_O_V1_V16     = 3819,
    3835             :     IMAGE_SAMPLE_L_O_V1_V2      = 3820,
    3836             :     IMAGE_SAMPLE_L_O_V1_V4      = 3821,
    3837             :     IMAGE_SAMPLE_L_O_V1_V8      = 3822,
    3838             :     IMAGE_SAMPLE_L_O_V2_V1      = 3823,
    3839             :     IMAGE_SAMPLE_L_O_V2_V16     = 3824,
    3840             :     IMAGE_SAMPLE_L_O_V2_V2      = 3825,
    3841             :     IMAGE_SAMPLE_L_O_V2_V4      = 3826,
    3842             :     IMAGE_SAMPLE_L_O_V2_V8      = 3827,
    3843             :     IMAGE_SAMPLE_L_O_V3_V1      = 3828,
    3844             :     IMAGE_SAMPLE_L_O_V3_V16     = 3829,
    3845             :     IMAGE_SAMPLE_L_O_V3_V2      = 3830,
    3846             :     IMAGE_SAMPLE_L_O_V3_V4      = 3831,
    3847             :     IMAGE_SAMPLE_L_O_V3_V8      = 3832,
    3848             :     IMAGE_SAMPLE_L_O_V4_V1      = 3833,
    3849             :     IMAGE_SAMPLE_L_O_V4_V16     = 3834,
    3850             :     IMAGE_SAMPLE_L_O_V4_V2      = 3835,
    3851             :     IMAGE_SAMPLE_L_O_V4_V4      = 3836,
    3852             :     IMAGE_SAMPLE_L_O_V4_V8      = 3837,
    3853             :     IMAGE_SAMPLE_L_V1_V1        = 3838,
    3854             :     IMAGE_SAMPLE_L_V1_V16       = 3839,
    3855             :     IMAGE_SAMPLE_L_V1_V2        = 3840,
    3856             :     IMAGE_SAMPLE_L_V1_V4        = 3841,
    3857             :     IMAGE_SAMPLE_L_V1_V8        = 3842,
    3858             :     IMAGE_SAMPLE_L_V2_V1        = 3843,
    3859             :     IMAGE_SAMPLE_L_V2_V16       = 3844,
    3860             :     IMAGE_SAMPLE_L_V2_V2        = 3845,
    3861             :     IMAGE_SAMPLE_L_V2_V4        = 3846,
    3862             :     IMAGE_SAMPLE_L_V2_V8        = 3847,
    3863             :     IMAGE_SAMPLE_L_V3_V1        = 3848,
    3864             :     IMAGE_SAMPLE_L_V3_V16       = 3849,
    3865             :     IMAGE_SAMPLE_L_V3_V2        = 3850,
    3866             :     IMAGE_SAMPLE_L_V3_V4        = 3851,
    3867             :     IMAGE_SAMPLE_L_V3_V8        = 3852,
    3868             :     IMAGE_SAMPLE_L_V4_V1        = 3853,
    3869             :     IMAGE_SAMPLE_L_V4_V16       = 3854,
    3870             :     IMAGE_SAMPLE_L_V4_V2        = 3855,
    3871             :     IMAGE_SAMPLE_L_V4_V4        = 3856,
    3872             :     IMAGE_SAMPLE_L_V4_V8        = 3857,
    3873             :     IMAGE_SAMPLE_O_V1_V1        = 3858,
    3874             :     IMAGE_SAMPLE_O_V1_V16       = 3859,
    3875             :     IMAGE_SAMPLE_O_V1_V2        = 3860,
    3876             :     IMAGE_SAMPLE_O_V1_V4        = 3861,
    3877             :     IMAGE_SAMPLE_O_V1_V8        = 3862,
    3878             :     IMAGE_SAMPLE_O_V2_V1        = 3863,
    3879             :     IMAGE_SAMPLE_O_V2_V16       = 3864,
    3880             :     IMAGE_SAMPLE_O_V2_V2        = 3865,
    3881             :     IMAGE_SAMPLE_O_V2_V4        = 3866,
    3882             :     IMAGE_SAMPLE_O_V2_V8        = 3867,
    3883             :     IMAGE_SAMPLE_O_V3_V1        = 3868,
    3884             :     IMAGE_SAMPLE_O_V3_V16       = 3869,
    3885             :     IMAGE_SAMPLE_O_V3_V2        = 3870,
    3886             :     IMAGE_SAMPLE_O_V3_V4        = 3871,
    3887             :     IMAGE_SAMPLE_O_V3_V8        = 3872,
    3888             :     IMAGE_SAMPLE_O_V4_V1        = 3873,
    3889             :     IMAGE_SAMPLE_O_V4_V16       = 3874,
    3890             :     IMAGE_SAMPLE_O_V4_V2        = 3875,
    3891             :     IMAGE_SAMPLE_O_V4_V4        = 3876,
    3892             :     IMAGE_SAMPLE_O_V4_V8        = 3877,
    3893             :     IMAGE_SAMPLE_V1_V1  = 3878,
    3894             :     IMAGE_SAMPLE_V1_V16 = 3879,
    3895             :     IMAGE_SAMPLE_V1_V2  = 3880,
    3896             :     IMAGE_SAMPLE_V1_V4  = 3881,
    3897             :     IMAGE_SAMPLE_V1_V8  = 3882,
    3898             :     IMAGE_SAMPLE_V2_V1  = 3883,
    3899             :     IMAGE_SAMPLE_V2_V16 = 3884,
    3900             :     IMAGE_SAMPLE_V2_V2  = 3885,
    3901             :     IMAGE_SAMPLE_V2_V4  = 3886,
    3902             :     IMAGE_SAMPLE_V2_V8  = 3887,
    3903             :     IMAGE_SAMPLE_V3_V1  = 3888,
    3904             :     IMAGE_SAMPLE_V3_V16 = 3889,
    3905             :     IMAGE_SAMPLE_V3_V2  = 3890,
    3906             :     IMAGE_SAMPLE_V3_V4  = 3891,
    3907             :     IMAGE_SAMPLE_V3_V8  = 3892,
    3908             :     IMAGE_SAMPLE_V4_V1  = 3893,
    3909             :     IMAGE_SAMPLE_V4_V16 = 3894,
    3910             :     IMAGE_SAMPLE_V4_V2  = 3895,
    3911             :     IMAGE_SAMPLE_V4_V4  = 3896,
    3912             :     IMAGE_SAMPLE_V4_V8  = 3897,
    3913             :     IMAGE_STORE_MIP_V1_V1       = 3898,
    3914             :     IMAGE_STORE_MIP_V1_V2       = 3899,
    3915             :     IMAGE_STORE_MIP_V1_V4       = 3900,
    3916             :     IMAGE_STORE_MIP_V2_V1       = 3901,
    3917             :     IMAGE_STORE_MIP_V2_V2       = 3902,
    3918             :     IMAGE_STORE_MIP_V2_V4       = 3903,
    3919             :     IMAGE_STORE_MIP_V3_V1       = 3904,
    3920             :     IMAGE_STORE_MIP_V3_V2       = 3905,
    3921             :     IMAGE_STORE_MIP_V3_V4       = 3906,
    3922             :     IMAGE_STORE_MIP_V4_V1       = 3907,
    3923             :     IMAGE_STORE_MIP_V4_V2       = 3908,
    3924             :     IMAGE_STORE_MIP_V4_V4       = 3909,
    3925             :     IMAGE_STORE_V1_V1   = 3910,
    3926             :     IMAGE_STORE_V1_V2   = 3911,
    3927             :     IMAGE_STORE_V1_V4   = 3912,
    3928             :     IMAGE_STORE_V2_V1   = 3913,
    3929             :     IMAGE_STORE_V2_V2   = 3914,
    3930             :     IMAGE_STORE_V2_V4   = 3915,
    3931             :     IMAGE_STORE_V3_V1   = 3916,
    3932             :     IMAGE_STORE_V3_V2   = 3917,
    3933             :     IMAGE_STORE_V3_V4   = 3918,
    3934             :     IMAGE_STORE_V4_V1   = 3919,
    3935             :     IMAGE_STORE_V4_V2   = 3920,
    3936             :     IMAGE_STORE_V4_V4   = 3921,
    3937             :     INTERP_LOAD_P0      = 3922,
    3938             :     INTERP_PAIR_XY      = 3923,
    3939             :     INTERP_PAIR_ZW      = 3924,
    3940             :     INTERP_VEC_LOAD     = 3925,
    3941             :     INTERP_XY   = 3926,
    3942             :     INTERP_ZW   = 3927,
    3943             :     INT_TO_FLT_eg       = 3928,
    3944             :     INT_TO_FLT_r600     = 3929,
    3945             :     JUMP        = 3930,
    3946             :     JUMP_COND   = 3931,
    3947             :     KILLGT      = 3932,
    3948             :     LDS_ADD     = 3933,
    3949             :     LDS_ADD_RET = 3934,
    3950             :     LDS_AND     = 3935,
    3951             :     LDS_AND_RET = 3936,
    3952             :     LDS_BYTE_READ_RET   = 3937,
    3953             :     LDS_BYTE_WRITE      = 3938,
    3954             :     LDS_CMPST   = 3939,
    3955             :     LDS_CMPST_RET       = 3940,
    3956             :     LDS_MAX_INT = 3941,
    3957             :     LDS_MAX_INT_RET     = 3942,
    3958             :     LDS_MAX_UINT        = 3943,
    3959             :     LDS_MAX_UINT_RET    = 3944,
    3960             :     LDS_MIN_INT = 3945,
    3961             :     LDS_MIN_INT_RET     = 3946,
    3962             :     LDS_MIN_UINT        = 3947,
    3963             :     LDS_MIN_UINT_RET    = 3948,
    3964             :     LDS_OR      = 3949,
    3965             :     LDS_OR_RET  = 3950,
    3966             :     LDS_READ_RET        = 3951,
    3967             :     LDS_SHORT_READ_RET  = 3952,
    3968             :     LDS_SHORT_WRITE     = 3953,
    3969             :     LDS_SUB     = 3954,
    3970             :     LDS_SUB_RET = 3955,
    3971             :     LDS_UBYTE_READ_RET  = 3956,
    3972             :     LDS_USHORT_READ_RET = 3957,
    3973             :     LDS_WRITE   = 3958,
    3974             :     LDS_WRXCHG  = 3959,
    3975             :     LDS_WRXCHG_RET      = 3960,
    3976             :     LDS_XOR     = 3961,
    3977             :     LDS_XOR_RET = 3962,
    3978             :     LITERALS    = 3963,
    3979             :     LOG_CLAMPED_eg      = 3964,
    3980             :     LOG_CLAMPED_r600    = 3965,
    3981             :     LOG_IEEE_cm = 3966,
    3982             :     LOG_IEEE_eg = 3967,
    3983             :     LOG_IEEE_r600       = 3968,
    3984             :     LOOP_BREAK_EG       = 3969,
    3985             :     LOOP_BREAK_R600     = 3970,
    3986             :     LSHL_eg     = 3971,
    3987             :     LSHL_r600   = 3972,
    3988             :     LSHR_eg     = 3973,
    3989             :     LSHR_r600   = 3974,
    3990             :     MASK_WRITE  = 3975,
    3991             :     MAX = 3976,
    3992             :     MAX_DX10    = 3977,
    3993             :     MAX_INT     = 3978,
    3994             :     MAX_UINT    = 3979,
    3995             :     MIN = 3980,
    3996             :     MIN_DX10    = 3981,
    3997             :     MIN_INT     = 3982,
    3998             :     MIN_UINT    = 3983,
    3999             :     MOV = 3984,
    4000             :     MOVA_INT_eg = 3985,
    4001             :     MOV_IMM_F32 = 3986,
    4002             :     MOV_IMM_GLOBAL_ADDR = 3987,
    4003             :     MOV_IMM_I32 = 3988,
    4004             :     MUL = 3989,
    4005             :     MULADD_IEEE_eg      = 3990,
    4006             :     MULADD_IEEE_r600    = 3991,
    4007             :     MULADD_INT24_cm     = 3992,
    4008             :     MULADD_UINT24_eg    = 3993,
    4009             :     MULADD_eg   = 3994,
    4010             :     MULADD_r600 = 3995,
    4011             :     MULHI_INT_cm        = 3996,
    4012             :     MULHI_INT_cm24      = 3997,
    4013             :     MULHI_INT_eg        = 3998,
    4014             :     MULHI_INT_r600      = 3999,
    4015             :     MULHI_UINT24_eg     = 4000,
    4016             :     MULHI_UINT_cm       = 4001,
    4017             :     MULHI_UINT_cm24     = 4002,
    4018             :     MULHI_UINT_eg       = 4003,
    4019             :     MULHI_UINT_r600     = 4004,
    4020             :     MULLO_INT_cm        = 4005,
    4021             :     MULLO_INT_eg        = 4006,
    4022             :     MULLO_INT_r600      = 4007,
    4023             :     MULLO_UINT_cm       = 4008,
    4024             :     MULLO_UINT_eg       = 4009,
    4025             :     MULLO_UINT_r600     = 4010,
    4026             :     MUL_IEEE    = 4011,
    4027             :     MUL_INT24_cm        = 4012,
    4028             :     MUL_LIT_eg  = 4013,
    4029             :     MUL_LIT_r600        = 4014,
    4030             :     MUL_UINT24_eg       = 4015,
    4031             :     NOT_INT     = 4016,
    4032             :     OR_INT      = 4017,
    4033             :     PAD = 4018,
    4034             :     POP_EG      = 4019,
    4035             :     POP_R600    = 4020,
    4036             :     PRED_SETE   = 4021,
    4037             :     PRED_SETE_INT       = 4022,
    4038             :     PRED_SETGE  = 4023,
    4039             :     PRED_SETGE_INT      = 4024,
    4040             :     PRED_SETGT  = 4025,
    4041             :     PRED_SETGT_INT      = 4026,
    4042             :     PRED_SETNE  = 4027,
    4043             :     PRED_SETNE_INT      = 4028,
    4044             :     PRED_X      = 4029,
    4045             :     R600_EXTRACT_ELT_V2 = 4030,
    4046             :     R600_EXTRACT_ELT_V4 = 4031,
    4047             :     R600_ExportBuf      = 4032,
    4048             :     R600_ExportSwz      = 4033,
    4049             :     R600_INSERT_ELT_V2  = 4034,
    4050             :     R600_INSERT_ELT_V4  = 4035,
    4051             :     R600_RegisterLoad   = 4036,
    4052             :     R600_RegisterStore  = 4037,
    4053             :     RAT_ATOMIC_ADD_NORET        = 4038,
    4054             :     RAT_ATOMIC_ADD_RTN  = 4039,
    4055             :     RAT_ATOMIC_AND_NORET        = 4040,
    4056             :     RAT_ATOMIC_AND_RTN  = 4041,
    4057             :     RAT_ATOMIC_CMPXCHG_INT_NORET        = 4042,
    4058             :     RAT_ATOMIC_CMPXCHG_INT_RTN  = 4043,
    4059             :     RAT_ATOMIC_DEC_UINT_NORET   = 4044,
    4060             :     RAT_ATOMIC_DEC_UINT_RTN     = 4045,
    4061             :     RAT_ATOMIC_INC_UINT_NORET   = 4046,
    4062             :     RAT_ATOMIC_INC_UINT_RTN     = 4047,
    4063             :     RAT_ATOMIC_MAX_INT_NORET    = 4048,
    4064             :     RAT_ATOMIC_MAX_INT_RTN      = 4049,
    4065             :     RAT_ATOMIC_MAX_UINT_NORET   = 4050,
    4066             :     RAT_ATOMIC_MAX_UINT_RTN     = 4051,
    4067             :     RAT_ATOMIC_MIN_INT_NORET    = 4052,
    4068             :     RAT_ATOMIC_MIN_INT_RTN      = 4053,
    4069             :     RAT_ATOMIC_MIN_UINT_NORET   = 4054,
    4070             :     RAT_ATOMIC_MIN_UINT_RTN     = 4055,
    4071             :     RAT_ATOMIC_OR_NORET = 4056,
    4072             :     RAT_ATOMIC_OR_RTN   = 4057,
    4073             :     RAT_ATOMIC_RSUB_NORET       = 4058,
    4074             :     RAT_ATOMIC_RSUB_RTN = 4059,
    4075             :     RAT_ATOMIC_SUB_NORET        = 4060,
    4076             :     RAT_ATOMIC_SUB_RTN  = 4061,
    4077             :     RAT_ATOMIC_XCHG_INT_NORET   = 4062,
    4078             :     RAT_ATOMIC_XCHG_INT_RTN     = 4063,
    4079             :     RAT_ATOMIC_XOR_NORET        = 4064,
    4080             :     RAT_ATOMIC_XOR_RTN  = 4065,
    4081             :     RAT_MSKOR   = 4066,
    4082             :     RAT_STORE_DWORD128  = 4067,
    4083             :     RAT_STORE_DWORD32   = 4068,
    4084             :     RAT_STORE_DWORD64   = 4069,
    4085             :     RAT_STORE_TYPED_cm  = 4070,
    4086             :     RAT_STORE_TYPED_eg  = 4071,
    4087             :     RAT_WRITE_CACHELESS_128_eg  = 4072,
    4088             :     RAT_WRITE_CACHELESS_32_eg   = 4073,
    4089             :     RAT_WRITE_CACHELESS_64_eg   = 4074,
    4090             :     RECIPSQRT_CLAMPED_cm        = 4075,
    4091             :     RECIPSQRT_CLAMPED_eg        = 4076,
    4092             :     RECIPSQRT_CLAMPED_r600      = 4077,
    4093             :     RECIPSQRT_IEEE_cm   = 4078,
    4094             :     RECIPSQRT_IEEE_eg   = 4079,
    4095             :     RECIPSQRT_IEEE_r600 = 4080,
    4096             :     RECIP_CLAMPED_cm    = 4081,
    4097             :     RECIP_CLAMPED_eg    = 4082,
    4098             :     RECIP_CLAMPED_r600  = 4083,
    4099             :     RECIP_IEEE_cm       = 4084,
    4100             :     RECIP_IEEE_eg       = 4085,
    4101             :     RECIP_IEEE_r600     = 4086,
    4102             :     RECIP_UINT_eg       = 4087,
    4103             :     RECIP_UINT_r600     = 4088,
    4104             :     RETDYN      = 4089,
    4105             :     RETURN      = 4090,
    4106             :     RNDNE       = 4091,
    4107             :     SCRATCH_LOAD_DWORD  = 4092,
    4108             :     SCRATCH_LOAD_DWORDX2        = 4093,
    4109             :     SCRATCH_LOAD_DWORDX2_SADDR  = 4094,
    4110             :     SCRATCH_LOAD_DWORDX2_SADDR_vi       = 4095,
    4111             :     SCRATCH_LOAD_DWORDX2_vi     = 4096,
    4112             :     SCRATCH_LOAD_DWORDX3        = 4097,
    4113             :     SCRATCH_LOAD_DWORDX3_SADDR  = 4098,
    4114             :     SCRATCH_LOAD_DWORDX3_SADDR_vi       = 4099,
    4115             :     SCRATCH_LOAD_DWORDX3_vi     = 4100,
    4116             :     SCRATCH_LOAD_DWORDX4        = 4101,
    4117             :     SCRATCH_LOAD_DWORDX4_SADDR  = 4102,
    4118             :     SCRATCH_LOAD_DWORDX4_SADDR_vi       = 4103,
    4119             :     SCRATCH_LOAD_DWORDX4_vi     = 4104,
    4120             :     SCRATCH_LOAD_DWORD_SADDR    = 4105,
    4121             :     SCRATCH_LOAD_DWORD_SADDR_vi = 4106,
    4122             :     SCRATCH_LOAD_DWORD_vi       = 4107,
    4123             :     SCRATCH_LOAD_SBYTE  = 4108,
    4124             :     SCRATCH_LOAD_SBYTE_D16      = 4109,
    4125             :     SCRATCH_LOAD_SBYTE_D16_HI   = 4110,
    4126             :     SCRATCH_LOAD_SBYTE_D16_HI_SADDR     = 4111,
    4127             :     SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi  = 4112,
    4128             :     SCRATCH_LOAD_SBYTE_D16_HI_vi        = 4113,
    4129             :     SCRATCH_LOAD_SBYTE_D16_SADDR        = 4114,
    4130             :     SCRATCH_LOAD_SBYTE_D16_SADDR_vi     = 4115,
    4131             :     SCRATCH_LOAD_SBYTE_D16_vi   = 4116,
    4132             :     SCRATCH_LOAD_SBYTE_SADDR    = 4117,
    4133             :     SCRATCH_LOAD_SBYTE_SADDR_vi = 4118,
    4134             :     SCRATCH_LOAD_SBYTE_vi       = 4119,
    4135             :     SCRATCH_LOAD_SHORT_D16      = 4120,
    4136             :     SCRATCH_LOAD_SHORT_D16_HI   = 4121,
    4137             :     SCRATCH_LOAD_SHORT_D16_HI_SADDR     = 4122,
    4138             :     SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi  = 4123,
    4139             :     SCRATCH_LOAD_SHORT_D16_HI_vi        = 4124,
    4140             :     SCRATCH_LOAD_SHORT_D16_SADDR        = 4125,
    4141             :     SCRATCH_LOAD_SHORT_D16_SADDR_vi     = 4126,
    4142             :     SCRATCH_LOAD_SHORT_D16_vi   = 4127,
    4143             :     SCRATCH_LOAD_SSHORT = 4128,
    4144             :     SCRATCH_LOAD_SSHORT_SADDR   = 4129,
    4145             :     SCRATCH_LOAD_SSHORT_SADDR_vi        = 4130,
    4146             :     SCRATCH_LOAD_SSHORT_vi      = 4131,
    4147             :     SCRATCH_LOAD_UBYTE  = 4132,
    4148             :     SCRATCH_LOAD_UBYTE_D16      = 4133,
    4149             :     SCRATCH_LOAD_UBYTE_D16_HI   = 4134,
    4150             :     SCRATCH_LOAD_UBYTE_D16_HI_SADDR     = 4135,
    4151             :     SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi  = 4136,
    4152             :     SCRATCH_LOAD_UBYTE_D16_HI_vi        = 4137,
    4153             :     SCRATCH_LOAD_UBYTE_D16_SADDR        = 4138,
    4154             :     SCRATCH_LOAD_UBYTE_D16_SADDR_vi     = 4139,
    4155             :     SCRATCH_LOAD_UBYTE_D16_vi   = 4140,
    4156             :     SCRATCH_LOAD_UBYTE_SADDR    = 4141,
    4157             :     SCRATCH_LOAD_UBYTE_SADDR_vi = 4142,
    4158             :     SCRATCH_LOAD_UBYTE_vi       = 4143,
    4159             :     SCRATCH_LOAD_USHORT = 4144,
    4160             :     SCRATCH_LOAD_USHORT_SADDR   = 4145,
    4161             :     SCRATCH_LOAD_USHORT_SADDR_vi        = 4146,
    4162             :     SCRATCH_LOAD_USHORT_vi      = 4147,
    4163             :     SCRATCH_STORE_BYTE  = 4148,
    4164             :     SCRATCH_STORE_BYTE_D16_HI   = 4149,
    4165             :     SCRATCH_STORE_BYTE_D16_HI_SADDR     = 4150,
    4166             :     SCRATCH_STORE_BYTE_D16_HI_SADDR_vi  = 4151,
    4167             :     SCRATCH_STORE_BYTE_D16_HI_vi        = 4152,
    4168             :     SCRATCH_STORE_BYTE_SADDR    = 4153,
    4169             :     SCRATCH_STORE_BYTE_SADDR_vi = 4154,
    4170             :     SCRATCH_STORE_BYTE_vi       = 4155,
    4171             :     SCRATCH_STORE_DWORD = 4156,
    4172             :     SCRATCH_STORE_DWORDX2       = 4157,
    4173             :     SCRATCH_STORE_DWORDX2_SADDR = 4158,
    4174             :     SCRATCH_STORE_DWORDX2_SADDR_vi      = 4159,
    4175             :     SCRATCH_STORE_DWORDX2_vi    = 4160,
    4176             :     SCRATCH_STORE_DWORDX3       = 4161,
    4177             :     SCRATCH_STORE_DWORDX3_SADDR = 4162,
    4178             :     SCRATCH_STORE_DWORDX3_SADDR_vi      = 4163,
    4179             :     SCRATCH_STORE_DWORDX3_vi    = 4164,
    4180             :     SCRATCH_STORE_DWORDX4       = 4165,
    4181             :     SCRATCH_STORE_DWORDX4_SADDR = 4166,
    4182             :     SCRATCH_STORE_DWORDX4_SADDR_vi      = 4167,
    4183             :     SCRATCH_STORE_DWORDX4_vi    = 4168,
    4184             :     SCRATCH_STORE_DWORD_SADDR   = 4169,
    4185             :     SCRATCH_STORE_DWORD_SADDR_vi        = 4170,
    4186             :     SCRATCH_STORE_DWORD_vi      = 4171,
    4187             :     SCRATCH_STORE_SHORT = 4172,
    4188             :     SCRATCH_STORE_SHORT_D16_HI  = 4173,
    4189             :     SCRATCH_STORE_SHORT_D16_HI_SADDR    = 4174,
    4190             :     SCRATCH_STORE_SHORT_D16_HI_SADDR_vi = 4175,
    4191             :     SCRATCH_STORE_SHORT_D16_HI_vi       = 4176,
    4192             :     SCRATCH_STORE_SHORT_SADDR   = 4177,
    4193             :     SCRATCH_STORE_SHORT_SADDR_vi        = 4178,
    4194             :     SCRATCH_STORE_SHORT_vi      = 4179,
    4195             :     SETE        = 4180,
    4196             :     SETE_DX10   = 4181,
    4197             :     SETE_INT    = 4182,
    4198             :     SETGE_DX10  = 4183,
    4199             :     SETGE_INT   = 4184,
    4200             :     SETGE_UINT  = 4185,
    4201             :     SETGT_DX10  = 4186,
    4202             :     SETGT_INT   = 4187,
    4203             :     SETGT_UINT  = 4188,
    4204             :     SETNE_DX10  = 4189,
    4205             :     SETNE_INT   = 4190,
    4206             :     SGE = 4191,
    4207             :     SGT = 4192,
    4208             :     SIN_cm      = 4193,
    4209             :     SIN_eg      = 4194,
    4210             :     SIN_r600    = 4195,
    4211             :     SIN_r700    = 4196,
    4212             :     SI_BREAK    = 4197,
    4213             :     SI_BR_UNDEF = 4198,
    4214             :     SI_CALL     = 4199,
    4215             :     SI_CALL_ISEL        = 4200,
    4216             :     SI_ELSE     = 4201,
    4217             :     SI_ELSE_BREAK       = 4202,
    4218             :     SI_END_CF   = 4203,
    4219             :     SI_IF       = 4204,
    4220             :     SI_IF_BREAK = 4205,
    4221             :     SI_ILLEGAL_COPY     = 4206,
    4222             :     SI_INDIRECT_DST_V1  = 4207,
    4223             :     SI_INDIRECT_DST_V16 = 4208,
    4224             :     SI_INDIRECT_DST_V2  = 4209,
    4225             :     SI_INDIRECT_DST_V4  = 4210,
    4226             :     SI_INDIRECT_DST_V8  = 4211,
    4227             :     SI_INDIRECT_SRC_V1  = 4212,
    4228             :     SI_INDIRECT_SRC_V16 = 4213,
    4229             :     SI_INDIRECT_SRC_V2  = 4214,
    4230             :     SI_INDIRECT_SRC_V4  = 4215,
    4231             :     SI_INDIRECT_SRC_V8  = 4216,
    4232             :     SI_INIT_EXEC        = 4217,
    4233             :     SI_INIT_EXEC_FROM_INPUT     = 4218,
    4234             :     SI_INIT_M0  = 4219,
    4235             :     SI_KILL     = 4220,
    4236             :     SI_KILL_TERMINATOR  = 4221,
    4237             :     SI_LOOP     = 4222,
    4238             :     SI_MASKED_UNREACHABLE       = 4223,
    4239             :     SI_MASK_BRANCH      = 4224,
    4240             :     SI_NON_UNIFORM_BRCOND_PSEUDO        = 4225,
    4241             :     SI_PC_ADD_REL_OFFSET        = 4226,
    4242             :     SI_PS_LIVE  = 4227,
    4243             :     SI_RETURN   = 4228,
    4244             :     SI_RETURN_TO_EPILOG = 4229,
    4245             :     SI_SPILL_S128_RESTORE       = 4230,
    4246             :     SI_SPILL_S128_SAVE  = 4231,
    4247             :     SI_SPILL_S256_RESTORE       = 4232,
    4248             :     SI_SPILL_S256_SAVE  = 4233,
    4249             :     SI_SPILL_S32_RESTORE        = 4234,
    4250             :     SI_SPILL_S32_SAVE   = 4235,
    4251             :     SI_SPILL_S512_RESTORE       = 4236,
    4252             :     SI_SPILL_S512_SAVE  = 4237,
    4253             :     SI_SPILL_S64_RESTORE        = 4238,
    4254             :     SI_SPILL_S64_SAVE   = 4239,
    4255             :     SI_SPILL_V128_RESTORE       = 4240,
    4256             :     SI_SPILL_V128_SAVE  = 4241,
    4257             :     SI_SPILL_V256_RESTORE       = 4242,
    4258             :     SI_SPILL_V256_SAVE  = 4243,
    4259             :     SI_SPILL_V32_RESTORE        = 4244,
    4260             :     SI_SPILL_V32_SAVE   = 4245,
    4261             :     SI_SPILL_V512_RESTORE       = 4246,
    4262             :     SI_SPILL_V512_SAVE  = 4247,
    4263             :     SI_SPILL_V64_RESTORE        = 4248,
    4264             :     SI_SPILL_V64_SAVE   = 4249,
    4265             :     SI_SPILL_V96_RESTORE        = 4250,
    4266             :     SI_SPILL_V96_SAVE   = 4251,
    4267             :     SI_TCRETURN = 4252,
    4268             :     SI_TCRETURN_ISEL    = 4253,
    4269             :     SNE = 4254,
    4270             :     SUBB_UINT   = 4255,
    4271             :     SUB_INT     = 4256,
    4272             :     S_ABSDIFF_I32       = 4257,
    4273             :     S_ABSDIFF_I32_si    = 4258,
    4274             :     S_ABSDIFF_I32_vi    = 4259,
    4275             :     S_ABS_I32   = 4260,
    4276             :     S_ABS_I32_si        = 4261,
    4277             :     S_ABS_I32_vi        = 4262,
    4278             :     S_ADDC_U32  = 4263,
    4279             :     S_ADDC_U32_si       = 4264,
    4280             :     S_ADDC_U32_vi       = 4265,
    4281             :     S_ADDK_I32  = 4266,
    4282             :     S_ADDK_I32_si       = 4267,
    4283             :     S_ADDK_I32_vi       = 4268,
    4284             :     S_ADD_I32   = 4269,
    4285             :     S_ADD_I32_si        = 4270,
    4286             :     S_ADD_I32_vi        = 4271,
    4287             :     S_ADD_U32   = 4272,
    4288             :     S_ADD_U32_si        = 4273,
    4289             :     S_ADD_U32_vi        = 4274,
    4290             :     S_ANDN2_B32 = 4275,
    4291             :     S_ANDN2_B32_si      = 4276,
    4292             :     S_ANDN2_B32_vi      = 4277,
    4293             :     S_ANDN2_B64 = 4278,
    4294             :     S_ANDN2_B64_si      = 4279,
    4295             :     S_ANDN2_B64_term    = 4280,
    4296             :     S_ANDN2_B64_vi      = 4281,
    4297             :     S_ANDN2_SAVEEXEC_B64        = 4282,
    4298             :     S_ANDN2_SAVEEXEC_B64_si     = 4283,
    4299             :     S_ANDN2_SAVEEXEC_B64_vi     = 4284,
    4300             :     S_AND_B32   = 4285,
    4301             :     S_AND_B32_si        = 4286,
    4302             :     S_AND_B32_vi        = 4287,
    4303             :     S_AND_B64   = 4288,
    4304             :     S_AND_B64_si        = 4289,
    4305             :     S_AND_B64_vi        = 4290,
    4306             :     S_AND_SAVEEXEC_B64  = 4291,
    4307             :     S_AND_SAVEEXEC_B64_si       = 4292,
    4308             :     S_AND_SAVEEXEC_B64_vi       = 4293,
    4309             :     S_ASHR_I32  = 4294,
    4310             :     S_ASHR_I32_si       = 4295,
    4311             :     S_ASHR_I32_vi       = 4296,
    4312             :     S_ASHR_I64  = 4297,
    4313             :     S_ASHR_I64_si       = 4298,
    4314             :     S_ASHR_I64_vi       = 4299,
    4315             :     S_BARRIER   = 4300,
    4316             :     S_BCNT0_I32_B32     = 4301,
    4317             :     S_BCNT0_I32_B32_si  = 4302,
    4318             :     S_BCNT0_I32_B32_vi  = 4303,
    4319             :     S_BCNT0_I32_B64     = 4304,
    4320             :     S_BCNT0_I32_B64_si  = 4305,
    4321             :     S_BCNT0_I32_B64_vi  = 4306,
    4322             :     S_BCNT1_I32_B32     = 4307,
    4323             :     S_BCNT1_I32_B32_si  = 4308,
    4324             :     S_BCNT1_I32_B32_vi  = 4309,
    4325             :     S_BCNT1_I32_B64     = 4310,
    4326             :     S_BCNT1_I32_B64_si  = 4311,
    4327             :     S_BCNT1_I32_B64_vi  = 4312,
    4328             :     S_BFE_I32   = 4313,
    4329             :     S_BFE_I32_si        = 4314,
    4330             :     S_BFE_I32_vi        = 4315,
    4331             :     S_BFE_I64   = 4316,
    4332             :     S_BFE_I64_si        = 4317,
    4333             :     S_BFE_I64_vi        = 4318,
    4334             :     S_BFE_U32   = 4319,
    4335             :     S_BFE_U32_si        = 4320,
    4336             :     S_BFE_U32_vi        = 4321,
    4337             :     S_BFE_U64   = 4322,
    4338             :     S_BFE_U64_si        = 4323,
    4339             :     S_BFE_U64_vi        = 4324,
    4340             :     S_BFM_B32   = 4325,
    4341             :     S_BFM_B32_si        = 4326,
    4342             :     S_BFM_B32_vi        = 4327,
    4343             :     S_BFM_B64   = 4328,
    4344             :     S_BFM_B64_si        = 4329,
    4345             :     S_BFM_B64_vi        = 4330,
    4346             :     S_BITCMP0_B32       = 4331,
    4347             :     S_BITCMP0_B64       = 4332,
    4348             :     S_BITCMP1_B32       = 4333,
    4349             :     S_BITCMP1_B64       = 4334,
    4350             :     S_BITSET0_B32       = 4335,
    4351             :     S_BITSET0_B32_si    = 4336,
    4352             :     S_BITSET0_B32_vi    = 4337,
    4353             :     S_BITSET0_B64       = 4338,
    4354             :     S_BITSET0_B64_si    = 4339,
    4355             :     S_BITSET0_B64_vi    = 4340,
    4356             :     S_BITSET1_B32       = 4341,
    4357             :     S_BITSET1_B32_si    = 4342,
    4358             :     S_BITSET1_B32_vi    = 4343,
    4359             :     S_BITSET1_B64       = 4344,
    4360             :     S_BITSET1_B64_si    = 4345,
    4361             :     S_BITSET1_B64_vi    = 4346,
    4362             :     S_BRANCH    = 4347,
    4363             :     S_BREV_B32  = 4348,
    4364             :     S_BREV_B32_si       = 4349,
    4365             :     S_BREV_B32_vi       = 4350,
    4366             :     S_BREV_B64  = 4351,
    4367             :     S_BREV_B64_si       = 4352,
    4368             :     S_BREV_B64_vi       = 4353,
    4369             :     S_BUFFER_LOAD_DWORDX16_IMM  = 4354,
    4370             :     S_BUFFER_LOAD_DWORDX16_IMM_ci       = 4355,
    4371             :     S_BUFFER_LOAD_DWORDX16_IMM_si       = 4356,
    4372             :     S_BUFFER_LOAD_DWORDX16_IMM_vi       = 4357,
    4373             :     S_BUFFER_LOAD_DWORDX16_SGPR = 4358,
    4374             :     S_BUFFER_LOAD_DWORDX16_SGPR_si      = 4359,
    4375             :     S_BUFFER_LOAD_DWORDX16_SGPR_vi      = 4360,
    4376             :     S_BUFFER_LOAD_DWORDX2_IMM   = 4361,
    4377             :     S_BUFFER_LOAD_DWORDX2_IMM_ci        = 4362,
    4378             :     S_BUFFER_LOAD_DWORDX2_IMM_si        = 4363,
    4379             :     S_BUFFER_LOAD_DWORDX2_IMM_vi        = 4364,
    4380             :     S_BUFFER_LOAD_DWORDX2_SGPR  = 4365,
    4381             :     S_BUFFER_LOAD_DWORDX2_SGPR_si       = 4366,
    4382             :     S_BUFFER_LOAD_DWORDX2_SGPR_vi       = 4367,
    4383             :     S_BUFFER_LOAD_DWORDX4_IMM   = 4368,
    4384             :     S_BUFFER_LOAD_DWORDX4_IMM_ci        = 4369,
    4385             :     S_BUFFER_LOAD_DWORDX4_IMM_si        = 4370,
    4386             :     S_BUFFER_LOAD_DWORDX4_IMM_vi        = 4371,
    4387             :     S_BUFFER_LOAD_DWORDX4_SGPR  = 4372,
    4388             :     S_BUFFER_LOAD_DWORDX4_SGPR_si       = 4373,
    4389             :     S_BUFFER_LOAD_DWORDX4_SGPR_vi       = 4374,
    4390             :     S_BUFFER_LOAD_DWORDX8_IMM   = 4375,
    4391             :     S_BUFFER_LOAD_DWORDX8_IMM_ci        = 4376,
    4392             :     S_BUFFER_LOAD_DWORDX8_IMM_si        = 4377,
    4393             :     S_BUFFER_LOAD_DWORDX8_IMM_vi        = 4378,
    4394             :     S_BUFFER_LOAD_DWORDX8_SGPR  = 4379,
    4395             :     S_BUFFER_LOAD_DWORDX8_SGPR_si       = 4380,
    4396             :     S_BUFFER_LOAD_DWORDX8_SGPR_vi       = 4381,
    4397             :     S_BUFFER_LOAD_DWORD_IMM     = 4382,
    4398             :     S_BUFFER_LOAD_DWORD_IMM_ci  = 4383,
    4399             :     S_BUFFER_LOAD_DWORD_IMM_si  = 4384,
    4400             :     S_BUFFER_LOAD_DWORD_IMM_vi  = 4385,
    4401             :     S_BUFFER_LOAD_DWORD_SGPR    = 4386,
    4402             :     S_BUFFER_LOAD_DWORD_SGPR_si = 4387,
    4403             :     S_BUFFER_LOAD_DWORD_SGPR_vi = 4388,
    4404             :     S_BUFFER_STORE_DWORDX2_IMM  = 4389,
    4405             :     S_BUFFER_STORE_DWORDX2_IMM_vi       = 4390,
    4406             :     S_BUFFER_STORE_DWORDX2_SGPR = 4391,
    4407             :     S_BUFFER_STORE_DWORDX2_SGPR_vi      = 4392,
    4408             :     S_BUFFER_STORE_DWORDX4_IMM  = 4393,
    4409             :     S_BUFFER_STORE_DWORDX4_IMM_vi       = 4394,
    4410             :     S_BUFFER_STORE_DWORDX4_SGPR = 4395,
    4411             :     S_BUFFER_STORE_DWORDX4_SGPR_vi      = 4396,
    4412             :     S_BUFFER_STORE_DWORD_IMM    = 4397,
    4413             :     S_BUFFER_STORE_DWORD_IMM_vi = 4398,
    4414             :     S_BUFFER_STORE_DWORD_SGPR   = 4399,
    4415             :     S_BUFFER_STORE_DWORD_SGPR_vi        = 4400,
    4416             :     S_CBRANCH_CDBGSYS   = 4401,
    4417             :     S_CBRANCH_CDBGSYS_AND_USER  = 4402,
    4418             :     S_CBRANCH_CDBGSYS_OR_USER   = 4403,
    4419             :     S_CBRANCH_CDBGUSER  = 4404,
    4420             :     S_CBRANCH_EXECNZ    = 4405,
    4421             :     S_CBRANCH_EXECZ     = 4406,
    4422             :     S_CBRANCH_G_FORK    = 4407,
    4423             :     S_CBRANCH_G_FORK_si = 4408,
    4424             :     S_CBRANCH_G_FORK_vi = 4409,
    4425             :     S_CBRANCH_I_FORK    = 4410,
    4426             :     S_CBRANCH_I_FORK_si = 4411,
    4427             :     S_CBRANCH_I_FORK_vi = 4412,
    4428             :     S_CBRANCH_JOIN      = 4413,
    4429             :     S_CBRANCH_JOIN_si   = 4414,
    4430             :     S_CBRANCH_JOIN_vi   = 4415,
    4431             :     S_CBRANCH_SCC0      = 4416,
    4432             :     S_CBRANCH_SCC1      = 4417,
    4433             :     S_CBRANCH_VCCNZ     = 4418,
    4434             :     S_CBRANCH_VCCZ      = 4419,
    4435             :     S_CMOVK_I32 = 4420,
    4436             :     S_CMOVK_I32_si      = 4421,
    4437             :     S_CMOVK_I32_vi      = 4422,
    4438             :     S_CMOV_B32  = 4423,
    4439             :     S_CMOV_B32_si       = 4424,
    4440             :     S_CMOV_B32_vi       = 4425,
    4441             :     S_CMOV_B64  = 4426,
    4442             :     S_CMOV_B64_si       = 4427,
    4443             :     S_CMOV_B64_vi       = 4428,
    4444             :     S_CMPK_EQ_I32       = 4429,
    4445             :     S_CMPK_EQ_I32_si    = 4430,
    4446             :     S_CMPK_EQ_I32_vi    = 4431,
    4447             :     S_CMPK_EQ_U32       = 4432,
    4448             :     S_CMPK_EQ_U32_si    = 4433,
    4449             :     S_CMPK_EQ_U32_vi    = 4434,
    4450             :     S_CMPK_GE_I32       = 4435,
    4451             :     S_CMPK_GE_I32_si    = 4436,
    4452             :     S_CMPK_GE_I32_vi    = 4437,
    4453             :     S_CMPK_GE_U32       = 4438,
    4454             :     S_CMPK_GE_U32_si    = 4439,
    4455             :     S_CMPK_GE_U32_vi    = 4440,
    4456             :     S_CMPK_GT_I32       = 4441,
    4457             :     S_CMPK_GT_I32_si    = 4442,
    4458             :     S_CMPK_GT_I32_vi    = 4443,
    4459             :     S_CMPK_GT_U32       = 4444,
    4460             :     S_CMPK_GT_U32_si    = 4445,
    4461             :     S_CMPK_GT_U32_vi    = 4446,
    4462             :     S_CMPK_LE_I32       = 4447,
    4463             :     S_CMPK_LE_I32_si    = 4448,
    4464             :     S_CMPK_LE_I32_vi    = 4449,
    4465             :     S_CMPK_LE_U32       = 4450,
    4466             :     S_CMPK_LE_U32_si    = 4451,
    4467             :     S_CMPK_LE_U32_vi    = 4452,
    4468             :     S_CMPK_LG_I32       = 4453,
    4469             :     S_CMPK_LG_I32_si    = 4454,
    4470             :     S_CMPK_LG_I32_vi    = 4455,
    4471             :     S_CMPK_LG_U32       = 4456,
    4472             :     S_CMPK_LG_U32_si    = 4457,
    4473             :     S_CMPK_LG_U32_vi    = 4458,
    4474             :     S_CMPK_LT_I32       = 4459,
    4475             :     S_CMPK_LT_I32_si    = 4460,
    4476             :     S_CMPK_LT_I32_vi    = 4461,
    4477             :     S_CMPK_LT_U32       = 4462,
    4478             :     S_CMPK_LT_U32_si    = 4463,
    4479             :     S_CMPK_LT_U32_vi    = 4464,
    4480             :     S_CMP_EQ_I32        = 4465,
    4481             :     S_CMP_EQ_U32        = 4466,
    4482             :     S_CMP_EQ_U64        = 4467,
    4483             :     S_CMP_GE_I32        = 4468,
    4484             :     S_CMP_GE_U32        = 4469,
    4485             :     S_CMP_GT_I32        = 4470,
    4486             :     S_CMP_GT_U32        = 4471,
    4487             :     S_CMP_LE_I32        = 4472,
    4488             :     S_CMP_LE_U32        = 4473,
    4489             :     S_CMP_LG_I32        = 4474,
    4490             :     S_CMP_LG_U32        = 4475,
    4491             :     S_CMP_LG_U64        = 4476,
    4492             :     S_CMP_LT_I32        = 4477,
    4493             :     S_CMP_LT_U32        = 4478,
    4494             :     S_CSELECT_B32       = 4479,
    4495             :     S_CSELECT_B32_si    = 4480,
    4496             :     S_CSELECT_B32_vi    = 4481,
    4497             :     S_CSELECT_B64       = 4482,
    4498             :     S_CSELECT_B64_si    = 4483,
    4499             :     S_CSELECT_B64_vi    = 4484,
    4500             :     S_DCACHE_INV        = 4485,
    4501             :     S_DCACHE_INV_VOL    = 4486,
    4502             :     S_DCACHE_INV_VOL_ci = 4487,
    4503             :     S_DCACHE_INV_VOL_vi = 4488,
    4504             :     S_DCACHE_INV_si     = 4489,
    4505             :     S_DCACHE_INV_vi     = 4490,
    4506             :     S_DCACHE_WB = 4491,
    4507             :     S_DCACHE_WB_VOL     = 4492,
    4508             :     S_DCACHE_WB_VOL_vi  = 4493,
    4509             :     S_DCACHE_WB_vi      = 4494,
    4510             :     S_DECPERFLEVEL      = 4495,
    4511             :     S_ENDPGM    = 4496,
    4512             :     S_ENDPGM_SAVED      = 4497,
    4513             :     S_FF0_I32_B32       = 4498,
    4514             :     S_FF0_I32_B32_si    = 4499,
    4515             :     S_FF0_I32_B32_vi    = 4500,
    4516             :     S_FF0_I32_B64       = 4501,
    4517             :     S_FF0_I32_B64_si    = 4502,
    4518             :     S_FF0_I32_B64_vi    = 4503,
    4519             :     S_FF1_I32_B32       = 4504,
    4520             :     S_FF1_I32_B32_si    = 4505,
    4521             :     S_FF1_I32_B32_vi    = 4506,
    4522             :     S_FF1_I32_B64       = 4507,
    4523             :     S_FF1_I32_B64_si    = 4508,
    4524             :     S_FF1_I32_B64_vi    = 4509,
    4525             :     S_FLBIT_I32 = 4510,
    4526             :     S_FLBIT_I32_B32     = 4511,
    4527             :     S_FLBIT_I32_B32_si  = 4512,
    4528             :     S_FLBIT_I32_B32_vi  = 4513,
    4529             :     S_FLBIT_I32_B64     = 4514,
    4530             :     S_FLBIT_I32_B64_si  = 4515,
    4531             :     S_FLBIT_I32_B64_vi  = 4516,
    4532             :     S_FLBIT_I32_I64     = 4517,
    4533             :     S_FLBIT_I32_I64_si  = 4518,
    4534             :     S_FLBIT_I32_I64_vi  = 4519,
    4535             :     S_FLBIT_I32_si      = 4520,
    4536             :     S_FLBIT_I32_vi      = 4521,
    4537             :     S_GETPC_B64 = 4522,
    4538             :     S_GETPC_B64_si      = 4523,
    4539             :     S_GETPC_B64_vi      = 4524,
    4540             :     S_GETREG_B32        = 4525,
    4541             :     S_GETREG_B32_si     = 4526,
    4542             :     S_GETREG_B32_vi     = 4527,
    4543             :     S_ICACHE_INV        = 4528,
    4544             :     S_INCPERFLEVEL      = 4529,
    4545             :     S_LOAD_DWORDX16_IMM = 4530,
    4546             :     S_LOAD_DWORDX16_IMM_ci      = 4531,
    4547             :     S_LOAD_DWORDX16_IMM_si      = 4532,
    4548             :     S_LOAD_DWORDX16_IMM_vi      = 4533,
    4549             :     S_LOAD_DWORDX16_SGPR        = 4534,
    4550             :     S_LOAD_DWORDX16_SGPR_si     = 4535,
    4551             :     S_LOAD_DWORDX16_SGPR_vi     = 4536,
    4552             :     S_LOAD_DWORDX2_IMM  = 4537,
    4553             :     S_LOAD_DWORDX2_IMM_ci       = 4538,
    4554             :     S_LOAD_DWORDX2_IMM_si       = 4539,
    4555             :     S_LOAD_DWORDX2_IMM_vi       = 4540,
    4556             :     S_LOAD_DWORDX2_SGPR = 4541,
    4557             :     S_LOAD_DWORDX2_SGPR_si      = 4542,
    4558             :     S_LOAD_DWORDX2_SGPR_vi      = 4543,
    4559             :     S_LOAD_DWORDX4_IMM  = 4544,
    4560             :     S_LOAD_DWORDX4_IMM_ci       = 4545,
    4561             :     S_LOAD_DWORDX4_IMM_si       = 4546,
    4562             :     S_LOAD_DWORDX4_IMM_vi       = 4547,
    4563             :     S_LOAD_DWORDX4_SGPR = 4548,
    4564             :     S_LOAD_DWORDX4_SGPR_si      = 4549,
    4565             :     S_LOAD_DWORDX4_SGPR_vi      = 4550,
    4566             :     S_LOAD_DWORDX8_IMM  = 4551,
    4567             :     S_LOAD_DWORDX8_IMM_ci       = 4552,
    4568             :     S_LOAD_DWORDX8_IMM_si       = 4553,
    4569             :     S_LOAD_DWORDX8_IMM_vi       = 4554,
    4570             :     S_LOAD_DWORDX8_SGPR = 4555,
    4571             :     S_LOAD_DWORDX8_SGPR_si      = 4556,
    4572             :     S_LOAD_DWORDX8_SGPR_vi      = 4557,
    4573             :     S_LOAD_DWORD_IMM    = 4558,
    4574             :     S_LOAD_DWORD_IMM_ci = 4559,
    4575             :     S_LOAD_DWORD_IMM_si = 4560,
    4576             :     S_LOAD_DWORD_IMM_vi = 4561,
    4577             :     S_LOAD_DWORD_SGPR   = 4562,
    4578             :     S_LOAD_DWORD_SGPR_si        = 4563,
    4579             :     S_LOAD_DWORD_SGPR_vi        = 4564,
    4580             :     S_LSHL_B32  = 4565,
    4581             :     S_LSHL_B32_si       = 4566,
    4582             :     S_LSHL_B32_vi       = 4567,
    4583             :     S_LSHL_B64  = 4568,
    4584             :     S_LSHL_B64_si       = 4569,
    4585             :     S_LSHL_B64_vi       = 4570,
    4586             :     S_LSHR_B32  = 4571,
    4587             :     S_LSHR_B32_si       = 4572,
    4588             :     S_LSHR_B32_vi       = 4573,
    4589             :     S_LSHR_B64  = 4574,
    4590             :     S_LSHR_B64_si       = 4575,
    4591             :     S_LSHR_B64_vi       = 4576,
    4592             :     S_MAX_I32   = 4577,
    4593             :     S_MAX_I32_si        = 4578,
    4594             :     S_MAX_I32_vi        = 4579,
    4595             :     S_MAX_U32   = 4580,
    4596             :     S_MAX_U32_si        = 4581,
    4597             :     S_MAX_U32_vi        = 4582,
    4598             :     S_MEMREALTIME       = 4583,
    4599             :     S_MEMREALTIME_vi    = 4584,
    4600             :     S_MEMTIME   = 4585,
    4601             :     S_MEMTIME_si        = 4586,
    4602             :     S_MEMTIME_vi        = 4587,
    4603             :     S_MIN_I32   = 4588,
    4604             :     S_MIN_I32_si        = 4589,
    4605             :     S_MIN_I32_vi        = 4590,
    4606             :     S_MIN_U32   = 4591,
    4607             :     S_MIN_U32_si        = 4592,
    4608             :     S_MIN_U32_vi        = 4593,
    4609             :     S_MOVK_I32  = 4594,
    4610             :     S_MOVK_I32_si       = 4595,
    4611             :     S_MOVK_I32_vi       = 4596,
    4612             :     S_MOVRELD_B32       = 4597,
    4613             :     S_MOVRELD_B32_si    = 4598,
    4614             :     S_MOVRELD_B32_vi    = 4599,
    4615             :     S_MOVRELD_B64       = 4600,
    4616             :     S_MOVRELD_B64_si    = 4601,
    4617             :     S_MOVRELD_B64_vi    = 4602,
    4618             :     S_MOVRELS_B32       = 4603,
    4619             :     S_MOVRELS_B32_si    = 4604,
    4620             :     S_MOVRELS_B32_vi    = 4605,
    4621             :     S_MOVRELS_B64       = 4606,
    4622             :     S_MOVRELS_B64_si    = 4607,
    4623             :     S_MOVRELS_B64_vi    = 4608,
    4624             :     S_MOV_B32   = 4609,
    4625             :     S_MOV_B32_si        = 4610,
    4626             :     S_MOV_B32_vi        = 4611,
    4627             :     S_MOV_B64   = 4612,
    4628             :     S_MOV_B64_si        = 4613,
    4629             :     S_MOV_B64_term      = 4614,
    4630             :     S_MOV_B64_vi        = 4615,
    4631             :     S_MOV_FED_B32       = 4616,
    4632             :     S_MOV_FED_B32_si    = 4617,
    4633             :     S_MOV_FED_B32_vi    = 4618,
    4634             :     S_MOV_REGRD_B32     = 4619,
    4635             :     S_MOV_REGRD_B32_si  = 4620,
    4636             :     S_MOV_REGRD_B32_vi  = 4621,
    4637             :     S_MULK_I32  = 4622,
    4638             :     S_MULK_I32_si       = 4623,
    4639             :     S_MULK_I32_vi       = 4624,
    4640             :     S_MUL_I32   = 4625,
    4641             :     S_MUL_I32_si        = 4626,
    4642             :     S_MUL_I32_vi        = 4627,
    4643             :     S_NAND_B32  = 4628,
    4644             :     S_NAND_B32_si       = 4629,
    4645             :     S_NAND_B32_vi       = 4630,
    4646             :     S_NAND_B64  = 4631,
    4647             :     S_NAND_B64_si       = 4632,
    4648             :     S_NAND_B64_vi       = 4633,
    4649             :     S_NAND_SAVEEXEC_B64 = 4634,
    4650             :     S_NAND_SAVEEXEC_B64_si      = 4635,
    4651             :     S_NAND_SAVEEXEC_B64_vi      = 4636,
    4652             :     S_NOP       = 4637,
    4653             :     S_NOR_B32   = 4638,
    4654             :     S_NOR_B32_si        = 4639,
    4655             :     S_NOR_B32_vi        = 4640,
    4656             :     S_NOR_B64   = 4641,
    4657             :     S_NOR_B64_si        = 4642,
    4658             :     S_NOR_B64_vi        = 4643,
    4659             :     S_NOR_SAVEEXEC_B64  = 4644,
    4660             :     S_NOR_SAVEEXEC_B64_si       = 4645,
    4661             :     S_NOR_SAVEEXEC_B64_vi       = 4646,
    4662             :     S_NOT_B32   = 4647,
    4663             :     S_NOT_B32_si        = 4648,
    4664             :     S_NOT_B32_vi        = 4649,
    4665             :     S_NOT_B64   = 4650,
    4666             :     S_NOT_B64_si        = 4651,
    4667             :     S_NOT_B64_vi        = 4652,
    4668             :     S_ORN2_B32  = 4653,
    4669             :     S_ORN2_B32_si       = 4654,
    4670             :     S_ORN2_B32_vi       = 4655,
    4671             :     S_ORN2_B64  = 4656,
    4672             :     S_ORN2_B64_si       = 4657,
    4673             :     S_ORN2_B64_vi       = 4658,
    4674             :     S_ORN2_SAVEEXEC_B64 = 4659,
    4675             :     S_ORN2_SAVEEXEC_B64_si      = 4660,
    4676             :     S_ORN2_SAVEEXEC_B64_vi      = 4661,
    4677             :     S_OR_B32    = 4662,
    4678             :     S_OR_B32_si = 4663,
    4679             :     S_OR_B32_vi = 4664,
    4680             :     S_OR_B64    = 4665,
    4681             :     S_OR_B64_si = 4666,
    4682             :     S_OR_B64_vi = 4667,
    4683             :     S_OR_SAVEEXEC_B64   = 4668,
    4684             :     S_OR_SAVEEXEC_B64_si        = 4669,
    4685             :     S_OR_SAVEEXEC_B64_vi        = 4670,
    4686             :     S_PACK_HH_B32_B16   = 4671,
    4687             :     S_PACK_HH_B32_B16_vi        = 4672,
    4688             :     S_PACK_LH_B32_B16   = 4673,
    4689             :     S_PACK_LH_B32_B16_vi        = 4674,
    4690             :     S_PACK_LL_B32_B16   = 4675,
    4691             :     S_PACK_LL_B32_B16_vi        = 4676,
    4692             :     S_QUADMASK_B32      = 4677,
    4693             :     S_QUADMASK_B32_si   = 4678,
    4694             :     S_QUADMASK_B32_vi   = 4679,
    4695             :     S_QUADMASK_B64      = 4680,
    4696             :     S_QUADMASK_B64_si   = 4681,
    4697             :     S_QUADMASK_B64_vi   = 4682,
    4698             :     S_RFE_B64   = 4683,
    4699             :     S_RFE_B64_si        = 4684,
    4700             :     S_RFE_B64_vi        = 4685,
    4701             :     S_RFE_RESTORE_B64   = 4686,
    4702             :     S_RFE_RESTORE_B64_vi        = 4687,
    4703             :     S_SENDMSG   = 4688,
    4704             :     S_SENDMSGHALT       = 4689,
    4705             :     S_SETHALT   = 4690,
    4706             :     S_SETKILL   = 4691,
    4707             :     S_SETPC_B64 = 4692,
    4708             :     S_SETPC_B64_return  = 4693,
    4709             :     S_SETPC_B64_si      = 4694,
    4710             :     S_SETPC_B64_vi      = 4695,
    4711             :     S_SETPRIO   = 4696,
    4712             :     S_SETREG_B32        = 4697,
    4713             :     S_SETREG_B32_si     = 4698,
    4714             :     S_SETREG_B32_vi     = 4699,
    4715             :     S_SETREG_IMM32_B32  = 4700,
    4716             :     S_SETREG_IMM32_B32_si       = 4701,
    4717             :     S_SETREG_IMM32_B32_vi       = 4702,
    4718             :     S_SETVSKIP  = 4703,
    4719             :     S_SET_GPR_IDX_IDX   = 4704,
    4720             :     S_SET_GPR_IDX_IDX_vi        = 4705,
    4721             :     S_SET_GPR_IDX_MODE  = 4706,
    4722             :     S_SET_GPR_IDX_OFF   = 4707,
    4723             :     S_SET_GPR_IDX_ON    = 4708,
    4724             :     S_SEXT_I32_I16      = 4709,
    4725             :     S_SEXT_I32_I16_si   = 4710,
    4726             :     S_SEXT_I32_I16_vi   = 4711,
    4727             :     S_SEXT_I32_I8       = 4712,
    4728             :     S_SEXT_I32_I8_si    = 4713,
    4729             :     S_SEXT_I32_I8_vi    = 4714,
    4730             :     S_SLEEP     = 4715,
    4731             :     S_STORE_DWORDX2_IMM = 4716,
    4732             :     S_STORE_DWORDX2_IMM_vi      = 4717,
    4733             :     S_STORE_DWORDX2_SGPR        = 4718,
    4734             :     S_STORE_DWORDX2_SGPR_vi     = 4719,
    4735             :     S_STORE_DWORDX4_IMM = 4720,
    4736             :     S_STORE_DWORDX4_IMM_vi      = 4721,
    4737             :     S_STORE_DWORDX4_SGPR        = 4722,
    4738             :     S_STORE_DWORDX4_SGPR_vi     = 4723,
    4739             :     S_STORE_DWORD_IMM   = 4724,
    4740             :     S_STORE_DWORD_IMM_vi        = 4725,
    4741             :     S_STORE_DWORD_SGPR  = 4726,
    4742             :     S_STORE_DWORD_SGPR_vi       = 4727,
    4743             :     S_SUBB_U32  = 4728,
    4744             :     S_SUBB_U32_si       = 4729,
    4745             :     S_SUBB_U32_vi       = 4730,
    4746             :     S_SUB_I32   = 4731,
    4747             :     S_SUB_I32_si        = 4732,
    4748             :     S_SUB_I32_vi        = 4733,
    4749             :     S_SUB_U32   = 4734,
    4750             :     S_SUB_U32_si        = 4735,
    4751             :     S_SUB_U32_vi        = 4736,
    4752             :     S_SWAPPC_B64        = 4737,
    4753             :     S_SWAPPC_B64_si     = 4738,
    4754             :     S_SWAPPC_B64_vi     = 4739,
    4755             :     S_TRAP      = 4740,
    4756             :     S_TTRACEDATA        = 4741,
    4757             :     S_WAITCNT   = 4742,
    4758             :     S_WAKEUP    = 4743,
    4759             :     S_WQM_B32   = 4744,
    4760             :     S_WQM_B32_si        = 4745,
    4761             :     S_WQM_B32_vi        = 4746,
    4762             :     S_WQM_B64   = 4747,
    4763             :     S_WQM_B64_si        = 4748,
    4764             :     S_WQM_B64_vi        = 4749,
    4765             :     S_XNOR_B32  = 4750,
    4766             :     S_XNOR_B32_si       = 4751,
    4767             :     S_XNOR_B32_vi       = 4752,
    4768             :     S_XNOR_B64  = 4753,
    4769             :     S_XNOR_B64_si       = 4754,
    4770             :     S_XNOR_B64_vi       = 4755,
    4771             :     S_XNOR_SAVEEXEC_B64 = 4756,
    4772             :     S_XNOR_SAVEEXEC_B64_si      = 4757,
    4773             :     S_XNOR_SAVEEXEC_B64_vi      = 4758,
    4774             :     S_XOR_B32   = 4759,
    4775             :     S_XOR_B32_si        = 4760,
    4776             :     S_XOR_B32_vi        = 4761,
    4777             :     S_XOR_B64   = 4762,
    4778             :     S_XOR_B64_si        = 4763,
    4779             :     S_XOR_B64_term      = 4764,
    4780             :     S_XOR_B64_vi        = 4765,
    4781             :     S_XOR_SAVEEXEC_B64  = 4766,
    4782             :     S_XOR_SAVEEXEC_B64_si       = 4767,
    4783             :     S_XOR_SAVEEXEC_B64_vi       = 4768,
    4784             :     TBUFFER_LOAD_FORMAT_XYZW_ADDR64     = 4769,
    4785             :     TBUFFER_LOAD_FORMAT_XYZW_ADDR64_si  = 4770,
    4786             :     TBUFFER_LOAD_FORMAT_XYZW_BOTHEN     = 4771,
    4787             :     TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_exact       = 4772,
    4788             :     TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_si  = 4773,
    4789             :     TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi  = 4774,
    4790             :     TBUFFER_LOAD_FORMAT_XYZW_IDXEN      = 4775,
    4791             :     TBUFFER_LOAD_FORMAT_XYZW_IDXEN_exact        = 4776,
    4792             :     TBUFFER_LOAD_FORMAT_XYZW_IDXEN_si   = 4777,
    4793             :     TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi   = 4778,
    4794             :     TBUFFER_LOAD_FORMAT_XYZW_OFFEN      = 4779,
    4795             :     TBUFFER_LOAD_FORMAT_XYZW_OFFEN_exact        = 4780,
    4796             :     TBUFFER_LOAD_FORMAT_XYZW_OFFEN_si   = 4781,
    4797             :     TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi   = 4782,
    4798             :     TBUFFER_LOAD_FORMAT_XYZW_OFFSET     = 4783,
    4799             :     TBUFFER_LOAD_FORMAT_XYZW_OFFSET_exact       = 4784,
    4800             :     TBUFFER_LOAD_FORMAT_XYZW_OFFSET_si  = 4785,
    4801             :     TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi  = 4786,
    4802             :     TBUFFER_LOAD_FORMAT_XYZ_ADDR64      = 4787,
    4803             :     TBUFFER_LOAD_FORMAT_XYZ_BOTHEN      = 4788,
    4804             :     TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_exact        = 4789,
    4805             :     TBUFFER_LOAD_FORMAT_XYZ_IDXEN       = 4790,
    4806             :     TBUFFER_LOAD_FORMAT_XYZ_IDXEN_exact = 4791,
    4807             :     TBUFFER_LOAD_FORMAT_XYZ_OFFEN       = 4792,
    4808             :     TBUFFER_LOAD_FORMAT_XYZ_OFFEN_exact = 4793,
    4809             :     TBUFFER_LOAD_FORMAT_XYZ_OFFSET      = 4794,
    4810             :     TBUFFER_LOAD_FORMAT_XYZ_OFFSET_exact        = 4795,
    4811             :     TBUFFER_LOAD_FORMAT_XY_ADDR64       = 4796,
    4812             :     TBUFFER_LOAD_FORMAT_XY_ADDR64_si    = 4797,
    4813             :     TBUFFER_LOAD_FORMAT_XY_BOTHEN       = 4798,
    4814             :     TBUFFER_LOAD_FORMAT_XY_BOTHEN_exact = 4799,
    4815             :     TBUFFER_LOAD_FORMAT_XY_BOTHEN_si    = 4800,
    4816             :     TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi    = 4801,
    4817             :     TBUFFER_LOAD_FORMAT_XY_IDXEN        = 4802,
    4818             :     TBUFFER_LOAD_FORMAT_XY_IDXEN_exact  = 4803,
    4819             :     TBUFFER_LOAD_FORMAT_XY_IDXEN_si     = 4804,
    4820             :     TBUFFER_LOAD_FORMAT_XY_IDXEN_vi     = 4805,
    4821             :     TBUFFER_LOAD_FORMAT_XY_OFFEN        = 4806,
    4822             :     TBUFFER_LOAD_FORMAT_XY_OFFEN_exact  = 4807,
    4823             :     TBUFFER_LOAD_FORMAT_XY_OFFEN_si     = 4808,
    4824             :     TBUFFER_LOAD_FORMAT_XY_OFFEN_vi     = 4809,
    4825             :     TBUFFER_LOAD_FORMAT_XY_OFFSET       = 4810,
    4826             :     TBUFFER_LOAD_FORMAT_XY_OFFSET_exact = 4811,
    4827             :     TBUFFER_LOAD_FORMAT_XY_OFFSET_si    = 4812,
    4828             :     TBUFFER_LOAD_FORMAT_XY_OFFSET_vi    = 4813,
    4829             :     TBUFFER_LOAD_FORMAT_X_ADDR64        = 4814,
    4830             :     TBUFFER_LOAD_FORMAT_X_ADDR64_si     = 4815,
    4831             :     TBUFFER_LOAD_FORMAT_X_BOTHEN        = 4816,
    4832             :     TBUFFER_LOAD_FORMAT_X_BOTHEN_exact  = 4817,
    4833             :     TBUFFER_LOAD_FORMAT_X_BOTHEN_si     = 4818,
    4834             :     TBUFFER_LOAD_FORMAT_X_BOTHEN_vi     = 4819,
    4835             :     TBUFFER_LOAD_FORMAT_X_IDXEN = 4820,
    4836             :     TBUFFER_LOAD_FORMAT_X_IDXEN_exact   = 4821,
    4837             :     TBUFFER_LOAD_FORMAT_X_IDXEN_si      = 4822,
    4838             :     TBUFFER_LOAD_FORMAT_X_IDXEN_vi      = 4823,
    4839             :     TBUFFER_LOAD_FORMAT_X_OFFEN = 4824,
    4840             :     TBUFFER_LOAD_FORMAT_X_OFFEN_exact   = 4825,
    4841             :     TBUFFER_LOAD_FORMAT_X_OFFEN_si      = 4826,
    4842             :     TBUFFER_LOAD_FORMAT_X_OFFEN_vi      = 4827,
    4843             :     TBUFFER_LOAD_FORMAT_X_OFFSET        = 4828,
    4844             :     TBUFFER_LOAD_FORMAT_X_OFFSET_exact  = 4829,
    4845             :     TBUFFER_LOAD_FORMAT_X_OFFSET_si     = 4830,
    4846             :     TBUFFER_LOAD_FORMAT_X_OFFSET_vi     = 4831,
    4847             :     TBUFFER_STORE_FORMAT_XYZW_ADDR64    = 4832,
    4848             :     TBUFFER_STORE_FORMAT_XYZW_ADDR64_si = 4833,
    4849             :     TBUFFER_STORE_FORMAT_XYZW_BOTHEN    = 4834,
    4850             :     TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact      = 4835,
    4851             :     TBUFFER_STORE_FORMAT_XYZW_BOTHEN_si = 4836,
    4852             :     TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi = 4837,
    4853             :     TBUFFER_STORE_FORMAT_XYZW_IDXEN     = 4838,
    4854             :     TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact       = 4839,
    4855             :     TBUFFER_STORE_FORMAT_XYZW_IDXEN_si  = 4840,
    4856             :     TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi  = 4841,
    4857             :     TBUFFER_STORE_FORMAT_XYZW_OFFEN     = 4842,
    4858             :     TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact       = 4843,
    4859             :     TBUFFER_STORE_FORMAT_XYZW_OFFEN_si  = 4844,
    4860             :     TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi  = 4845,
    4861             :     TBUFFER_STORE_FORMAT_XYZW_OFFSET    = 4846,
    4862             :     TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact      = 4847,
    4863             :     TBUFFER_STORE_FORMAT_XYZW_OFFSET_si = 4848,
    4864             :     TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi = 4849,
    4865             :     TBUFFER_STORE_FORMAT_XYZ_ADDR64     = 4850,
    4866             :     TBUFFER_STORE_FORMAT_XYZ_ADDR64_si  = 4851,
    4867             :     TBUFFER_STORE_FORMAT_XYZ_BOTHEN     = 4852,
    4868             :     TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact       = 4853,
    4869             :     TBUFFER_STORE_FORMAT_XYZ_BOTHEN_si  = 4854,
    4870             :     TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi  = 4855,
    4871             :     TBUFFER_STORE_FORMAT_XYZ_IDXEN      = 4856,
    4872             :     TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact        = 4857,
    4873             :     TBUFFER_STORE_FORMAT_XYZ_IDXEN_si   = 4858,
    4874             :     TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi   = 4859,
    4875             :     TBUFFER_STORE_FORMAT_XYZ_OFFEN      = 4860,
    4876             :     TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact        = 4861,
    4877             :     TBUFFER_STORE_FORMAT_XYZ_OFFEN_si   = 4862,
    4878             :     TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi   = 4863,
    4879             :     TBUFFER_STORE_FORMAT_XYZ_OFFSET     = 4864,
    4880             :     TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact       = 4865,
    4881             :     TBUFFER_STORE_FORMAT_XYZ_OFFSET_si  = 4866,
    4882             :     TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi  = 4867,
    4883             :     TBUFFER_STORE_FORMAT_XY_ADDR64      = 4868,
    4884             :     TBUFFER_STORE_FORMAT_XY_ADDR64_si   = 4869,
    4885             :     TBUFFER_STORE_FORMAT_XY_BOTHEN      = 4870,
    4886             :     TBUFFER_STORE_FORMAT_XY_BOTHEN_exact        = 4871,
    4887             :     TBUFFER_STORE_FORMAT_XY_BOTHEN_si   = 4872,
    4888             :     TBUFFER_STORE_FORMAT_XY_BOTHEN_vi   = 4873,
    4889             :     TBUFFER_STORE_FORMAT_XY_IDXEN       = 4874,
    4890             :     TBUFFER_STORE_FORMAT_XY_IDXEN_exact = 4875,
    4891             :     TBUFFER_STORE_FORMAT_XY_IDXEN_si    = 4876,
    4892             :     TBUFFER_STORE_FORMAT_XY_IDXEN_vi    = 4877,
    4893             :     TBUFFER_STORE_FORMAT_XY_OFFEN       = 4878,
    4894             :     TBUFFER_STORE_FORMAT_XY_OFFEN_exact = 4879,
    4895             :     TBUFFER_STORE_FORMAT_XY_OFFEN_si    = 4880,
    4896             :     TBUFFER_STORE_FORMAT_XY_OFFEN_vi    = 4881,
    4897             :     TBUFFER_STORE_FORMAT_XY_OFFSET      = 4882,
    4898             :     TBUFFER_STORE_FORMAT_XY_OFFSET_exact        = 4883,
    4899             :     TBUFFER_STORE_FORMAT_XY_OFFSET_si   = 4884,
    4900             :     TBUFFER_STORE_FORMAT_XY_OFFSET_vi   = 4885,
    4901             :     TBUFFER_STORE_FORMAT_X_ADDR64       = 4886,
    4902             :     TBUFFER_STORE_FORMAT_X_ADDR64_si    = 4887,
    4903             :     TBUFFER_STORE_FORMAT_X_BOTHEN       = 4888,
    4904             :     TBUFFER_STORE_FORMAT_X_BOTHEN_exact = 4889,
    4905             :     TBUFFER_STORE_FORMAT_X_BOTHEN_si    = 4890,
    4906             :     TBUFFER_STORE_FORMAT_X_BOTHEN_vi    = 4891,
    4907             :     TBUFFER_STORE_FORMAT_X_IDXEN        = 4892,
    4908             :     TBUFFER_STORE_FORMAT_X_IDXEN_exact  = 4893,
    4909             :     TBUFFER_STORE_FORMAT_X_IDXEN_si     = 4894,
    4910             :     TBUFFER_STORE_FORMAT_X_IDXEN_vi     = 4895,
    4911             :     TBUFFER_STORE_FORMAT_X_OFFEN        = 4896,
    4912             :     TBUFFER_STORE_FORMAT_X_OFFEN_exact  = 4897,
    4913             :     TBUFFER_STORE_FORMAT_X_OFFEN_si     = 4898,
    4914             :     TBUFFER_STORE_FORMAT_X_OFFEN_vi     = 4899,
    4915             :     TBUFFER_STORE_FORMAT_X_OFFSET       = 4900,
    4916             :     TBUFFER_STORE_FORMAT_X_OFFSET_exact = 4901,
    4917             :     TBUFFER_STORE_FORMAT_X_OFFSET_si    = 4902,
    4918             :     TBUFFER_STORE_FORMAT_X_OFFSET_vi    = 4903,
    4919             :     TEX_GET_GRADIENTS_H = 4904,
    4920             :     TEX_GET_GRADIENTS_V = 4905,
    4921             :     TEX_GET_TEXTURE_RESINFO     = 4906,
    4922             :     TEX_LD      = 4907,
    4923             :     TEX_LDPTR   = 4908,
    4924             :     TEX_SAMPLE  = 4909,
    4925             :     TEX_SAMPLE_C        = 4910,
    4926             :     TEX_SAMPLE_C_G      = 4911,
    4927             :     TEX_SAMPLE_C_L      = 4912,
    4928             :     TEX_SAMPLE_C_LB     = 4913,
    4929             :     TEX_SAMPLE_G        = 4914,
    4930             :     TEX_SAMPLE_L        = 4915,
    4931             :     TEX_SAMPLE_LB       = 4916,
    4932             :     TEX_SET_GRADIENTS_H = 4917,
    4933             :     TEX_SET_GRADIENTS_V = 4918,
    4934             :     TEX_VTX_CONSTBUF    = 4919,
    4935             :     TEX_VTX_TEXBUF      = 4920,
    4936             :     TRUNC       = 4921,
    4937             :     TXD = 4922,
    4938             :     TXD_SHADOW  = 4923,
    4939             :     UINT_TO_FLT_eg      = 4924,
    4940             :     UINT_TO_FLT_r600    = 4925,
    4941             :     VTX_READ_128_cm     = 4926,
    4942             :     VTX_READ_128_eg     = 4927,
    4943             :     VTX_READ_16_cm      = 4928,
    4944             :     VTX_READ_16_eg      = 4929,
    4945             :     VTX_READ_32_cm      = 4930,
    4946             :     VTX_READ_32_eg      = 4931,
    4947             :     VTX_READ_64_cm      = 4932,
    4948             :     VTX_READ_64_eg      = 4933,
    4949             :     VTX_READ_8_cm       = 4934,
    4950             :     VTX_READ_8_eg       = 4935,
    4951             :     V_ADD3_U32  = 4936,
    4952             :     V_ADD3_U32_vi       = 4937,
    4953             :     V_ADDC_U32_dpp      = 4938,
    4954             :     V_ADDC_U32_e32      = 4939,
    4955             :     V_ADDC_U32_e32_si   = 4940,
    4956             :     V_ADDC_U32_e32_vi   = 4941,
    4957             :     V_ADDC_U32_e64      = 4942,
    4958             :     V_ADDC_U32_e64_si   = 4943,
    4959             :     V_ADDC_U32_e64_vi   = 4944,
    4960             :     V_ADDC_U32_sdwa     = 4945,
    4961             :     V_ADDC_U32_sdwa_gfx9        = 4946,
    4962             :     V_ADDC_U32_sdwa_vi  = 4947,
    4963             :     V_ADD_F16_dpp       = 4948,
    4964             :     V_ADD_F16_e32       = 4949,
    4965             :     V_ADD_F16_e32_vi    = 4950,
    4966             :     V_ADD_F16_e64       = 4951,
    4967             :     V_ADD_F16_e64_vi    = 4952,
    4968             :     V_ADD_F16_sdwa      = 4953,
    4969             :     V_ADD_F16_sdwa_gfx9 = 4954,
    4970             :     V_ADD_F16_sdwa_vi   = 4955,
    4971             :     V_ADD_F32_dpp       = 4956,
    4972             :     V_ADD_F32_e32       = 4957,
    4973             :     V_ADD_F32_e32_si    = 4958,
    4974             :     V_ADD_F32_e32_vi    = 4959,
    4975             :     V_ADD_F32_e64       = 4960,
    4976             :     V_ADD_F32_e64_si    = 4961,
    4977             :     V_ADD_F32_e64_vi    = 4962,
    4978             :     V_ADD_F32_sdwa      = 4963,
    4979             :     V_ADD_F32_sdwa_gfx9 = 4964,
    4980             :     V_ADD_F32_sdwa_vi   = 4965,
    4981             :     V_ADD_F64   = 4966,
    4982             :     V_ADD_F64_si        = 4967,
    4983             :     V_ADD_F64_vi        = 4968,
    4984             :     V_ADD_I16   = 4969,
    4985             :     V_ADD_I16_vi        = 4970,
    4986             :     V_ADD_I32_dpp       = 4971,
    4987             :     V_ADD_I32_e32       = 4972,
    4988             :     V_ADD_I32_e32_si    = 4973,
    4989             :     V_ADD_I32_e32_vi    = 4974,
    4990             :     V_ADD_I32_e64       = 4975,
    4991             :     V_ADD_I32_e64_si    = 4976,
    4992             :     V_ADD_I32_e64_vi    = 4977,
    4993             :     V_ADD_I32_sdwa      = 4978,
    4994             :     V_ADD_I32_sdwa_gfx9 = 4979,
    4995             :     V_ADD_I32_sdwa_vi   = 4980,
    4996             :     V_ADD_LSHL_U32      = 4981,
    4997             :     V_ADD_LSHL_U32_vi   = 4982,
    4998             :     V_ADD_U16_dpp       = 4983,
    4999             :     V_ADD_U16_e32       = 4984,
    5000             :     V_ADD_U16_e32_vi    = 4985,
    5001             :     V_ADD_U16_e64       = 4986,
    5002             :     V_ADD_U16_e64_vi    = 4987,
    5003             :     V_ADD_U16_sdwa      = 4988,
    5004             :     V_ADD_U16_sdwa_gfx9 = 4989,
    5005             :     V_ADD_U16_sdwa_vi   = 4990,
    5006             :     V_ADD_U32_dpp       = 4991,
    5007             :     V_ADD_U32_e32       = 4992,
    5008             :     V_ADD_U32_e32_vi    = 4993,
    5009             :     V_ADD_U32_e64       = 4994,
    5010             :     V_ADD_U32_e64_vi    = 4995,
    5011             :     V_ADD_U32_sdwa      = 4996,
    5012             :     V_ADD_U32_sdwa_gfx9 = 4997,
    5013             :     V_ADD_U32_sdwa_vi   = 4998,
    5014             :     V_ALIGNBIT_B32      = 4999,
    5015             :     V_ALIGNBIT_B32_si   = 5000,
    5016             :     V_ALIGNBIT_B32_vi   = 5001,
    5017             :     V_ALIGNBYTE_B32     = 5002,
    5018             :     V_ALIGNBYTE_B32_si  = 5003,
    5019             :     V_ALIGNBYTE_B32_vi  = 5004,
    5020             :     V_AND_B32_dpp       = 5005,
    5021             :     V_AND_B32_e32       = 5006,
    5022             :     V_AND_B32_e32_si    = 5007,
    5023             :     V_AND_B32_e32_vi    = 5008,
    5024             :     V_AND_B32_e64       = 5009,
    5025             :     V_AND_B32_e64_si    = 5010,
    5026             :     V_AND_B32_e64_vi    = 5011,
    5027             :     V_AND_B32_sdwa      = 5012,
    5028             :     V_AND_B32_sdwa_gfx9 = 5013,
    5029             :     V_AND_B32_sdwa_vi   = 5014,
    5030             :     V_AND_OR_B32        = 5015,
    5031             :     V_AND_OR_B32_vi     = 5016,
    5032             :     V_ASHRREV_I16_dpp   = 5017,
    5033             :     V_ASHRREV_I16_e32   = 5018,
    5034             :     V_ASHRREV_I16_e32_vi        = 5019,
    5035             :     V_ASHRREV_I16_e64   = 5020,
    5036             :     V_ASHRREV_I16_e64_vi        = 5021,
    5037             :     V_ASHRREV_I16_sdwa  = 5022,
    5038             :     V_ASHRREV_I16_sdwa_gfx9     = 5023,
    5039             :     V_ASHRREV_I16_sdwa_vi       = 5024,
    5040             :     V_ASHRREV_I32_dpp   = 5025,
    5041             :     V_ASHRREV_I32_e32   = 5026,
    5042             :     V_ASHRREV_I32_e32_si        = 5027,
    5043             :     V_ASHRREV_I32_e32_vi        = 5028,
    5044             :     V_ASHRREV_I32_e64   = 5029,
    5045             :     V_ASHRREV_I32_e64_si        = 5030,
    5046             :     V_ASHRREV_I32_e64_vi        = 5031,
    5047             :     V_ASHRREV_I32_sdwa  = 5032,
    5048             :     V_ASHRREV_I32_sdwa_gfx9     = 5033,
    5049             :     V_ASHRREV_I32_sdwa_vi       = 5034,
    5050             :     V_ASHRREV_I64       = 5035,
    5051             :     V_ASHRREV_I64_vi    = 5036,
    5052             :     V_ASHR_I32_e32      = 5037,
    5053             :     V_ASHR_I32_e32_si   = 5038,
    5054             :     V_ASHR_I32_e64      = 5039,
    5055             :     V_ASHR_I32_e64_si   = 5040,
    5056             :     V_ASHR_I32_sdwa     = 5041,
    5057             :     V_ASHR_I64  = 5042,
    5058             :     V_ASHR_I64_si       = 5043,
    5059             :     V_BCNT_U32_B32_e32  = 5044,
    5060             :     V_BCNT_U32_B32_e32_si       = 5045,
    5061             :     V_BCNT_U32_B32_e64  = 5046,
    5062             :     V_BCNT_U32_B32_e64_si       = 5047,
    5063             :     V_BCNT_U32_B32_e64_vi       = 5048,
    5064             :     V_BCNT_U32_B32_sdwa = 5049,
    5065             :     V_BFE_I32   = 5050,
    5066             :     V_BFE_I32_si        = 5051,
    5067             :     V_BFE_I32_vi        = 5052,
    5068             :     V_BFE_U32   = 5053,
    5069             :     V_BFE_U32_si        = 5054,
    5070             :     V_BFE_U32_vi        = 5055,
    5071             :     V_BFI_B32   = 5056,
    5072             :     V_BFI_B32_si        = 5057,
    5073             :     V_BFI_B32_vi        = 5058,
    5074             :     V_BFM_B32_e32       = 5059,
    5075             :     V_BFM_B32_e32_si    = 5060,
    5076             :     V_BFM_B32_e64       = 5061,
    5077             :     V_BFM_B32_e64_si    = 5062,
    5078             :     V_BFM_B32_e64_vi    = 5063,
    5079             :     V_BFM_B32_sdwa      = 5064,
    5080             :     V_BFREV_B32_dpp     = 5065,
    5081             :     V_BFREV_B32_e32     = 5066,
    5082             :     V_BFREV_B32_e32_si  = 5067,
    5083             :     V_BFREV_B32_e32_vi  = 5068,
    5084             :     V_BFREV_B32_e64     = 5069,
    5085             :     V_BFREV_B32_e64_si  = 5070,
    5086             :     V_BFREV_B32_e64_vi  = 5071,
    5087             :     V_BFREV_B32_sdwa    = 5072,
    5088             :     V_BFREV_B32_sdwa_gfx9       = 5073,
    5089             :     V_BFREV_B32_sdwa_vi = 5074,
    5090             :     V_CEIL_F16_dpp      = 5075,
    5091             :     V_CEIL_F16_e32      = 5076,
    5092             :     V_CEIL_F16_e32_vi   = 5077,
    5093             :     V_CEIL_F16_e64      = 5078,
    5094             :     V_CEIL_F16_e64_vi   = 5079,
    5095             :     V_CEIL_F16_sdwa     = 5080,
    5096             :     V_CEIL_F16_sdwa_gfx9        = 5081,
    5097             :     V_CEIL_F16_sdwa_vi  = 5082,
    5098             :     V_CEIL_F32_dpp      = 5083,
    5099             :     V_CEIL_F32_e32      = 5084,
    5100             :     V_CEIL_F32_e32_si   = 5085,
    5101             :     V_CEIL_F32_e32_vi   = 5086,
    5102             :     V_CEIL_F32_e64      = 5087,
    5103             :     V_CEIL_F32_e64_si   = 5088,
    5104             :     V_CEIL_F32_e64_vi   = 5089,
    5105             :     V_CEIL_F32_sdwa     = 5090,
    5106             :     V_CEIL_F32_sdwa_gfx9        = 5091,
    5107             :     V_CEIL_F32_sdwa_vi  = 5092,
    5108             :     V_CEIL_F64_dpp      = 5093,
    5109             :     V_CEIL_F64_e32      = 5094,
    5110             :     V_CEIL_F64_e32_ci   = 5095,
    5111             :     V_CEIL_F64_e32_vi   = 5096,
    5112             :     V_CEIL_F64_e64      = 5097,
    5113             :     V_CEIL_F64_e64_ci   = 5098,
    5114             :     V_CEIL_F64_e64_vi   = 5099,
    5115             :     V_CEIL_F64_sdwa     = 5100,
    5116             :     V_CEIL_F64_sdwa_gfx9        = 5101,
    5117             :     V_CEIL_F64_sdwa_vi  = 5102,
    5118             :     V_CLREXCP_dpp       = 5103,
    5119             :     V_CLREXCP_e32       = 5104,
    5120             :     V_CLREXCP_e32_si    = 5105,
    5121             :     V_CLREXCP_e32_vi    = 5106,
    5122             :     V_CLREXCP_e64       = 5107,
    5123             :     V_CLREXCP_e64_si    = 5108,
    5124             :     V_CLREXCP_e64_vi    = 5109,
    5125             :     V_CLREXCP_sdwa      = 5110,
    5126             :     V_CLREXCP_sdwa_gfx9 = 5111,
    5127             :     V_CLREXCP_sdwa_vi   = 5112,
    5128             :     V_CMPSX_EQ_F32_e32  = 5113,
    5129             :     V_CMPSX_EQ_F32_e32_si       = 5114,
    5130             :     V_CMPSX_EQ_F32_e64  = 5115,
    5131             :     V_CMPSX_EQ_F32_e64_si       = 5116,
    5132             :     V_CMPSX_EQ_F32_sdwa = 5117,
    5133             :     V_CMPSX_EQ_F64_e32  = 5118,
    5134             :     V_CMPSX_EQ_F64_e32_si       = 5119,
    5135             :     V_CMPSX_EQ_F64_e64  = 5120,
    5136             :     V_CMPSX_EQ_F64_e64_si       = 5121,
    5137             :     V_CMPSX_EQ_F64_sdwa = 5122,
    5138             :     V_CMPSX_F_F32_e32   = 5123,
    5139             :     V_CMPSX_F_F32_e32_si        = 5124,
    5140             :     V_CMPSX_F_F32_e64   = 5125,
    5141             :     V_CMPSX_F_F32_e64_si        = 5126,
    5142             :     V_CMPSX_F_F32_sdwa  = 5127,
    5143             :     V_CMPSX_F_F64_e32   = 5128,
    5144             :     V_CMPSX_F_F64_e32_si        = 5129,
    5145             :     V_CMPSX_F_F64_e64   = 5130,
    5146             :     V_CMPSX_F_F64_e64_si        = 5131,
    5147             :     V_CMPSX_F_F64_sdwa  = 5132,
    5148             :     V_CMPSX_GE_F32_e32  = 5133,
    5149             :     V_CMPSX_GE_F32_e32_si       = 5134,
    5150             :     V_CMPSX_GE_F32_e64  = 5135,
    5151             :     V_CMPSX_GE_F32_e64_si       = 5136,
    5152             :     V_CMPSX_GE_F32_sdwa = 5137,
    5153             :     V_CMPSX_GE_F64_e32  = 5138,
    5154             :     V_CMPSX_GE_F64_e32_si       = 5139,
    5155             :     V_CMPSX_GE_F64_e64  = 5140,
    5156             :     V_CMPSX_GE_F64_e64_si       = 5141,
    5157             :     V_CMPSX_GE_F64_sdwa = 5142,
    5158             :     V_CMPSX_GT_F32_e32  = 5143,
    5159             :     V_CMPSX_GT_F32_e32_si       = 5144,
    5160             :     V_CMPSX_GT_F32_e64  = 5145,
    5161             :     V_CMPSX_GT_F32_e64_si       = 5146,
    5162             :     V_CMPSX_GT_F32_sdwa = 5147,
    5163             :     V_CMPSX_GT_F64_e32  = 5148,
    5164             :     V_CMPSX_GT_F64_e32_si       = 5149,
    5165             :     V_CMPSX_GT_F64_e64  = 5150,
    5166             :     V_CMPSX_GT_F64_e64_si       = 5151,
    5167             :     V_CMPSX_GT_F64_sdwa = 5152,
    5168             :     V_CMPSX_LE_F32_e32  = 5153,
    5169             :     V_CMPSX_LE_F32_e32_si       = 5154,
    5170             :     V_CMPSX_LE_F32_e64  = 5155,
    5171             :     V_CMPSX_LE_F32_e64_si       = 5156,
    5172             :     V_CMPSX_LE_F32_sdwa = 5157,
    5173             :     V_CMPSX_LE_F64_e32  = 5158,
    5174             :     V_CMPSX_LE_F64_e32_si       = 5159,
    5175             :     V_CMPSX_LE_F64_e64  = 5160,
    5176             :     V_CMPSX_LE_F64_e64_si       = 5161,
    5177             :     V_CMPSX_LE_F64_sdwa = 5162,
    5178             :     V_CMPSX_LG_F32_e32  = 5163,
    5179             :     V_CMPSX_LG_F32_e32_si       = 5164,
    5180             :     V_CMPSX_LG_F32_e64  = 5165,
    5181             :     V_CMPSX_LG_F32_e64_si       = 5166,
    5182             :     V_CMPSX_LG_F32_sdwa = 5167,
    5183             :     V_CMPSX_LG_F64_e32  = 5168,
    5184             :     V_CMPSX_LG_F64_e32_si       = 5169,
    5185             :     V_CMPSX_LG_F64_e64  = 5170,
    5186             :     V_CMPSX_LG_F64_e64_si       = 5171,
    5187             :     V_CMPSX_LG_F64_sdwa = 5172,
    5188             :     V_CMPSX_LT_F32_e32  = 5173,
    5189             :     V_CMPSX_LT_F32_e32_si       = 5174,
    5190             :     V_CMPSX_LT_F32_e64  = 5175,
    5191             :     V_CMPSX_LT_F32_e64_si       = 5176,
    5192             :     V_CMPSX_LT_F32_sdwa = 5177,
    5193             :     V_CMPSX_LT_F64_e32  = 5178,
    5194             :     V_CMPSX_LT_F64_e32_si       = 5179,
    5195             :     V_CMPSX_LT_F64_e64  = 5180,
    5196             :     V_CMPSX_LT_F64_e64_si       = 5181,
    5197             :     V_CMPSX_LT_F64_sdwa = 5182,
    5198             :     V_CMPSX_NEQ_F32_e32 = 5183,
    5199             :     V_CMPSX_NEQ_F32_e32_si      = 5184,
    5200             :     V_CMPSX_NEQ_F32_e64 = 5185,
    5201             :     V_CMPSX_NEQ_F32_e64_si      = 5186,
    5202             :     V_CMPSX_NEQ_F32_sdwa        = 5187,
    5203             :     V_CMPSX_NEQ_F64_e32 = 5188,
    5204             :     V_CMPSX_NEQ_F64_e32_si      = 5189,
    5205             :     V_CMPSX_NEQ_F64_e64 = 5190,
    5206             :     V_CMPSX_NEQ_F64_e64_si      = 5191,
    5207             :     V_CMPSX_NEQ_F64_sdwa        = 5192,
    5208             :     V_CMPSX_NGE_F32_e32 = 5193,
    5209             :     V_CMPSX_NGE_F32_e32_si      = 5194,
    5210             :     V_CMPSX_NGE_F32_e64 = 5195,
    5211             :     V_CMPSX_NGE_F32_e64_si      = 5196,
    5212             :     V_CMPSX_NGE_F32_sdwa        = 5197,
    5213             :     V_CMPSX_NGE_F64_e32 = 5198,
    5214             :     V_CMPSX_NGE_F64_e32_si      = 5199,
    5215             :     V_CMPSX_NGE_F64_e64 = 5200,
    5216             :     V_CMPSX_NGE_F64_e64_si      = 5201,
    5217             :     V_CMPSX_NGE_F64_sdwa        = 5202,
    5218             :     V_CMPSX_NGT_F32_e32 = 5203,
    5219             :     V_CMPSX_NGT_F32_e32_si      = 5204,
    5220             :     V_CMPSX_NGT_F32_e64 = 5205,
    5221             :     V_CMPSX_NGT_F32_e64_si      = 5206,
    5222             :     V_CMPSX_NGT_F32_sdwa        = 5207,
    5223             :     V_CMPSX_NGT_F64_e32 = 5208,
    5224             :     V_CMPSX_NGT_F64_e32_si      = 5209,
    5225             :     V_CMPSX_NGT_F64_e64 = 5210,
    5226             :     V_CMPSX_NGT_F64_e64_si      = 5211,
    5227             :     V_CMPSX_NGT_F64_sdwa        = 5212,
    5228             :     V_CMPSX_NLE_F32_e32 = 5213,
    5229             :     V_CMPSX_NLE_F32_e32_si      = 5214,
    5230             :     V_CMPSX_NLE_F32_e64 = 5215,
    5231             :     V_CMPSX_NLE_F32_e64_si      = 5216,
    5232             :     V_CMPSX_NLE_F32_sdwa        = 5217,
    5233             :     V_CMPSX_NLE_F64_e32 = 5218,
    5234             :     V_CMPSX_NLE_F64_e32_si      = 5219,
    5235             :     V_CMPSX_NLE_F64_e64 = 5220,
    5236             :     V_CMPSX_NLE_F64_e64_si      = 5221,
    5237             :     V_CMPSX_NLE_F64_sdwa        = 5222,
    5238             :     V_CMPSX_NLG_F32_e32 = 5223,
    5239             :     V_CMPSX_NLG_F32_e32_si      = 5224,
    5240             :     V_CMPSX_NLG_F32_e64 = 5225,
    5241             :     V_CMPSX_NLG_F32_e64_si      = 5226,
    5242             :     V_CMPSX_NLG_F32_sdwa        = 5227,
    5243             :     V_CMPSX_NLG_F64_e32 = 5228,
    5244             :     V_CMPSX_NLG_F64_e32_si      = 5229,
    5245             :     V_CMPSX_NLG_F64_e64 = 5230,
    5246             :     V_CMPSX_NLG_F64_e64_si      = 5231,
    5247             :     V_CMPSX_NLG_F64_sdwa        = 5232,
    5248             :     V_CMPSX_NLT_F32_e32 = 5233,
    5249             :     V_CMPSX_NLT_F32_e32_si      = 5234,
    5250             :     V_CMPSX_NLT_F32_e64 = 5235,
    5251             :     V_CMPSX_NLT_F32_e64_si      = 5236,
    5252             :     V_CMPSX_NLT_F32_sdwa        = 5237,
    5253             :     V_CMPSX_NLT_F64_e32 = 5238,
    5254             :     V_CMPSX_NLT_F64_e32_si      = 5239,
    5255             :     V_CMPSX_NLT_F64_e64 = 5240,
    5256             :     V_CMPSX_NLT_F64_e64_si      = 5241,
    5257             :     V_CMPSX_NLT_F64_sdwa        = 5242,
    5258             :     V_CMPSX_O_F32_e32   = 5243,
    5259             :     V_CMPSX_O_F32_e32_si        = 5244,
    5260             :     V_CMPSX_O_F32_e64   = 5245,
    5261             :     V_CMPSX_O_F32_e64_si        = 5246,
    5262             :     V_CMPSX_O_F32_sdwa  = 5247,
    5263             :     V_CMPSX_O_F64_e32   = 5248,
    5264             :     V_CMPSX_O_F64_e32_si        = 5249,
    5265             :     V_CMPSX_O_F64_e64   = 5250,
    5266             :     V_CMPSX_O_F64_e64_si        = 5251,
    5267             :     V_CMPSX_O_F64_sdwa  = 5252,
    5268             :     V_CMPSX_TRU_F32_e32 = 5253,
    5269             :     V_CMPSX_TRU_F32_e32_si      = 5254,
    5270             :     V_CMPSX_TRU_F32_e64 = 5255,
    5271             :     V_CMPSX_TRU_F32_e64_si      = 5256,
    5272             :     V_CMPSX_TRU_F32_sdwa        = 5257,
    5273             :     V_CMPSX_TRU_F64_e32 = 5258,
    5274             :     V_CMPSX_TRU_F64_e32_si      = 5259,
    5275             :     V_CMPSX_TRU_F64_e64 = 5260,
    5276             :     V_CMPSX_TRU_F64_e64_si      = 5261,
    5277             :     V_CMPSX_TRU_F64_sdwa        = 5262,
    5278             :     V_CMPSX_U_F32_e32   = 5263,
    5279             :     V_CMPSX_U_F32_e32_si        = 5264,
    5280             :     V_CMPSX_U_F32_e64   = 5265,
    5281             :     V_CMPSX_U_F32_e64_si        = 5266,
    5282             :     V_CMPSX_U_F32_sdwa  = 5267,
    5283             :     V_CMPSX_U_F64_e32   = 5268,
    5284             :     V_CMPSX_U_F64_e32_si        = 5269,
    5285             :     V_CMPSX_U_F64_e64   = 5270,
    5286             :     V_CMPSX_U_F64_e64_si        = 5271,
    5287             :     V_CMPSX_U_F64_sdwa  = 5272,
    5288             :     V_CMPS_EQ_F32_e32   = 5273,
    5289             :     V_CMPS_EQ_F32_e32_si        = 5274,
    5290             :     V_CMPS_EQ_F32_e64   = 5275,
    5291             :     V_CMPS_EQ_F32_e64_si        = 5276,
    5292             :     V_CMPS_EQ_F32_sdwa  = 5277,
    5293             :     V_CMPS_EQ_F64_e32   = 5278,
    5294             :     V_CMPS_EQ_F64_e32_si        = 5279,
    5295             :     V_CMPS_EQ_F64_e64   = 5280,
    5296             :     V_CMPS_EQ_F64_e64_si        = 5281,
    5297             :     V_CMPS_EQ_F64_sdwa  = 5282,
    5298             :     V_CMPS_F_F32_e32    = 5283,
    5299             :     V_CMPS_F_F32_e32_si = 5284,
    5300             :     V_CMPS_F_F32_e64    = 5285,
    5301             :     V_CMPS_F_F32_e64_si = 5286,
    5302             :     V_CMPS_F_F32_sdwa   = 5287,
    5303             :     V_CMPS_F_F64_e32    = 5288,
    5304             :     V_CMPS_F_F64_e32_si = 5289,
    5305             :     V_CMPS_F_F64_e64    = 5290,
    5306             :     V_CMPS_F_F64_e64_si = 5291,
    5307             :     V_CMPS_F_F64_sdwa   = 5292,
    5308             :     V_CMPS_GE_F32_e32   = 5293,
    5309             :     V_CMPS_GE_F32_e32_si        = 5294,
    5310             :     V_CMPS_GE_F32_e64   = 5295,
    5311             :     V_CMPS_GE_F32_e64_si        = 5296,
    5312             :     V_CMPS_GE_F32_sdwa  = 5297,
    5313             :     V_CMPS_GE_F64_e32   = 5298,
    5314             :     V_CMPS_GE_F64_e32_si        = 5299,
    5315             :     V_CMPS_GE_F64_e64   = 5300,
    5316             :     V_CMPS_GE_F64_e64_si        = 5301,
    5317             :     V_CMPS_GE_F64_sdwa  = 5302,
    5318             :     V_CMPS_GT_F32_e32   = 5303,
    5319             :     V_CMPS_GT_F32_e32_si        = 5304,
    5320             :     V_CMPS_GT_F32_e64   = 5305,
    5321             :     V_CMPS_GT_F32_e64_si        = 5306,
    5322             :     V_CMPS_GT_F32_sdwa  = 5307,
    5323             :     V_CMPS_GT_F64_e32   = 5308,
    5324             :     V_CMPS_GT_F64_e32_si        = 5309,
    5325             :     V_CMPS_GT_F64_e64   = 5310,
    5326             :     V_CMPS_GT_F64_e64_si        = 5311,
    5327             :     V_CMPS_GT_F64_sdwa  = 5312,
    5328             :     V_CMPS_LE_F32_e32   = 5313,
    5329             :     V_CMPS_LE_F32_e32_si        = 5314,
    5330             :     V_CMPS_LE_F32_e64   = 5315,
    5331             :     V_CMPS_LE_F32_e64_si        = 5316,
    5332             :     V_CMPS_LE_F32_sdwa  = 5317,
    5333             :     V_CMPS_LE_F64_e32   = 5318,
    5334             :     V_CMPS_LE_F64_e32_si        = 5319,
    5335             :     V_CMPS_LE_F64_e64   = 5320,
    5336             :     V_CMPS_LE_F64_e64_si        = 5321,
    5337             :     V_CMPS_LE_F64_sdwa  = 5322,
    5338             :     V_CMPS_LG_F32_e32   = 5323,
    5339             :     V_CMPS_LG_F32_e32_si        = 5324,
    5340             :     V_CMPS_LG_F32_e64   = 5325,
    5341             :     V_CMPS_LG_F32_e64_si        = 5326,
    5342             :     V_CMPS_LG_F32_sdwa  = 5327,
    5343             :     V_CMPS_LG_F64_e32   = 5328,
    5344             :     V_CMPS_LG_F64_e32_si        = 5329,
    5345             :     V_CMPS_LG_F64_e64   = 5330,
    5346             :     V_CMPS_LG_F64_e64_si        = 5331,
    5347             :     V_CMPS_LG_F64_sdwa  = 5332,
    5348             :     V_CMPS_LT_F32_e32   = 5333,
    5349             :     V_CMPS_LT_F32_e32_si        = 5334,
    5350             :     V_CMPS_LT_F32_e64   = 5335,
    5351             :     V_CMPS_LT_F32_e64_si        = 5336,
    5352             :     V_CMPS_LT_F32_sdwa  = 5337,
    5353             :     V_CMPS_LT_F64_e32   = 5338,
    5354             :     V_CMPS_LT_F64_e32_si        = 5339,
    5355             :     V_CMPS_LT_F64_e64   = 5340,
    5356             :     V_CMPS_LT_F64_e64_si        = 5341,
    5357             :     V_CMPS_LT_F64_sdwa  = 5342,
    5358             :     V_CMPS_NEQ_F32_e32  = 5343,
    5359             :     V_CMPS_NEQ_F32_e32_si       = 5344,
    5360             :     V_CMPS_NEQ_F32_e64  = 5345,
    5361             :     V_CMPS_NEQ_F32_e64_si       = 5346,
    5362             :     V_CMPS_NEQ_F32_sdwa = 5347,
    5363             :     V_CMPS_NEQ_F64_e32  = 5348,
    5364             :     V_CMPS_NEQ_F64_e32_si       = 5349,
    5365             :     V_CMPS_NEQ_F64_e64  = 5350,
    5366             :     V_CMPS_NEQ_F64_e64_si       = 5351,
    5367             :     V_CMPS_NEQ_F64_sdwa = 5352,
    5368             :     V_CMPS_NGE_F32_e32  = 5353,
    5369             :     V_CMPS_NGE_F32_e32_si       = 5354,
    5370             :     V_CMPS_NGE_F32_e64  = 5355,
    5371             :     V_CMPS_NGE_F32_e64_si       = 5356,
    5372             :     V_CMPS_NGE_F32_sdwa = 5357,
    5373             :     V_CMPS_NGE_F64_e32  = 5358,
    5374             :     V_CMPS_NGE_F64_e32_si       = 5359,
    5375             :     V_CMPS_NGE_F64_e64  = 5360,
    5376             :     V_CMPS_NGE_F64_e64_si       = 5361,
    5377             :     V_CMPS_NGE_F64_sdwa = 5362,
    5378             :     V_CMPS_NGT_F32_e32  = 5363,
    5379             :     V_CMPS_NGT_F32_e32_si       = 5364,
    5380             :     V_CMPS_NGT_F32_e64  = 5365,
    5381             :     V_CMPS_NGT_F32_e64_si       = 5366,
    5382             :     V_CMPS_NGT_F32_sdwa = 5367,
    5383             :     V_CMPS_NGT_F64_e32  = 5368,
    5384             :     V_CMPS_NGT_F64_e32_si       = 5369,
    5385             :     V_CMPS_NGT_F64_e64  = 5370,
    5386             :     V_CMPS_NGT_F64_e64_si       = 5371,
    5387             :     V_CMPS_NGT_F64_sdwa = 5372,
    5388             :     V_CMPS_NLE_F32_e32  = 5373,
    5389             :     V_CMPS_NLE_F32_e32_si       = 5374,
    5390             :     V_CMPS_NLE_F32_e64  = 5375,
    5391             :     V_CMPS_NLE_F32_e64_si       = 5376,
    5392             :     V_CMPS_NLE_F32_sdwa = 5377,
    5393             :     V_CMPS_NLE_F64_e32  = 5378,
    5394             :     V_CMPS_NLE_F64_e32_si       = 5379,
    5395             :     V_CMPS_NLE_F64_e64  = 5380,
    5396             :     V_CMPS_NLE_F64_e64_si       = 5381,
    5397             :     V_CMPS_NLE_F64_sdwa = 5382,
    5398             :     V_CMPS_NLG_F32_e32  = 5383,
    5399             :     V_CMPS_NLG_F32_e32_si       = 5384,
    5400             :     V_CMPS_NLG_F32_e64  = 5385,
    5401             :     V_CMPS_NLG_F32_e64_si       = 5386,
    5402             :     V_CMPS_NLG_F32_sdwa = 5387,
    5403             :     V_CMPS_NLG_F64_e32  = 5388,
    5404             :     V_CMPS_NLG_F64_e32_si       = 5389,
    5405             :     V_CMPS_NLG_F64_e64  = 5390,
    5406             :     V_CMPS_NLG_F64_e64_si       = 5391,
    5407             :     V_CMPS_NLG_F64_sdwa = 5392,
    5408             :     V_CMPS_NLT_F32_e32  = 5393,
    5409             :     V_CMPS_NLT_F32_e32_si       = 5394,
    5410             :     V_CMPS_NLT_F32_e64  = 5395,
    5411             :     V_CMPS_NLT_F32_e64_si       = 5396,
    5412             :     V_CMPS_NLT_F32_sdwa = 5397,
    5413             :     V_CMPS_NLT_F64_e32  = 5398,
    5414             :     V_CMPS_NLT_F64_e32_si       = 5399,
    5415             :     V_CMPS_NLT_F64_e64  = 5400,
    5416             :     V_CMPS_NLT_F64_e64_si       = 5401,
    5417             :     V_CMPS_NLT_F64_sdwa = 5402,
    5418             :     V_CMPS_O_F32_e32    = 5403,
    5419             :     V_CMPS_O_F32_e32_si = 5404,
    5420             :     V_CMPS_O_F32_e64    = 5405,
    5421             :     V_CMPS_O_F32_e64_si = 5406,
    5422             :     V_CMPS_O_F32_sdwa   = 5407,
    5423             :     V_CMPS_O_F64_e32    = 5408,
    5424             :     V_CMPS_O_F64_e32_si = 5409,
    5425             :     V_CMPS_O_F64_e64    = 5410,
    5426             :     V_CMPS_O_F64_e64_si = 5411,
    5427             :     V_CMPS_O_F64_sdwa   = 5412,
    5428             :     V_CMPS_TRU_F32_e32  = 5413,
    5429             :     V_CMPS_TRU_F32_e32_si       = 5414,
    5430             :     V_CMPS_TRU_F32_e64  = 5415,
    5431             :     V_CMPS_TRU_F32_e64_si       = 5416,
    5432             :     V_CMPS_TRU_F32_sdwa = 5417,
    5433             :     V_CMPS_TRU_F64_e32  = 5418,
    5434             :     V_CMPS_TRU_F64_e32_si       = 5419,
    5435             :     V_CMPS_TRU_F64_e64  = 5420,
    5436             :     V_CMPS_TRU_F64_e64_si       = 5421,
    5437             :     V_CMPS_TRU_F64_sdwa = 5422,
    5438             :     V_CMPS_U_F32_e32    = 5423,
    5439             :     V_CMPS_U_F32_e32_si = 5424,
    5440             :     V_CMPS_U_F32_e64    = 5425,
    5441             :     V_CMPS_U_F32_e64_si = 5426,
    5442             :     V_CMPS_U_F32_sdwa   = 5427,
    5443             :     V_CMPS_U_F64_e32    = 5428,
    5444             :     V_CMPS_U_F64_e32_si = 5429,
    5445             :     V_CMPS_U_F64_e64    = 5430,
    5446             :     V_CMPS_U_F64_e64_si = 5431,
    5447             :     V_CMPS_U_F64_sdwa   = 5432,
    5448             :     V_CMPX_CLASS_F16_e32        = 5433,
    5449             :     V_CMPX_CLASS_F16_e32_vi     = 5434,
    5450             :     V_CMPX_CLASS_F16_e64        = 5435,
    5451             :     V_CMPX_CLASS_F16_e64_vi     = 5436,
    5452             :     V_CMPX_CLASS_F16_sdwa       = 5437,
    5453             :     V_CMPX_CLASS_F16_sdwa_gfx9  = 5438,
    5454             :     V_CMPX_CLASS_F16_sdwa_vi    = 5439,
    5455             :     V_CMPX_CLASS_F32_e32        = 5440,
    5456             :     V_CMPX_CLASS_F32_e32_si     = 5441,
    5457             :     V_CMPX_CLASS_F32_e32_vi     = 5442,
    5458             :     V_CMPX_CLASS_F32_e64        = 5443,
    5459             :     V_CMPX_CLASS_F32_e64_si     = 5444,
    5460             :     V_CMPX_CLASS_F32_e64_vi     = 5445,
    5461             :     V_CMPX_CLASS_F32_sdwa       = 5446,
    5462             :     V_CMPX_CLASS_F32_sdwa_gfx9  = 5447,
    5463             :     V_CMPX_CLASS_F32_sdwa_vi    = 5448,
    5464             :     V_CMPX_CLASS_F64_e32        = 5449,
    5465             :     V_CMPX_CLASS_F64_e32_si     = 5450,
    5466             :     V_CMPX_CLASS_F64_e32_vi     = 5451,
    5467             :     V_CMPX_CLASS_F64_e64        = 5452,
    5468             :     V_CMPX_CLASS_F64_e64_si     = 5453,
    5469             :     V_CMPX_CLASS_F64_e64_vi     = 5454,
    5470             :     V_CMPX_CLASS_F64_sdwa       = 5455,
    5471             :     V_CMPX_CLASS_F64_sdwa_gfx9  = 5456,
    5472             :     V_CMPX_CLASS_F64_sdwa_vi    = 5457,
    5473             :     V_CMPX_EQ_F16_e32   = 5458,
    5474             :     V_CMPX_EQ_F16_e32_vi        = 5459,
    5475             :     V_CMPX_EQ_F16_e64   = 5460,
    5476             :     V_CMPX_EQ_F16_e64_vi        = 5461,
    5477             :     V_CMPX_EQ_F16_sdwa  = 5462,
    5478             :     V_CMPX_EQ_F16_sdwa_gfx9     = 5463,
    5479             :     V_CMPX_EQ_F16_sdwa_vi       = 5464,
    5480             :     V_CMPX_EQ_F32_e32   = 5465,
    5481             :     V_CMPX_EQ_F32_e32_si        = 5466,
    5482             :     V_CMPX_EQ_F32_e32_vi        = 5467,
    5483             :     V_CMPX_EQ_F32_e64   = 5468,
    5484             :     V_CMPX_EQ_F32_e64_si        = 5469,
    5485             :     V_CMPX_EQ_F32_e64_vi        = 5470,
    5486             :     V_CMPX_EQ_F32_sdwa  = 5471,
    5487             :     V_CMPX_EQ_F32_sdwa_gfx9     = 5472,
    5488             :     V_CMPX_EQ_F32_sdwa_vi       = 5473,
    5489             :     V_CMPX_EQ_F64_e32   = 5474,
    5490             :     V_CMPX_EQ_F64_e32_si        = 5475,
    5491             :     V_CMPX_EQ_F64_e32_vi        = 5476,
    5492             :     V_CMPX_EQ_F64_e64   = 5477,
    5493             :     V_CMPX_EQ_F64_e64_si        = 5478,
    5494             :     V_CMPX_EQ_F64_e64_vi        = 5479,
    5495             :     V_CMPX_EQ_F64_sdwa  = 5480,
    5496             :     V_CMPX_EQ_F64_sdwa_gfx9     = 5481,
    5497             :     V_CMPX_EQ_F64_sdwa_vi       = 5482,
    5498             :     V_CMPX_EQ_I16_e32   = 5483,
    5499             :     V_CMPX_EQ_I16_e32_vi        = 5484,
    5500             :     V_CMPX_EQ_I16_e64   = 5485,
    5501             :     V_CMPX_EQ_I16_e64_vi        = 5486,
    5502             :     V_CMPX_EQ_I16_sdwa  = 5487,
    5503             :     V_CMPX_EQ_I16_sdwa_gfx9     = 5488,
    5504             :     V_CMPX_EQ_I16_sdwa_vi       = 5489,
    5505             :     V_CMPX_EQ_I32_e32   = 5490,
    5506             :     V_CMPX_EQ_I32_e32_si        = 5491,
    5507             :     V_CMPX_EQ_I32_e32_vi        = 5492,
    5508             :     V_CMPX_EQ_I32_e64   = 5493,
    5509             :     V_CMPX_EQ_I32_e64_si        = 5494,
    5510             :     V_CMPX_EQ_I32_e64_vi        = 5495,
    5511             :     V_CMPX_EQ_I32_sdwa  = 5496,
    5512             :     V_CMPX_EQ_I32_sdwa_gfx9     = 5497,
    5513             :     V_CMPX_EQ_I32_sdwa_vi       = 5498,
    5514             :     V_CMPX_EQ_I64_e32   = 5499,
    5515             :     V_CMPX_EQ_I64_e32_si        = 5500,
    5516             :     V_CMPX_EQ_I64_e32_vi        = 5501,
    5517             :     V_CMPX_EQ_I64_e64   = 5502,
    5518             :     V_CMPX_EQ_I64_e64_si        = 5503,
    5519             :     V_CMPX_EQ_I64_e64_vi        = 5504,
    5520             :     V_CMPX_EQ_I64_sdwa  = 5505,
    5521             :     V_CMPX_EQ_I64_sdwa_gfx9     = 5506,
    5522             :     V_CMPX_EQ_I64_sdwa_vi       = 5507,
    5523             :     V_CMPX_EQ_U16_e32   = 5508,
    5524             :     V_CMPX_EQ_U16_e32_vi        = 5509,
    5525             :     V_CMPX_EQ_U16_e64   = 5510,
    5526             :     V_CMPX_EQ_U16_e64_vi        = 5511,
    5527             :     V_CMPX_EQ_U16_sdwa  = 5512,
    5528             :     V_CMPX_EQ_U16_sdwa_gfx9     = 5513,
    5529             :     V_CMPX_EQ_U16_sdwa_vi       = 5514,
    5530             :     V_CMPX_EQ_U32_e32   = 5515,
    5531             :     V_CMPX_EQ_U32_e32_si        = 5516,
    5532             :     V_CMPX_EQ_U32_e32_vi        = 5517,
    5533             :     V_CMPX_EQ_U32_e64   = 5518,
    5534             :     V_CMPX_EQ_U32_e64_si        = 5519,
    5535             :     V_CMPX_EQ_U32_e64_vi        = 5520,
    5536             :     V_CMPX_EQ_U32_sdwa  = 5521,
    5537             :     V_CMPX_EQ_U32_sdwa_gfx9     = 5522,
    5538             :     V_CMPX_EQ_U32_sdwa_vi       = 5523,
    5539             :     V_CMPX_EQ_U64_e32   = 5524,
    5540             :     V_CMPX_EQ_U64_e32_si        = 5525,
    5541             :     V_CMPX_EQ_U64_e32_vi        = 5526,
    5542             :     V_CMPX_EQ_U64_e64   = 5527,
    5543             :     V_CMPX_EQ_U64_e64_si        = 5528,
    5544             :     V_CMPX_EQ_U64_e64_vi        = 5529,
    5545             :     V_CMPX_EQ_U64_sdwa  = 5530,
    5546             :     V_CMPX_EQ_U64_sdwa_gfx9     = 5531,
    5547             :     V_CMPX_EQ_U64_sdwa_vi       = 5532,
    5548             :     V_CMPX_F_F16_e32    = 5533,
    5549             :     V_CMPX_F_F16_e32_vi = 5534,
    5550             :     V_CMPX_F_F16_e64    = 5535,
    5551             :     V_CMPX_F_F16_e64_vi = 5536,
    5552             :     V_CMPX_F_F16_sdwa   = 5537,
    5553             :     V_CMPX_F_F16_sdwa_gfx9      = 5538,
    5554             :     V_CMPX_F_F16_sdwa_vi        = 5539,
    5555             :     V_CMPX_F_F32_e32    = 5540,
    5556             :     V_CMPX_F_F32_e32_si = 5541,
    5557             :     V_CMPX_F_F32_e32_vi = 5542,
    5558             :     V_CMPX_F_F32_e64    = 5543,
    5559             :     V_CMPX_F_F32_e64_si = 5544,
    5560             :     V_CMPX_F_F32_e64_vi = 5545,
    5561             :     V_CMPX_F_F32_sdwa   = 5546,
    5562             :     V_CMPX_F_F32_sdwa_gfx9      = 5547,
    5563             :     V_CMPX_F_F32_sdwa_vi        = 5548,
    5564             :     V_CMPX_F_F64_e32    = 5549,
    5565             :     V_CMPX_F_F64_e32_si = 5550,
    5566             :     V_CMPX_F_F64_e32_vi = 5551,
    5567             :     V_CMPX_F_F64_e64    = 5552,
    5568             :     V_CMPX_F_F64_e64_si = 5553,
    5569             :     V_CMPX_F_F64_e64_vi = 5554,
    5570             :     V_CMPX_F_F64_sdwa   = 5555,
    5571             :     V_CMPX_F_F64_sdwa_gfx9      = 5556,
    5572             :     V_CMPX_F_F64_sdwa_vi        = 5557,
    5573             :     V_CMPX_F_I16_e32    = 5558,
    5574             :     V_CMPX_F_I16_e32_vi = 5559,
    5575             :     V_CMPX_F_I16_e64    = 5560,
    5576             :     V_CMPX_F_I16_e64_vi = 5561,
    5577             :     V_CMPX_F_I16_sdwa   = 5562,
    5578             :     V_CMPX_F_I16_sdwa_gfx9      = 5563,
    5579             :     V_CMPX_F_I16_sdwa_vi        = 5564,
    5580             :     V_CMPX_F_I32_e32    = 5565,
    5581             :     V_CMPX_F_I32_e32_si = 5566,
    5582             :     V_CMPX_F_I32_e32_vi = 5567,
    5583             :     V_CMPX_F_I32_e64    = 5568,
    5584             :     V_CMPX_F_I32_e64_si = 5569,
    5585             :     V_CMPX_F_I32_e64_vi = 5570,
    5586             :     V_CMPX_F_I32_sdwa   = 5571,
    5587             :     V_CMPX_F_I32_sdwa_gfx9      = 5572,
    5588             :     V_CMPX_F_I32_sdwa_vi        = 5573,
    5589             :     V_CMPX_F_I64_e32    = 5574,
    5590             :     V_CMPX_F_I64_e32_si = 5575,
    5591             :     V_CMPX_F_I64_e32_vi = 5576,
    5592             :     V_CMPX_F_I64_e64    = 5577,
    5593             :     V_CMPX_F_I64_e64_si = 5578,
    5594             :     V_CMPX_F_I64_e64_vi = 5579,
    5595             :     V_CMPX_F_I64_sdwa   = 5580,
    5596             :     V_CMPX_F_I64_sdwa_gfx9      = 5581,
    5597             :     V_CMPX_F_I64_sdwa_vi        = 5582,
    5598             :     V_CMPX_F_U16_e32    = 5583,
    5599             :     V_CMPX_F_U16_e32_vi = 5584,
    5600             :     V_CMPX_F_U16_e64    = 5585,
    5601             :     V_CMPX_F_U16_e64_vi = 5586,
    5602             :     V_CMPX_F_U16_sdwa   = 5587,
    5603             :     V_CMPX_F_U16_sdwa_gfx9      = 5588,
    5604             :     V_CMPX_F_U16_sdwa_vi        = 5589,
    5605             :     V_CMPX_F_U32_e32    = 5590,
    5606             :     V_CMPX_F_U32_e32_si = 5591,
    5607             :     V_CMPX_F_U32_e32_vi = 5592,
    5608             :     V_CMPX_F_U32_e64    = 5593,
    5609             :     V_CMPX_F_U32_e64_si = 5594,
    5610             :     V_CMPX_F_U32_e64_vi = 5595,
    5611             :     V_CMPX_F_U32_sdwa   = 5596,
    5612             :     V_CMPX_F_U32_sdwa_gfx9      = 5597,
    5613             :     V_CMPX_F_U32_sdwa_vi        = 5598,
    5614             :     V_CMPX_F_U64_e32    = 5599,
    5615             :     V_CMPX_F_U64_e32_si = 5600,
    5616             :     V_CMPX_F_U64_e32_vi = 5601,
    5617             :     V_CMPX_F_U64_e64    = 5602,
    5618             :     V_CMPX_F_U64_e64_si = 5603,
    5619             :     V_CMPX_F_U64_e64_vi = 5604,
    5620             :     V_CMPX_F_U64_sdwa   = 5605,
    5621             :     V_CMPX_F_U64_sdwa_gfx9      = 5606,
    5622             :     V_CMPX_F_U64_sdwa_vi        = 5607,
    5623             :     V_CMPX_GE_F16_e32   = 5608,
    5624             :     V_CMPX_GE_F16_e32_vi        = 5609,
    5625             :     V_CMPX_GE_F16_e64   = 5610,
    5626             :     V_CMPX_GE_F16_e64_vi        = 5611,
    5627             :     V_CMPX_GE_F16_sdwa  = 5612,
    5628             :     V_CMPX_GE_F16_sdwa_gfx9     = 5613,
    5629             :     V_CMPX_GE_F16_sdwa_vi       = 5614,
    5630             :     V_CMPX_GE_F32_e32   = 5615,
    5631             :     V_CMPX_GE_F32_e32_si        = 5616,
    5632             :     V_CMPX_GE_F32_e32_vi        = 5617,
    5633             :     V_CMPX_GE_F32_e64   = 5618,
    5634             :     V_CMPX_GE_F32_e64_si        = 5619,
    5635             :     V_CMPX_GE_F32_e64_vi        = 5620,
    5636             :     V_CMPX_GE_F32_sdwa  = 5621,
    5637             :     V_CMPX_GE_F32_sdwa_gfx9     = 5622,
    5638             :     V_CMPX_GE_F32_sdwa_vi       = 5623,
    5639             :     V_CMPX_GE_F64_e32   = 5624,
    5640             :     V_CMPX_GE_F64_e32_si        = 5625,
    5641             :     V_CMPX_GE_F64_e32_vi        = 5626,
    5642             :     V_CMPX_GE_F64_e64   = 5627,
    5643             :     V_CMPX_GE_F64_e64_si        = 5628,
    5644             :     V_CMPX_GE_F64_e64_vi        = 5629,
    5645             :     V_CMPX_GE_F64_sdwa  = 5630,
    5646             :     V_CMPX_GE_F64_sdwa_gfx9     = 5631,
    5647             :     V_CMPX_GE_F64_sdwa_vi       = 5632,
    5648             :     V_CMPX_GE_I16_e32   = 5633,
    5649             :     V_CMPX_GE_I16_e32_vi        = 5634,
    5650             :     V_CMPX_GE_I16_e64   = 5635,
    5651             :     V_CMPX_GE_I16_e64_vi        = 5636,
    5652             :     V_CMPX_GE_I16_sdwa  = 5637,
    5653             :     V_CMPX_GE_I16_sdwa_gfx9     = 5638,
    5654             :     V_CMPX_GE_I16_sdwa_vi       = 5639,
    5655             :     V_CMPX_GE_I32_e32   = 5640,
    5656             :     V_CMPX_GE_I32_e32_si        = 5641,
    5657             :     V_CMPX_GE_I32_e32_vi        = 5642,
    5658             :     V_CMPX_GE_I32_e64   = 5643,
    5659             :     V_CMPX_GE_I32_e64_si        = 5644,
    5660             :     V_CMPX_GE_I32_e64_vi        = 5645,
    5661             :     V_CMPX_GE_I32_sdwa  = 5646,
    5662             :     V_CMPX_GE_I32_sdwa_gfx9     = 5647,
    5663             :     V_CMPX_GE_I32_sdwa_vi       = 5648,
    5664             :     V_CMPX_GE_I64_e32   = 5649,
    5665             :     V_CMPX_GE_I64_e32_si        = 5650,
    5666             :     V_CMPX_GE_I64_e32_vi        = 5651,
    5667             :     V_CMPX_GE_I64_e64   = 5652,
    5668             :     V_CMPX_GE_I64_e64_si        = 5653,
    5669             :     V_CMPX_GE_I64_e64_vi        = 5654,
    5670             :     V_CMPX_GE_I64_sdwa  = 5655,
    5671             :     V_CMPX_GE_I64_sdwa_gfx9     = 5656,
    5672             :     V_CMPX_GE_I64_sdwa_vi       = 5657,
    5673             :     V_CMPX_GE_U16_e32   = 5658,
    5674             :     V_CMPX_GE_U16_e32_vi        = 5659,
    5675             :     V_CMPX_GE_U16_e64   = 5660,
    5676             :     V_CMPX_GE_U16_e64_vi        = 5661,
    5677             :     V_CMPX_GE_U16_sdwa  = 5662,
    5678             :     V_CMPX_GE_U16_sdwa_gfx9     = 5663,
    5679             :     V_CMPX_GE_U16_sdwa_vi       = 5664,
    5680             :     V_CMPX_GE_U32_e32   = 5665,
    5681             :     V_CMPX_GE_U32_e32_si        = 5666,
    5682             :     V_CMPX_GE_U32_e32_vi        = 5667,
    5683             :     V_CMPX_GE_U32_e64   = 5668,
    5684             :     V_CMPX_GE_U32_e64_si        = 5669,
    5685             :     V_CMPX_GE_U32_e64_vi        = 5670,
    5686             :     V_CMPX_GE_U32_sdwa  = 5671,
    5687             :     V_CMPX_GE_U32_sdwa_gfx9     = 5672,
    5688             :     V_CMPX_GE_U32_sdwa_vi       = 5673,
    5689             :     V_CMPX_GE_U64_e32   = 5674,
    5690             :     V_CMPX_GE_U64_e32_si        = 5675,
    5691             :     V_CMPX_GE_U64_e32_vi        = 5676,
    5692             :     V_CMPX_GE_U64_e64   = 5677,
    5693             :     V_CMPX_GE_U64_e64_si        = 5678,
    5694             :     V_CMPX_GE_U64_e64_vi        = 5679,
    5695             :     V_CMPX_GE_U64_sdwa  = 5680,
    5696             :     V_CMPX_GE_U64_sdwa_gfx9     = 5681,
    5697             :     V_CMPX_GE_U64_sdwa_vi       = 5682,
    5698             :     V_CMPX_GT_F16_e32   = 5683,
    5699             :     V_CMPX_GT_F16_e32_vi        = 5684,
    5700             :     V_CMPX_GT_F16_e64   = 5685,
    5701             :     V_CMPX_GT_F16_e64_vi        = 5686,
    5702             :     V_CMPX_GT_F16_sdwa  = 5687,
    5703             :     V_CMPX_GT_F16_sdwa_gfx9     = 5688,
    5704             :     V_CMPX_GT_F16_sdwa_vi       = 5689,
    5705             :     V_CMPX_GT_F32_e32   = 5690,
    5706             :     V_CMPX_GT_F32_e32_si        = 5691,
    5707             :     V_CMPX_GT_F32_e32_vi        = 5692,
    5708             :     V_CMPX_GT_F32_e64   = 5693,
    5709             :     V_CMPX_GT_F32_e64_si        = 5694,
    5710             :     V_CMPX_GT_F32_e64_vi        = 5695,
    5711             :     V_CMPX_GT_F32_sdwa  = 5696,
    5712             :     V_CMPX_GT_F32_sdwa_gfx9     = 5697,
    5713             :     V_CMPX_GT_F32_sdwa_vi       = 5698,
    5714             :     V_CMPX_GT_F64_e32   = 5699,
    5715             :     V_CMPX_GT_F64_e32_si        = 5700,
    5716             :     V_CMPX_GT_F64_e32_vi        = 5701,
    5717             :     V_CMPX_GT_F64_e64   = 5702,
    5718             :     V_CMPX_GT_F64_e64_si        = 5703,
    5719             :     V_CMPX_GT_F64_e64_vi        = 5704,
    5720             :     V_CMPX_GT_F64_sdwa  = 5705,
    5721             :     V_CMPX_GT_F64_sdwa_gfx9     = 5706,
    5722             :     V_CMPX_GT_F64_sdwa_vi       = 5707,
    5723             :     V_CMPX_GT_I16_e32   = 5708,
    5724             :     V_CMPX_GT_I16_e32_vi        = 5709,
    5725             :     V_CMPX_GT_I16_e64   = 5710,
    5726             :     V_CMPX_GT_I16_e64_vi        = 5711,
    5727             :     V_CMPX_GT_I16_sdwa  = 5712,
    5728             :     V_CMPX_GT_I16_sdwa_gfx9     = 5713,
    5729             :     V_CMPX_GT_I16_sdwa_vi       = 5714,
    5730             :     V_CMPX_GT_I32_e32   = 5715,
    5731             :     V_CMPX_GT_I32_e32_si        = 5716,
    5732             :     V_CMPX_GT_I32_e32_vi        = 5717,
    5733             :     V_CMPX_GT_I32_e64   = 5718,
    5734             :     V_CMPX_GT_I32_e64_si        = 5719,
    5735             :     V_CMPX_GT_I32_e64_vi        = 5720,
    5736             :     V_CMPX_GT_I32_sdwa  = 5721,
    5737             :     V_CMPX_GT_I32_sdwa_gfx9     = 5722,
    5738             :     V_CMPX_GT_I32_sdwa_vi       = 5723,
    5739             :     V_CMPX_GT_I64_e32   = 5724,
    5740             :     V_CMPX_GT_I64_e32_si        = 5725,
    5741             :     V_CMPX_GT_I64_e32_vi        = 5726,
    5742             :     V_CMPX_GT_I64_e64   = 5727,
    5743             :     V_CMPX_GT_I64_e64_si        = 5728,
    5744             :     V_CMPX_GT_I64_e64_vi        = 5729,
    5745             :     V_CMPX_GT_I64_sdwa  = 5730,
    5746             :     V_CMPX_GT_I64_sdwa_gfx9     = 5731,
    5747             :     V_CMPX_GT_I64_sdwa_vi       = 5732,
    5748             :     V_CMPX_GT_U16_e32   = 5733,
    5749             :     V_CMPX_GT_U16_e32_vi        = 5734,
    5750             :     V_CMPX_GT_U16_e64   = 5735,
    5751             :     V_CMPX_GT_U16_e64_vi        = 5736,
    5752             :     V_CMPX_GT_U16_sdwa  = 5737,
    5753             :     V_CMPX_GT_U16_sdwa_gfx9     = 5738,
    5754             :     V_CMPX_GT_U16_sdwa_vi       = 5739,
    5755             :     V_CMPX_GT_U32_e32   = 5740,
    5756             :     V_CMPX_GT_U32_e32_si        = 5741,
    5757             :     V_CMPX_GT_U32_e32_vi        = 5742,
    5758             :     V_CMPX_GT_U32_e64   = 5743,
    5759             :     V_CMPX_GT_U32_e64_si        = 5744,
    5760             :     V_CMPX_GT_U32_e64_vi        = 5745,
    5761             :     V_CMPX_GT_U32_sdwa  = 5746,
    5762             :     V_CMPX_GT_U32_sdwa_gfx9     = 5747,
    5763             :     V_CMPX_GT_U32_sdwa_vi       = 5748,
    5764             :     V_CMPX_GT_U64_e32   = 5749,
    5765             :     V_CMPX_GT_U64_e32_si        = 5750,
    5766             :     V_CMPX_GT_U64_e32_vi        = 5751,
    5767             :     V_CMPX_GT_U64_e64   = 5752,
    5768             :     V_CMPX_GT_U64_e64_si        = 5753,
    5769             :     V_CMPX_GT_U64_e64_vi        = 5754,
    5770             :     V_CMPX_GT_U64_sdwa  = 5755,
    5771             :     V_CMPX_GT_U64_sdwa_gfx9     = 5756,
    5772             :     V_CMPX_GT_U64_sdwa_vi       = 5757,
    5773             :     V_CMPX_LE_F16_e32   = 5758,
    5774             :     V_CMPX_LE_F16_e32_vi        = 5759,
    5775             :     V_CMPX_LE_F16_e64   = 5760,
    5776             :     V_CMPX_LE_F16_e64_vi        = 5761,
    5777             :     V_CMPX_LE_F16_sdwa  = 5762,
    5778             :     V_CMPX_LE_F16_sdwa_gfx9     = 5763,
    5779             :     V_CMPX_LE_F16_sdwa_vi       = 5764,
    5780             :     V_CMPX_LE_F32_e32   = 5765,
    5781             :     V_CMPX_LE_F32_e32_si        = 5766,
    5782             :     V_CMPX_LE_F32_e32_vi        = 5767,
    5783             :     V_CMPX_LE_F32_e64   = 5768,
    5784             :     V_CMPX_LE_F32_e64_si        = 5769,
    5785             :     V_CMPX_LE_F32_e64_vi        = 5770,
    5786             :     V_CMPX_LE_F32_sdwa  = 5771,
    5787             :     V_CMPX_LE_F32_sdwa_gfx9     = 5772,
    5788             :     V_CMPX_LE_F32_sdwa_vi       = 5773,
    5789             :     V_CMPX_LE_F64_e32   = 5774,
    5790             :     V_CMPX_LE_F64_e32_si        = 5775,
    5791             :     V_CMPX_LE_F64_e32_vi        = 5776,
    5792             :     V_CMPX_LE_F64_e64   = 5777,
    5793             :     V_CMPX_LE_F64_e64_si        = 5778,
    5794             :     V_CMPX_LE_F64_e64_vi        = 5779,
    5795             :     V_CMPX_LE_F64_sdwa  = 5780,
    5796             :     V_CMPX_LE_F64_sdwa_gfx9     = 5781,
    5797             :     V_CMPX_LE_F64_sdwa_vi       = 5782,
    5798             :     V_CMPX_LE_I16_e32   = 5783,
    5799             :     V_CMPX_LE_I16_e32_vi        = 5784,
    5800             :     V_CMPX_LE_I16_e64   = 5785,
    5801             :     V_CMPX_LE_I16_e64_vi        = 5786,
    5802             :     V_CMPX_LE_I16_sdwa  = 5787,
    5803             :     V_CMPX_LE_I16_sdwa_gfx9     = 5788,
    5804             :     V_CMPX_LE_I16_sdwa_vi       = 5789,
    5805             :     V_CMPX_LE_I32_e32   = 5790,
    5806             :     V_CMPX_LE_I32_e32_si        = 5791,
    5807             :     V_CMPX_LE_I32_e32_vi        = 5792,
    5808             :     V_CMPX_LE_I32_e64   = 5793,
    5809             :     V_CMPX_LE_I32_e64_si        = 5794,
    5810             :     V_CMPX_LE_I32_e64_vi        = 5795,
    5811             :     V_CMPX_LE_I32_sdwa  = 5796,
    5812             :     V_CMPX_LE_I32_sdwa_gfx9     = 5797,
    5813             :     V_CMPX_LE_I32_sdwa_vi       = 5798,
    5814             :     V_CMPX_LE_I64_e32   = 5799,
    5815             :     V_CMPX_LE_I64_e32_si        = 5800,
    5816             :     V_CMPX_LE_I64_e32_vi        = 5801,
    5817             :     V_CMPX_LE_I64_e64   = 5802,
    5818             :     V_CMPX_LE_I64_e64_si        = 5803,
    5819             :     V_CMPX_LE_I64_e64_vi        = 5804,
    5820             :     V_CMPX_LE_I64_sdwa  = 5805,
    5821             :     V_CMPX_LE_I64_sdwa_gfx9     = 5806,
    5822             :     V_CMPX_LE_I64_sdwa_vi       = 5807,
    5823             :     V_CMPX_LE_U16_e32   = 5808,
    5824             :     V_CMPX_LE_U16_e32_vi        = 5809,
    5825             :     V_CMPX_LE_U16_e64   = 5810,
    5826             :     V_CMPX_LE_U16_e64_vi        = 5811,
    5827             :     V_CMPX_LE_U16_sdwa  = 5812,
    5828             :     V_CMPX_LE_U16_sdwa_gfx9     = 5813,
    5829             :     V_CMPX_LE_U16_sdwa_vi       = 5814,
    5830             :     V_CMPX_LE_U32_e32   = 5815,
    5831             :     V_CMPX_LE_U32_e32_si        = 5816,
    5832             :     V_CMPX_LE_U32_e32_vi        = 5817,
    5833             :     V_CMPX_LE_U32_e64   = 5818,
    5834             :     V_CMPX_LE_U32_e64_si        = 5819,
    5835             :     V_CMPX_LE_U32_e64_vi        = 5820,
    5836             :     V_CMPX_LE_U32_sdwa  = 5821,
    5837             :     V_CMPX_LE_U32_sdwa_gfx9     = 5822,
    5838             :     V_CMPX_LE_U32_sdwa_vi       = 5823,
    5839             :     V_CMPX_LE_U64_e32   = 5824,
    5840             :     V_CMPX_LE_U64_e32_si        = 5825,
    5841             :     V_CMPX_LE_U64_e32_vi        = 5826,
    5842             :     V_CMPX_LE_U64_e64   = 5827,
    5843             :     V_CMPX_LE_U64_e64_si        = 5828,
    5844             :     V_CMPX_LE_U64_e64_vi        = 5829,
    5845             :     V_CMPX_LE_U64_sdwa  = 5830,
    5846             :     V_CMPX_LE_U64_sdwa_gfx9     = 5831,
    5847             :     V_CMPX_LE_U64_sdwa_vi       = 5832,
    5848             :     V_CMPX_LG_F16_e32   = 5833,
    5849             :     V_CMPX_LG_F16_e32_vi        = 5834,
    5850             :     V_CMPX_LG_F16_e64   = 5835,
    5851             :     V_CMPX_LG_F16_e64_vi        = 5836,
    5852             :     V_CMPX_LG_F16_sdwa  = 5837,
    5853             :     V_CMPX_LG_F16_sdwa_gfx9     = 5838,
    5854             :     V_CMPX_LG_F16_sdwa_vi       = 5839,
    5855             :     V_CMPX_LG_F32_e32   = 5840,
    5856             :     V_CMPX_LG_F32_e32_si        = 5841,
    5857             :     V_CMPX_LG_F32_e32_vi        = 5842,
    5858             :     V_CMPX_LG_F32_e64   = 5843,
    5859             :     V_CMPX_LG_F32_e64_si        = 5844,
    5860             :     V_CMPX_LG_F32_e64_vi        = 5845,
    5861             :     V_CMPX_LG_F32_sdwa  = 5846,
    5862             :     V_CMPX_LG_F32_sdwa_gfx9     = 5847,
    5863             :     V_CMPX_LG_F32_sdwa_vi       = 5848,
    5864             :     V_CMPX_LG_F64_e32   = 5849,
    5865             :     V_CMPX_LG_F64_e32_si        = 5850,
    5866             :     V_CMPX_LG_F64_e32_vi        = 5851,
    5867             :     V_CMPX_LG_F64_e64   = 5852,
    5868             :     V_CMPX_LG_F64_e64_si        = 5853,
    5869             :     V_CMPX_LG_F64_e64_vi        = 5854,
    5870             :     V_CMPX_LG_F64_sdwa  = 5855,
    5871             :     V_CMPX_LG_F64_sdwa_gfx9     = 5856,
    5872             :     V_CMPX_LG_F64_sdwa_vi       = 5857,
    5873             :     V_CMPX_LT_F16_e32   = 5858,
    5874             :     V_CMPX_LT_F16_e32_vi        = 5859,
    5875             :     V_CMPX_LT_F16_e64   = 5860,
    5876             :     V_CMPX_LT_F16_e64_vi        = 5861,
    5877             :     V_CMPX_LT_F16_sdwa  = 5862,
    5878             :     V_CMPX_LT_F16_sdwa_gfx9     = 5863,
    5879             :     V_CMPX_LT_F16_sdwa_vi       = 5864,
    5880             :     V_CMPX_LT_F32_e32   = 5865,
    5881             :     V_CMPX_LT_F32_e32_si        = 5866,
    5882             :     V_CMPX_LT_F32_e32_vi        = 5867,
    5883             :     V_CMPX_LT_F32_e64   = 5868,
    5884             :     V_CMPX_LT_F32_e64_si        = 5869,
    5885             :     V_CMPX_LT_F32_e64_vi        = 5870,
    5886             :     V_CMPX_LT_F32_sdwa  = 5871,
    5887             :     V_CMPX_LT_F32_sdwa_gfx9     = 5872,
    5888             :     V_CMPX_LT_F32_sdwa_vi       = 5873,
    5889             :     V_CMPX_LT_F64_e32   = 5874,
    5890             :     V_CMPX_LT_F64_e32_si        = 5875,
    5891             :     V_CMPX_LT_F64_e32_vi        = 5876,
    5892             :     V_CMPX_LT_F64_e64   = 5877,
    5893             :     V_CMPX_LT_F64_e64_si        = 5878,
    5894             :     V_CMPX_LT_F64_e64_vi        = 5879,
    5895             :     V_CMPX_LT_F64_sdwa  = 5880,
    5896             :     V_CMPX_LT_F64_sdwa_gfx9     = 5881,
    5897             :     V_CMPX_LT_F64_sdwa_vi       = 5882,
    5898             :     V_CMPX_LT_I16_e32   = 5883,
    5899             :     V_CMPX_LT_I16_e32_vi        = 5884,
    5900             :     V_CMPX_LT_I16_e64   = 5885,
    5901             :     V_CMPX_LT_I16_e64_vi        = 5886,
    5902             :     V_CMPX_LT_I16_sdwa  = 5887,
    5903             :     V_CMPX_LT_I16_sdwa_gfx9     = 5888,
    5904             :     V_CMPX_LT_I16_sdwa_vi       = 5889,
    5905             :     V_CMPX_LT_I32_e32   = 5890,
    5906             :     V_CMPX_LT_I32_e32_si        = 5891,
    5907             :     V_CMPX_LT_I32_e32_vi        = 5892,
    5908             :     V_CMPX_LT_I32_e64   = 5893,
    5909             :     V_CMPX_LT_I32_e64_si        = 5894,
    5910             :     V_CMPX_LT_I32_e64_vi        = 5895,
    5911             :     V_CMPX_LT_I32_sdwa  = 5896,
    5912             :     V_CMPX_LT_I32_sdwa_gfx9     = 5897,
    5913             :     V_CMPX_LT_I32_sdwa_vi       = 5898,
    5914             :     V_CMPX_LT_I64_e32   = 5899,
    5915             :     V_CMPX_LT_I64_e32_si        = 5900,
    5916             :     V_CMPX_LT_I64_e32_vi        = 5901,
    5917             :     V_CMPX_LT_I64_e64   = 5902,
    5918             :     V_CMPX_LT_I64_e64_si        = 5903,
    5919             :     V_CMPX_LT_I64_e64_vi        = 5904,
    5920             :     V_CMPX_LT_I64_sdwa  = 5905,
    5921             :     V_CMPX_LT_I64_sdwa_gfx9     = 5906,
    5922             :     V_CMPX_LT_I64_sdwa_vi       = 5907,
    5923             :     V_CMPX_LT_U16_e32   = 5908,
    5924             :     V_CMPX_LT_U16_e32_vi        = 5909,
    5925             :     V_CMPX_LT_U16_e64   = 5910,
    5926             :     V_CMPX_LT_U16_e64_vi        = 5911,
    5927             :     V_CMPX_LT_U16_sdwa  = 5912,
    5928             :     V_CMPX_LT_U16_sdwa_gfx9     = 5913,
    5929             :     V_CMPX_LT_U16_sdwa_vi       = 5914,
    5930             :     V_CMPX_LT_U32_e32   = 5915,
    5931             :     V_CMPX_LT_U32_e32_si        = 5916,
    5932             :     V_CMPX_LT_U32_e32_vi        = 5917,
    5933             :     V_CMPX_LT_U32_e64   = 5918,
    5934             :     V_CMPX_LT_U32_e64_si        = 5919,
    5935             :     V_CMPX_LT_U32_e64_vi        = 5920,
    5936             :     V_CMPX_LT_U32_sdwa  = 5921,
    5937             :     V_CMPX_LT_U32_sdwa_gfx9     = 5922,
    5938             :     V_CMPX_LT_U32_sdwa_vi       = 5923,
    5939             :     V_CMPX_LT_U64_e32   = 5924,
    5940             :     V_CMPX_LT_U64_e32_si        = 5925,
    5941             :     V_CMPX_LT_U64_e32_vi        = 5926,
    5942             :     V_CMPX_LT_U64_e64   = 5927,
    5943             :     V_CMPX_LT_U64_e64_si        = 5928,
    5944             :     V_CMPX_LT_U64_e64_vi        = 5929,
    5945             :     V_CMPX_LT_U64_sdwa  = 5930,
    5946             :     V_CMPX_LT_U64_sdwa_gfx9     = 5931,
    5947             :     V_CMPX_LT_U64_sdwa_vi       = 5932,
    5948             :     V_CMPX_NEQ_F16_e32  = 5933,
    5949             :     V_CMPX_NEQ_F16_e32_vi       = 5934,
    5950             :     V_CMPX_NEQ_F16_e64  = 5935,
    5951             :     V_CMPX_NEQ_F16_e64_vi       = 5936,
    5952             :     V_CMPX_NEQ_F16_sdwa = 5937,
    5953             :     V_CMPX_NEQ_F16_sdwa_gfx9    = 5938,
    5954             :     V_CMPX_NEQ_F16_sdwa_vi      = 5939,
    5955             :     V_CMPX_NEQ_F32_e32  = 5940,
    5956             :     V_CMPX_NEQ_F32_e32_si       = 5941,
    5957             :     V_CMPX_NEQ_F32_e32_vi       = 5942,
    5958             :     V_CMPX_NEQ_F32_e64  = 5943,
    5959             :     V_CMPX_NEQ_F32_e64_si       = 5944,
    5960             :     V_CMPX_NEQ_F32_e64_vi       = 5945,
    5961             :     V_CMPX_NEQ_F32_sdwa = 5946,
    5962             :     V_CMPX_NEQ_F32_sdwa_gfx9    = 5947,
    5963             :     V_CMPX_NEQ_F32_sdwa_vi      = 5948,
    5964             :     V_CMPX_NEQ_F64_e32  = 5949,
    5965             :     V_CMPX_NEQ_F64_e32_si       = 5950,
    5966             :     V_CMPX_NEQ_F64_e32_vi       = 5951,
    5967             :     V_CMPX_NEQ_F64_e64  = 5952,
    5968             :     V_CMPX_NEQ_F64_e64_si       = 5953,
    5969             :     V_CMPX_NEQ_F64_e64_vi       = 5954,
    5970             :     V_CMPX_NEQ_F64_sdwa = 5955,
    5971             :     V_CMPX_NEQ_F64_sdwa_gfx9    = 5956,
    5972             :     V_CMPX_NEQ_F64_sdwa_vi      = 5957,
    5973             :     V_CMPX_NE_I16_e32   = 5958,
    5974             :     V_CMPX_NE_I16_e32_vi        = 5959,
    5975             :     V_CMPX_NE_I16_e64   = 5960,
    5976             :     V_CMPX_NE_I16_e64_vi        = 5961,
    5977             :     V_CMPX_NE_I16_sdwa  = 5962,
    5978             :     V_CMPX_NE_I16_sdwa_gfx9     = 5963,
    5979             :     V_CMPX_NE_I16_sdwa_vi       = 5964,
    5980             :     V_CMPX_NE_I32_e32   = 5965,
    5981             :     V_CMPX_NE_I32_e32_si        = 5966,
    5982             :     V_CMPX_NE_I32_e32_vi        = 5967,
    5983             :     V_CMPX_NE_I32_e64   = 5968,
    5984             :     V_CMPX_NE_I32_e64_si        = 5969,
    5985             :     V_CMPX_NE_I32_e64_vi        = 5970,
    5986             :     V_CMPX_NE_I32_sdwa  = 5971,
    5987             :     V_CMPX_NE_I32_sdwa_gfx9     = 5972,
    5988             :     V_CMPX_NE_I32_sdwa_vi       = 5973,
    5989             :     V_CMPX_NE_I64_e32   = 5974,
    5990             :     V_CMPX_NE_I64_e32_si        = 5975,
    5991             :     V_CMPX_NE_I64_e32_vi        = 5976,
    5992             :     V_CMPX_NE_I64_e64   = 5977,
    5993             :     V_CMPX_NE_I64_e64_si        = 5978,
    5994             :     V_CMPX_NE_I64_e64_vi        = 5979,
    5995             :     V_CMPX_NE_I64_sdwa  = 5980,
    5996             :     V_CMPX_NE_I64_sdwa_gfx9     = 5981,
    5997             :     V_CMPX_NE_I64_sdwa_vi       = 5982,
    5998             :     V_CMPX_NE_U16_e32   = 5983,
    5999             :     V_CMPX_NE_U16_e32_vi        = 5984,
    6000             :     V_CMPX_NE_U16_e64   = 5985,
    6001             :     V_CMPX_NE_U16_e64_vi        = 5986,
    6002             :     V_CMPX_NE_U16_sdwa  = 5987,
    6003             :     V_CMPX_NE_U16_sdwa_gfx9     = 5988,
    6004             :     V_CMPX_NE_U16_sdwa_vi       = 5989,
    6005             :     V_CMPX_NE_U32_e32   = 5990,
    6006             :     V_CMPX_NE_U32_e32_si        = 5991,
    6007             :     V_CMPX_NE_U32_e32_vi        = 5992,
    6008             :     V_CMPX_NE_U32_e64   = 5993,
    6009             :     V_CMPX_NE_U32_e64_si        = 5994,
    6010             :     V_CMPX_NE_U32_e64_vi        = 5995,
    6011             :     V_CMPX_NE_U32_sdwa  = 5996,
    6012             :     V_CMPX_NE_U32_sdwa_gfx9     = 5997,
    6013             :     V_CMPX_NE_U32_sdwa_vi       = 5998,
    6014             :     V_CMPX_NE_U64_e32   = 5999,
    6015             :     V_CMPX_NE_U64_e32_si        = 6000,
    6016             :     V_CMPX_NE_U64_e32_vi        = 6001,
    6017             :     V_CMPX_NE_U64_e64   = 6002,
    6018             :     V_CMPX_NE_U64_e64_si        = 6003,
    6019             :     V_CMPX_NE_U64_e64_vi        = 6004,
    6020             :     V_CMPX_NE_U64_sdwa  = 6005,
    6021             :     V_CMPX_NE_U64_sdwa_gfx9     = 6006,
    6022             :     V_CMPX_NE_U64_sdwa_vi       = 6007,
    6023             :     V_CMPX_NGE_F16_e32  = 6008,
    6024             :     V_CMPX_NGE_F16_e32_vi       = 6009,
    6025             :     V_CMPX_NGE_F16_e64  = 6010,
    6026             :     V_CMPX_NGE_F16_e64_vi       = 6011,
    6027             :     V_CMPX_NGE_F16_sdwa = 6012,
    6028             :     V_CMPX_NGE_F16_sdwa_gfx9    = 6013,
    6029             :     V_CMPX_NGE_F16_sdwa_vi      = 6014,
    6030             :     V_CMPX_NGE_F32_e32  = 6015,
    6031             :     V_CMPX_NGE_F32_e32_si       = 6016,
    6032             :     V_CMPX_NGE_F32_e32_vi       = 6017,
    6033             :     V_CMPX_NGE_F32_e64  = 6018,
    6034             :     V_CMPX_NGE_F32_e64_si       = 6019,
    6035             :     V_CMPX_NGE_F32_e64_vi       = 6020,
    6036             :     V_CMPX_NGE_F32_sdwa = 6021,
    6037             :     V_CMPX_NGE_F32_sdwa_gfx9    = 6022,
    6038             :     V_CMPX_NGE_F32_sdwa_vi      = 6023,
    6039             :     V_CMPX_NGE_F64_e32  = 6024,
    6040             :     V_CMPX_NGE_F64_e32_si       = 6025,
    6041             :     V_CMPX_NGE_F64_e32_vi       = 6026,
    6042             :     V_CMPX_NGE_F64_e64  = 6027,
    6043             :     V_CMPX_NGE_F64_e64_si       = 6028,
    6044             :     V_CMPX_NGE_F64_e64_vi       = 6029,
    6045             :     V_CMPX_NGE_F64_sdwa = 6030,
    6046             :     V_CMPX_NGE_F64_sdwa_gfx9    = 6031,
    6047             :     V_CMPX_NGE_F64_sdwa_vi      = 6032,
    6048             :     V_CMPX_NGT_F16_e32  = 6033,
    6049             :     V_CMPX_NGT_F16_e32_vi       = 6034,
    6050             :     V_CMPX_NGT_F16_e64  = 6035,
    6051             :     V_CMPX_NGT_F16_e64_vi       = 6036,
    6052             :     V_CMPX_NGT_F16_sdwa = 6037,
    6053             :     V_CMPX_NGT_F16_sdwa_gfx9    = 6038,
    6054             :     V_CMPX_NGT_F16_sdwa_vi      = 6039,
    6055             :     V_CMPX_NGT_F32_e32  = 6040,
    6056             :     V_CMPX_NGT_F32_e32_si       = 6041,
    6057             :     V_CMPX_NGT_F32_e32_vi       = 6042,
    6058             :     V_CMPX_NGT_F32_e64  = 6043,
    6059             :     V_CMPX_NGT_F32_e64_si       = 6044,
    6060             :     V_CMPX_NGT_F32_e64_vi       = 6045,
    6061             :     V_CMPX_NGT_F32_sdwa = 6046,
    6062             :     V_CMPX_NGT_F32_sdwa_gfx9    = 6047,
    6063             :     V_CMPX_NGT_F32_sdwa_vi      = 6048,
    6064             :     V_CMPX_NGT_F64_e32  = 6049,
    6065             :     V_CMPX_NGT_F64_e32_si       = 6050,
    6066             :     V_CMPX_NGT_F64_e32_vi       = 6051,
    6067             :     V_CMPX_NGT_F64_e64  = 6052,
    6068             :     V_CMPX_NGT_F64_e64_si       = 6053,
    6069             :     V_CMPX_NGT_F64_e64_vi       = 6054,
    6070             :     V_CMPX_NGT_F64_sdwa = 6055,
    6071             :     V_CMPX_NGT_F64_sdwa_gfx9    = 6056,
    6072             :     V_CMPX_NGT_F64_sdwa_vi      = 6057,
    6073             :     V_CMPX_NLE_F16_e32  = 6058,
    6074             :     V_CMPX_NLE_F16_e32_vi       = 6059,
    6075             :     V_CMPX_NLE_F16_e64  = 6060,
    6076             :     V_CMPX_NLE_F16_e64_vi       = 6061,
    6077             :     V_CMPX_NLE_F16_sdwa = 6062,
    6078             :     V_CMPX_NLE_F16_sdwa_gfx9    = 6063,
    6079             :     V_CMPX_NLE_F16_sdwa_vi      = 6064,
    6080             :     V_CMPX_NLE_F32_e32  = 6065,
    6081             :     V_CMPX_NLE_F32_e32_si       = 6066,
    6082             :     V_CMPX_NLE_F32_e32_vi       = 6067,
    6083             :     V_CMPX_NLE_F32_e64  = 6068,
    6084             :     V_CMPX_NLE_F32_e64_si       = 6069,
    6085             :     V_CMPX_NLE_F32_e64_vi       = 6070,
    6086             :     V_CMPX_NLE_F32_sdwa = 6071,
    6087             :     V_CMPX_NLE_F32_sdwa_gfx9    = 6072,
    6088             :     V_CMPX_NLE_F32_sdwa_vi      = 6073,
    6089             :     V_CMPX_NLE_F64_e32  = 6074,
    6090             :     V_CMPX_NLE_F64_e32_si       = 6075,
    6091             :     V_CMPX_NLE_F64_e32_vi       = 6076,
    6092             :     V_CMPX_NLE_F64_e64  = 6077,
    6093             :     V_CMPX_NLE_F64_e64_si       = 6078,
    6094             :     V_CMPX_NLE_F64_e64_vi       = 6079,
    6095             :     V_CMPX_NLE_F64_sdwa = 6080,
    6096             :     V_CMPX_NLE_F64_sdwa_gfx9    = 6081,
    6097             :     V_CMPX_NLE_F64_sdwa_vi      = 6082,
    6098             :     V_CMPX_NLG_F16_e32  = 6083,
    6099             :     V_CMPX_NLG_F16_e32_vi       = 6084,
    6100             :     V_CMPX_NLG_F16_e64  = 6085,
    6101             :     V_CMPX_NLG_F16_e64_vi       = 6086,
    6102             :     V_CMPX_NLG_F16_sdwa = 6087,
    6103             :     V_CMPX_NLG_F16_sdwa_gfx9    = 6088,
    6104             :     V_CMPX_NLG_F16_sdwa_vi      = 6089,
    6105             :     V_CMPX_NLG_F32_e32  = 6090,
    6106             :     V_CMPX_NLG_F32_e32_si       = 6091,
    6107             :     V_CMPX_NLG_F32_e32_vi       = 6092,
    6108             :     V_CMPX_NLG_F32_e64  = 6093,
    6109             :     V_CMPX_NLG_F32_e64_si       = 6094,
    6110             :     V_CMPX_NLG_F32_e64_vi       = 6095,
    6111             :     V_CMPX_NLG_F32_sdwa = 6096,
    6112             :     V_CMPX_NLG_F32_sdwa_gfx9    = 6097,
    6113             :     V_CMPX_NLG_F32_sdwa_vi      = 6098,
    6114             :     V_CMPX_NLG_F64_e32  = 6099,
    6115             :     V_CMPX_NLG_F64_e32_si       = 6100,
    6116             :     V_CMPX_NLG_F64_e32_vi       = 6101,
    6117             :     V_CMPX_NLG_F64_e64  = 6102,
    6118             :     V_CMPX_NLG_F64_e64_si       = 6103,
    6119             :     V_CMPX_NLG_F64_e64_vi       = 6104,
    6120             :     V_CMPX_NLG_F64_sdwa = 6105,
    6121             :     V_CMPX_NLG_F64_sdwa_gfx9    = 6106,
    6122             :     V_CMPX_NLG_F64_sdwa_vi      = 6107,
    6123             :     V_CMPX_NLT_F16_e32  = 6108,
    6124             :     V_CMPX_NLT_F16_e32_vi       = 6109,
    6125             :     V_CMPX_NLT_F16_e64  = 6110,
    6126             :     V_CMPX_NLT_F16_e64_vi       = 6111,
    6127             :     V_CMPX_NLT_F16_sdwa = 6112,
    6128             :     V_CMPX_NLT_F16_sdwa_gfx9    = 6113,
    6129             :     V_CMPX_NLT_F16_sdwa_vi      = 6114,
    6130             :     V_CMPX_NLT_F32_e32  = 6115,
    6131             :     V_CMPX_NLT_F32_e32_si       = 6116,
    6132             :     V_CMPX_NLT_F32_e32_vi       = 6117,
    6133             :     V_CMPX_NLT_F32_e64  = 6118,
    6134             :     V_CMPX_NLT_F32_e64_si       = 6119,
    6135             :     V_CMPX_NLT_F32_e64_vi       = 6120,
    6136             :     V_CMPX_NLT_F32_sdwa = 6121,
    6137             :     V_CMPX_NLT_F32_sdwa_gfx9    = 6122,
    6138             :     V_CMPX_NLT_F32_sdwa_vi      = 6123,
    6139             :     V_CMPX_NLT_F64_e32  = 6124,
    6140             :     V_CMPX_NLT_F64_e32_si       = 6125,
    6141             :     V_CMPX_NLT_F64_e32_vi       = 6126,
    6142             :     V_CMPX_NLT_F64_e64  = 6127,
    6143             :     V_CMPX_NLT_F64_e64_si       = 6128,
    6144             :     V_CMPX_NLT_F64_e64_vi       = 6129,
    6145             :     V_CMPX_NLT_F64_sdwa = 6130,
    6146             :     V_CMPX_NLT_F64_sdwa_gfx9    = 6131,
    6147             :     V_CMPX_NLT_F64_sdwa_vi      = 6132,
    6148             :     V_CMPX_O_F16_e32    = 6133,
    6149             :     V_CMPX_O_F16_e32_vi = 6134,
    6150             :     V_CMPX_O_F16_e64    = 6135,
    6151             :     V_CMPX_O_F16_e64_vi = 6136,
    6152             :     V_CMPX_O_F16_sdwa   = 6137,
    6153             :     V_CMPX_O_F16_sdwa_gfx9      = 6138,
    6154             :     V_CMPX_O_F16_sdwa_vi        = 6139,
    6155             :     V_CMPX_O_F32_e32    = 6140,
    6156             :     V_CMPX_O_F32_e32_si = 6141,
    6157             :     V_CMPX_O_F32_e32_vi = 6142,
    6158             :     V_CMPX_O_F32_e64    = 6143,
    6159             :     V_CMPX_O_F32_e64_si = 6144,
    6160             :     V_CMPX_O_F32_e64_vi = 6145,
    6161             :     V_CMPX_O_F32_sdwa   = 6146,
    6162             :     V_CMPX_O_F32_sdwa_gfx9      = 6147,
    6163             :     V_CMPX_O_F32_sdwa_vi        = 6148,
    6164             :     V_CMPX_O_F64_e32    = 6149,
    6165             :     V_CMPX_O_F64_e32_si = 6150,
    6166             :     V_CMPX_O_F64_e32_vi = 6151,
    6167             :     V_CMPX_O_F64_e64    = 6152,
    6168             :     V_CMPX_O_F64_e64_si = 6153,
    6169             :     V_CMPX_O_F64_e64_vi = 6154,
    6170             :     V_CMPX_O_F64_sdwa   = 6155,
    6171             :     V_CMPX_O_F64_sdwa_gfx9      = 6156,
    6172             :     V_CMPX_O_F64_sdwa_vi        = 6157,
    6173             :     V_CMPX_TRU_F16_e32  = 6158,
    6174             :     V_CMPX_TRU_F16_e32_vi       = 6159,
    6175             :     V_CMPX_TRU_F16_e64  = 6160,
    6176             :     V_CMPX_TRU_F16_e64_vi       = 6161,
    6177             :     V_CMPX_TRU_F16_sdwa = 6162,
    6178             :     V_CMPX_TRU_F16_sdwa_gfx9    = 6163,
    6179             :     V_CMPX_TRU_F16_sdwa_vi      = 6164,
    6180             :     V_CMPX_TRU_F32_e32  = 6165,
    6181             :     V_CMPX_TRU_F32_e32_si       = 6166,
    6182             :     V_CMPX_TRU_F32_e32_vi       = 6167,
    6183             :     V_CMPX_TRU_F32_e64  = 6168,
    6184             :     V_CMPX_TRU_F32_e64_si       = 6169,
    6185             :     V_CMPX_TRU_F32_e64_vi       = 6170,
    6186             :     V_CMPX_TRU_F32_sdwa = 6171,
    6187             :     V_CMPX_TRU_F32_sdwa_gfx9    = 6172,
    6188             :     V_CMPX_TRU_F32_sdwa_vi      = 6173,
    6189             :     V_CMPX_TRU_F64_e32  = 6174,
    6190             :     V_CMPX_TRU_F64_e32_si       = 6175,
    6191             :     V_CMPX_TRU_F64_e32_vi       = 6176,
    6192             :     V_CMPX_TRU_F64_e64  = 6177,
    6193             :     V_CMPX_TRU_F64_e64_si       = 6178,
    6194             :     V_CMPX_TRU_F64_e64_vi       = 6179,
    6195             :     V_CMPX_TRU_F64_sdwa = 6180,
    6196             :     V_CMPX_TRU_F64_sdwa_gfx9    = 6181,
    6197             :     V_CMPX_TRU_F64_sdwa_vi      = 6182,
    6198             :     V_CMPX_T_I16_e32    = 6183,
    6199             :     V_CMPX_T_I16_e32_vi = 6184,
    6200             :     V_CMPX_T_I16_e64    = 6185,
    6201             :     V_CMPX_T_I16_e64_vi = 6186,
    6202             :     V_CMPX_T_I16_sdwa   = 6187,
    6203             :     V_CMPX_T_I16_sdwa_gfx9      = 6188,
    6204             :     V_CMPX_T_I16_sdwa_vi        = 6189,
    6205             :     V_CMPX_T_I32_e32    = 6190,
    6206             :     V_CMPX_T_I32_e32_si = 6191,
    6207             :     V_CMPX_T_I32_e32_vi = 6192,
    6208             :     V_CMPX_T_I32_e64    = 6193,
    6209             :     V_CMPX_T_I32_e64_si = 6194,
    6210             :     V_CMPX_T_I32_e64_vi = 6195,
    6211             :     V_CMPX_T_I32_sdwa   = 6196,
    6212             :     V_CMPX_T_I32_sdwa_gfx9      = 6197,
    6213             :     V_CMPX_T_I32_sdwa_vi        = 6198,
    6214             :     V_CMPX_T_I64_e32    = 6199,
    6215             :     V_CMPX_T_I64_e32_si = 6200,
    6216             :     V_CMPX_T_I64_e32_vi = 6201,
    6217             :     V_CMPX_T_I64_e64    = 6202,
    6218             :     V_CMPX_T_I64_e64_si = 6203,
    6219             :     V_CMPX_T_I64_e64_vi = 6204,
    6220             :     V_CMPX_T_I64_sdwa   = 6205,
    6221             :     V_CMPX_T_I64_sdwa_gfx9      = 6206,
    6222             :     V_CMPX_T_I64_sdwa_vi        = 6207,
    6223             :     V_CMPX_T_U16_e32    = 6208,
    6224             :     V_CMPX_T_U16_e32_vi = 6209,
    6225             :     V_CMPX_T_U16_e64    = 6210,
    6226             :     V_CMPX_T_U16_e64_vi = 6211,
    6227             :     V_CMPX_T_U16_sdwa   = 6212,
    6228             :     V_CMPX_T_U16_sdwa_gfx9      = 6213,
    6229             :     V_CMPX_T_U16_sdwa_vi        = 6214,
    6230             :     V_CMPX_T_U32_e32    = 6215,
    6231             :     V_CMPX_T_U32_e32_si = 6216,
    6232             :     V_CMPX_T_U32_e32_vi = 6217,
    6233             :     V_CMPX_T_U32_e64    = 6218,
    6234             :     V_CMPX_T_U32_e64_si = 6219,
    6235             :     V_CMPX_T_U32_e64_vi = 6220,
    6236             :     V_CMPX_T_U32_sdwa   = 6221,
    6237             :     V_CMPX_T_U32_sdwa_gfx9      = 6222,
    6238             :     V_CMPX_T_U32_sdwa_vi        = 6223,
    6239             :     V_CMPX_T_U64_e32    = 6224,
    6240             :     V_CMPX_T_U64_e32_si = 6225,
    6241             :     V_CMPX_T_U64_e32_vi = 6226,
    6242             :     V_CMPX_T_U64_e64    = 6227,
    6243             :     V_CMPX_T_U64_e64_si = 6228,
    6244             :     V_CMPX_T_U64_e64_vi = 6229,
    6245             :     V_CMPX_T_U64_sdwa   = 6230,
    6246             :     V_CMPX_T_U64_sdwa_gfx9      = 6231,
    6247             :     V_CMPX_T_U64_sdwa_vi        = 6232,
    6248             :     V_CMPX_U_F16_e32    = 6233,
    6249             :     V_CMPX_U_F16_e32_vi = 6234,
    6250             :     V_CMPX_U_F16_e64    = 6235,
    6251             :     V_CMPX_U_F16_e64_vi = 6236,
    6252             :     V_CMPX_U_F16_sdwa   = 6237,
    6253             :     V_CMPX_U_F16_sdwa_gfx9      = 6238,
    6254             :     V_CMPX_U_F16_sdwa_vi        = 6239,
    6255             :     V_CMPX_U_F32_e32    = 6240,
    6256             :     V_CMPX_U_F32_e32_si = 6241,
    6257             :     V_CMPX_U_F32_e32_vi = 6242,
    6258             :     V_CMPX_U_F32_e64    = 6243,
    6259             :     V_CMPX_U_F32_e64_si = 6244,
    6260             :     V_CMPX_U_F32_e64_vi = 6245,
    6261             :     V_CMPX_U_F32_sdwa   = 6246,
    6262             :     V_CMPX_U_F32_sdwa_gfx9      = 6247,
    6263             :     V_CMPX_U_F32_sdwa_vi        = 6248,
    6264             :     V_CMPX_U_F64_e32    = 6249,
    6265             :     V_CMPX_U_F64_e32_si = 6250,
    6266             :     V_CMPX_U_F64_e32_vi = 6251,
    6267             :     V_CMPX_U_F64_e64    = 6252,
    6268             :     V_CMPX_U_F64_e64_si = 6253,
    6269             :     V_CMPX_U_F64_e64_vi = 6254,
    6270             :     V_CMPX_U_F64_sdwa   = 6255,
    6271             :     V_CMPX_U_F64_sdwa_gfx9      = 6256,
    6272             :     V_CMPX_U_F64_sdwa_vi        = 6257,
    6273             :     V_CMP_CLASS_F16_e32 = 6258,
    6274             :     V_CMP_CLASS_F16_e32_vi      = 6259,
    6275             :     V_CMP_CLASS_F16_e64 = 6260,
    6276             :     V_CMP_CLASS_F16_e64_vi      = 6261,
    6277             :     V_CMP_CLASS_F16_sdwa        = 6262,
    6278             :     V_CMP_CLASS_F16_sdwa_gfx9   = 6263,
    6279             :     V_CMP_CLASS_F16_sdwa_vi     = 6264,
    6280             :     V_CMP_CLASS_F32_e32 = 6265,
    6281             :     V_CMP_CLASS_F32_e32_si      = 6266,
    6282             :     V_CMP_CLASS_F32_e32_vi      = 6267,
    6283             :     V_CMP_CLASS_F32_e64 = 6268,
    6284             :     V_CMP_CLASS_F32_e64_si      = 6269,
    6285             :     V_CMP_CLASS_F32_e64_vi      = 6270,
    6286             :     V_CMP_CLASS_F32_sdwa        = 6271,
    6287             :     V_CMP_CLASS_F32_sdwa_gfx9   = 6272,
    6288             :     V_CMP_CLASS_F32_sdwa_vi     = 6273,
    6289             :     V_CMP_CLASS_F64_e32 = 6274,
    6290             :     V_CMP_CLASS_F64_e32_si      = 6275,
    6291             :     V_CMP_CLASS_F64_e32_vi      = 6276,
    6292             :     V_CMP_CLASS_F64_e64 = 6277,
    6293             :     V_CMP_CLASS_F64_e64_si      = 6278,
    6294             :     V_CMP_CLASS_F64_e64_vi      = 6279,
    6295             :     V_CMP_CLASS_F64_sdwa        = 6280,
    6296             :     V_CMP_CLASS_F64_sdwa_gfx9   = 6281,
    6297             :     V_CMP_CLASS_F64_sdwa_vi     = 6282,
    6298             :     V_CMP_EQ_F16_e32    = 6283,
    6299             :     V_CMP_EQ_F16_e32_vi = 6284,
    6300             :     V_CMP_EQ_F16_e64    = 6285,
    6301             :     V_CMP_EQ_F16_e64_vi = 6286,
    6302             :     V_CMP_EQ_F16_sdwa   = 6287,
    6303             :     V_CMP_EQ_F16_sdwa_gfx9      = 6288,
    6304             :     V_CMP_EQ_F16_sdwa_vi        = 6289,
    6305             :     V_CMP_EQ_F32_e32    = 6290,
    6306             :     V_CMP_EQ_F32_e32_si = 6291,
    6307             :     V_CMP_EQ_F32_e32_vi = 6292,
    6308             :     V_CMP_EQ_F32_e64    = 6293,
    6309             :     V_CMP_EQ_F32_e64_si = 6294,
    6310             :     V_CMP_EQ_F32_e64_vi = 6295,
    6311             :     V_CMP_EQ_F32_sdwa   = 6296,
    6312             :     V_CMP_EQ_F32_sdwa_gfx9      = 6297,
    6313             :     V_CMP_EQ_F32_sdwa_vi        = 6298,
    6314             :     V_CMP_EQ_F64_e32    = 6299,
    6315             :     V_CMP_EQ_F64_e32_si = 6300,
    6316             :     V_CMP_EQ_F64_e32_vi = 6301,
    6317             :     V_CMP_EQ_F64_e64    = 6302,
    6318             :     V_CMP_EQ_F64_e64_si = 6303,
    6319             :     V_CMP_EQ_F64_e64_vi = 6304,
    6320             :     V_CMP_EQ_F64_sdwa   = 6305,
    6321             :     V_CMP_EQ_F64_sdwa_gfx9      = 6306,
    6322             :     V_CMP_EQ_F64_sdwa_vi        = 6307,
    6323             :     V_CMP_EQ_I16_e32    = 6308,
    6324             :     V_CMP_EQ_I16_e32_vi = 6309,
    6325             :     V_CMP_EQ_I16_e64    = 6310,
    6326             :     V_CMP_EQ_I16_e64_vi = 6311,
    6327             :     V_CMP_EQ_I16_sdwa   = 6312,
    6328             :     V_CMP_EQ_I16_sdwa_gfx9      = 6313,
    6329             :     V_CMP_EQ_I16_sdwa_vi        = 6314,
    6330             :     V_CMP_EQ_I32_e32    = 6315,
    6331             :     V_CMP_EQ_I32_e32_si = 6316,
    6332             :     V_CMP_EQ_I32_e32_vi = 6317,
    6333             :     V_CMP_EQ_I32_e64    = 6318,
    6334             :     V_CMP_EQ_I32_e64_si = 6319,
    6335             :     V_CMP_EQ_I32_e64_vi = 6320,
    6336             :     V_CMP_EQ_I32_sdwa   = 6321,
    6337             :     V_CMP_EQ_I32_sdwa_gfx9      = 6322,
    6338             :     V_CMP_EQ_I32_sdwa_vi        = 6323,
    6339             :     V_CMP_EQ_I64_e32    = 6324,
    6340             :     V_CMP_EQ_I64_e32_si = 6325,
    6341             :     V_CMP_EQ_I64_e32_vi = 6326,
    6342             :     V_CMP_EQ_I64_e64    = 6327,
    6343             :     V_CMP_EQ_I64_e64_si = 6328,
    6344             :     V_CMP_EQ_I64_e64_vi = 6329,
    6345             :     V_CMP_EQ_I64_sdwa   = 6330,
    6346             :     V_CMP_EQ_I64_sdwa_gfx9      = 6331,
    6347             :     V_CMP_EQ_I64_sdwa_vi        = 6332,
    6348             :     V_CMP_EQ_U16_e32    = 6333,
    6349             :     V_CMP_EQ_U16_e32_vi = 6334,
    6350             :     V_CMP_EQ_U16_e64    = 6335,
    6351             :     V_CMP_EQ_U16_e64_vi = 6336,
    6352             :     V_CMP_EQ_U16_sdwa   = 6337,
    6353             :     V_CMP_EQ_U16_sdwa_gfx9      = 6338,
    6354             :     V_CMP_EQ_U16_sdwa_vi        = 6339,
    6355             :     V_CMP_EQ_U32_e32    = 6340,
    6356             :     V_CMP_EQ_U32_e32_si = 6341,
    6357             :     V_CMP_EQ_U32_e32_vi = 6342,
    6358             :     V_CMP_EQ_U32_e64    = 6343,
    6359             :     V_CMP_EQ_U32_e64_si = 6344,
    6360             :     V_CMP_EQ_U32_e64_vi = 6345,
    6361             :     V_CMP_EQ_U32_sdwa   = 6346,
    6362             :     V_CMP_EQ_U32_sdwa_gfx9      = 6347,
    6363             :     V_CMP_EQ_U32_sdwa_vi        = 6348,
    6364             :     V_CMP_EQ_U64_e32    = 6349,
    6365             :     V_CMP_EQ_U64_e32_si = 6350,
    6366             :     V_CMP_EQ_U64_e32_vi = 6351,
    6367             :     V_CMP_EQ_U64_e64    = 6352,
    6368             :     V_CMP_EQ_U64_e64_si = 6353,
    6369             :     V_CMP_EQ_U64_e64_vi = 6354,
    6370             :     V_CMP_EQ_U64_sdwa   = 6355,
    6371             :     V_CMP_EQ_U64_sdwa_gfx9      = 6356,
    6372             :     V_CMP_EQ_U64_sdwa_vi        = 6357,
    6373             :     V_CMP_F_F16_e32     = 6358,
    6374             :     V_CMP_F_F16_e32_vi  = 6359,
    6375             :     V_CMP_F_F16_e64     = 6360,
    6376             :     V_CMP_F_F16_e64_vi  = 6361,
    6377             :     V_CMP_F_F16_sdwa    = 6362,
    6378             :     V_CMP_F_F16_sdwa_gfx9       = 6363,
    6379             :     V_CMP_F_F16_sdwa_vi = 6364,
    6380             :     V_CMP_F_F32_e32     = 6365,
    6381             :     V_CMP_F_F32_e32_si  = 6366,
    6382             :     V_CMP_F_F32_e32_vi  = 6367,
    6383             :     V_CMP_F_F32_e64     = 6368,
    6384             :     V_CMP_F_F32_e64_si  = 6369,
    6385             :     V_CMP_F_F32_e64_vi  = 6370,
    6386             :     V_CMP_F_F32_sdwa    = 6371,
    6387             :     V_CMP_F_F32_sdwa_gfx9       = 6372,
    6388             :     V_CMP_F_F32_sdwa_vi = 6373,
    6389             :     V_CMP_F_F64_e32     = 6374,
    6390             :     V_CMP_F_F64_e32_si  = 6375,
    6391             :     V_CMP_F_F64_e32_vi  = 6376,
    6392             :     V_CMP_F_F64_e64     = 6377,
    6393             :     V_CMP_F_F64_e64_si  = 6378,
    6394             :     V_CMP_F_F64_e64_vi  = 6379,
    6395             :     V_CMP_F_F64_sdwa    = 6380,
    6396             :     V_CMP_F_F64_sdwa_gfx9       = 6381,
    6397             :     V_CMP_F_F64_sdwa_vi = 6382,
    6398             :     V_CMP_F_I16_e32     = 6383,
    6399             :     V_CMP_F_I16_e32_vi  = 6384,
    6400             :     V_CMP_F_I16_e64     = 6385,
    6401             :     V_CMP_F_I16_e64_vi  = 6386,
    6402             :     V_CMP_F_I16_sdwa    = 6387,
    6403             :     V_CMP_F_I16_sdwa_gfx9       = 6388,
    6404             :     V_CMP_F_I16_sdwa_vi = 6389,
    6405             :     V_CMP_F_I32_e32     = 6390,
    6406             :     V_CMP_F_I32_e32_si  = 6391,
    6407             :     V_CMP_F_I32_e32_vi  = 6392,
    6408             :     V_CMP_F_I32_e64     = 6393,
    6409             :     V_CMP_F_I32_e64_si  = 6394,
    6410             :     V_CMP_F_I32_e64_vi  = 6395,
    6411             :     V_CMP_F_I32_sdwa    = 6396,
    6412             :     V_CMP_F_I32_sdwa_gfx9       = 6397,
    6413             :     V_CMP_F_I32_sdwa_vi = 6398,
    6414             :     V_CMP_F_I64_e32     = 6399,
    6415             :     V_CMP_F_I64_e32_si  = 6400,
    6416             :     V_CMP_F_I64_e32_vi  = 6401,
    6417             :     V_CMP_F_I64_e64     = 6402,
    6418             :     V_CMP_F_I64_e64_si  = 6403,
    6419             :     V_CMP_F_I64_e64_vi  = 6404,
    6420             :     V_CMP_F_I64_sdwa    = 6405,
    6421             :     V_CMP_F_I64_sdwa_gfx9       = 6406,
    6422             :     V_CMP_F_I64_sdwa_vi = 6407,
    6423             :     V_CMP_F_U16_e32     = 6408,
    6424             :     V_CMP_F_U16_e32_vi  = 6409,
    6425             :     V_CMP_F_U16_e64     = 6410,
    6426             :     V_CMP_F_U16_e64_vi  = 6411,
    6427             :     V_CMP_F_U16_sdwa    = 6412,
    6428             :     V_CMP_F_U16_sdwa_gfx9       = 6413,
    6429             :     V_CMP_F_U16_sdwa_vi = 6414,
    6430             :     V_CMP_F_U32_e32     = 6415,
    6431             :     V_CMP_F_U32_e32_si  = 6416,
    6432             :     V_CMP_F_U32_e32_vi  = 6417,
    6433             :     V_CMP_F_U32_e64     = 6418,
    6434             :     V_CMP_F_U32_e64_si  = 6419,
    6435             :     V_CMP_F_U32_e64_vi  = 6420,
    6436             :     V_CMP_F_U32_sdwa    = 6421,
    6437             :     V_CMP_F_U32_sdwa_gfx9       = 6422,
    6438             :     V_CMP_F_U32_sdwa_vi = 6423,
    6439             :     V_CMP_F_U64_e32     = 6424,
    6440             :     V_CMP_F_U64_e32_si  = 6425,
    6441             :     V_CMP_F_U64_e32_vi  = 6426,
    6442             :     V_CMP_F_U64_e64     = 6427,
    6443             :     V_CMP_F_U64_e64_si  = 6428,
    6444             :     V_CMP_F_U64_e64_vi  = 6429,
    6445             :     V_CMP_F_U64_sdwa    = 6430,
    6446             :     V_CMP_F_U64_sdwa_gfx9       = 6431,
    6447             :     V_CMP_F_U64_sdwa_vi = 6432,
    6448             :     V_CMP_GE_F16_e32    = 6433,
    6449             :     V_CMP_GE_F16_e32_vi = 6434,
    6450             :     V_CMP_GE_F16_e64    = 6435,
    6451             :     V_CMP_GE_F16_e64_vi = 6436,
    6452             :     V_CMP_GE_F16_sdwa   = 6437,
    6453             :     V_CMP_GE_F16_sdwa_gfx9      = 6438,
    6454             :     V_CMP_GE_F16_sdwa_vi        = 6439,
    6455             :     V_CMP_GE_F32_e32    = 6440,
    6456             :     V_CMP_GE_F32_e32_si = 6441,
    6457             :     V_CMP_GE_F32_e32_vi = 6442,
    6458             :     V_CMP_GE_F32_e64    = 6443,
    6459             :     V_CMP_GE_F32_e64_si = 6444,
    6460             :     V_CMP_GE_F32_e64_vi = 6445,
    6461             :     V_CMP_GE_F32_sdwa   = 6446,
    6462             :     V_CMP_GE_F32_sdwa_gfx9      = 6447,
    6463             :     V_CMP_GE_F32_sdwa_vi        = 6448,
    6464             :     V_CMP_GE_F64_e32    = 6449,
    6465             :     V_CMP_GE_F64_e32_si = 6450,
    6466             :     V_CMP_GE_F64_e32_vi = 6451,
    6467             :     V_CMP_GE_F64_e64    = 6452,
    6468             :     V_CMP_GE_F64_e64_si = 6453,
    6469             :     V_CMP_GE_F64_e64_vi = 6454,
    6470             :     V_CMP_GE_F64_sdwa   = 6455,
    6471             :     V_CMP_GE_F64_sdwa_gfx9      = 6456,
    6472             :     V_CMP_GE_F64_sdwa_vi        = 6457,
    6473             :     V_CMP_GE_I16_e32    = 6458,
    6474             :     V_CMP_GE_I16_e32_vi = 6459,
    6475             :     V_CMP_GE_I16_e64    = 6460,
    6476             :     V_CMP_GE_I16_e64_vi = 6461,
    6477             :     V_CMP_GE_I16_sdwa   = 6462,
    6478             :     V_CMP_GE_I16_sdwa_gfx9      = 6463,
    6479             :     V_CMP_GE_I16_sdwa_vi        = 6464,
    6480             :     V_CMP_GE_I32_e32    = 6465,
    6481             :     V_CMP_GE_I32_e32_si = 6466,
    6482             :     V_CMP_GE_I32_e32_vi = 6467,
    6483             :     V_CMP_GE_I32_e64    = 6468,
    6484             :     V_CMP_GE_I32_e64_si = 6469,
    6485             :     V_CMP_GE_I32_e64_vi = 6470,
    6486             :     V_CMP_GE_I32_sdwa   = 6471,
    6487             :     V_CMP_GE_I32_sdwa_gfx9      = 6472,
    6488             :     V_CMP_GE_I32_sdwa_vi        = 6473,
    6489             :     V_CMP_GE_I64_e32    = 6474,
    6490             :     V_CMP_GE_I64_e32_si = 6475,
    6491             :     V_CMP_GE_I64_e32_vi = 6476,
    6492             :     V_CMP_GE_I64_e64    = 6477,
    6493             :     V_CMP_GE_I64_e64_si = 6478,
    6494             :     V_CMP_GE_I64_e64_vi = 6479,
    6495             :     V_CMP_GE_I64_sdwa   = 6480,
    6496             :     V_CMP_GE_I64_sdwa_gfx9      = 6481,
    6497             :     V_CMP_GE_I64_sdwa_vi        = 6482,
    6498             :     V_CMP_GE_U16_e32    = 6483,
    6499             :     V_CMP_GE_U16_e32_vi = 6484,
    6500             :     V_CMP_GE_U16_e64    = 6485,
    6501             :     V_CMP_GE_U16_e64_vi = 6486,
    6502             :     V_CMP_GE_U16_sdwa   = 6487,
    6503             :     V_CMP_GE_U16_sdwa_gfx9      = 6488,
    6504             :     V_CMP_GE_U16_sdwa_vi        = 6489,
    6505             :     V_CMP_GE_U32_e32    = 6490,
    6506             :     V_CMP_GE_U32_e32_si = 6491,
    6507             :     V_CMP_GE_U32_e32_vi = 6492,
    6508             :     V_CMP_GE_U32_e64    = 6493,
    6509             :     V_CMP_GE_U32_e64_si = 6494,
    6510             :     V_CMP_GE_U32_e64_vi = 6495,
    6511             :     V_CMP_GE_U32_sdwa   = 6496,
    6512             :     V_CMP_GE_U32_sdwa_gfx9      = 6497,
    6513             :     V_CMP_GE_U32_sdwa_vi        = 6498,
    6514             :     V_CMP_GE_U64_e32    = 6499,
    6515             :     V_CMP_GE_U64_e32_si = 6500,
    6516             :     V_CMP_GE_U64_e32_vi = 6501,
    6517             :     V_CMP_GE_U64_e64    = 6502,
    6518             :     V_CMP_GE_U64_e64_si = 6503,
    6519             :     V_CMP_GE_U64_e64_vi = 6504,
    6520             :     V_CMP_GE_U64_sdwa   = 6505,
    6521             :     V_CMP_GE_U64_sdwa_gfx9      = 6506,
    6522             :     V_CMP_GE_U64_sdwa_vi        = 6507,
    6523             :     V_CMP_GT_F16_e32    = 6508,
    6524             :     V_CMP_GT_F16_e32_vi = 6509,
    6525             :     V_CMP_GT_F16_e64    = 6510,
    6526             :     V_CMP_GT_F16_e64_vi = 6511,
    6527             :     V_CMP_GT_F16_sdwa   = 6512,
    6528             :     V_CMP_GT_F16_sdwa_gfx9      = 6513,
    6529             :     V_CMP_GT_F16_sdwa_vi        = 6514,
    6530             :     V_CMP_GT_F32_e32    = 6515,
    6531             :     V_CMP_GT_F32_e32_si = 6516,
    6532             :     V_CMP_GT_F32_e32_vi = 6517,
    6533             :     V_CMP_GT_F32_e64    = 6518,
    6534             :     V_CMP_GT_F32_e64_si = 6519,
    6535             :     V_CMP_GT_F32_e64_vi = 6520,
    6536             :     V_CMP_GT_F32_sdwa   = 6521,
    6537             :     V_CMP_GT_F32_sdwa_gfx9      = 6522,
    6538             :     V_CMP_GT_F32_sdwa_vi        = 6523,
    6539             :     V_CMP_GT_F64_e32    = 6524,
    6540             :     V_CMP_GT_F64_e32_si = 6525,
    6541             :     V_CMP_GT_F64_e32_vi = 6526,
    6542             :     V_CMP_GT_F64_e64    = 6527,
    6543             :     V_CMP_GT_F64_e64_si = 6528,
    6544             :     V_CMP_GT_F64_e64_vi = 6529,
    6545             :     V_CMP_GT_F64_sdwa   = 6530,
    6546             :     V_CMP_GT_F64_sdwa_gfx9      = 6531,
    6547             :     V_CMP_GT_F64_sdwa_vi        = 6532,
    6548             :     V_CMP_GT_I16_e32    = 6533,
    6549             :     V_CMP_GT_I16_e32_vi = 6534,
    6550             :     V_CMP_GT_I16_e64    = 6535,
    6551             :     V_CMP_GT_I16_e64_vi = 6536,
    6552             :     V_CMP_GT_I16_sdwa   = 6537,
    6553             :     V_CMP_GT_I16_sdwa_gfx9      = 6538,
    6554             :     V_CMP_GT_I16_sdwa_vi        = 6539,
    6555             :     V_CMP_GT_I32_e32    = 6540,
    6556             :     V_CMP_GT_I32_e32_si = 6541,
    6557             :     V_CMP_GT_I32_e32_vi = 6542,
    6558             :     V_CMP_GT_I32_e64    = 6543,
    6559             :     V_CMP_GT_I32_e64_si = 6544,
    6560             :     V_CMP_GT_I32_e64_vi = 6545,
    6561             :     V_CMP_GT_I32_sdwa   = 6546,
    6562             :     V_CMP_GT_I32_sdwa_gfx9      = 6547,
    6563             :     V_CMP_GT_I32_sdwa_vi        = 6548,
    6564             :     V_CMP_GT_I64_e32    = 6549,
    6565             :     V_CMP_GT_I64_e32_si = 6550,
    6566             :     V_CMP_GT_I64_e32_vi = 6551,
    6567             :     V_CMP_GT_I64_e64    = 6552,
    6568             :     V_CMP_GT_I64_e64_si = 6553,
    6569             :     V_CMP_GT_I64_e64_vi = 6554,
    6570             :     V_CMP_GT_I64_sdwa   = 6555,
    6571             :     V_CMP_GT_I64_sdwa_gfx9      = 6556,
    6572             :     V_CMP_GT_I64_sdwa_vi        = 6557,
    6573             :     V_CMP_GT_U16_e32    = 6558,
    6574             :     V_CMP_GT_U16_e32_vi = 6559,
    6575             :     V_CMP_GT_U16_e64    = 6560,
    6576             :     V_CMP_GT_U16_e64_vi = 6561,
    6577             :     V_CMP_GT_U16_sdwa   = 6562,
    6578             :     V_CMP_GT_U16_sdwa_gfx9      = 6563,
    6579             :     V_CMP_GT_U16_sdwa_vi        = 6564,
    6580             :     V_CMP_GT_U32_e32    = 6565,
    6581             :     V_CMP_GT_U32_e32_si = 6566,
    6582             :     V_CMP_GT_U32_e32_vi = 6567,
    6583             :     V_CMP_GT_U32_e64    = 6568,
    6584             :     V_CMP_GT_U32_e64_si = 6569,
    6585             :     V_CMP_GT_U32_e64_vi = 6570,
    6586             :     V_CMP_GT_U32_sdwa   = 6571,
    6587             :     V_CMP_GT_U32_sdwa_gfx9      = 6572,
    6588             :     V_CMP_GT_U32_sdwa_vi        = 6573,
    6589             :     V_CMP_GT_U64_e32    = 6574,
    6590             :     V_CMP_GT_U64_e32_si = 6575,
    6591             :     V_CMP_GT_U64_e32_vi = 6576,
    6592             :     V_CMP_GT_U64_e64    = 6577,
    6593             :     V_CMP_GT_U64_e64_si = 6578,
    6594             :     V_CMP_GT_U64_e64_vi = 6579,
    6595             :     V_CMP_GT_U64_sdwa   = 6580,
    6596             :     V_CMP_GT_U64_sdwa_gfx9      = 6581,
    6597             :     V_CMP_GT_U64_sdwa_vi        = 6582,
    6598             :     V_CMP_LE_F16_e32    = 6583,
    6599             :     V_CMP_LE_F16_e32_vi = 6584,
    6600             :     V_CMP_LE_F16_e64    = 6585,
    6601             :     V_CMP_LE_F16_e64_vi = 6586,
    6602             :     V_CMP_LE_F16_sdwa   = 6587,
    6603             :     V_CMP_LE_F16_sdwa_gfx9      = 6588,
    6604             :     V_CMP_LE_F16_sdwa_vi        = 6589,
    6605             :     V_CMP_LE_F32_e32    = 6590,
    6606             :     V_CMP_LE_F32_e32_si = 6591,
    6607             :     V_CMP_LE_F32_e32_vi = 6592,
    6608             :     V_CMP_LE_F32_e64    = 6593,
    6609             :     V_CMP_LE_F32_e64_si = 6594,
    6610             :     V_CMP_LE_F32_e64_vi = 6595,
    6611             :     V_CMP_LE_F32_sdwa   = 6596,
    6612             :     V_CMP_LE_F32_sdwa_gfx9      = 6597,
    6613             :     V_CMP_LE_F32_sdwa_vi        = 6598,
    6614             :     V_CMP_LE_F64_e32    = 6599,
    6615             :     V_CMP_LE_F64_e32_si = 6600,
    6616             :     V_CMP_LE_F64_e32_vi = 6601,
    6617             :     V_CMP_LE_F64_e64    = 6602,
    6618             :     V_CMP_LE_F64_e64_si = 6603,
    6619             :     V_CMP_LE_F64_e64_vi = 6604,
    6620             :     V_CMP_LE_F64_sdwa   = 6605,
    6621             :     V_CMP_LE_F64_sdwa_gfx9      = 6606,
    6622             :     V_CMP_LE_F64_sdwa_vi        = 6607,
    6623             :     V_CMP_LE_I16_e32    = 6608,
    6624             :     V_CMP_LE_I16_e32_vi = 6609,
    6625             :     V_CMP_LE_I16_e64    = 6610,
    6626             :     V_CMP_LE_I16_e64_vi = 6611,
    6627             :     V_CMP_LE_I16_sdwa   = 6612,
    6628             :     V_CMP_LE_I16_sdwa_gfx9      = 6613,
    6629             :     V_CMP_LE_I16_sdwa_vi        = 6614,
    6630             :     V_CMP_LE_I32_e32    = 6615,
    6631             :     V_CMP_LE_I32_e32_si = 6616,
    6632             :     V_CMP_LE_I32_e32_vi = 6617,
    6633             :     V_CMP_LE_I32_e64    = 6618,
    6634             :     V_CMP_LE_I32_e64_si = 6619,
    6635             :     V_CMP_LE_I32_e64_vi = 6620,
    6636             :     V_CMP_LE_I32_sdwa   = 6621,
    6637             :     V_CMP_LE_I32_sdwa_gfx9      = 6622,
    6638             :     V_CMP_LE_I32_sdwa_vi        = 6623,
    6639             :     V_CMP_LE_I64_e32    = 6624,
    6640             :     V_CMP_LE_I64_e32_si = 6625,
    6641             :     V_CMP_LE_I64_e32_vi = 6626,
    6642             :     V_CMP_LE_I64_e64    = 6627,
    6643             :     V_CMP_LE_I64_e64_si = 6628,
    6644             :     V_CMP_LE_I64_e64_vi = 6629,
    6645             :     V_CMP_LE_I64_sdwa   = 6630,
    6646             :     V_CMP_LE_I64_sdwa_gfx9      = 6631,
    6647             :     V_CMP_LE_I64_sdwa_vi        = 6632,
    6648             :     V_CMP_LE_U16_e32    = 6633,
    6649             :     V_CMP_LE_U16_e32_vi = 6634,
    6650             :     V_CMP_LE_U16_e64    = 6635,
    6651             :     V_CMP_LE_U16_e64_vi = 6636,
    6652             :     V_CMP_LE_U16_sdwa   = 6637,
    6653             :     V_CMP_LE_U16_sdwa_gfx9      = 6638,
    6654             :     V_CMP_LE_U16_sdwa_vi        = 6639,
    6655             :     V_CMP_LE_U32_e32    = 6640,
    6656             :     V_CMP_LE_U32_e32_si = 6641,
    6657             :     V_CMP_LE_U32_e32_vi = 6642,
    6658             :     V_CMP_LE_U32_e64    = 6643,
    6659             :     V_CMP_LE_U32_e64_si = 6644,
    6660             :     V_CMP_LE_U32_e64_vi = 6645,
    6661             :     V_CMP_LE_U32_sdwa   = 6646,
    6662             :     V_CMP_LE_U32_sdwa_gfx9      = 6647,
    6663             :     V_CMP_LE_U32_sdwa_vi        = 6648,
    6664             :     V_CMP_LE_U64_e32    = 6649,
    6665             :     V_CMP_LE_U64_e32_si = 6650,
    6666             :     V_CMP_LE_U64_e32_vi = 6651,
    6667             :     V_CMP_LE_U64_e64    = 6652,
    6668             :     V_CMP_LE_U64_e64_si = 6653,
    6669             :     V_CMP_LE_U64_e64_vi = 6654,
    6670             :     V_CMP_LE_U64_sdwa   = 6655,
    6671             :     V_CMP_LE_U64_sdwa_gfx9      = 6656,
    6672             :     V_CMP_LE_U64_sdwa_vi        = 6657,
    6673             :     V_CMP_LG_F16_e32    = 6658,
    6674             :     V_CMP_LG_F16_e32_vi = 6659,
    6675             :     V_CMP_LG_F16_e64    = 6660,
    6676             :     V_CMP_LG_F16_e64_vi = 6661,
    6677             :     V_CMP_LG_F16_sdwa   = 6662,
    6678             :     V_CMP_LG_F16_sdwa_gfx9      = 6663,
    6679             :     V_CMP_LG_F16_sdwa_vi        = 6664,
    6680             :     V_CMP_LG_F32_e32    = 6665,
    6681             :     V_CMP_LG_F32_e32_si = 6666,
    6682             :     V_CMP_LG_F32_e32_vi = 6667,
    6683             :     V_CMP_LG_F32_e64    = 6668,
    6684             :     V_CMP_LG_F32_e64_si = 6669,
    6685             :     V_CMP_LG_F32_e64_vi = 6670,
    6686             :     V_CMP_LG_F32_sdwa   = 6671,
    6687             :     V_CMP_LG_F32_sdwa_gfx9      = 6672,
    6688             :     V_CMP_LG_F32_sdwa_vi        = 6673,
    6689             :     V_CMP_LG_F64_e32    = 6674,
    6690             :     V_CMP_LG_F64_e32_si = 6675,
    6691             :     V_CMP_LG_F64_e32_vi = 6676,
    6692             :     V_CMP_LG_F64_e64    = 6677,
    6693             :     V_CMP_LG_F64_e64_si = 6678,
    6694             :     V_CMP_LG_F64_e64_vi = 6679,
    6695             :     V_CMP_LG_F64_sdwa   = 6680,
    6696             :     V_CMP_LG_F64_sdwa_gfx9      = 6681,
    6697             :     V_CMP_LG_F64_sdwa_vi        = 6682,
    6698             :     V_CMP_LT_F16_e32    = 6683,
    6699             :     V_CMP_LT_F16_e32_vi = 6684,
    6700             :     V_CMP_LT_F16_e64    = 6685,
    6701             :     V_CMP_LT_F16_e64_vi = 6686,
    6702             :     V_CMP_LT_F16_sdwa   = 6687,
    6703             :     V_CMP_LT_F16_sdwa_gfx9      = 6688,
    6704             :     V_CMP_LT_F16_sdwa_vi        = 6689,
    6705             :     V_CMP_LT_F32_e32    = 6690,
    6706             :     V_CMP_LT_F32_e32_si = 6691,
    6707             :     V_CMP_LT_F32_e32_vi = 6692,
    6708             :     V_CMP_LT_F32_e64    = 6693,
    6709             :     V_CMP_LT_F32_e64_si = 6694,
    6710             :     V_CMP_LT_F32_e64_vi = 6695,
    6711             :     V_CMP_LT_F32_sdwa   = 6696,
    6712             :     V_CMP_LT_F32_sdwa_gfx9      = 6697,
    6713             :     V_CMP_LT_F32_sdwa_vi        = 6698,
    6714             :     V_CMP_LT_F64_e32    = 6699,
    6715             :     V_CMP_LT_F64_e32_si = 6700,
    6716             :     V_CMP_LT_F64_e32_vi = 6701,
    6717             :     V_CMP_LT_F64_e64    = 6702,
    6718             :     V_CMP_LT_F64_e64_si = 6703,
    6719             :     V_CMP_LT_F64_e64_vi = 6704,
    6720             :     V_CMP_LT_F64_sdwa   = 6705,
    6721             :     V_CMP_LT_F64_sdwa_gfx9      = 6706,
    6722             :     V_CMP_LT_F64_sdwa_vi        = 6707,
    6723             :     V_CMP_LT_I16_e32    = 6708,
    6724             :     V_CMP_LT_I16_e32_vi = 6709,
    6725             :     V_CMP_LT_I16_e64    = 6710,
    6726             :     V_CMP_LT_I16_e64_vi = 6711,
    6727             :     V_CMP_LT_I16_sdwa   = 6712,
    6728             :     V_CMP_LT_I16_sdwa_gfx9      = 6713,
    6729             :     V_CMP_LT_I16_sdwa_vi        = 6714,
    6730             :     V_CMP_LT_I32_e32    = 6715,
    6731             :     V_CMP_LT_I32_e32_si = 6716,
    6732             :     V_CMP_LT_I32_e32_vi = 6717,
    6733             :     V_CMP_LT_I32_e64    = 6718,
    6734             :     V_CMP_LT_I32_e64_si = 6719,
    6735             :     V_CMP_LT_I32_e64_vi = 6720,
    6736             :     V_CMP_LT_I32_sdwa   = 6721,
    6737             :     V_CMP_LT_I32_sdwa_gfx9      = 6722,
    6738             :     V_CMP_LT_I32_sdwa_vi        = 6723,
    6739             :     V_CMP_LT_I64_e32    = 6724,
    6740             :     V_CMP_LT_I64_e32_si = 6725,
    6741             :     V_CMP_LT_I64_e32_vi = 6726,
    6742             :     V_CMP_LT_I64_e64    = 6727,
    6743             :     V_CMP_LT_I64_e64_si = 6728,
    6744             :     V_CMP_LT_I64_e64_vi = 6729,
    6745             :     V_CMP_LT_I64_sdwa   = 6730,
    6746             :     V_CMP_LT_I64_sdwa_gfx9      = 6731,
    6747             :     V_CMP_LT_I64_sdwa_vi        = 6732,
    6748             :     V_CMP_LT_U16_e32    = 6733,
    6749             :     V_CMP_LT_U16_e32_vi = 6734,
    6750             :     V_CMP_LT_U16_e64    = 6735,
    6751             :     V_CMP_LT_U16_e64_vi = 6736,
    6752             :     V_CMP_LT_U16_sdwa   = 6737,
    6753             :     V_CMP_LT_U16_sdwa_gfx9      = 6738,
    6754             :     V_CMP_LT_U16_sdwa_vi        = 6739,
    6755             :     V_CMP_LT_U32_e32    = 6740,
    6756             :     V_CMP_LT_U32_e32_si = 6741,
    6757             :     V_CMP_LT_U32_e32_vi = 6742,
    6758             :     V_CMP_LT_U32_e64    = 6743,
    6759             :     V_CMP_LT_U32_e64_si = 6744,
    6760             :     V_CMP_LT_U32_e64_vi = 6745,
    6761             :     V_CMP_LT_U32_sdwa   = 6746,
    6762             :     V_CMP_LT_U32_sdwa_gfx9      = 6747,
    6763             :     V_CMP_LT_U32_sdwa_vi        = 6748,
    6764             :     V_CMP_LT_U64_e32    = 6749,
    6765             :     V_CMP_LT_U64_e32_si = 6750,
    6766             :     V_CMP_LT_U64_e32_vi = 6751,
    6767             :     V_CMP_LT_U64_e64    = 6752,
    6768             :     V_CMP_LT_U64_e64_si = 6753,
    6769             :     V_CMP_LT_U64_e64_vi = 6754,
    6770             :     V_CMP_LT_U64_sdwa   = 6755,
    6771             :     V_CMP_LT_U64_sdwa_gfx9      = 6756,
    6772             :     V_CMP_LT_U64_sdwa_vi        = 6757,
    6773             :     V_CMP_NEQ_F16_e32   = 6758,
    6774             :     V_CMP_NEQ_F16_e32_vi        = 6759,
    6775             :     V_CMP_NEQ_F16_e64   = 6760,
    6776             :     V_CMP_NEQ_F16_e64_vi        = 6761,
    6777             :     V_CMP_NEQ_F16_sdwa  = 6762,
    6778             :     V_CMP_NEQ_F16_sdwa_gfx9     = 6763,
    6779             :     V_CMP_NEQ_F16_sdwa_vi       = 6764,
    6780             :     V_CMP_NEQ_F32_e32   = 6765,
    6781             :     V_CMP_NEQ_F32_e32_si        = 6766,
    6782             :     V_CMP_NEQ_F32_e32_vi        = 6767,
    6783             :     V_CMP_NEQ_F32_e64   = 6768,
    6784             :     V_CMP_NEQ_F32_e64_si        = 6769,
    6785             :     V_CMP_NEQ_F32_e64_vi        = 6770,
    6786             :     V_CMP_NEQ_F32_sdwa  = 6771,
    6787             :     V_CMP_NEQ_F32_sdwa_gfx9     = 6772,
    6788             :     V_CMP_NEQ_F32_sdwa_vi       = 6773,
    6789             :     V_CMP_NEQ_F64_e32   = 6774,
    6790             :     V_CMP_NEQ_F64_e32_si        = 6775,
    6791             :     V_CMP_NEQ_F64_e32_vi        = 6776,
    6792             :     V_CMP_NEQ_F64_e64   = 6777,
    6793             :     V_CMP_NEQ_F64_e64_si        = 6778,
    6794             :     V_CMP_NEQ_F64_e64_vi        = 6779,
    6795             :     V_CMP_NEQ_F64_sdwa  = 6780,
    6796             :     V_CMP_NEQ_F64_sdwa_gfx9     = 6781,
    6797             :     V_CMP_NEQ_F64_sdwa_vi       = 6782,
    6798             :     V_CMP_NE_I16_e32    = 6783,
    6799             :     V_CMP_NE_I16_e32_vi = 6784,
    6800             :     V_CMP_NE_I16_e64    = 6785,
    6801             :     V_CMP_NE_I16_e64_vi = 6786,
    6802             :     V_CMP_NE_I16_sdwa   = 6787,
    6803             :     V_CMP_NE_I16_sdwa_gfx9      = 6788,
    6804             :     V_CMP_NE_I16_sdwa_vi        = 6789,
    6805             :     V_CMP_NE_I32_e32    = 6790,
    6806             :     V_CMP_NE_I32_e32_si = 6791,
    6807             :     V_CMP_NE_I32_e32_vi = 6792,
    6808             :     V_CMP_NE_I32_e64    = 6793,
    6809             :     V_CMP_NE_I32_e64_si = 6794,
    6810             :     V_CMP_NE_I32_e64_vi = 6795,
    6811             :     V_CMP_NE_I32_sdwa   = 6796,
    6812             :     V_CMP_NE_I32_sdwa_gfx9      = 6797,
    6813             :     V_CMP_NE_I32_sdwa_vi        = 6798,
    6814             :     V_CMP_NE_I64_e32    = 6799,
    6815             :     V_CMP_NE_I64_e32_si = 6800,
    6816             :     V_CMP_NE_I64_e32_vi = 6801,
    6817             :     V_CMP_NE_I64_e64    = 6802,
    6818             :     V_CMP_NE_I64_e64_si = 6803,
    6819             :     V_CMP_NE_I64_e64_vi = 6804,
    6820             :     V_CMP_NE_I64_sdwa   = 6805,
    6821             :     V_CMP_NE_I64_sdwa_gfx9      = 6806,
    6822             :     V_CMP_NE_I64_sdwa_vi        = 6807,
    6823             :     V_CMP_NE_U16_e32    = 6808,
    6824             :     V_CMP_NE_U16_e32_vi = 6809,
    6825             :     V_CMP_NE_U16_e64    = 6810,
    6826             :     V_CMP_NE_U16_e64_vi = 6811,
    6827             :     V_CMP_NE_U16_sdwa   = 6812,
    6828             :     V_CMP_NE_U16_sdwa_gfx9      = 6813,
    6829             :     V_CMP_NE_U16_sdwa_vi        = 6814,
    6830             :     V_CMP_NE_U32_e32    = 6815,
    6831             :     V_CMP_NE_U32_e32_si = 6816,
    6832             :     V_CMP_NE_U32_e32_vi = 6817,
    6833             :     V_CMP_NE_U32_e64    = 6818,
    6834             :     V_CMP_NE_U32_e64_si = 6819,
    6835             :     V_CMP_NE_U32_e64_vi = 6820,
    6836             :     V_CMP_NE_U32_sdwa   = 6821,
    6837             :     V_CMP_NE_U32_sdwa_gfx9      = 6822,
    6838             :     V_CMP_NE_U32_sdwa_vi        = 6823,
    6839             :     V_CMP_NE_U64_e32    = 6824,
    6840             :     V_CMP_NE_U64_e32_si = 6825,
    6841             :     V_CMP_NE_U64_e32_vi = 6826,
    6842             :     V_CMP_NE_U64_e64    = 6827,
    6843             :     V_CMP_NE_U64_e64_si = 6828,
    6844             :     V_CMP_NE_U64_e64_vi = 6829,
    6845             :     V_CMP_NE_U64_sdwa   = 6830,
    6846             :     V_CMP_NE_U64_sdwa_gfx9      = 6831,
    6847             :     V_CMP_NE_U64_sdwa_vi        = 6832,
    6848             :     V_CMP_NGE_F16_e32   = 6833,
    6849             :     V_CMP_NGE_F16_e32_vi        = 6834,
    6850             :     V_CMP_NGE_F16_e64   = 6835,
    6851             :     V_CMP_NGE_F16_e64_vi        = 6836,
    6852             :     V_CMP_NGE_F16_sdwa  = 6837,
    6853             :     V_CMP_NGE_F16_sdwa_gfx9     = 6838,
    6854             :     V_CMP_NGE_F16_sdwa_vi       = 6839,
    6855             :     V_CMP_NGE_F32_e32   = 6840,
    6856             :     V_CMP_NGE_F32_e32_si        = 6841,
    6857             :     V_CMP_NGE_F32_e32_vi        = 6842,
    6858             :     V_CMP_NGE_F32_e64   = 6843,
    6859             :     V_CMP_NGE_F32_e64_si        = 6844,
    6860             :     V_CMP_NGE_F32_e64_vi        = 6845,
    6861             :     V_CMP_NGE_F32_sdwa  = 6846,
    6862             :     V_CMP_NGE_F32_sdwa_gfx9     = 6847,
    6863             :     V_CMP_NGE_F32_sdwa_vi       = 6848,
    6864             :     V_CMP_NGE_F64_e32   = 6849,
    6865             :     V_CMP_NGE_F64_e32_si        = 6850,
    6866             :     V_CMP_NGE_F64_e32_vi        = 6851,
    6867             :     V_CMP_NGE_F64_e64   = 6852,
    6868             :     V_CMP_NGE_F64_e64_si        = 6853,
    6869             :     V_CMP_NGE_F64_e64_vi        = 6854,
    6870             :     V_CMP_NGE_F64_sdwa  = 6855,
    6871             :     V_CMP_NGE_F64_sdwa_gfx9     = 6856,
    6872             :     V_CMP_NGE_F64_sdwa_vi       = 6857,
    6873             :     V_CMP_NGT_F16_e32   = 6858,
    6874             :     V_CMP_NGT_F16_e32_vi        = 6859,
    6875             :     V_CMP_NGT_F16_e64   = 6860,
    6876             :     V_CMP_NGT_F16_e64_vi        = 6861,
    6877             :     V_CMP_NGT_F16_sdwa  = 6862,
    6878             :     V_CMP_NGT_F16_sdwa_gfx9     = 6863,
    6879             :     V_CMP_NGT_F16_sdwa_vi       = 6864,
    6880             :     V_CMP_NGT_F32_e32   = 6865,
    6881             :     V_CMP_NGT_F32_e32_si        = 6866,
    6882             :     V_CMP_NGT_F32_e32_vi        = 6867,
    6883             :     V_CMP_NGT_F32_e64   = 6868,
    6884             :     V_CMP_NGT_F32_e64_si        = 6869,
    6885             :     V_CMP_NGT_F32_e64_vi        = 6870,
    6886             :     V_CMP_NGT_F32_sdwa  = 6871,
    6887             :     V_CMP_NGT_F32_sdwa_gfx9     = 6872,
    6888             :     V_CMP_NGT_F32_sdwa_vi       = 6873,
    6889             :     V_CMP_NGT_F64_e32   = 6874,
    6890             :     V_CMP_NGT_F64_e32_si        = 6875,
    6891             :     V_CMP_NGT_F64_e32_vi        = 6876,
    6892             :     V_CMP_NGT_F64_e64   = 6877,
    6893             :     V_CMP_NGT_F64_e64_si        = 6878,
    6894             :     V_CMP_NGT_F64_e64_vi        = 6879,
    6895             :     V_CMP_NGT_F64_sdwa  = 6880,
    6896             :     V_CMP_NGT_F64_sdwa_gfx9     = 6881,
    6897             :     V_CMP_NGT_F64_sdwa_vi       = 6882,
    6898             :     V_CMP_NLE_F16_e32   = 6883,
    6899             :     V_CMP_NLE_F16_e32_vi        = 6884,
    6900             :     V_CMP_NLE_F16_e64   = 6885,
    6901             :     V_CMP_NLE_F16_e64_vi        = 6886,
    6902             :     V_CMP_NLE_F16_sdwa  = 6887,
    6903             :     V_CMP_NLE_F16_sdwa_gfx9     = 6888,
    6904             :     V_CMP_NLE_F16_sdwa_vi       = 6889,
    6905             :     V_CMP_NLE_F32_e32   = 6890,
    6906             :     V_CMP_NLE_F32_e32_si        = 6891,
    6907             :     V_CMP_NLE_F32_e32_vi        = 6892,
    6908             :     V_CMP_NLE_F32_e64   = 6893,
    6909             :     V_CMP_NLE_F32_e64_si        = 6894,
    6910             :     V_CMP_NLE_F32_e64_vi        = 6895,
    6911             :     V_CMP_NLE_F32_sdwa  = 6896,
    6912             :     V_CMP_NLE_F32_sdwa_gfx9     = 6897,
    6913             :     V_CMP_NLE_F32_sdwa_vi       = 6898,
    6914             :     V_CMP_NLE_F64_e32   = 6899,
    6915             :     V_CMP_NLE_F64_e32_si        = 6900,
    6916             :     V_CMP_NLE_F64_e32_vi        = 6901,
    6917             :     V_CMP_NLE_F64_e64   = 6902,
    6918             :     V_CMP_NLE_F64_e64_si        = 6903,
    6919             :     V_CMP_NLE_F64_e64_vi        = 6904,
    6920             :     V_CMP_NLE_F64_sdwa  = 6905,
    6921             :     V_CMP_NLE_F64_sdwa_gfx9     = 6906,
    6922             :     V_CMP_NLE_F64_sdwa_vi       = 6907,
    6923             :     V_CMP_NLG_F16_e32   = 6908,
    6924             :     V_CMP_NLG_F16_e32_vi        = 6909,
    6925             :     V_CMP_NLG_F16_e64   = 6910,
    6926             :     V_CMP_NLG_F16_e64_vi        = 6911,
    6927             :     V_CMP_NLG_F16_sdwa  = 6912,
    6928             :     V_CMP_NLG_F16_sdwa_gfx9     = 6913,
    6929             :     V_CMP_NLG_F16_sdwa_vi       = 6914,
    6930             :     V_CMP_NLG_F32_e32   = 6915,
    6931             :     V_CMP_NLG_F32_e32_si        = 6916,
    6932             :     V_CMP_NLG_F32_e32_vi        = 6917,
    6933             :     V_CMP_NLG_F32_e64   = 6918,
    6934             :     V_CMP_NLG_F32_e64_si        = 6919,
    6935             :     V_CMP_NLG_F32_e64_vi        = 6920,
    6936             :     V_CMP_NLG_F32_sdwa  = 6921,
    6937             :     V_CMP_NLG_F32_sdwa_gfx9     = 6922,
    6938             :     V_CMP_NLG_F32_sdwa_vi       = 6923,
    6939             :     V_CMP_NLG_F64_e32   = 6924,
    6940             :     V_CMP_NLG_F64_e32_si        = 6925,
    6941             :     V_CMP_NLG_F64_e32_vi        = 6926,
    6942             :     V_CMP_NLG_F64_e64   = 6927,
    6943             :     V_CMP_NLG_F64_e64_si        = 6928,
    6944             :     V_CMP_NLG_F64_e64_vi        = 6929,
    6945             :     V_CMP_NLG_F64_sdwa  = 6930,
    6946             :     V_CMP_NLG_F64_sdwa_gfx9     = 6931,
    6947             :     V_CMP_NLG_F64_sdwa_vi       = 6932,
    6948             :     V_CMP_NLT_F16_e32   = 6933,
    6949             :     V_CMP_NLT_F16_e32_vi        = 6934,
    6950             :     V_CMP_NLT_F16_e64   = 6935,
    6951             :     V_CMP_NLT_F16_e64_vi        = 6936,
    6952             :     V_CMP_NLT_F16_sdwa  = 6937,
    6953             :     V_CMP_NLT_F16_sdwa_gfx9     = 6938,
    6954             :     V_CMP_NLT_F16_sdwa_vi       = 6939,
    6955             :     V_CMP_NLT_F32_e32   = 6940,
    6956             :     V_CMP_NLT_F32_e32_si        = 6941,
    6957             :     V_CMP_NLT_F32_e32_vi        = 6942,
    6958             :     V_CMP_NLT_F32_e64   = 6943,
    6959             :     V_CMP_NLT_F32_e64_si        = 6944,
    6960             :     V_CMP_NLT_F32_e64_vi        = 6945,
    6961             :     V_CMP_NLT_F32_sdwa  = 6946,
    6962             :     V_CMP_NLT_F32_sdwa_gfx9     = 6947,
    6963             :     V_CMP_NLT_F32_sdwa_vi       = 6948,
    6964             :     V_CMP_NLT_F64_e32   = 6949,
    6965             :     V_CMP_NLT_F64_e32_si        = 6950,
    6966             :     V_CMP_NLT_F64_e32_vi        = 6951,
    6967             :     V_CMP_NLT_F64_e64   = 6952,
    6968             :     V_CMP_NLT_F64_e64_si        = 6953,
    6969             :     V_CMP_NLT_F64_e64_vi        = 6954,
    6970             :     V_CMP_NLT_F64_sdwa  = 6955,
    6971             :     V_CMP_NLT_F64_sdwa_gfx9     = 6956,
    6972             :     V_CMP_NLT_F64_sdwa_vi       = 6957,
    6973             :     V_CMP_O_F16_e32     = 6958,
    6974             :     V_CMP_O_F16_e32_vi  = 6959,
    6975             :     V_CMP_O_F16_e64     = 6960,
    6976             :     V_CMP_O_F16_e64_vi  = 6961,
    6977             :     V_CMP_O_F16_sdwa    = 6962,
    6978             :     V_CMP_O_F16_sdwa_gfx9       = 6963,
    6979             :     V_CMP_O_F16_sdwa_vi = 6964,
    6980             :     V_CMP_O_F32_e32     = 6965,
    6981             :     V_CMP_O_F32_e32_si  = 6966,
    6982             :     V_CMP_O_F32_e32_vi  = 6967,
    6983             :     V_CMP_O_F32_e64     = 6968,
    6984             :     V_CMP_O_F32_e64_si  = 6969,
    6985             :     V_CMP_O_F32_e64_vi  = 6970,
    6986             :     V_CMP_O_F32_sdwa    = 6971,
    6987             :     V_CMP_O_F32_sdwa_gfx9       = 6972,
    6988             :     V_CMP_O_F32_sdwa_vi = 6973,
    6989             :     V_CMP_O_F64_e32     = 6974,
    6990             :     V_CMP_O_F64_e32_si  = 6975,
    6991             :     V_CMP_O_F64_e32_vi  = 6976,
    6992             :     V_CMP_O_F64_e64     = 6977,
    6993             :     V_CMP_O_F64_e64_si  = 6978,
    6994             :     V_CMP_O_F64_e64_vi  = 6979,
    6995             :     V_CMP_O_F64_sdwa    = 6980,
    6996             :     V_CMP_O_F64_sdwa_gfx9       = 6981,
    6997             :     V_CMP_O_F64_sdwa_vi = 6982,
    6998             :     V_CMP_TRU_F16_e32   = 6983,
    6999             :     V_CMP_TRU_F16_e32_vi        = 6984,
    7000             :     V_CMP_TRU_F16_e64   = 6985,
    7001             :     V_CMP_TRU_F16_e64_vi        = 6986,
    7002             :     V_CMP_TRU_F16_sdwa  = 6987,
    7003             :     V_CMP_TRU_F16_sdwa_gfx9     = 6988,
    7004             :     V_CMP_TRU_F16_sdwa_vi       = 6989,
    7005             :     V_CMP_TRU_F32_e32   = 6990,
    7006             :     V_CMP_TRU_F32_e32_si        = 6991,
    7007             :     V_CMP_TRU_F32_e32_vi        = 6992,
    7008             :     V_CMP_TRU_F32_e64   = 6993,
    7009             :     V_CMP_TRU_F32_e64_si        = 6994,
    7010             :     V_CMP_TRU_F32_e64_vi        = 6995,
    7011             :     V_CMP_TRU_F32_sdwa  = 6996,
    7012             :     V_CMP_TRU_F32_sdwa_gfx9     = 6997,
    7013             :     V_CMP_TRU_F32_sdwa_vi       = 6998,
    7014             :     V_CMP_TRU_F64_e32   = 6999,
    7015             :     V_CMP_TRU_F64_e32_si        = 7000,
    7016             :     V_CMP_TRU_F64_e32_vi        = 7001,
    7017             :     V_CMP_TRU_F64_e64   = 7002,
    7018             :     V_CMP_TRU_F64_e64_si        = 7003,
    7019             :     V_CMP_TRU_F64_e64_vi        = 7004,
    7020             :     V_CMP_TRU_F64_sdwa  = 7005,
    7021             :     V_CMP_TRU_F64_sdwa_gfx9     = 7006,
    7022             :     V_CMP_TRU_F64_sdwa_vi       = 7007,
    7023             :     V_CMP_T_I16_e32     = 7008,
    7024             :     V_CMP_T_I16_e32_vi  = 7009,
    7025             :     V_CMP_T_I16_e64     = 7010,
    7026             :     V_CMP_T_I16_e64_vi  = 7011,
    7027             :     V_CMP_T_I16_sdwa    = 7012,
    7028             :     V_CMP_T_I16_sdwa_gfx9       = 7013,
    7029             :     V_CMP_T_I16_sdwa_vi = 7014,
    7030             :     V_CMP_T_I32_e32     = 7015,
    7031             :     V_CMP_T_I32_e32_si  = 7016,
    7032             :     V_CMP_T_I32_e32_vi  = 7017,
    7033             :     V_CMP_T_I32_e64     = 7018,
    7034             :     V_CMP_T_I32_e64_si  = 7019,
    7035             :     V_CMP_T_I32_e64_vi  = 7020,
    7036             :     V_CMP_T_I32_sdwa    = 7021,
    7037             :     V_CMP_T_I32_sdwa_gfx9       = 7022,
    7038             :     V_CMP_T_I32_sdwa_vi = 7023,
    7039             :     V_CMP_T_I64_e32     = 7024,
    7040             :     V_CMP_T_I64_e32_si  = 7025,
    7041             :     V_CMP_T_I64_e32_vi  = 7026,
    7042             :     V_CMP_T_I64_e64     = 7027,
    7043             :     V_CMP_T_I64_e64_si  = 7028,
    7044             :     V_CMP_T_I64_e64_vi  = 7029,
    7045             :     V_CMP_T_I64_sdwa    = 7030,
    7046             :     V_CMP_T_I64_sdwa_gfx9       = 7031,
    7047             :     V_CMP_T_I64_sdwa_vi = 7032,
    7048             :     V_CMP_T_U16_e32     = 7033,
    7049             :     V_CMP_T_U16_e32_vi  = 7034,
    7050             :     V_CMP_T_U16_e64     = 7035,
    7051             :     V_CMP_T_U16_e64_vi  = 7036,
    7052             :     V_CMP_T_U16_sdwa    = 7037,
    7053             :     V_CMP_T_U16_sdwa_gfx9       = 7038,
    7054             :     V_CMP_T_U16_sdwa_vi = 7039,
    7055             :     V_CMP_T_U32_e32     = 7040,
    7056             :     V_CMP_T_U32_e32_si  = 7041,
    7057             :     V_CMP_T_U32_e32_vi  = 7042,
    7058             :     V_CMP_T_U32_e64     = 7043,
    7059             :     V_CMP_T_U32_e64_si  = 7044,
    7060             :     V_CMP_T_U32_e64_vi  = 7045,
    7061             :     V_CMP_T_U32_sdwa    = 7046,
    7062             :     V_CMP_T_U32_sdwa_gfx9       = 7047,
    7063             :     V_CMP_T_U32_sdwa_vi = 7048,
    7064             :     V_CMP_T_U64_e32     = 7049,
    7065             :     V_CMP_T_U64_e32_si  = 7050,
    7066             :     V_CMP_T_U64_e32_vi  = 7051,
    7067             :     V_CMP_T_U64_e64     = 7052,
    7068             :     V_CMP_T_U64_e64_si  = 7053,
    7069             :     V_CMP_T_U64_e64_vi  = 7054,
    7070             :     V_CMP_T_U64_sdwa    = 7055,
    7071             :     V_CMP_T_U64_sdwa_gfx9       = 7056,
    7072             :     V_CMP_T_U64_sdwa_vi = 7057,
    7073             :     V_CMP_U_F16_e32     = 7058,
    7074             :     V_CMP_U_F16_e32_vi  = 7059,
    7075             :     V_CMP_U_F16_e64     = 7060,
    7076             :     V_CMP_U_F16_e64_vi  = 7061,
    7077             :     V_CMP_U_F16_sdwa    = 7062,
    7078             :     V_CMP_U_F16_sdwa_gfx9       = 7063,
    7079             :     V_CMP_U_F16_sdwa_vi = 7064,
    7080             :     V_CMP_U_F32_e32     = 7065,
    7081             :     V_CMP_U_F32_e32_si  = 7066,
    7082             :     V_CMP_U_F32_e32_vi  = 7067,
    7083             :     V_CMP_U_F32_e64     = 7068,
    7084             :     V_CMP_U_F32_e64_si  = 7069,
    7085             :     V_CMP_U_F32_e64_vi  = 7070,
    7086             :     V_CMP_U_F32_sdwa    = 7071,
    7087             :     V_CMP_U_F32_sdwa_gfx9       = 7072,
    7088             :     V_CMP_U_F32_sdwa_vi = 7073,
    7089             :     V_CMP_U_F64_e32     = 7074,
    7090             :     V_CMP_U_F64_e32_si  = 7075,
    7091             :     V_CMP_U_F64_e32_vi  = 7076,
    7092             :     V_CMP_U_F64_e64     = 7077,
    7093             :     V_CMP_U_F64_e64_si  = 7078,
    7094             :     V_CMP_U_F64_e64_vi  = 7079,
    7095             :     V_CMP_U_F64_sdwa    = 7080,
    7096             :     V_CMP_U_F64_sdwa_gfx9       = 7081,
    7097             :     V_CMP_U_F64_sdwa_vi = 7082,
    7098             :     V_CNDMASK_B32_e32   = 7083,
    7099             :     V_CNDMASK_B32_e32_si        = 7084,
    7100             :     V_CNDMASK_B32_e32_vi        = 7085,
    7101             :     V_CNDMASK_B32_e64   = 7086,
    7102             :     V_CNDMASK_B32_e64_si        = 7087,
    7103             :     V_CNDMASK_B32_e64_vi        = 7088,
    7104             :     V_CNDMASK_B64_PSEUDO        = 7089,
    7105             :     V_COS_F16_dpp       = 7090,
    7106             :     V_COS_F16_e32       = 7091,
    7107             :     V_COS_F16_e32_vi    = 7092,
    7108             :     V_COS_F16_e64       = 7093,
    7109             :     V_COS_F16_e64_vi    = 7094,
    7110             :     V_COS_F16_sdwa      = 7095,
    7111             :     V_COS_F16_sdwa_gfx9 = 7096,
    7112             :     V_COS_F16_sdwa_vi   = 7097,
    7113             :     V_COS_F32_dpp       = 7098,
    7114             :     V_COS_F32_e32       = 7099,
    7115             :     V_COS_F32_e32_si    = 7100,
    7116             :     V_COS_F32_e32_vi    = 7101,
    7117             :     V_COS_F32_e64       = 7102,
    7118             :     V_COS_F32_e64_si    = 7103,
    7119             :     V_COS_F32_e64_vi    = 7104,
    7120             :     V_COS_F32_sdwa      = 7105,
    7121             :     V_COS_F32_sdwa_gfx9 = 7106,
    7122             :     V_COS_F32_sdwa_vi   = 7107,
    7123             :     V_CUBEID_F32        = 7108,
    7124             :     V_CUBEID_F32_si     = 7109,
    7125             :     V_CUBEID_F32_vi     = 7110,
    7126             :     V_CUBEMA_F32        = 7111,
    7127             :     V_CUBEMA_F32_si     = 7112,
    7128             :     V_CUBEMA_F32_vi     = 7113,
    7129             :     V_CUBESC_F32        = 7114,
    7130             :     V_CUBESC_F32_si     = 7115,
    7131             :     V_CUBESC_F32_vi     = 7116,
    7132             :     V_CUBETC_F32        = 7117,
    7133             :     V_CUBETC_F32_si     = 7118,
    7134             :     V_CUBETC_F32_vi     = 7119,
    7135             :     V_CVT_F16_F32_dpp   = 7120,
    7136             :     V_CVT_F16_F32_e32   = 7121,
    7137             :     V_CVT_F16_F32_e32_si        = 7122,
    7138             :     V_CVT_F16_F32_e32_vi        = 7123,
    7139             :     V_CVT_F16_F32_e64   = 7124,
    7140             :     V_CVT_F16_F32_e64_si        = 7125,
    7141             :     V_CVT_F16_F32_e64_vi        = 7126,
    7142             :     V_CVT_F16_F32_sdwa  = 7127,
    7143             :     V_CVT_F16_F32_sdwa_gfx9     = 7128,
    7144             :     V_CVT_F16_F32_sdwa_vi       = 7129,
    7145             :     V_CVT_F16_I16_dpp   = 7130,
    7146             :     V_CVT_F16_I16_e32   = 7131,
    7147             :     V_CVT_F16_I16_e32_vi        = 7132,
    7148             :     V_CVT_F16_I16_e64   = 7133,
    7149             :     V_CVT_F16_I16_e64_vi        = 7134,
    7150             :     V_CVT_F16_I16_sdwa  = 7135,
    7151             :     V_CVT_F16_I16_sdwa_gfx9     = 7136,
    7152             :     V_CVT_F16_I16_sdwa_vi       = 7137,
    7153             :     V_CVT_F16_U16_dpp   = 7138,
    7154             :     V_CVT_F16_U16_e32   = 7139,
    7155             :     V_CVT_F16_U16_e32_vi        = 7140,
    7156             :     V_CVT_F16_U16_e64   = 7141,
    7157             :     V_CVT_F16_U16_e64_vi        = 7142,
    7158             :     V_CVT_F16_U16_sdwa  = 7143,
    7159             :     V_CVT_F16_U16_sdwa_gfx9     = 7144,
    7160             :     V_CVT_F16_U16_sdwa_vi       = 7145,
    7161             :     V_CVT_F32_F16_dpp   = 7146,
    7162             :     V_CVT_F32_F16_e32   = 7147,
    7163             :     V_CVT_F32_F16_e32_si        = 7148,
    7164             :     V_CVT_F32_F16_e32_vi        = 7149,
    7165             :     V_CVT_F32_F16_e64   = 7150,
    7166             :     V_CVT_F32_F16_e64_si        = 7151,
    7167             :     V_CVT_F32_F16_e64_vi        = 7152,
    7168             :     V_CVT_F32_F16_sdwa  = 7153,
    7169             :     V_CVT_F32_F16_sdwa_gfx9     = 7154,
    7170             :     V_CVT_F32_F16_sdwa_vi       = 7155,
    7171             :     V_CVT_F32_F64_dpp   = 7156,
    7172             :     V_CVT_F32_F64_e32   = 7157,
    7173             :     V_CVT_F32_F64_e32_si        = 7158,
    7174             :     V_CVT_F32_F64_e32_vi        = 7159,
    7175             :     V_CVT_F32_F64_e64   = 7160,
    7176             :     V_CVT_F32_F64_e64_si        = 7161,
    7177             :     V_CVT_F32_F64_e64_vi        = 7162,
    7178             :     V_CVT_F32_F64_sdwa  = 7163,
    7179             :     V_CVT_F32_F64_sdwa_gfx9     = 7164,
    7180             :     V_CVT_F32_F64_sdwa_vi       = 7165,
    7181             :     V_CVT_F32_I32_dpp   = 7166,
    7182             :     V_CVT_F32_I32_e32   = 7167,
    7183             :     V_CVT_F32_I32_e32_si        = 7168,
    7184             :     V_CVT_F32_I32_e32_vi        = 7169,
    7185             :     V_CVT_F32_I32_e64   = 7170,
    7186             :     V_CVT_F32_I32_e64_si        = 7171,
    7187             :     V_CVT_F32_I32_e64_vi        = 7172,
    7188             :     V_CVT_F32_I32_sdwa  = 7173,
    7189             :     V_CVT_F32_I32_sdwa_gfx9     = 7174,
    7190             :     V_CVT_F32_I32_sdwa_vi       = 7175,
    7191             :     V_CVT_F32_U32_dpp   = 7176,
    7192             :     V_CVT_F32_U32_e32   = 7177,
    7193             :     V_CVT_F32_U32_e32_si        = 7178,
    7194             :     V_CVT_F32_U32_e32_vi        = 7179,
    7195             :     V_CVT_F32_U32_e64   = 7180,
    7196             :     V_CVT_F32_U32_e64_si        = 7181,
    7197             :     V_CVT_F32_U32_e64_vi        = 7182,
    7198             :     V_CVT_F32_U32_sdwa  = 7183,
    7199             :     V_CVT_F32_U32_sdwa_gfx9     = 7184,
    7200             :     V_CVT_F32_U32_sdwa_vi       = 7185,
    7201             :     V_CVT_F32_UBYTE0_dpp        = 7186,
    7202             :     V_CVT_F32_UBYTE0_e32        = 7187,
    7203             :     V_CVT_F32_UBYTE0_e32_si     = 7188,
    7204             :     V_CVT_F32_UBYTE0_e32_vi     = 7189,
    7205             :     V_CVT_F32_UBYTE0_e64        = 7190,
    7206             :     V_CVT_F32_UBYTE0_e64_si     = 7191,
    7207             :     V_CVT_F32_UBYTE0_e64_vi     = 7192,
    7208             :     V_CVT_F32_UBYTE0_sdwa       = 7193,
    7209             :     V_CVT_F32_UBYTE0_sdwa_gfx9  = 7194,
    7210             :     V_CVT_F32_UBYTE0_sdwa_vi    = 7195,
    7211             :     V_CVT_F32_UBYTE1_dpp        = 7196,
    7212             :     V_CVT_F32_UBYTE1_e32        = 7197,
    7213             :     V_CVT_F32_UBYTE1_e32_si     = 7198,
    7214             :     V_CVT_F32_UBYTE1_e32_vi     = 7199,
    7215             :     V_CVT_F32_UBYTE1_e64        = 7200,
    7216             :     V_CVT_F32_UBYTE1_e64_si     = 7201,
    7217             :     V_CVT_F32_UBYTE1_e64_vi     = 7202,
    7218             :     V_CVT_F32_UBYTE1_sdwa       = 7203,
    7219             :     V_CVT_F32_UBYTE1_sdwa_gfx9  = 7204,
    7220             :     V_CVT_F32_UBYTE1_sdwa_vi    = 7205,
    7221             :     V_CVT_F32_UBYTE2_dpp        = 7206,
    7222             :     V_CVT_F32_UBYTE2_e32        = 7207,
    7223             :     V_CVT_F32_UBYTE2_e32_si     = 7208,
    7224             :     V_CVT_F32_UBYTE2_e32_vi     = 7209,
    7225             :     V_CVT_F32_UBYTE2_e64        = 7210,
    7226             :     V_CVT_F32_UBYTE2_e64_si     = 7211,
    7227             :     V_CVT_F32_UBYTE2_e64_vi     = 7212,
    7228             :     V_CVT_F32_UBYTE2_sdwa       = 7213,
    7229             :     V_CVT_F32_UBYTE2_sdwa_gfx9  = 7214,
    7230             :     V_CVT_F32_UBYTE2_sdwa_vi    = 7215,
    7231             :     V_CVT_F32_UBYTE3_dpp        = 7216,
    7232             :     V_CVT_F32_UBYTE3_e32        = 7217,
    7233             :     V_CVT_F32_UBYTE3_e32_si     = 7218,
    7234             :     V_CVT_F32_UBYTE3_e32_vi     = 7219,
    7235             :     V_CVT_F32_UBYTE3_e64        = 7220,
    7236             :     V_CVT_F32_UBYTE3_e64_si     = 7221,
    7237             :     V_CVT_F32_UBYTE3_e64_vi     = 7222,
    7238             :     V_CVT_F32_UBYTE3_sdwa       = 7223,
    7239             :     V_CVT_F32_UBYTE3_sdwa_gfx9  = 7224,
    7240             :     V_CVT_F32_UBYTE3_sdwa_vi    = 7225,
    7241             :     V_CVT_F64_F32_dpp   = 7226,
    7242             :     V_CVT_F64_F32_e32   = 7227,
    7243             :     V_CVT_F64_F32_e32_si        = 7228,
    7244             :     V_CVT_F64_F32_e32_vi        = 7229,
    7245             :     V_CVT_F64_F32_e64   = 7230,
    7246             :     V_CVT_F64_F32_e64_si        = 7231,
    7247             :     V_CVT_F64_F32_e64_vi        = 7232,
    7248             :     V_CVT_F64_F32_sdwa  = 7233,
    7249             :     V_CVT_F64_F32_sdwa_gfx9     = 7234,
    7250             :     V_CVT_F64_F32_sdwa_vi       = 7235,
    7251             :     V_CVT_F64_I32_dpp   = 7236,
    7252             :     V_CVT_F64_I32_e32   = 7237,
    7253             :     V_CVT_F64_I32_e32_si        = 7238,
    7254             :     V_CVT_F64_I32_e32_vi        = 7239,
    7255             :     V_CVT_F64_I32_e64   = 7240,
    7256             :     V_CVT_F64_I32_e64_si        = 7241,
    7257             :     V_CVT_F64_I32_e64_vi        = 7242,
    7258             :     V_CVT_F64_I32_sdwa  = 7243,
    7259             :     V_CVT_F64_I32_sdwa_gfx9     = 7244,
    7260             :     V_CVT_F64_I32_sdwa_vi       = 7245,
    7261             :     V_CVT_F64_U32_dpp   = 7246,
    7262             :     V_CVT_F64_U32_e32   = 7247,
    7263             :     V_CVT_F64_U32_e32_si        = 7248,
    7264             :     V_CVT_F64_U32_e32_vi        = 7249,
    7265             :     V_CVT_F64_U32_e64   = 7250,
    7266             :     V_CVT_F64_U32_e64_si        = 7251,
    7267             :     V_CVT_F64_U32_e64_vi        = 7252,
    7268             :     V_CVT_F64_U32_sdwa  = 7253,
    7269             :     V_CVT_F64_U32_sdwa_gfx9     = 7254,
    7270             :     V_CVT_F64_U32_sdwa_vi       = 7255,
    7271             :     V_CVT_FLR_I32_F32_dpp       = 7256,
    7272             :     V_CVT_FLR_I32_F32_e32       = 7257,
    7273             :     V_CVT_FLR_I32_F32_e32_si    = 7258,
    7274             :     V_CVT_FLR_I32_F32_e32_vi    = 7259,
    7275             :     V_CVT_FLR_I32_F32_e64       = 7260,
    7276             :     V_CVT_FLR_I32_F32_e64_si    = 7261,
    7277             :     V_CVT_FLR_I32_F32_e64_vi    = 7262,
    7278             :     V_CVT_FLR_I32_F32_sdwa      = 7263,
    7279             :     V_CVT_FLR_I32_F32_sdwa_gfx9 = 7264,
    7280             :     V_CVT_FLR_I32_F32_sdwa_vi   = 7265,
    7281             :     V_CVT_I16_F16_dpp   = 7266,
    7282             :     V_CVT_I16_F16_e32   = 7267,
    7283             :     V_CVT_I16_F16_e32_vi        = 7268,
    7284             :     V_CVT_I16_F16_e64   = 7269,
    7285             :     V_CVT_I16_F16_e64_vi        = 7270,
    7286             :     V_CVT_I16_F16_sdwa  = 7271,
    7287             :     V_CVT_I16_F16_sdwa_gfx9     = 7272,
    7288             :     V_CVT_I16_F16_sdwa_vi       = 7273,
    7289             :     V_CVT_I32_F32_dpp   = 7274,
    7290             :     V_CVT_I32_F32_e32   = 7275,
    7291             :     V_CVT_I32_F32_e32_si        = 7276,
    7292             :     V_CVT_I32_F32_e32_vi        = 7277,
    7293             :     V_CVT_I32_F32_e64   = 7278,
    7294             :     V_CVT_I32_F32_e64_si        = 7279,
    7295             :     V_CVT_I32_F32_e64_vi        = 7280,
    7296             :     V_CVT_I32_F32_sdwa  = 7281,
    7297             :     V_CVT_I32_F32_sdwa_gfx9     = 7282,
    7298             :     V_CVT_I32_F32_sdwa_vi       = 7283,
    7299             :     V_CVT_I32_F64_dpp   = 7284,
    7300             :     V_CVT_I32_F64_e32   = 7285,
    7301             :     V_CVT_I32_F64_e32_si        = 7286,
    7302             :     V_CVT_I32_F64_e32_vi        = 7287,
    7303             :     V_CVT_I32_F64_e64   = 7288,
    7304             :     V_CVT_I32_F64_e64_si        = 7289,
    7305             :     V_CVT_I32_F64_e64_vi        = 7290,
    7306             :     V_CVT_I32_F64_sdwa  = 7291,
    7307             :     V_CVT_I32_F64_sdwa_gfx9     = 7292,
    7308             :     V_CVT_I32_F64_sdwa_vi       = 7293,
    7309             :     V_CVT_OFF_F32_I4_dpp        = 7294,
    7310             :     V_CVT_OFF_F32_I4_e32        = 7295,
    7311             :     V_CVT_OFF_F32_I4_e32_si     = 7296,
    7312             :     V_CVT_OFF_F32_I4_e32_vi     = 7297,
    7313             :     V_CVT_OFF_F32_I4_e64        = 7298,
    7314             :     V_CVT_OFF_F32_I4_e64_si     = 7299,
    7315             :     V_CVT_OFF_F32_I4_e64_vi     = 7300,
    7316             :     V_CVT_OFF_F32_I4_sdwa       = 7301,
    7317             :     V_CVT_OFF_F32_I4_sdwa_gfx9  = 7302,
    7318             :     V_CVT_OFF_F32_I4_sdwa_vi    = 7303,
    7319             :     V_CVT_PKACCUM_U8_F32_e32    = 7304,
    7320             :     V_CVT_PKACCUM_U8_F32_e32_si = 7305,
    7321             :     V_CVT_PKACCUM_U8_F32_e64    = 7306,
    7322             :     V_CVT_PKACCUM_U8_F32_e64_si = 7307,
    7323             :     V_CVT_PKACCUM_U8_F32_e64_vi = 7308,
    7324             :     V_CVT_PKACCUM_U8_F32_sdwa   = 7309,
    7325             :     V_CVT_PKNORM_I16_F16        = 7310,
    7326             :     V_CVT_PKNORM_I16_F16_vi     = 7311,
    7327             :     V_CVT_PKNORM_I16_F32_e32    = 7312,
    7328             :     V_CVT_PKNORM_I16_F32_e32_si = 7313,
    7329             :     V_CVT_PKNORM_I16_F32_e64    = 7314,
    7330             :     V_CVT_PKNORM_I16_F32_e64_si = 7315,
    7331             :     V_CVT_PKNORM_I16_F32_e64_vi = 7316,
    7332             :     V_CVT_PKNORM_I16_F32_sdwa   = 7317,
    7333             :     V_CVT_PKNORM_U16_F16        = 7318,
    7334             :     V_CVT_PKNORM_U16_F16_vi     = 7319,
    7335             :     V_CVT_PKNORM_U16_F32_e32    = 7320,
    7336             :     V_CVT_PKNORM_U16_F32_e32_si = 7321,
    7337             :     V_CVT_PKNORM_U16_F32_e64    = 7322,
    7338             :     V_CVT_PKNORM_U16_F32_e64_si = 7323,
    7339             :     V_CVT_PKNORM_U16_F32_e64_vi = 7324,
    7340             :     V_CVT_PKNORM_U16_F32_sdwa   = 7325,
    7341             :     V_CVT_PKRTZ_F16_F32_e32     = 7326,
    7342             :     V_CVT_PKRTZ_F16_F32_e32_si  = 7327,
    7343             :     V_CVT_PKRTZ_F16_F32_e64     = 7328,
    7344             :     V_CVT_PKRTZ_F16_F32_e64_si  = 7329,
    7345             :     V_CVT_PKRTZ_F16_F32_e64_vi  = 7330,
    7346             :     V_CVT_PKRTZ_F16_F32_sdwa    = 7331,
    7347             :     V_CVT_PK_I16_I32_e32        = 7332,
    7348             :     V_CVT_PK_I16_I32_e32_si     = 7333,
    7349             :     V_CVT_PK_I16_I32_e64        = 7334,
    7350             :     V_CVT_PK_I16_I32_e64_si     = 7335,
    7351             :     V_CVT_PK_I16_I32_e64_vi     = 7336,
    7352             :     V_CVT_PK_I16_I32_sdwa       = 7337,
    7353             :     V_CVT_PK_U16_U32_e32        = 7338,
    7354             :     V_CVT_PK_U16_U32_e32_si     = 7339,
    7355             :     V_CVT_PK_U16_U32_e64        = 7340,
    7356             :     V_CVT_PK_U16_U32_e64_si     = 7341,
    7357             :     V_CVT_PK_U16_U32_e64_vi     = 7342,
    7358             :     V_CVT_PK_U16_U32_sdwa       = 7343,
    7359             :     V_CVT_PK_U8_F32     = 7344,
    7360             :     V_CVT_PK_U8_F32_si  = 7345,
    7361             :     V_CVT_PK_U8_F32_vi  = 7346,
    7362             :     V_CVT_RPI_I32_F32_dpp       = 7347,
    7363             :     V_CVT_RPI_I32_F32_e32       = 7348,
    7364             :     V_CVT_RPI_I32_F32_e32_si    = 7349,
    7365             :     V_CVT_RPI_I32_F32_e32_vi    = 7350,
    7366             :     V_CVT_RPI_I32_F32_e64       = 7351,
    7367             :     V_CVT_RPI_I32_F32_e64_si    = 7352,
    7368             :     V_CVT_RPI_I32_F32_e64_vi    = 7353,
    7369             :     V_CVT_RPI_I32_F32_sdwa      = 7354,
    7370             :     V_CVT_RPI_I32_F32_sdwa_gfx9 = 7355,
    7371             :     V_CVT_RPI_I32_F32_sdwa_vi   = 7356,
    7372             :     V_CVT_U16_F16_dpp   = 7357,
    7373             :     V_CVT_U16_F16_e32   = 7358,
    7374             :     V_CVT_U16_F16_e32_vi        = 7359,
    7375             :     V_CVT_U16_F16_e64   = 7360,
    7376             :     V_CVT_U16_F16_e64_vi        = 7361,
    7377             :     V_CVT_U16_F16_sdwa  = 7362,
    7378             :     V_CVT_U16_F16_sdwa_gfx9     = 7363,
    7379             :     V_CVT_U16_F16_sdwa_vi       = 7364,
    7380             :     V_CVT_U32_F32_dpp   = 7365,
    7381             :     V_CVT_U32_F32_e32   = 7366,
    7382             :     V_CVT_U32_F32_e32_si        = 7367,
    7383             :     V_CVT_U32_F32_e32_vi        = 7368,
    7384             :     V_CVT_U32_F32_e64   = 7369,
    7385             :     V_CVT_U32_F32_e64_si        = 7370,
    7386             :     V_CVT_U32_F32_e64_vi        = 7371,
    7387             :     V_CVT_U32_F32_sdwa  = 7372,
    7388             :     V_CVT_U32_F32_sdwa_gfx9     = 7373,
    7389             :     V_CVT_U32_F32_sdwa_vi       = 7374,
    7390             :     V_CVT_U32_F64_dpp   = 7375,
    7391             :     V_CVT_U32_F64_e32   = 7376,
    7392             :     V_CVT_U32_F64_e32_si        = 7377,
    7393             :     V_CVT_U32_F64_e32_vi        = 7378,
    7394             :     V_CVT_U32_F64_e64   = 7379,
    7395             :     V_CVT_U32_F64_e64_si        = 7380,
    7396             :     V_CVT_U32_F64_e64_vi        = 7381,
    7397             :     V_CVT_U32_F64_sdwa  = 7382,
    7398             :     V_CVT_U32_F64_sdwa_gfx9     = 7383,
    7399             :     V_CVT_U32_F64_sdwa_vi       = 7384,
    7400             :     V_DIV_FIXUP_F16     = 7385,
    7401             :     V_DIV_FIXUP_F16_gfx9        = 7386,
    7402             :     V_DIV_FIXUP_F16_gfx9_vi     = 7387,
    7403             :     V_DIV_FIXUP_F16_vi  = 7388,
    7404             :     V_DIV_FIXUP_F32     = 7389,
    7405             :     V_DIV_FIXUP_F32_si  = 7390,
    7406             :     V_DIV_FIXUP_F32_vi  = 7391,
    7407             :     V_DIV_FIXUP_F64     = 7392,
    7408             :     V_DIV_FIXUP_F64_si  = 7393,
    7409             :     V_DIV_FIXUP_F64_vi  = 7394,
    7410             :     V_DIV_FIXUP_LEGACY_F16_vi   = 7395,
    7411             :     V_DIV_FMAS_F32      = 7396,
    7412             :     V_DIV_FMAS_F32_si   = 7397,
    7413             :     V_DIV_FMAS_F32_vi   = 7398,
    7414             :     V_DIV_FMAS_F64      = 7399,
    7415             :     V_DIV_FMAS_F64_si   = 7400,
    7416             :     V_DIV_FMAS_F64_vi   = 7401,
    7417             :     V_DIV_SCALE_F32     = 7402,
    7418             :     V_DIV_SCALE_F32_si  = 7403,
    7419             :     V_DIV_SCALE_F32_vi  = 7404,
    7420             :     V_DIV_SCALE_F64     = 7405,
    7421             :     V_DIV_SCALE_F64_si  = 7406,
    7422             :     V_DIV_SCALE_F64_vi  = 7407,
    7423             :     V_EXP_F16_dpp       = 7408,
    7424             :     V_EXP_F16_e32       = 7409,
    7425             :     V_EXP_F16_e32_vi    = 7410,
    7426             :     V_EXP_F16_e64       = 7411,
    7427             :     V_EXP_F16_e64_vi    = 7412,
    7428             :     V_EXP_F16_sdwa      = 7413,
    7429             :     V_EXP_F16_sdwa_gfx9 = 7414,
    7430             :     V_EXP_F16_sdwa_vi   = 7415,
    7431             :     V_EXP_F32_dpp       = 7416,
    7432             :     V_EXP_F32_e32       = 7417,
    7433             :     V_EXP_F32_e32_si    = 7418,
    7434             :     V_EXP_F32_e32_vi    = 7419,
    7435             :     V_EXP_F32_e64       = 7420,
    7436             :     V_EXP_F32_e64_si    = 7421,
    7437             :     V_EXP_F32_e64_vi    = 7422,
    7438             :     V_EXP_F32_sdwa      = 7423,
    7439             :     V_EXP_F32_sdwa_gfx9 = 7424,
    7440             :     V_EXP_F32_sdwa_vi   = 7425,
    7441             :     V_EXP_LEGACY_F32_dpp        = 7426,
    7442             :     V_EXP_LEGACY_F32_e32        = 7427,
    7443             :     V_EXP_LEGACY_F32_e32_ci     = 7428,
    7444             :     V_EXP_LEGACY_F32_e32_vi     = 7429,
    7445             :     V_EXP_LEGACY_F32_e64        = 7430,
    7446             :     V_EXP_LEGACY_F32_e64_ci     = 7431,
    7447             :     V_EXP_LEGACY_F32_e64_vi     = 7432,
    7448             :     V_EXP_LEGACY_F32_sdwa       = 7433,
    7449             :     V_EXP_LEGACY_F32_sdwa_gfx9  = 7434,
    7450             :     V_EXP_LEGACY_F32_sdwa_vi    = 7435,
    7451             :     V_FFBH_I32_dpp      = 7436,
    7452             :     V_FFBH_I32_e32      = 7437,
    7453             :     V_FFBH_I32_e32_si   = 7438,
    7454             :     V_FFBH_I32_e32_vi   = 7439,
    7455             :     V_FFBH_I32_e64      = 7440,
    7456             :     V_FFBH_I32_e64_si   = 7441,
    7457             :     V_FFBH_I32_e64_vi   = 7442,
    7458             :     V_FFBH_I32_sdwa     = 7443,
    7459             :     V_FFBH_I32_sdwa_gfx9        = 7444,
    7460             :     V_FFBH_I32_sdwa_vi  = 7445,
    7461             :     V_FFBH_U32_dpp      = 7446,
    7462             :     V_FFBH_U32_e32      = 7447,
    7463             :     V_FFBH_U32_e32_si   = 7448,
    7464             :     V_FFBH_U32_e32_vi   = 7449,
    7465             :     V_FFBH_U32_e64      = 7450,
    7466             :     V_FFBH_U32_e64_si   = 7451,
    7467             :     V_FFBH_U32_e64_vi   = 7452,
    7468             :     V_FFBH_U32_sdwa     = 7453,
    7469             :     V_FFBH_U32_sdwa_gfx9        = 7454,
    7470             :     V_FFBH_U32_sdwa_vi  = 7455,
    7471             :     V_FFBL_B32_dpp      = 7456,
    7472             :     V_FFBL_B32_e32      = 7457,
    7473             :     V_FFBL_B32_e32_si   = 7458,
    7474             :     V_FFBL_B32_e32_vi   = 7459,
    7475             :     V_FFBL_B32_e64      = 7460,
    7476             :     V_FFBL_B32_e64_si   = 7461,
    7477             :     V_FFBL_B32_e64_vi   = 7462,
    7478             :     V_FFBL_B32_sdwa     = 7463,
    7479             :     V_FFBL_B32_sdwa_gfx9        = 7464,
    7480             :     V_FFBL_B32_sdwa_vi  = 7465,
    7481             :     V_FLOOR_F16_dpp     = 7466,
    7482             :     V_FLOOR_F16_e32     = 7467,
    7483             :     V_FLOOR_F16_e32_vi  = 7468,
    7484             :     V_FLOOR_F16_e64     = 7469,
    7485             :     V_FLOOR_F16_e64_vi  = 7470,
    7486             :     V_FLOOR_F16_sdwa    = 7471,
    7487             :     V_FLOOR_F16_sdwa_gfx9       = 7472,
    7488             :     V_FLOOR_F16_sdwa_vi = 7473,
    7489             :     V_FLOOR_F32_dpp     = 7474,
    7490             :     V_FLOOR_F32_e32     = 7475,
    7491             :     V_FLOOR_F32_e32_si  = 7476,
    7492             :     V_FLOOR_F32_e32_vi  = 7477,
    7493             :     V_FLOOR_F32_e64     = 7478,
    7494             :     V_FLOOR_F32_e64_si  = 7479,
    7495             :     V_FLOOR_F32_e64_vi  = 7480,
    7496             :     V_FLOOR_F32_sdwa    = 7481,
    7497             :     V_FLOOR_F32_sdwa_gfx9       = 7482,
    7498             :     V_FLOOR_F32_sdwa_vi = 7483,
    7499             :     V_FLOOR_F64_dpp     = 7484,
    7500             :     V_FLOOR_F64_e32     = 7485,
    7501             :     V_FLOOR_F64_e32_ci  = 7486,
    7502             :     V_FLOOR_F64_e32_vi  = 7487,
    7503             :     V_FLOOR_F64_e64     = 7488,
    7504             :     V_FLOOR_F64_e64_ci  = 7489,
    7505             :     V_FLOOR_F64_e64_vi  = 7490,
    7506             :     V_FLOOR_F64_sdwa    = 7491,
    7507             :     V_FLOOR_F64_sdwa_gfx9       = 7492,
    7508             :     V_FLOOR_F64_sdwa_vi = 7493,
    7509             :     V_FMA_F16   = 7494,
    7510             :     V_FMA_F16_gfx9      = 7495,
    7511             :     V_FMA_F16_gfx9_vi   = 7496,
    7512             :     V_FMA_F16_vi        = 7497,
    7513             :     V_FMA_F32   = 7498,
    7514             :     V_FMA_F32_si        = 7499,
    7515             :     V_FMA_F32_vi        = 7500,
    7516             :     V_FMA_F64   = 7501,
    7517             :     V_FMA_F64_si        = 7502,
    7518             :     V_FMA_F64_vi        = 7503,
    7519             :     V_FMA_LEGACY_F16_vi = 7504,
    7520             :     V_FRACT_F16_dpp     = 7505,
    7521             :     V_FRACT_F16_e32     = 7506,
    7522             :     V_FRACT_F16_e32_vi  = 7507,
    7523             :     V_FRACT_F16_e64     = 7508,
    7524             :     V_FRACT_F16_e64_vi  = 7509,
    7525             :     V_FRACT_F16_sdwa    = 7510,
    7526             :     V_FRACT_F16_sdwa_gfx9       = 7511,
    7527             :     V_FRACT_F16_sdwa_vi = 7512,
    7528             :     V_FRACT_F32_dpp     = 7513,
    7529             :     V_FRACT_F32_e32     = 7514,
    7530             :     V_FRACT_F32_e32_si  = 7515,
    7531             :     V_FRACT_F32_e32_vi  = 7516,
    7532             :     V_FRACT_F32_e64     = 7517,
    7533             :     V_FRACT_F32_e64_si  = 7518,
    7534             :     V_FRACT_F32_e64_vi  = 7519,
    7535             :     V_FRACT_F32_sdwa    = 7520,
    7536             :     V_FRACT_F32_sdwa_gfx9       = 7521,
    7537             :     V_FRACT_F32_sdwa_vi = 7522,
    7538             :     V_FRACT_F64_dpp     = 7523,
    7539             :     V_FRACT_F64_e32     = 7524,
    7540             :     V_FRACT_F64_e32_si  = 7525,
    7541             :     V_FRACT_F64_e32_vi  = 7526,
    7542             :     V_FRACT_F64_e64     = 7527,
    7543             :     V_FRACT_F64_e64_si  = 7528,
    7544             :     V_FRACT_F64_e64_vi  = 7529,
    7545             :     V_FRACT_F64_sdwa    = 7530,
    7546             :     V_FRACT_F64_sdwa_gfx9       = 7531,
    7547             :     V_FRACT_F64_sdwa_vi = 7532,
    7548             :     V_FREXP_EXP_I16_F16_dpp     = 7533,
    7549             :     V_FREXP_EXP_I16_F16_e32     = 7534,
    7550             :     V_FREXP_EXP_I16_F16_e32_vi  = 7535,
    7551             :     V_FREXP_EXP_I16_F16_e64     = 7536,
    7552             :     V_FREXP_EXP_I16_F16_e64_vi  = 7537,
    7553             :     V_FREXP_EXP_I16_F16_sdwa    = 7538,
    7554             :     V_FREXP_EXP_I16_F16_sdwa_gfx9       = 7539,
    7555             :     V_FREXP_EXP_I16_F16_sdwa_vi = 7540,
    7556             :     V_FREXP_EXP_I32_F32_dpp     = 7541,
    7557             :     V_FREXP_EXP_I32_F32_e32     = 7542,
    7558             :     V_FREXP_EXP_I32_F32_e32_si  = 7543,
    7559             :     V_FREXP_EXP_I32_F32_e32_vi  = 7544,
    7560             :     V_FREXP_EXP_I32_F32_e64     = 7545,
    7561             :     V_FREXP_EXP_I32_F32_e64_si  = 7546,
    7562             :     V_FREXP_EXP_I32_F32_e64_vi  = 7547,
    7563             :     V_FREXP_EXP_I32_F32_sdwa    = 7548,
    7564             :     V_FREXP_EXP_I32_F32_sdwa_gfx9       = 7549,
    7565             :     V_FREXP_EXP_I32_F32_sdwa_vi = 7550,
    7566             :     V_FREXP_EXP_I32_F64_dpp     = 7551,
    7567             :     V_FREXP_EXP_I32_F64_e32     = 7552,
    7568             :     V_FREXP_EXP_I32_F64_e32_si  = 7553,
    7569             :     V_FREXP_EXP_I32_F64_e32_vi  = 7554,
    7570             :     V_FREXP_EXP_I32_F64_e64     = 7555,
    7571             :     V_FREXP_EXP_I32_F64_e64_si  = 7556,
    7572             :     V_FREXP_EXP_I32_F64_e64_vi  = 7557,
    7573             :     V_FREXP_EXP_I32_F64_sdwa    = 7558,
    7574             :     V_FREXP_EXP_I32_F64_sdwa_gfx9       = 7559,
    7575             :     V_FREXP_EXP_I32_F64_sdwa_vi = 7560,
    7576             :     V_FREXP_MANT_F16_dpp        = 7561,
    7577             :     V_FREXP_MANT_F16_e32        = 7562,
    7578             :     V_FREXP_MANT_F16_e32_vi     = 7563,
    7579             :     V_FREXP_MANT_F16_e64        = 7564,
    7580             :     V_FREXP_MANT_F16_e64_vi     = 7565,
    7581             :     V_FREXP_MANT_F16_sdwa       = 7566,
    7582             :     V_FREXP_MANT_F16_sdwa_gfx9  = 7567,
    7583             :     V_FREXP_MANT_F16_sdwa_vi    = 7568,
    7584             :     V_FREXP_MANT_F32_dpp        = 7569,
    7585             :     V_FREXP_MANT_F32_e32        = 7570,
    7586             :     V_FREXP_MANT_F32_e32_si     = 7571,
    7587             :     V_FREXP_MANT_F32_e32_vi     = 7572,
    7588             :     V_FREXP_MANT_F32_e64        = 7573,
    7589             :     V_FREXP_MANT_F32_e64_si     = 7574,
    7590             :     V_FREXP_MANT_F32_e64_vi     = 7575,
    7591             :     V_FREXP_MANT_F32_sdwa       = 7576,
    7592             :     V_FREXP_MANT_F32_sdwa_gfx9  = 7577,
    7593             :     V_FREXP_MANT_F32_sdwa_vi    = 7578,
    7594             :     V_FREXP_MANT_F64_dpp        = 7579,
    7595             :     V_FREXP_MANT_F64_e32        = 7580,
    7596             :     V_FREXP_MANT_F64_e32_si     = 7581,
    7597             :     V_FREXP_MANT_F64_e32_vi     = 7582,
    7598             :     V_FREXP_MANT_F64_e64        = 7583,
    7599             :     V_FREXP_MANT_F64_e64_si     = 7584,
    7600             :     V_FREXP_MANT_F64_e64_vi     = 7585,
    7601             :     V_FREXP_MANT_F64_sdwa       = 7586,
    7602             :     V_FREXP_MANT_F64_sdwa_gfx9  = 7587,
    7603             :     V_FREXP_MANT_F64_sdwa_vi    = 7588,
    7604             :     V_INTERP_MOV_F32    = 7589,
    7605             :     V_INTERP_MOV_F32_e64        = 7590,
    7606             :     V_INTERP_MOV_F32_e64_vi     = 7591,
    7607             :     V_INTERP_MOV_F32_si = 7592,
    7608             :     V_INTERP_MOV_F32_vi = 7593,
    7609             :     V_INTERP_P1LL_F16   = 7594,
    7610             :     V_INTERP_P1LL_F16_vi        = 7595,
    7611             :     V_INTERP_P1LV_F16   = 7596,
    7612             :     V_INTERP_P1LV_F16_vi        = 7597,
    7613             :     V_INTERP_P1_F32     = 7598,
    7614             :     V_INTERP_P1_F32_16bank      = 7599,
    7615             :     V_INTERP_P1_F32_16bank_si   = 7600,
    7616             :     V_INTERP_P1_F32_16bank_vi   = 7601,
    7617             :     V_INTERP_P1_F32_e64 = 7602,
    7618             :     V_INTERP_P1_F32_e64_vi      = 7603,
    7619             :     V_INTERP_P1_F32_si  = 7604,
    7620             :     V_INTERP_P1_F32_vi  = 7605,
    7621             :     V_INTERP_P2_F16     = 7606,
    7622             :     V_INTERP_P2_F16_vi  = 7607,
    7623             :     V_INTERP_P2_F32     = 7608,
    7624             :     V_INTERP_P2_F32_e64 = 7609,
    7625             :     V_INTERP_P2_F32_e64_vi      = 7610,
    7626             :     V_INTERP_P2_F32_si  = 7611,
    7627             :     V_INTERP_P2_F32_vi  = 7612,
    7628             :     V_LDEXP_F16_dpp     = 7613,
    7629             :     V_LDEXP_F16_e32     = 7614,
    7630             :     V_LDEXP_F16_e32_vi  = 7615,
    7631             :     V_LDEXP_F16_e64     = 7616,
    7632             :     V_LDEXP_F16_e64_vi  = 7617,
    7633             :     V_LDEXP_F16_sdwa    = 7618,
    7634             :     V_LDEXP_F16_sdwa_gfx9       = 7619,
    7635             :     V_LDEXP_F16_sdwa_vi = 7620,
    7636             :     V_LDEXP_F32_e32     = 7621,
    7637             :     V_LDEXP_F32_e32_si  = 7622,
    7638             :     V_LDEXP_F32_e64     = 7623,
    7639             :     V_LDEXP_F32_e64_si  = 7624,
    7640             :     V_LDEXP_F32_e64_vi  = 7625,
    7641             :     V_LDEXP_F32_sdwa    = 7626,
    7642             :     V_LDEXP_F64 = 7627,
    7643             :     V_LDEXP_F64_si      = 7628,
    7644             :     V_LDEXP_F64_vi      = 7629,
    7645             :     V_LERP_U8   = 7630,
    7646             :     V_LERP_U8_si        = 7631,
    7647             :     V_LERP_U8_vi        = 7632,
    7648             :     V_LOG_CLAMP_F32_e32 = 7633,
    7649             :     V_LOG_CLAMP_F32_e32_si      = 7634,
    7650             :     V_LOG_CLAMP_F32_e64 = 7635,
    7651             :     V_LOG_CLAMP_F32_e64_si      = 7636,
    7652             :     V_LOG_CLAMP_F32_sdwa        = 7637,
    7653             :     V_LOG_F16_dpp       = 7638,
    7654             :     V_LOG_F16_e32       = 7639,
    7655             :     V_LOG_F16_e32_vi    = 7640,
    7656             :     V_LOG_F16_e64       = 7641,
    7657             :     V_LOG_F16_e64_vi    = 7642,
    7658             :     V_LOG_F16_sdwa      = 7643,
    7659             :     V_LOG_F16_sdwa_gfx9 = 7644,
    7660             :     V_LOG_F16_sdwa_vi   = 7645,
    7661             :     V_LOG_F32_dpp       = 7646,
    7662             :     V_LOG_F32_e32       = 7647,
    7663             :     V_LOG_F32_e32_si    = 7648,
    7664             :     V_LOG_F32_e32_vi    = 7649,
    7665             :     V_LOG_F32_e64       = 7650,
    7666             :     V_LOG_F32_e64_si    = 7651,
    7667             :     V_LOG_F32_e64_vi    = 7652,
    7668             :     V_LOG_F32_sdwa      = 7653,
    7669             :     V_LOG_F32_sdwa_gfx9 = 7654,
    7670             :     V_LOG_F32_sdwa_vi   = 7655,
    7671             :     V_LOG_LEGACY_F32_dpp        = 7656,
    7672             :     V_LOG_LEGACY_F32_e32        = 7657,
    7673             :     V_LOG_LEGACY_F32_e32_ci     = 7658,
    7674             :     V_LOG_LEGACY_F32_e32_vi     = 7659,
    7675             :     V_LOG_LEGACY_F32_e64        = 7660,
    7676             :     V_LOG_LEGACY_F32_e64_ci     = 7661,
    7677             :     V_LOG_LEGACY_F32_e64_vi     = 7662,
    7678             :     V_LOG_LEGACY_F32_sdwa       = 7663,
    7679             :     V_LOG_LEGACY_F32_sdwa_gfx9  = 7664,
    7680             :     V_LOG_LEGACY_F32_sdwa_vi    = 7665,
    7681             :     V_LSHLREV_B16_dpp   = 7666,
    7682             :     V_LSHLREV_B16_e32   = 7667,
    7683             :     V_LSHLREV_B16_e32_vi        = 7668,
    7684             :     V_LSHLREV_B16_e64   = 7669,
    7685             :     V_LSHLREV_B16_e64_vi        = 7670,
    7686             :     V_LSHLREV_B16_sdwa  = 7671,
    7687             :     V_LSHLREV_B16_sdwa_gfx9     = 7672,
    7688             :     V_LSHLREV_B16_sdwa_vi       = 7673,
    7689             :     V_LSHLREV_B32_dpp   = 7674,
    7690             :     V_LSHLREV_B32_e32   = 7675,
    7691             :     V_LSHLREV_B32_e32_si        = 7676,
    7692             :     V_LSHLREV_B32_e32_vi        = 7677,
    7693             :     V_LSHLREV_B32_e64   = 7678,
    7694             :     V_LSHLREV_B32_e64_si        = 7679,
    7695             :     V_LSHLREV_B32_e64_vi        = 7680,
    7696             :     V_LSHLREV_B32_sdwa  = 7681,
    7697             :     V_LSHLREV_B32_sdwa_gfx9     = 7682,
    7698             :     V_LSHLREV_B32_sdwa_vi       = 7683,
    7699             :     V_LSHLREV_B64       = 7684,
    7700             :     V_LSHLREV_B64_vi    = 7685,
    7701             :     V_LSHL_ADD_U32      = 7686,
    7702             :     V_LSHL_ADD_U32_vi   = 7687,
    7703             :     V_LSHL_B32_e32      = 7688,
    7704             :     V_LSHL_B32_e32_si   = 7689,
    7705             :     V_LSHL_B32_e64      = 7690,
    7706             :     V_LSHL_B32_e64_si   = 7691,
    7707             :     V_LSHL_B32_sdwa     = 7692,
    7708             :     V_LSHL_B64  = 7693,
    7709             :     V_LSHL_B64_si       = 7694,
    7710             :     V_LSHL_OR_B32       = 7695,
    7711             :     V_LSHL_OR_B32_vi    = 7696,
    7712             :     V_LSHRREV_B16_dpp   = 7697,
    7713             :     V_LSHRREV_B16_e32   = 7698,
    7714             :     V_LSHRREV_B16_e32_vi        = 7699,
    7715             :     V_LSHRREV_B16_e64   = 7700,
    7716             :     V_LSHRREV_B16_e64_vi        = 7701,
    7717             :     V_LSHRREV_B16_sdwa  = 7702,
    7718             :     V_LSHRREV_B16_sdwa_gfx9     = 7703,
    7719             :     V_LSHRREV_B16_sdwa_vi       = 7704,
    7720             :     V_LSHRREV_B32_dpp   = 7705,
    7721             :     V_LSHRREV_B32_e32   = 7706,
    7722             :     V_LSHRREV_B32_e32_si        = 7707,
    7723             :     V_LSHRREV_B32_e32_vi        = 7708,
    7724             :     V_LSHRREV_B32_e64   = 7709,
    7725             :     V_LSHRREV_B32_e64_si        = 7710,
    7726             :     V_LSHRREV_B32_e64_vi        = 7711,
    7727             :     V_LSHRREV_B32_sdwa  = 7712,
    7728             :     V_LSHRREV_B32_sdwa_gfx9     = 7713,
    7729             :     V_LSHRREV_B32_sdwa_vi       = 7714,
    7730             :     V_LSHRREV_B64       = 7715,
    7731             :     V_LSHRREV_B64_vi    = 7716,
    7732             :     V_LSHR_B32_e32      = 7717,
    7733             :     V_LSHR_B32_e32_si   = 7718,
    7734             :     V_LSHR_B32_e64      = 7719,
    7735             :     V_LSHR_B32_e64_si   = 7720,
    7736             :     V_LSHR_B32_sdwa     = 7721,
    7737             :     V_LSHR_B64  = 7722,
    7738             :     V_LSHR_B64_si       = 7723,
    7739             :     V_MAC_F16_dpp       = 7724,
    7740             :     V_MAC_F16_e32       = 7725,
    7741             :     V_MAC_F16_e32_vi    = 7726,
    7742             :     V_MAC_F16_e64       = 7727,
    7743             :     V_MAC_F16_e64_vi    = 7728,
    7744             :     V_MAC_F16_sdwa      = 7729,
    7745             :     V_MAC_F16_sdwa_gfx9 = 7730,
    7746             :     V_MAC_F16_sdwa_vi   = 7731,
    7747             :     V_MAC_F32_dpp       = 7732,
    7748             :     V_MAC_F32_e32       = 7733,
    7749             :     V_MAC_F32_e32_si    = 7734,
    7750             :     V_MAC_F32_e32_vi    = 7735,
    7751             :     V_MAC_F32_e64       = 7736,
    7752             :     V_MAC_F32_e64_si    = 7737,
    7753             :     V_MAC_F32_e64_vi    = 7738,
    7754             :     V_MAC_F32_sdwa      = 7739,
    7755             :     V_MAC_F32_sdwa_gfx9 = 7740,
    7756             :     V_MAC_F32_sdwa_vi   = 7741,
    7757             :     V_MAC_LEGACY_F32_e32        = 7742,
    7758             :     V_MAC_LEGACY_F32_e32_si     = 7743,
    7759             :     V_MAC_LEGACY_F32_e64        = 7744,
    7760             :     V_MAC_LEGACY_F32_e64_si     = 7745,
    7761             :     V_MAC_LEGACY_F32_sdwa       = 7746,
    7762             :     V_MADAK_F16 = 7747,
    7763             :     V_MADAK_F16_vi      = 7748,
    7764             :     V_MADAK_F32 = 7749,
    7765             :     V_MADAK_F32_si      = 7750,
    7766             :     V_MADAK_F32_vi      = 7751,
    7767             :     V_MADMK_F16 = 7752,
    7768             :     V_MADMK_F16_vi      = 7753,
    7769             :     V_MADMK_F32 = 7754,
    7770             :     V_MADMK_F32_si      = 7755,
    7771             :     V_MADMK_F32_vi      = 7756,
    7772             :     V_MAD_F16   = 7757,
    7773             :     V_MAD_F16_gfx9      = 7758,
    7774             :     V_MAD_F16_gfx9_vi   = 7759,
    7775             :     V_MAD_F16_vi        = 7760,
    7776             :     V_MAD_F32   = 7761,
    7777             :     V_MAD_F32_si        = 7762,
    7778             :     V_MAD_F32_vi        = 7763,
    7779             :     V_MAD_I16   = 7764,
    7780             :     V_MAD_I16_gfx9      = 7765,
    7781             :     V_MAD_I16_gfx9_vi   = 7766,
    7782             :     V_MAD_I16_vi        = 7767,
    7783             :     V_MAD_I32_I16       = 7768,
    7784             :     V_MAD_I32_I16_vi    = 7769,
    7785             :     V_MAD_I32_I24       = 7770,
    7786             :     V_MAD_I32_I24_si    = 7771,
    7787             :     V_MAD_I32_I24_vi    = 7772,
    7788             :     V_MAD_I64_I32       = 7773,
    7789             :     V_MAD_I64_I32_ci    = 7774,
    7790             :     V_MAD_I64_I32_vi    = 7775,
    7791             :     V_MAD_LEGACY_F16_vi = 7776,
    7792             :     V_MAD_LEGACY_F32    = 7777,
    7793             :     V_MAD_LEGACY_F32_si = 7778,
    7794             :     V_MAD_LEGACY_F32_vi = 7779,
    7795             :     V_MAD_LEGACY_I16_vi = 7780,
    7796             :     V_MAD_LEGACY_U16_vi = 7781,
    7797             :     V_MAD_MIXHI_F16     = 7782,
    7798             :     V_MAD_MIXHI_F16_vi  = 7783,
    7799             :     V_MAD_MIXLO_F16     = 7784,
    7800             :     V_MAD_MIXLO_F16_vi  = 7785,
    7801             :     V_MAD_MIX_F32       = 7786,
    7802             :     V_MAD_MIX_F32_vi    = 7787,
    7803             :     V_MAD_U16   = 7788,
    7804             :     V_MAD_U16_gfx9      = 7789,
    7805             :     V_MAD_U16_gfx9_vi   = 7790,
    7806             :     V_MAD_U16_vi        = 7791,
    7807             :     V_MAD_U32_U16       = 7792,
    7808             :     V_MAD_U32_U16_vi    = 7793,
    7809             :     V_MAD_U32_U24       = 7794,
    7810             :     V_MAD_U32_U24_si    = 7795,
    7811             :     V_MAD_U32_U24_vi    = 7796,
    7812             :     V_MAD_U64_U32       = 7797,
    7813             :     V_MAD_U64_U32_ci    = 7798,
    7814             :     V_MAD_U64_U32_vi    = 7799,
    7815             :     V_MAX3_F16  = 7800,
    7816             :     V_MAX3_F16_vi       = 7801,
    7817             :     V_MAX3_F32  = 7802,
    7818             :     V_MAX3_F32_si       = 7803,
    7819             :     V_MAX3_F32_vi       = 7804,
    7820             :     V_MAX3_I16  = 7805,
    7821             :     V_MAX3_I16_vi       = 7806,
    7822             :     V_MAX3_I32  = 7807,
    7823             :     V_MAX3_I32_si       = 7808,
    7824             :     V_MAX3_I32_vi       = 7809,
    7825             :     V_MAX3_U16  = 7810,
    7826             :     V_MAX3_U16_vi       = 7811,
    7827             :     V_MAX3_U32  = 7812,
    7828             :     V_MAX3_U32_si       = 7813,
    7829             :     V_MAX3_U32_vi       = 7814,
    7830             :     V_MAX_F16_dpp       = 7815,
    7831             :     V_MAX_F16_e32       = 7816,
    7832             :     V_MAX_F16_e32_vi    = 7817,
    7833             :     V_MAX_F16_e64       = 7818,
    7834             :     V_MAX_F16_e64_vi    = 7819,
    7835             :     V_MAX_F16_sdwa      = 7820,
    7836             :     V_MAX_F16_sdwa_gfx9 = 7821,
    7837             :     V_MAX_F16_sdwa_vi   = 7822,
    7838             :     V_MAX_F32_dpp       = 7823,
    7839             :     V_MAX_F32_e32       = 7824,
    7840             :     V_MAX_F32_e32_si    = 7825,
    7841             :     V_MAX_F32_e32_vi    = 7826,
    7842             :     V_MAX_F32_e64       = 7827,
    7843             :     V_MAX_F32_e64_si    = 7828,
    7844             :     V_MAX_F32_e64_vi    = 7829,
    7845             :     V_MAX_F32_sdwa      = 7830,
    7846             :     V_MAX_F32_sdwa_gfx9 = 7831,
    7847             :     V_MAX_F32_sdwa_vi   = 7832,
    7848             :     V_MAX_F64   = 7833,
    7849             :     V_MAX_F64_si        = 7834,
    7850             :     V_MAX_F64_vi        = 7835,
    7851             :     V_MAX_I16_dpp       = 7836,
    7852             :     V_MAX_I16_e32       = 7837,
    7853             :     V_MAX_I16_e32_vi    = 7838,
    7854             :     V_MAX_I16_e64       = 7839,
    7855             :     V_MAX_I16_e64_vi    = 7840,
    7856             :     V_MAX_I16_sdwa      = 7841,
    7857             :     V_MAX_I16_sdwa_gfx9 = 7842,
    7858             :     V_MAX_I16_sdwa_vi   = 7843,
    7859             :     V_MAX_I32_dpp       = 7844,
    7860             :     V_MAX_I32_e32       = 7845,
    7861             :     V_MAX_I32_e32_si    = 7846,
    7862             :     V_MAX_I32_e32_vi    = 7847,
    7863             :     V_MAX_I32_e64       = 7848,
    7864             :     V_MAX_I32_e64_si    = 7849,
    7865             :     V_MAX_I32_e64_vi    = 7850,
    7866             :     V_MAX_I32_sdwa      = 7851,
    7867             :     V_MAX_I32_sdwa_gfx9 = 7852,
    7868             :     V_MAX_I32_sdwa_vi   = 7853,
    7869             :     V_MAX_LEGACY_F32_e32        = 7854,
    7870             :     V_MAX_LEGACY_F32_e32_si     = 7855,
    7871             :     V_MAX_LEGACY_F32_e64        = 7856,
    7872             :     V_MAX_LEGACY_F32_e64_si     = 7857,
    7873             :     V_MAX_LEGACY_F32_sdwa       = 7858,
    7874             :     V_MAX_U16_dpp       = 7859,
    7875             :     V_MAX_U16_e32       = 7860,
    7876             :     V_MAX_U16_e32_vi    = 7861,
    7877             :     V_MAX_U16_e64       = 7862,
    7878             :     V_MAX_U16_e64_vi    = 7863,
    7879             :     V_MAX_U16_sdwa      = 7864,
    7880             :     V_MAX_U16_sdwa_gfx9 = 7865,
    7881             :     V_MAX_U16_sdwa_vi   = 7866,
    7882             :     V_MAX_U32_dpp       = 7867,
    7883             :     V_MAX_U32_e32       = 7868,
    7884             :     V_MAX_U32_e32_si    = 7869,
    7885             :     V_MAX_U32_e32_vi    = 7870,
    7886             :     V_MAX_U32_e64       = 7871,
    7887             :     V_MAX_U32_e64_si    = 7872,
    7888             :     V_MAX_U32_e64_vi    = 7873,
    7889             :     V_MAX_U32_sdwa      = 7874,
    7890             :     V_MAX_U32_sdwa_gfx9 = 7875,
    7891             :     V_MAX_U32_sdwa_vi   = 7876,
    7892             :     V_MBCNT_HI_U32_B32_e32      = 7877,
    7893             :     V_MBCNT_HI_U32_B32_e32_si   = 7878,
    7894             :     V_MBCNT_HI_U32_B32_e64      = 7879,
    7895             :     V_MBCNT_HI_U32_B32_e64_si   = 7880,
    7896             :     V_MBCNT_HI_U32_B32_e64_vi   = 7881,
    7897             :     V_MBCNT_HI_U32_B32_sdwa     = 7882,
    7898             :     V_MBCNT_LO_U32_B32_e32      = 7883,
    7899             :     V_MBCNT_LO_U32_B32_e32_si   = 7884,
    7900             :     V_MBCNT_LO_U32_B32_e64      = 7885,
    7901             :     V_MBCNT_LO_U32_B32_e64_si   = 7886,
    7902             :     V_MBCNT_LO_U32_B32_e64_vi   = 7887,
    7903             :     V_MBCNT_LO_U32_B32_sdwa     = 7888,
    7904             :     V_MED3_F16  = 7889,
    7905             :     V_MED3_F16_vi       = 7890,
    7906             :     V_MED3_F32  = 7891,
    7907             :     V_MED3_F32_si       = 7892,
    7908             :     V_MED3_F32_vi       = 7893,
    7909             :     V_MED3_I16  = 7894,
    7910             :     V_MED3_I16_vi       = 7895,
    7911             :     V_MED3_I32  = 7896,
    7912             :     V_MED3_I32_si       = 7897,
    7913             :     V_MED3_I32_vi       = 7898,
    7914             :     V_MED3_U16  = 7899,
    7915             :     V_MED3_U16_vi       = 7900,
    7916             :     V_MED3_U32  = 7901,
    7917             :     V_MED3_U32_si       = 7902,
    7918             :     V_MED3_U32_vi       = 7903,
    7919             :     V_MIN3_F16  = 7904,
    7920             :     V_MIN3_F16_vi       = 7905,
    7921             :     V_MIN3_F32  = 7906,
    7922             :     V_MIN3_F32_si       = 7907,
    7923             :     V_MIN3_F32_vi       = 7908,
    7924             :     V_MIN3_I16  = 7909,
    7925             :     V_MIN3_I16_vi       = 7910,
    7926             :     V_MIN3_I32  = 7911,
    7927             :     V_MIN3_I32_si       = 7912,
    7928             :     V_MIN3_I32_vi       = 7913,
    7929             :     V_MIN3_U16  = 7914,
    7930             :     V_MIN3_U16_vi       = 7915,
    7931             :     V_MIN3_U32  = 7916,
    7932             :     V_MIN3_U32_si       = 7917,
    7933             :     V_MIN3_U32_vi       = 7918,
    7934             :     V_MIN_F16_dpp       = 7919,
    7935             :     V_MIN_F16_e32       = 7920,
    7936             :     V_MIN_F16_e32_vi    = 7921,
    7937             :     V_MIN_F16_e64       = 7922,
    7938             :     V_MIN_F16_e64_vi    = 7923,
    7939             :     V_MIN_F16_sdwa      = 7924,
    7940             :     V_MIN_F16_sdwa_gfx9 = 7925,
    7941             :     V_MIN_F16_sdwa_vi   = 7926,
    7942             :     V_MIN_F32_dpp       = 7927,
    7943             :     V_MIN_F32_e32       = 7928,
    7944             :     V_MIN_F32_e32_si    = 7929,
    7945             :     V_MIN_F32_e32_vi    = 7930,
    7946             :     V_MIN_F32_e64       = 7931,
    7947             :     V_MIN_F32_e64_si    = 7932,
    7948             :     V_MIN_F32_e64_vi    = 7933,
    7949             :     V_MIN_F32_sdwa      = 7934,
    7950             :     V_MIN_F32_sdwa_gfx9 = 7935,
    7951             :     V_MIN_F32_sdwa_vi   = 7936,
    7952             :     V_MIN_F64   = 7937,
    7953             :     V_MIN_F64_si        = 7938,
    7954             :     V_MIN_F64_vi        = 7939,
    7955             :     V_MIN_I16_dpp       = 7940,
    7956             :     V_MIN_I16_e32       = 7941,
    7957             :     V_MIN_I16_e32_vi    = 7942,
    7958             :     V_MIN_I16_e64       = 7943,
    7959             :     V_MIN_I16_e64_vi    = 7944,
    7960             :     V_MIN_I16_sdwa      = 7945,
    7961             :     V_MIN_I16_sdwa_gfx9 = 7946,
    7962             :     V_MIN_I16_sdwa_vi   = 7947,
    7963             :     V_MIN_I32_dpp       = 7948,
    7964             :     V_MIN_I32_e32       = 7949,
    7965             :     V_MIN_I32_e32_si    = 7950,
    7966             :     V_MIN_I32_e32_vi    = 7951,
    7967             :     V_MIN_I32_e64       = 7952,
    7968             :     V_MIN_I32_e64_si    = 7953,
    7969             :     V_MIN_I32_e64_vi    = 7954,
    7970             :     V_MIN_I32_sdwa      = 7955,
    7971             :     V_MIN_I32_sdwa_gfx9 = 7956,
    7972             :     V_MIN_I32_sdwa_vi   = 7957,
    7973             :     V_MIN_LEGACY_F32_e32        = 7958,
    7974             :     V_MIN_LEGACY_F32_e32_si     = 7959,
    7975             :     V_MIN_LEGACY_F32_e64        = 7960,
    7976             :     V_MIN_LEGACY_F32_e64_si     = 7961,
    7977             :     V_MIN_LEGACY_F32_sdwa       = 7962,
    7978             :     V_MIN_U16_dpp       = 7963,
    7979             :     V_MIN_U16_e32       = 7964,
    7980             :     V_MIN_U16_e32_vi    = 7965,
    7981             :     V_MIN_U16_e64       = 7966,
    7982             :     V_MIN_U16_e64_vi    = 7967,
    7983             :     V_MIN_U16_sdwa      = 7968,
    7984             :     V_MIN_U16_sdwa_gfx9 = 7969,
    7985             :     V_MIN_U16_sdwa_vi   = 7970,
    7986             :     V_MIN_U32_dpp       = 7971,
    7987             :     V_MIN_U32_e32       = 7972,
    7988             :     V_MIN_U32_e32_si    = 7973,
    7989             :     V_MIN_U32_e32_vi    = 7974,
    7990             :     V_MIN_U32_e64       = 7975,
    7991             :     V_MIN_U32_e64_si    = 7976,
    7992             :     V_MIN_U32_e64_vi    = 7977,
    7993             :     V_MIN_U32_sdwa      = 7978,
    7994             :     V_MIN_U32_sdwa_gfx9 = 7979,
    7995             :     V_MIN_U32_sdwa_vi   = 7980,
    7996             :     V_MOVRELD_B32_V1    = 7981,
    7997             :     V_MOVRELD_B32_V16   = 7982,
    7998             :     V_MOVRELD_B32_V2    = 7983,
    7999             :     V_MOVRELD_B32_V4    = 7984,
    8000             :     V_MOVRELD_B32_V8    = 7985,
    8001             :     V_MOVRELD_B32_dpp   = 7986,
    8002             :     V_MOVRELD_B32_e32   = 7987,
    8003             :     V_MOVRELD_B32_e32_si        = 7988,
    8004             :     V_MOVRELD_B32_e32_vi        = 7989,
    8005             :     V_MOVRELD_B32_e64   = 7990,
    8006             :     V_MOVRELD_B32_e64_si        = 7991,
    8007             :     V_MOVRELD_B32_e64_vi        = 7992,
    8008             :     V_MOVRELD_B32_sdwa  = 7993,
    8009             :     V_MOVRELD_B32_sdwa_gfx9     = 7994,
    8010             :     V_MOVRELD_B32_sdwa_vi       = 7995,
    8011             :     V_MOVRELSD_B32_dpp  = 7996,
    8012             :     V_MOVRELSD_B32_e32  = 7997,
    8013             :     V_MOVRELSD_B32_e32_si       = 7998,
    8014             :     V_MOVRELSD_B32_e32_vi       = 7999,
    8015             :     V_MOVRELSD_B32_e64  = 8000,
    8016             :     V_MOVRELSD_B32_e64_si       = 8001,
    8017             :     V_MOVRELSD_B32_e64_vi       = 8002,
    8018             :     V_MOVRELSD_B32_sdwa = 8003,
    8019             :     V_MOVRELSD_B32_sdwa_gfx9    = 8004,
    8020             :     V_MOVRELSD_B32_sdwa_vi      = 8005,
    8021             :     V_MOVRELS_B32_dpp   = 8006,
    8022             :     V_MOVRELS_B32_e32   = 8007,
    8023             :     V_MOVRELS_B32_e32_si        = 8008,
    8024             :     V_MOVRELS_B32_e32_vi        = 8009,
    8025             :     V_MOVRELS_B32_e64   = 8010,
    8026             :     V_MOVRELS_B32_e64_si        = 8011,
    8027             :     V_MOVRELS_B32_e64_vi        = 8012,
    8028             :     V_MOVRELS_B32_sdwa  = 8013,
    8029             :     V_MOVRELS_B32_sdwa_gfx9     = 8014,
    8030             :     V_MOVRELS_B32_sdwa_vi       = 8015,
    8031             :     V_MOV_B32_dpp       = 8016,
    8032             :     V_MOV_B32_e32       = 8017,
    8033             :     V_MOV_B32_e32_si    = 8018,
    8034             :     V_MOV_B32_e32_vi    = 8019,
    8035             :     V_MOV_B32_e64       = 8020,
    8036             :     V_MOV_B32_e64_si    = 8021,
    8037             :     V_MOV_B32_e64_vi    = 8022,
    8038             :     V_MOV_B32_indirect  = 8023,
    8039             :     V_MOV_B32_sdwa      = 8024,
    8040             :     V_MOV_B32_sdwa_gfx9 = 8025,
    8041             :     V_MOV_B32_sdwa_vi   = 8026,
    8042             :     V_MOV_B64_PSEUDO    = 8027,
    8043             :     V_MOV_FED_B32_dpp   = 8028,
    8044             :     V_MOV_FED_B32_e32   = 8029,
    8045             :     V_MOV_FED_B32_e32_si        = 8030,
    8046             :     V_MOV_FED_B32_e32_vi        = 8031,
    8047             :     V_MOV_FED_B32_e64   = 8032,
    8048             :     V_MOV_FED_B32_e64_si        = 8033,
    8049             :     V_MOV_FED_B32_e64_vi        = 8034,
    8050             :     V_MOV_FED_B32_sdwa  = 8035,
    8051             :     V_MOV_FED_B32_sdwa_gfx9     = 8036,
    8052             :     V_MOV_FED_B32_sdwa_vi       = 8037,
    8053             :     V_MQSAD_PK_U16_U8   = 8038,
    8054             :     V_MQSAD_PK_U16_U8_si        = 8039,
    8055             :     V_MQSAD_PK_U16_U8_vi        = 8040,
    8056             :     V_MQSAD_U32_U8      = 8041,
    8057             :     V_MQSAD_U32_U8_ci   = 8042,
    8058             :     V_MQSAD_U32_U8_vi   = 8043,
    8059             :     V_MSAD_U8   = 8044,
    8060             :     V_MSAD_U8_si        = 8045,
    8061             :     V_MSAD_U8_vi        = 8046,
    8062             :     V_MULLIT_F32        = 8047,
    8063             :     V_MULLIT_F32_si     = 8048,
    8064             :     V_MUL_F16_dpp       = 8049,
    8065             :     V_MUL_F16_e32       = 8050,
    8066             :     V_MUL_F16_e32_vi    = 8051,
    8067             :     V_MUL_F16_e64       = 8052,
    8068             :     V_MUL_F16_e64_vi    = 8053,
    8069             :     V_MUL_F16_sdwa      = 8054,
    8070             :     V_MUL_F16_sdwa_gfx9 = 8055,
    8071             :     V_MUL_F16_sdwa_vi   = 8056,
    8072             :     V_MUL_F32_dpp       = 8057,
    8073             :     V_MUL_F32_e32       = 8058,
    8074             :     V_MUL_F32_e32_si    = 8059,
    8075             :     V_MUL_F32_e32_vi    = 8060,
    8076             :     V_MUL_F32_e64       = 8061,
    8077             :     V_MUL_F32_e64_si    = 8062,
    8078             :     V_MUL_F32_e64_vi    = 8063,
    8079             :     V_MUL_F32_sdwa      = 8064,
    8080             :     V_MUL_F32_sdwa_gfx9 = 8065,
    8081             :     V_MUL_F32_sdwa_vi   = 8066,
    8082             :     V_MUL_F64   = 8067,
    8083             :     V_MUL_F64_si        = 8068,
    8084             :     V_MUL_F64_vi        = 8069,
    8085             :     V_MUL_HI_I32        = 8070,
    8086             :     V_MUL_HI_I32_I24_dpp        = 8071,
    8087             :     V_MUL_HI_I32_I24_e32        = 8072,
    8088             :     V_MUL_HI_I32_I24_e32_si     = 8073,
    8089             :     V_MUL_HI_I32_I24_e32_vi     = 8074,
    8090             :     V_MUL_HI_I32_I24_e64        = 8075,
    8091             :     V_MUL_HI_I32_I24_e64_si     = 8076,
    8092             :     V_MUL_HI_I32_I24_e64_vi     = 8077,
    8093             :     V_MUL_HI_I32_I24_sdwa       = 8078,
    8094             :     V_MUL_HI_I32_I24_sdwa_gfx9  = 8079,
    8095             :     V_MUL_HI_I32_I24_sdwa_vi    = 8080,
    8096             :     V_MUL_HI_I32_si     = 8081,
    8097             :     V_MUL_HI_I32_vi     = 8082,
    8098             :     V_MUL_HI_U32        = 8083,
    8099             :     V_MUL_HI_U32_U24_dpp        = 8084,
    8100             :     V_MUL_HI_U32_U24_e32        = 8085,
    8101             :     V_MUL_HI_U32_U24_e32_si     = 8086,
    8102             :     V_MUL_HI_U32_U24_e32_vi     = 8087,
    8103             :     V_MUL_HI_U32_U24_e64        = 8088,
    8104             :     V_MUL_HI_U32_U24_e64_si     = 8089,
    8105             :     V_MUL_HI_U32_U24_e64_vi     = 8090,
    8106             :     V_MUL_HI_U32_U24_sdwa       = 8091,
    8107             :     V_MUL_HI_U32_U24_sdwa_gfx9  = 8092,
    8108             :     V_MUL_HI_U32_U24_sdwa_vi    = 8093,
    8109             :     V_MUL_HI_U32_si     = 8094,
    8110             :     V_MUL_HI_U32_vi     = 8095,
    8111             :     V_MUL_I32_I24_dpp   = 8096,
    8112             :     V_MUL_I32_I24_e32   = 8097,
    8113             :     V_MUL_I32_I24_e32_si        = 8098,
    8114             :     V_MUL_I32_I24_e32_vi        = 8099,
    8115             :     V_MUL_I32_I24_e64   = 8100,
    8116             :     V_MUL_I32_I24_e64_si        = 8101,
    8117             :     V_MUL_I32_I24_e64_vi        = 8102,
    8118             :     V_MUL_I32_I24_sdwa  = 8103,
    8119             :     V_MUL_I32_I24_sdwa_gfx9     = 8104,
    8120             :     V_MUL_I32_I24_sdwa_vi       = 8105,
    8121             :     V_MUL_LEGACY_F32_dpp        = 8106,
    8122             :     V_MUL_LEGACY_F32_e32        = 8107,
    8123             :     V_MUL_LEGACY_F32_e32_si     = 8108,
    8124             :     V_MUL_LEGACY_F32_e32_vi     = 8109,
    8125             :     V_MUL_LEGACY_F32_e64        = 8110,
    8126             :     V_MUL_LEGACY_F32_e64_si     = 8111,
    8127             :     V_MUL_LEGACY_F32_e64_vi     = 8112,
    8128             :     V_MUL_LEGACY_F32_sdwa       = 8113,
    8129             :     V_MUL_LEGACY_F32_sdwa_gfx9  = 8114,
    8130             :     V_MUL_LEGACY_F32_sdwa_vi    = 8115,
    8131             :     V_MUL_LO_I32        = 8116,
    8132             :     V_MUL_LO_I32_si     = 8117,
    8133             :     V_MUL_LO_I32_vi     = 8118,
    8134             :     V_MUL_LO_U16_dpp    = 8119,
    8135             :     V_MUL_LO_U16_e32    = 8120,
    8136             :     V_MUL_LO_U16_e32_vi = 8121,
    8137             :     V_MUL_LO_U16_e64    = 8122,
    8138             :     V_MUL_LO_U16_e64_vi = 8123,
    8139             :     V_MUL_LO_U16_sdwa   = 8124,
    8140             :     V_MUL_LO_U16_sdwa_gfx9      = 8125,
    8141             :     V_MUL_LO_U16_sdwa_vi        = 8126,
    8142             :     V_MUL_LO_U32        = 8127,
    8143             :     V_MUL_LO_U32_si     = 8128,
    8144             :     V_MUL_LO_U32_vi     = 8129,
    8145             :     V_MUL_U32_U24_dpp   = 8130,
    8146             :     V_MUL_U32_U24_e32   = 8131,
    8147             :     V_MUL_U32_U24_e32_si        = 8132,
    8148             :     V_MUL_U32_U24_e32_vi        = 8133,
    8149             :     V_MUL_U32_U24_e64   = 8134,
    8150             :     V_MUL_U32_U24_e64_si        = 8135,
    8151             :     V_MUL_U32_U24_e64_vi        = 8136,
    8152             :     V_MUL_U32_U24_sdwa  = 8137,
    8153             :     V_MUL_U32_U24_sdwa_gfx9     = 8138,
    8154             :     V_MUL_U32_U24_sdwa_vi       = 8139,
    8155             :     V_NOP_dpp   = 8140,
    8156             :     V_NOP_e32   = 8141,
    8157             :     V_NOP_e32_si        = 8142,
    8158             :     V_NOP_e32_vi        = 8143,
    8159             :     V_NOP_e64   = 8144,
    8160             :     V_NOP_e64_si        = 8145,
    8161             :     V_NOP_e64_vi        = 8146,
    8162             :     V_NOP_sdwa  = 8147,
    8163             :     V_NOP_sdwa_gfx9     = 8148,
    8164             :     V_NOP_sdwa_vi       = 8149,
    8165             :     V_NOT_B32_dpp       = 8150,
    8166             :     V_NOT_B32_e32       = 8151,
    8167             :     V_NOT_B32_e32_si    = 8152,
    8168             :     V_NOT_B32_e32_vi    = 8153,
    8169             :     V_NOT_B32_e64       = 8154,
    8170             :     V_NOT_B32_e64_si    = 8155,
    8171             :     V_NOT_B32_e64_vi    = 8156,
    8172             :     V_NOT_B32_sdwa      = 8157,
    8173             :     V_NOT_B32_sdwa_gfx9 = 8158,
    8174             :     V_NOT_B32_sdwa_vi   = 8159,
    8175             :     V_OR3_B32   = 8160,
    8176             :     V_OR3_B32_vi        = 8161,
    8177             :     V_OR_B32_dpp        = 8162,
    8178             :     V_OR_B32_e32        = 8163,
    8179             :     V_OR_B32_e32_si     = 8164,
    8180             :     V_OR_B32_e32_vi     = 8165,
    8181             :     V_OR_B32_e64        = 8166,
    8182             :     V_OR_B32_e64_si     = 8167,
    8183             :     V_OR_B32_e64_vi     = 8168,
    8184             :     V_OR_B32_sdwa       = 8169,
    8185             :     V_OR_B32_sdwa_gfx9  = 8170,
    8186             :     V_OR_B32_sdwa_vi    = 8171,
    8187             :     V_PACK_B32_F16      = 8172,
    8188             :     V_PACK_B32_F16_vi   = 8173,
    8189             :     V_PERM_B32  = 8174,
    8190             :     V_PERM_B32_vi       = 8175,
    8191             :     V_PK_ADD_F16        = 8176,
    8192             :     V_PK_ADD_F16_vi     = 8177,
    8193             :     V_PK_ADD_I16        = 8178,
    8194             :     V_PK_ADD_I16_vi     = 8179,
    8195             :     V_PK_ADD_U16        = 8180,
    8196             :     V_PK_ADD_U16_vi     = 8181,
    8197             :     V_PK_ASHRREV_I16    = 8182,
    8198             :     V_PK_ASHRREV_I16_vi = 8183,
    8199             :     V_PK_FMA_F16        = 8184,
    8200             :     V_PK_FMA_F16_vi     = 8185,
    8201             :     V_PK_LSHLREV_B16    = 8186,
    8202             :     V_PK_LSHLREV_B16_vi = 8187,
    8203             :     V_PK_LSHRREV_B16    = 8188,
    8204             :     V_PK_LSHRREV_B16_vi = 8189,
    8205             :     V_PK_MAD_I16        = 8190,
    8206             :     V_PK_MAD_I16_vi     = 8191,
    8207             :     V_PK_MAD_U16        = 8192,
    8208             :     V_PK_MAD_U16_vi     = 8193,
    8209             :     V_PK_MAX_F16        = 8194,
    8210             :     V_PK_MAX_F16_vi     = 8195,
    8211             :     V_PK_MAX_I16        = 8196,
    8212             :     V_PK_MAX_I16_vi     = 8197,
    8213             :     V_PK_MAX_U16        = 8198,
    8214             :     V_PK_MAX_U16_vi     = 8199,
    8215             :     V_PK_MIN_F16        = 8200,
    8216             :     V_PK_MIN_F16_vi     = 8201,
    8217             :     V_PK_MIN_I16        = 8202,
    8218             :     V_PK_MIN_I16_vi     = 8203,
    8219             :     V_PK_MIN_U16        = 8204,
    8220             :     V_PK_MIN_U16_vi     = 8205,
    8221             :     V_PK_MUL_F16        = 8206,
    8222             :     V_PK_MUL_F16_vi     = 8207,
    8223             :     V_PK_MUL_LO_U16     = 8208,
    8224             :     V_PK_MUL_LO_U16_vi  = 8209,
    8225             :     V_PK_SUB_I16        = 8210,
    8226             :     V_PK_SUB_I16_vi     = 8211,
    8227             :     V_PK_SUB_U16        = 8212,
    8228             :     V_PK_SUB_U16_vi     = 8213,
    8229             :     V_QSAD_PK_U16_U8    = 8214,
    8230             :     V_QSAD_PK_U16_U8_ci = 8215,
    8231             :     V_QSAD_PK_U16_U8_vi = 8216,
    8232             :     V_RCP_CLAMP_F32_e32 = 8217,
    8233             :     V_RCP_CLAMP_F32_e32_si      = 8218,
    8234             :     V_RCP_CLAMP_F32_e64 = 8219,
    8235             :     V_RCP_CLAMP_F32_e64_si      = 8220,
    8236             :     V_RCP_CLAMP_F32_sdwa        = 8221,
    8237             :     V_RCP_CLAMP_F64_e32 = 8222,
    8238             :     V_RCP_CLAMP_F64_e32_si      = 8223,
    8239             :     V_RCP_CLAMP_F64_e64 = 8224,
    8240             :     V_RCP_CLAMP_F64_e64_si      = 8225,
    8241             :     V_RCP_CLAMP_F64_sdwa        = 8226,
    8242             :     V_RCP_F16_dpp       = 8227,
    8243             :     V_RCP_F16_e32       = 8228,
    8244             :     V_RCP_F16_e32_vi    = 8229,
    8245             :     V_RCP_F16_e64       = 8230,
    8246             :     V_RCP_F16_e64_vi    = 8231,
    8247             :     V_RCP_F16_sdwa      = 8232,
    8248             :     V_RCP_F16_sdwa_gfx9 = 8233,
    8249             :     V_RCP_F16_sdwa_vi   = 8234,
    8250             :     V_RCP_F32_dpp       = 8235,
    8251             :     V_RCP_F32_e32       = 8236,
    8252             :     V_RCP_F32_e32_si    = 8237,
    8253             :     V_RCP_F32_e32_vi    = 8238,
    8254             :     V_RCP_F32_e64       = 8239,
    8255             :     V_RCP_F32_e64_si    = 8240,
    8256             :     V_RCP_F32_e64_vi    = 8241,
    8257             :     V_RCP_F32_sdwa      = 8242,
    8258             :     V_RCP_F32_sdwa_gfx9 = 8243,
    8259             :     V_RCP_F32_sdwa_vi   = 8244,
    8260             :     V_RCP_F64_dpp       = 8245,
    8261             :     V_RCP_F64_e32       = 8246,
    8262             :     V_RCP_F64_e32_si    = 8247,
    8263             :     V_RCP_F64_e32_vi    = 8248,
    8264             :     V_RCP_F64_e64       = 8249,
    8265             :     V_RCP_F64_e64_si    = 8250,
    8266             :     V_RCP_F64_e64_vi    = 8251,
    8267             :     V_RCP_F64_sdwa      = 8252,
    8268             :     V_RCP_F64_sdwa_gfx9 = 8253,
    8269             :     V_RCP_F64_sdwa_vi   = 8254,
    8270             :     V_RCP_IFLAG_F32_dpp = 8255,
    8271             :     V_RCP_IFLAG_F32_e32 = 8256,
    8272             :     V_RCP_IFLAG_F32_e32_si      = 8257,
    8273             :     V_RCP_IFLAG_F32_e32_vi      = 8258,
    8274             :     V_RCP_IFLAG_F32_e64 = 8259,
    8275             :     V_RCP_IFLAG_F32_e64_si      = 8260,
    8276             :     V_RCP_IFLAG_F32_e64_vi      = 8261,
    8277             :     V_RCP_IFLAG_F32_sdwa        = 8262,
    8278             :     V_RCP_IFLAG_F32_sdwa_gfx9   = 8263,
    8279             :     V_RCP_IFLAG_F32_sdwa_vi     = 8264,
    8280             :     V_RCP_LEGACY_F32_e32        = 8265,
    8281             :     V_RCP_LEGACY_F32_e32_si     = 8266,
    8282             :     V_RCP_LEGACY_F32_e64        = 8267,
    8283             :     V_RCP_LEGACY_F32_e64_si     = 8268,
    8284             :     V_RCP_LEGACY_F32_sdwa       = 8269,
    8285             :     V_READFIRSTLANE_B32 = 8270,
    8286             :     V_READLANE_B32      = 8271,
    8287             :     V_READLANE_B32_si   = 8272,
    8288             :     V_READLANE_B32_vi   = 8273,
    8289             :     V_RNDNE_F16_dpp     = 8274,
    8290             :     V_RNDNE_F16_e32     = 8275,
    8291             :     V_RNDNE_F16_e32_vi  = 8276,
    8292             :     V_RNDNE_F16_e64     = 8277,
    8293             :     V_RNDNE_F16_e64_vi  = 8278,
    8294             :     V_RNDNE_F16_sdwa    = 8279,
    8295             :     V_RNDNE_F16_sdwa_gfx9       = 8280,
    8296             :     V_RNDNE_F16_sdwa_vi = 8281,
    8297             :     V_RNDNE_F32_dpp     = 8282,
    8298             :     V_RNDNE_F32_e32     = 8283,
    8299             :     V_RNDNE_F32_e32_si  = 8284,
    8300             :     V_RNDNE_F32_e32_vi  = 8285,
    8301             :     V_RNDNE_F32_e64     = 8286,
    8302             :     V_RNDNE_F32_e64_si  = 8287,
    8303             :     V_RNDNE_F32_e64_vi  = 8288,
    8304             :     V_RNDNE_F32_sdwa    = 8289,
    8305             :     V_RNDNE_F32_sdwa_gfx9       = 8290,
    8306             :     V_RNDNE_F32_sdwa_vi = 8291,
    8307             :     V_RNDNE_F64_dpp     = 8292,
    8308             :     V_RNDNE_F64_e32     = 8293,
    8309             :     V_RNDNE_F64_e32_ci  = 8294,
    8310             :     V_RNDNE_F64_e32_vi  = 8295,
    8311             :     V_RNDNE_F64_e64     = 8296,
    8312             :     V_RNDNE_F64_e64_ci  = 8297,
    8313             :     V_RNDNE_F64_e64_vi  = 8298,
    8314             :     V_RNDNE_F64_sdwa    = 8299,
    8315             :     V_RNDNE_F64_sdwa_gfx9       = 8300,
    8316             :     V_RNDNE_F64_sdwa_vi = 8301,
    8317             :     V_RSQ_CLAMP_F32_e32 = 8302,
    8318             :     V_RSQ_CLAMP_F32_e32_si      = 8303,
    8319             :     V_RSQ_CLAMP_F32_e64 = 8304,
    8320             :     V_RSQ_CLAMP_F32_e64_si      = 8305,
    8321             :     V_RSQ_CLAMP_F32_sdwa        = 8306,
    8322             :     V_RSQ_CLAMP_F64_e32 = 8307,
    8323             :     V_RSQ_CLAMP_F64_e32_si      = 8308,
    8324             :     V_RSQ_CLAMP_F64_e64 = 8309,
    8325             :     V_RSQ_CLAMP_F64_e64_si      = 8310,
    8326             :     V_RSQ_CLAMP_F64_sdwa        = 8311,
    8327             :     V_RSQ_F16_dpp       = 8312,
    8328             :     V_RSQ_F16_e32       = 8313,
    8329             :     V_RSQ_F16_e32_vi    = 8314,
    8330             :     V_RSQ_F16_e64       = 8315,
    8331             :     V_RSQ_F16_e64_vi    = 8316,
    8332             :     V_RSQ_F16_sdwa      = 8317,
    8333             :     V_RSQ_F16_sdwa_gfx9 = 8318,
    8334             :     V_RSQ_F16_sdwa_vi   = 8319,
    8335             :     V_RSQ_F32_dpp       = 8320,
    8336             :     V_RSQ_F32_e32       = 8321,
    8337             :     V_RSQ_F32_e32_si    = 8322,
    8338             :     V_RSQ_F32_e32_vi    = 8323,
    8339             :     V_RSQ_F32_e64       = 8324,
    8340             :     V_RSQ_F32_e64_si    = 8325,
    8341             :     V_RSQ_F32_e64_vi    = 8326,
    8342             :     V_RSQ_F32_sdwa      = 8327,
    8343             :     V_RSQ_F32_sdwa_gfx9 = 8328,
    8344             :     V_RSQ_F32_sdwa_vi   = 8329,
    8345             :     V_RSQ_F64_dpp       = 8330,
    8346             :     V_RSQ_F64_e32       = 8331,
    8347             :     V_RSQ_F64_e32_si    = 8332,
    8348             :     V_RSQ_F64_e32_vi    = 8333,
    8349             :     V_RSQ_F64_e64       = 8334,
    8350             :     V_RSQ_F64_e64_si    = 8335,
    8351             :     V_RSQ_F64_e64_vi    = 8336,
    8352             :     V_RSQ_F64_sdwa      = 8337,
    8353             :     V_RSQ_F64_sdwa_gfx9 = 8338,
    8354             :     V_RSQ_F64_sdwa_vi   = 8339,
    8355             :     V_RSQ_LEGACY_F32_e32        = 8340,
    8356             :     V_RSQ_LEGACY_F32_e32_si     = 8341,
    8357             :     V_RSQ_LEGACY_F32_e64        = 8342,
    8358             :     V_RSQ_LEGACY_F32_e64_si     = 8343,
    8359             :     V_RSQ_LEGACY_F32_sdwa       = 8344,
    8360             :     V_SAD_HI_U8 = 8345,
    8361             :     V_SAD_HI_U8_si      = 8346,
    8362             :     V_SAD_HI_U8_vi      = 8347,
    8363             :     V_SAD_U16   = 8348,
    8364             :     V_SAD_U16_si        = 8349,
    8365             :     V_SAD_U16_vi        = 8350,
    8366             :     V_SAD_U32   = 8351,
    8367             :     V_SAD_U32_si        = 8352,
    8368             :     V_SAD_U32_vi        = 8353,
    8369             :     V_SAD_U8    = 8354,
    8370             :     V_SAD_U8_si = 8355,
    8371             :     V_SAD_U8_vi = 8356,
    8372             :     V_SET_INACTIVE_B32  = 8357,
    8373             :     V_SET_INACTIVE_B64  = 8358,
    8374             :     V_SIN_F16_dpp       = 8359,
    8375             :     V_SIN_F16_e32       = 8360,
    8376             :     V_SIN_F16_e32_vi    = 8361,
    8377             :     V_SIN_F16_e64       = 8362,
    8378             :     V_SIN_F16_e64_vi    = 8363,
    8379             :     V_SIN_F16_sdwa      = 8364,
    8380             :     V_SIN_F16_sdwa_gfx9 = 8365,
    8381             :     V_SIN_F16_sdwa_vi   = 8366,
    8382             :     V_SIN_F32_dpp       = 8367,
    8383             :     V_SIN_F32_e32       = 8368,
    8384             :     V_SIN_F32_e32_si    = 8369,
    8385             :     V_SIN_F32_e32_vi    = 8370,
    8386             :     V_SIN_F32_e64       = 8371,
    8387             :     V_SIN_F32_e64_si    = 8372,
    8388             :     V_SIN_F32_e64_vi    = 8373,
    8389             :     V_SIN_F32_sdwa      = 8374,
    8390             :     V_SIN_F32_sdwa_gfx9 = 8375,
    8391             :     V_SIN_F32_sdwa_vi   = 8376,
    8392             :     V_SQRT_F16_dpp      = 8377,
    8393             :     V_SQRT_F16_e32      = 8378,
    8394             :     V_SQRT_F16_e32_vi   = 8379,
    8395             :     V_SQRT_F16_e64      = 8380,
    8396             :     V_SQRT_F16_e64_vi   = 8381,
    8397             :     V_SQRT_F16_sdwa     = 8382,
    8398             :     V_SQRT_F16_sdwa_gfx9        = 8383,
    8399             :     V_SQRT_F16_sdwa_vi  = 8384,
    8400             :     V_SQRT_F32_dpp      = 8385,
    8401             :     V_SQRT_F32_e32      = 8386,
    8402             :     V_SQRT_F32_e32_si   = 8387,
    8403             :     V_SQRT_F32_e32_vi   = 8388,
    8404             :     V_SQRT_F32_e64      = 8389,
    8405             :     V_SQRT_F32_e64_si   = 8390,
    8406             :     V_SQRT_F32_e64_vi   = 8391,
    8407             :     V_SQRT_F32_sdwa     = 8392,
    8408             :     V_SQRT_F32_sdwa_gfx9        = 8393,
    8409             :     V_SQRT_F32_sdwa_vi  = 8394,
    8410             :     V_SQRT_F64_dpp      = 8395,
    8411             :     V_SQRT_F64_e32      = 8396,
    8412             :     V_SQRT_F64_e32_si   = 8397,
    8413             :     V_SQRT_F64_e32_vi   = 8398,
    8414             :     V_SQRT_F64_e64      = 8399,
    8415             :     V_SQRT_F64_e64_si   = 8400,
    8416             :     V_SQRT_F64_e64_vi   = 8401,
    8417             :     V_SQRT_F64_sdwa     = 8402,
    8418             :     V_SQRT_F64_sdwa_gfx9        = 8403,
    8419             :     V_SQRT_F64_sdwa_vi  = 8404,
    8420             :     V_SUBBREV_U32_dpp   = 8405,
    8421             :     V_SUBBREV_U32_e32   = 8406,
    8422             :     V_SUBBREV_U32_e32_si        = 8407,
    8423             :     V_SUBBREV_U32_e32_vi        = 8408,
    8424             :     V_SUBBREV_U32_e64   = 8409,
    8425             :     V_SUBBREV_U32_e64_si        = 8410,
    8426             :     V_SUBBREV_U32_e64_vi        = 8411,
    8427             :     V_SUBBREV_U32_sdwa  = 8412,
    8428             :     V_SUBBREV_U32_sdwa_gfx9     = 8413,
    8429             :     V_SUBBREV_U32_sdwa_vi       = 8414,
    8430             :     V_SUBB_U32_dpp      = 8415,
    8431             :     V_SUBB_U32_e32      = 8416,
    8432             :     V_SUBB_U32_e32_si   = 8417,
    8433             :     V_SUBB_U32_e32_vi   = 8418,
    8434             :     V_SUBB_U32_e64      = 8419,
    8435             :     V_SUBB_U32_e64_si   = 8420,
    8436             :     V_SUBB_U32_e64_vi   = 8421,
    8437             :     V_SUBB_U32_sdwa     = 8422,
    8438             :     V_SUBB_U32_sdwa_gfx9        = 8423,
    8439             :     V_SUBB_U32_sdwa_vi  = 8424,
    8440             :     V_SUBREV_F16_dpp    = 8425,
    8441             :     V_SUBREV_F16_e32    = 8426,
    8442             :     V_SUBREV_F16_e32_vi = 8427,
    8443             :     V_SUBREV_F16_e64    = 8428,
    8444             :     V_SUBREV_F16_e64_vi = 8429,
    8445             :     V_SUBREV_F16_sdwa   = 8430,
    8446             :     V_SUBREV_F16_sdwa_gfx9      = 8431,
    8447             :     V_SUBREV_F16_sdwa_vi        = 8432,
    8448             :     V_SUBREV_F32_dpp    = 8433,
    8449             :     V_SUBREV_F32_e32    = 8434,
    8450             :     V_SUBREV_F32_e32_si = 8435,
    8451             :     V_SUBREV_F32_e32_vi = 8436,
    8452             :     V_SUBREV_F32_e64    = 8437,
    8453             :     V_SUBREV_F32_e64_si = 8438,
    8454             :     V_SUBREV_F32_e64_vi = 8439,
    8455             :     V_SUBREV_F32_sdwa   = 8440,
    8456             :     V_SUBREV_F32_sdwa_gfx9      = 8441,
    8457             :     V_SUBREV_F32_sdwa_vi        = 8442,
    8458             :     V_SUBREV_I32_dpp    = 8443,
    8459             :     V_SUBREV_I32_e32    = 8444,
    8460             :     V_SUBREV_I32_e32_si = 8445,
    8461             :     V_SUBREV_I32_e32_vi = 8446,
    8462             :     V_SUBREV_I32_e64    = 8447,
    8463             :     V_SUBREV_I32_e64_si = 8448,
    8464             :     V_SUBREV_I32_e64_vi = 8449,
    8465             :     V_SUBREV_I32_sdwa   = 8450,
    8466             :     V_SUBREV_I32_sdwa_gfx9      = 8451,
    8467             :     V_SUBREV_I32_sdwa_vi        = 8452,
    8468             :     V_SUBREV_U16_dpp    = 8453,
    8469             :     V_SUBREV_U16_e32    = 8454,
    8470             :     V_SUBREV_U16_e32_vi = 8455,
    8471             :     V_SUBREV_U16_e64    = 8456,
    8472             :     V_SUBREV_U16_e64_vi = 8457,
    8473             :     V_SUBREV_U16_sdwa   = 8458,
    8474             :     V_SUBREV_U16_sdwa_gfx9      = 8459,
    8475             :     V_SUBREV_U16_sdwa_vi        = 8460,
    8476             :     V_SUBREV_U32_dpp    = 8461,
    8477             :     V_SUBREV_U32_e32    = 8462,
    8478             :     V_SUBREV_U32_e32_vi = 8463,
    8479             :     V_SUBREV_U32_e64    = 8464,
    8480             :     V_SUBREV_U32_e64_vi = 8465,
    8481             :     V_SUBREV_U32_sdwa   = 8466,
    8482             :     V_SUBREV_U32_sdwa_gfx9      = 8467,
    8483             :     V_SUBREV_U32_sdwa_vi        = 8468,
    8484             :     V_SUB_F16_dpp       = 8469,
    8485             :     V_SUB_F16_e32       = 8470,
    8486             :     V_SUB_F16_e32_vi    = 8471,
    8487             :     V_SUB_F16_e64       = 8472,
    8488             :     V_SUB_F16_e64_vi    = 8473,
    8489             :     V_SUB_F16_sdwa      = 8474,
    8490             :     V_SUB_F16_sdwa_gfx9 = 8475,
    8491             :     V_SUB_F16_sdwa_vi   = 8476,
    8492             :     V_SUB_F32_dpp       = 8477,
    8493             :     V_SUB_F32_e32       = 8478,
    8494             :     V_SUB_F32_e32_si    = 8479,
    8495             :     V_SUB_F32_e32_vi    = 8480,
    8496             :     V_SUB_F32_e64       = 8481,
    8497             :     V_SUB_F32_e64_si    = 8482,
    8498             :     V_SUB_F32_e64_vi    = 8483,
    8499             :     V_SUB_F32_sdwa      = 8484,
    8500             :     V_SUB_F32_sdwa_gfx9 = 8485,
    8501             :     V_SUB_F32_sdwa_vi   = 8486,
    8502             :     V_SUB_I16   = 8487,
    8503             :     V_SUB_I16_vi        = 8488,
    8504             :     V_SUB_I32_dpp       = 8489,
    8505             :     V_SUB_I32_e32       = 8490,
    8506             :     V_SUB_I32_e32_si    = 8491,
    8507             :     V_SUB_I32_e32_vi    = 8492,
    8508             :     V_SUB_I32_e64       = 8493,
    8509             :     V_SUB_I32_e64_si    = 8494,
    8510             :     V_SUB_I32_e64_vi    = 8495,
    8511             :     V_SUB_I32_sdwa      = 8496,
    8512             :     V_SUB_I32_sdwa_gfx9 = 8497,
    8513             :     V_SUB_I32_sdwa_vi   = 8498,
    8514             :     V_SUB_U16_dpp       = 8499,
    8515             :     V_SUB_U16_e32       = 8500,
    8516             :     V_SUB_U16_e32_vi    = 8501,
    8517             :     V_SUB_U16_e64       = 8502,
    8518             :     V_SUB_U16_e64_vi    = 8503,
    8519             :     V_SUB_U16_sdwa      = 8504,
    8520             :     V_SUB_U16_sdwa_gfx9 = 8505,
    8521             :     V_SUB_U16_sdwa_vi   = 8506,
    8522             :     V_SUB_U32_dpp       = 8507,
    8523             :     V_SUB_U32_e32       = 8508,
    8524             :     V_SUB_U32_e32_vi    = 8509,
    8525             :     V_SUB_U32_e64       = 8510,
    8526             :     V_SUB_U32_e64_vi    = 8511,
    8527             :     V_SUB_U32_sdwa      = 8512,
    8528             :     V_SUB_U32_sdwa_gfx9 = 8513,
    8529             :     V_SUB_U32_sdwa_vi   = 8514,
    8530             :     V_SWAP_B32  = 8515,
    8531             :     V_SWAP_B32_vi       = 8516,
    8532             :     V_TRIG_PREOP_F64    = 8517,
    8533             :     V_TRIG_PREOP_F64_si = 8518,
    8534             :     V_TRIG_PREOP_F64_vi = 8519,
    8535             :     V_TRUNC_F16_dpp     = 8520,
    8536             :     V_TRUNC_F16_e32     = 8521,
    8537             :     V_TRUNC_F16_e32_vi  = 8522,
    8538             :     V_TRUNC_F16_e64     = 8523,
    8539             :     V_TRUNC_F16_e64_vi  = 8524,
    8540             :     V_TRUNC_F16_sdwa    = 8525,
    8541             :     V_TRUNC_F16_sdwa_gfx9       = 8526,
    8542             :     V_TRUNC_F16_sdwa_vi = 8527,
    8543             :     V_TRUNC_F32_dpp     = 8528,
    8544             :     V_TRUNC_F32_e32     = 8529,
    8545             :     V_TRUNC_F32_e32_si  = 8530,
    8546             :     V_TRUNC_F32_e32_vi  = 8531,
    8547             :     V_TRUNC_F32_e64     = 8532,
    8548             :     V_TRUNC_F32_e64_si  = 8533,
    8549             :     V_TRUNC_F32_e64_vi  = 8534,
    8550             :     V_TRUNC_F32_sdwa    = 8535,
    8551             :     V_TRUNC_F32_sdwa_gfx9       = 8536,
    8552             :     V_TRUNC_F32_sdwa_vi = 8537,
    8553             :     V_TRUNC_F64_dpp     = 8538,
    8554             :     V_TRUNC_F64_e32     = 8539,
    8555             :     V_TRUNC_F64_e32_ci  = 8540,
    8556             :     V_TRUNC_F64_e32_vi  = 8541,
    8557             :     V_TRUNC_F64_e64     = 8542,
    8558             :     V_TRUNC_F64_e64_ci  = 8543,
    8559             :     V_TRUNC_F64_e64_vi  = 8544,
    8560             :     V_TRUNC_F64_sdwa    = 8545,
    8561             :     V_TRUNC_F64_sdwa_gfx9       = 8546,
    8562             :     V_TRUNC_F64_sdwa_vi = 8547,
    8563             :     V_WRITELANE_B32     = 8548,
    8564             :     V_WRITELANE_B32_si  = 8549,
    8565             :     V_WRITELANE_B32_vi  = 8550,
    8566             :     V_XAD_U32   = 8551,
    8567             :     V_XAD_U32_vi        = 8552,
    8568             :     V_XOR_B32_dpp       = 8553,
    8569             :     V_XOR_B32_e32       = 8554,
    8570             :     V_XOR_B32_e32_si    = 8555,
    8571             :     V_XOR_B32_e32_vi    = 8556,
    8572             :     V_XOR_B32_e64       = 8557,
    8573             :     V_XOR_B32_e64_si    = 8558,
    8574             :     V_XOR_B32_e64_vi    = 8559,
    8575             :     V_XOR_B32_sdwa      = 8560,
    8576             :     V_XOR_B32_sdwa_gfx9 = 8561,
    8577             :     V_XOR_B32_sdwa_vi   = 8562,
    8578             :     WAVE_BARRIER        = 8563,
    8579             :     WHILELOOP   = 8564,
    8580             :     WHILE_LOOP_EG       = 8565,
    8581             :     WHILE_LOOP_R600     = 8566,
    8582             :     WQM = 8567,
    8583             :     WWM = 8568,
    8584             :     XOR_INT     = 8569,
    8585             :     INSTRUCTION_LIST_END = 8570
    8586             :   };
    8587             : 
    8588             : namespace Sched {
    8589             :   enum {
    8590             :     NoInstrModel        = 0,
    8591             :     AnyALU      = 1,
    8592             :     NullALU_Write32Bit  = 2,
    8593             :     NullALU     = 3,
    8594             :     VecALU      = 4,
    8595             :     NullALU_WriteVMEM   = 5,
    8596             :     TransALU    = 6,
    8597             :     NullALU_WriteLDS    = 7,
    8598             :     NullALU_WriteExport = 8,
    8599             :     XALU        = 9,
    8600             :     NullALU_WriteBranch = 10,
    8601             :     NullALU_WriteSALU   = 11,
    8602             :     NullALU_WriteBarrier        = 12,
    8603             :     NullALU_WriteSMEM   = 13,
    8604             :     NullALU_Write32Bit_WriteSALU        = 14,
    8605             :     NullALU_WriteDoubleAdd      = 15,
    8606             :     NullALU_Write64Bit  = 16,
    8607             :     NullALU_WriteQuarterRate32  = 17,
    8608             :     NullALU_WriteFloatFMA       = 18,
    8609             :     NullALU_WriteDouble = 19,
    8610             :     NullALU_WriteFloatFMA_WriteSALU     = 20,
    8611             :     NullALU_WriteDouble_WriteSALU       = 21,
    8612             :     NullALU_Write64Bit_Write64Bit       = 22,
    8613             :     COPY        = 23,
    8614             :     SCHED_LIST_END = 24
    8615             :   };
    8616             : } // end Sched namespace
    8617             : } // end AMDGPU namespace
    8618             : } // end llvm namespace
    8619             : #endif // GET_INSTRINFO_ENUM
    8620             : 
    8621             : #ifdef GET_INSTRINFO_MC_DESC
    8622             : #undef GET_INSTRINFO_MC_DESC
    8623             : namespace llvm {
    8624             : 
    8625             : static const MCPhysReg ImplicitList1[] = { AMDGPU::EXEC, 0 };
    8626             : static const MCPhysReg ImplicitList2[] = { AMDGPU::M0, AMDGPU::EXEC, 0 };
    8627             : static const MCPhysReg ImplicitList3[] = { AMDGPU::EXEC, AMDGPU::FLAT_SCR, 0 };
    8628             : static const MCPhysReg ImplicitList4[] = { AMDGPU::SCC, 0 };
    8629             : static const MCPhysReg ImplicitList5[] = { AMDGPU::EXEC, AMDGPU::SCC, 0 };
    8630             : static const MCPhysReg ImplicitList6[] = { AMDGPU::EXEC, AMDGPU::VCC, 0 };
    8631             : static const MCPhysReg ImplicitList7[] = { AMDGPU::M0, 0 };
    8632             : static const MCPhysReg ImplicitList8[] = { AMDGPU::VCC, 0 };
    8633             : static const MCPhysReg ImplicitList9[] = { AMDGPU::EXEC, AMDGPU::M0, 0 };
    8634             : static const MCPhysReg ImplicitList10[] = { AMDGPU::VCC, AMDGPU::EXEC, 0 };
    8635             : 
    8636             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8637             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8638             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8639             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8640             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8641             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8642             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8643             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8644             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
    8645             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8646             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    8647             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    8648             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8649             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8650             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8651             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    8652             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    8653             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    8654             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    8655             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    8656             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    8657             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    8658             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8659             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    8660             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    8661             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    8662             : static const MCOperandInfo OperandInfo28[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8663             : static const MCOperandInfo OperandInfo29[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8664             : static const MCOperandInfo OperandInfo30[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8665             : static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8666             : static const MCOperandInfo OperandInfo32[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8667             : static const MCOperandInfo OperandInfo33[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8668             : static const MCOperandInfo OperandInfo34[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8669             : static const MCOperandInfo OperandInfo35[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8670             : static const MCOperandInfo OperandInfo36[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8671             : static const MCOperandInfo OperandInfo37[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8672             : static const MCOperandInfo OperandInfo38[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8673             : static const MCOperandInfo OperandInfo39[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8674             : static const MCOperandInfo OperandInfo40[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8675             : static const MCOperandInfo OperandInfo41[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8676             : static const MCOperandInfo OperandInfo42[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8677             : static const MCOperandInfo OperandInfo43[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8678             : static const MCOperandInfo OperandInfo44[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8679             : static const MCOperandInfo OperandInfo45[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8680             : static const MCOperandInfo OperandInfo46[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8681             : static const MCOperandInfo OperandInfo47[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8682             : static const MCOperandInfo OperandInfo48[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8683             : static const MCOperandInfo OperandInfo49[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8684             : static const MCOperandInfo OperandInfo50[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8685             : static const MCOperandInfo OperandInfo51[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8686             : static const MCOperandInfo OperandInfo52[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8687             : static const MCOperandInfo OperandInfo53[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8688             : static const MCOperandInfo OperandInfo54[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8689             : static const MCOperandInfo OperandInfo55[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8690             : static const MCOperandInfo OperandInfo56[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8691             : static const MCOperandInfo OperandInfo57[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8692             : static const MCOperandInfo OperandInfo58[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8693             : static const MCOperandInfo OperandInfo59[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8694             : static const MCOperandInfo OperandInfo60[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8695             : static const MCOperandInfo OperandInfo61[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8696             : static const MCOperandInfo OperandInfo62[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8697             : static const MCOperandInfo OperandInfo63[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8698             : static const MCOperandInfo OperandInfo64[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8699             : static const MCOperandInfo OperandInfo65[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8700             : static const MCOperandInfo OperandInfo66[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8701             : static const MCOperandInfo OperandInfo67[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8702             : static const MCOperandInfo OperandInfo68[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8703             : static const MCOperandInfo OperandInfo69[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8704             : static const MCOperandInfo OperandInfo70[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8705             : static const MCOperandInfo OperandInfo71[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8706             : static const MCOperandInfo OperandInfo72[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8707             : static const MCOperandInfo OperandInfo73[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8708             : static const MCOperandInfo OperandInfo74[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8709             : static const MCOperandInfo OperandInfo75[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8710             : static const MCOperandInfo OperandInfo76[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8711             : static const MCOperandInfo OperandInfo77[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8712             : static const MCOperandInfo OperandInfo78[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8713             : static const MCOperandInfo OperandInfo79[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8714             : static const MCOperandInfo OperandInfo80[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8715             : static const MCOperandInfo OperandInfo81[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8716             : static const MCOperandInfo OperandInfo82[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8717             : static const MCOperandInfo OperandInfo83[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8718             : static const MCOperandInfo OperandInfo84[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8719             : static const MCOperandInfo OperandInfo85[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8720             : static const MCOperandInfo OperandInfo86[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8721             : static const MCOperandInfo OperandInfo87[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8722             : static const MCOperandInfo OperandInfo88[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8723             : static const MCOperandInfo OperandInfo89[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8724             : static const MCOperandInfo OperandInfo90[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8725             : static const MCOperandInfo OperandInfo91[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8726             : static const MCOperandInfo OperandInfo92[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8727             : static const MCOperandInfo OperandInfo93[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8728             : static const MCOperandInfo OperandInfo94[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8729             : static const MCOperandInfo OperandInfo95[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8730             : static const MCOperandInfo OperandInfo96[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8731             : static const MCOperandInfo OperandInfo97[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8732             : static const MCOperandInfo OperandInfo98[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8733             : static const MCOperandInfo OperandInfo99[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8734             : static const MCOperandInfo OperandInfo100[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8735             : static const MCOperandInfo OperandInfo101[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8736             : static const MCOperandInfo OperandInfo102[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8737             : static const MCOperandInfo OperandInfo103[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8738             : static const MCOperandInfo OperandInfo104[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8739             : static const MCOperandInfo OperandInfo105[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8740             : static const MCOperandInfo OperandInfo106[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8741             : static const MCOperandInfo OperandInfo107[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8742             : static const MCOperandInfo OperandInfo108[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8743             : static const MCOperandInfo OperandInfo109[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8744             : static const MCOperandInfo OperandInfo110[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8745             : static const MCOperandInfo OperandInfo111[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8746             : static const MCOperandInfo OperandInfo112[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8747             : static const MCOperandInfo OperandInfo113[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8748             : static const MCOperandInfo OperandInfo114[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8749             : static const MCOperandInfo OperandInfo115[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8750             : static const MCOperandInfo OperandInfo116[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8751             : static const MCOperandInfo OperandInfo117[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8752             : static const MCOperandInfo OperandInfo118[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8753             : static const MCOperandInfo OperandInfo119[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8754             : static const MCOperandInfo OperandInfo120[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8755             : static const MCOperandInfo OperandInfo121[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8756             : static const MCOperandInfo OperandInfo122[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8757             : static const MCOperandInfo OperandInfo123[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8758             : static const MCOperandInfo OperandInfo124[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8759             : static const MCOperandInfo OperandInfo125[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8760             : static const MCOperandInfo OperandInfo126[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8761             : static const MCOperandInfo OperandInfo127[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8762             : static const MCOperandInfo OperandInfo128[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8763             : static const MCOperandInfo OperandInfo129[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8764             : static const MCOperandInfo OperandInfo130[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8765             : static const MCOperandInfo OperandInfo131[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8766             : static const MCOperandInfo OperandInfo132[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8767             : static const MCOperandInfo OperandInfo133[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8768             : static const MCOperandInfo OperandInfo134[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8769             : static const MCOperandInfo OperandInfo135[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8770             : static const MCOperandInfo OperandInfo136[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8771             : static const MCOperandInfo OperandInfo137[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8772             : static const MCOperandInfo OperandInfo138[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8773             : static const MCOperandInfo OperandInfo139[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8774             : static const MCOperandInfo OperandInfo140[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8775             : static const MCOperandInfo OperandInfo141[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8776             : static const MCOperandInfo OperandInfo142[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8777             : static const MCOperandInfo OperandInfo143[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8778             : static const MCOperandInfo OperandInfo144[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8779             : static const MCOperandInfo OperandInfo145[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8780             : static const MCOperandInfo OperandInfo146[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8781             : static const MCOperandInfo OperandInfo147[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8782             : static const MCOperandInfo OperandInfo148[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8783             : static const MCOperandInfo OperandInfo149[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8784             : static const MCOperandInfo OperandInfo150[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8785             : static const MCOperandInfo OperandInfo151[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8786             : static const MCOperandInfo OperandInfo152[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8787             : static const MCOperandInfo OperandInfo153[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8788             : static const MCOperandInfo OperandInfo154[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8789             : static const MCOperandInfo OperandInfo155[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8790             : static const MCOperandInfo OperandInfo156[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8791             : static const MCOperandInfo OperandInfo157[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8792             : static const MCOperandInfo OperandInfo158[] = { { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8793             : static const MCOperandInfo OperandInfo159[] = { { AMDGPU::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8794             : static const MCOperandInfo OperandInfo160[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8795             : static const MCOperandInfo OperandInfo161[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8796             : static const MCOperandInfo OperandInfo162[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8797             : static const MCOperandInfo OperandInfo163[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8798             : static const MCOperandInfo OperandInfo164[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8799             : static const MCOperandInfo OperandInfo165[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8800             : static const MCOperandInfo OperandInfo166[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AMDGPU::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8801             : static const MCOperandInfo OperandInfo167[] = { { AMDGPU::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8802             : static const MCOperandInfo OperandInfo168[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8803             : static const MCOperandInfo OperandInfo169[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8804             : static const MCOperandInfo OperandInfo170[] = { { AMDGPU::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8805             : static const MCOperandInfo OperandInfo171[] = { { AMDGPU::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8806             : static const MCOperandInfo OperandInfo172[] = { { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8807             : static const MCOperandInfo OperandInfo173[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8808             : static const MCOperandInfo OperandInfo174[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8809             : static const MCOperandInfo OperandInfo175[] = { { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8810             : static const MCOperandInfo OperandInfo176[] = { { AMDGPU::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8811             : static const MCOperandInfo OperandInfo177[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8812             : static const MCOperandInfo OperandInfo178[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8813             : static const MCOperandInfo OperandInfo179[] = { { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8814             : static const MCOperandInfo OperandInfo180[] = { { AMDGPU::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8815             : static const MCOperandInfo OperandInfo181[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8816             : static const MCOperandInfo OperandInfo182[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XEXEC_HIRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8817             : static const MCOperandInfo OperandInfo183[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8818             : static const MCOperandInfo OperandInfo184[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XEXEC_HIRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8819             : static const MCOperandInfo OperandInfo185[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XEXEC_HIRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8820             : static const MCOperandInfo OperandInfo186[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XEXEC_HIRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8821             : static const MCOperandInfo OperandInfo187[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    8822             : static const MCOperandInfo OperandInfo188[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8823             : static const MCOperandInfo OperandInfo189[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
    8824             : static const MCOperandInfo OperandInfo190[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8825             : static const MCOperandInfo OperandInfo191[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8826             : static const MCOperandInfo OperandInfo192[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8827             : static const MCOperandInfo OperandInfo193[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8828             : static const MCOperandInfo OperandInfo194[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8829             : static const MCOperandInfo OperandInfo195[] = { { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8830             : static const MCOperandInfo OperandInfo196[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8831             : static const MCOperandInfo OperandInfo197[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8832             : static const MCOperandInfo OperandInfo198[] = { { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8833             : static const MCOperandInfo OperandInfo199[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8834             : static const MCOperandInfo OperandInfo200[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8835             : static const MCOperandInfo OperandInfo201[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8836             : static const MCOperandInfo OperandInfo202[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8837             : static const MCOperandInfo OperandInfo203[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8838             : static const MCOperandInfo OperandInfo204[] = { { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8839             : static const MCOperandInfo OperandInfo205[] = { { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8840             : static const MCOperandInfo OperandInfo206[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8841             : static const MCOperandInfo OperandInfo207[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8842             : static const MCOperandInfo OperandInfo208[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8843             : static const MCOperandInfo OperandInfo209[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8844             : static const MCOperandInfo OperandInfo210[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8845             : static const MCOperandInfo OperandInfo211[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8846             : static const MCOperandInfo OperandInfo212[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8847             : static const MCOperandInfo OperandInfo213[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8848             : static const MCOperandInfo OperandInfo214[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8849             : static const MCOperandInfo OperandInfo215[] = { { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8850             : static const MCOperandInfo OperandInfo216[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8851             : static const MCOperandInfo OperandInfo217[] = { { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8852             : static const MCOperandInfo OperandInfo218[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8853             : static const MCOperandInfo OperandInfo219[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8854             : static const MCOperandInfo OperandInfo220[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8855             : static const MCOperandInfo OperandInfo221[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8856             : static const MCOperandInfo OperandInfo222[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8857             : static const MCOperandInfo OperandInfo223[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8858             : static const MCOperandInfo OperandInfo224[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8859             : static const MCOperandInfo OperandInfo225[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
    8860             : static const MCOperandInfo OperandInfo226[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
    8861             : static const MCOperandInfo OperandInfo227[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8862             : static const MCOperandInfo OperandInfo228[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
    8863             : static const MCOperandInfo OperandInfo229[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8864             : static const MCOperandInfo OperandInfo230[] = { { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8865             : static const MCOperandInfo OperandInfo231[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8866             : static const MCOperandInfo OperandInfo232[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8867             : static const MCOperandInfo OperandInfo233[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8868             : static const MCOperandInfo OperandInfo234[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8869             : static const MCOperandInfo OperandInfo235[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8870             : static const MCOperandInfo OperandInfo236[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8871             : static const MCOperandInfo OperandInfo237[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8872             : static const MCOperandInfo OperandInfo238[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8873             : static const MCOperandInfo OperandInfo239[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8874             : static const MCOperandInfo OperandInfo240[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8875             : static const MCOperandInfo OperandInfo241[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8876             : static const MCOperandInfo OperandInfo242[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8877             : static const MCOperandInfo OperandInfo243[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, };
    8878             : static const MCOperandInfo OperandInfo244[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
    8879             : static const MCOperandInfo OperandInfo245[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8880             : static const MCOperandInfo OperandInfo246[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8881             : static const MCOperandInfo OperandInfo247[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8882             : static const MCOperandInfo OperandInfo248[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8883             : static const MCOperandInfo OperandInfo249[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8884             : static const MCOperandInfo OperandInfo250[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8885             : static const MCOperandInfo OperandInfo251[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8886             : static const MCOperandInfo OperandInfo252[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8887             : static const MCOperandInfo OperandInfo253[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8888             : static const MCOperandInfo OperandInfo254[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8889             : static const MCOperandInfo OperandInfo255[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8890             : static const MCOperandInfo OperandInfo256[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8891             : static const MCOperandInfo OperandInfo257[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8892             : static const MCOperandInfo OperandInfo258[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8893             : static const MCOperandInfo OperandInfo259[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8894             : static const MCOperandInfo OperandInfo260[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8895             : static const MCOperandInfo OperandInfo261[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8896             : static const MCOperandInfo OperandInfo262[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8897             : static const MCOperandInfo OperandInfo263[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8898             : static const MCOperandInfo OperandInfo264[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8899             : static const MCOperandInfo OperandInfo265[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    8900             : static const MCOperandInfo OperandInfo266[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8901             : static const MCOperandInfo OperandInfo267[] = { { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8902             : static const MCOperandInfo OperandInfo268[] = { { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8903             : static const MCOperandInfo OperandInfo269[] = { { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8904             : static const MCOperandInfo OperandInfo270[] = { { AMDGPU::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8905             : static const MCOperandInfo OperandInfo271[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8906             : static const MCOperandInfo OperandInfo272[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8907             : static const MCOperandInfo OperandInfo273[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8908             : static const MCOperandInfo OperandInfo274[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, };
    8909             : static const MCOperandInfo OperandInfo275[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8910             : static const MCOperandInfo OperandInfo276[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8911             : static const MCOperandInfo OperandInfo277[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8912             : static const MCOperandInfo OperandInfo278[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8913             : static const MCOperandInfo OperandInfo279[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8914             : static const MCOperandInfo OperandInfo280[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8915             : static const MCOperandInfo OperandInfo281[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8916             : static const MCOperandInfo OperandInfo282[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8917             : static const MCOperandInfo OperandInfo283[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8918             : static const MCOperandInfo OperandInfo284[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8919             : static const MCOperandInfo OperandInfo285[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8920             : static const MCOperandInfo OperandInfo286[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8921             : static const MCOperandInfo OperandInfo287[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, };
    8922             : static const MCOperandInfo OperandInfo288[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8923             : static const MCOperandInfo OperandInfo289[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, };
    8924             : static const MCOperandInfo OperandInfo290[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8925             : static const MCOperandInfo OperandInfo291[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8926             : static const MCOperandInfo OperandInfo292[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8927             : static const MCOperandInfo OperandInfo293[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8928             : static const MCOperandInfo OperandInfo294[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8929             : static const MCOperandInfo OperandInfo295[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8930             : static const MCOperandInfo OperandInfo296[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, };
    8931             : static const MCOperandInfo OperandInfo297[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8932             : static const MCOperandInfo OperandInfo298[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8933             : static const MCOperandInfo OperandInfo299[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, };
    8934             : static const MCOperandInfo OperandInfo300[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8935             : static const MCOperandInfo OperandInfo301[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8936             : static const MCOperandInfo OperandInfo302[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
    8937             : static const MCOperandInfo OperandInfo303[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8938             : static const MCOperandInfo OperandInfo304[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8939             : static const MCOperandInfo OperandInfo305[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8940             : static const MCOperandInfo OperandInfo306[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8941             : static const MCOperandInfo OperandInfo307[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8942             : static const MCOperandInfo OperandInfo308[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8943             : static const MCOperandInfo OperandInfo309[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8944             : static const MCOperandInfo OperandInfo310[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8945             : static const MCOperandInfo OperandInfo311[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8946             : static const MCOperandInfo OperandInfo312[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8947             : static const MCOperandInfo OperandInfo313[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8948             : static const MCOperandInfo OperandInfo314[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8949             : static const MCOperandInfo OperandInfo315[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8950             : static const MCOperandInfo OperandInfo316[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8951             : static const MCOperandInfo OperandInfo317[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, };
    8952             : static const MCOperandInfo OperandInfo318[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8953             : static const MCOperandInfo OperandInfo319[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    8954             : static const MCOperandInfo OperandInfo320[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8955             : static const MCOperandInfo OperandInfo321[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, };
    8956             : static const MCOperandInfo OperandInfo322[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, };
    8957             : static const MCOperandInfo OperandInfo323[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
    8958             : static const MCOperandInfo OperandInfo324[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8959             : static const MCOperandInfo OperandInfo325[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT16, 0 }, };
    8960             : static const MCOperandInfo OperandInfo326[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8961             : static const MCOperandInfo OperandInfo327[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8962             : static const MCOperandInfo OperandInfo328[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
    8963             : static const MCOperandInfo OperandInfo329[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8964             : static const MCOperandInfo OperandInfo330[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8965             : static const MCOperandInfo OperandInfo331[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8966             : static const MCOperandInfo OperandInfo332[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, };
    8967             : static const MCOperandInfo OperandInfo333[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8968             : static const MCOperandInfo OperandInfo334[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8969             : static const MCOperandInfo OperandInfo335[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    8970             : static const MCOperandInfo OperandInfo336[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8971             : static const MCOperandInfo OperandInfo337[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8972             : static const MCOperandInfo OperandInfo338[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8973             : static const MCOperandInfo OperandInfo339[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8974             : static const MCOperandInfo OperandInfo340[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8975             : static const MCOperandInfo OperandInfo341[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8976             : static const MCOperandInfo OperandInfo342[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, };
    8977             : static const MCOperandInfo OperandInfo343[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, };
    8978             : static const MCOperandInfo OperandInfo344[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8979             : static const MCOperandInfo OperandInfo345[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8980             : static const MCOperandInfo OperandInfo346[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8981             : static const MCOperandInfo OperandInfo347[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8982             : static const MCOperandInfo OperandInfo348[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8983             : static const MCOperandInfo OperandInfo349[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8984             : static const MCOperandInfo OperandInfo350[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8985             : static const MCOperandInfo OperandInfo351[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8986             : static const MCOperandInfo OperandInfo352[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8987             : static const MCOperandInfo OperandInfo353[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8988             : static const MCOperandInfo OperandInfo354[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8989             : static const MCOperandInfo OperandInfo355[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    8990             : static const MCOperandInfo OperandInfo356[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8991             : static const MCOperandInfo OperandInfo357[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_SDWA_SRC, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8992             : static const MCOperandInfo OperandInfo358[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    8993             : static const MCOperandInfo OperandInfo359[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8994             : static const MCOperandInfo OperandInfo360[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_KIMM16, 0 }, };
    8995             : static const MCOperandInfo OperandInfo361[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_KIMM32, 0 }, };
    8996             : static const MCOperandInfo OperandInfo362[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_KIMM16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8997             : static const MCOperandInfo OperandInfo363[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_KIMM32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    8998             : static const MCOperandInfo OperandInfo364[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    8999             : static const MCOperandInfo OperandInfo365[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9000             : static const MCOperandInfo OperandInfo366[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9001             : static const MCOperandInfo OperandInfo367[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9002             : static const MCOperandInfo OperandInfo368[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9003             : static const MCOperandInfo OperandInfo369[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9004             : static const MCOperandInfo OperandInfo370[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9005             : static const MCOperandInfo OperandInfo371[] = { { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9006             : static const MCOperandInfo OperandInfo372[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9007             : static const MCOperandInfo OperandInfo373[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9008             : static const MCOperandInfo OperandInfo374[] = { { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9009             : static const MCOperandInfo OperandInfo375[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9010             : static const MCOperandInfo OperandInfo376[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    9011             : static const MCOperandInfo OperandInfo377[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
    9012             : static const MCOperandInfo OperandInfo378[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9013             : static const MCOperandInfo OperandInfo379[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9014             : static const MCOperandInfo OperandInfo380[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9015             : static const MCOperandInfo OperandInfo381[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9016             : static const MCOperandInfo OperandInfo382[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9017             : static const MCOperandInfo OperandInfo383[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    9018             : static const MCOperandInfo OperandInfo384[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    9019             : static const MCOperandInfo OperandInfo385[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    9020             : static const MCOperandInfo OperandInfo386[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
    9021             : static const MCOperandInfo OperandInfo387[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
    9022             : static const MCOperandInfo OperandInfo388[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    9023             : static const MCOperandInfo OperandInfo389[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    9024             : static const MCOperandInfo OperandInfo390[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
    9025             : static const MCOperandInfo OperandInfo391[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, (1 << MCOI::EARLY_CLOBBER) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    9026             : 
    9027             : extern const MCInstrDesc AMDGPUInsts[] = {
    9028             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
    9029             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
    9030             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
    9031             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
    9032             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
    9033             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
    9034             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
    9035             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
    9036             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
    9037             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
    9038             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
    9039             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
    9040             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
    9041             :   { 13, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #13 = REG_SEQUENCE
    9042             :   { 14, 2,      1,      0,      23,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = COPY
    9043             :   { 15, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #15 = BUNDLE
    9044             :   { 16, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #16 = LIFETIME_START
    9045             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_END
    9046             :   { 18, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #18 = STACKMAP
    9047             :   { 19, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #19 = FENTRY_CALL
    9048             :   { 20, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #20 = PATCHPOINT
    9049             :   { 21, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #21 = LOAD_STACK_GUARD
    9050             :   { 22, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #22 = STATEPOINT
    9051             :   { 23, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #23 = LOCAL_ESCAPE
    9052             :   { 24, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #24 = FAULTING_OP
    9053             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = PATCHABLE_OP
    9054             :   { 26, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_FUNCTION_ENTER
    9055             :   { 27, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #27 = PATCHABLE_RET
    9056             :   { 28, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_EXIT
    9057             :   { 29, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #29 = PATCHABLE_TAIL_CALL
    9058             :   { 30, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #30 = PATCHABLE_EVENT_CALL
    9059             :   { 31, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #31 = G_ADD
    9060             :   { 32, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = G_SUB
    9061             :   { 33, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = G_MUL
    9062             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #34 = G_SDIV
    9063             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #35 = G_UDIV
    9064             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #36 = G_SREM
    9065             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #37 = G_UREM
    9066             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #38 = G_AND
    9067             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #39 = G_OR
    9068             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #40 = G_XOR
    9069             :   { 41, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_IMPLICIT_DEF
    9070             :   { 42, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_PHI
    9071             :   { 43, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #43 = G_FRAME_INDEX
    9072             :   { 44, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_GLOBAL_VALUE
    9073             :   { 45, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #45 = G_EXTRACT
    9074             :   { 46, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #46 = G_UNMERGE_VALUES
    9075             :   { 47, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #47 = G_INSERT
    9076             :   { 48, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #48 = G_MERGE_VALUES
    9077             :   { 49, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_PTRTOINT
    9078             :   { 50, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_INTTOPTR
    9079             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_BITCAST
    9080             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_LOAD
    9081             :   { 53, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_STORE
    9082             :   { 54, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #54 = G_BRCOND
    9083             :   { 55, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #55 = G_BRINDIRECT
    9084             :   { 56, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #56 = G_INTRINSIC
    9085             :   { 57, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #57 = G_INTRINSIC_W_SIDE_EFFECTS
    9086             :   { 58, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_ANYEXT
    9087             :   { 59, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_TRUNC
    9088             :   { 60, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #60 = G_CONSTANT
    9089             :   { 61, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #61 = G_FCONSTANT
    9090             :   { 62, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #62 = G_VASTART
    9091             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #63 = G_VAARG
    9092             :   { 64, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_SEXT
    9093             :   { 65, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #65 = G_ZEXT
    9094             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #66 = G_SHL
    9095             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #67 = G_LSHR
    9096             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #68 = G_ASHR
    9097             :   { 69, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #69 = G_ICMP
    9098             :   { 70, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #70 = G_FCMP
    9099             :   { 71, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #71 = G_SELECT
    9100             :   { 72, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #72 = G_UADDE
    9101             :   { 73, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #73 = G_USUBE
    9102             :   { 74, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #74 = G_SADDO
    9103             :   { 75, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #75 = G_SSUBO
    9104             :   { 76, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #76 = G_UMULO
    9105             :   { 77, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #77 = G_SMULO
    9106             :   { 78, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #78 = G_UMULH
    9107             :   { 79, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #79 = G_SMULH
    9108             :   { 80, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #80 = G_FADD
    9109             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #81 = G_FSUB
    9110             :   { 82, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #82 = G_FMUL
    9111             :   { 83, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #83 = G_FMA
    9112             :   { 84, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #84 = G_FDIV
    9113             :   { 85, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #85 = G_FREM
    9114             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #86 = G_FPOW
    9115             :   { 87, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_FEXP
    9116             :   { 88, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FEXP2
    9117             :   { 89, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #89 = G_FLOG
    9118             :   { 90, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #90 = G_FLOG2
    9119             :   { 91, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #91 = G_FNEG
    9120             :   { 92, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #92 = G_FPEXT
    9121             :   { 93, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #93 = G_FPTRUNC
    9122             :   { 94, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #94 = G_FPTOSI
    9123             :   { 95, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #95 = G_FPTOUI
    9124             :   { 96, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #96 = G_SITOFP
    9125             :   { 97, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #97 = G_UITOFP
    9126             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #98 = G_GEP
    9127             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_PTR_MASK
    9128             :   { 100,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #100 = G_BR
    9129             :   { 101,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #101 = G_INSERT_VECTOR_ELT
    9130             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #102 = G_EXTRACT_VECTOR_ELT
    9131             :   { 103,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #103 = G_SHUFFLE_VECTOR
    9132             :   { 104,        21,     1,      0,      1,      0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #104 = ADD
    9133             :   { 105,        21,     1,      0,      1,      0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #105 = ADDC_UINT
    9134             :   { 106,        21,     1,      0,      1,      0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #106 = ADD_INT
    9135             :   { 107,        2,      0,      8,      2,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #107 = ADJCALLSTACKDOWN
    9136             :   { 108,        2,      0,      8,      2,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000001ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #108 = ADJCALLSTACKUP
    9137             :   { 109,        1,      0,      0,      3,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #109 = ALU_CLAUSE
    9138             :   { 110,        21,     1,      0,      1,      0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #110 = AND_INT
    9139             :   { 111,        21,     1,      0,      1,      0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #111 = ASHR_eg
    9140             :   { 112,        21,     1,      0,      1,      0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #112 = ASHR_r600
    9141             :   { 113,        2,      0,      0,      2,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x80000000001ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #113 = ATOMIC_FENCE
    9142             :   { 114,        14,     1,      0,      4,      0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #114 = BCNT_INT
    9143             :   { 115,        19,     1,      0,      4,      0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #115 = BFE_INT_eg
    9144             :   { 116,        19,     1,      0,      4,      0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #116 = BFE_UINT_eg
    9145             :   { 117,        19,     1,      0,      4,      0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #117 = BFI_INT_eg
    9146             :   { 118,        21,     1,      0,      4,      0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #118 = BFM_INT_eg
    9147             :   { 119,        19,     1,      0,      4,      0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #119 = BIT_ALIGN_INT_eg
    9148             :   { 120,        1,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #120 = BRANCH
    9149             :   { 121,        2,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #121 = BRANCH_COND_f32
    9150             :   { 122,        2,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #122 = BRANCH_COND_i32
    9151             :   { 123,        0,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #123 = BREAK
    9152             :   { 124,        2,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #124 = BREAKC_f32
    9153             :   { 125,        2,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #125 = BREAKC_i32
    9154             :   { 126,        1,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #126 = BREAK_LOGICALNZ_f32
    9155             :   { 127,        1,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #127 = BREAK_LOGICALNZ_i32
    9156             :   { 128,        1,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #128 = BREAK_LOGICALZ_f32
    9157             :   { 129,        1,      0,      0,      3,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #129 = BREAK_LOGICALZ_i32
    9158             :   { 130,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #130 = BUFFER_ATOMIC_ADD_ADDR64
    9159             :   { 131,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #131 = BUFFER_ATOMIC_ADD_ADDR64_RTN
    9160             :   { 132,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #132 = BUFFER_ATOMIC_ADD_ADDR64_RTN_si
    9161             :   { 133,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #133 = BUFFER_ATOMIC_ADD_ADDR64_si
    9162             :   { 134,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #134 = BUFFER_ATOMIC_ADD_BOTHEN
    9163             :   { 135,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #135 = BUFFER_ATOMIC_ADD_BOTHEN_RTN
    9164             :   { 136,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #136 = BUFFER_ATOMIC_ADD_BOTHEN_RTN_si
    9165             :   { 137,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #137 = BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi
    9166             :   { 138,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #138 = BUFFER_ATOMIC_ADD_BOTHEN_si
    9167             :   { 139,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #139 = BUFFER_ATOMIC_ADD_BOTHEN_vi
    9168             :   { 140,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #140 = BUFFER_ATOMIC_ADD_IDXEN
    9169             :   { 141,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #141 = BUFFER_ATOMIC_ADD_IDXEN_RTN
    9170             :   { 142,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #142 = BUFFER_ATOMIC_ADD_IDXEN_RTN_si
    9171             :   { 143,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #143 = BUFFER_ATOMIC_ADD_IDXEN_RTN_vi
    9172             :   { 144,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #144 = BUFFER_ATOMIC_ADD_IDXEN_si
    9173             :   { 145,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #145 = BUFFER_ATOMIC_ADD_IDXEN_vi
    9174             :   { 146,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #146 = BUFFER_ATOMIC_ADD_OFFEN
    9175             :   { 147,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #147 = BUFFER_ATOMIC_ADD_OFFEN_RTN
    9176             :   { 148,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #148 = BUFFER_ATOMIC_ADD_OFFEN_RTN_si
    9177             :   { 149,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #149 = BUFFER_ATOMIC_ADD_OFFEN_RTN_vi
    9178             :   { 150,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #150 = BUFFER_ATOMIC_ADD_OFFEN_si
    9179             :   { 151,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #151 = BUFFER_ATOMIC_ADD_OFFEN_vi
    9180             :   { 152,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #152 = BUFFER_ATOMIC_ADD_OFFSET
    9181             :   { 153,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #153 = BUFFER_ATOMIC_ADD_OFFSET_RTN
    9182             :   { 154,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #154 = BUFFER_ATOMIC_ADD_OFFSET_RTN_si
    9183             :   { 155,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #155 = BUFFER_ATOMIC_ADD_OFFSET_RTN_vi
    9184             :   { 156,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #156 = BUFFER_ATOMIC_ADD_OFFSET_si
    9185             :   { 157,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #157 = BUFFER_ATOMIC_ADD_OFFSET_vi
    9186             :   { 158,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #158 = BUFFER_ATOMIC_ADD_X2_ADDR64
    9187             :   { 159,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #159 = BUFFER_ATOMIC_ADD_X2_ADDR64_RTN
    9188             :   { 160,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #160 = BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_si
    9189             :   { 161,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #161 = BUFFER_ATOMIC_ADD_X2_ADDR64_si
    9190             :   { 162,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #162 = BUFFER_ATOMIC_ADD_X2_BOTHEN
    9191             :   { 163,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #163 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN
    9192             :   { 164,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #164 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_si
    9193             :   { 165,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #165 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi
    9194             :   { 166,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #166 = BUFFER_ATOMIC_ADD_X2_BOTHEN_si
    9195             :   { 167,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #167 = BUFFER_ATOMIC_ADD_X2_BOTHEN_vi
    9196             :   { 168,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #168 = BUFFER_ATOMIC_ADD_X2_IDXEN
    9197             :   { 169,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #169 = BUFFER_ATOMIC_ADD_X2_IDXEN_RTN
    9198             :   { 170,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #170 = BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_si
    9199             :   { 171,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #171 = BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi
    9200             :   { 172,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #172 = BUFFER_ATOMIC_ADD_X2_IDXEN_si
    9201             :   { 173,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #173 = BUFFER_ATOMIC_ADD_X2_IDXEN_vi
    9202             :   { 174,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #174 = BUFFER_ATOMIC_ADD_X2_OFFEN
    9203             :   { 175,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #175 = BUFFER_ATOMIC_ADD_X2_OFFEN_RTN
    9204             :   { 176,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #176 = BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_si
    9205             :   { 177,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #177 = BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi
    9206             :   { 178,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #178 = BUFFER_ATOMIC_ADD_X2_OFFEN_si
    9207             :   { 179,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #179 = BUFFER_ATOMIC_ADD_X2_OFFEN_vi
    9208             :   { 180,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #180 = BUFFER_ATOMIC_ADD_X2_OFFSET
    9209             :   { 181,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #181 = BUFFER_ATOMIC_ADD_X2_OFFSET_RTN
    9210             :   { 182,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #182 = BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_si
    9211             :   { 183,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #183 = BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi
    9212             :   { 184,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #184 = BUFFER_ATOMIC_ADD_X2_OFFSET_si
    9213             :   { 185,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #185 = BUFFER_ATOMIC_ADD_X2_OFFSET_vi
    9214             :   { 186,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #186 = BUFFER_ATOMIC_AND_ADDR64
    9215             :   { 187,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #187 = BUFFER_ATOMIC_AND_ADDR64_RTN
    9216             :   { 188,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #188 = BUFFER_ATOMIC_AND_ADDR64_RTN_si
    9217             :   { 189,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #189 = BUFFER_ATOMIC_AND_ADDR64_si
    9218             :   { 190,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #190 = BUFFER_ATOMIC_AND_BOTHEN
    9219             :   { 191,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #191 = BUFFER_ATOMIC_AND_BOTHEN_RTN
    9220             :   { 192,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #192 = BUFFER_ATOMIC_AND_BOTHEN_RTN_si
    9221             :   { 193,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #193 = BUFFER_ATOMIC_AND_BOTHEN_RTN_vi
    9222             :   { 194,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #194 = BUFFER_ATOMIC_AND_BOTHEN_si
    9223             :   { 195,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #195 = BUFFER_ATOMIC_AND_BOTHEN_vi
    9224             :   { 196,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #196 = BUFFER_ATOMIC_AND_IDXEN
    9225             :   { 197,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #197 = BUFFER_ATOMIC_AND_IDXEN_RTN
    9226             :   { 198,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #198 = BUFFER_ATOMIC_AND_IDXEN_RTN_si
    9227             :   { 199,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #199 = BUFFER_ATOMIC_AND_IDXEN_RTN_vi
    9228             :   { 200,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #200 = BUFFER_ATOMIC_AND_IDXEN_si
    9229             :   { 201,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #201 = BUFFER_ATOMIC_AND_IDXEN_vi
    9230             :   { 202,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #202 = BUFFER_ATOMIC_AND_OFFEN
    9231             :   { 203,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #203 = BUFFER_ATOMIC_AND_OFFEN_RTN
    9232             :   { 204,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #204 = BUFFER_ATOMIC_AND_OFFEN_RTN_si
    9233             :   { 205,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #205 = BUFFER_ATOMIC_AND_OFFEN_RTN_vi
    9234             :   { 206,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #206 = BUFFER_ATOMIC_AND_OFFEN_si
    9235             :   { 207,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #207 = BUFFER_ATOMIC_AND_OFFEN_vi
    9236             :   { 208,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #208 = BUFFER_ATOMIC_AND_OFFSET
    9237             :   { 209,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #209 = BUFFER_ATOMIC_AND_OFFSET_RTN
    9238             :   { 210,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #210 = BUFFER_ATOMIC_AND_OFFSET_RTN_si
    9239             :   { 211,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #211 = BUFFER_ATOMIC_AND_OFFSET_RTN_vi
    9240             :   { 212,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #212 = BUFFER_ATOMIC_AND_OFFSET_si
    9241             :   { 213,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #213 = BUFFER_ATOMIC_AND_OFFSET_vi
    9242             :   { 214,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #214 = BUFFER_ATOMIC_AND_X2_ADDR64
    9243             :   { 215,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #215 = BUFFER_ATOMIC_AND_X2_ADDR64_RTN
    9244             :   { 216,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #216 = BUFFER_ATOMIC_AND_X2_ADDR64_RTN_si
    9245             :   { 217,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #217 = BUFFER_ATOMIC_AND_X2_ADDR64_si
    9246             :   { 218,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #218 = BUFFER_ATOMIC_AND_X2_BOTHEN
    9247             :   { 219,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #219 = BUFFER_ATOMIC_AND_X2_BOTHEN_RTN
    9248             :   { 220,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #220 = BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_si
    9249             :   { 221,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #221 = BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi
    9250             :   { 222,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #222 = BUFFER_ATOMIC_AND_X2_BOTHEN_si
    9251             :   { 223,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #223 = BUFFER_ATOMIC_AND_X2_BOTHEN_vi
    9252             :   { 224,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #224 = BUFFER_ATOMIC_AND_X2_IDXEN
    9253             :   { 225,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #225 = BUFFER_ATOMIC_AND_X2_IDXEN_RTN
    9254             :   { 226,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #226 = BUFFER_ATOMIC_AND_X2_IDXEN_RTN_si
    9255             :   { 227,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #227 = BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi
    9256             :   { 228,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #228 = BUFFER_ATOMIC_AND_X2_IDXEN_si
    9257             :   { 229,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #229 = BUFFER_ATOMIC_AND_X2_IDXEN_vi
    9258             :   { 230,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #230 = BUFFER_ATOMIC_AND_X2_OFFEN
    9259             :   { 231,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #231 = BUFFER_ATOMIC_AND_X2_OFFEN_RTN
    9260             :   { 232,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #232 = BUFFER_ATOMIC_AND_X2_OFFEN_RTN_si
    9261             :   { 233,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #233 = BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi
    9262             :   { 234,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #234 = BUFFER_ATOMIC_AND_X2_OFFEN_si
    9263             :   { 235,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #235 = BUFFER_ATOMIC_AND_X2_OFFEN_vi
    9264             :   { 236,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #236 = BUFFER_ATOMIC_AND_X2_OFFSET
    9265             :   { 237,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #237 = BUFFER_ATOMIC_AND_X2_OFFSET_RTN
    9266             :   { 238,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #238 = BUFFER_ATOMIC_AND_X2_OFFSET_RTN_si
    9267             :   { 239,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #239 = BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi
    9268             :   { 240,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #240 = BUFFER_ATOMIC_AND_X2_OFFSET_si
    9269             :   { 241,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #241 = BUFFER_ATOMIC_AND_X2_OFFSET_vi
    9270             :   { 242,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #242 = BUFFER_ATOMIC_CMPSWAP_ADDR64
    9271             :   { 243,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #243 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN
    9272             :   { 244,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #244 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_si
    9273             :   { 245,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #245 = BUFFER_ATOMIC_CMPSWAP_ADDR64_si
    9274             :   { 246,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #246 = BUFFER_ATOMIC_CMPSWAP_BOTHEN
    9275             :   { 247,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #247 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN
    9276             :   { 248,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #248 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_si
    9277             :   { 249,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #249 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi
    9278             :   { 250,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #250 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_si
    9279             :   { 251,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #251 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi
    9280             :   { 252,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #252 = BUFFER_ATOMIC_CMPSWAP_IDXEN
    9281             :   { 253,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #253 = BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN
    9282             :   { 254,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #254 = BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_si
    9283             :   { 255,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #255 = BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi
    9284             :   { 256,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #256 = BUFFER_ATOMIC_CMPSWAP_IDXEN_si
    9285             :   { 257,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #257 = BUFFER_ATOMIC_CMPSWAP_IDXEN_vi
    9286             :   { 258,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #258 = BUFFER_ATOMIC_CMPSWAP_OFFEN
    9287             :   { 259,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #259 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN
    9288             :   { 260,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #260 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_si
    9289             :   { 261,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #261 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi
    9290             :   { 262,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #262 = BUFFER_ATOMIC_CMPSWAP_OFFEN_si
    9291             :   { 263,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #263 = BUFFER_ATOMIC_CMPSWAP_OFFEN_vi
    9292             :   { 264,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #264 = BUFFER_ATOMIC_CMPSWAP_OFFSET
    9293             :   { 265,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #265 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN
    9294             :   { 266,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #266 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_si
    9295             :   { 267,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #267 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi
    9296             :   { 268,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #268 = BUFFER_ATOMIC_CMPSWAP_OFFSET_si
    9297             :   { 269,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #269 = BUFFER_ATOMIC_CMPSWAP_OFFSET_vi
    9298             :   { 270,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #270 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64
    9299             :   { 271,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #271 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN
    9300             :   { 272,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #272 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_si
    9301             :   { 273,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #273 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_si
    9302             :   { 274,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #274 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN
    9303             :   { 275,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #275 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN
    9304             :   { 276,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #276 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_si
    9305             :   { 277,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #277 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi
    9306             :   { 278,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #278 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_si
    9307             :   { 279,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #279 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi
    9308             :   { 280,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #280 = BUFFER_ATOMIC_CMPSWAP_X2_IDXEN
    9309             :   { 281,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #281 = BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN
    9310             :   { 282,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #282 = BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_si
    9311             :   { 283,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #283 = BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi
    9312             :   { 284,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #284 = BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_si
    9313             :   { 285,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #285 = BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi
    9314             :   { 286,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #286 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN
    9315             :   { 287,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #287 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN
    9316             :   { 288,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #288 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_si
    9317             :   { 289,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #289 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi
    9318             :   { 290,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #290 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_si
    9319             :   { 291,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #291 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi
    9320             :   { 292,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #292 = BUFFER_ATOMIC_CMPSWAP_X2_OFFSET
    9321             :   { 293,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #293 = BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN
    9322             :   { 294,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #294 = BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_si
    9323             :   { 295,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #295 = BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi
    9324             :   { 296,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #296 = BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_si
    9325             :   { 297,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #297 = BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi
    9326             :   { 298,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #298 = BUFFER_ATOMIC_DEC_ADDR64
    9327             :   { 299,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #299 = BUFFER_ATOMIC_DEC_ADDR64_RTN
    9328             :   { 300,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #300 = BUFFER_ATOMIC_DEC_ADDR64_RTN_si
    9329             :   { 301,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #301 = BUFFER_ATOMIC_DEC_ADDR64_si
    9330             :   { 302,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #302 = BUFFER_ATOMIC_DEC_BOTHEN
    9331             :   { 303,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #303 = BUFFER_ATOMIC_DEC_BOTHEN_RTN
    9332             :   { 304,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #304 = BUFFER_ATOMIC_DEC_BOTHEN_RTN_si
    9333             :   { 305,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #305 = BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi
    9334             :   { 306,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #306 = BUFFER_ATOMIC_DEC_BOTHEN_si
    9335             :   { 307,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #307 = BUFFER_ATOMIC_DEC_BOTHEN_vi
    9336             :   { 308,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #308 = BUFFER_ATOMIC_DEC_IDXEN
    9337             :   { 309,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #309 = BUFFER_ATOMIC_DEC_IDXEN_RTN
    9338             :   { 310,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #310 = BUFFER_ATOMIC_DEC_IDXEN_RTN_si
    9339             :   { 311,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #311 = BUFFER_ATOMIC_DEC_IDXEN_RTN_vi
    9340             :   { 312,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #312 = BUFFER_ATOMIC_DEC_IDXEN_si
    9341             :   { 313,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #313 = BUFFER_ATOMIC_DEC_IDXEN_vi
    9342             :   { 314,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #314 = BUFFER_ATOMIC_DEC_OFFEN
    9343             :   { 315,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #315 = BUFFER_ATOMIC_DEC_OFFEN_RTN
    9344             :   { 316,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #316 = BUFFER_ATOMIC_DEC_OFFEN_RTN_si
    9345             :   { 317,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #317 = BUFFER_ATOMIC_DEC_OFFEN_RTN_vi
    9346             :   { 318,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #318 = BUFFER_ATOMIC_DEC_OFFEN_si
    9347             :   { 319,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #319 = BUFFER_ATOMIC_DEC_OFFEN_vi
    9348             :   { 320,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #320 = BUFFER_ATOMIC_DEC_OFFSET
    9349             :   { 321,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #321 = BUFFER_ATOMIC_DEC_OFFSET_RTN
    9350             :   { 322,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #322 = BUFFER_ATOMIC_DEC_OFFSET_RTN_si
    9351             :   { 323,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #323 = BUFFER_ATOMIC_DEC_OFFSET_RTN_vi
    9352             :   { 324,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #324 = BUFFER_ATOMIC_DEC_OFFSET_si
    9353             :   { 325,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #325 = BUFFER_ATOMIC_DEC_OFFSET_vi
    9354             :   { 326,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #326 = BUFFER_ATOMIC_DEC_X2_ADDR64
    9355             :   { 327,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #327 = BUFFER_ATOMIC_DEC_X2_ADDR64_RTN
    9356             :   { 328,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #328 = BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_si
    9357             :   { 329,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #329 = BUFFER_ATOMIC_DEC_X2_ADDR64_si
    9358             :   { 330,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #330 = BUFFER_ATOMIC_DEC_X2_BOTHEN
    9359             :   { 331,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #331 = BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN
    9360             :   { 332,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #332 = BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_si
    9361             :   { 333,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #333 = BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi
    9362             :   { 334,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #334 = BUFFER_ATOMIC_DEC_X2_BOTHEN_si
    9363             :   { 335,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #335 = BUFFER_ATOMIC_DEC_X2_BOTHEN_vi
    9364             :   { 336,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #336 = BUFFER_ATOMIC_DEC_X2_IDXEN
    9365             :   { 337,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #337 = BUFFER_ATOMIC_DEC_X2_IDXEN_RTN
    9366             :   { 338,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #338 = BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_si
    9367             :   { 339,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #339 = BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi
    9368             :   { 340,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #340 = BUFFER_ATOMIC_DEC_X2_IDXEN_si
    9369             :   { 341,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #341 = BUFFER_ATOMIC_DEC_X2_IDXEN_vi
    9370             :   { 342,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #342 = BUFFER_ATOMIC_DEC_X2_OFFEN
    9371             :   { 343,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #343 = BUFFER_ATOMIC_DEC_X2_OFFEN_RTN
    9372             :   { 344,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #344 = BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_si
    9373             :   { 345,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #345 = BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi
    9374             :   { 346,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #346 = BUFFER_ATOMIC_DEC_X2_OFFEN_si
    9375             :   { 347,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #347 = BUFFER_ATOMIC_DEC_X2_OFFEN_vi
    9376             :   { 348,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #348 = BUFFER_ATOMIC_DEC_X2_OFFSET
    9377             :   { 349,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #349 = BUFFER_ATOMIC_DEC_X2_OFFSET_RTN
    9378             :   { 350,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #350 = BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_si
    9379             :   { 351,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #351 = BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi
    9380             :   { 352,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #352 = BUFFER_ATOMIC_DEC_X2_OFFSET_si
    9381             :   { 353,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #353 = BUFFER_ATOMIC_DEC_X2_OFFSET_vi
    9382             :   { 354,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #354 = BUFFER_ATOMIC_INC_ADDR64
    9383             :   { 355,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #355 = BUFFER_ATOMIC_INC_ADDR64_RTN
    9384             :   { 356,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #356 = BUFFER_ATOMIC_INC_ADDR64_RTN_si
    9385             :   { 357,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #357 = BUFFER_ATOMIC_INC_ADDR64_si
    9386             :   { 358,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #358 = BUFFER_ATOMIC_INC_BOTHEN
    9387             :   { 359,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #359 = BUFFER_ATOMIC_INC_BOTHEN_RTN
    9388             :   { 360,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #360 = BUFFER_ATOMIC_INC_BOTHEN_RTN_si
    9389             :   { 361,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #361 = BUFFER_ATOMIC_INC_BOTHEN_RTN_vi
    9390             :   { 362,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #362 = BUFFER_ATOMIC_INC_BOTHEN_si
    9391             :   { 363,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #363 = BUFFER_ATOMIC_INC_BOTHEN_vi
    9392             :   { 364,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #364 = BUFFER_ATOMIC_INC_IDXEN
    9393             :   { 365,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #365 = BUFFER_ATOMIC_INC_IDXEN_RTN
    9394             :   { 366,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #366 = BUFFER_ATOMIC_INC_IDXEN_RTN_si
    9395             :   { 367,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #367 = BUFFER_ATOMIC_INC_IDXEN_RTN_vi
    9396             :   { 368,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #368 = BUFFER_ATOMIC_INC_IDXEN_si
    9397             :   { 369,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #369 = BUFFER_ATOMIC_INC_IDXEN_vi
    9398             :   { 370,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #370 = BUFFER_ATOMIC_INC_OFFEN
    9399             :   { 371,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #371 = BUFFER_ATOMIC_INC_OFFEN_RTN
    9400             :   { 372,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #372 = BUFFER_ATOMIC_INC_OFFEN_RTN_si
    9401             :   { 373,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #373 = BUFFER_ATOMIC_INC_OFFEN_RTN_vi
    9402             :   { 374,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #374 = BUFFER_ATOMIC_INC_OFFEN_si
    9403             :   { 375,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #375 = BUFFER_ATOMIC_INC_OFFEN_vi
    9404             :   { 376,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #376 = BUFFER_ATOMIC_INC_OFFSET
    9405             :   { 377,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #377 = BUFFER_ATOMIC_INC_OFFSET_RTN
    9406             :   { 378,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #378 = BUFFER_ATOMIC_INC_OFFSET_RTN_si
    9407             :   { 379,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #379 = BUFFER_ATOMIC_INC_OFFSET_RTN_vi
    9408             :   { 380,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #380 = BUFFER_ATOMIC_INC_OFFSET_si
    9409             :   { 381,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #381 = BUFFER_ATOMIC_INC_OFFSET_vi
    9410             :   { 382,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #382 = BUFFER_ATOMIC_INC_X2_ADDR64
    9411             :   { 383,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #383 = BUFFER_ATOMIC_INC_X2_ADDR64_RTN
    9412             :   { 384,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #384 = BUFFER_ATOMIC_INC_X2_ADDR64_RTN_si
    9413             :   { 385,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #385 = BUFFER_ATOMIC_INC_X2_ADDR64_si
    9414             :   { 386,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #386 = BUFFER_ATOMIC_INC_X2_BOTHEN
    9415             :   { 387,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #387 = BUFFER_ATOMIC_INC_X2_BOTHEN_RTN
    9416             :   { 388,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #388 = BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_si
    9417             :   { 389,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #389 = BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi
    9418             :   { 390,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #390 = BUFFER_ATOMIC_INC_X2_BOTHEN_si
    9419             :   { 391,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #391 = BUFFER_ATOMIC_INC_X2_BOTHEN_vi
    9420             :   { 392,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #392 = BUFFER_ATOMIC_INC_X2_IDXEN
    9421             :   { 393,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #393 = BUFFER_ATOMIC_INC_X2_IDXEN_RTN
    9422             :   { 394,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #394 = BUFFER_ATOMIC_INC_X2_IDXEN_RTN_si
    9423             :   { 395,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #395 = BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi
    9424             :   { 396,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #396 = BUFFER_ATOMIC_INC_X2_IDXEN_si
    9425             :   { 397,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #397 = BUFFER_ATOMIC_INC_X2_IDXEN_vi
    9426             :   { 398,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #398 = BUFFER_ATOMIC_INC_X2_OFFEN
    9427             :   { 399,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #399 = BUFFER_ATOMIC_INC_X2_OFFEN_RTN
    9428             :   { 400,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #400 = BUFFER_ATOMIC_INC_X2_OFFEN_RTN_si
    9429             :   { 401,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #401 = BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi
    9430             :   { 402,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #402 = BUFFER_ATOMIC_INC_X2_OFFEN_si
    9431             :   { 403,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #403 = BUFFER_ATOMIC_INC_X2_OFFEN_vi
    9432             :   { 404,        5,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #404 = BUFFER_ATOMIC_INC_X2_OFFSET
    9433             :   { 405,        6,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #405 = BUFFER_ATOMIC_INC_X2_OFFSET_RTN
    9434             :   { 406,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #406 = BUFFER_ATOMIC_INC_X2_OFFSET_RTN_si
    9435             :   { 407,        6,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #407 = BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi
    9436             :   { 408,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #408 = BUFFER_ATOMIC_INC_X2_OFFSET_si
    9437             :   { 409,        5,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #409 = BUFFER_ATOMIC_INC_X2_OFFSET_vi
    9438             :   { 410,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #410 = BUFFER_ATOMIC_OR_ADDR64
    9439             :   { 411,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #411 = BUFFER_ATOMIC_OR_ADDR64_RTN
    9440             :   { 412,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #412 = BUFFER_ATOMIC_OR_ADDR64_RTN_si
    9441             :   { 413,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #413 = BUFFER_ATOMIC_OR_ADDR64_si
    9442             :   { 414,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #414 = BUFFER_ATOMIC_OR_BOTHEN
    9443             :   { 415,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #415 = BUFFER_ATOMIC_OR_BOTHEN_RTN
    9444             :   { 416,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #416 = BUFFER_ATOMIC_OR_BOTHEN_RTN_si
    9445             :   { 417,        7,      1,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #417 = BUFFER_ATOMIC_OR_BOTHEN_RTN_vi
    9446             :   { 418,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #418 = BUFFER_ATOMIC_OR_BOTHEN_si
    9447             :   { 419,        6,      0,      8,      2,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #419 = BUFFER_ATOMIC_OR_BOTHEN_vi
    9448             :   { 420,        6,      0,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #420 = BUFFER_ATOMIC_OR_IDXEN
    9449             :   { 421,        7,      1,      8,      5,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1U