LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenSubtargetInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 122 123 99.2 %
Date: 2018-05-20 00:06:23 Functions: 4 6 66.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Subtarget Enumeration Source Fragment                                      *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_SUBTARGETINFO_ENUM
      11             : #undef GET_SUBTARGETINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : namespace AMDGPU {
      15             : enum {
      16             :   Feature16BitInsts = 0,
      17             :   FeatureAddNoCarryInsts = 1,
      18             :   FeatureApertureRegs = 2,
      19             :   FeatureAutoWaitcntBeforeBarrier = 3,
      20             :   FeatureCFALUBug = 4,
      21             :   FeatureCIInsts = 5,
      22             :   FeatureCaymanISA = 6,
      23             :   FeatureCodeObjectV3 = 7,
      24             :   FeatureD16PreservesUnusedBits = 8,
      25             :   FeatureDLInsts = 9,
      26             :   FeatureDPP = 10,
      27             :   FeatureDX10Clamp = 11,
      28             :   FeatureDebuggerEmitPrologue = 12,
      29             :   FeatureDebuggerInsertNops = 13,
      30             :   FeatureDebuggerReserveRegs = 14,
      31             :   FeatureDisable = 15,
      32             :   FeatureDumpCode = 16,
      33             :   FeatureDumpCodeLower = 17,
      34             :   FeatureEnableDS128 = 18,
      35             :   FeatureEnableHugePrivateBuffer = 19,
      36             :   FeatureEnableLoadStoreOpt = 20,
      37             :   FeatureEnableSIScheduler = 21,
      38             :   FeatureEnableUnsafeDSOffsetFolding = 22,
      39             :   FeatureEvergreen = 23,
      40             :   FeatureFMA = 24,
      41             :   FeatureFP16Denormals = 25,
      42             :   FeatureFP32Denormals = 26,
      43             :   FeatureFP64 = 27,
      44             :   FeatureFP64Denormals = 28,
      45             :   FeatureFP64FP16Denormals = 29,
      46             :   FeatureFPExceptions = 30,
      47             :   FeatureFastFMAF32 = 31,
      48             :   FeatureFetchLimit8 = 32,
      49             :   FeatureFetchLimit16 = 33,
      50             :   FeatureFlatAddressSpace = 34,
      51             :   FeatureFlatForGlobal = 35,
      52             :   FeatureFlatGlobalInsts = 36,
      53             :   FeatureFlatInstOffsets = 37,
      54             :   FeatureFlatScratchInsts = 38,
      55             :   FeatureFmaMixInsts = 39,
      56             :   FeatureGCN = 40,
      57             :   FeatureGCN3Encoding = 41,
      58             :   FeatureGFX9 = 42,
      59             :   FeatureGFX9Insts = 43,
      60             :   FeatureISAVersion6_0_0 = 44,
      61             :   FeatureISAVersion6_0_1 = 45,
      62             :   FeatureISAVersion7_0_0 = 46,
      63             :   FeatureISAVersion7_0_1 = 47,
      64             :   FeatureISAVersion7_0_2 = 48,
      65             :   FeatureISAVersion7_0_3 = 49,
      66             :   FeatureISAVersion7_0_4 = 50,
      67             :   FeatureISAVersion8_0_1 = 51,
      68             :   FeatureISAVersion8_0_2 = 52,
      69             :   FeatureISAVersion8_0_3 = 53,
      70             :   FeatureISAVersion8_1_0 = 54,
      71             :   FeatureISAVersion9_0_0 = 55,
      72             :   FeatureISAVersion9_0_2 = 56,
      73             :   FeatureISAVersion9_0_4 = 57,
      74             :   FeatureISAVersion9_0_6 = 58,
      75             :   FeatureIntClamp = 59,
      76             :   FeatureInv2PiInlineImm = 60,
      77             :   FeatureLDSBankCount16 = 61,
      78             :   FeatureLDSBankCount32 = 62,
      79             :   FeatureLocalMemorySize0 = 63,
      80             :   FeatureLocalMemorySize32768 = 64,
      81             :   FeatureLocalMemorySize65536 = 65,
      82             :   FeatureMIMG_R128 = 66,
      83             :   FeatureMadMixInsts = 67,
      84             :   FeatureMaxPrivateElementSize4 = 68,
      85             :   FeatureMaxPrivateElementSize8 = 69,
      86             :   FeatureMaxPrivateElementSize16 = 70,
      87             :   FeatureMovrel = 71,
      88             :   FeatureNorthernIslands = 72,
      89             :   FeaturePromoteAlloca = 73,
      90             :   FeatureR600 = 74,
      91             :   FeatureR600ALUInst = 75,
      92             :   FeatureR700 = 76,
      93             :   FeatureSDWA = 77,
      94             :   FeatureSDWAMac = 78,
      95             :   FeatureSDWAOmod = 79,
      96             :   FeatureSDWAOutModsVOPC = 80,
      97             :   FeatureSDWAScalar = 81,
      98             :   FeatureSDWASdst = 82,
      99             :   FeatureSGPRInitBug = 83,
     100             :   FeatureSMemRealTime = 84,
     101             :   FeatureScalarAtomics = 85,
     102             :   FeatureScalarStores = 86,
     103             :   FeatureSeaIslands = 87,
     104             :   FeatureSouthernIslands = 88,
     105             :   FeatureTrapHandler = 89,
     106             :   FeatureUnalignedBufferAccess = 90,
     107             :   FeatureUnalignedScratchAccess = 91,
     108             :   FeatureUnpackedD16VMem = 92,
     109             :   FeatureVGPRIndexMode = 93,
     110             :   FeatureVGPRSpilling = 94,
     111             :   FeatureVOP3P = 95,
     112             :   FeatureVertexCache = 96,
     113             :   FeatureVolcanicIslands = 97,
     114             :   FeatureWavefrontSize16 = 98,
     115             :   FeatureWavefrontSize32 = 99,
     116             :   FeatureWavefrontSize64 = 100,
     117             :   FeatureXNACK = 101,
     118             :   HalfRate64Ops = 102,
     119             : };
     120             : } // end namespace AMDGPU
     121             : } // end namespace llvm
     122             : 
     123             : #endif // GET_SUBTARGETINFO_ENUM
     124             : 
     125             : 
     126             : #ifdef GET_SUBTARGETINFO_MC_DESC
     127             : #undef GET_SUBTARGETINFO_MC_DESC
     128             : 
     129             : namespace llvm {
     130             : // Sorted (by key) array of values for CPU features.
     131             : extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[] = {
     132             :   { "16-bit-insts", "Has i16/f16 instructions", { AMDGPU::Feature16BitInsts }, { } },
     133             :   { "DumpCode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCode }, { } },
     134             :   { "EVERGREEN", "EVERGREEN GPU generation", { AMDGPU::FeatureEvergreen }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureLocalMemorySize32768 } },
     135             :   { "GFX9", "GFX9 GPU generation", { AMDGPU::FeatureGFX9 }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureApertureRegs, AMDGPU::FeatureGFX9Insts, AMDGPU::FeatureVOP3P, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOmod, AMDGPU::FeatureSDWAScalar, AMDGPU::FeatureSDWASdst, AMDGPU::FeatureFlatInstOffsets, AMDGPU::FeatureFlatGlobalInsts, AMDGPU::FeatureFlatScratchInsts, AMDGPU::FeatureAddNoCarryInsts, AMDGPU::FeatureScalarAtomics } },
     136             :   { "HasVertexCache", "Specify use of dedicated vertex cache", { AMDGPU::FeatureVertexCache }, { } },
     137             :   { "NORTHERN_ISLANDS", "NORTHERN_ISLANDS GPU generation", { AMDGPU::FeatureNorthernIslands }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureLocalMemorySize32768 } },
     138             :   { "R600", "R600 GPU generation", { AMDGPU::FeatureR600 }, { AMDGPU::FeatureR600ALUInst, AMDGPU::FeatureFetchLimit8, AMDGPU::FeatureLocalMemorySize0 } },
     139             :   { "R600ALUInst", "Older version of ALU instructions encoding", { AMDGPU::FeatureR600ALUInst }, { } },
     140             :   { "R700", "R700 GPU generation", { AMDGPU::FeatureR700 }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureLocalMemorySize0 } },
     141             :   { "SEA_ISLANDS", "SEA_ISLANDS GPU generation", { AMDGPU::FeatureSeaIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureCIInsts, AMDGPU::FeatureMovrel } },
     142             :   { "SOUTHERN_ISLANDS", "SOUTHERN_ISLANDS GPU generation", { AMDGPU::FeatureSouthernIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize32768, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureMovrel } },
     143             :   { "VOLCANIC_ISLANDS", "VOLCANIC_ISLANDS GPU generation", { AMDGPU::FeatureVolcanicIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureMovrel, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOutModsVOPC, AMDGPU::FeatureSDWAMac, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp } },
     144             :   { "add-no-carry-insts", "Have VALU add/sub instructions without carry out", { AMDGPU::FeatureAddNoCarryInsts }, { } },
     145             :   { "amdgpu-debugger-emit-prologue", "Emit debugger prologue", { AMDGPU::FeatureDebuggerEmitPrologue }, { } },
     146             :   { "amdgpu-debugger-insert-nops", "Insert one nop instruction for each high level source statement", { AMDGPU::FeatureDebuggerInsertNops }, { } },
     147             :   { "amdgpu-debugger-reserve-regs", "Reserve registers for debugger usage", { AMDGPU::FeatureDebuggerReserveRegs }, { } },
     148             :   { "aperture-regs", "Has Memory Aperture Base and Size Registers", { AMDGPU::FeatureApertureRegs }, { } },
     149             :   { "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", { AMDGPU::FeatureAutoWaitcntBeforeBarrier }, { } },
     150             :   { "caymanISA", "Use Cayman ISA", { AMDGPU::FeatureCaymanISA }, { } },
     151             :   { "cfalubug", "GPU has CF_ALU bug", { AMDGPU::FeatureCFALUBug }, { } },
     152             :   { "ci-insts", "Additional instructions for CI+", { AMDGPU::FeatureCIInsts }, { } },
     153             :   { "code-object-v3", "Generate code object version 3", { AMDGPU::FeatureCodeObjectV3 }, { } },
     154             :   { "d16-preserves-unused-bits", "If present, then instructions defined by HasD16LoadStore predicate preserve unused bits. Otherwise instructions defined by HasD16LoadStore predicate zero unused bits.", { AMDGPU::FeatureD16PreservesUnusedBits }, { } },
     155             :   { "dl-insts", "Has deep learning instructions", { AMDGPU::FeatureDLInsts }, { } },
     156             :   { "dpp", "Support DPP (Data Parallel Primitives) extension", { AMDGPU::FeatureDPP }, { } },
     157             :   { "dumpcode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCodeLower }, { } },
     158             :   { "dx10-clamp", "clamp modifier clamps NaNs to 0.0", { AMDGPU::FeatureDX10Clamp }, { } },
     159             :   { "enable-ds128", "Use ds_{read|write}_b128", { AMDGPU::FeatureEnableDS128 }, { } },
     160             :   { "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", { AMDGPU::FeatureFastFMAF32 }, { } },
     161             :   { "fetch16", "Limit the maximum number of fetches in a clause to 16", { AMDGPU::FeatureFetchLimit16 }, { } },
     162             :   { "fetch8", "Limit the maximum number of fetches in a clause to 8", { AMDGPU::FeatureFetchLimit8 }, { } },
     163             :   { "flat-address-space", "Support flat address space", { AMDGPU::FeatureFlatAddressSpace }, { } },
     164             :   { "flat-for-global", "Force to generate flat instruction for global", { AMDGPU::FeatureFlatForGlobal }, { } },
     165             :   { "flat-global-insts", "Have global_* flat memory instructions", { AMDGPU::FeatureFlatGlobalInsts }, { } },
     166             :   { "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", { AMDGPU::FeatureFlatInstOffsets }, { } },
     167             :   { "flat-scratch-insts", "Have scratch_* flat memory instructions", { AMDGPU::FeatureFlatScratchInsts }, { } },
     168             :   { "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", { AMDGPU::FeatureFmaMixInsts }, { } },
     169             :   { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", { AMDGPU::FeatureFMA }, { } },
     170             :   { "fp-exceptions", "Enable floating point exceptions", { AMDGPU::FeatureFPExceptions }, { } },
     171             :   { "fp16-denormals", "Enable half precision denormal handling", { AMDGPU::FeatureFP16Denormals }, { AMDGPU::FeatureFP64FP16Denormals } },
     172             :   { "fp32-denormals", "Enable single precision denormal handling", { AMDGPU::FeatureFP32Denormals }, { } },
     173             :   { "fp64", "Enable double precision operations", { AMDGPU::FeatureFP64 }, { } },
     174             :   { "fp64-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64Denormals }, { AMDGPU::FeatureFP64, AMDGPU::FeatureFP64FP16Denormals } },
     175             :   { "fp64-fp16-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64FP16Denormals }, { AMDGPU::FeatureFP64 } },
     176             :   { "gcn", "GCN or newer GPU", { AMDGPU::FeatureGCN }, { } },
     177             :   { "gcn3-encoding", "Encoding format for VI", { AMDGPU::FeatureGCN3Encoding }, { } },
     178             :   { "gfx9-insts", "Additional instructions for GFX9+", { AMDGPU::FeatureGFX9Insts }, { } },
     179             :   { "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", { AMDGPU::HalfRate64Ops }, { } },
     180             :   { "huge-private-buffer", "Enable private/scratch buffer sizes greater than 128 GB", { AMDGPU::FeatureEnableHugePrivateBuffer }, { } },
     181             :   { "int-clamp-insts", "Support clamp for integer destination", { AMDGPU::FeatureIntClamp }, { } },
     182             :   { "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", { AMDGPU::FeatureInv2PiInlineImm }, { } },
     183             :   { "isaver6.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion6_0_0 }, { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32 } },
     184             :   { "isaver6.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion6_0_1 }, { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32 } },
     185             :   { "isaver7.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_0 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32 } },
     186             :   { "isaver7.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_1 }, { AMDGPU::FeatureSeaIslands, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFastFMAF32 } },
     187             :   { "isaver7.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_2 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureFastFMAF32 } },
     188             :   { "isaver7.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_3 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16 } },
     189             :   { "isaver7.0.4", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_4 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32 } },
     190             :   { "isaver8.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_1 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureUnpackedD16VMem } },
     191             :   { "isaver8.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_2 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureSGPRInitBug, AMDGPU::FeatureUnpackedD16VMem } },
     192             :   { "isaver8.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_3 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureUnpackedD16VMem } },
     193             :   { "isaver8.1.0", "Instruction set version number", { AMDGPU::FeatureISAVersion8_1_0 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureXNACK } },
     194             :   { "isaver9.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_0 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureD16PreservesUnusedBits } },
     195             :   { "isaver9.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_2 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureD16PreservesUnusedBits } },
     196             :   { "isaver9.0.4", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_4 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFmaMixInsts, AMDGPU::FeatureD16PreservesUnusedBits } },
     197             :   { "isaver9.0.6", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_6 }, { AMDGPU::FeatureGFX9, AMDGPU::HalfRate64Ops, AMDGPU::FeatureFmaMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureDLInsts } },
     198             :   { "ldsbankcount16", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount16 }, { } },
     199             :   { "ldsbankcount32", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount32 }, { } },
     200             :   { "load-store-opt", "Enable SI load/store optimizer pass", { AMDGPU::FeatureEnableLoadStoreOpt }, { } },
     201             :   { "localmemorysize0", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize0 }, { } },
     202             :   { "localmemorysize32768", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize32768 }, { } },
     203             :   { "localmemorysize65536", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize65536 }, { } },
     204             :   { "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", { AMDGPU::FeatureMadMixInsts }, { } },
     205             :   { "max-private-element-size-16", "Maximum private access size may be 16", { AMDGPU::FeatureMaxPrivateElementSize16 }, { } },
     206             :   { "max-private-element-size-4", "Maximum private access size may be 4", { AMDGPU::FeatureMaxPrivateElementSize4 }, { } },
     207             :   { "max-private-element-size-8", "Maximum private access size may be 8", { AMDGPU::FeatureMaxPrivateElementSize8 }, { } },
     208             :   { "mimg-r128", "Support 128-bit texture resources", { AMDGPU::FeatureMIMG_R128 }, { } },
     209             :   { "movrel", "Has v_movrel*_b32 instructions", { AMDGPU::FeatureMovrel }, { } },
     210             :   { "promote-alloca", "Enable promote alloca pass", { AMDGPU::FeaturePromoteAlloca }, { } },
     211             :   { "s-memrealtime", "Has s_memrealtime instruction", { AMDGPU::FeatureSMemRealTime }, { } },
     212             :   { "scalar-atomics", "Has atomic scalar memory instructions", { AMDGPU::FeatureScalarAtomics }, { } },
     213             :   { "scalar-stores", "Has store scalar memory instructions", { AMDGPU::FeatureScalarStores }, { } },
     214             :   { "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWA }, { } },
     215             :   { "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAMac }, { } },
     216             :   { "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOmod }, { } },
     217             :   { "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOutModsVOPC }, { } },
     218             :   { "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAScalar }, { } },
     219             :   { "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWASdst }, { } },
     220             :   { "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", { AMDGPU::FeatureSGPRInitBug }, { } },
     221             :   { "si-scheduler", "Enable SI Machine Scheduler", { AMDGPU::FeatureEnableSIScheduler }, { } },
     222             :   { "trap-handler", "Trap handler support", { AMDGPU::FeatureTrapHandler }, { } },
     223             :   { "unaligned-buffer-access", "Support unaligned global loads and stores", { AMDGPU::FeatureUnalignedBufferAccess }, { } },
     224             :   { "unaligned-scratch-access", "Support unaligned scratch loads and stores", { AMDGPU::FeatureUnalignedScratchAccess }, { } },
     225             :   { "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", { AMDGPU::FeatureUnpackedD16VMem }, { } },
     226             :   { "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", { AMDGPU::FeatureEnableUnsafeDSOffsetFolding }, { } },
     227             :   { "vgpr-index-mode", "Has VGPR mode register indexing", { AMDGPU::FeatureVGPRIndexMode }, { } },
     228             :   { "vgpr-spilling", "Enable spilling of VGPRs to scratch memory", { AMDGPU::FeatureVGPRSpilling }, { } },
     229             :   { "vop3p", "Has VOP3P packed instructions", { AMDGPU::FeatureVOP3P }, { } },
     230             :   { "wavefrontsize16", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize16 }, { } },
     231             :   { "wavefrontsize32", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize32 }, { } },
     232             :   { "wavefrontsize64", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize64 }, { } },
     233             :   { "xnack", "Enable XNACK support", { AMDGPU::FeatureXNACK }, { } },
     234       99237 : };
     235             : 
     236             : // Sorted (by key) array of values for CPU subtype.
     237             : extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[] = {
     238             :   { "barts", "Select the barts processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureVertexCache, AMDGPU::FeatureCFALUBug }, { } },
     239             :   { "bonaire", "Select the bonaire processor", { AMDGPU::FeatureISAVersion7_0_4 }, { } },
     240             :   { "caicos", "Select the caicos processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureCFALUBug }, { } },
     241             :   { "carrizo", "Select the carrizo processor", { AMDGPU::FeatureISAVersion8_0_1 }, { } },
     242             :   { "cayman", "Select the cayman processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureCaymanISA, AMDGPU::FeatureFMA }, { } },
     243             :   { "cedar", "Select the cedar processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureWavefrontSize32, AMDGPU::FeatureVertexCache, AMDGPU::FeatureCFALUBug }, { } },
     244             :   { "cypress", "Select the cypress processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureVertexCache, AMDGPU::FeatureFMA }, { } },
     245             :   { "fiji", "Select the fiji processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     246             :   { "generic", "Select the generic processor", { AMDGPU::FeatureGCN, AMDGPU::FeatureWavefrontSize64 }, { } },
     247             :   { "gfx600", "Select the gfx600 processor", { AMDGPU::FeatureISAVersion6_0_0 }, { } },
     248             :   { "gfx601", "Select the gfx601 processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     249             :   { "gfx700", "Select the gfx700 processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
     250             :   { "gfx701", "Select the gfx701 processor", { AMDGPU::FeatureISAVersion7_0_1 }, { } },
     251             :   { "gfx702", "Select the gfx702 processor", { AMDGPU::FeatureISAVersion7_0_2 }, { } },
     252             :   { "gfx703", "Select the gfx703 processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     253             :   { "gfx704", "Select the gfx704 processor", { AMDGPU::FeatureISAVersion7_0_4 }, { } },
     254             :   { "gfx801", "Select the gfx801 processor", { AMDGPU::FeatureISAVersion8_0_1 }, { } },
     255             :   { "gfx802", "Select the gfx802 processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
     256             :   { "gfx803", "Select the gfx803 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     257             :   { "gfx810", "Select the gfx810 processor", { AMDGPU::FeatureISAVersion8_1_0 }, { } },
     258             :   { "gfx900", "Select the gfx900 processor", { AMDGPU::FeatureISAVersion9_0_0 }, { } },
     259             :   { "gfx902", "Select the gfx902 processor", { AMDGPU::FeatureISAVersion9_0_2 }, { } },
     260             :   { "gfx904", "Select the gfx904 processor", { AMDGPU::FeatureISAVersion9_0_4 }, { } },
     261             :   { "gfx906", "Select the gfx906 processor", { AMDGPU::FeatureISAVersion9_0_6 }, { } },
     262             :   { "hainan", "Select the hainan processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     263             :   { "hawaii", "Select the hawaii processor", { AMDGPU::FeatureISAVersion7_0_1 }, { } },
     264             :   { "iceland", "Select the iceland processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
     265             :   { "juniper", "Select the juniper processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureVertexCache }, { } },
     266             :   { "kabini", "Select the kabini processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     267             :   { "kaveri", "Select the kaveri processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
     268             :   { "mullins", "Select the mullins processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     269             :   { "oland", "Select the oland processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     270             :   { "pitcairn", "Select the pitcairn processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     271             :   { "polaris10", "Select the polaris10 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     272             :   { "polaris11", "Select the polaris11 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     273             :   { "r600", "Select the r600 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureVertexCache }, { } },
     274             :   { "r630", "Select the r630 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureWavefrontSize32, AMDGPU::FeatureVertexCache }, { } },
     275             :   { "redwood", "Select the redwood processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureVertexCache, AMDGPU::FeatureCFALUBug }, { } },
     276             :   { "rs880", "Select the rs880 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureWavefrontSize16 }, { } },
     277             :   { "rv670", "Select the rv670 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureVertexCache }, { } },
     278             :   { "rv710", "Select the rv710 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureWavefrontSize32, AMDGPU::FeatureVertexCache }, { } },
     279             :   { "rv730", "Select the rv730 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureWavefrontSize32, AMDGPU::FeatureVertexCache }, { } },
     280             :   { "rv770", "Select the rv770 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureVertexCache }, { } },
     281             :   { "stoney", "Select the stoney processor", { AMDGPU::FeatureISAVersion8_1_0 }, { } },
     282             :   { "sumo", "Select the sumo processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureCFALUBug }, { } },
     283             :   { "tahiti", "Select the tahiti processor", { AMDGPU::FeatureISAVersion6_0_0 }, { } },
     284             :   { "tonga", "Select the tonga processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
     285             :   { "turks", "Select the turks processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureVertexCache, AMDGPU::FeatureCFALUBug }, { } },
     286             :   { "verde", "Select the verde processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     287       99237 : };
     288             : 
     289             : #ifdef DBGFIELD
     290             : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
     291             : #endif
     292             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     293             : #define DBGFIELD(x) x,
     294             : #else
     295             : #define DBGFIELD(x)
     296             : #endif
     297             : 
     298             : // Functional units for "R600_VLIW5_Itin"
     299             : namespace R600_VLIW5_ItinFU {
     300             :   const unsigned ALU_X = 1 << 0;
     301             :   const unsigned ALU_Y = 1 << 1;
     302             :   const unsigned ALU_Z = 1 << 2;
     303             :   const unsigned ALU_W = 1 << 3;
     304             :   const unsigned TRANS = 1 << 4;
     305             :   const unsigned ALU_NULL = 1 << 5;
     306             : } // end namespace R600_VLIW5_ItinFU
     307             : 
     308             : // Functional units for "R600_VLIW4_Itin"
     309             : namespace R600_VLIW4_ItinFU {
     310             :   const unsigned ALU_X = 1 << 0;
     311             :   const unsigned ALU_Y = 1 << 1;
     312             :   const unsigned ALU_Z = 1 << 2;
     313             :   const unsigned ALU_W = 1 << 3;
     314             :   const unsigned ALU_NULL = 1 << 4;
     315             : } // end namespace R600_VLIW4_ItinFU
     316             : 
     317             : extern const llvm::InstrStage AMDGPUStages[] = {
     318             :   { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
     319             :   { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
     320             :   { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
     321             :   { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
     322             :   { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
     323             :   { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
     324             :   { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
     325             :   { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
     326             :   { 0, 0, 0, llvm::InstrStage::Required } // End stages
     327             : };
     328             : extern const unsigned AMDGPUOperandCycles[] = {
     329             :   0, // No itinerary
     330             :   0 // End operand cycles
     331             : };
     332             : extern const unsigned AMDGPUForwardingPaths[] = {
     333             :  0, // No itinerary
     334             :  0 // End bypass tables
     335             : };
     336             : 
     337             : static const llvm::InstrItinerary R600_VLIW5_Itin[] = {
     338             :   { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
     339             :   { 1, 1, 2, 0, 0 }, // 1 AnyALU
     340             :   { 1, 2, 3, 0, 0 }, // 2 NullALU_Write32Bit
     341             :   { 1, 2, 3, 0, 0 }, // 3 NullALU
     342             :   { 1, 3, 4, 0, 0 }, // 4 VecALU
     343             :   { 1, 2, 3, 0, 0 }, // 5 NullALU_WriteVMEM
     344             :   { 1, 4, 5, 0, 0 }, // 6 TransALU
     345             :   { 1, 2, 3, 0, 0 }, // 7 NullALU_WriteLDS
     346             :   { 1, 2, 3, 0, 0 }, // 8 NullALU_WriteExport
     347             :   { 1, 5, 6, 0, 0 }, // 9 XALU
     348             :   { 1, 2, 3, 0, 0 }, // 10 NullALU_WriteBranch
     349             :   { 1, 2, 3, 0, 0 }, // 11 NullALU_WriteSALU
     350             :   { 1, 2, 3, 0, 0 }, // 12 NullALU_WriteSMEM
     351             :   { 1, 2, 3, 0, 0 }, // 13 NullALU_WriteBarrier
     352             :   { 1, 2, 3, 0, 0 }, // 14 NullALU_Write32Bit_WriteSALU
     353             :   { 1, 2, 3, 0, 0 }, // 15 NullALU_WriteDoubleAdd
     354             :   { 1, 2, 3, 0, 0 }, // 16 NullALU_Write64Bit
     355             :   { 1, 2, 3, 0, 0 }, // 17 NullALU_WriteQuarterRate32
     356             :   { 1, 2, 3, 0, 0 }, // 18 NullALU_WriteFloatFMA
     357             :   { 1, 2, 3, 0, 0 }, // 19 NullALU_WriteDouble
     358             :   { 1, 2, 3, 0, 0 }, // 20 NullALU_WriteFloatFMA_WriteSALU
     359             :   { 1, 2, 3, 0, 0 }, // 21 NullALU_WriteDouble_WriteSALU
     360             :   { 1, 2, 3, 0, 0 }, // 22 NullALU_WriteQuarterRate32_WriteSALU
     361             :   { 1, 2, 3, 0, 0 }, // 23 NullALU_Write64Bit_Write64Bit
     362             :   { 0, 0, 0, 0, 0 }, // 24 COPY
     363             :   { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
     364             : };
     365             : 
     366             : static const llvm::InstrItinerary R600_VLIW4_Itin[] = {
     367             :   { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
     368             :   { 1, 6, 7, 0, 0 }, // 1 AnyALU
     369             :   { 1, 7, 8, 0, 0 }, // 2 NullALU_Write32Bit
     370             :   { 1, 7, 8, 0, 0 }, // 3 NullALU
     371             :   { 1, 6, 7, 0, 0 }, // 4 VecALU
     372             :   { 1, 7, 8, 0, 0 }, // 5 NullALU_WriteVMEM
     373             :   { 1, 7, 8, 0, 0 }, // 6 TransALU
     374             :   { 1, 7, 8, 0, 0 }, // 7 NullALU_WriteLDS
     375             :   { 1, 7, 8, 0, 0 }, // 8 NullALU_WriteExport
     376             :   { 0, 0, 0, 0, 0 }, // 9 XALU
     377             :   { 1, 7, 8, 0, 0 }, // 10 NullALU_WriteBranch
     378             :   { 1, 7, 8, 0, 0 }, // 11 NullALU_WriteSALU
     379             :   { 1, 7, 8, 0, 0 }, // 12 NullALU_WriteSMEM
     380             :   { 1, 7, 8, 0, 0 }, // 13 NullALU_WriteBarrier
     381             :   { 1, 7, 8, 0, 0 }, // 14 NullALU_Write32Bit_WriteSALU
     382             :   { 1, 7, 8, 0, 0 }, // 15 NullALU_WriteDoubleAdd
     383             :   { 1, 7, 8, 0, 0 }, // 16 NullALU_Write64Bit
     384             :   { 1, 7, 8, 0, 0 }, // 17 NullALU_WriteQuarterRate32
     385             :   { 1, 7, 8, 0, 0 }, // 18 NullALU_WriteFloatFMA
     386             :   { 1, 7, 8, 0, 0 }, // 19 NullALU_WriteDouble
     387             :   { 1, 7, 8, 0, 0 }, // 20 NullALU_WriteFloatFMA_WriteSALU
     388             :   { 1, 7, 8, 0, 0 }, // 21 NullALU_WriteDouble_WriteSALU
     389             :   { 1, 7, 8, 0, 0 }, // 22 NullALU_WriteQuarterRate32_WriteSALU
     390             :   { 1, 7, 8, 0, 0 }, // 23 NullALU_Write64Bit_Write64Bit
     391             :   { 0, 0, 0, 0, 0 }, // 24 COPY
     392             :   { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
     393             : };
     394             : 
     395             : // ===============================================================
     396             : // Data tables for the new per-operand machine model.
     397             : 
     398             : // {ProcResourceIdx, Cycles}
     399             : extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = {
     400             :   { 0,  0}, // Invalid
     401             :   { 5,  1}, // #1
     402             :   { 6,  1}, // #2
     403             :   { 3,  1}, // #3
     404             :   { 2,  1}, // #4
     405             :   { 1,  1}, // #5
     406             :   { 4,  1}, // #6
     407             :   { 4,  1}, // #7
     408             :   { 5,  1}, // #8
     409             :   { 5,  2} // #9
     410             : }; // AMDGPUWriteProcResTable
     411             : 
     412             : // {Cycles, WriteResourceID}
     413             : extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = {
     414             :   { 0,  0}, // Invalid
     415             :   { 1,  0}, // #1 Write32Bit_WriteSALU_WriteFloatFMA
     416             :   {80,  0}, // #2 WriteVMEM
     417             :   { 5,  0}, // #3 WriteLDS_WriteSMEM
     418             :   { 4,  0}, // #4 WriteExport_WriteQuarterRate32_WriteDouble
     419             :   { 8,  0}, // #5 WriteBranch_WriteDoubleAdd
     420             :   {500,  0}, // #6 WriteBarrier
     421             :   { 1,  0}, // #7 Write32Bit_WriteFloatFMA
     422             :   { 1,  0}, // #8 WriteSALU
     423             :   { 2,  0}, // #9 Write64Bit_WriteDoubleAdd
     424             :   {16,  0}, // #10 WriteFloatFMA_WriteDouble
     425             :   {16,  0}, // #11 WriteFloatFMA_WriteDouble
     426             :   { 1,  0}, // #12 WriteSALU
     427             :   { 4,  0}, // #13 WriteQuarterRate32_WriteDouble
     428             :   { 1,  0}, // #14 WriteSALU
     429             :   { 2,  0}, // #15 Write64Bit
     430             :   { 2,  0} // #16 Write64Bit
     431             : }; // AMDGPUWriteLatencyTable
     432             : 
     433             : // {UseIdx, WriteResourceID, Cycles}
     434             : extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = {
     435             :   {0,  0,  0}, // Invalid
     436             : }; // AMDGPUReadAdvanceTable
     437             : 
     438             : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
     439             : static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = {
     440             :   {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
     441             :   {DBGFIELD("AnyALU")             0, false, false,  0, 0,  0, 0,  0, 0}, // #1
     442             :   {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #2
     443             :   {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #3
     444             :   {DBGFIELD("VecALU")             0, false, false,  0, 0,  0, 0,  0, 0}, // #4
     445             :   {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #5
     446             :   {DBGFIELD("TransALU")           0, false, false,  0, 0,  0, 0,  0, 0}, // #6
     447             :   {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #7
     448             :   {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #8
     449             :   {DBGFIELD("XALU")               0, false, false,  0, 0,  0, 0,  0, 0}, // #9
     450             :   {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #10
     451             :   {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #11
     452             :   {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #12
     453             :   {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1,  6, 1,  0, 0}, // #13
     454             :   {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  7, 2,  0, 0}, // #14
     455             :   {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  5, 1,  0, 0}, // #15
     456             :   {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  9, 1,  0, 0}, // #16
     457             :   {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #17
     458             :   {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1, 10, 1,  0, 0}, // #18
     459             :   {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1, 10, 1,  0, 0}, // #19
     460             :   {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2, 11, 2,  0, 0}, // #20
     461             :   {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 11, 2,  0, 0}, // #21
     462             :   {DBGFIELD("NullALU_WriteQuarterRate32_WriteSALU") 2, false, false,  7, 2, 13, 2,  0, 0}, // #22
     463             :   {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 15, 2,  0, 0}, // #23
     464             :   {DBGFIELD("COPY")               16382, false, false,  0, 0,  0, 0,  0, 0}, // #24
     465             :   {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #25
     466             :   {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  9, 1,  0, 0}, // #26
     467             :   {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0}, // #27
     468             : }; // SIQuarterSpeedModelSchedClasses
     469             : 
     470             : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
     471             : static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = {
     472             :   {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
     473             :   {DBGFIELD("AnyALU")             0, false, false,  0, 0,  0, 0,  0, 0}, // #1
     474             :   {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #2
     475             :   {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #3
     476             :   {DBGFIELD("VecALU")             0, false, false,  0, 0,  0, 0,  0, 0}, // #4
     477             :   {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #5
     478             :   {DBGFIELD("TransALU")           0, false, false,  0, 0,  0, 0,  0, 0}, // #6
     479             :   {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #7
     480             :   {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #8
     481             :   {DBGFIELD("XALU")               0, false, false,  0, 0,  0, 0,  0, 0}, // #9
     482             :   {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #10
     483             :   {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #11
     484             :   {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #12
     485             :   {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1,  6, 1,  0, 0}, // #13
     486             :   {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  7, 2,  0, 0}, // #14
     487             :   {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  9, 1,  0, 0}, // #15
     488             :   {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  9, 1,  0, 0}, // #16
     489             :   {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #17
     490             :   {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1,  1, 1,  0, 0}, // #18
     491             :   {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1,  4, 1,  0, 0}, // #19
     492             :   {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2,  7, 2,  0, 0}, // #20
     493             :   {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 13, 2,  0, 0}, // #21
     494             :   {DBGFIELD("NullALU_WriteQuarterRate32_WriteSALU") 2, false, false,  7, 2, 13, 2,  0, 0}, // #22
     495             :   {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 15, 2,  0, 0}, // #23
     496             :   {DBGFIELD("COPY")               16382, false, false,  0, 0,  0, 0,  0, 0}, // #24
     497             :   {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #25
     498             :   {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  9, 1,  0, 0}, // #26
     499             :   {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0}, // #27
     500             : }; // SIFullSpeedModelSchedClasses
     501             : 
     502             : static const llvm::MCSchedModel NoSchedModel = {
     503             :   MCSchedModel::DefaultIssueWidth,
     504             :   MCSchedModel::DefaultMicroOpBufferSize,
     505             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     506             :   MCSchedModel::DefaultLoadLatency,
     507             :   MCSchedModel::DefaultHighLatency,
     508             :   MCSchedModel::DefaultMispredictPenalty,
     509             :   false, // PostRAScheduler
     510             :   false, // CompleteModel
     511             :   0, // Processor ID
     512             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     513             :   nullptr, // No Itinerary
     514             :   nullptr // No extra processor descriptor
     515             : };
     516             : 
     517             : static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
     518             :   MCSchedModel::DefaultIssueWidth,
     519             :   MCSchedModel::DefaultMicroOpBufferSize,
     520             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     521             :   MCSchedModel::DefaultLoadLatency,
     522             :   MCSchedModel::DefaultHighLatency,
     523             :   MCSchedModel::DefaultMispredictPenalty,
     524             :   false, // PostRAScheduler
     525             :   false, // CompleteModel
     526             :   1, // Processor ID
     527             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     528             :   R600_VLIW5_Itin,
     529             :   nullptr // No extra processor descriptor
     530             : };
     531             : 
     532             : static const unsigned SIQuarterSpeedModelProcResourceSubUnits[] = {
     533             :   0,  // Invalid
     534             : };
     535             : 
     536             : // {Name, NumUnits, SuperIdx, IsBuffered, SubUnitsIdxBegin}
     537             : static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = {
     538             :   {"InvalidUnit", 0, 0, 0, 0},
     539             :   {"HWBranch",        1, 0, 1, nullptr}, // #1
     540             :   {"HWExport",        1, 0, 7, nullptr}, // #2
     541             :   {"HWLGKM",          1, 0, 31, nullptr}, // #3
     542             :   {"HWSALU",          1, 0, 1, nullptr}, // #4
     543             :   {"HWVALU",          1, 0, 1, nullptr}, // #5
     544             :   {"HWVMEM",          1, 0, 15, nullptr}, // #6
     545             : };
     546             : 
     547             : static const llvm::MCSchedModel SIQuarterSpeedModel = {
     548             :   1, // IssueWidth
     549             :   1, // MicroOpBufferSize
     550             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     551             :   MCSchedModel::DefaultLoadLatency,
     552             :   MCSchedModel::DefaultHighLatency,
     553             :   20, // MispredictPenalty
     554             :   true, // PostRAScheduler
     555             :   false, // CompleteModel
     556             :   2, // Processor ID
     557             :   SIQuarterSpeedModelProcResources,
     558             :   SIQuarterSpeedModelSchedClasses,
     559             :   7,
     560             :   28,
     561             :   nullptr, // No Itinerary
     562             :   nullptr // No extra processor descriptor
     563             : };
     564             : 
     565             : static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
     566             :   MCSchedModel::DefaultIssueWidth,
     567             :   MCSchedModel::DefaultMicroOpBufferSize,
     568             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     569             :   MCSchedModel::DefaultLoadLatency,
     570             :   MCSchedModel::DefaultHighLatency,
     571             :   MCSchedModel::DefaultMispredictPenalty,
     572             :   false, // PostRAScheduler
     573             :   false, // CompleteModel
     574             :   3, // Processor ID
     575             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     576             :   R600_VLIW4_Itin,
     577             :   nullptr // No extra processor descriptor
     578             : };
     579             : 
     580             : static const unsigned SIFullSpeedModelProcResourceSubUnits[] = {
     581             :   0,  // Invalid
     582             : };
     583             : 
     584             : // {Name, NumUnits, SuperIdx, IsBuffered, SubUnitsIdxBegin}
     585             : static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = {
     586             :   {"InvalidUnit", 0, 0, 0, 0},
     587             :   {"HWBranch",        1, 0, 1, nullptr}, // #1
     588             :   {"HWExport",        1, 0, 7, nullptr}, // #2
     589             :   {"HWLGKM",          1, 0, 31, nullptr}, // #3
     590             :   {"HWSALU",          1, 0, 1, nullptr}, // #4
     591             :   {"HWVALU",          1, 0, 1, nullptr}, // #5
     592             :   {"HWVMEM",          1, 0, 15, nullptr}, // #6
     593             : };
     594             : 
     595             : static const llvm::MCSchedModel SIFullSpeedModel = {
     596             :   1, // IssueWidth
     597             :   1, // MicroOpBufferSize
     598             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     599             :   MCSchedModel::DefaultLoadLatency,
     600             :   MCSchedModel::DefaultHighLatency,
     601             :   20, // MispredictPenalty
     602             :   true, // PostRAScheduler
     603             :   false, // CompleteModel
     604             :   4, // Processor ID
     605             :   SIFullSpeedModelProcResources,
     606             :   SIFullSpeedModelSchedClasses,
     607             :   7,
     608             :   28,
     609             :   nullptr, // No Itinerary
     610             :   nullptr // No extra processor descriptor
     611             : };
     612             : 
     613             : // Sorted (by key) array of itineraries for CPU subtype.
     614             : extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[] = {
     615             :   { "barts", (const void *)&R600_VLIW5_ItinModel },
     616             :   { "bonaire", (const void *)&SIQuarterSpeedModel },
     617             :   { "caicos", (const void *)&R600_VLIW5_ItinModel },
     618             :   { "carrizo", (const void *)&SIQuarterSpeedModel },
     619             :   { "cayman", (const void *)&R600_VLIW4_ItinModel },
     620             :   { "cedar", (const void *)&R600_VLIW5_ItinModel },
     621             :   { "cypress", (const void *)&R600_VLIW5_ItinModel },
     622             :   { "fiji", (const void *)&SIQuarterSpeedModel },
     623             :   { "generic", (const void *)&NoSchedModel },
     624             :   { "gfx600", (const void *)&SIFullSpeedModel },
     625             :   { "gfx601", (const void *)&SIQuarterSpeedModel },
     626             :   { "gfx700", (const void *)&SIQuarterSpeedModel },
     627             :   { "gfx701", (const void *)&SIFullSpeedModel },
     628             :   { "gfx702", (const void *)&SIQuarterSpeedModel },
     629             :   { "gfx703", (const void *)&SIQuarterSpeedModel },
     630             :   { "gfx704", (const void *)&SIQuarterSpeedModel },
     631             :   { "gfx801", (const void *)&SIQuarterSpeedModel },
     632             :   { "gfx802", (const void *)&SIQuarterSpeedModel },
     633             :   { "gfx803", (const void *)&SIQuarterSpeedModel },
     634             :   { "gfx810", (const void *)&SIQuarterSpeedModel },
     635             :   { "gfx900", (const void *)&SIQuarterSpeedModel },
     636             :   { "gfx902", (const void *)&SIQuarterSpeedModel },
     637             :   { "gfx904", (const void *)&SIQuarterSpeedModel },
     638             :   { "gfx906", (const void *)&SIQuarterSpeedModel },
     639             :   { "hainan", (const void *)&SIQuarterSpeedModel },
     640             :   { "hawaii", (const void *)&SIFullSpeedModel },
     641             :   { "iceland", (const void *)&SIQuarterSpeedModel },
     642             :   { "juniper", (const void *)&R600_VLIW5_ItinModel },
     643             :   { "kabini", (const void *)&SIQuarterSpeedModel },
     644             :   { "kaveri", (const void *)&SIQuarterSpeedModel },
     645             :   { "mullins", (const void *)&SIQuarterSpeedModel },
     646             :   { "oland", (const void *)&SIQuarterSpeedModel },
     647             :   { "pitcairn", (const void *)&SIQuarterSpeedModel },
     648             :   { "polaris10", (const void *)&SIQuarterSpeedModel },
     649             :   { "polaris11", (const void *)&SIQuarterSpeedModel },
     650             :   { "r600", (const void *)&R600_VLIW5_ItinModel },
     651             :   { "r630", (const void *)&R600_VLIW5_ItinModel },
     652             :   { "redwood", (const void *)&R600_VLIW5_ItinModel },
     653             :   { "rs880", (const void *)&R600_VLIW5_ItinModel },
     654             :   { "rv670", (const void *)&R600_VLIW5_ItinModel },
     655             :   { "rv710", (const void *)&R600_VLIW5_ItinModel },
     656             :   { "rv730", (const void *)&R600_VLIW5_ItinModel },
     657             :   { "rv770", (const void *)&R600_VLIW5_ItinModel },
     658             :   { "stoney", (const void *)&SIQuarterSpeedModel },
     659             :   { "sumo", (const void *)&R600_VLIW5_ItinModel },
     660             :   { "tahiti", (const void *)&SIFullSpeedModel },
     661             :   { "tonga", (const void *)&SIQuarterSpeedModel },
     662             :   { "turks", (const void *)&R600_VLIW5_ItinModel },
     663             :   { "verde", (const void *)&SIQuarterSpeedModel },
     664             : };
     665             : 
     666             : #undef DBGFIELD
     667             : 
     668        2923 : static inline MCSubtargetInfo *createAMDGPUMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
     669             :   return new MCSubtargetInfo(TT, CPU, FS, AMDGPUFeatureKV, AMDGPUSubTypeKV, 
     670             :                       AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
     671        5846 :                       AMDGPUStages, AMDGPUOperandCycles, AMDGPUForwardingPaths);
     672             : }
     673             : 
     674             : } // end namespace llvm
     675             : 
     676             : #endif // GET_SUBTARGETINFO_MC_DESC
     677             : 
     678             : 
     679             : #ifdef GET_SUBTARGETINFO_TARGET_DESC
     680             : #undef GET_SUBTARGETINFO_TARGET_DESC
     681             : 
     682             : #include "llvm/Support/Debug.h"
     683             : #include "llvm/Support/raw_ostream.h"
     684             : 
     685             : // ParseSubtargetFeatures - Parses features string setting specified
     686             : // subtarget options.
     687        2489 : void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
     688             :   LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
     689             :   LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
     690        2489 :   InitMCProcessorInfo(CPU, FS);
     691             :   const FeatureBitset& Bits = getFeatureBits();
     692        2489 :   if (Bits[AMDGPU::Feature16BitInsts]) Has16BitInsts = true;
     693        2489 :   if (Bits[AMDGPU::FeatureAddNoCarryInsts]) AddNoCarryInsts = true;
     694        2489 :   if (Bits[AMDGPU::FeatureApertureRegs]) HasApertureRegs = true;
     695        2489 :   if (Bits[AMDGPU::FeatureAutoWaitcntBeforeBarrier]) AutoWaitcntBeforeBarrier = true;
     696        2489 :   if (Bits[AMDGPU::FeatureCFALUBug]) CFALUBug = true;
     697        2489 :   if (Bits[AMDGPU::FeatureCIInsts]) CIInsts = true;
     698        2489 :   if (Bits[AMDGPU::FeatureCaymanISA]) CaymanISA = true;
     699        2489 :   if (Bits[AMDGPU::FeatureCodeObjectV3]) CodeObjectV3 = true;
     700        2489 :   if (Bits[AMDGPU::FeatureD16PreservesUnusedBits]) D16PreservesUnusedBits = true;
     701        2489 :   if (Bits[AMDGPU::FeatureDLInsts]) HasDLInsts = true;
     702        2489 :   if (Bits[AMDGPU::FeatureDPP]) HasDPP = true;
     703        2489 :   if (Bits[AMDGPU::FeatureDX10Clamp]) DX10Clamp = true;
     704        2489 :   if (Bits[AMDGPU::FeatureDebuggerEmitPrologue]) DebuggerEmitPrologue = true;
     705        2489 :   if (Bits[AMDGPU::FeatureDebuggerInsertNops]) DebuggerInsertNops = true;
     706        2489 :   if (Bits[AMDGPU::FeatureDebuggerReserveRegs]) DebuggerReserveRegs = true;
     707        2489 :   if (Bits[AMDGPU::FeatureDisable]) FeatureDisable = true;
     708        2489 :   if (Bits[AMDGPU::FeatureDumpCode]) DumpCode = true;
     709        2489 :   if (Bits[AMDGPU::FeatureDumpCodeLower]) DumpCode = true;
     710        2489 :   if (Bits[AMDGPU::FeatureEnableDS128]) EnableDS128 = true;
     711        2489 :   if (Bits[AMDGPU::FeatureEnableHugePrivateBuffer]) EnableHugePrivateBuffer = true;
     712        2489 :   if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) EnableLoadStoreOpt = true;
     713        2489 :   if (Bits[AMDGPU::FeatureEnableSIScheduler]) EnableSIScheduler = true;
     714        2489 :   if (Bits[AMDGPU::FeatureEnableUnsafeDSOffsetFolding]) EnableUnsafeDSOffsetFolding = true;
     715        2489 :   if (Bits[AMDGPU::FeatureEvergreen] && Gen < AMDGPUSubtarget::EVERGREEN) Gen = AMDGPUSubtarget::EVERGREEN;
     716        2489 :   if (Bits[AMDGPU::FeatureFMA]) FMA = true;
     717        2489 :   if (Bits[AMDGPU::FeatureFP16Denormals]) FP64FP16Denormals = true;
     718        2489 :   if (Bits[AMDGPU::FeatureFP32Denormals]) FP32Denormals = true;
     719        2489 :   if (Bits[AMDGPU::FeatureFP64]) FP64 = true;
     720        2489 :   if (Bits[AMDGPU::FeatureFP64Denormals]) FP64FP16Denormals = true;
     721        2489 :   if (Bits[AMDGPU::FeatureFP64FP16Denormals]) FP64FP16Denormals = true;
     722        2489 :   if (Bits[AMDGPU::FeatureFPExceptions]) FPExceptions = true;
     723        2489 :   if (Bits[AMDGPU::FeatureFastFMAF32]) FastFMAF32 = true;
     724        2489 :   if (Bits[AMDGPU::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
     725        2489 :   if (Bits[AMDGPU::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
     726        2489 :   if (Bits[AMDGPU::FeatureFlatAddressSpace]) FlatAddressSpace = true;
     727        2489 :   if (Bits[AMDGPU::FeatureFlatForGlobal]) FlatForGlobal = true;
     728        2489 :   if (Bits[AMDGPU::FeatureFlatGlobalInsts]) FlatGlobalInsts = true;
     729        2489 :   if (Bits[AMDGPU::FeatureFlatInstOffsets]) FlatInstOffsets = true;
     730        2489 :   if (Bits[AMDGPU::FeatureFlatScratchInsts]) FlatScratchInsts = true;
     731        2489 :   if (Bits[AMDGPU::FeatureFmaMixInsts]) HasFmaMixInsts = true;
     732        2489 :   if (Bits[AMDGPU::FeatureGCN]) IsGCN = true;
     733        2489 :   if (Bits[AMDGPU::FeatureGCN3Encoding]) GCN3Encoding = true;
     734        2489 :   if (Bits[AMDGPU::FeatureGFX9] && Gen < AMDGPUSubtarget::GFX9) Gen = AMDGPUSubtarget::GFX9;
     735        2489 :   if (Bits[AMDGPU::FeatureGFX9Insts]) GFX9Insts = true;
     736        2489 :   if (Bits[AMDGPU::FeatureISAVersion6_0_0] && IsaVersion < ISAVersion6_0_0) IsaVersion = ISAVersion6_0_0;
     737        2489 :   if (Bits[AMDGPU::FeatureISAVersion6_0_1] && IsaVersion < ISAVersion6_0_1) IsaVersion = ISAVersion6_0_1;
     738        2489 :   if (Bits[AMDGPU::FeatureISAVersion7_0_0] && IsaVersion < ISAVersion7_0_0) IsaVersion = ISAVersion7_0_0;
     739        2489 :   if (Bits[AMDGPU::FeatureISAVersion7_0_1] && IsaVersion < ISAVersion7_0_1) IsaVersion = ISAVersion7_0_1;
     740        2489 :   if (Bits[AMDGPU::FeatureISAVersion7_0_2] && IsaVersion < ISAVersion7_0_2) IsaVersion = ISAVersion7_0_2;
     741        2489 :   if (Bits[AMDGPU::FeatureISAVersion7_0_3] && IsaVersion < ISAVersion7_0_3) IsaVersion = ISAVersion7_0_3;
     742        2489 :   if (Bits[AMDGPU::FeatureISAVersion7_0_4] && IsaVersion < ISAVersion7_0_4) IsaVersion = ISAVersion7_0_4;
     743        2489 :   if (Bits[AMDGPU::FeatureISAVersion8_0_1] && IsaVersion < ISAVersion8_0_1) IsaVersion = ISAVersion8_0_1;
     744        2489 :   if (Bits[AMDGPU::FeatureISAVersion8_0_2] && IsaVersion < ISAVersion8_0_2) IsaVersion = ISAVersion8_0_2;
     745        2489 :   if (Bits[AMDGPU::FeatureISAVersion8_0_3] && IsaVersion < ISAVersion8_0_3) IsaVersion = ISAVersion8_0_3;
     746        2489 :   if (Bits[AMDGPU::FeatureISAVersion8_1_0] && IsaVersion < ISAVersion8_1_0) IsaVersion = ISAVersion8_1_0;
     747        2489 :   if (Bits[AMDGPU::FeatureISAVersion9_0_0] && IsaVersion < ISAVersion9_0_0) IsaVersion = ISAVersion9_0_0;
     748        2489 :   if (Bits[AMDGPU::FeatureISAVersion9_0_2] && IsaVersion < ISAVersion9_0_2) IsaVersion = ISAVersion9_0_2;
     749        2489 :   if (Bits[AMDGPU::FeatureISAVersion9_0_4] && IsaVersion < ISAVersion9_0_4) IsaVersion = ISAVersion9_0_4;
     750        2489 :   if (Bits[AMDGPU::FeatureISAVersion9_0_6] && IsaVersion < ISAVersion9_0_6) IsaVersion = ISAVersion9_0_6;
     751        2489 :   if (Bits[AMDGPU::FeatureIntClamp]) HasIntClamp = true;
     752        2489 :   if (Bits[AMDGPU::FeatureInv2PiInlineImm]) HasInv2PiInlineImm = true;
     753        2489 :   if (Bits[AMDGPU::FeatureLDSBankCount16] && LDSBankCount < 16) LDSBankCount = 16;
     754        2489 :   if (Bits[AMDGPU::FeatureLDSBankCount32] && LDSBankCount < 32) LDSBankCount = 32;
     755        2489 :   if (Bits[AMDGPU::FeatureLocalMemorySize0] && LocalMemorySize < 0) LocalMemorySize = 0;
     756        2489 :   if (Bits[AMDGPU::FeatureLocalMemorySize32768] && LocalMemorySize < 32768) LocalMemorySize = 32768;
     757        2489 :   if (Bits[AMDGPU::FeatureLocalMemorySize65536] && LocalMemorySize < 65536) LocalMemorySize = 65536;
     758        2489 :   if (Bits[AMDGPU::FeatureMIMG_R128]) MIMG_R128 = true;
     759        2489 :   if (Bits[AMDGPU::FeatureMadMixInsts]) HasMadMixInsts = true;
     760        2489 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize4] && MaxPrivateElementSize < 4) MaxPrivateElementSize = 4;
     761        2489 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize8] && MaxPrivateElementSize < 8) MaxPrivateElementSize = 8;
     762        2489 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize16] && MaxPrivateElementSize < 16) MaxPrivateElementSize = 16;
     763        2489 :   if (Bits[AMDGPU::FeatureMovrel]) HasMovrel = true;
     764        2489 :   if (Bits[AMDGPU::FeatureNorthernIslands] && Gen < AMDGPUSubtarget::NORTHERN_ISLANDS) Gen = AMDGPUSubtarget::NORTHERN_ISLANDS;
     765        2489 :   if (Bits[AMDGPU::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
     766        2489 :   if (Bits[AMDGPU::FeatureR600] && Gen < AMDGPUSubtarget::R600) Gen = AMDGPUSubtarget::R600;
     767        2489 :   if (Bits[AMDGPU::FeatureR600ALUInst]) R600ALUInst = false;
     768        2489 :   if (Bits[AMDGPU::FeatureR700] && Gen < AMDGPUSubtarget::R700) Gen = AMDGPUSubtarget::R700;
     769        2489 :   if (Bits[AMDGPU::FeatureSDWA]) HasSDWA = true;
     770        2489 :   if (Bits[AMDGPU::FeatureSDWAMac]) HasSDWAMac = true;
     771        2489 :   if (Bits[AMDGPU::FeatureSDWAOmod]) HasSDWAOmod = true;
     772        2489 :   if (Bits[AMDGPU::FeatureSDWAOutModsVOPC]) HasSDWAOutModsVOPC = true;
     773        2489 :   if (Bits[AMDGPU::FeatureSDWAScalar]) HasSDWAScalar = true;
     774        2489 :   if (Bits[AMDGPU::FeatureSDWASdst]) HasSDWASdst = true;
     775        2489 :   if (Bits[AMDGPU::FeatureSGPRInitBug]) SGPRInitBug = true;
     776        2489 :   if (Bits[AMDGPU::FeatureSMemRealTime]) HasSMemRealTime = true;
     777        2489 :   if (Bits[AMDGPU::FeatureScalarAtomics]) HasScalarAtomics = true;
     778        2489 :   if (Bits[AMDGPU::FeatureScalarStores]) HasScalarStores = true;
     779        2489 :   if (Bits[AMDGPU::FeatureSeaIslands] && Gen < AMDGPUSubtarget::SEA_ISLANDS) Gen = AMDGPUSubtarget::SEA_ISLANDS;
     780        2489 :   if (Bits[AMDGPU::FeatureSouthernIslands] && Gen < AMDGPUSubtarget::SOUTHERN_ISLANDS) Gen = AMDGPUSubtarget::SOUTHERN_ISLANDS;
     781        2489 :   if (Bits[AMDGPU::FeatureTrapHandler]) TrapHandler = true;
     782        2489 :   if (Bits[AMDGPU::FeatureUnalignedBufferAccess]) UnalignedBufferAccess = true;
     783        2489 :   if (Bits[AMDGPU::FeatureUnalignedScratchAccess]) UnalignedScratchAccess = true;
     784        2489 :   if (Bits[AMDGPU::FeatureUnpackedD16VMem]) HasUnpackedD16VMem = true;
     785        2489 :   if (Bits[AMDGPU::FeatureVGPRIndexMode]) HasVGPRIndexMode = true;
     786        2489 :   if (Bits[AMDGPU::FeatureVGPRSpilling]) EnableVGPRSpilling = true;
     787        2489 :   if (Bits[AMDGPU::FeatureVOP3P]) HasVOP3PInsts = true;
     788        2489 :   if (Bits[AMDGPU::FeatureVertexCache]) HasVertexCache = true;
     789        2489 :   if (Bits[AMDGPU::FeatureVolcanicIslands] && Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS) Gen = AMDGPUSubtarget::VOLCANIC_ISLANDS;
     790        2489 :   if (Bits[AMDGPU::FeatureWavefrontSize16] && WavefrontSize < 16) WavefrontSize = 16;
     791        2489 :   if (Bits[AMDGPU::FeatureWavefrontSize32] && WavefrontSize < 32) WavefrontSize = 32;
     792        2489 :   if (Bits[AMDGPU::FeatureWavefrontSize64] && WavefrontSize < 64) WavefrontSize = 64;
     793        2489 :   if (Bits[AMDGPU::FeatureXNACK]) EnableXNACK = true;
     794        2489 :   if (Bits[AMDGPU::HalfRate64Ops]) HalfRate64Ops = true;
     795        2489 : }
     796             : #endif // GET_SUBTARGETINFO_TARGET_DESC
     797             : 
     798             : 
     799             : #ifdef GET_SUBTARGETINFO_HEADER
     800             : #undef GET_SUBTARGETINFO_HEADER
     801             : 
     802             : namespace llvm {
     803             : class DFAPacketizer;
     804        2480 : struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo {
     805             :   explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
     806             : public:
     807             :   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
     808             :   DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
     809             : };
     810             : } // end namespace llvm
     811             : 
     812             : #endif // GET_SUBTARGETINFO_HEADER
     813             : 
     814             : 
     815             : #ifdef GET_SUBTARGETINFO_CTOR
     816             : #undef GET_SUBTARGETINFO_CTOR
     817             : 
     818             : #include "llvm/CodeGen/TargetSchedule.h"
     819             : 
     820             : namespace llvm {
     821             : extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[];
     822             : extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[];
     823             : extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[];
     824             : extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[];
     825             : extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[];
     826             : extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[];
     827             : extern const llvm::InstrStage AMDGPUStages[];
     828             : extern const unsigned AMDGPUOperandCycles[];
     829             : extern const unsigned AMDGPUForwardingPaths[];
     830        2489 : AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
     831             :   : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(AMDGPUFeatureKV, 102), makeArrayRef(AMDGPUSubTypeKV, 49), 
     832             :                         AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
     833        2489 :                         AMDGPUStages, AMDGPUOperandCycles, AMDGPUForwardingPaths) {}
     834             : 
     835      466610 : unsigned AMDGPUGenSubtargetInfo
     836             : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
     837             : 
     838             :   const SIInstrInfo *TII =
     839      466610 :     static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
     840             :   (void)TII;
     841             : 
     842      466610 :   switch (SchedClass) {
     843             :   case 24: // COPY
     844      466610 :     if (SchedModel->getProcessorID() == 2) { // SIQuarterSpeedModel
     845      405684 :       if ((TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32))
     846             :         return 25; // Write32Bit
     847      160399 :       if ((TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32))
     848             :         return 26; // Write64Bit
     849             :       if ((true))
     850             :         return 27; // WriteSALU
     851             :     }
     852       60926 :     if (SchedModel->getProcessorID() == 4) { // SIFullSpeedModel
     853       60926 :       if ((TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32))
     854             :         return 25; // Write32Bit
     855       30828 :       if ((TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32))
     856             :         return 26; // Write64Bit
     857             :       if ((true))
     858             :         return 27; // WriteSALU
     859             :     }
     860             :     break;
     861             :   };
     862           0 :   report_fatal_error("Expected a variant SchedClass");
     863             : } // AMDGPUGenSubtargetInfo::resolveSchedClass
     864             : } // end namespace llvm
     865             : 
     866             : #endif // GET_SUBTARGETINFO_CTOR
     867             : 

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