LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenSubtargetInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 114 115 99.1 %
Date: 2017-09-14 15:23:50 Functions: 4 6 66.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Subtarget Enumeration Source Fragment                                      *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_SUBTARGETINFO_ENUM
      11             : #undef GET_SUBTARGETINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : namespace AMDGPU {
      15             : enum {
      16             :   Feature16BitInsts = 0,
      17             :   FeatureAddNoCarryInsts = 1,
      18             :   FeatureApertureRegs = 2,
      19             :   FeatureAutoWaitcntBeforeBarrier = 3,
      20             :   FeatureCFALUBug = 4,
      21             :   FeatureCIInsts = 5,
      22             :   FeatureCaymanISA = 6,
      23             :   FeatureDPP = 7,
      24             :   FeatureDX10Clamp = 8,
      25             :   FeatureDebuggerEmitPrologue = 9,
      26             :   FeatureDebuggerInsertNops = 10,
      27             :   FeatureDebuggerReserveRegs = 11,
      28             :   FeatureDisable = 12,
      29             :   FeatureDumpCode = 13,
      30             :   FeatureDumpCodeLower = 14,
      31             :   FeatureEnableLoadStoreOpt = 15,
      32             :   FeatureEnableSIScheduler = 16,
      33             :   FeatureEnableUnsafeDSOffsetFolding = 17,
      34             :   FeatureEvergreen = 18,
      35             :   FeatureFP16Denormals = 19,
      36             :   FeatureFP32Denormals = 20,
      37             :   FeatureFP64 = 21,
      38             :   FeatureFP64Denormals = 22,
      39             :   FeatureFP64FP16Denormals = 23,
      40             :   FeatureFPExceptions = 24,
      41             :   FeatureFastFMAF32 = 25,
      42             :   FeatureFetchLimit8 = 26,
      43             :   FeatureFetchLimit16 = 27,
      44             :   FeatureFlatAddressSpace = 28,
      45             :   FeatureFlatForGlobal = 29,
      46             :   FeatureFlatGlobalInsts = 30,
      47             :   FeatureFlatInstOffsets = 31,
      48             :   FeatureFlatScratchInsts = 32,
      49             :   FeatureGCN = 33,
      50             :   FeatureGCN3Encoding = 34,
      51             :   FeatureGFX9 = 35,
      52             :   FeatureGFX9Insts = 36,
      53             :   FeatureISAVersion6_0_0 = 37,
      54             :   FeatureISAVersion6_0_1 = 38,
      55             :   FeatureISAVersion7_0_0 = 39,
      56             :   FeatureISAVersion7_0_1 = 40,
      57             :   FeatureISAVersion7_0_2 = 41,
      58             :   FeatureISAVersion7_0_3 = 42,
      59             :   FeatureISAVersion8_0_0 = 43,
      60             :   FeatureISAVersion8_0_1 = 44,
      61             :   FeatureISAVersion8_0_2 = 45,
      62             :   FeatureISAVersion8_0_3 = 46,
      63             :   FeatureISAVersion8_0_4 = 47,
      64             :   FeatureISAVersion8_1_0 = 48,
      65             :   FeatureISAVersion9_0_0 = 49,
      66             :   FeatureISAVersion9_0_1 = 50,
      67             :   FeatureISAVersion9_0_2 = 51,
      68             :   FeatureISAVersion9_0_3 = 52,
      69             :   FeatureIntClamp = 53,
      70             :   FeatureInv2PiInlineImm = 54,
      71             :   FeatureLDSBankCount16 = 55,
      72             :   FeatureLDSBankCount32 = 56,
      73             :   FeatureLocalMemorySize0 = 57,
      74             :   FeatureLocalMemorySize32768 = 58,
      75             :   FeatureLocalMemorySize65536 = 59,
      76             :   FeatureMaxPrivateElementSize4 = 60,
      77             :   FeatureMaxPrivateElementSize8 = 61,
      78             :   FeatureMaxPrivateElementSize16 = 62,
      79             :   FeatureMovrel = 63,
      80             :   FeatureNorthernIslands = 64,
      81             :   FeaturePromoteAlloca = 65,
      82             :   FeatureR600 = 66,
      83             :   FeatureR600ALUInst = 67,
      84             :   FeatureR700 = 68,
      85             :   FeatureSDWA = 69,
      86             :   FeatureSDWAMac = 70,
      87             :   FeatureSDWAOmod = 71,
      88             :   FeatureSDWAOutModsVOPC = 72,
      89             :   FeatureSDWAScalar = 73,
      90             :   FeatureSDWASdst = 74,
      91             :   FeatureSGPRInitBug = 75,
      92             :   FeatureSMemRealTime = 76,
      93             :   FeatureScalarStores = 77,
      94             :   FeatureSeaIslands = 78,
      95             :   FeatureSouthernIslands = 79,
      96             :   FeatureTrapHandler = 80,
      97             :   FeatureUnalignedBufferAccess = 81,
      98             :   FeatureUnalignedScratchAccess = 82,
      99             :   FeatureVGPRIndexMode = 83,
     100             :   FeatureVGPRSpilling = 84,
     101             :   FeatureVOP3P = 85,
     102             :   FeatureVertexCache = 86,
     103             :   FeatureVolcanicIslands = 87,
     104             :   FeatureWavefrontSize16 = 88,
     105             :   FeatureWavefrontSize32 = 89,
     106             :   FeatureWavefrontSize64 = 90,
     107             :   FeatureXNACK = 91,
     108             :   HalfRate64Ops = 92
     109             : };
     110             : } // end namespace AMDGPU
     111             : } // end namespace llvm
     112             : 
     113             : #endif // GET_SUBTARGETINFO_ENUM
     114             : 
     115             : 
     116             : #ifdef GET_SUBTARGETINFO_MC_DESC
     117             : #undef GET_SUBTARGETINFO_MC_DESC
     118             : 
     119             : namespace llvm {
     120             : // Sorted (by key) array of values for CPU features.
     121             : extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[] = {
     122             :   { "16-bit-insts", "Has i16/f16 instructions", { AMDGPU::Feature16BitInsts }, { } },
     123             :   { "DumpCode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCode }, { } },
     124             :   { "EVERGREEN", "EVERGREEN GPU generation", { AMDGPU::FeatureEvergreen }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureLocalMemorySize32768 } },
     125             :   { "GFX9", "GFX9 GPU generation", { AMDGPU::FeatureGFX9 }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureApertureRegs, AMDGPU::FeatureGFX9Insts, AMDGPU::FeatureVOP3P, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOmod, AMDGPU::FeatureSDWAScalar, AMDGPU::FeatureSDWASdst, AMDGPU::FeatureFlatInstOffsets, AMDGPU::FeatureFlatGlobalInsts, AMDGPU::FeatureFlatScratchInsts, AMDGPU::FeatureAddNoCarryInsts } },
     126             :   { "HasVertexCache", "Specify use of dedicated vertex cache", { AMDGPU::FeatureVertexCache }, { } },
     127             :   { "NORTHERN_ISLANDS", "NORTHERN_ISLANDS GPU generation", { AMDGPU::FeatureNorthernIslands }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureLocalMemorySize32768 } },
     128             :   { "R600", "R600 GPU generation", { AMDGPU::FeatureR600 }, { AMDGPU::FeatureR600ALUInst, AMDGPU::FeatureFetchLimit8, AMDGPU::FeatureLocalMemorySize0 } },
     129             :   { "R600ALUInst", "Older version of ALU instructions encoding", { AMDGPU::FeatureR600ALUInst }, { } },
     130             :   { "R700", "R700 GPU generation", { AMDGPU::FeatureR700 }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureLocalMemorySize0 } },
     131             :   { "SEA_ISLANDS", "SEA_ISLANDS GPU generation", { AMDGPU::FeatureSeaIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureCIInsts, AMDGPU::FeatureMovrel } },
     132             :   { "SOUTHERN_ISLANDS", "SOUTHERN_ISLANDS GPU generation", { AMDGPU::FeatureSouthernIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize32768, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureMovrel } },
     133             :   { "VOLCANIC_ISLANDS", "VOLCANIC_ISLANDS GPU generation", { AMDGPU::FeatureVolcanicIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureMovrel, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOutModsVOPC, AMDGPU::FeatureSDWAMac, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp } },
     134             :   { "add-no-carry-insts", "Have VALU add/sub instructions without carry out", { AMDGPU::FeatureAddNoCarryInsts }, { } },
     135             :   { "amdgpu-debugger-emit-prologue", "Emit debugger prologue", { AMDGPU::FeatureDebuggerEmitPrologue }, { } },
     136             :   { "amdgpu-debugger-insert-nops", "Insert one nop instruction for each high level source statement", { AMDGPU::FeatureDebuggerInsertNops }, { } },
     137             :   { "amdgpu-debugger-reserve-regs", "Reserve registers for debugger usage", { AMDGPU::FeatureDebuggerReserveRegs }, { } },
     138             :   { "aperture-regs", "Has Memory Aperture Base and Size Registers", { AMDGPU::FeatureApertureRegs }, { } },
     139             :   { "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", { AMDGPU::FeatureAutoWaitcntBeforeBarrier }, { } },
     140             :   { "caymanISA", "Use Cayman ISA", { AMDGPU::FeatureCaymanISA }, { } },
     141             :   { "cfalubug", "GPU has CF_ALU bug", { AMDGPU::FeatureCFALUBug }, { } },
     142             :   { "ci-insts", "Additional intstructions for CI+", { AMDGPU::FeatureCIInsts }, { } },
     143             :   { "dpp", "Support DPP (Data Parallel Primitives) extension", { AMDGPU::FeatureDPP }, { } },
     144             :   { "dumpcode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCodeLower }, { } },
     145             :   { "dx10-clamp", "clamp modifier clamps NaNs to 0.0", { AMDGPU::FeatureDX10Clamp }, { } },
     146             :   { "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", { AMDGPU::FeatureFastFMAF32 }, { } },
     147             :   { "fetch16", "Limit the maximum number of fetches in a clause to 16", { AMDGPU::FeatureFetchLimit16 }, { } },
     148             :   { "fetch8", "Limit the maximum number of fetches in a clause to 8", { AMDGPU::FeatureFetchLimit8 }, { } },
     149             :   { "flat-address-space", "Support flat address space", { AMDGPU::FeatureFlatAddressSpace }, { } },
     150             :   { "flat-for-global", "Force to generate flat instruction for global", { AMDGPU::FeatureFlatForGlobal }, { } },
     151             :   { "flat-global-insts", "Have global_* flat memory instructions", { AMDGPU::FeatureFlatGlobalInsts }, { } },
     152             :   { "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", { AMDGPU::FeatureFlatInstOffsets }, { } },
     153             :   { "flat-scratch-insts", "Have scratch_* flat memory instructions", { AMDGPU::FeatureFlatScratchInsts }, { } },
     154             :   { "fp-exceptions", "Enable floating point exceptions", { AMDGPU::FeatureFPExceptions }, { } },
     155             :   { "fp16-denormals", "Enable half precision denormal handling", { AMDGPU::FeatureFP16Denormals }, { AMDGPU::FeatureFP64FP16Denormals } },
     156             :   { "fp32-denormals", "Enable single precision denormal handling", { AMDGPU::FeatureFP32Denormals }, { } },
     157             :   { "fp64", "Enable double precision operations", { AMDGPU::FeatureFP64 }, { } },
     158             :   { "fp64-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64Denormals }, { AMDGPU::FeatureFP64, AMDGPU::FeatureFP64FP16Denormals } },
     159             :   { "fp64-fp16-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64FP16Denormals }, { AMDGPU::FeatureFP64 } },
     160             :   { "gcn", "GCN or newer GPU", { AMDGPU::FeatureGCN }, { } },
     161             :   { "gcn3-encoding", "Encoding format for VI", { AMDGPU::FeatureGCN3Encoding }, { } },
     162             :   { "gfx9-insts", "Additional intstructions for GFX9+", { AMDGPU::FeatureGFX9Insts }, { } },
     163             :   { "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", { AMDGPU::HalfRate64Ops }, { } },
     164             :   { "int-clamp-insts", "Support clamp for integer destination", { AMDGPU::FeatureIntClamp }, { } },
     165             :   { "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", { AMDGPU::FeatureInv2PiInlineImm }, { } },
     166             :   { "isaver6.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion6_0_0 }, { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32 } },
     167             :   { "isaver6.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion6_0_1 }, { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32 } },
     168             :   { "isaver7.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_0 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32 } },
     169             :   { "isaver7.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_1 }, { AMDGPU::FeatureSeaIslands, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFastFMAF32 } },
     170             :   { "isaver7.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_2 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16 } },
     171             :   { "isaver7.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_3 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16 } },
     172             :   { "isaver8.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_0 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureSGPRInitBug } },
     173             :   { "isaver8.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_1 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK } },
     174             :   { "isaver8.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_2 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureSGPRInitBug } },
     175             :   { "isaver8.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_3 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32 } },
     176             :   { "isaver8.0.4", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_4 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32 } },
     177             :   { "isaver8.1.0", "Instruction set version number", { AMDGPU::FeatureISAVersion8_1_0 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureXNACK } },
     178             :   { "isaver9.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_0 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureLDSBankCount32 } },
     179             :   { "isaver9.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_1 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK } },
     180             :   { "isaver9.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_2 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureLDSBankCount32 } },
     181             :   { "isaver9.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_3 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK } },
     182             :   { "ldsbankcount16", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount16 }, { } },
     183             :   { "ldsbankcount32", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount32 }, { } },
     184             :   { "load-store-opt", "Enable SI load/store optimizer pass", { AMDGPU::FeatureEnableLoadStoreOpt }, { } },
     185             :   { "localmemorysize0", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize0 }, { } },
     186             :   { "localmemorysize32768", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize32768 }, { } },
     187             :   { "localmemorysize65536", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize65536 }, { } },
     188             :   { "max-private-element-size-16", "Maximum private access size may be 16", { AMDGPU::FeatureMaxPrivateElementSize16 }, { } },
     189             :   { "max-private-element-size-4", "Maximum private access size may be 4", { AMDGPU::FeatureMaxPrivateElementSize4 }, { } },
     190             :   { "max-private-element-size-8", "Maximum private access size may be 8", { AMDGPU::FeatureMaxPrivateElementSize8 }, { } },
     191             :   { "movrel", "Has v_movrel*_b32 instructions", { AMDGPU::FeatureMovrel }, { } },
     192             :   { "promote-alloca", "Enable promote alloca pass", { AMDGPU::FeaturePromoteAlloca }, { } },
     193             :   { "s-memrealtime", "Has s_memrealtime instruction", { AMDGPU::FeatureSMemRealTime }, { } },
     194             :   { "scalar-stores", "Has store scalar memory instructions", { AMDGPU::FeatureScalarStores }, { } },
     195             :   { "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWA }, { } },
     196             :   { "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAMac }, { } },
     197             :   { "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOmod }, { } },
     198             :   { "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOutModsVOPC }, { } },
     199             :   { "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAScalar }, { } },
     200             :   { "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWASdst }, { } },
     201             :   { "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", { AMDGPU::FeatureSGPRInitBug }, { } },
     202             :   { "si-scheduler", "Enable SI Machine Scheduler", { AMDGPU::FeatureEnableSIScheduler }, { } },
     203             :   { "trap-handler", "Trap handler support", { AMDGPU::FeatureTrapHandler }, { } },
     204             :   { "unaligned-buffer-access", "Support unaligned global loads and stores", { AMDGPU::FeatureUnalignedBufferAccess }, { } },
     205             :   { "unaligned-scratch-access", "Support unaligned scratch loads and stores", { AMDGPU::FeatureUnalignedScratchAccess }, { } },
     206             :   { "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", { AMDGPU::FeatureEnableUnsafeDSOffsetFolding }, { } },
     207             :   { "vgpr-index-mode", "Has VGPR mode register indexing", { AMDGPU::FeatureVGPRIndexMode }, { } },
     208             :   { "vgpr-spilling", "Enable spilling of VGPRs to scratch memory", { AMDGPU::FeatureVGPRSpilling }, { } },
     209             :   { "vop3p", "Has VOP3P packed instructions", { AMDGPU::FeatureVOP3P }, { } },
     210             :   { "wavefrontsize16", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize16 }, { } },
     211             :   { "wavefrontsize32", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize32 }, { } },
     212             :   { "wavefrontsize64", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize64 }, { } },
     213             :   { "xnack", "Enable XNACK support", { AMDGPU::FeatureXNACK }, { } }
     214       72306 : };
     215             : 
     216             : // Sorted (by key) array of values for CPU subtype.
     217             : extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[] = {
     218             :   { "barts", "Select the barts processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureVertexCache, AMDGPU::FeatureCFALUBug }, { } },
     219             :   { "bonaire", "Select the bonaire processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
     220             :   { "caicos", "Select the caicos processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureCFALUBug }, { } },
     221             :   { "carrizo", "Select the carrizo processor", { AMDGPU::FeatureISAVersion8_0_1 }, { } },
     222             :   { "cayman", "Select the cayman processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureFP64, AMDGPU::FeatureCaymanISA }, { } },
     223             :   { "cedar", "Select the cedar processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize32, AMDGPU::FeatureCFALUBug }, { } },
     224             :   { "cypress", "Select the cypress processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureFP64, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
     225             :   { "fiji", "Select the fiji processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     226             :   { "generic", "Select the generic processor", { AMDGPU::FeatureGCN }, { } },
     227             :   { "gfx600", "Select the gfx600 processor", { AMDGPU::FeatureISAVersion6_0_0 }, { } },
     228             :   { "gfx601", "Select the gfx601 processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     229             :   { "gfx700", "Select the gfx700 processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
     230             :   { "gfx701", "Select the gfx701 processor", { AMDGPU::FeatureISAVersion7_0_1 }, { } },
     231             :   { "gfx702", "Select the gfx702 processor", { AMDGPU::FeatureISAVersion7_0_2 }, { } },
     232             :   { "gfx703", "Select the gfx703 processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     233             :   { "gfx800", "Select the gfx800 processor", { AMDGPU::FeatureISAVersion8_0_0 }, { } },
     234             :   { "gfx801", "Select the gfx801 processor", { AMDGPU::FeatureISAVersion8_0_1 }, { } },
     235             :   { "gfx802", "Select the gfx802 processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
     236             :   { "gfx803", "Select the gfx803 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     237             :   { "gfx804", "Select the gfx804 processor", { AMDGPU::FeatureISAVersion8_0_4 }, { } },
     238             :   { "gfx810", "Select the gfx810 processor", { AMDGPU::FeatureISAVersion8_1_0 }, { } },
     239             :   { "gfx900", "Select the gfx900 processor", { AMDGPU::FeatureISAVersion9_0_0 }, { } },
     240             :   { "gfx901", "Select the gfx901 processor", { AMDGPU::FeatureISAVersion9_0_1 }, { } },
     241             :   { "gfx902", "Select the gfx902 processor", { AMDGPU::FeatureISAVersion9_0_2 }, { } },
     242             :   { "gfx903", "Select the gfx903 processor", { AMDGPU::FeatureISAVersion9_0_3 }, { } },
     243             :   { "hainan", "Select the hainan processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     244             :   { "hawaii", "Select the hawaii processor", { AMDGPU::FeatureISAVersion7_0_1 }, { } },
     245             :   { "iceland", "Select the iceland processor", { AMDGPU::FeatureISAVersion8_0_0 }, { } },
     246             :   { "juniper", "Select the juniper processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
     247             :   { "kabini", "Select the kabini processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     248             :   { "kaveri", "Select the kaveri processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
     249             :   { "mullins", "Select the mullins processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     250             :   { "oland", "Select the oland processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     251             :   { "pitcairn", "Select the pitcairn processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     252             :   { "polaris10", "Select the polaris10 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     253             :   { "polaris11", "Select the polaris11 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     254             :   { "r600", "Select the r600 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
     255             :   { "r630", "Select the r630 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize32 }, { } },
     256             :   { "redwood", "Select the redwood processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureCFALUBug }, { } },
     257             :   { "rs880", "Select the rs880 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureWavefrontSize16 }, { } },
     258             :   { "rv670", "Select the rv670 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureFP64, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
     259             :   { "rv710", "Select the rv710 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize32 }, { } },
     260             :   { "rv730", "Select the rv730 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize32 }, { } },
     261             :   { "rv770", "Select the rv770 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureFP64, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
     262             :   { "stoney", "Select the stoney processor", { AMDGPU::FeatureISAVersion8_1_0 }, { } },
     263             :   { "sumo", "Select the sumo processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureCFALUBug }, { } },
     264             :   { "tahiti", "Select the tahiti processor", { AMDGPU::FeatureISAVersion6_0_0 }, { } },
     265             :   { "tonga", "Select the tonga processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
     266             :   { "turks", "Select the turks processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureVertexCache, AMDGPU::FeatureCFALUBug }, { } },
     267             :   { "verde", "Select the verde processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } }
     268       72306 : };
     269             : 
     270             : #ifdef DBGFIELD
     271             : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
     272             : #endif
     273             : #ifndef NDEBUG
     274             : #define DBGFIELD(x) x,
     275             : #else
     276             : #define DBGFIELD(x)
     277             : #endif
     278             : 
     279             : // Functional units for "R600_VLIW5_Itin"
     280             : namespace R600_VLIW5_ItinFU {
     281             :   const unsigned ALU_X = 1 << 0;
     282             :   const unsigned ALU_Y = 1 << 1;
     283             :   const unsigned ALU_Z = 1 << 2;
     284             :   const unsigned ALU_W = 1 << 3;
     285             :   const unsigned TRANS = 1 << 4;
     286             :   const unsigned ALU_NULL = 1 << 5;
     287             : } // end namespace R600_VLIW5_ItinFU
     288             : 
     289             : // Functional units for "R600_VLIW4_Itin"
     290             : namespace R600_VLIW4_ItinFU {
     291             :   const unsigned ALU_X = 1 << 0;
     292             :   const unsigned ALU_Y = 1 << 1;
     293             :   const unsigned ALU_Z = 1 << 2;
     294             :   const unsigned ALU_W = 1 << 3;
     295             :   const unsigned ALU_NULL = 1 << 4;
     296             : } // end namespace R600_VLIW4_ItinFU
     297             : 
     298             : extern const llvm::InstrStage AMDGPUStages[] = {
     299             :   { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
     300             :   { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
     301             :   { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
     302             :   { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
     303             :   { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
     304             :   { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
     305             :   { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
     306             :   { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
     307             :   { 0, 0, 0, llvm::InstrStage::Required } // End stages
     308             : };
     309             : extern const unsigned AMDGPUOperandCycles[] = {
     310             :   0, // No itinerary
     311             :   0 // End operand cycles
     312             : };
     313             : extern const unsigned AMDGPUForwardingPaths[] = {
     314             :  0, // No itinerary
     315             :  0 // End bypass tables
     316             : };
     317             : 
     318             : static const llvm::InstrItinerary R600_VLIW5_Itin[] = {
     319             :   { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
     320             :   { 1, 1, 2, 0, 0 }, // 1 AnyALU
     321             :   { 1, 2, 3, 0, 0 }, // 2 NullALU_Write32Bit
     322             :   { 1, 2, 3, 0, 0 }, // 3 NullALU
     323             :   { 1, 3, 4, 0, 0 }, // 4 VecALU
     324             :   { 1, 2, 3, 0, 0 }, // 5 NullALU_WriteVMEM
     325             :   { 1, 4, 5, 0, 0 }, // 6 TransALU
     326             :   { 1, 2, 3, 0, 0 }, // 7 NullALU_WriteLDS
     327             :   { 1, 2, 3, 0, 0 }, // 8 NullALU_WriteExport
     328             :   { 1, 5, 6, 0, 0 }, // 9 XALU
     329             :   { 1, 2, 3, 0, 0 }, // 10 NullALU_WriteBranch
     330             :   { 1, 2, 3, 0, 0 }, // 11 NullALU_WriteSALU
     331             :   { 1, 2, 3, 0, 0 }, // 12 NullALU_WriteBarrier
     332             :   { 1, 2, 3, 0, 0 }, // 13 NullALU_WriteSMEM
     333             :   { 1, 2, 3, 0, 0 }, // 14 NullALU_Write32Bit_WriteSALU
     334             :   { 1, 2, 3, 0, 0 }, // 15 NullALU_WriteDoubleAdd
     335             :   { 1, 2, 3, 0, 0 }, // 16 NullALU_Write64Bit
     336             :   { 1, 2, 3, 0, 0 }, // 17 NullALU_WriteQuarterRate32
     337             :   { 1, 2, 3, 0, 0 }, // 18 NullALU_WriteFloatFMA
     338             :   { 1, 2, 3, 0, 0 }, // 19 NullALU_WriteDouble
     339             :   { 1, 2, 3, 0, 0 }, // 20 NullALU_WriteFloatFMA_WriteSALU
     340             :   { 1, 2, 3, 0, 0 }, // 21 NullALU_WriteDouble_WriteSALU
     341             :   { 1, 2, 3, 0, 0 }, // 22 NullALU_Write64Bit_Write64Bit
     342             :   { 0, 0, 0, 0, 0 }, // 23 COPY
     343             :   { 0, ~0U, ~0U, ~0U, ~0U } // end marker
     344             : };
     345             : 
     346             : static const llvm::InstrItinerary R600_VLIW4_Itin[] = {
     347             :   { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
     348             :   { 1, 6, 7, 0, 0 }, // 1 AnyALU
     349             :   { 1, 7, 8, 0, 0 }, // 2 NullALU_Write32Bit
     350             :   { 1, 7, 8, 0, 0 }, // 3 NullALU
     351             :   { 1, 6, 7, 0, 0 }, // 4 VecALU
     352             :   { 1, 7, 8, 0, 0 }, // 5 NullALU_WriteVMEM
     353             :   { 1, 7, 8, 0, 0 }, // 6 TransALU
     354             :   { 1, 7, 8, 0, 0 }, // 7 NullALU_WriteLDS
     355             :   { 1, 7, 8, 0, 0 }, // 8 NullALU_WriteExport
     356             :   { 0, 0, 0, 0, 0 }, // 9 XALU
     357             :   { 1, 7, 8, 0, 0 }, // 10 NullALU_WriteBranch
     358             :   { 1, 7, 8, 0, 0 }, // 11 NullALU_WriteSALU
     359             :   { 1, 7, 8, 0, 0 }, // 12 NullALU_WriteBarrier
     360             :   { 1, 7, 8, 0, 0 }, // 13 NullALU_WriteSMEM
     361             :   { 1, 7, 8, 0, 0 }, // 14 NullALU_Write32Bit_WriteSALU
     362             :   { 1, 7, 8, 0, 0 }, // 15 NullALU_WriteDoubleAdd
     363             :   { 1, 7, 8, 0, 0 }, // 16 NullALU_Write64Bit
     364             :   { 1, 7, 8, 0, 0 }, // 17 NullALU_WriteQuarterRate32
     365             :   { 1, 7, 8, 0, 0 }, // 18 NullALU_WriteFloatFMA
     366             :   { 1, 7, 8, 0, 0 }, // 19 NullALU_WriteDouble
     367             :   { 1, 7, 8, 0, 0 }, // 20 NullALU_WriteFloatFMA_WriteSALU
     368             :   { 1, 7, 8, 0, 0 }, // 21 NullALU_WriteDouble_WriteSALU
     369             :   { 1, 7, 8, 0, 0 }, // 22 NullALU_Write64Bit_Write64Bit
     370             :   { 0, 0, 0, 0, 0 }, // 23 COPY
     371             :   { 0, ~0U, ~0U, ~0U, ~0U } // end marker
     372             : };
     373             : 
     374             : // ===============================================================
     375             : // Data tables for the new per-operand machine model.
     376             : 
     377             : // {ProcResourceIdx, Cycles}
     378             : extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = {
     379             :   { 0,  0}, // Invalid
     380             :   { 5,  1}, // #1
     381             :   { 6,  1}, // #2
     382             :   { 3,  1}, // #3
     383             :   { 2,  1}, // #4
     384             :   { 1,  1}, // #5
     385             :   { 4,  1}, // #6
     386             :   { 4,  1}, // #7
     387             :   { 5,  1}, // #8
     388             :   { 5,  2} // #9
     389             : }; // AMDGPUWriteProcResTable
     390             : 
     391             : // {Cycles, WriteResourceID}
     392             : extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = {
     393             :   { 0,  0}, // Invalid
     394             :   { 1,  0}, // #1 Write32Bit_WriteSALU_WriteFloatFMA
     395             :   {80,  0}, // #2 WriteVMEM
     396             :   { 5,  0}, // #3 WriteLDS_WriteSMEM
     397             :   { 4,  0}, // #4 WriteExport_WriteQuarterRate32_WriteDouble
     398             :   { 8,  0}, // #5 WriteBranch_WriteDoubleAdd
     399             :   {500,  0}, // #6 WriteBarrier
     400             :   { 1,  0}, // #7 Write32Bit_WriteFloatFMA
     401             :   { 1,  0}, // #8 WriteSALU
     402             :   { 2,  0}, // #9 Write64Bit_WriteDoubleAdd
     403             :   {16,  0}, // #10 WriteFloatFMA_WriteDouble
     404             :   {16,  0}, // #11 WriteFloatFMA_WriteDouble
     405             :   { 1,  0}, // #12 WriteSALU
     406             :   { 2,  0}, // #13 Write64Bit
     407             :   { 2,  0}, // #14 Write64Bit
     408             :   { 4,  0}, // #15 WriteDouble
     409             :   { 1,  0} // #16 WriteSALU
     410             : }; // AMDGPUWriteLatencyTable
     411             : 
     412             : // {UseIdx, WriteResourceID, Cycles}
     413             : extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = {
     414             :   {0,  0,  0}, // Invalid
     415             : }; // AMDGPUReadAdvanceTable
     416             : 
     417             : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
     418             : static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = {
     419             :   {DBGFIELD("InvalidSchedClass")  65535, false, false,  0, 0,  0, 0,  0, 0},
     420             :   {DBGFIELD("AnyALU")             0, false, false,  0, 0,  0, 0,  0, 0}, // #1
     421             :   {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #2
     422             :   {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #3
     423             :   {DBGFIELD("VecALU")             0, false, false,  0, 0,  0, 0,  0, 0}, // #4
     424             :   {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #5
     425             :   {DBGFIELD("TransALU")           0, false, false,  0, 0,  0, 0,  0, 0}, // #6
     426             :   {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #7
     427             :   {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #8
     428             :   {DBGFIELD("XALU")               0, false, false,  0, 0,  0, 0,  0, 0}, // #9
     429             :   {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #10
     430             :   {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #11
     431             :   {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1,  6, 1,  0, 0}, // #12
     432             :   {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #13
     433             :   {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  7, 2,  0, 0}, // #14
     434             :   {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  5, 1,  0, 0}, // #15
     435             :   {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  9, 1,  0, 0}, // #16
     436             :   {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #17
     437             :   {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1, 10, 1,  0, 0}, // #18
     438             :   {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1, 10, 1,  0, 0}, // #19
     439             :   {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2, 11, 2,  0, 0}, // #20
     440             :   {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 11, 2,  0, 0}, // #21
     441             :   {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 13, 2,  0, 0}, // #22
     442             :   {DBGFIELD("COPY")               65534, false, false,  0, 0,  0, 0,  0, 0}, // #23
     443             :   {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #24
     444             :   {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  9, 1,  0, 0}, // #25
     445             :   {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0} // #26
     446             : }; // SIQuarterSpeedModelSchedClasses
     447             : 
     448             : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
     449             : static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = {
     450             :   {DBGFIELD("InvalidSchedClass")  65535, false, false,  0, 0,  0, 0,  0, 0},
     451             :   {DBGFIELD("AnyALU")             0, false, false,  0, 0,  0, 0,  0, 0}, // #1
     452             :   {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #2
     453             :   {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #3
     454             :   {DBGFIELD("VecALU")             0, false, false,  0, 0,  0, 0,  0, 0}, // #4
     455             :   {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #5
     456             :   {DBGFIELD("TransALU")           0, false, false,  0, 0,  0, 0,  0, 0}, // #6
     457             :   {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #7
     458             :   {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #8
     459             :   {DBGFIELD("XALU")               0, false, false,  0, 0,  0, 0,  0, 0}, // #9
     460             :   {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #10
     461             :   {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #11
     462             :   {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1,  6, 1,  0, 0}, // #12
     463             :   {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #13
     464             :   {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  7, 2,  0, 0}, // #14
     465             :   {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  9, 1,  0, 0}, // #15
     466             :   {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  9, 1,  0, 0}, // #16
     467             :   {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #17
     468             :   {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1,  1, 1,  0, 0}, // #18
     469             :   {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1,  4, 1,  0, 0}, // #19
     470             :   {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2,  7, 2,  0, 0}, // #20
     471             :   {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 15, 2,  0, 0}, // #21
     472             :   {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 13, 2,  0, 0}, // #22
     473             :   {DBGFIELD("COPY")               65534, false, false,  0, 0,  0, 0,  0, 0}, // #23
     474             :   {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #24
     475             :   {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  9, 1,  0, 0}, // #25
     476             :   {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0} // #26
     477             : }; // SIFullSpeedModelSchedClasses
     478             : 
     479             : static const llvm::MCSchedModel NoSchedModel = {
     480             :   MCSchedModel::DefaultIssueWidth,
     481             :   MCSchedModel::DefaultMicroOpBufferSize,
     482             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     483             :   MCSchedModel::DefaultLoadLatency,
     484             :   MCSchedModel::DefaultHighLatency,
     485             :   MCSchedModel::DefaultMispredictPenalty,
     486             :   false, // PostRAScheduler
     487             :   false, // CompleteModel
     488             :   0, // Processor ID
     489             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     490             :   nullptr}; // No Itinerary
     491             : 
     492             : static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
     493             :   MCSchedModel::DefaultIssueWidth,
     494             :   MCSchedModel::DefaultMicroOpBufferSize,
     495             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     496             :   MCSchedModel::DefaultLoadLatency,
     497             :   MCSchedModel::DefaultHighLatency,
     498             :   MCSchedModel::DefaultMispredictPenalty,
     499             :   false, // PostRAScheduler
     500             :   false, // CompleteModel
     501             :   1, // Processor ID
     502             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     503             :   R600_VLIW5_Itin};
     504             : 
     505             : // {Name, NumUnits, SuperIdx, IsBuffered}
     506             : static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = {
     507             :   {DBGFIELD("InvalidUnit")     0, 0, 0},
     508             :   {DBGFIELD("HWBranch")        1, 0, 1}, // #1
     509             :   {DBGFIELD("HWExport")        1, 0, 7}, // #2
     510             :   {DBGFIELD("HWLGKM")          1, 0, 31}, // #3
     511             :   {DBGFIELD("HWSALU")          1, 0, 1}, // #4
     512             :   {DBGFIELD("HWVALU")          1, 0, 1}, // #5
     513             :   {DBGFIELD("HWVMEM")          1, 0, 15}  // #6
     514             : };
     515             : 
     516             : static const llvm::MCSchedModel SIQuarterSpeedModel = {
     517             :   1, // IssueWidth
     518             :   1, // MicroOpBufferSize
     519             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     520             :   MCSchedModel::DefaultLoadLatency,
     521             :   MCSchedModel::DefaultHighLatency,
     522             :   20, // MispredictPenalty
     523             :   true, // PostRAScheduler
     524             :   true, // CompleteModel
     525             :   2, // Processor ID
     526             :   SIQuarterSpeedModelProcResources,
     527             :   SIQuarterSpeedModelSchedClasses,
     528             :   7,
     529             :   27,
     530             :   nullptr}; // No Itinerary
     531             : 
     532             : static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
     533             :   MCSchedModel::DefaultIssueWidth,
     534             :   MCSchedModel::DefaultMicroOpBufferSize,
     535             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     536             :   MCSchedModel::DefaultLoadLatency,
     537             :   MCSchedModel::DefaultHighLatency,
     538             :   MCSchedModel::DefaultMispredictPenalty,
     539             :   false, // PostRAScheduler
     540             :   false, // CompleteModel
     541             :   3, // Processor ID
     542             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     543             :   R600_VLIW4_Itin};
     544             : 
     545             : // {Name, NumUnits, SuperIdx, IsBuffered}
     546             : static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = {
     547             :   {DBGFIELD("InvalidUnit")     0, 0, 0},
     548             :   {DBGFIELD("HWBranch")        1, 0, 1}, // #1
     549             :   {DBGFIELD("HWExport")        1, 0, 7}, // #2
     550             :   {DBGFIELD("HWLGKM")          1, 0, 31}, // #3
     551             :   {DBGFIELD("HWSALU")          1, 0, 1}, // #4
     552             :   {DBGFIELD("HWVALU")          1, 0, 1}, // #5
     553             :   {DBGFIELD("HWVMEM")          1, 0, 15}  // #6
     554             : };
     555             : 
     556             : static const llvm::MCSchedModel SIFullSpeedModel = {
     557             :   1, // IssueWidth
     558             :   1, // MicroOpBufferSize
     559             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     560             :   MCSchedModel::DefaultLoadLatency,
     561             :   MCSchedModel::DefaultHighLatency,
     562             :   20, // MispredictPenalty
     563             :   true, // PostRAScheduler
     564             :   true, // CompleteModel
     565             :   4, // Processor ID
     566             :   SIFullSpeedModelProcResources,
     567             :   SIFullSpeedModelSchedClasses,
     568             :   7,
     569             :   27,
     570             :   nullptr}; // No Itinerary
     571             : 
     572             : // Sorted (by key) array of itineraries for CPU subtype.
     573             : extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[] = {
     574             :   { "barts", (const void *)&R600_VLIW5_ItinModel },
     575             :   { "bonaire", (const void *)&SIQuarterSpeedModel },
     576             :   { "caicos", (const void *)&R600_VLIW5_ItinModel },
     577             :   { "carrizo", (const void *)&SIQuarterSpeedModel },
     578             :   { "cayman", (const void *)&R600_VLIW4_ItinModel },
     579             :   { "cedar", (const void *)&R600_VLIW5_ItinModel },
     580             :   { "cypress", (const void *)&R600_VLIW5_ItinModel },
     581             :   { "fiji", (const void *)&SIQuarterSpeedModel },
     582             :   { "generic", (const void *)&NoSchedModel },
     583             :   { "gfx600", (const void *)&SIFullSpeedModel },
     584             :   { "gfx601", (const void *)&SIQuarterSpeedModel },
     585             :   { "gfx700", (const void *)&SIQuarterSpeedModel },
     586             :   { "gfx701", (const void *)&SIFullSpeedModel },
     587             :   { "gfx702", (const void *)&SIQuarterSpeedModel },
     588             :   { "gfx703", (const void *)&SIQuarterSpeedModel },
     589             :   { "gfx800", (const void *)&SIQuarterSpeedModel },
     590             :   { "gfx801", (const void *)&SIQuarterSpeedModel },
     591             :   { "gfx802", (const void *)&SIQuarterSpeedModel },
     592             :   { "gfx803", (const void *)&SIQuarterSpeedModel },
     593             :   { "gfx804", (const void *)&SIQuarterSpeedModel },
     594             :   { "gfx810", (const void *)&SIQuarterSpeedModel },
     595             :   { "gfx900", (const void *)&SIQuarterSpeedModel },
     596             :   { "gfx901", (const void *)&SIQuarterSpeedModel },
     597             :   { "gfx902", (const void *)&SIQuarterSpeedModel },
     598             :   { "gfx903", (const void *)&SIQuarterSpeedModel },
     599             :   { "hainan", (const void *)&SIQuarterSpeedModel },
     600             :   { "hawaii", (const void *)&SIFullSpeedModel },
     601             :   { "iceland", (const void *)&SIQuarterSpeedModel },
     602             :   { "juniper", (const void *)&R600_VLIW5_ItinModel },
     603             :   { "kabini", (const void *)&SIQuarterSpeedModel },
     604             :   { "kaveri", (const void *)&SIQuarterSpeedModel },
     605             :   { "mullins", (const void *)&SIQuarterSpeedModel },
     606             :   { "oland", (const void *)&SIQuarterSpeedModel },
     607             :   { "pitcairn", (const void *)&SIQuarterSpeedModel },
     608             :   { "polaris10", (const void *)&SIQuarterSpeedModel },
     609             :   { "polaris11", (const void *)&SIQuarterSpeedModel },
     610             :   { "r600", (const void *)&R600_VLIW5_ItinModel },
     611             :   { "r630", (const void *)&R600_VLIW5_ItinModel },
     612             :   { "redwood", (const void *)&R600_VLIW5_ItinModel },
     613             :   { "rs880", (const void *)&R600_VLIW5_ItinModel },
     614             :   { "rv670", (const void *)&R600_VLIW5_ItinModel },
     615             :   { "rv710", (const void *)&R600_VLIW5_ItinModel },
     616             :   { "rv730", (const void *)&R600_VLIW5_ItinModel },
     617             :   { "rv770", (const void *)&R600_VLIW5_ItinModel },
     618             :   { "stoney", (const void *)&SIQuarterSpeedModel },
     619             :   { "sumo", (const void *)&R600_VLIW5_ItinModel },
     620             :   { "tahiti", (const void *)&SIFullSpeedModel },
     621             :   { "tonga", (const void *)&SIQuarterSpeedModel },
     622             :   { "turks", (const void *)&R600_VLIW5_ItinModel },
     623             :   { "verde", (const void *)&SIQuarterSpeedModel }
     624             : };
     625             : #undef DBGFIELD
     626        2372 : static inline MCSubtargetInfo *createAMDGPUMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
     627             :   return new MCSubtargetInfo(TT, CPU, FS, AMDGPUFeatureKV, AMDGPUSubTypeKV, 
     628             :                       AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
     629        7116 :                       AMDGPUStages, AMDGPUOperandCycles, AMDGPUForwardingPaths);
     630             : }
     631             : 
     632             : } // end namespace llvm
     633             : 
     634             : #endif // GET_SUBTARGETINFO_MC_DESC
     635             : 
     636             : 
     637             : #ifdef GET_SUBTARGETINFO_TARGET_DESC
     638             : #undef GET_SUBTARGETINFO_TARGET_DESC
     639             : 
     640             : #include "llvm/Support/Debug.h"
     641             : #include "llvm/Support/raw_ostream.h"
     642             : 
     643             : // ParseSubtargetFeatures - Parses features string setting specified
     644             : // subtarget options.
     645        2049 : void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
     646             :   DEBUG(dbgs() << "\nFeatures:" << FS);
     647             :   DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
     648        2049 :   InitMCProcessorInfo(CPU, FS);
     649        2049 :   const FeatureBitset& Bits = getFeatureBits();
     650        4098 :   if (Bits[AMDGPU::Feature16BitInsts]) Has16BitInsts = true;
     651        4098 :   if (Bits[AMDGPU::FeatureAddNoCarryInsts]) AddNoCarryInsts = true;
     652        4098 :   if (Bits[AMDGPU::FeatureApertureRegs]) HasApertureRegs = true;
     653        4098 :   if (Bits[AMDGPU::FeatureAutoWaitcntBeforeBarrier]) AutoWaitcntBeforeBarrier = true;
     654        4098 :   if (Bits[AMDGPU::FeatureCFALUBug]) CFALUBug = true;
     655        4098 :   if (Bits[AMDGPU::FeatureCIInsts]) CIInsts = true;
     656        4098 :   if (Bits[AMDGPU::FeatureCaymanISA]) CaymanISA = true;
     657        4098 :   if (Bits[AMDGPU::FeatureDPP]) HasDPP = true;
     658        4098 :   if (Bits[AMDGPU::FeatureDX10Clamp]) DX10Clamp = true;
     659        4098 :   if (Bits[AMDGPU::FeatureDebuggerEmitPrologue]) DebuggerEmitPrologue = true;
     660        4098 :   if (Bits[AMDGPU::FeatureDebuggerInsertNops]) DebuggerInsertNops = true;
     661        4098 :   if (Bits[AMDGPU::FeatureDebuggerReserveRegs]) DebuggerReserveRegs = true;
     662        4098 :   if (Bits[AMDGPU::FeatureDisable]) FeatureDisable = true;
     663        4098 :   if (Bits[AMDGPU::FeatureDumpCode]) DumpCode = true;
     664        4098 :   if (Bits[AMDGPU::FeatureDumpCodeLower]) DumpCode = true;
     665        4098 :   if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) EnableLoadStoreOpt = true;
     666        4098 :   if (Bits[AMDGPU::FeatureEnableSIScheduler]) EnableSIScheduler = true;
     667        4098 :   if (Bits[AMDGPU::FeatureEnableUnsafeDSOffsetFolding]) EnableUnsafeDSOffsetFolding = true;
     668        4098 :   if (Bits[AMDGPU::FeatureEvergreen] && Gen < AMDGPUSubtarget::EVERGREEN) Gen = AMDGPUSubtarget::EVERGREEN;
     669        4098 :   if (Bits[AMDGPU::FeatureFP16Denormals]) FP64FP16Denormals = true;
     670        4098 :   if (Bits[AMDGPU::FeatureFP32Denormals]) FP32Denormals = true;
     671        4098 :   if (Bits[AMDGPU::FeatureFP64]) FP64 = true;
     672        4098 :   if (Bits[AMDGPU::FeatureFP64Denormals]) FP64FP16Denormals = true;
     673        4098 :   if (Bits[AMDGPU::FeatureFP64FP16Denormals]) FP64FP16Denormals = true;
     674        4098 :   if (Bits[AMDGPU::FeatureFPExceptions]) FPExceptions = true;
     675        4098 :   if (Bits[AMDGPU::FeatureFastFMAF32]) FastFMAF32 = true;
     676        4098 :   if (Bits[AMDGPU::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
     677        4098 :   if (Bits[AMDGPU::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
     678        4098 :   if (Bits[AMDGPU::FeatureFlatAddressSpace]) FlatAddressSpace = true;
     679        4098 :   if (Bits[AMDGPU::FeatureFlatForGlobal]) FlatForGlobal = true;
     680        4098 :   if (Bits[AMDGPU::FeatureFlatGlobalInsts]) FlatGlobalInsts = true;
     681        4098 :   if (Bits[AMDGPU::FeatureFlatInstOffsets]) FlatInstOffsets = true;
     682        4098 :   if (Bits[AMDGPU::FeatureFlatScratchInsts]) FlatScratchInsts = true;
     683        4098 :   if (Bits[AMDGPU::FeatureGCN]) IsGCN = true;
     684        4098 :   if (Bits[AMDGPU::FeatureGCN3Encoding]) GCN3Encoding = true;
     685        4098 :   if (Bits[AMDGPU::FeatureGFX9] && Gen < AMDGPUSubtarget::GFX9) Gen = AMDGPUSubtarget::GFX9;
     686        4098 :   if (Bits[AMDGPU::FeatureGFX9Insts]) GFX9Insts = true;
     687        4098 :   if (Bits[AMDGPU::FeatureISAVersion6_0_0] && IsaVersion < ISAVersion6_0_0) IsaVersion = ISAVersion6_0_0;
     688        4098 :   if (Bits[AMDGPU::FeatureISAVersion6_0_1] && IsaVersion < ISAVersion6_0_1) IsaVersion = ISAVersion6_0_1;
     689        4098 :   if (Bits[AMDGPU::FeatureISAVersion7_0_0] && IsaVersion < ISAVersion7_0_0) IsaVersion = ISAVersion7_0_0;
     690        4098 :   if (Bits[AMDGPU::FeatureISAVersion7_0_1] && IsaVersion < ISAVersion7_0_1) IsaVersion = ISAVersion7_0_1;
     691        4098 :   if (Bits[AMDGPU::FeatureISAVersion7_0_2] && IsaVersion < ISAVersion7_0_2) IsaVersion = ISAVersion7_0_2;
     692        4098 :   if (Bits[AMDGPU::FeatureISAVersion7_0_3] && IsaVersion < ISAVersion7_0_3) IsaVersion = ISAVersion7_0_3;
     693        4098 :   if (Bits[AMDGPU::FeatureISAVersion8_0_0] && IsaVersion < ISAVersion8_0_0) IsaVersion = ISAVersion8_0_0;
     694        4098 :   if (Bits[AMDGPU::FeatureISAVersion8_0_1] && IsaVersion < ISAVersion8_0_1) IsaVersion = ISAVersion8_0_1;
     695        4098 :   if (Bits[AMDGPU::FeatureISAVersion8_0_2] && IsaVersion < ISAVersion8_0_2) IsaVersion = ISAVersion8_0_2;
     696        4098 :   if (Bits[AMDGPU::FeatureISAVersion8_0_3] && IsaVersion < ISAVersion8_0_3) IsaVersion = ISAVersion8_0_3;
     697        4098 :   if (Bits[AMDGPU::FeatureISAVersion8_0_4] && IsaVersion < ISAVersion8_0_4) IsaVersion = ISAVersion8_0_4;
     698        4098 :   if (Bits[AMDGPU::FeatureISAVersion8_1_0] && IsaVersion < ISAVersion8_1_0) IsaVersion = ISAVersion8_1_0;
     699        4098 :   if (Bits[AMDGPU::FeatureISAVersion9_0_0] && IsaVersion < ISAVersion9_0_0) IsaVersion = ISAVersion9_0_0;
     700        4098 :   if (Bits[AMDGPU::FeatureISAVersion9_0_1] && IsaVersion < ISAVersion9_0_1) IsaVersion = ISAVersion9_0_1;
     701        4098 :   if (Bits[AMDGPU::FeatureISAVersion9_0_2] && IsaVersion < ISAVersion9_0_2) IsaVersion = ISAVersion9_0_2;
     702        4098 :   if (Bits[AMDGPU::FeatureISAVersion9_0_3] && IsaVersion < ISAVersion9_0_3) IsaVersion = ISAVersion9_0_3;
     703        4098 :   if (Bits[AMDGPU::FeatureIntClamp]) HasIntClamp = true;
     704        4098 :   if (Bits[AMDGPU::FeatureInv2PiInlineImm]) HasInv2PiInlineImm = true;
     705        4098 :   if (Bits[AMDGPU::FeatureLDSBankCount16] && LDSBankCount < 16) LDSBankCount = 16;
     706        4098 :   if (Bits[AMDGPU::FeatureLDSBankCount32] && LDSBankCount < 32) LDSBankCount = 32;
     707        4098 :   if (Bits[AMDGPU::FeatureLocalMemorySize0] && LocalMemorySize < 0) LocalMemorySize = 0;
     708        4098 :   if (Bits[AMDGPU::FeatureLocalMemorySize32768] && LocalMemorySize < 32768) LocalMemorySize = 32768;
     709        4098 :   if (Bits[AMDGPU::FeatureLocalMemorySize65536] && LocalMemorySize < 65536) LocalMemorySize = 65536;
     710        4098 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize4] && MaxPrivateElementSize < 4) MaxPrivateElementSize = 4;
     711        4098 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize8] && MaxPrivateElementSize < 8) MaxPrivateElementSize = 8;
     712        4098 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize16] && MaxPrivateElementSize < 16) MaxPrivateElementSize = 16;
     713        4098 :   if (Bits[AMDGPU::FeatureMovrel]) HasMovrel = true;
     714        4098 :   if (Bits[AMDGPU::FeatureNorthernIslands] && Gen < AMDGPUSubtarget::NORTHERN_ISLANDS) Gen = AMDGPUSubtarget::NORTHERN_ISLANDS;
     715        4098 :   if (Bits[AMDGPU::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
     716        4098 :   if (Bits[AMDGPU::FeatureR600] && Gen < AMDGPUSubtarget::R600) Gen = AMDGPUSubtarget::R600;
     717        4098 :   if (Bits[AMDGPU::FeatureR600ALUInst]) R600ALUInst = false;
     718        4098 :   if (Bits[AMDGPU::FeatureR700] && Gen < AMDGPUSubtarget::R700) Gen = AMDGPUSubtarget::R700;
     719        4098 :   if (Bits[AMDGPU::FeatureSDWA]) HasSDWA = true;
     720        4098 :   if (Bits[AMDGPU::FeatureSDWAMac]) HasSDWAMac = true;
     721        4098 :   if (Bits[AMDGPU::FeatureSDWAOmod]) HasSDWAOmod = true;
     722        4098 :   if (Bits[AMDGPU::FeatureSDWAOutModsVOPC]) HasSDWAOutModsVOPC = true;
     723        4098 :   if (Bits[AMDGPU::FeatureSDWAScalar]) HasSDWAScalar = true;
     724        4098 :   if (Bits[AMDGPU::FeatureSDWASdst]) HasSDWASdst = true;
     725        4098 :   if (Bits[AMDGPU::FeatureSGPRInitBug]) SGPRInitBug = true;
     726        4098 :   if (Bits[AMDGPU::FeatureSMemRealTime]) HasSMemRealTime = true;
     727        4098 :   if (Bits[AMDGPU::FeatureScalarStores]) HasScalarStores = true;
     728        4098 :   if (Bits[AMDGPU::FeatureSeaIslands] && Gen < AMDGPUSubtarget::SEA_ISLANDS) Gen = AMDGPUSubtarget::SEA_ISLANDS;
     729        4098 :   if (Bits[AMDGPU::FeatureSouthernIslands] && Gen < AMDGPUSubtarget::SOUTHERN_ISLANDS) Gen = AMDGPUSubtarget::SOUTHERN_ISLANDS;
     730        4098 :   if (Bits[AMDGPU::FeatureTrapHandler]) TrapHandler = true;
     731        4098 :   if (Bits[AMDGPU::FeatureUnalignedBufferAccess]) UnalignedBufferAccess = true;
     732        4098 :   if (Bits[AMDGPU::FeatureUnalignedScratchAccess]) UnalignedScratchAccess = true;
     733        4098 :   if (Bits[AMDGPU::FeatureVGPRIndexMode]) HasVGPRIndexMode = true;
     734        4098 :   if (Bits[AMDGPU::FeatureVGPRSpilling]) EnableVGPRSpilling = true;
     735        4098 :   if (Bits[AMDGPU::FeatureVOP3P]) HasVOP3PInsts = true;
     736        4098 :   if (Bits[AMDGPU::FeatureVertexCache]) HasVertexCache = true;
     737        4098 :   if (Bits[AMDGPU::FeatureVolcanicIslands] && Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS) Gen = AMDGPUSubtarget::VOLCANIC_ISLANDS;
     738        4098 :   if (Bits[AMDGPU::FeatureWavefrontSize16] && WavefrontSize < 16) WavefrontSize = 16;
     739        4098 :   if (Bits[AMDGPU::FeatureWavefrontSize32] && WavefrontSize < 32) WavefrontSize = 32;
     740        4098 :   if (Bits[AMDGPU::FeatureWavefrontSize64] && WavefrontSize < 64) WavefrontSize = 64;
     741        4098 :   if (Bits[AMDGPU::FeatureXNACK]) EnableXNACK = true;
     742        4098 :   if (Bits[AMDGPU::HalfRate64Ops]) HalfRate64Ops = true;
     743        2049 : }
     744             : #endif // GET_SUBTARGETINFO_TARGET_DESC
     745             : 
     746             : 
     747             : #ifdef GET_SUBTARGETINFO_HEADER
     748             : #undef GET_SUBTARGETINFO_HEADER
     749             : 
     750             : namespace llvm {
     751             : class DFAPacketizer;
     752        2040 : struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo {
     753             :   explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
     754             : public:
     755             :   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
     756             :   DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
     757             : };
     758             : } // end namespace llvm
     759             : 
     760             : #endif // GET_SUBTARGETINFO_HEADER
     761             : 
     762             : 
     763             : #ifdef GET_SUBTARGETINFO_CTOR
     764             : #undef GET_SUBTARGETINFO_CTOR
     765             : 
     766             : #include "llvm/CodeGen/TargetSchedule.h"
     767             : 
     768             : namespace llvm {
     769             : extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[];
     770             : extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[];
     771             : extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[];
     772             : extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[];
     773             : extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[];
     774             : extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[];
     775             : extern const llvm::InstrStage AMDGPUStages[];
     776             : extern const unsigned AMDGPUOperandCycles[];
     777             : extern const unsigned AMDGPUForwardingPaths[];
     778        2049 : AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
     779             :   : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(AMDGPUFeatureKV, 92), makeArrayRef(AMDGPUSubTypeKV, 50), 
     780             :                         AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
     781        6147 :                         AMDGPUStages, AMDGPUOperandCycles, AMDGPUForwardingPaths) {}
     782             : 
     783      376471 : unsigned AMDGPUGenSubtargetInfo
     784             : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
     785             : 
     786             :   const SIInstrInfo *TII =
     787      376471 :     static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
     788             :   (void)TII;
     789             : 
     790      376471 :   switch (SchedClass) {
     791      376471 :   case 23: // COPY
     792      376471 :     if (SchedModel->getProcessorID() == 2) { // SIQuarterSpeedModel
     793      527656 :       if ((TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32))
     794             :         return 24; // Write32Bit
     795      126164 :       if ((TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32))
     796             :         return 25; // Write64Bit
     797             :       if ((true))
     798             :         return 26; // WriteSALU
     799             :     }
     800       51356 :     if (SchedModel->getProcessorID() == 4) { // SIFullSpeedModel
     801       75604 :       if ((TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32))
     802             :         return 24; // Write32Bit
     803       28692 :       if ((TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32))
     804             :         return 25; // Write64Bit
     805             :       if ((true))
     806             :         return 26; // WriteSALU
     807             :     }
     808             :     break;
     809             :   };
     810           0 :   report_fatal_error("Expected a variant SchedClass");
     811             : } // AMDGPUGenSubtargetInfo::resolveSchedClass
     812             : } // end namespace llvm
     813             : 
     814             : #endif // GET_SUBTARGETINFO_CTOR
     815             : 

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