LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenSubtargetInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 116 123 94.3 %
Date: 2018-10-17 09:37:48 Functions: 4 7 57.1 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Subtarget Enumeration Source Fragment                                      *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_SUBTARGETINFO_ENUM
      11             : #undef GET_SUBTARGETINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : namespace AMDGPU {
      15             : enum {
      16             :   Feature16BitInsts = 0,
      17             :   FeatureAddNoCarryInsts = 1,
      18             :   FeatureApertureRegs = 2,
      19             :   FeatureAutoWaitcntBeforeBarrier = 3,
      20             :   FeatureCIInsts = 4,
      21             :   FeatureCodeObjectV3 = 5,
      22             :   FeatureD16PreservesUnusedBits = 6,
      23             :   FeatureDLInsts = 7,
      24             :   FeatureDPP = 8,
      25             :   FeatureDX10Clamp = 9,
      26             :   FeatureDebuggerEmitPrologue = 10,
      27             :   FeatureDebuggerInsertNops = 11,
      28             :   FeatureDisable = 12,
      29             :   FeatureDumpCode = 13,
      30             :   FeatureDumpCodeLower = 14,
      31             :   FeatureEnableDS128 = 15,
      32             :   FeatureEnableHugePrivateBuffer = 16,
      33             :   FeatureEnableLoadStoreOpt = 17,
      34             :   FeatureEnableSIScheduler = 18,
      35             :   FeatureEnableUnsafeDSOffsetFolding = 19,
      36             :   FeatureFMA = 20,
      37             :   FeatureFP16Denormals = 21,
      38             :   FeatureFP32Denormals = 22,
      39             :   FeatureFP64 = 23,
      40             :   FeatureFP64Denormals = 24,
      41             :   FeatureFP64FP16Denormals = 25,
      42             :   FeatureFPExceptions = 26,
      43             :   FeatureFastFMAF32 = 27,
      44             :   FeatureFlatAddressSpace = 28,
      45             :   FeatureFlatForGlobal = 29,
      46             :   FeatureFlatGlobalInsts = 30,
      47             :   FeatureFlatInstOffsets = 31,
      48             :   FeatureFlatScratchInsts = 32,
      49             :   FeatureFmaMixInsts = 33,
      50             :   FeatureGCN = 34,
      51             :   FeatureGCN3Encoding = 35,
      52             :   FeatureGFX9 = 36,
      53             :   FeatureGFX9Insts = 37,
      54             :   FeatureISAVersion6_0_0 = 38,
      55             :   FeatureISAVersion6_0_1 = 39,
      56             :   FeatureISAVersion7_0_0 = 40,
      57             :   FeatureISAVersion7_0_1 = 41,
      58             :   FeatureISAVersion7_0_2 = 42,
      59             :   FeatureISAVersion7_0_3 = 43,
      60             :   FeatureISAVersion7_0_4 = 44,
      61             :   FeatureISAVersion8_0_1 = 45,
      62             :   FeatureISAVersion8_0_2 = 46,
      63             :   FeatureISAVersion8_0_3 = 47,
      64             :   FeatureISAVersion8_1_0 = 48,
      65             :   FeatureISAVersion9_0_0 = 49,
      66             :   FeatureISAVersion9_0_2 = 50,
      67             :   FeatureISAVersion9_0_4 = 51,
      68             :   FeatureISAVersion9_0_6 = 52,
      69             :   FeatureIntClamp = 53,
      70             :   FeatureInv2PiInlineImm = 54,
      71             :   FeatureLDSBankCount16 = 55,
      72             :   FeatureLDSBankCount32 = 56,
      73             :   FeatureLocalMemorySize0 = 57,
      74             :   FeatureLocalMemorySize32768 = 58,
      75             :   FeatureLocalMemorySize65536 = 59,
      76             :   FeatureMIMG_R128 = 60,
      77             :   FeatureMadMixInsts = 61,
      78             :   FeatureMaxPrivateElementSize4 = 62,
      79             :   FeatureMaxPrivateElementSize8 = 63,
      80             :   FeatureMaxPrivateElementSize16 = 64,
      81             :   FeatureMovrel = 65,
      82             :   FeaturePromoteAlloca = 66,
      83             :   FeatureR128A16 = 67,
      84             :   FeatureSDWA = 68,
      85             :   FeatureSDWAMac = 69,
      86             :   FeatureSDWAOmod = 70,
      87             :   FeatureSDWAOutModsVOPC = 71,
      88             :   FeatureSDWAScalar = 72,
      89             :   FeatureSDWASdst = 73,
      90             :   FeatureSGPRInitBug = 74,
      91             :   FeatureSMemRealTime = 75,
      92             :   FeatureScalarAtomics = 76,
      93             :   FeatureScalarStores = 77,
      94             :   FeatureSeaIslands = 78,
      95             :   FeatureSouthernIslands = 79,
      96             :   FeatureTrapHandler = 80,
      97             :   FeatureTrigReducedRange = 81,
      98             :   FeatureUnalignedBufferAccess = 82,
      99             :   FeatureUnalignedScratchAccess = 83,
     100             :   FeatureUnpackedD16VMem = 84,
     101             :   FeatureVGPRIndexMode = 85,
     102             :   FeatureVGPRSpilling = 86,
     103             :   FeatureVIInsts = 87,
     104             :   FeatureVOP3P = 88,
     105             :   FeatureVolcanicIslands = 89,
     106             :   FeatureWavefrontSize16 = 90,
     107             :   FeatureWavefrontSize32 = 91,
     108             :   FeatureWavefrontSize64 = 92,
     109             :   FeatureXNACK = 93,
     110             :   HalfRate64Ops = 94,
     111             : };
     112             : } // end namespace AMDGPU
     113             : } // end namespace llvm
     114             : 
     115             : #endif // GET_SUBTARGETINFO_ENUM
     116             : 
     117             : 
     118             : #ifdef GET_SUBTARGETINFO_MC_DESC
     119             : #undef GET_SUBTARGETINFO_MC_DESC
     120             : 
     121             : namespace llvm {
     122             : // Sorted (by key) array of values for CPU features.
     123             : extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[] = {
     124             :   { "16-bit-insts", "Has i16/f16 instructions", { AMDGPU::Feature16BitInsts }, { } },
     125             :   { "DumpCode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCode }, { } },
     126             :   { "GFX9", "GFX9 GPU generation", { AMDGPU::FeatureGFX9 }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::FeatureVIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureApertureRegs, AMDGPU::FeatureGFX9Insts, AMDGPU::FeatureVOP3P, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOmod, AMDGPU::FeatureSDWAScalar, AMDGPU::FeatureSDWASdst, AMDGPU::FeatureFlatInstOffsets, AMDGPU::FeatureFlatGlobalInsts, AMDGPU::FeatureFlatScratchInsts, AMDGPU::FeatureAddNoCarryInsts, AMDGPU::FeatureScalarAtomics, AMDGPU::FeatureR128A16 } },
     127             :   { "SEA_ISLANDS", "SEA_ISLANDS GPU generation", { AMDGPU::FeatureSeaIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureCIInsts, AMDGPU::FeatureMovrel, AMDGPU::FeatureTrigReducedRange } },
     128             :   { "SOUTHERN_ISLANDS", "SOUTHERN_ISLANDS GPU generation", { AMDGPU::FeatureSouthernIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize32768, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureMovrel, AMDGPU::FeatureTrigReducedRange } },
     129             :   { "VOLCANIC_ISLANDS", "VOLCANIC_ISLANDS GPU generation", { AMDGPU::FeatureVolcanicIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::FeatureVIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureMovrel, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOutModsVOPC, AMDGPU::FeatureSDWAMac, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp, AMDGPU::FeatureTrigReducedRange } },
     130             :   { "add-no-carry-insts", "Have VALU add/sub instructions without carry out", { AMDGPU::FeatureAddNoCarryInsts }, { } },
     131             :   { "amdgpu-debugger-emit-prologue", "Emit debugger prologue", { AMDGPU::FeatureDebuggerEmitPrologue }, { } },
     132             :   { "amdgpu-debugger-insert-nops", "Insert one nop instruction for each high level source statement", { AMDGPU::FeatureDebuggerInsertNops }, { } },
     133             :   { "aperture-regs", "Has Memory Aperture Base and Size Registers", { AMDGPU::FeatureApertureRegs }, { } },
     134             :   { "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", { AMDGPU::FeatureAutoWaitcntBeforeBarrier }, { } },
     135             :   { "ci-insts", "Additional instructions for CI+", { AMDGPU::FeatureCIInsts }, { } },
     136             :   { "code-object-v3", "Generate code object version 3", { AMDGPU::FeatureCodeObjectV3 }, { } },
     137             :   { "d16-preserves-unused-bits", "If present, then instructions defined by HasD16LoadStore predicate preserve unused bits. Otherwise instructions defined by HasD16LoadStore predicate zero unused bits.", { AMDGPU::FeatureD16PreservesUnusedBits }, { } },
     138             :   { "dl-insts", "Has deep learning instructions", { AMDGPU::FeatureDLInsts }, { } },
     139             :   { "dpp", "Support DPP (Data Parallel Primitives) extension", { AMDGPU::FeatureDPP }, { } },
     140             :   { "dumpcode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCodeLower }, { } },
     141             :   { "dx10-clamp", "clamp modifier clamps NaNs to 0.0", { AMDGPU::FeatureDX10Clamp }, { } },
     142             :   { "enable-ds128", "Use ds_{read|write}_b128", { AMDGPU::FeatureEnableDS128 }, { } },
     143             :   { "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", { AMDGPU::FeatureFastFMAF32 }, { } },
     144             :   { "flat-address-space", "Support flat address space", { AMDGPU::FeatureFlatAddressSpace }, { } },
     145             :   { "flat-for-global", "Force to generate flat instruction for global", { AMDGPU::FeatureFlatForGlobal }, { } },
     146             :   { "flat-global-insts", "Have global_* flat memory instructions", { AMDGPU::FeatureFlatGlobalInsts }, { } },
     147             :   { "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", { AMDGPU::FeatureFlatInstOffsets }, { } },
     148             :   { "flat-scratch-insts", "Have scratch_* flat memory instructions", { AMDGPU::FeatureFlatScratchInsts }, { } },
     149             :   { "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", { AMDGPU::FeatureFmaMixInsts }, { } },
     150             :   { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", { AMDGPU::FeatureFMA }, { } },
     151             :   { "fp-exceptions", "Enable floating point exceptions", { AMDGPU::FeatureFPExceptions }, { } },
     152             :   { "fp16-denormals", "Enable half precision denormal handling", { AMDGPU::FeatureFP16Denormals }, { AMDGPU::FeatureFP64FP16Denormals } },
     153             :   { "fp32-denormals", "Enable single precision denormal handling", { AMDGPU::FeatureFP32Denormals }, { } },
     154             :   { "fp64", "Enable double precision operations", { AMDGPU::FeatureFP64 }, { } },
     155             :   { "fp64-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64Denormals }, { AMDGPU::FeatureFP64, AMDGPU::FeatureFP64FP16Denormals } },
     156             :   { "fp64-fp16-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64FP16Denormals }, { AMDGPU::FeatureFP64 } },
     157             :   { "gcn", "GCN or newer GPU", { AMDGPU::FeatureGCN }, { } },
     158             :   { "gcn3-encoding", "Encoding format for VI", { AMDGPU::FeatureGCN3Encoding }, { } },
     159             :   { "gfx9-insts", "Additional instructions for GFX9+", { AMDGPU::FeatureGFX9Insts }, { } },
     160             :   { "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", { AMDGPU::HalfRate64Ops }, { } },
     161             :   { "huge-private-buffer", "Enable private/scratch buffer sizes greater than 128 GB", { AMDGPU::FeatureEnableHugePrivateBuffer }, { } },
     162             :   { "int-clamp-insts", "Support clamp for integer destination", { AMDGPU::FeatureIntClamp }, { } },
     163             :   { "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", { AMDGPU::FeatureInv2PiInlineImm }, { } },
     164             :   { "isaver6.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion6_0_0 }, { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32 } },
     165             :   { "isaver6.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion6_0_1 }, { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32 } },
     166             :   { "isaver7.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_0 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32 } },
     167             :   { "isaver7.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_1 }, { AMDGPU::FeatureSeaIslands, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFastFMAF32 } },
     168             :   { "isaver7.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_2 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureFastFMAF32 } },
     169             :   { "isaver7.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_3 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16 } },
     170             :   { "isaver7.0.4", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_4 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32 } },
     171             :   { "isaver8.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_1 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureUnpackedD16VMem } },
     172             :   { "isaver8.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_2 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureSGPRInitBug, AMDGPU::FeatureUnpackedD16VMem } },
     173             :   { "isaver8.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_3 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureUnpackedD16VMem } },
     174             :   { "isaver8.1.0", "Instruction set version number", { AMDGPU::FeatureISAVersion8_1_0 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureXNACK } },
     175             :   { "isaver9.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_0 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureD16PreservesUnusedBits } },
     176             :   { "isaver9.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_2 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureD16PreservesUnusedBits } },
     177             :   { "isaver9.0.4", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_4 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFmaMixInsts, AMDGPU::FeatureD16PreservesUnusedBits } },
     178             :   { "isaver9.0.6", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_6 }, { AMDGPU::FeatureGFX9, AMDGPU::HalfRate64Ops, AMDGPU::FeatureFmaMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureDLInsts } },
     179             :   { "ldsbankcount16", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount16 }, { } },
     180             :   { "ldsbankcount32", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount32 }, { } },
     181             :   { "load-store-opt", "Enable SI load/store optimizer pass", { AMDGPU::FeatureEnableLoadStoreOpt }, { } },
     182             :   { "localmemorysize0", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize0 }, { } },
     183             :   { "localmemorysize32768", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize32768 }, { } },
     184             :   { "localmemorysize65536", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize65536 }, { } },
     185             :   { "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", { AMDGPU::FeatureMadMixInsts }, { } },
     186             :   { "max-private-element-size-16", "Maximum private access size may be 16", { AMDGPU::FeatureMaxPrivateElementSize16 }, { } },
     187             :   { "max-private-element-size-4", "Maximum private access size may be 4", { AMDGPU::FeatureMaxPrivateElementSize4 }, { } },
     188             :   { "max-private-element-size-8", "Maximum private access size may be 8", { AMDGPU::FeatureMaxPrivateElementSize8 }, { } },
     189             :   { "mimg-r128", "Support 128-bit texture resources", { AMDGPU::FeatureMIMG_R128 }, { } },
     190             :   { "movrel", "Has v_movrel*_b32 instructions", { AMDGPU::FeatureMovrel }, { } },
     191             :   { "promote-alloca", "Enable promote alloca pass", { AMDGPU::FeaturePromoteAlloca }, { } },
     192             :   { "r128-a16", "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9", { AMDGPU::FeatureR128A16 }, { } },
     193             :   { "s-memrealtime", "Has s_memrealtime instruction", { AMDGPU::FeatureSMemRealTime }, { } },
     194             :   { "scalar-atomics", "Has atomic scalar memory instructions", { AMDGPU::FeatureScalarAtomics }, { } },
     195             :   { "scalar-stores", "Has store scalar memory instructions", { AMDGPU::FeatureScalarStores }, { } },
     196             :   { "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWA }, { } },
     197             :   { "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAMac }, { } },
     198             :   { "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOmod }, { } },
     199             :   { "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOutModsVOPC }, { } },
     200             :   { "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAScalar }, { } },
     201             :   { "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWASdst }, { } },
     202             :   { "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", { AMDGPU::FeatureSGPRInitBug }, { } },
     203             :   { "si-scheduler", "Enable SI Machine Scheduler", { AMDGPU::FeatureEnableSIScheduler }, { } },
     204             :   { "trap-handler", "Trap handler support", { AMDGPU::FeatureTrapHandler }, { } },
     205             :   { "trig-reduced-range", "Requires use of fract on arguments to trig instructions", { AMDGPU::FeatureTrigReducedRange }, { } },
     206             :   { "unaligned-buffer-access", "Support unaligned global loads and stores", { AMDGPU::FeatureUnalignedBufferAccess }, { } },
     207             :   { "unaligned-scratch-access", "Support unaligned scratch loads and stores", { AMDGPU::FeatureUnalignedScratchAccess }, { } },
     208             :   { "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", { AMDGPU::FeatureUnpackedD16VMem }, { } },
     209             :   { "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", { AMDGPU::FeatureEnableUnsafeDSOffsetFolding }, { } },
     210             :   { "vgpr-index-mode", "Has VGPR mode register indexing", { AMDGPU::FeatureVGPRIndexMode }, { } },
     211             :   { "vgpr-spilling", "Enable spilling of VGPRs to scratch memory", { AMDGPU::FeatureVGPRSpilling }, { } },
     212             :   { "vi-insts", "Additional instructions for VI+", { AMDGPU::FeatureVIInsts }, { } },
     213             :   { "vop3p", "Has VOP3P packed instructions", { AMDGPU::FeatureVOP3P }, { } },
     214             :   { "wavefrontsize16", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize16 }, { } },
     215             :   { "wavefrontsize32", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize32 }, { } },
     216             :   { "wavefrontsize64", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize64 }, { } },
     217             :   { "xnack", "Enable XNACK support", { AMDGPU::FeatureXNACK }, { } },
     218             : };
     219             : 
     220             : // Sorted (by key) array of values for CPU subtype.
     221             : extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[] = {
     222             :   { "bonaire", "Select the bonaire processor", { AMDGPU::FeatureISAVersion7_0_4 }, { } },
     223             :   { "carrizo", "Select the carrizo processor", { AMDGPU::FeatureISAVersion8_0_1 }, { } },
     224             :   { "fiji", "Select the fiji processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     225             :   { "generic", "Select the generic processor", { AMDGPU::FeatureGCN, AMDGPU::FeatureWavefrontSize64 }, { } },
     226             :   { "gfx600", "Select the gfx600 processor", { AMDGPU::FeatureISAVersion6_0_0 }, { } },
     227             :   { "gfx601", "Select the gfx601 processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     228             :   { "gfx700", "Select the gfx700 processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
     229             :   { "gfx701", "Select the gfx701 processor", { AMDGPU::FeatureISAVersion7_0_1 }, { } },
     230             :   { "gfx702", "Select the gfx702 processor", { AMDGPU::FeatureISAVersion7_0_2 }, { } },
     231             :   { "gfx703", "Select the gfx703 processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     232             :   { "gfx704", "Select the gfx704 processor", { AMDGPU::FeatureISAVersion7_0_4 }, { } },
     233             :   { "gfx801", "Select the gfx801 processor", { AMDGPU::FeatureISAVersion8_0_1 }, { } },
     234             :   { "gfx802", "Select the gfx802 processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
     235             :   { "gfx803", "Select the gfx803 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     236             :   { "gfx810", "Select the gfx810 processor", { AMDGPU::FeatureISAVersion8_1_0 }, { } },
     237             :   { "gfx900", "Select the gfx900 processor", { AMDGPU::FeatureISAVersion9_0_0 }, { } },
     238             :   { "gfx902", "Select the gfx902 processor", { AMDGPU::FeatureISAVersion9_0_2 }, { } },
     239             :   { "gfx904", "Select the gfx904 processor", { AMDGPU::FeatureISAVersion9_0_4 }, { } },
     240             :   { "gfx906", "Select the gfx906 processor", { AMDGPU::FeatureISAVersion9_0_6 }, { } },
     241             :   { "hainan", "Select the hainan processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     242             :   { "hawaii", "Select the hawaii processor", { AMDGPU::FeatureISAVersion7_0_1 }, { } },
     243             :   { "iceland", "Select the iceland processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
     244             :   { "kabini", "Select the kabini processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     245             :   { "kaveri", "Select the kaveri processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
     246             :   { "mullins", "Select the mullins processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
     247             :   { "oland", "Select the oland processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     248             :   { "pitcairn", "Select the pitcairn processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     249             :   { "polaris10", "Select the polaris10 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     250             :   { "polaris11", "Select the polaris11 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
     251             :   { "stoney", "Select the stoney processor", { AMDGPU::FeatureISAVersion8_1_0 }, { } },
     252             :   { "tahiti", "Select the tahiti processor", { AMDGPU::FeatureISAVersion6_0_0 }, { } },
     253             :   { "tonga", "Select the tonga processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
     254             :   { "verde", "Select the verde processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
     255             : };
     256             : 
     257             : #ifdef DBGFIELD
     258             : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
     259             : #endif
     260             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     261             : #define DBGFIELD(x) x,
     262             : #else
     263             : #define DBGFIELD(x)
     264             : #endif
     265             : 
     266             : // ===============================================================
     267             : // Data tables for the new per-operand machine model.
     268             : 
     269             : // {ProcResourceIdx, Cycles}
     270             : extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = {
     271             :   { 0,  0}, // Invalid
     272             :   { 5,  1}, // #1
     273             :   { 6,  1}, // #2
     274             :   { 3,  1}, // #3
     275             :   { 2,  1}, // #4
     276             :   { 1,  1}, // #5
     277             :   { 4,  1}, // #6
     278             :   { 4,  1}, // #7
     279             :   { 5,  1}, // #8
     280             :   { 5,  2} // #9
     281             : }; // AMDGPUWriteProcResTable
     282             : 
     283             : // {Cycles, WriteResourceID}
     284             : extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = {
     285             :   { 0,  0}, // Invalid
     286             :   { 1,  0}, // #1 Write32Bit_WriteSALU_WriteFloatFMA
     287             :   {80,  0}, // #2 WriteVMEM
     288             :   { 5,  0}, // #3 WriteLDS_WriteSMEM
     289             :   { 4,  0}, // #4 WriteExport_WriteQuarterRate32_WriteDouble
     290             :   { 8,  0}, // #5 WriteBranch_WriteDoubleAdd
     291             :   { 1,  0}, // #6 Write32Bit_WriteFloatFMA
     292             :   { 1,  0}, // #7 WriteSALU
     293             :   { 2,  0}, // #8 Write64Bit_WriteDoubleAdd
     294             :   {16,  0}, // #9 WriteFloatFMA_WriteDouble
     295             :   {16,  0}, // #10 WriteFloatFMA_WriteDouble
     296             :   { 1,  0}, // #11 WriteSALU
     297             :   { 4,  0}, // #12 WriteQuarterRate32_WriteDouble
     298             :   { 1,  0}, // #13 WriteSALU
     299             :   { 2,  0}, // #14 Write64Bit
     300             :   { 2,  0}, // #15 Write64Bit
     301             :   {500,  0} // #16 WriteBarrier
     302             : }; // AMDGPUWriteLatencyTable
     303             : 
     304             : // {UseIdx, WriteResourceID, Cycles}
     305             : extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = {
     306             :   {0,  0,  0}, // Invalid
     307             : }; // AMDGPUReadAdvanceTable
     308             : 
     309             : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
     310             : static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = {
     311             :   {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
     312             :   {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #1
     313             :   {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #2
     314             :   {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #3
     315             :   {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #4
     316             :   {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #5
     317             :   {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #6
     318             :   {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #7
     319             :   {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #8
     320             :   {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #9
     321             :   {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  5, 1,  0, 0}, // #10
     322             :   {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  8, 1,  0, 0}, // #11
     323             :   {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #12
     324             :   {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1,  9, 1,  0, 0}, // #13
     325             :   {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1,  9, 1,  0, 0}, // #14
     326             :   {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2, 10, 2,  0, 0}, // #15
     327             :   {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 10, 2,  0, 0}, // #16
     328             :   {DBGFIELD("NullALU_WriteQuarterRate32_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #17
     329             :   {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 14, 2,  0, 0}, // #18
     330             :   {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1, 16, 1,  0, 0}, // #19
     331             :   {DBGFIELD("COPY")               16382, false, false,  0, 0,  0, 0,  0, 0}, // #20
     332             :   {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #21
     333             :   {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  8, 1,  0, 0}, // #22
     334             :   {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0}, // #23
     335             : }; // SIQuarterSpeedModelSchedClasses
     336             : 
     337             : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
     338             : static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = {
     339             :   {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
     340             :   {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #1
     341             :   {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #2
     342             :   {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #3
     343             :   {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #4
     344             :   {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #5
     345             :   {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #6
     346             :   {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #7
     347             :   {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #8
     348             :   {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #9
     349             :   {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  8, 1,  0, 0}, // #10
     350             :   {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  8, 1,  0, 0}, // #11
     351             :   {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #12
     352             :   {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1,  1, 1,  0, 0}, // #13
     353             :   {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1,  4, 1,  0, 0}, // #14
     354             :   {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #15
     355             :   {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #16
     356             :   {DBGFIELD("NullALU_WriteQuarterRate32_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #17
     357             :   {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 14, 2,  0, 0}, // #18
     358             :   {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1, 16, 1,  0, 0}, // #19
     359             :   {DBGFIELD("COPY")               16382, false, false,  0, 0,  0, 0,  0, 0}, // #20
     360             :   {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #21
     361             :   {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  8, 1,  0, 0}, // #22
     362             :   {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0}, // #23
     363             : }; // SIFullSpeedModelSchedClasses
     364             : 
     365             : static const llvm::MCSchedModel NoSchedModel = {
     366             :   MCSchedModel::DefaultIssueWidth,
     367             :   MCSchedModel::DefaultMicroOpBufferSize,
     368             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     369             :   MCSchedModel::DefaultLoadLatency,
     370             :   MCSchedModel::DefaultHighLatency,
     371             :   MCSchedModel::DefaultMispredictPenalty,
     372             :   false, // PostRAScheduler
     373             :   false, // CompleteModel
     374             :   0, // Processor ID
     375             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     376             :   nullptr, // No Itinerary
     377             :   nullptr // No extra processor descriptor
     378             : };
     379             : 
     380             : static const unsigned SIQuarterSpeedModelProcResourceSubUnits[] = {
     381             :   0,  // Invalid
     382             : };
     383             : 
     384             : // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
     385             : static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = {
     386             :   {"InvalidUnit", 0, 0, 0, 0},
     387             :   {"HWBranch",        1, 0, 1, nullptr}, // #1
     388             :   {"HWExport",        1, 0, 7, nullptr}, // #2
     389             :   {"HWLGKM",          1, 0, 31, nullptr}, // #3
     390             :   {"HWSALU",          1, 0, 1, nullptr}, // #4
     391             :   {"HWVALU",          1, 0, 1, nullptr}, // #5
     392             :   {"HWVMEM",          1, 0, 15, nullptr}, // #6
     393             : };
     394             : 
     395             : static const llvm::MCSchedModel SIQuarterSpeedModel = {
     396             :   1, // IssueWidth
     397             :   1, // MicroOpBufferSize
     398             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     399             :   MCSchedModel::DefaultLoadLatency,
     400             :   MCSchedModel::DefaultHighLatency,
     401             :   20, // MispredictPenalty
     402             :   true, // PostRAScheduler
     403             :   false, // CompleteModel
     404             :   1, // Processor ID
     405             :   SIQuarterSpeedModelProcResources,
     406             :   SIQuarterSpeedModelSchedClasses,
     407             :   7,
     408             :   24,
     409             :   nullptr, // No Itinerary
     410             :   nullptr // No extra processor descriptor
     411             : };
     412             : 
     413             : static const unsigned SIFullSpeedModelProcResourceSubUnits[] = {
     414             :   0,  // Invalid
     415             : };
     416             : 
     417             : // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
     418             : static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = {
     419             :   {"InvalidUnit", 0, 0, 0, 0},
     420             :   {"HWBranch",        1, 0, 1, nullptr}, // #1
     421             :   {"HWExport",        1, 0, 7, nullptr}, // #2
     422             :   {"HWLGKM",          1, 0, 31, nullptr}, // #3
     423             :   {"HWSALU",          1, 0, 1, nullptr}, // #4
     424             :   {"HWVALU",          1, 0, 1, nullptr}, // #5
     425             :   {"HWVMEM",          1, 0, 15, nullptr}, // #6
     426             : };
     427             : 
     428             : static const llvm::MCSchedModel SIFullSpeedModel = {
     429             :   1, // IssueWidth
     430             :   1, // MicroOpBufferSize
     431             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     432             :   MCSchedModel::DefaultLoadLatency,
     433             :   MCSchedModel::DefaultHighLatency,
     434             :   20, // MispredictPenalty
     435             :   true, // PostRAScheduler
     436             :   false, // CompleteModel
     437             :   2, // Processor ID
     438             :   SIFullSpeedModelProcResources,
     439             :   SIFullSpeedModelSchedClasses,
     440             :   7,
     441             :   24,
     442             :   nullptr, // No Itinerary
     443             :   nullptr // No extra processor descriptor
     444             : };
     445             : 
     446             : // Sorted (by key) array of itineraries for CPU subtype.
     447             : extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[] = {
     448             :   { "bonaire", (const void *)&SIQuarterSpeedModel },
     449             :   { "carrizo", (const void *)&SIQuarterSpeedModel },
     450             :   { "fiji", (const void *)&SIQuarterSpeedModel },
     451             :   { "generic", (const void *)&NoSchedModel },
     452             :   { "gfx600", (const void *)&SIFullSpeedModel },
     453             :   { "gfx601", (const void *)&SIQuarterSpeedModel },
     454             :   { "gfx700", (const void *)&SIQuarterSpeedModel },
     455             :   { "gfx701", (const void *)&SIFullSpeedModel },
     456             :   { "gfx702", (const void *)&SIQuarterSpeedModel },
     457             :   { "gfx703", (const void *)&SIQuarterSpeedModel },
     458             :   { "gfx704", (const void *)&SIQuarterSpeedModel },
     459             :   { "gfx801", (const void *)&SIQuarterSpeedModel },
     460             :   { "gfx802", (const void *)&SIQuarterSpeedModel },
     461             :   { "gfx803", (const void *)&SIQuarterSpeedModel },
     462             :   { "gfx810", (const void *)&SIQuarterSpeedModel },
     463             :   { "gfx900", (const void *)&SIQuarterSpeedModel },
     464             :   { "gfx902", (const void *)&SIQuarterSpeedModel },
     465             :   { "gfx904", (const void *)&SIQuarterSpeedModel },
     466             :   { "gfx906", (const void *)&SIQuarterSpeedModel },
     467             :   { "hainan", (const void *)&SIQuarterSpeedModel },
     468             :   { "hawaii", (const void *)&SIFullSpeedModel },
     469             :   { "iceland", (const void *)&SIQuarterSpeedModel },
     470             :   { "kabini", (const void *)&SIQuarterSpeedModel },
     471             :   { "kaveri", (const void *)&SIQuarterSpeedModel },
     472             :   { "mullins", (const void *)&SIQuarterSpeedModel },
     473             :   { "oland", (const void *)&SIQuarterSpeedModel },
     474             :   { "pitcairn", (const void *)&SIQuarterSpeedModel },
     475             :   { "polaris10", (const void *)&SIQuarterSpeedModel },
     476             :   { "polaris11", (const void *)&SIQuarterSpeedModel },
     477             :   { "stoney", (const void *)&SIQuarterSpeedModel },
     478             :   { "tahiti", (const void *)&SIFullSpeedModel },
     479             :   { "tonga", (const void *)&SIQuarterSpeedModel },
     480             :   { "verde", (const void *)&SIQuarterSpeedModel },
     481             : };
     482             : 
     483             : #undef DBGFIELD
     484             : namespace AMDGPU_MC {
     485           0 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
     486             :     const MCInst *MI, unsigned CPUID) {
     487             :   // Don't know how to resolve this scheduling class.
     488           0 :   return 0;
     489             : }
     490             : } // end of namespace AMDGPU_MC
     491             : 
     492             : struct AMDGPUGenMCSubtargetInfo : public MCSubtargetInfo {
     493             :   AMDGPUGenMCSubtargetInfo(const Triple &TT, 
     494             :     StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
     495             :     ArrayRef<SubtargetFeatureKV> PD,
     496             :     const SubtargetInfoKV *ProcSched,
     497             :     const MCWriteProcResEntry *WPR,
     498             :     const MCWriteLatencyEntry *WL,
     499             :     const MCReadAdvanceEntry *RA, const InstrStage *IS,
     500        2929 :     const unsigned *OC, const unsigned *FP) :
     501             :       MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
     502        2929 :                       WPR, WL, RA, IS, OC, FP) { }
     503             : 
     504           0 :   unsigned resolveVariantSchedClass(unsigned SchedClass,
     505             :       const MCInst *MI, unsigned CPUID) const override {
     506           0 :     return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
     507             :   }
     508             : };
     509             : 
     510        2929 : static inline MCSubtargetInfo *createAMDGPUMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
     511             :   return new AMDGPUGenMCSubtargetInfo(TT, CPU, FS, AMDGPUFeatureKV, AMDGPUSubTypeKV, 
     512             :                       AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
     513        2929 :                       nullptr, nullptr, nullptr);
     514             : }
     515             : 
     516             : } // end namespace llvm
     517             : 
     518             : #endif // GET_SUBTARGETINFO_MC_DESC
     519             : 
     520             : 
     521             : #ifdef GET_SUBTARGETINFO_TARGET_DESC
     522             : #undef GET_SUBTARGETINFO_TARGET_DESC
     523             : 
     524             : #include "llvm/Support/Debug.h"
     525             : #include "llvm/Support/raw_ostream.h"
     526             : 
     527             : // ParseSubtargetFeatures - Parses features string setting specified
     528             : // subtarget options.
     529        2490 : void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
     530             :   LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
     531             :   LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
     532        2490 :   InitMCProcessorInfo(CPU, FS);
     533             :   const FeatureBitset& Bits = getFeatureBits();
     534        2490 :   if (Bits[AMDGPU::Feature16BitInsts]) Has16BitInsts = true;
     535        2490 :   if (Bits[AMDGPU::FeatureAddNoCarryInsts]) AddNoCarryInsts = true;
     536        2490 :   if (Bits[AMDGPU::FeatureApertureRegs]) HasApertureRegs = true;
     537        2490 :   if (Bits[AMDGPU::FeatureAutoWaitcntBeforeBarrier]) AutoWaitcntBeforeBarrier = true;
     538        2490 :   if (Bits[AMDGPU::FeatureCIInsts]) CIInsts = true;
     539        2490 :   if (Bits[AMDGPU::FeatureCodeObjectV3]) CodeObjectV3 = true;
     540        2490 :   if (Bits[AMDGPU::FeatureD16PreservesUnusedBits]) D16PreservesUnusedBits = true;
     541        2490 :   if (Bits[AMDGPU::FeatureDLInsts]) HasDLInsts = true;
     542        2490 :   if (Bits[AMDGPU::FeatureDPP]) HasDPP = true;
     543        2490 :   if (Bits[AMDGPU::FeatureDX10Clamp]) DX10Clamp = true;
     544        2490 :   if (Bits[AMDGPU::FeatureDebuggerEmitPrologue]) DebuggerEmitPrologue = true;
     545        2490 :   if (Bits[AMDGPU::FeatureDebuggerInsertNops]) DebuggerInsertNops = true;
     546        2490 :   if (Bits[AMDGPU::FeatureDisable]) FeatureDisable = true;
     547        2490 :   if (Bits[AMDGPU::FeatureDumpCode]) DumpCode = true;
     548        2490 :   if (Bits[AMDGPU::FeatureDumpCodeLower]) DumpCode = true;
     549        2490 :   if (Bits[AMDGPU::FeatureEnableDS128]) EnableDS128 = true;
     550        2490 :   if (Bits[AMDGPU::FeatureEnableHugePrivateBuffer]) EnableHugePrivateBuffer = true;
     551        2490 :   if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) EnableLoadStoreOpt = true;
     552        2490 :   if (Bits[AMDGPU::FeatureEnableSIScheduler]) EnableSIScheduler = true;
     553        2490 :   if (Bits[AMDGPU::FeatureEnableUnsafeDSOffsetFolding]) EnableUnsafeDSOffsetFolding = true;
     554        2490 :   if (Bits[AMDGPU::FeatureFMA]) FMA = true;
     555        2490 :   if (Bits[AMDGPU::FeatureFP16Denormals]) FP64FP16Denormals = true;
     556        2490 :   if (Bits[AMDGPU::FeatureFP32Denormals]) FP32Denormals = true;
     557        2490 :   if (Bits[AMDGPU::FeatureFP64]) FP64 = true;
     558        2490 :   if (Bits[AMDGPU::FeatureFP64Denormals]) FP64FP16Denormals = true;
     559        2490 :   if (Bits[AMDGPU::FeatureFP64FP16Denormals]) FP64FP16Denormals = true;
     560        2490 :   if (Bits[AMDGPU::FeatureFPExceptions]) FPExceptions = true;
     561        2490 :   if (Bits[AMDGPU::FeatureFastFMAF32]) FastFMAF32 = true;
     562        2490 :   if (Bits[AMDGPU::FeatureFlatAddressSpace]) FlatAddressSpace = true;
     563        2490 :   if (Bits[AMDGPU::FeatureFlatForGlobal]) FlatForGlobal = true;
     564        2490 :   if (Bits[AMDGPU::FeatureFlatGlobalInsts]) FlatGlobalInsts = true;
     565        2490 :   if (Bits[AMDGPU::FeatureFlatInstOffsets]) FlatInstOffsets = true;
     566        2490 :   if (Bits[AMDGPU::FeatureFlatScratchInsts]) FlatScratchInsts = true;
     567        2490 :   if (Bits[AMDGPU::FeatureFmaMixInsts]) HasFmaMixInsts = true;
     568        2490 :   if (Bits[AMDGPU::FeatureGCN]) IsGCN = true;
     569        2490 :   if (Bits[AMDGPU::FeatureGCN3Encoding]) GCN3Encoding = true;
     570        2490 :   if (Bits[AMDGPU::FeatureGFX9] && Gen < GCNSubtarget::GFX9) Gen = GCNSubtarget::GFX9;
     571        2490 :   if (Bits[AMDGPU::FeatureGFX9Insts]) GFX9Insts = true;
     572        2490 :   if (Bits[AMDGPU::FeatureISAVersion6_0_0] && IsaVersion < ISAVersion6_0_0) IsaVersion = ISAVersion6_0_0;
     573        2490 :   if (Bits[AMDGPU::FeatureISAVersion6_0_1] && IsaVersion < ISAVersion6_0_1) IsaVersion = ISAVersion6_0_1;
     574        2490 :   if (Bits[AMDGPU::FeatureISAVersion7_0_0] && IsaVersion < ISAVersion7_0_0) IsaVersion = ISAVersion7_0_0;
     575        2490 :   if (Bits[AMDGPU::FeatureISAVersion7_0_1] && IsaVersion < ISAVersion7_0_1) IsaVersion = ISAVersion7_0_1;
     576        2490 :   if (Bits[AMDGPU::FeatureISAVersion7_0_2] && IsaVersion < ISAVersion7_0_2) IsaVersion = ISAVersion7_0_2;
     577        2490 :   if (Bits[AMDGPU::FeatureISAVersion7_0_3] && IsaVersion < ISAVersion7_0_3) IsaVersion = ISAVersion7_0_3;
     578        2490 :   if (Bits[AMDGPU::FeatureISAVersion7_0_4] && IsaVersion < ISAVersion7_0_4) IsaVersion = ISAVersion7_0_4;
     579        2490 :   if (Bits[AMDGPU::FeatureISAVersion8_0_1] && IsaVersion < ISAVersion8_0_1) IsaVersion = ISAVersion8_0_1;
     580        2490 :   if (Bits[AMDGPU::FeatureISAVersion8_0_2] && IsaVersion < ISAVersion8_0_2) IsaVersion = ISAVersion8_0_2;
     581        2490 :   if (Bits[AMDGPU::FeatureISAVersion8_0_3] && IsaVersion < ISAVersion8_0_3) IsaVersion = ISAVersion8_0_3;
     582        2490 :   if (Bits[AMDGPU::FeatureISAVersion8_1_0] && IsaVersion < ISAVersion8_1_0) IsaVersion = ISAVersion8_1_0;
     583        2490 :   if (Bits[AMDGPU::FeatureISAVersion9_0_0] && IsaVersion < ISAVersion9_0_0) IsaVersion = ISAVersion9_0_0;
     584        2490 :   if (Bits[AMDGPU::FeatureISAVersion9_0_2] && IsaVersion < ISAVersion9_0_2) IsaVersion = ISAVersion9_0_2;
     585        2490 :   if (Bits[AMDGPU::FeatureISAVersion9_0_4] && IsaVersion < ISAVersion9_0_4) IsaVersion = ISAVersion9_0_4;
     586        2490 :   if (Bits[AMDGPU::FeatureISAVersion9_0_6] && IsaVersion < ISAVersion9_0_6) IsaVersion = ISAVersion9_0_6;
     587        2490 :   if (Bits[AMDGPU::FeatureIntClamp]) HasIntClamp = true;
     588        2490 :   if (Bits[AMDGPU::FeatureInv2PiInlineImm]) HasInv2PiInlineImm = true;
     589        2490 :   if (Bits[AMDGPU::FeatureLDSBankCount16] && LDSBankCount < 16) LDSBankCount = 16;
     590        2490 :   if (Bits[AMDGPU::FeatureLDSBankCount32] && LDSBankCount < 32) LDSBankCount = 32;
     591        2490 :   if (Bits[AMDGPU::FeatureLocalMemorySize0] && LocalMemorySize < 0) LocalMemorySize = 0;
     592        2490 :   if (Bits[AMDGPU::FeatureLocalMemorySize32768] && LocalMemorySize < 32768) LocalMemorySize = 32768;
     593        2490 :   if (Bits[AMDGPU::FeatureLocalMemorySize65536] && LocalMemorySize < 65536) LocalMemorySize = 65536;
     594        2490 :   if (Bits[AMDGPU::FeatureMIMG_R128]) MIMG_R128 = true;
     595        2490 :   if (Bits[AMDGPU::FeatureMadMixInsts]) HasMadMixInsts = true;
     596        2490 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize4] && MaxPrivateElementSize < 4) MaxPrivateElementSize = 4;
     597        2490 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize8] && MaxPrivateElementSize < 8) MaxPrivateElementSize = 8;
     598        2490 :   if (Bits[AMDGPU::FeatureMaxPrivateElementSize16] && MaxPrivateElementSize < 16) MaxPrivateElementSize = 16;
     599        2490 :   if (Bits[AMDGPU::FeatureMovrel]) HasMovrel = true;
     600        2490 :   if (Bits[AMDGPU::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
     601        2490 :   if (Bits[AMDGPU::FeatureR128A16]) HasR128A16 = true;
     602        2490 :   if (Bits[AMDGPU::FeatureSDWA]) HasSDWA = true;
     603        2490 :   if (Bits[AMDGPU::FeatureSDWAMac]) HasSDWAMac = true;
     604        2490 :   if (Bits[AMDGPU::FeatureSDWAOmod]) HasSDWAOmod = true;
     605        2490 :   if (Bits[AMDGPU::FeatureSDWAOutModsVOPC]) HasSDWAOutModsVOPC = true;
     606        2490 :   if (Bits[AMDGPU::FeatureSDWAScalar]) HasSDWAScalar = true;
     607        2490 :   if (Bits[AMDGPU::FeatureSDWASdst]) HasSDWASdst = true;
     608        2490 :   if (Bits[AMDGPU::FeatureSGPRInitBug]) SGPRInitBug = true;
     609        2490 :   if (Bits[AMDGPU::FeatureSMemRealTime]) HasSMemRealTime = true;
     610        2490 :   if (Bits[AMDGPU::FeatureScalarAtomics]) HasScalarAtomics = true;
     611        2490 :   if (Bits[AMDGPU::FeatureScalarStores]) HasScalarStores = true;
     612        2490 :   if (Bits[AMDGPU::FeatureSeaIslands] && Gen < GCNSubtarget::SEA_ISLANDS) Gen = GCNSubtarget::SEA_ISLANDS;
     613        2490 :   if (Bits[AMDGPU::FeatureSouthernIslands] && Gen < GCNSubtarget::SOUTHERN_ISLANDS) Gen = GCNSubtarget::SOUTHERN_ISLANDS;
     614        2490 :   if (Bits[AMDGPU::FeatureTrapHandler]) TrapHandler = true;
     615        2490 :   if (Bits[AMDGPU::FeatureTrigReducedRange]) HasTrigReducedRange = true;
     616        2490 :   if (Bits[AMDGPU::FeatureUnalignedBufferAccess]) UnalignedBufferAccess = true;
     617        2490 :   if (Bits[AMDGPU::FeatureUnalignedScratchAccess]) UnalignedScratchAccess = true;
     618        2490 :   if (Bits[AMDGPU::FeatureUnpackedD16VMem]) HasUnpackedD16VMem = true;
     619        2490 :   if (Bits[AMDGPU::FeatureVGPRIndexMode]) HasVGPRIndexMode = true;
     620        2490 :   if (Bits[AMDGPU::FeatureVGPRSpilling]) EnableVGPRSpilling = true;
     621        2490 :   if (Bits[AMDGPU::FeatureVIInsts]) VIInsts = true;
     622        2490 :   if (Bits[AMDGPU::FeatureVOP3P]) HasVOP3PInsts = true;
     623        2490 :   if (Bits[AMDGPU::FeatureVolcanicIslands] && Gen < GCNSubtarget::VOLCANIC_ISLANDS) Gen = GCNSubtarget::VOLCANIC_ISLANDS;
     624        2490 :   if (Bits[AMDGPU::FeatureWavefrontSize16] && WavefrontSize < 16) WavefrontSize = 16;
     625        2490 :   if (Bits[AMDGPU::FeatureWavefrontSize32] && WavefrontSize < 32) WavefrontSize = 32;
     626        2490 :   if (Bits[AMDGPU::FeatureWavefrontSize64] && WavefrontSize < 64) WavefrontSize = 64;
     627        2490 :   if (Bits[AMDGPU::FeatureXNACK]) EnableXNACK = true;
     628        2490 :   if (Bits[AMDGPU::HalfRate64Ops]) HalfRate64Ops = true;
     629        2490 : }
     630             : #endif // GET_SUBTARGETINFO_TARGET_DESC
     631             : 
     632             : 
     633             : #ifdef GET_SUBTARGETINFO_HEADER
     634             : #undef GET_SUBTARGETINFO_HEADER
     635             : 
     636             : namespace llvm {
     637             : class DFAPacketizer;
     638             : namespace AMDGPU_MC {
     639             : unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
     640             : }
     641             : 
     642        2479 : struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo {
     643             :   explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
     644             : public:
     645             :   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
     646             :   unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
     647             :   DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
     648             : };
     649             : } // end namespace llvm
     650             : 
     651             : #endif // GET_SUBTARGETINFO_HEADER
     652             : 
     653             : 
     654             : #ifdef GET_SUBTARGETINFO_CTOR
     655             : #undef GET_SUBTARGETINFO_CTOR
     656             : 
     657             : #include "llvm/CodeGen/TargetSchedule.h"
     658             : 
     659             : namespace llvm {
     660             : extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[];
     661             : extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[];
     662             : extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[];
     663             : extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[];
     664             : extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[];
     665             : extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[];
     666        2490 : AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
     667             :   : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(AMDGPUFeatureKV, 94), makeArrayRef(AMDGPUSubTypeKV, 33), 
     668             :                         AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
     669        2490 :                         nullptr, nullptr, nullptr) {}
     670             : 
     671      662383 : unsigned AMDGPUGenSubtargetInfo
     672             : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
     673             : 
     674             :   const SIInstrInfo *TII =
     675      662383 :     static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
     676             :   (void)TII;
     677             : 
     678      662383 :   switch (SchedClass) {
     679             :   case 20: // COPY
     680      662383 :     if (SchedModel->getProcessorID() == 1) { // SIQuarterSpeedModel
     681      579788 :       if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
     682             :         return 21; // Write32Bit
     683      233252 :       if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
     684             :         return 22; // Write64Bit
     685      233202 :       return 23; // WriteSALU
     686             :     }
     687       82595 :     if (SchedModel->getProcessorID() == 2) { // SIFullSpeedModel
     688       82595 :       if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
     689             :         return 21; // Write32Bit
     690       37214 :       if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
     691             :         return 22; // Write64Bit
     692       37214 :       return 23; // WriteSALU
     693             :     }
     694             :     break;
     695             :   };
     696           0 :   report_fatal_error("Expected a variant SchedClass");
     697             : } // AMDGPUGenSubtargetInfo::resolveSchedClass
     698             : 
     699           0 : unsigned AMDGPUGenSubtargetInfo
     700             : ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
     701           0 :   return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
     702             : } // AMDGPUGenSubtargetInfo::resolveVariantSchedClass
     703             : 
     704             : } // end namespace llvm
     705             : 
     706             : #endif // GET_SUBTARGETINFO_CTOR
     707             : 
     708             : 
     709             : #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
     710             : #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
     711             : 
     712             : #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
     713             : 
     714             : 
     715             : #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
     716             : #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
     717             : 
     718             : #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
     719             : 

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