LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/ARM - ARMGenAsmMatcher.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1454 2552 57.0 %
Date: 2017-09-14 15:23:50 Functions: 12 13 92.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Assembly Matcher Source Fragment                                           *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_ASSEMBLER_HEADER
      11             : #undef GET_ASSEMBLER_HEADER
      12             :   // This should be included into the middle of the declaration of
      13             :   // your subclasses implementation of MCTargetAsmParser.
      14             :   uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
      15             :   void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
      16             :                        const OperandVector &Operands);
      17             :   void convertToMapAndConstraints(unsigned Kind,
      18             :                            const OperandVector &Operands) override;
      19             :   unsigned MatchInstructionImpl(const OperandVector &Operands,
      20             :                                 MCInst &Inst,
      21             :                                 uint64_t &ErrorInfo, bool matchingInlineAsm,
      22             :                                 unsigned VariantID = 0);
      23             :   OperandMatchResultTy MatchOperandParserImpl(
      24             :     OperandVector &Operands,
      25             :     StringRef Mnemonic);
      26             :   OperandMatchResultTy tryCustomParseOperand(
      27             :     OperandVector &Operands,
      28             :     unsigned MCK);
      29             : 
      30             : #endif // GET_ASSEMBLER_HEADER_INFO
      31             : 
      32             : 
      33             : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
      34             : #undef GET_OPERAND_DIAGNOSTIC_TYPES
      35             : 
      36             :   Match_AlignedMemoryRequires16,
      37             :   Match_AlignedMemoryRequires32,
      38             :   Match_AlignedMemoryRequires64,
      39             :   Match_AlignedMemoryRequires64or128,
      40             :   Match_AlignedMemoryRequires64or128or256,
      41             :   Match_AlignedMemoryRequiresNone,
      42             :   Match_DupAlignedMemoryRequires16,
      43             :   Match_DupAlignedMemoryRequires32,
      44             :   Match_DupAlignedMemoryRequires64,
      45             :   Match_DupAlignedMemoryRequires64or128,
      46             :   Match_DupAlignedMemoryRequiresNone,
      47             :   Match_ImmRange0_1,
      48             :   Match_ImmRange0_15,
      49             :   Match_ImmRange0_16777215,
      50             :   Match_ImmRange0_239,
      51             :   Match_ImmRange0_255,
      52             :   Match_ImmRange0_3,
      53             :   Match_ImmRange0_31,
      54             :   Match_ImmRange0_32,
      55             :   Match_ImmRange0_4095,
      56             :   Match_ImmRange0_63,
      57             :   Match_ImmRange0_65535,
      58             :   Match_ImmRange0_7,
      59             :   Match_ImmRange16_16,
      60             :   Match_ImmRange1_15,
      61             :   Match_ImmRange1_16,
      62             :   Match_ImmRange1_31,
      63             :   Match_ImmRange1_32,
      64             :   Match_ImmRange1_64,
      65             :   Match_ImmRange1_7,
      66             :   Match_ImmRange1_8,
      67             :   Match_ImmRange256_65535,
      68             :   Match_ImmRange32_32,
      69             :   Match_ImmRange8_255,
      70             :   Match_ImmRange8_8,
      71             :   END_OPERAND_DIAGNOSTIC_TYPES
      72             : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
      73             : 
      74             : 
      75             : #ifdef GET_REGISTER_MATCHER
      76             : #undef GET_REGISTER_MATCHER
      77             : 
      78             : // Flags for subtarget features that participate in instruction matching.
      79             : enum SubtargetFeatureFlag : uint64_t {
      80             :   Feature_HasV4T = (1ULL << 17),
      81             :   Feature_HasV5T = (1ULL << 18),
      82             :   Feature_HasV5TE = (1ULL << 19),
      83             :   Feature_HasV6 = (1ULL << 20),
      84             :   Feature_HasV6M = (1ULL << 22),
      85             :   Feature_HasV8MBaseline = (1ULL << 27),
      86             :   Feature_HasV8MMainline = (1ULL << 28),
      87             :   Feature_HasV6T2 = (1ULL << 23),
      88             :   Feature_HasV6K = (1ULL << 21),
      89             :   Feature_HasV7 = (1ULL << 24),
      90             :   Feature_HasV8 = (1ULL << 26),
      91             :   Feature_PreV8 = (1ULL << 41),
      92             :   Feature_HasV8_1a = (1ULL << 29),
      93             :   Feature_HasV8_2a = (1ULL << 30),
      94             :   Feature_HasV8_3a = (1ULL << 31),
      95             :   Feature_HasVFP2 = (1ULL << 32),
      96             :   Feature_HasVFP3 = (1ULL << 33),
      97             :   Feature_HasVFP4 = (1ULL << 34),
      98             :   Feature_HasDPVFP = (1ULL << 5),
      99             :   Feature_HasFPARMv8 = (1ULL << 11),
     100             :   Feature_HasNEON = (1ULL << 14),
     101             :   Feature_HasCrypto = (1ULL << 3),
     102             :   Feature_HasDotProd = (1ULL << 9),
     103             :   Feature_HasCRC = (1ULL << 2),
     104             :   Feature_HasRAS = (1ULL << 15),
     105             :   Feature_HasFP16 = (1ULL << 10),
     106             :   Feature_HasFullFP16 = (1ULL << 12),
     107             :   Feature_HasDivideInThumb = (1ULL << 8),
     108             :   Feature_HasDivideInARM = (1ULL << 7),
     109             :   Feature_HasDSP = (1ULL << 6),
     110             :   Feature_HasDB = (1ULL << 4),
     111             :   Feature_HasV7Clrex = (1ULL << 25),
     112             :   Feature_HasAcquireRelease = (1ULL << 1),
     113             :   Feature_HasMP = (1ULL << 13),
     114             :   Feature_HasVirtualization = (1ULL << 35),
     115             :   Feature_HasTrustZone = (1ULL << 16),
     116             :   Feature_Has8MSecExt = (1ULL << 0),
     117             :   Feature_IsThumb = (1ULL << 39),
     118             :   Feature_IsThumb2 = (1ULL << 40),
     119             :   Feature_IsMClass = (1ULL << 37),
     120             :   Feature_IsNotMClass = (1ULL << 38),
     121             :   Feature_IsARM = (1ULL << 36),
     122             :   Feature_UseNaClTrap = (1ULL << 42),
     123             :   Feature_UseNegativeImmediates = (1ULL << 43),
     124             :   Feature_None = 0
     125             : };
     126             : 
     127       49600 : static unsigned MatchRegisterName(StringRef Name) {
     128       49600 :   switch (Name.size()) {
     129             :   default: break;
     130       43462 :   case 2:        // 43 strings to match.
     131       86924 :     switch (Name[0]) {
     132             :     default: break;
     133        9844 :     case 'd':    // 10 strings to match.
     134       19688 :       switch (Name[1]) {
     135             :       default: break;
     136             :       case '0':  // 1 string to match.
     137             :         return 14;       // "d0"
     138             :       case '1':  // 1 string to match.
     139             :         return 15;       // "d1"
     140             :       case '2':  // 1 string to match.
     141             :         return 16;       // "d2"
     142             :       case '3':  // 1 string to match.
     143             :         return 17;       // "d3"
     144             :       case '4':  // 1 string to match.
     145             :         return 18;       // "d4"
     146             :       case '5':  // 1 string to match.
     147             :         return 19;       // "d5"
     148             :       case '6':  // 1 string to match.
     149             :         return 20;       // "d6"
     150             :       case '7':  // 1 string to match.
     151             :         return 21;       // "d7"
     152             :       case '8':  // 1 string to match.
     153             :         return 22;       // "d8"
     154             :       case '9':  // 1 string to match.
     155             :         return 23;       // "d9"
     156             :       }
     157             :       break;
     158         574 :     case 'l':    // 1 string to match.
     159        1148 :       if (Name[1] != 'r')
     160             :         break;
     161             :       return 10;         // "lr"
     162         625 :     case 'p':    // 1 string to match.
     163        1250 :       if (Name[1] != 'c')
     164             :         break;
     165             :       return 11;         // "pc"
     166        3711 :     case 'q':    // 10 strings to match.
     167        7422 :       switch (Name[1]) {
     168             :       default: break;
     169             :       case '0':  // 1 string to match.
     170             :         return 50;       // "q0"
     171             :       case '1':  // 1 string to match.
     172             :         return 51;       // "q1"
     173             :       case '2':  // 1 string to match.
     174             :         return 52;       // "q2"
     175             :       case '3':  // 1 string to match.
     176             :         return 53;       // "q3"
     177             :       case '4':  // 1 string to match.
     178             :         return 54;       // "q4"
     179             :       case '5':  // 1 string to match.
     180             :         return 55;       // "q5"
     181             :       case '6':  // 1 string to match.
     182             :         return 56;       // "q6"
     183             :       case '7':  // 1 string to match.
     184             :         return 57;       // "q7"
     185             :       case '8':  // 1 string to match.
     186             :         return 58;       // "q8"
     187             :       case '9':  // 1 string to match.
     188             :         return 59;       // "q9"
     189             :       }
     190             :       break;
     191       25603 :     case 'r':    // 10 strings to match.
     192       51206 :       switch (Name[1]) {
     193             :       default: break;
     194             :       case '0':  // 1 string to match.
     195             :         return 66;       // "r0"
     196             :       case '1':  // 1 string to match.
     197             :         return 67;       // "r1"
     198             :       case '2':  // 1 string to match.
     199             :         return 68;       // "r2"
     200             :       case '3':  // 1 string to match.
     201             :         return 69;       // "r3"
     202             :       case '4':  // 1 string to match.
     203             :         return 70;       // "r4"
     204             :       case '5':  // 1 string to match.
     205             :         return 71;       // "r5"
     206             :       case '6':  // 1 string to match.
     207             :         return 72;       // "r6"
     208             :       case '7':  // 1 string to match.
     209             :         return 73;       // "r7"
     210             :       case '8':  // 1 string to match.
     211             :         return 74;       // "r8"
     212             :       case '9':  // 1 string to match.
     213             :         return 75;       // "r9"
     214             :       }
     215             :       break;
     216        2977 :     case 's':    // 11 strings to match.
     217        5954 :       switch (Name[1]) {
     218             :       default: break;
     219             :       case '0':  // 1 string to match.
     220             :         return 79;       // "s0"
     221             :       case '1':  // 1 string to match.
     222             :         return 80;       // "s1"
     223             :       case '2':  // 1 string to match.
     224             :         return 81;       // "s2"
     225             :       case '3':  // 1 string to match.
     226             :         return 82;       // "s3"
     227             :       case '4':  // 1 string to match.
     228             :         return 83;       // "s4"
     229             :       case '5':  // 1 string to match.
     230             :         return 84;       // "s5"
     231             :       case '6':  // 1 string to match.
     232             :         return 85;       // "s6"
     233             :       case '7':  // 1 string to match.
     234             :         return 86;       // "s7"
     235             :       case '8':  // 1 string to match.
     236             :         return 87;       // "s8"
     237             :       case '9':  // 1 string to match.
     238             :         return 88;       // "s9"
     239             :       case 'p':  // 1 string to match.
     240             :         return 12;       // "sp"
     241             :       }
     242             :       break;
     243             :     }
     244             :     break;
     245        5872 :   case 3:        // 53 strings to match.
     246       11744 :     switch (Name[0]) {
     247             :     default: break;
     248        3521 :     case 'd':    // 22 strings to match.
     249        7042 :       switch (Name[1]) {
     250             :       default: break;
     251        3139 :       case '1':  // 10 strings to match.
     252        6278 :         switch (Name[2]) {
     253             :         default: break;
     254             :         case '0':        // 1 string to match.
     255             :           return 24;     // "d10"
     256             :         case '1':        // 1 string to match.
     257             :           return 25;     // "d11"
     258             :         case '2':        // 1 string to match.
     259             :           return 26;     // "d12"
     260             :         case '3':        // 1 string to match.
     261             :           return 27;     // "d13"
     262             :         case '4':        // 1 string to match.
     263             :           return 28;     // "d14"
     264             :         case '5':        // 1 string to match.
     265             :           return 29;     // "d15"
     266             :         case '6':        // 1 string to match.
     267             :           return 30;     // "d16"
     268             :         case '7':        // 1 string to match.
     269             :           return 31;     // "d17"
     270             :         case '8':        // 1 string to match.
     271             :           return 32;     // "d18"
     272             :         case '9':        // 1 string to match.
     273             :           return 33;     // "d19"
     274             :         }
     275             :         break;
     276         347 :       case '2':  // 10 strings to match.
     277         694 :         switch (Name[2]) {
     278             :         default: break;
     279             :         case '0':        // 1 string to match.
     280             :           return 34;     // "d20"
     281             :         case '1':        // 1 string to match.
     282             :           return 35;     // "d21"
     283             :         case '2':        // 1 string to match.
     284             :           return 36;     // "d22"
     285             :         case '3':        // 1 string to match.
     286             :           return 37;     // "d23"
     287             :         case '4':        // 1 string to match.
     288             :           return 38;     // "d24"
     289             :         case '5':        // 1 string to match.
     290             :           return 39;     // "d25"
     291             :         case '6':        // 1 string to match.
     292             :           return 40;     // "d26"
     293             :         case '7':        // 1 string to match.
     294             :           return 41;     // "d27"
     295             :         case '8':        // 1 string to match.
     296             :           return 42;     // "d28"
     297             :         case '9':        // 1 string to match.
     298             :           return 43;     // "d29"
     299             :         }
     300             :         break;
     301          35 :       case '3':  // 2 strings to match.
     302          70 :         switch (Name[2]) {
     303             :         default: break;
     304             :         case '0':        // 1 string to match.
     305             :           return 44;     // "d30"
     306          18 :         case '1':        // 1 string to match.
     307          18 :           return 45;     // "d31"
     308             :         }
     309             :         break;
     310             :       }
     311             :       break;
     312         149 :     case 'q':    // 6 strings to match.
     313         298 :       if (Name[1] != '1')
     314             :         break;
     315         298 :       switch (Name[2]) {
     316             :       default: break;
     317             :       case '0':  // 1 string to match.
     318             :         return 60;       // "q10"
     319             :       case '1':  // 1 string to match.
     320             :         return 61;       // "q11"
     321             :       case '2':  // 1 string to match.
     322             :         return 62;       // "q12"
     323             :       case '3':  // 1 string to match.
     324             :         return 63;       // "q13"
     325             :       case '4':  // 1 string to match.
     326             :         return 64;       // "q14"
     327             :       case '5':  // 1 string to match.
     328             :         return 65;       // "q15"
     329             :       }
     330             :       break;
     331        1307 :     case 'r':    // 3 strings to match.
     332        2614 :       if (Name[1] != '1')
     333             :         break;
     334        2186 :       switch (Name[2]) {
     335             :       default: break;
     336             :       case '0':  // 1 string to match.
     337             :         return 76;       // "r10"
     338             :       case '1':  // 1 string to match.
     339             :         return 77;       // "r11"
     340             :       case '2':  // 1 string to match.
     341             :         return 78;       // "r12"
     342             :       }
     343             :       break;
     344         201 :     case 's':    // 22 strings to match.
     345         402 :       switch (Name[1]) {
     346             :       default: break;
     347         138 :       case '1':  // 10 strings to match.
     348         276 :         switch (Name[2]) {
     349             :         default: break;
     350             :         case '0':        // 1 string to match.
     351             :           return 89;     // "s10"
     352             :         case '1':        // 1 string to match.
     353             :           return 90;     // "s11"
     354             :         case '2':        // 1 string to match.
     355             :           return 91;     // "s12"
     356             :         case '3':        // 1 string to match.
     357             :           return 92;     // "s13"
     358             :         case '4':        // 1 string to match.
     359             :           return 93;     // "s14"
     360             :         case '5':        // 1 string to match.
     361             :           return 94;     // "s15"
     362             :         case '6':        // 1 string to match.
     363             :           return 95;     // "s16"
     364             :         case '7':        // 1 string to match.
     365             :           return 96;     // "s17"
     366             :         case '8':        // 1 string to match.
     367             :           return 97;     // "s18"
     368             :         case '9':        // 1 string to match.
     369             :           return 98;     // "s19"
     370             :         }
     371             :         break;
     372          57 :       case '2':  // 10 strings to match.
     373         114 :         switch (Name[2]) {
     374             :         default: break;
     375             :         case '0':        // 1 string to match.
     376             :           return 99;     // "s20"
     377             :         case '1':        // 1 string to match.
     378             :           return 100;    // "s21"
     379             :         case '2':        // 1 string to match.
     380             :           return 101;    // "s22"
     381             :         case '3':        // 1 string to match.
     382             :           return 102;    // "s23"
     383             :         case '4':        // 1 string to match.
     384             :           return 103;    // "s24"
     385             :         case '5':        // 1 string to match.
     386             :           return 104;    // "s25"
     387             :         case '6':        // 1 string to match.
     388             :           return 105;    // "s26"
     389             :         case '7':        // 1 string to match.
     390             :           return 106;    // "s27"
     391             :         case '8':        // 1 string to match.
     392             :           return 107;    // "s28"
     393             :         case '9':        // 1 string to match.
     394             :           return 108;    // "s29"
     395             :         }
     396             :         break;
     397           6 :       case '3':  // 2 strings to match.
     398          12 :         switch (Name[2]) {
     399             :         default: break;
     400             :         case '0':        // 1 string to match.
     401             :           return 109;    // "s30"
     402           0 :         case '1':        // 1 string to match.
     403           0 :           return 110;    // "s31"
     404             :         }
     405             :         break;
     406             :       }
     407             :       break;
     408             :     }
     409             :     break;
     410          65 :   case 4:        // 3 strings to match.
     411         130 :     switch (Name[0]) {
     412             :     default: break;
     413           4 :     case 'a':    // 1 string to match.
     414           4 :       if (memcmp(Name.data()+1, "psr", 3) != 0)
     415             :         break;
     416             :       return 1;  // "apsr"
     417           4 :     case 'c':    // 1 string to match.
     418           4 :       if (memcmp(Name.data()+1, "psr", 3) != 0)
     419             :         break;
     420             :       return 3;  // "cpsr"
     421          15 :     case 's':    // 1 string to match.
     422          15 :       if (memcmp(Name.data()+1, "psr", 3) != 0)
     423             :         break;
     424             :       return 13;         // "spsr"
     425             :     }
     426             :     break;
     427          49 :   case 5:        // 6 strings to match.
     428          98 :     switch (Name[0]) {
     429             :     default: break;
     430          13 :     case 'f':    // 3 strings to match.
     431          26 :       if (Name[1] != 'p')
     432             :         break;
     433          26 :       switch (Name[2]) {
     434             :       default: break;
     435           2 :       case 'e':  // 1 string to match.
     436           2 :         if (memcmp(Name.data()+3, "xc", 2) != 0)
     437             :           break;
     438             :         return 4;        // "fpexc"
     439          11 :       case 's':  // 2 strings to match.
     440          22 :         switch (Name[3]) {
     441             :         default: break;
     442           7 :         case 'c':        // 1 string to match.
     443          14 :           if (Name[4] != 'r')
     444             :             break;
     445             :           return 6;      // "fpscr"
     446           4 :         case 'i':        // 1 string to match.
     447           8 :           if (Name[4] != 'd')
     448             :             break;
     449             :           return 8;      // "fpsid"
     450             :         }
     451             :         break;
     452             :       }
     453             :       break;
     454          11 :     case 'm':    // 3 strings to match.
     455          11 :       if (memcmp(Name.data()+1, "vfr", 3) != 0)
     456             :         break;
     457          22 :       switch (Name[4]) {
     458             :       default: break;
     459             :       case '0':  // 1 string to match.
     460             :         return 47;       // "mvfr0"
     461             :       case '1':  // 1 string to match.
     462             :         return 48;       // "mvfr1"
     463             :       case '2':  // 1 string to match.
     464             :         return 49;       // "mvfr2"
     465             :       }
     466             :       break;
     467             :     }
     468             :     break;
     469          43 :   case 6:        // 1 string to match.
     470          43 :     if (memcmp(Name.data()+0, "fpinst", 6) != 0)
     471             :       break;
     472             :     return 5;    // "fpinst"
     473          19 :   case 7:        // 2 strings to match.
     474          38 :     switch (Name[0]) {
     475             :     default: break;
     476           2 :     case 'f':    // 1 string to match.
     477           2 :       if (memcmp(Name.data()+1, "pinst2", 6) != 0)
     478             :         break;
     479             :       return 46;         // "fpinst2"
     480           2 :     case 'i':    // 1 string to match.
     481           2 :       if (memcmp(Name.data()+1, "tstate", 6) != 0)
     482             :         break;
     483             :       return 9;  // "itstate"
     484             :     }
     485             :     break;
     486          15 :   case 9:        // 1 string to match.
     487          15 :     if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0)
     488             :       break;
     489             :     return 2;    // "apsr_nzcv"
     490           8 :   case 10:       // 1 string to match.
     491           8 :     if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0)
     492             :       break;
     493             :     return 7;    // "fpscr_nzcv"
     494             :   }
     495             :   return 0;
     496             : }
     497             : 
     498             : #endif // GET_REGISTER_MATCHER
     499             : 
     500             : 
     501             : #ifdef GET_SUBTARGET_FEATURE_NAME
     502             : #undef GET_SUBTARGET_FEATURE_NAME
     503             : 
     504             : // User-level names for subtarget features that participate in
     505             : // instruction matching.
     506        2029 : static const char *getSubtargetFeatureName(uint64_t Val) {
     507        2029 :   switch(Val) {
     508             :   case Feature_HasV4T: return "armv4t";
     509           1 :   case Feature_HasV5T: return "armv5t";
     510           0 :   case Feature_HasV5TE: return "armv5te";
     511           0 :   case Feature_HasV6: return "armv6";
     512          12 :   case Feature_HasV6M: return "armv6m or armv6t2";
     513           8 :   case Feature_HasV8MBaseline: return "armv8m.base";
     514           2 :   case Feature_HasV8MMainline: return "armv8m.main";
     515           4 :   case Feature_HasV6T2: return "armv6t2";
     516           5 :   case Feature_HasV6K: return "armv6k";
     517           6 :   case Feature_HasV7: return "armv7";
     518         116 :   case Feature_HasV8: return "armv8";
     519           4 :   case Feature_PreV8: return "armv7 or earlier";
     520          36 :   case Feature_HasV8_1a: return "armv8.1a";
     521           0 :   case Feature_HasV8_2a: return "armv8.2a";
     522           2 :   case Feature_HasV8_3a: return "armv8.3a";
     523           0 :   case Feature_HasVFP2: return "VFP2";
     524           0 :   case Feature_HasVFP3: return "VFP3";
     525           0 :   case Feature_HasVFP4: return "VFP4";
     526          51 :   case Feature_HasDPVFP: return "double precision VFP";
     527         665 :   case Feature_HasFPARMv8: return "FPARMv8";
     528         250 :   case Feature_HasNEON: return "NEON";
     529         105 :   case Feature_HasCrypto: return "crypto";
     530          64 :   case Feature_HasDotProd: return "dotprod";
     531          42 :   case Feature_HasCRC: return "crc";
     532           0 :   case Feature_HasRAS: return "ras";
     533           4 :   case Feature_HasFP16: return "half-float conversions";
     534         370 :   case Feature_HasFullFP16: return "full half-float";
     535           5 :   case Feature_HasDivideInThumb: return "divide in THUMB";
     536          15 :   case Feature_HasDivideInARM: return "divide in ARM";
     537           0 :   case Feature_HasDSP: return "dsp";
     538           5 :   case Feature_HasDB: return "data-barriers";
     539           2 :   case Feature_HasV7Clrex: return "v7 clrex";
     540          28 :   case Feature_HasAcquireRelease: return "acquire/release";
     541          13 :   case Feature_HasMP: return "mp-extensions";
     542           0 :   case Feature_HasVirtualization: return "virtualization-extensions";
     543          11 :   case Feature_HasTrustZone: return "TrustZone";
     544           0 :   case Feature_Has8MSecExt: return "ARMv8-M Security Extensions";
     545           3 :   case Feature_IsThumb: return "thumb";
     546          56 :   case Feature_IsThumb2: return "thumb2";
     547           0 :   case Feature_IsMClass: return "armv*m";
     548          20 :   case Feature_IsNotMClass: return "!armv*m";
     549          86 :   case Feature_IsARM: return "arm-mode";
     550           0 :   case Feature_UseNaClTrap: return "NaCl";
     551          38 :   case Feature_UseNegativeImmediates: return "NegativeImmediates";
     552           0 :   default: return "(unknown)";
     553             :   }
     554             : }
     555             : 
     556             : #endif // GET_SUBTARGET_FEATURE_NAME
     557             : 
     558             : 
     559             : #ifdef GET_MATCHER_IMPLEMENTATION
     560             : #undef GET_MATCHER_IMPLEMENTATION
     561             : 
     562       48256 : static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
     563             :   switch (VariantID) {
     564             :     case 0:
     565             :     break;
     566             :   }
     567       48256 :   switch (Mnemonic.size()) {
     568             :   default: break;
     569       12839 :   case 3:        // 4 strings to match.
     570       25678 :     switch (Mnemonic[0]) {
     571             :     default: break;
     572         624 :     case 'r':    // 1 string to match.
     573         624 :       if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
     574             :         break;
     575           4 :       Mnemonic = "rfeia";      // "rfe"
     576             :       return;
     577        1708 :     case 's':    // 3 strings to match.
     578        3416 :       switch (Mnemonic[1]) {
     579             :       default: break;
     580          39 :       case 'm':  // 1 string to match.
     581          78 :         if (Mnemonic[2] != 'i')
     582             :           break;
     583           3 :         Mnemonic = "smc";      // "smi"
     584             :         return;
     585          16 :       case 'r':  // 1 string to match.
     586          32 :         if (Mnemonic[2] != 's')
     587             :           break;
     588          16 :         Mnemonic = "srsia";    // "srs"
     589             :         return;
     590          18 :       case 'w':  // 1 string to match.
     591          36 :         if (Mnemonic[2] != 'i')
     592             :           break;
     593           2 :         Mnemonic = "svc";      // "swi"
     594             :         return;
     595             :       }
     596             :       break;
     597             :     }
     598             :     break;
     599       10181 :   case 4:        // 10 strings to match.
     600       20362 :     switch (Mnemonic[0]) {
     601             :     default: break;
     602           9 :     case 'f':    // 8 strings to match.
     603          18 :       switch (Mnemonic[1]) {
     604             :       default: break;
     605           0 :       case 'l':  // 2 strings to match.
     606           0 :         if (Mnemonic[2] != 'd')
     607             :           break;
     608           0 :         switch (Mnemonic[3]) {
     609             :         default: break;
     610           0 :         case 'd':        // 1 string to match.
     611           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldd"
     612           0 :             Mnemonic = "vldr";
     613             :           return;
     614           0 :         case 's':        // 1 string to match.
     615           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "flds"
     616           0 :             Mnemonic = "vldr";
     617             :           return;
     618             :         }
     619             :         break;
     620           0 :       case 'm':  // 4 strings to match.
     621           0 :         switch (Mnemonic[2]) {
     622             :         default: break;
     623           0 :         case 'r':        // 2 strings to match.
     624           0 :           switch (Mnemonic[3]) {
     625             :           default: break;
     626           0 :           case 's':      // 1 string to match.
     627           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fmrs"
     628           0 :               Mnemonic = "vmov";
     629             :             return;
     630           0 :           case 'x':      // 1 string to match.
     631           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fmrx"
     632           0 :               Mnemonic = "vmrs";
     633             :             return;
     634             :           }
     635             :           break;
     636           0 :         case 's':        // 1 string to match.
     637           0 :           if (Mnemonic[3] != 'r')
     638             :             break;
     639           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fmsr"
     640           0 :             Mnemonic = "vmov";
     641             :           return;
     642           0 :         case 'x':        // 1 string to match.
     643           0 :           if (Mnemonic[3] != 'r')
     644             :             break;
     645           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fmxr"
     646           0 :             Mnemonic = "vmsr";
     647             :           return;
     648             :         }
     649             :         break;
     650           0 :       case 's':  // 2 strings to match.
     651           0 :         if (Mnemonic[2] != 't')
     652             :           break;
     653           0 :         switch (Mnemonic[3]) {
     654             :         default: break;
     655           0 :         case 'd':        // 1 string to match.
     656           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstd"
     657           0 :             Mnemonic = "vstr";
     658             :           return;
     659           0 :         case 's':        // 1 string to match.
     660           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fsts"
     661           0 :             Mnemonic = "vstr";
     662             :           return;
     663             :         }
     664             :         break;
     665             :       }
     666             :       break;
     667        5021 :     case 'v':    // 2 strings to match.
     668       10042 :       switch (Mnemonic[1]) {
     669             :       default: break;
     670        1743 :       case 'l':  // 1 string to match.
     671        1743 :         if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
     672             :           break;
     673           1 :         Mnemonic = "vldmia";   // "vldm"
     674             :         return;
     675        1482 :       case 's':  // 1 string to match.
     676        1482 :         if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
     677             :           break;
     678           1 :         Mnemonic = "vstmia";   // "vstm"
     679             :         return;
     680             :       }
     681             :       break;
     682             :     }
     683             :     break;
     684        5529 :   case 5:        // 51 strings to match.
     685       11058 :     switch (Mnemonic[0]) {
     686             :     default: break;
     687           0 :     case 'f':    // 18 strings to match.
     688           0 :       switch (Mnemonic[1]) {
     689             :       default: break;
     690           0 :       case 'a':  // 2 strings to match.
     691           0 :         if (memcmp(Mnemonic.data()+2, "dd", 2) != 0)
     692             :           break;
     693           0 :         switch (Mnemonic[4]) {
     694             :         default: break;
     695           0 :         case 'd':        // 1 string to match.
     696           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "faddd"
     697           0 :             Mnemonic = "vadd.f64";
     698             :           return;
     699           0 :         case 's':        // 1 string to match.
     700           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fadds"
     701           0 :             Mnemonic = "vadd.f32";
     702             :           return;
     703             :         }
     704             :         break;
     705           0 :       case 'c':  // 4 strings to match.
     706           0 :         switch (Mnemonic[2]) {
     707             :         default: break;
     708           0 :         case 'm':        // 2 strings to match.
     709           0 :           if (Mnemonic[3] != 'p')
     710             :             break;
     711           0 :           switch (Mnemonic[4]) {
     712             :           default: break;
     713           0 :           case 'd':      // 1 string to match.
     714           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fcmpd"
     715           0 :               Mnemonic = "vcmp.f64";
     716             :             return;
     717           0 :           case 's':      // 1 string to match.
     718           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fcmps"
     719           0 :               Mnemonic = "vcmp.f32";
     720             :             return;
     721             :           }
     722             :           break;
     723           0 :         case 'p':        // 2 strings to match.
     724           0 :           if (Mnemonic[3] != 'y')
     725             :             break;
     726           0 :           switch (Mnemonic[4]) {
     727             :           default: break;
     728           0 :           case 'd':      // 1 string to match.
     729           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fcpyd"
     730           0 :               Mnemonic = "vmov.f64";
     731             :             return;
     732           0 :           case 's':      // 1 string to match.
     733           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fcpys"
     734           0 :               Mnemonic = "vmov.f32";
     735             :             return;
     736             :           }
     737             :           break;
     738             :         }
     739             :         break;
     740           0 :       case 'd':  // 2 strings to match.
     741           0 :         if (memcmp(Mnemonic.data()+2, "iv", 2) != 0)
     742             :           break;
     743           0 :         switch (Mnemonic[4]) {
     744             :         default: break;
     745           0 :         case 'd':        // 1 string to match.
     746           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fdivd"
     747           0 :             Mnemonic = "vdiv.f64";
     748             :           return;
     749           0 :         case 's':        // 1 string to match.
     750           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fdivs"
     751           0 :             Mnemonic = "vdiv.f32";
     752             :           return;
     753             :         }
     754             :         break;
     755           0 :       case 'm':  // 8 strings to match.
     756           0 :         switch (Mnemonic[2]) {
     757             :         default: break;
     758           0 :         case 'a':        // 2 strings to match.
     759           0 :           if (Mnemonic[3] != 'c')
     760             :             break;
     761           0 :           switch (Mnemonic[4]) {
     762             :           default: break;
     763           0 :           case 'd':      // 1 string to match.
     764           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fmacd"
     765           0 :               Mnemonic = "vmla.f64";
     766             :             return;
     767           0 :           case 's':      // 1 string to match.
     768           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fmacs"
     769           0 :               Mnemonic = "vmla.f32";
     770             :             return;
     771             :           }
     772             :           break;
     773           0 :         case 'd':        // 1 string to match.
     774           0 :           if (memcmp(Mnemonic.data()+3, "rr", 2) != 0)
     775             :             break;
     776           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fmdrr"
     777           0 :             Mnemonic = "vmov";
     778             :           return;
     779           0 :         case 'r':        // 3 strings to match.
     780           0 :           switch (Mnemonic[3]) {
     781             :           default: break;
     782           0 :           case 'd':      // 2 strings to match.
     783           0 :             switch (Mnemonic[4]) {
     784             :             default: break;
     785           0 :             case 'd':    // 1 string to match.
     786           0 :               if ((Features & Feature_HasVFP2) == Feature_HasVFP2)   // "fmrdd"
     787           0 :                 Mnemonic = "vmov";
     788             :               return;
     789           0 :             case 's':    // 1 string to match.
     790           0 :               if ((Features & Feature_HasVFP2) == Feature_HasVFP2)   // "fmrds"
     791           0 :                 Mnemonic = "vmov";
     792             :               return;
     793             :             }
     794             :             break;
     795           0 :           case 'r':      // 1 string to match.
     796           0 :             if (Mnemonic[4] != 'd')
     797             :               break;
     798           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fmrrd"
     799           0 :               Mnemonic = "vmov";
     800             :             return;
     801             :           }
     802             :           break;
     803           0 :         case 'u':        // 2 strings to match.
     804           0 :           if (Mnemonic[3] != 'l')
     805             :             break;
     806           0 :           switch (Mnemonic[4]) {
     807             :           default: break;
     808           0 :           case 'd':      // 1 string to match.
     809           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fmuld"
     810           0 :               Mnemonic = "vmul.f64";
     811             :             return;
     812           0 :           case 's':      // 1 string to match.
     813           0 :             if ((Features & Feature_HasVFP2) == Feature_HasVFP2)     // "fmuls"
     814           0 :               Mnemonic = "vmul.f32";
     815             :             return;
     816             :           }
     817             :           break;
     818             :         }
     819             :         break;
     820           0 :       case 'n':  // 2 strings to match.
     821           0 :         if (memcmp(Mnemonic.data()+2, "eg", 2) != 0)
     822             :           break;
     823           0 :         switch (Mnemonic[4]) {
     824             :         default: break;
     825           0 :         case 'd':        // 1 string to match.
     826           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fnegd"
     827           0 :             Mnemonic = "vneg.f64";
     828             :           return;
     829           0 :         case 's':        // 1 string to match.
     830           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fnegs"
     831           0 :             Mnemonic = "vneg.f32";
     832             :           return;
     833             :         }
     834             :         break;
     835             :       }
     836             :       break;
     837         963 :     case 'l':    // 3 strings to match.
     838         963 :       if (memcmp(Mnemonic.data()+1, "dm", 2) != 0)
     839             :         break;
     840         422 :       switch (Mnemonic[3]) {
     841             :       default: break;
     842          15 :       case 'e':  // 1 string to match.
     843          30 :         if (Mnemonic[4] != 'a')
     844             :           break;
     845           2 :         Mnemonic = "ldmdb";    // "ldmea"
     846             :         return;
     847          13 :       case 'f':  // 1 string to match.
     848          26 :         if (Mnemonic[4] != 'd')
     849             :           break;
     850          13 :         Mnemonic = "ldm";      // "ldmfd"
     851             :         return;
     852          52 :       case 'i':  // 1 string to match.
     853         104 :         if (Mnemonic[4] != 'a')
     854             :           break;
     855          28 :         Mnemonic = "ldm";      // "ldmia"
     856             :         return;
     857             :       }
     858             :       break;
     859         207 :     case 'r':    // 4 strings to match.
     860         207 :       if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
     861             :         break;
     862         156 :       switch (Mnemonic[3]) {
     863             :       default: break;
     864           8 :       case 'e':  // 2 strings to match.
     865          16 :         switch (Mnemonic[4]) {
     866             :         default: break;
     867           4 :         case 'a':        // 1 string to match.
     868           4 :           Mnemonic = "rfedb";  // "rfeea"
     869             :           return;
     870           4 :         case 'd':        // 1 string to match.
     871           4 :           Mnemonic = "rfeib";  // "rfeed"
     872             :           return;
     873             :         }
     874             :         break;
     875           8 :       case 'f':  // 2 strings to match.
     876          16 :         switch (Mnemonic[4]) {
     877             :         default: break;
     878           4 :         case 'a':        // 1 string to match.
     879           4 :           Mnemonic = "rfeda";  // "rfefa"
     880             :           return;
     881           4 :         case 'd':        // 1 string to match.
     882           4 :           Mnemonic = "rfeia";  // "rfefd"
     883             :           return;
     884             :         }
     885             :         break;
     886             :       }
     887             :       break;
     888        1212 :     case 's':    // 7 strings to match.
     889        2424 :       switch (Mnemonic[1]) {
     890             :       default: break;
     891         210 :       case 'r':  // 4 strings to match.
     892         420 :         if (Mnemonic[2] != 's')
     893             :           break;
     894         420 :         switch (Mnemonic[3]) {
     895             :         default: break;
     896          24 :         case 'e':        // 2 strings to match.
     897          48 :           switch (Mnemonic[4]) {
     898             :           default: break;
     899          16 :           case 'a':      // 1 string to match.
     900          16 :             Mnemonic = "srsia";        // "srsea"
     901             :             return;
     902           8 :           case 'd':      // 1 string to match.
     903           8 :             Mnemonic = "srsda";        // "srsed"
     904             :             return;
     905             :           }
     906             :           break;
     907          24 :         case 'f':        // 2 strings to match.
     908          48 :           switch (Mnemonic[4]) {
     909             :           default: break;
     910           8 :           case 'a':      // 1 string to match.
     911           8 :             Mnemonic = "srsib";        // "srsfa"
     912             :             return;
     913          16 :           case 'd':      // 1 string to match.
     914          16 :             Mnemonic = "srsdb";        // "srsfd"
     915             :             return;
     916             :           }
     917             :           break;
     918             :         }
     919             :         break;
     920         520 :       case 't':  // 3 strings to match.
     921        1040 :         if (Mnemonic[2] != 'm')
     922             :           break;
     923         404 :         switch (Mnemonic[3]) {
     924             :         default: break;
     925           4 :         case 'e':        // 1 string to match.
     926           8 :           if (Mnemonic[4] != 'a')
     927             :             break;
     928           4 :           Mnemonic = "stm";    // "stmea"
     929             :           return;
     930           4 :         case 'f':        // 1 string to match.
     931           8 :           if (Mnemonic[4] != 'd')
     932             :             break;
     933           4 :           Mnemonic = "stmdb";  // "stmfd"
     934             :           return;
     935          50 :         case 'i':        // 1 string to match.
     936         100 :           if (Mnemonic[4] != 'a')
     937             :             break;
     938          18 :           Mnemonic = "stm";    // "stmia"
     939             :           return;
     940             :         }
     941             :         break;
     942             :       }
     943             :       break;
     944        1466 :     case 'v':    // 19 strings to match.
     945        2932 :       switch (Mnemonic[1]) {
     946             :       default: break;
     947         118 :       case 'a':  // 3 strings to match.
     948         236 :         switch (Mnemonic[2]) {
     949             :         default: break;
     950          24 :         case 'b':        // 1 string to match.
     951          24 :           if (memcmp(Mnemonic.data()+3, "sq", 2) != 0)
     952             :             break;
     953           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vabsq"
     954           0 :             Mnemonic = "vabs";
     955             :           return;
     956          30 :         case 'd':        // 1 string to match.
     957          30 :           if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
     958             :             break;
     959           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vaddq"
     960           0 :             Mnemonic = "vadd";
     961             :           return;
     962           0 :         case 'n':        // 1 string to match.
     963           0 :           if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
     964             :             break;
     965           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vandq"
     966           0 :             Mnemonic = "vand";
     967             :           return;
     968             :         }
     969             :         break;
     970           0 :       case 'b':  // 1 string to match.
     971           0 :         if (memcmp(Mnemonic.data()+2, "icq", 3) != 0)
     972             :           break;
     973           0 :         if ((Features & Feature_HasNEON) == Feature_HasNEON)         // "vbicq"
     974           0 :           Mnemonic = "vbic";
     975             :         return;
     976         550 :       case 'c':  // 3 strings to match.
     977        1100 :         switch (Mnemonic[2]) {
     978             :         default: break;
     979           0 :         case 'e':        // 1 string to match.
     980           0 :           if (memcmp(Mnemonic.data()+3, "qq", 2) != 0)
     981             :             break;
     982           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vceqq"
     983           0 :             Mnemonic = "vceq";
     984             :           return;
     985           0 :         case 'l':        // 1 string to match.
     986           0 :           if (memcmp(Mnemonic.data()+3, "eq", 2) != 0)
     987             :             break;
     988           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vcleq"
     989           0 :             Mnemonic = "vcle";
     990             :           return;
     991         536 :         case 'v':        // 1 string to match.
     992         536 :           if (memcmp(Mnemonic.data()+3, "tq", 2) != 0)
     993             :             break;
     994           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vcvtq"
     995           0 :             Mnemonic = "vcvt";
     996             :           return;
     997             :         }
     998             :         break;
     999           0 :       case 'e':  // 1 string to match.
    1000           0 :         if (memcmp(Mnemonic.data()+2, "orq", 3) != 0)
    1001             :           break;
    1002           0 :         if ((Features & Feature_HasNEON) == Feature_HasNEON)         // "veorq"
    1003           0 :           Mnemonic = "veor";
    1004             :         return;
    1005          75 :       case 'm':  // 5 strings to match.
    1006         150 :         switch (Mnemonic[2]) {
    1007             :         default: break;
    1008           0 :         case 'a':        // 1 string to match.
    1009           0 :           if (memcmp(Mnemonic.data()+3, "xq", 2) != 0)
    1010             :             break;
    1011           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vmaxq"
    1012           0 :             Mnemonic = "vmax";
    1013             :           return;
    1014           0 :         case 'i':        // 1 string to match.
    1015           0 :           if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
    1016             :             break;
    1017           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vminq"
    1018           0 :             Mnemonic = "vmin";
    1019             :           return;
    1020          22 :         case 'o':        // 1 string to match.
    1021          22 :           if (memcmp(Mnemonic.data()+3, "vq", 2) != 0)
    1022             :             break;
    1023           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vmovq"
    1024           0 :             Mnemonic = "vmov";
    1025             :           return;
    1026          27 :         case 'u':        // 1 string to match.
    1027          27 :           if (memcmp(Mnemonic.data()+3, "lq", 2) != 0)
    1028             :             break;
    1029           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vmulq"
    1030           0 :             Mnemonic = "vmul";
    1031             :           return;
    1032           0 :         case 'v':        // 1 string to match.
    1033           0 :           if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
    1034             :             break;
    1035           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vmvnq"
    1036           0 :             Mnemonic = "vmvn";
    1037             :           return;
    1038             :         }
    1039             :         break;
    1040           0 :       case 'o':  // 1 string to match.
    1041           0 :         if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0)
    1042             :           break;
    1043           0 :         if ((Features & Feature_HasNEON) == Feature_HasNEON)         // "vorrq"
    1044           0 :           Mnemonic = "vorr";
    1045             :         return;
    1046         113 :       case 's':  // 4 strings to match.
    1047         226 :         switch (Mnemonic[2]) {
    1048             :         default: break;
    1049          24 :         case 'h':        // 2 strings to match.
    1050          48 :           switch (Mnemonic[3]) {
    1051             :           default: break;
    1052          18 :           case 'l':      // 1 string to match.
    1053          36 :             if (Mnemonic[4] != 'q')
    1054             :               break;
    1055           0 :             if ((Features & Feature_HasNEON) == Feature_HasNEON)     // "vshlq"
    1056           0 :               Mnemonic = "vshl";
    1057             :             return;
    1058           6 :           case 'r':      // 1 string to match.
    1059          12 :             if (Mnemonic[4] != 'q')
    1060             :               break;
    1061           0 :             if ((Features & Feature_HasNEON) == Feature_HasNEON)     // "vshrq"
    1062           0 :               Mnemonic = "vshr";
    1063             :             return;
    1064             :           }
    1065             :           break;
    1066          18 :         case 'u':        // 1 string to match.
    1067          18 :           if (memcmp(Mnemonic.data()+3, "bq", 2) != 0)
    1068             :             break;
    1069           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vsubq"
    1070           0 :             Mnemonic = "vsub";
    1071             :           return;
    1072           0 :         case 'w':        // 1 string to match.
    1073           0 :           if (memcmp(Mnemonic.data()+3, "pq", 2) != 0)
    1074             :             break;
    1075           0 :           if ((Features & Feature_HasNEON) == Feature_HasNEON)       // "vswpq"
    1076           0 :             Mnemonic = "vswp";
    1077             :           return;
    1078             :         }
    1079             :         break;
    1080           0 :       case 'z':  // 1 string to match.
    1081           0 :         if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0)
    1082             :           break;
    1083           0 :         if ((Features & Feature_HasNEON) == Feature_HasNEON)         // "vzipq"
    1084           0 :           Mnemonic = "vzip";
    1085             :         return;
    1086             :       }
    1087             :       break;
    1088             :     }
    1089             :     break;
    1090        4164 :   case 6:        // 10 strings to match.
    1091        8328 :     if (Mnemonic[0] != 'f')
    1092             :       break;
    1093           8 :     switch (Mnemonic[1]) {
    1094             :     default: break;
    1095           2 :     case 's':    // 4 strings to match.
    1096           4 :       switch (Mnemonic[2]) {
    1097             :       default: break;
    1098           0 :       case 'i':  // 2 strings to match.
    1099           0 :         if (memcmp(Mnemonic.data()+3, "to", 2) != 0)
    1100             :           break;
    1101           0 :         switch (Mnemonic[5]) {
    1102             :         default: break;
    1103           0 :         case 'd':        // 1 string to match.
    1104           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fsitod"
    1105           0 :             Mnemonic = "vcvt.f64.s32";
    1106             :           return;
    1107           0 :         case 's':        // 1 string to match.
    1108           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fsitos"
    1109           0 :             Mnemonic = "vcvt.f32.s32";
    1110             :           return;
    1111             :         }
    1112             :         break;
    1113           2 :       case 'q':  // 2 strings to match.
    1114           2 :         if (memcmp(Mnemonic.data()+3, "rt", 2) != 0)
    1115             :           break;
    1116           4 :         switch (Mnemonic[5]) {
    1117             :         default: break;
    1118           1 :         case 'd':        // 1 string to match.
    1119           1 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fsqrtd"
    1120           1 :             Mnemonic = "vsqrt";
    1121             :           return;
    1122           1 :         case 's':        // 1 string to match.
    1123           1 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fsqrts"
    1124           1 :             Mnemonic = "vsqrt";
    1125             :           return;
    1126             :         }
    1127             :         break;
    1128             :       }
    1129             :       break;
    1130           0 :     case 't':    // 4 strings to match.
    1131           0 :       if (Mnemonic[2] != 'o')
    1132             :         break;
    1133           0 :       switch (Mnemonic[3]) {
    1134             :       default: break;
    1135           0 :       case 's':  // 2 strings to match.
    1136           0 :         if (Mnemonic[4] != 'i')
    1137             :           break;
    1138           0 :         switch (Mnemonic[5]) {
    1139             :         default: break;
    1140           0 :         case 'd':        // 1 string to match.
    1141           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "ftosid"
    1142           0 :             Mnemonic = "vcvtr.s32.f64";
    1143             :           return;
    1144           0 :         case 's':        // 1 string to match.
    1145           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "ftosis"
    1146           0 :             Mnemonic = "vcvtr.s32.f32";
    1147             :           return;
    1148             :         }
    1149             :         break;
    1150           0 :       case 'u':  // 2 strings to match.
    1151           0 :         if (Mnemonic[4] != 'i')
    1152             :           break;
    1153           0 :         switch (Mnemonic[5]) {
    1154             :         default: break;
    1155           0 :         case 'd':        // 1 string to match.
    1156           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "ftouid"
    1157           0 :             Mnemonic = "vcvtr.u32.f64";
    1158             :           return;
    1159           0 :         case 's':        // 1 string to match.
    1160           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "ftouis"
    1161           0 :             Mnemonic = "vcvtr.u32.f32";
    1162             :           return;
    1163             :         }
    1164             :         break;
    1165             :       }
    1166             :       break;
    1167           0 :     case 'u':    // 2 strings to match.
    1168           0 :       if (memcmp(Mnemonic.data()+2, "ito", 3) != 0)
    1169             :         break;
    1170           0 :       switch (Mnemonic[5]) {
    1171             :       default: break;
    1172           0 :       case 'd':  // 1 string to match.
    1173           0 :         if ((Features & Feature_HasVFP2) == Feature_HasVFP2)         // "fuitod"
    1174           0 :           Mnemonic = "vcvt.f64.u32";
    1175             :         return;
    1176           0 :       case 's':  // 1 string to match.
    1177           0 :         if ((Features & Feature_HasVFP2) == Feature_HasVFP2)         // "fuitos"
    1178           0 :           Mnemonic = "vcvt.f32.u32";
    1179             :         return;
    1180             :       }
    1181             :       break;
    1182             :     }
    1183             :     break;
    1184        3495 :   case 7:        // 24 strings to match.
    1185        6990 :     if (Mnemonic[0] != 'f')
    1186             :       break;
    1187         142 :     switch (Mnemonic[1]) {
    1188             :     default: break;
    1189          26 :     case 'l':    // 10 strings to match.
    1190          26 :       if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
    1191             :         break;
    1192          52 :       switch (Mnemonic[4]) {
    1193             :       default: break;
    1194           6 :       case 'd':  // 2 strings to match.
    1195          12 :         if (Mnemonic[5] != 'b')
    1196             :           break;
    1197          12 :         switch (Mnemonic[6]) {
    1198             :         default: break;
    1199           2 :         case 'd':        // 1 string to match.
    1200           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmdbd"
    1201           2 :             Mnemonic = "vldmdb";
    1202             :           return;
    1203           2 :         case 's':        // 1 string to match.
    1204           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmdbs"
    1205           2 :             Mnemonic = "vldmdb";
    1206             :           return;
    1207             :         }
    1208             :         break;
    1209           6 :       case 'e':  // 3 strings to match.
    1210          12 :         if (Mnemonic[5] != 'a')
    1211             :           break;
    1212          12 :         switch (Mnemonic[6]) {
    1213             :         default: break;
    1214           2 :         case 'd':        // 1 string to match.
    1215           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmead"
    1216           2 :             Mnemonic = "vldmdb";
    1217             :           return;
    1218           2 :         case 's':        // 1 string to match.
    1219           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmeas"
    1220           2 :             Mnemonic = "vldmdb";
    1221             :           return;
    1222           2 :         case 'x':        // 1 string to match.
    1223           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmeax"
    1224           2 :             Mnemonic = "fldmdbx";
    1225             :           return;
    1226             :         }
    1227             :         break;
    1228           6 :       case 'f':  // 3 strings to match.
    1229          12 :         if (Mnemonic[5] != 'd')
    1230             :           break;
    1231          12 :         switch (Mnemonic[6]) {
    1232             :         default: break;
    1233           2 :         case 'd':        // 1 string to match.
    1234           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmfdd"
    1235           2 :             Mnemonic = "vldmia";
    1236             :           return;
    1237           2 :         case 's':        // 1 string to match.
    1238           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmfds"
    1239           2 :             Mnemonic = "vldmia";
    1240             :           return;
    1241           2 :         case 'x':        // 1 string to match.
    1242           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmfdx"
    1243           2 :             Mnemonic = "fldmiax";
    1244             :           return;
    1245             :         }
    1246             :         break;
    1247           8 :       case 'i':  // 2 strings to match.
    1248          16 :         if (Mnemonic[5] != 'a')
    1249             :           break;
    1250          16 :         switch (Mnemonic[6]) {
    1251             :         default: break;
    1252           2 :         case 'd':        // 1 string to match.
    1253           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmiad"
    1254           2 :             Mnemonic = "vldmia";
    1255             :           return;
    1256           2 :         case 's':        // 1 string to match.
    1257           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fldmias"
    1258           2 :             Mnemonic = "vldmia";
    1259             :           return;
    1260             :         }
    1261             :         break;
    1262             :       }
    1263             :       break;
    1264          31 :     case 's':    // 10 strings to match.
    1265          31 :       if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
    1266             :         break;
    1267          62 :       switch (Mnemonic[4]) {
    1268             :       default: break;
    1269           6 :       case 'd':  // 2 strings to match.
    1270          12 :         if (Mnemonic[5] != 'b')
    1271             :           break;
    1272          12 :         switch (Mnemonic[6]) {
    1273             :         default: break;
    1274           2 :         case 'd':        // 1 string to match.
    1275           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmdbd"
    1276           2 :             Mnemonic = "vstmdb";
    1277             :           return;
    1278           2 :         case 's':        // 1 string to match.
    1279           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmdbs"
    1280           2 :             Mnemonic = "vstmdb";
    1281             :           return;
    1282             :         }
    1283             :         break;
    1284           6 :       case 'e':  // 3 strings to match.
    1285          12 :         if (Mnemonic[5] != 'a')
    1286             :           break;
    1287          12 :         switch (Mnemonic[6]) {
    1288             :         default: break;
    1289           2 :         case 'd':        // 1 string to match.
    1290           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmead"
    1291           2 :             Mnemonic = "vstmia";
    1292             :           return;
    1293           2 :         case 's':        // 1 string to match.
    1294           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmeas"
    1295           2 :             Mnemonic = "vstmia";
    1296             :           return;
    1297           2 :         case 'x':        // 1 string to match.
    1298           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmeax"
    1299           2 :             Mnemonic = "fstmiax";
    1300             :           return;
    1301             :         }
    1302             :         break;
    1303           7 :       case 'f':  // 3 strings to match.
    1304          14 :         if (Mnemonic[5] != 'd')
    1305             :           break;
    1306          14 :         switch (Mnemonic[6]) {
    1307             :         default: break;
    1308           3 :         case 'd':        // 1 string to match.
    1309           3 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmfdd"
    1310           3 :             Mnemonic = "vstmdb";
    1311             :           return;
    1312           2 :         case 's':        // 1 string to match.
    1313           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmfds"
    1314           2 :             Mnemonic = "vstmdb";
    1315             :           return;
    1316           2 :         case 'x':        // 1 string to match.
    1317           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmfdx"
    1318           2 :             Mnemonic = "fstmdbx";
    1319             :           return;
    1320             :         }
    1321             :         break;
    1322          12 :       case 'i':  // 2 strings to match.
    1323          24 :         if (Mnemonic[5] != 'a')
    1324             :           break;
    1325          24 :         switch (Mnemonic[6]) {
    1326             :         default: break;
    1327           2 :         case 'd':        // 1 string to match.
    1328           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmiad"
    1329           2 :             Mnemonic = "vstmia";
    1330             :           return;
    1331           2 :         case 's':        // 1 string to match.
    1332           2 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "fstmias"
    1333           2 :             Mnemonic = "vstmia";
    1334             :           return;
    1335             :         }
    1336             :         break;
    1337             :       }
    1338             :       break;
    1339           0 :     case 't':    // 4 strings to match.
    1340           0 :       if (Mnemonic[2] != 'o')
    1341             :         break;
    1342           0 :       switch (Mnemonic[3]) {
    1343             :       default: break;
    1344           0 :       case 's':  // 2 strings to match.
    1345           0 :         if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
    1346             :           break;
    1347           0 :         switch (Mnemonic[6]) {
    1348             :         default: break;
    1349           0 :         case 'd':        // 1 string to match.
    1350           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "ftosizd"
    1351           0 :             Mnemonic = "vcvt.s32.f64";
    1352             :           return;
    1353           0 :         case 's':        // 1 string to match.
    1354           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "ftosizs"
    1355           0 :             Mnemonic = "vcvt.s32.f32";
    1356             :           return;
    1357             :         }
    1358             :         break;
    1359           0 :       case 'u':  // 2 strings to match.
    1360           0 :         if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
    1361             :           break;
    1362           0 :         switch (Mnemonic[6]) {
    1363             :         default: break;
    1364           0 :         case 'd':        // 1 string to match.
    1365           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "ftouizd"
    1366           0 :             Mnemonic = "vcvt.u32.f64";
    1367             :           return;
    1368           0 :         case 's':        // 1 string to match.
    1369           0 :           if ((Features & Feature_HasVFP2) == Feature_HasVFP2)       // "ftouizs"
    1370           0 :             Mnemonic = "vcvt.u32.f32";
    1371             :           return;
    1372             :         }
    1373             :         break;
    1374             :       }
    1375             :       break;
    1376             :     }
    1377             :     break;
    1378        2276 :   case 8:        // 5 strings to match.
    1379        4552 :     switch (Mnemonic[0]) {
    1380             :     default: break;
    1381           8 :     case 'q':    // 1 string to match.
    1382           8 :       if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0)
    1383             :         break;
    1384           0 :       Mnemonic = "qsax";       // "qsubaddx"
    1385             :       return;
    1386         308 :     case 's':    // 2 strings to match.
    1387         616 :       switch (Mnemonic[1]) {
    1388             :       default: break;
    1389          10 :       case 'a':  // 1 string to match.
    1390          10 :         if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
    1391             :           break;
    1392           4 :         Mnemonic = "sasx";     // "saddsubx"
    1393             :         return;
    1394           8 :       case 's':  // 1 string to match.
    1395           8 :         if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
    1396             :           break;
    1397           4 :         Mnemonic = "ssax";     // "ssubaddx"
    1398             :         return;
    1399             :       }
    1400             :       break;
    1401          49 :     case 'u':    // 2 strings to match.
    1402          98 :       switch (Mnemonic[1]) {
    1403             :       default: break;
    1404           8 :       case 'a':  // 1 string to match.
    1405           8 :         if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
    1406             :           break;
    1407           4 :         Mnemonic = "uasx";     // "uaddsubx"
    1408             :         return;
    1409          12 :       case 's':  // 1 string to match.
    1410          12 :         if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
    1411             :           break;
    1412           4 :         Mnemonic = "usax";     // "usubaddx"
    1413             :         return;
    1414             :       }
    1415             :       break;
    1416             :     }
    1417             :     break;
    1418         817 :   case 9:        // 8 strings to match.
    1419        1634 :     switch (Mnemonic[0]) {
    1420             :     default: break;
    1421          70 :     case 's':    // 2 strings to match.
    1422         140 :       if (Mnemonic[1] != 'h')
    1423             :         break;
    1424          76 :       switch (Mnemonic[2]) {
    1425             :       default: break;
    1426          30 :       case 'a':  // 1 string to match.
    1427          30 :         if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
    1428             :           break;
    1429           4 :         Mnemonic = "shasx";    // "shaddsubx"
    1430             :         return;
    1431           8 :       case 's':  // 1 string to match.
    1432           8 :         if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
    1433             :           break;
    1434           4 :         Mnemonic = "shsax";    // "shsubaddx"
    1435             :         return;
    1436             :       }
    1437             :       break;
    1438          40 :     case 'u':    // 4 strings to match.
    1439          80 :       switch (Mnemonic[1]) {
    1440             :       default: break;
    1441          16 :       case 'h':  // 2 strings to match.
    1442          32 :         switch (Mnemonic[2]) {
    1443             :         default: break;
    1444           8 :         case 'a':        // 1 string to match.
    1445           8 :           if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
    1446             :             break;
    1447           4 :           Mnemonic = "uhasx";  // "uhaddsubx"
    1448             :           return;
    1449           8 :         case 's':        // 1 string to match.
    1450           8 :           if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
    1451             :             break;
    1452           4 :           Mnemonic = "uhsax";  // "uhsubaddx"
    1453             :           return;
    1454             :         }
    1455             :         break;
    1456          16 :       case 'q':  // 2 strings to match.
    1457          32 :         switch (Mnemonic[2]) {
    1458             :         default: break;
    1459           8 :         case 'a':        // 1 string to match.
    1460           8 :           if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
    1461             :             break;
    1462           4 :           Mnemonic = "uqasx";  // "uqaddsubx"
    1463             :           return;
    1464           8 :         case 's':        // 1 string to match.
    1465           8 :           if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
    1466             :             break;
    1467           4 :           Mnemonic = "uqsax";  // "uqsubaddx"
    1468             :           return;
    1469             :         }
    1470             :         break;
    1471             :       }
    1472             :       break;
    1473         620 :     case 'v':    // 2 strings to match.
    1474         620 :       if (memcmp(Mnemonic.data()+1, "movq.f", 6) != 0)
    1475             :         break;
    1476           0 :       switch (Mnemonic[7]) {
    1477             :       default: break;
    1478           0 :       case '3':  // 1 string to match.
    1479           0 :         if (Mnemonic[8] != '2')
    1480             :           break;
    1481           0 :         if ((Features & Feature_HasNEON) == Feature_HasNEON)         // "vmovq.f32"
    1482           0 :           Mnemonic = "vmov.f32";
    1483             :         return;
    1484           0 :       case '6':  // 1 string to match.
    1485           0 :         if (Mnemonic[8] != '4')
    1486             :           break;
    1487           0 :         if ((Features & Feature_HasNEON) == Feature_HasNEON)         // "vmovq.f64"
    1488           0 :           Mnemonic = "vmov.f64";
    1489             :         return;
    1490             :       }
    1491             :       break;
    1492             :     }
    1493             :     break;
    1494         153 :   case 11:       // 2 strings to match.
    1495         153 :     if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0)
    1496             :       break;
    1497           0 :     switch (Mnemonic[8]) {
    1498             :     default: break;
    1499           0 :     case 'f':    // 1 string to match.
    1500           0 :       if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
    1501             :         break;
    1502           0 :       if ((Features & Feature_HasNEON) == Feature_HasNEON)   // "vrecpeq.f32"
    1503           0 :         Mnemonic = "vrecpe.f32";
    1504             :       return;
    1505           0 :     case 'u':    // 1 string to match.
    1506           0 :       if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
    1507             :         break;
    1508           0 :       if ((Features & Feature_HasNEON) == Feature_HasNEON)   // "vrecpeq.u32"
    1509           0 :         Mnemonic = "vrecpe.u32";
    1510             :       return;
    1511             :     }
    1512             :     break;
    1513             :   }
    1514             : }
    1515             : 
    1516             : namespace {
    1517             : enum OperatorConversionKind {
    1518             :   CVT_Done,
    1519             :   CVT_Reg,
    1520             :   CVT_Tied,
    1521             :   CVT_95_Reg,
    1522             :   CVT_95_addCCOutOperands,
    1523             :   CVT_95_addCondCodeOperands,
    1524             :   CVT_95_addRegShiftedRegOperands,
    1525             :   CVT_95_addModImmOperands,
    1526             :   CVT_95_addModImmNotOperands,
    1527             :   CVT_95_addRegShiftedImmOperands,
    1528             :   CVT_95_addImmOperands,
    1529             :   CVT_95_addT2SOImmNotOperands,
    1530             :   CVT_95_addImm0_95_508s4Operands,
    1531             :   CVT_regSP,
    1532             :   CVT_95_addImm0_95_508s4NegOperands,
    1533             :   CVT_95_addImm0_95_4095NegOperands,
    1534             :   CVT_95_addThumbModImmNeg8_95_255Operands,
    1535             :   CVT_95_addT2SOImmNegOperands,
    1536             :   CVT_95_addModImmNegOperands,
    1537             :   CVT_95_addImm0_95_1020s4Operands,
    1538             :   CVT_95_addThumbModImmNeg1_95_7Operands,
    1539             :   CVT_95_addUnsignedOffset_95_b8s2Operands,
    1540             :   CVT_95_addAdrLabelOperands,
    1541             :   CVT_95_addARMBranchTargetOperands,
    1542             :   CVT_cvtThumbBranches,
    1543             :   CVT_95_addBitfieldOperands,
    1544             :   CVT_imm_95_0,
    1545             :   CVT_95_addThumbBranchTargetOperands,
    1546             :   CVT_95_addCoprocNumOperands,
    1547             :   CVT_95_addCoprocRegOperands,
    1548             :   CVT_95_addProcIFlagsOperands,
    1549             :   CVT_imm_95_15,
    1550             :   CVT_95_addMemBarrierOptOperands,
    1551             :   CVT_imm_95_16,
    1552             :   CVT_95_addFPImmOperands,
    1553             :   CVT_95_addDPRRegListOperands,
    1554             :   CVT_imm_95_1,
    1555             :   CVT_95_addInstSyncBarrierOptOperands,
    1556             :   CVT_95_addITCondCodeOperands,
    1557             :   CVT_95_addITMaskOperands,
    1558             :   CVT_95_addMemNoOffsetOperands,
    1559             :   CVT_95_addAddrMode5Operands,
    1560             :   CVT_95_addCoprocOptionOperands,
    1561             :   CVT_95_addPostIdxImm8s4Operands,
    1562             :   CVT_95_addRegListOperands,
    1563             :   CVT_95_addThumbMemPCOperands,
    1564             :   CVT_95_addConstPoolAsmImmOperands,
    1565             :   CVT_95_addMemThumbRIs4Operands,
    1566             :   CVT_95_addMemThumbRROperands,
    1567             :   CVT_95_addMemThumbSPIOperands,
    1568             :   CVT_95_addMemImm12OffsetOperands,
    1569             :   CVT_95_addMemNegImm8OffsetOperands,
    1570             :   CVT_95_addMemRegOffsetOperands,
    1571             :   CVT_95_addMemUImm12OffsetOperands,
    1572             :   CVT_95_addT2MemRegOffsetOperands,
    1573             :   CVT_95_addMemPCRelImm12Operands,
    1574             :   CVT_95_addMemImm8OffsetOperands,
    1575             :   CVT_95_addAM2OffsetImmOperands,
    1576             :   CVT_95_addPostIdxRegShiftedOperands,
    1577             :   CVT_95_addMemThumbRIs1Operands,
    1578             :   CVT_95_addMemPosImm8OffsetOperands,
    1579             :   CVT_95_addMemImm8s4OffsetOperands,
    1580             :   CVT_95_addAddrMode3Operands,
    1581             :   CVT_95_addAM3OffsetOperands,
    1582             :   CVT_95_addMemImm0_95_1020s4OffsetOperands,
    1583             :   CVT_95_addMemThumbRIs2Operands,
    1584             :   CVT_95_addPostIdxRegOperands,
    1585             :   CVT_95_addPostIdxImm8Operands,
    1586             :   CVT_reg0,
    1587             :   CVT_regCPSR,
    1588             :   CVT_imm_95_14,
    1589             :   CVT_95_addBankedRegOperands,
    1590             :   CVT_95_addMSRMaskOperands,
    1591             :   CVT_cvtThumbMultiply,
    1592             :   CVT_regR8,
    1593             :   CVT_regR0,
    1594             :   CVT_95_addPKHASRImmOperands,
    1595             :   CVT_95_addImm1_95_32Operands,
    1596             :   CVT_imm_95_4,
    1597             :   CVT_imm_95_5,
    1598             :   CVT_95_addShifterImmOperands,
    1599             :   CVT_95_addImm1_95_16Operands,
    1600             :   CVT_95_addRotImmOperands,
    1601             :   CVT_95_addMemTBBOperands,
    1602             :   CVT_95_addMemTBHOperands,
    1603             :   CVT_95_addNEONi16splatNotOperands,
    1604             :   CVT_95_addNEONi32splatNotOperands,
    1605             :   CVT_95_addNEONi16splatOperands,
    1606             :   CVT_95_addNEONi32splatOperands,
    1607             :   CVT_95_addFBits16Operands,
    1608             :   CVT_95_addFBits32Operands,
    1609             :   CVT_95_addVectorIndex16Operands,
    1610             :   CVT_95_addVectorIndex32Operands,
    1611             :   CVT_95_addVectorIndex8Operands,
    1612             :   CVT_95_addVecListOperands,
    1613             :   CVT_95_addDupAlignedMemory16Operands,
    1614             :   CVT_95_addAlignedMemory64or128Operands,
    1615             :   CVT_95_addAlignedMemory64or128or256Operands,
    1616             :   CVT_95_addAlignedMemory64Operands,
    1617             :   CVT_95_addVecListIndexedOperands,
    1618             :   CVT_95_addAlignedMemory16Operands,
    1619             :   CVT_95_addDupAlignedMemory32Operands,
    1620             :   CVT_95_addAlignedMemory32Operands,
    1621             :   CVT_95_addDupAlignedMemoryNoneOperands,
    1622             :   CVT_95_addAlignedMemoryNoneOperands,
    1623             :   CVT_95_addAlignedMemoryOperands,
    1624             :   CVT_95_addDupAlignedMemory64Operands,
    1625             :   CVT_95_addDupAlignedMemory64or128Operands,
    1626             :   CVT_95_addSPRRegListOperands,
    1627             :   CVT_95_addAddrMode5FP16Operands,
    1628             :   CVT_95_addNEONi32vmovOperands,
    1629             :   CVT_95_addNEONvmovByteReplicateOperands,
    1630             :   CVT_95_addNEONi32vmovNegOperands,
    1631             :   CVT_95_addNEONi64splatOperands,
    1632             :   CVT_95_addNEONi8splatOperands,
    1633             :   CVT_95_addNEONinvByteReplicateOperands,
    1634             :   CVT_imm_95_2,
    1635             :   CVT_imm_95_3,
    1636             :   CVT_NUM_CONVERTERS
    1637             : };
    1638             : 
    1639             : enum InstructionConversionKind {
    1640             :   Convert_NoOperands,
    1641             :   Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1,
    1642             :   Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
    1643             :   Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
    1644             :   Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
    1645             :   Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
    1646             :   Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
    1647             :   Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
    1648             :   Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
    1649             :   Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
    1650             :   Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
    1651             :   Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0,
    1652             :   Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0,
    1653             :   Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0,
    1654             :   Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
    1655             :   Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0,
    1656             :   Convert__Reg1_1__Tie0__Reg1_2__CondCode2_0,
    1657             :   Convert__Reg1_1__Tie0__Imm0_508s41_2__CondCode2_0,
    1658             :   Convert__regSP__Tie0__Imm0_508s4Neg1_2__CondCode2_0,
    1659             :   Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0,
    1660             :   Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0,
    1661             :   Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1,
    1662             :   Convert__Reg1_2__CCOut1_0__Tie0__Imm0_2551_3__CondCode2_1,
    1663             :   Convert__Reg1_2__CCOut1_0__Tie0__ThumbModImmNeg8_2551_3__CondCode2_1,
    1664             :   Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
    1665             :   Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0,
    1666             :   Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0,
    1667             :   Convert__regSP__Tie0__Imm0_508s41_3__CondCode2_0,
    1668             :   Convert__regSP__Tie0__Imm0_508s4Neg1_3__CondCode2_0,
    1669             :   Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0,
    1670             :   Convert__Reg1_1__Imm0_40951_3__CondCode2_0,
    1671             :   Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0,
    1672             :   Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0,
    1673             :   Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0,
    1674             :   Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
    1675             :   Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1,
    1676             :   Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1,
    1677             :   Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1,
    1678             :   Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
    1679             :   Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0,
    1680             :   Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0,
    1681             :   Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0,
    1682             :   Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0,
    1683             :   Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0,
    1684             :   Convert__Reg1_1__Imm1_2__CondCode2_0,
    1685             :   Convert__Reg1_1__AdrLabel1_2__CondCode2_0,
    1686             :   Convert__Reg1_2__Imm1_3__CondCode2_0,
    1687             :   Convert__Reg1_1__Tie0__Reg1_2,
    1688             :   Convert__Reg1_1__Reg1_2,
    1689             :   Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
    1690             :   Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
    1691             :   Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
    1692             :   Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
    1693             :   Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1,
    1694             :   Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0,
    1695             :   Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0,
    1696             :   Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
    1697             :   Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1,
    1698             :   Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
    1699             :   Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0,
    1700             :   Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0,
    1701             :   Convert__ARMBranchTarget1_1__CondCode2_0,
    1702             :   ConvertCustom_cvtThumbBranches,
    1703             :   Convert__Reg1_1__Tie0__Bitfield1_2__CondCode2_0,
    1704             :   Convert__Reg1_1__Tie0__Reg1_2__Bitfield1_3__CondCode2_0,
    1705             :   Convert__imm_95_0,
    1706             :   Convert__Imm0_2551_0,
    1707             :   Convert__Imm0_655351_0,
    1708             :   Convert__ARMBranchTarget1_0,
    1709             :   Convert__CondCode2_0__ThumbBranchTarget1_1,
    1710             :   Convert__Reg1_0,
    1711             :   Convert__ThumbBranchTarget1_0,
    1712             :   Convert__Reg1_1__CondCode2_0,
    1713             :   Convert__CondCode2_0__Reg1_1,
    1714             :   Convert__CondCode2_0__ARMBranchTarget1_1,
    1715             :   Convert__CondCode2_0,
    1716             :   Convert__Reg1_0__ThumbBranchTarget1_1,
    1717             :   Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
    1718             :   Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
    1719             :   Convert__Reg1_1__Reg1_2__CondCode2_0,
    1720             :   Convert__Reg1_1__ModImmNeg1_2__CondCode2_0,
    1721             :   Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0,
    1722             :   Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0,
    1723             :   Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0,
    1724             :   Convert__Reg1_1__T2SOImm1_2__CondCode2_0,
    1725             :   Convert__Reg1_1__ModImm1_2__CondCode2_0,
    1726             :   Convert__Reg1_2__Reg1_3__CondCode2_0,
    1727             :   Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0,
    1728             :   Convert__Reg1_2__T2SOImm1_3__CondCode2_0,
    1729             :   Convert__Reg1_1__Imm0_2551_2__CondCode2_0,
    1730             :   Convert__Imm0_311_0,
    1731             :   Convert__Imm1_0__imm_95_0,
    1732             :   Convert__Imm0_311_1,
    1733             :   Convert__Imm1_0__ProcIFlags1_1,
    1734             :   Convert__Imm1_0__ProcIFlags1_2,
    1735             :   Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2,
    1736             :   Convert__Imm1_0__ProcIFlags1_1__Imm1_2,
    1737             :   Convert__Imm1_0__ProcIFlags1_2__Imm1_3,
    1738             :   Convert__Reg1_0__Reg1_1__Reg1_2,
    1739             :   Convert__Imm0_151_1__CondCode2_0,
    1740             :   Convert__imm_95_15,
    1741             :   Convert__imm_95_15__CondCode2_0,
    1742             :   Convert__MemBarrierOpt1_0,
    1743             :   Convert__MemBarrierOpt1_1__CondCode2_0,
    1744             :   Convert__imm_95_0__CondCode2_0,
    1745             :   Convert__imm_95_16__CondCode2_0,
    1746             :   Convert__Reg1_1__FPImm1_2__CondCode2_0,
    1747             :   Convert__Reg1_1__Tie0__CondCode2_0__DPRRegList1_3,
    1748             :   Convert__Reg1_1__CondCode2_0__DPRRegList1_2,
    1749             :   Convert__Reg1_1__Tie0__Reg1_2__imm_95_1__CondCode2_0,
    1750             :   Convert__Reg1_1__Tie0__Reg1_2__imm_95_0__CondCode2_0,
    1751             :   Convert__Imm0_2391_1__CondCode2_0,
    1752             :   Convert__Imm0_2391_2__CondCode2_0,
    1753             :   Convert__Imm0_631_0,
    1754             :   Convert__Imm0_655351_1,
    1755             :   Convert__InstSyncBarrierOpt1_0,
    1756             :   Convert__InstSyncBarrierOpt1_1__CondCode2_0,
    1757             :   Convert__ITCondCode1_1__ITMask1_0,
    1758             :   Convert__Reg1_1__MemNoOffset1_2__CondCode2_0,
    1759             :   Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0,
    1760             :   Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0,
    1761             :   Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0,
    1762             :   Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0,
    1763             :   Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2,
    1764             :   Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3,
    1765             :   Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3,
    1766             :   Convert__Reg1_1__CondCode2_0__RegList1_2,
    1767             :   Convert__Reg1_2__CondCode2_0__RegList1_3,
    1768             :   Convert__Reg1_1__CondCode2_0__RegList1_3,
    1769             :   Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3,
    1770             :   Convert__Reg1_2__Tie0__CondCode2_0__RegList1_4,
    1771             :   Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0,
    1772             :   Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0,
    1773             :   Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0,
    1774             :   Convert__Reg1_1__MemThumbRR2_2__CondCode2_0,
    1775             :   Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0,
    1776             :   Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0,
    1777             :   Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0,
    1778             :   Convert__Reg1_1__MemRegOffset3_2__CondCode2_0,
    1779             :   Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0,
    1780             :   Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0,
    1781             :   Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0,
    1782             :   Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0,
    1783             :   Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0,
    1784             :   Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0,
    1785             :   Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0,
    1786             :   Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0,
    1787             :   Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0,
    1788             :   Convert__Reg1_1__MemNoOffset1_2__Tie1__AM2OffsetImm2_3__CondCode2_0,
    1789             :   Convert__Reg1_1__MemNoOffset1_2__Tie1__Imm1_3__CondCode2_0,
    1790             :   Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxRegShifted2_3__CondCode2_0,
    1791             :   Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0,
    1792             :   Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0,
    1793             :   Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0,
    1794             :   Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
    1795             :   Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
    1796             :   Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0,
    1797             :   Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2__Imm1_4__CondCode2_0,
    1798             :   Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0,
    1799             :   Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2__AM3Offset2_4__CondCode2_0,
    1800             :   Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0,
    1801             :   Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0,
    1802             :   Convert__Reg1_1__AddrMode33_2__CondCode2_0,
    1803             :   Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0,
    1804             :   Convert__Reg1_1__MemNoOffset1_2__Tie1__AM3Offset2_3__CondCode2_0,
    1805             :   Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxReg2_3__CondCode2_0,
    1806             :   Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxImm81_3__CondCode2_0,
    1807             :   Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1,
    1808             :   Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0,
    1809             :   Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0,
    1810             :   Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
    1811             :   Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1,
    1812             :   Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
    1813             :   Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
    1814             :   Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
    1815             :   Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0,
    1816             :   Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
    1817             :   Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
    1818             :   Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
    1819             :   Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0,
    1820             :   Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
    1821             :   Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0,
    1822             :   Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4,
    1823             :   Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
    1824             :   Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
    1825             :   Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0,
    1826             :   Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0,
    1827             :   Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0,
    1828             :   Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0,
    1829             :   Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1,
    1830             :   Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
    1831             :   Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
    1832             :   Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
    1833             :   Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
    1834             :   Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0,
    1835             :   Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0,
    1836             :   Convert__Reg1_2__Reg1_3__CondCode2_0__reg0,
    1837             :   Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
    1838             :   Convert__Reg1_0__Reg1_1,
    1839             :   Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0,
    1840             :   Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR,
    1841             :   Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR,
    1842             :   Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR,
    1843             :   Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR,
    1844             :   Convert__Reg1_1__Tie0__Imm0_65535Expr1_2__CondCode2_0,
    1845             :   Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
    1846             :   Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
    1847             :   Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0,
    1848             :   Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
    1849             :   Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0,
    1850             :   Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4,
    1851             :   Convert__Reg1_1__BankedReg1_2__CondCode2_0,
    1852             :   Convert__Reg1_1__MSRMask1_2__CondCode2_0,
    1853             :   Convert__BankedReg1_1__Reg1_2__CondCode2_0,
    1854             :   Convert__MSRMask1_1__Reg1_2__CondCode2_0,
    1855             :   Convert__MSRMask1_1__ModImm1_2__CondCode2_0,
    1856             :   Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0,
    1857             :   ConvertCustom_cvtThumbMultiply,
    1858             :   Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1,
    1859             :   Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
    1860             :   Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
    1861             :   Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
    1862             :   Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0,
    1863             :   Convert__regR8__regR8__imm_95_14__imm_95_0,
    1864             :   Convert__regR0__regR0__CondCode2_0__reg0,
    1865             :   Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
    1866             :   Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0,
    1867             :   Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0,
    1868             :   Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0,
    1869             :   Convert__MemImm12Offset2_0,
    1870             :   Convert__MemRegOffset3_0,
    1871             :   Convert__Imm1_1__CondCode2_0,
    1872             :   Convert__MemNegImm8Offset2_1__CondCode2_0,
    1873             :   Convert__MemUImm12Offset2_1__CondCode2_0,
    1874             :   Convert__T2MemRegOffset3_1__CondCode2_0,
    1875             :   Convert__MemPCRelImm121_1__CondCode2_0,
    1876             :   Convert__CondCode2_0__RegList1_1,
    1877             :   Convert__regSP__Tie0__CondCode2_0__RegList1_1,
    1878             :   Convert__regSP__Tie0__CondCode2_0__RegList1_2,
    1879             :   Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
    1880             :   Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0,
    1881             :   Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0,
    1882             :   Convert__SetEndImm1_0,
    1883             :   Convert__Imm0_11_0,
    1884             :   Convert__imm_95_4__CondCode2_0,
    1885             :   Convert__imm_95_5__CondCode2_0,
    1886             :   Convert__Reg1_1__Tie0__Reg1_2__Reg1_3,
    1887             :   Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0,
    1888             :   Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0__Tie1__CondCode2_1__CCOut1_0,
    1889             :   Convert__Imm0_311_2,
    1890             :   Convert__Imm0_311_1__CondCode2_0,
    1891             :   Convert__Imm0_311_2__CondCode2_0,
    1892             :   Convert__Imm0_311_3__CondCode2_0,
    1893             :   Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0,
    1894             :   Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0,
    1895             :   Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0,
    1896             :   Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0,
    1897             :   Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0,
    1898             :   Convert__MemNoOffset1_2__Reg1_1__Tie0__Imm1_3__CondCode2_0,
    1899             :   Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0,
    1900             :   Convert__MemNoOffset1_2__Reg1_1__Tie0__AM2OffsetImm2_3__CondCode2_0,
    1901             :   Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxRegShifted2_3__CondCode2_0,
    1902             :   Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0,
    1903             :   Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0,
    1904             :   Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
    1905             :   Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0__Imm1_4__CondCode2_0,
    1906             :   Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
    1907             :   Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0__AM3Offset2_4__CondCode2_0,
    1908             :   Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0,
    1909             :   Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0,
    1910             :   Convert__MemNoOffset1_2__Reg1_1__Tie0__AM3Offset2_3__CondCode2_0,
    1911             :   Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxImm81_3__CondCode2_0,
    1912             :   Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxReg2_3__CondCode2_0,
    1913             :   Convert__Imm0_2551_3__CondCode2_0,
    1914             :   Convert__Imm0_2551_1__CondCode2_0,
    1915             :   Convert__Imm24bit1_1__CondCode2_0,
    1916             :   Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
    1917             :   Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0,
    1918             :   Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
    1919             :   Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0,
    1920             :   Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
    1921             :   Convert__MemTBB2_1__CondCode2_0,
    1922             :   Convert__MemTBH2_1__CondCode2_0,
    1923             :   Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0,
    1924             :   Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0,
    1925             :   Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0,
    1926             :   Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0,
    1927             :   Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0,
    1928             :   Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
    1929             :   Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0,
    1930             :   Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0,
    1931             :   Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0,
    1932             :   Convert__Reg1_2__NEONi16splatNot1_3__Tie0__CondCode2_0,
    1933             :   Convert__Reg1_2__NEONi32splatNot1_3__Tie0__CondCode2_0,
    1934             :   Convert__Reg1_2__NEONi16splat1_3__Tie0__CondCode2_0,
    1935             :   Convert__Reg1_2__NEONi32splat1_3__Tie0__CondCode2_0,
    1936             :   Convert__Reg1_1__Tie0__Reg1_2__Reg1_3__CondCode2_0,
    1937             :   Convert__Reg1_2__Reg1_2__CondCode2_0,
    1938             :   Convert__Reg1_2__CondCode2_0,
    1939             :   Convert__Reg1_3__Reg1_4__CondCode2_0,
    1940             :   Convert__Reg1_3__Tie0__FBits161_5__CondCode2_0,
    1941             :   Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0,
    1942             :   Convert__Reg1_3__Tie0__FBits321_5__CondCode2_0,
    1943             :   Convert__Reg1_2__Reg1_3,
    1944             :   Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
    1945             :   Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
    1946             :   Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0,
    1947             :   Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0,
    1948             :   Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0,
    1949             :   Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0,
    1950             :   Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0,
    1951             :   Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0,
    1952             :   Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0,
    1953             :   Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0,
    1954             :   Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0,
    1955             :   Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
    1956             :   Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0,
    1957             :   Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0,
    1958             :   Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
    1959             :   Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0,
    1960             :   Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0,
    1961             :   Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0,
    1962             :   Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
    1963             :   Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
    1964             :   Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
    1965             :   Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
    1966             :   Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
    1967             :   Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
    1968             :   Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
    1969             :   Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
    1970             :   Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
    1971             :   Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
    1972             :   Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0,
    1973             :   Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
    1974             :   Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
    1975             :   Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
    1976             :   Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
    1977             :   Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
    1978             :   Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
    1979             :   Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
    1980             :   Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
    1981             :   Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
    1982             :   Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
    1983             :   Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
    1984             :   Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
    1985             :   Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
    1986             :   Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
    1987             :   Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    1988             :   Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
    1989             :   Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    1990             :   Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    1991             :   Convert__Reg1_3__AlignedMemory2_8__Tie0__Imm1_5__CondCode2_0,
    1992             :   Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0__Imm1_5__CondCode2_0,
    1993             :   Convert__Reg1_3__Reg1_8__Imm1_9__Tie0__Imm1_5__CondCode2_0,
    1994             :   Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
    1995             :   Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0,
    1996             :   Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
    1997             :   Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
    1998             :   Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
    1999             :   Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
    2000             :   Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
    2001             :   Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
    2002             :   Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
    2003             :   Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0,
    2004             :   Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
    2005             :   Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
    2006             :   Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
    2007             :   Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
    2008             :   Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
    2009             :   Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
    2010             :   Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
    2011             :   Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
    2012             :   Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
    2013             :   Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
    2014             :   Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
    2015             :   Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
    2016             :   Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
    2017             :   Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
    2018             :   Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
    2019             :   Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
    2020             :   Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
    2021             :   Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
    2022             :   Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0,
    2023             :   Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
    2024             :   Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
    2025             :   Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
    2026             :   Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
    2027             :   Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    2028             :   Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
    2029             :   Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    2030             :   Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    2031             :   Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
    2032             :   Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    2033             :   Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    2034             :   Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    2035             :   Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
    2036             :   Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0,
    2037             :   Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0,
    2038             :   Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0,
    2039             :   Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0,
    2040             :   Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
    2041             :   Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
    2042             :   Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
    2043             :   Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0,
    2044             :   Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
    2045             :   Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
    2046             :   Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
    2047             :   Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
    2048             :   Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
    2049             :   Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
    2050             :   Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0,
    2051             :   Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
    2052             :   Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
    2053             :   Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
    2054             :   Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
    2055             :   Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
    2056             :   Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
    2057             :   Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
    2058             :   Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
    2059             :   Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
    2060             :   Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
    2061             :   Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
    2062             :   Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
    2063             :   Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
    2064             :   Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
    2065             :   Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0,
    2066             :   Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0,
    2067             :   Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0,
    2068             :   Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0,
    2069             :   Convert__Reg1_1__Tie0__CondCode2_0__SPRRegList1_3,
    2070             :   Convert__Reg1_1__CondCode2_0__SPRRegList1_2,
    2071             :   Convert__Reg1_1__AddrMode52_2__CondCode2_0,
    2072             :   Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0,
    2073             :   Convert__Reg1_2__AddrMode52_3__CondCode2_0,
    2074             :   Convert__Reg1_1__Reg1_2__Reg1_3,
    2075             :   Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
    2076             :   Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
    2077             :   Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0,
    2078             :   Convert__Reg1_2__FPImm1_3__CondCode2_0,
    2079             :   Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0,
    2080             :   Convert__Reg1_2__NEONi16splat1_3__CondCode2_0,
    2081             :   Convert__Reg1_2__NEONi16vmovByteReplicate1_3__CondCode2_0,
    2082             :   Convert__Reg1_2__NEONi32vmovByteReplicate1_3__CondCode2_0,
    2083             :   Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0,
    2084             :   Convert__Reg1_2__NEONi64splat1_3__CondCode2_0,
    2085             :   Convert__Reg1_2__NEONi8splat1_3__CondCode2_0,
    2086             :   Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0,
    2087             :   Convert__Reg1_2__Tie0__Reg1_4__VectorIndex161_3__CondCode2_0,
    2088             :   Convert__Reg1_2__Tie0__Reg1_4__VectorIndex321_3__CondCode2_0,
    2089             :   Convert__Reg1_2__Tie0__Reg1_4__VectorIndex81_3__CondCode2_0,
    2090             :   Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
    2091             :   Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
    2092             :   Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
    2093             :   Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
    2094             :   Convert__Reg1_2__NEONi16invByteReplicate1_3__CondCode2_0,
    2095             :   Convert__Reg1_2__NEONi32invByteReplicate1_3__CondCode2_0,
    2096             :   Convert__Reg1_2__Tie0__Reg1_3__CondCode2_0,
    2097             :   Convert__regSP__Tie0__CondCode2_0__DPRRegList1_1,
    2098             :   Convert__regSP__Tie0__CondCode2_0__SPRRegList1_1,
    2099             :   Convert__regSP__Tie0__CondCode2_0__DPRRegList1_2,
    2100             :   Convert__regSP__Tie0__CondCode2_0__SPRRegList1_2,
    2101             :   Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0,
    2102             :   Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0,
    2103             :   Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0,
    2104             :   Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0,
    2105             :   Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0,
    2106             :   Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0,
    2107             :   Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0,
    2108             :   Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0,
    2109             :   Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0,
    2110             :   Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0,
    2111             :   Convert__Reg1_2__Tie0__Reg1_2__ShrImm161_3__CondCode2_0,
    2112             :   Convert__Reg1_2__Tie0__Reg1_2__ShrImm321_3__CondCode2_0,
    2113             :   Convert__Reg1_2__Tie0__Reg1_2__ShrImm641_3__CondCode2_0,
    2114             :   Convert__Reg1_2__Tie0__Reg1_2__ShrImm81_3__CondCode2_0,
    2115             :   Convert__Reg1_2__Tie0__Reg1_3__ShrImm161_4__CondCode2_0,
    2116             :   Convert__Reg1_2__Tie0__Reg1_3__ShrImm321_4__CondCode2_0,
    2117             :   Convert__Reg1_2__Tie0__Reg1_3__ShrImm641_4__CondCode2_0,
    2118             :   Convert__Reg1_2__Tie0__Reg1_3__ShrImm81_4__CondCode2_0,
    2119             :   Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4,
    2120             :   Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0,
    2121             :   Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0,
    2122             :   Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0,
    2123             :   Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0,
    2124             :   Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0,
    2125             :   Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0,
    2126             :   Convert__Reg1_2__Tie0__Reg1_2__Imm1_3__CondCode2_0,
    2127             :   Convert__Reg1_2__Tie0__Reg1_3__Imm1_4__CondCode2_0,
    2128             :   Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
    2129             :   Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
    2130             :   Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
    2131             :   Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
    2132             :   Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
    2133             :   Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0,
    2134             :   Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
    2135             :   Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0,
    2136             :   Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
    2137             :   Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0,
    2138             :   Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
    2139             :   Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0,
    2140             :   Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0,
    2141             :   Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
    2142             :   Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
    2143             :   Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0,
    2144             :   Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
    2145             :   Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
    2146             :   Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0,
    2147             :   Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
    2148             :   Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
    2149             :   Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
    2150             :   Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
    2151             :   Convert__Reg1_1__Reg1_2__Tie0__Tie1__CondCode2_0,
    2152             :   Convert__Reg1_2__Reg1_3__Tie0__Tie1__CondCode2_0,
    2153             :   Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0,
    2154             :   Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0,
    2155             :   Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0,
    2156             :   Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0,
    2157             :   Convert__Reg1_2__Tie0__VecListDPair1_3__Reg1_4__CondCode2_0,
    2158             :   Convert__Reg1_2__Tie0__VecListFourD1_3__Reg1_4__CondCode2_0,
    2159             :   Convert__Reg1_2__Tie0__VecListOneD1_3__Reg1_4__CondCode2_0,
    2160             :   Convert__Reg1_2__Tie0__VecListThreeD1_3__Reg1_4__CondCode2_0,
    2161             :   Convert__imm_95_2__CondCode2_0,
    2162             :   Convert__imm_95_3__CondCode2_0,
    2163             :   Convert__imm_95_1__CondCode2_0,
    2164             :   CVT_NUM_SIGNATURES
    2165             : };
    2166             : 
    2167             : } // end anonymous namespace
    2168             : 
    2169             : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = {
    2170             :   // Convert_NoOperands
    2171             :   { CVT_Done },
    2172             :   // Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1
    2173             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2174             :   // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
    2175             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2176             :   // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
    2177             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2178             :   // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
    2179             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2180             :   // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
    2181             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2182             :   // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
    2183             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2184             :   // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
    2185             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2186             :   // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
    2187             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2188             :   // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
    2189             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2190             :   // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
    2191             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2192             :   // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0
    2193             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2194             :   // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0
    2195             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2196             :   // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0
    2197             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2198             :   // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
    2199             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2200             :   // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0
    2201             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2202             :   // Convert__Reg1_1__Tie0__Reg1_2__CondCode2_0
    2203             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2204             :   // Convert__Reg1_1__Tie0__Imm0_508s41_2__CondCode2_0
    2205             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2206             :   // Convert__regSP__Tie0__Imm0_508s4Neg1_2__CondCode2_0
    2207             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2208             :   // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0
    2209             :   { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2210             :   // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0
    2211             :   { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2212             :   // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1
    2213             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2214             :   // Convert__Reg1_2__CCOut1_0__Tie0__Imm0_2551_3__CondCode2_1
    2215             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, 0, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2216             :   // Convert__Reg1_2__CCOut1_0__Tie0__ThumbModImmNeg8_2551_3__CondCode2_1
    2217             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, 0, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2218             :   // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
    2219             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2220             :   // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0
    2221             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2222             :   // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0
    2223             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2224             :   // Convert__regSP__Tie0__Imm0_508s41_3__CondCode2_0
    2225             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2226             :   // Convert__regSP__Tie0__Imm0_508s4Neg1_3__CondCode2_0
    2227             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2228             :   // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0
    2229             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2230             :   // Convert__Reg1_1__Imm0_40951_3__CondCode2_0
    2231             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2232             :   // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0
    2233             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2234             :   // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0
    2235             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2236             :   // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0
    2237             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2238             :   // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
    2239             :   { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2240             :   // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1
    2241             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2242             :   // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1
    2243             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2244             :   // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1
    2245             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2246             :   // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
    2247             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2248             :   // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0
    2249             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2250             :   // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0
    2251             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2252             :   // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0
    2253             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2254             :   // Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0
    2255             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2256             :   // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0
    2257             :   { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2258             :   // Convert__Reg1_1__Imm1_2__CondCode2_0
    2259             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2260             :   // Convert__Reg1_1__AdrLabel1_2__CondCode2_0
    2261             :   { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2262             :   // Convert__Reg1_2__Imm1_3__CondCode2_0
    2263             :   { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2264             :   // Convert__Reg1_1__Tie0__Reg1_2
    2265             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 3, CVT_Done },
    2266             :   // Convert__Reg1_1__Reg1_2
    2267             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    2268             :   // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
    2269             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2270             :   // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
    2271             :   { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2272             :   // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
    2273             :   { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2274             :   // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
    2275             :   { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2276             :   // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1
    2277             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2278             :   // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0
    2279             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2280             :   // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0
    2281             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2282             :   // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
    2283             :   { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2284             :   // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1
    2285             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2286             :   // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
    2287             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2288             :   // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0
    2289             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2290             :   // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0
    2291             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2292             :   // Convert__ARMBranchTarget1_1__CondCode2_0
    2293             :   { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2294             :   // ConvertCustom_cvtThumbBranches
    2295             :   { CVT_cvtThumbBranches, 0, CVT_Done },
    2296             :   // Convert__Reg1_1__Tie0__Bitfield1_2__CondCode2_0
    2297             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2298             :   // Convert__Reg1_1__Tie0__Reg1_2__Bitfield1_3__CondCode2_0
    2299             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2300             :   // Convert__imm_95_0
    2301             :   { CVT_imm_95_0, 0, CVT_Done },
    2302             :   // Convert__Imm0_2551_0
    2303             :   { CVT_95_addImmOperands, 1, CVT_Done },
    2304             :   // Convert__Imm0_655351_0
    2305             :   { CVT_95_addImmOperands, 1, CVT_Done },
    2306             :   // Convert__ARMBranchTarget1_0
    2307             :   { CVT_95_addARMBranchTargetOperands, 1, CVT_Done },
    2308             :   // Convert__CondCode2_0__ThumbBranchTarget1_1
    2309             :   { CVT_95_addCondCodeOperands, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
    2310             :   // Convert__Reg1_0
    2311             :   { CVT_95_Reg, 1, CVT_Done },
    2312             :   // Convert__ThumbBranchTarget1_0
    2313             :   { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done },
    2314             :   // Convert__Reg1_1__CondCode2_0
    2315             :   { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2316             :   // Convert__CondCode2_0__Reg1_1
    2317             :   { CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 2, CVT_Done },
    2318             :   // Convert__CondCode2_0__ARMBranchTarget1_1
    2319             :   { CVT_95_addCondCodeOperands, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done },
    2320             :   // Convert__CondCode2_0
    2321             :   { CVT_95_addCondCodeOperands, 1, CVT_Done },
    2322             :   // Convert__Reg1_0__ThumbBranchTarget1_1
    2323             :   { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
    2324             :   // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
    2325             :   { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2326             :   // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
    2327             :   { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
    2328             :   // Convert__Reg1_1__Reg1_2__CondCode2_0
    2329             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2330             :   // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0
    2331             :   { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2332             :   // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0
    2333             :   { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2334             :   // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0
    2335             :   { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2336             :   // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0
    2337             :   { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2338             :   // Convert__Reg1_1__T2SOImm1_2__CondCode2_0
    2339             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2340             :   // Convert__Reg1_1__ModImm1_2__CondCode2_0
    2341             :   { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2342             :   // Convert__Reg1_2__Reg1_3__CondCode2_0
    2343             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2344             :   // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0
    2345             :   { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2346             :   // Convert__Reg1_2__T2SOImm1_3__CondCode2_0
    2347             :   { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2348             :   // Convert__Reg1_1__Imm0_2551_2__CondCode2_0
    2349             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2350             :   // Convert__Imm0_311_0
    2351             :   { CVT_95_addImmOperands, 1, CVT_Done },
    2352             :   // Convert__Imm1_0__imm_95_0
    2353             :   { CVT_95_addImmOperands, 1, CVT_imm_95_0, 0, CVT_Done },
    2354             :   // Convert__Imm0_311_1
    2355             :   { CVT_95_addImmOperands, 2, CVT_Done },
    2356             :   // Convert__Imm1_0__ProcIFlags1_1
    2357             :   { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done },
    2358             :   // Convert__Imm1_0__ProcIFlags1_2
    2359             :   { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done },
    2360             :   // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2
    2361             :   { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    2362             :   // Convert__Imm1_0__ProcIFlags1_1__Imm1_2
    2363             :   { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    2364             :   // Convert__Imm1_0__ProcIFlags1_2__Imm1_3
    2365             :   { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    2366             :   // Convert__Reg1_0__Reg1_1__Reg1_2
    2367             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    2368             :   // Convert__Imm0_151_1__CondCode2_0
    2369             :   { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2370             :   // Convert__imm_95_15
    2371             :   { CVT_imm_95_15, 0, CVT_Done },
    2372             :   // Convert__imm_95_15__CondCode2_0
    2373             :   { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2374             :   // Convert__MemBarrierOpt1_0
    2375             :   { CVT_95_addMemBarrierOptOperands, 1, CVT_Done },
    2376             :   // Convert__MemBarrierOpt1_1__CondCode2_0
    2377             :   { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2378             :   // Convert__imm_95_0__CondCode2_0
    2379             :   { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2380             :   // Convert__imm_95_16__CondCode2_0
    2381             :   { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2382             :   // Convert__Reg1_1__FPImm1_2__CondCode2_0
    2383             :   { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2384             :   // Convert__Reg1_1__Tie0__CondCode2_0__DPRRegList1_3
    2385             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done },
    2386             :   // Convert__Reg1_1__CondCode2_0__DPRRegList1_2
    2387             :   { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
    2388             :   // Convert__Reg1_1__Tie0__Reg1_2__imm_95_1__CondCode2_0
    2389             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2390             :   // Convert__Reg1_1__Tie0__Reg1_2__imm_95_0__CondCode2_0
    2391             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2392             :   // Convert__Imm0_2391_1__CondCode2_0
    2393             :   { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2394             :   // Convert__Imm0_2391_2__CondCode2_0
    2395             :   { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2396             :   // Convert__Imm0_631_0
    2397             :   { CVT_95_addImmOperands, 1, CVT_Done },
    2398             :   // Convert__Imm0_655351_1
    2399             :   { CVT_95_addImmOperands, 2, CVT_Done },
    2400             :   // Convert__InstSyncBarrierOpt1_0
    2401             :   { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done },
    2402             :   // Convert__InstSyncBarrierOpt1_1__CondCode2_0
    2403             :   { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2404             :   // Convert__ITCondCode1_1__ITMask1_0
    2405             :   { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done },
    2406             :   // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0
    2407             :   { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2408             :   // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0
    2409             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2410             :   // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0
    2411             :   { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2412             :   // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0
    2413             :   { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2414             :   // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0
    2415             :   { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2416             :   // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2
    2417             :   { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done },
    2418             :   // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3
    2419             :   { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done },
    2420             :   // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3
    2421             :   { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done },
    2422             :   // Convert__Reg1_1__CondCode2_0__RegList1_2
    2423             :   { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done },
    2424             :   // Convert__Reg1_2__CondCode2_0__RegList1_3
    2425             :   { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
    2426             :   // Convert__Reg1_1__CondCode2_0__RegList1_3
    2427             :   { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
    2428             :   // Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3
    2429             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
    2430             :   // Convert__Reg1_2__Tie0__CondCode2_0__RegList1_4
    2431             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 5, CVT_Done },
    2432             :   // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0
    2433             :   { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2434             :   // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0
    2435             :   { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2436             :   // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0
    2437             :   { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2438             :   // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0
    2439             :   { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2440             :   // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0
    2441             :   { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2442             :   // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0
    2443             :   { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2444             :   // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0
    2445             :   { CVT_95_Reg, 2, CVT_95_addMemNegImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2446             :   // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0
    2447             :   { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2448             :   // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0
    2449             :   { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2450             :   // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0
    2451             :   { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2452             :   // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0
    2453             :   { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2454             :   // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0
    2455             :   { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2456             :   // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0
    2457             :   { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2458             :   // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0
    2459             :   { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2460             :   // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0
    2461             :   { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2462             :   // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0
    2463             :   { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2464             :   // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0
    2465             :   { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2466             :   // Convert__Reg1_1__MemNoOffset1_2__Tie1__AM2OffsetImm2_3__CondCode2_0
    2467             :   { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, 1, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2468             :   // Convert__Reg1_1__MemNoOffset1_2__Tie1__Imm1_3__CondCode2_0
    2469             :   { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2470             :   // Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxRegShifted2_3__CondCode2_0
    2471             :   { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, 1, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2472             :   // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0
    2473             :   { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2474             :   // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0
    2475             :   { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2476             :   // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0
    2477             :   { CVT_95_Reg, 2, CVT_95_addMemPosImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2478             :   // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
    2479             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2480             :   // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
    2481             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2482             :   // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0
    2483             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2484             :   // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2__Imm1_4__CondCode2_0
    2485             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, 2, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2486             :   // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0
    2487             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2488             :   // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2__AM3Offset2_4__CondCode2_0
    2489             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, 2, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2490             :   // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0
    2491             :   { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2492             :   // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0
    2493             :   { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2494             :   // Convert__Reg1_1__AddrMode33_2__CondCode2_0
    2495             :   { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2496             :   // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0
    2497             :   { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2498             :   // Convert__Reg1_1__MemNoOffset1_2__Tie1__AM3Offset2_3__CondCode2_0
    2499             :   { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, 1, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2500             :   // Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxReg2_3__CondCode2_0
    2501             :   { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, 1, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2502             :   // Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxImm81_3__CondCode2_0
    2503             :   { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, 1, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2504             :   // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1
    2505             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2506             :   // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0
    2507             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2508             :   // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0
    2509             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2510             :   // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
    2511             :   { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2512             :   // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1
    2513             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2514             :   // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
    2515             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2516             :   // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
    2517             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2518             :   // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
    2519             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2520             :   // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0
    2521             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2522             :   // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
    2523             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2524             :   // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
    2525             :   { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2526             :   // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
    2527             :   { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2528             :   // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0
    2529             :   { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
    2530             :   // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
    2531             :   { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
    2532             :   // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0
    2533             :   { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2534             :   // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4
    2535             :   { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done },
    2536             :   // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
    2537             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2538             :   // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
    2539             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2540             :   // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0
    2541             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2542             :   // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0
    2543             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
    2544             :   // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0
    2545             :   { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
    2546             :   // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0
    2547             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2548             :   // Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1
    2549             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2550             :   // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
    2551             :   { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2552             :   // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
    2553             :   { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2554             :   // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
    2555             :   { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2556             :   // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
    2557             :   { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2558             :   // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0
    2559             :   { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2560             :   // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0
    2561             :   { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
    2562             :   // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0
    2563             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
    2564             :   // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
    2565             :   { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2566             :   // Convert__Reg1_0__Reg1_1
    2567             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
    2568             :   // Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0
    2569             :   { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
    2570             :   // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR
    2571             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
    2572             :   // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR
    2573             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
    2574             :   // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR
    2575             :   { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
    2576             :   // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR
    2577             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
    2578             :   // Convert__Reg1_1__Tie0__Imm0_65535Expr1_2__CondCode2_0
    2579             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2580             :   // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
    2581             :   { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2582             :   // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
    2583             :   { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2584             :   // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0
    2585             :   { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
    2586             :   // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
    2587             :   { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
    2588             :   // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0
    2589             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2590             :   // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4
    2591             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done },
    2592             :   // Convert__Reg1_1__BankedReg1_2__CondCode2_0
    2593             :   { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2594             :   // Convert__Reg1_1__MSRMask1_2__CondCode2_0
    2595             :   { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2596             :   // Convert__BankedReg1_1__Reg1_2__CondCode2_0
    2597             :   { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2598             :   // Convert__MSRMask1_1__Reg1_2__CondCode2_0
    2599             :   { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2600             :   // Convert__MSRMask1_1__ModImm1_2__CondCode2_0
    2601             :   { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2602             :   // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0
    2603             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2604             :   // ConvertCustom_cvtThumbMultiply
    2605             :   { CVT_cvtThumbMultiply, 0, CVT_Done },
    2606             :   // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1
    2607             :   { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
    2608             :   // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
    2609             :   { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2610             :   // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
    2611             :   { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2612             :   // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
    2613             :   { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2614             :   // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0
    2615             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2616             :   // Convert__regR8__regR8__imm_95_14__imm_95_0
    2617             :   { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
    2618             :   // Convert__regR0__regR0__CondCode2_0__reg0
    2619             :   { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
    2620             :   // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
    2621             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2622             :   // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0
    2623             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2624             :   // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0
    2625             :   { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2626             :   // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0
    2627             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2628             :   // Convert__MemImm12Offset2_0
    2629             :   { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done },
    2630             :   // Convert__MemRegOffset3_0
    2631             :   { CVT_95_addMemRegOffsetOperands, 1, CVT_Done },
    2632             :   // Convert__Imm1_1__CondCode2_0
    2633             :   { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2634             :   // Convert__MemNegImm8Offset2_1__CondCode2_0
    2635             :   { CVT_95_addMemNegImm8OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2636             :   // Convert__MemUImm12Offset2_1__CondCode2_0
    2637             :   { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2638             :   // Convert__T2MemRegOffset3_1__CondCode2_0
    2639             :   { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2640             :   // Convert__MemPCRelImm121_1__CondCode2_0
    2641             :   { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2642             :   // Convert__CondCode2_0__RegList1_1
    2643             :   { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done },
    2644             :   // Convert__regSP__Tie0__CondCode2_0__RegList1_1
    2645             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done },
    2646             :   // Convert__regSP__Tie0__CondCode2_0__RegList1_2
    2647             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done },
    2648             :   // Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
    2649             :   { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2650             :   // Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0
    2651             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2652             :   // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0
    2653             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2654             :   // Convert__SetEndImm1_0
    2655             :   { CVT_95_addImmOperands, 1, CVT_Done },
    2656             :   // Convert__Imm0_11_0
    2657             :   { CVT_95_addImmOperands, 1, CVT_Done },
    2658             :   // Convert__imm_95_4__CondCode2_0
    2659             :   { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2660             :   // Convert__imm_95_5__CondCode2_0
    2661             :   { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2662             :   // Convert__Reg1_1__Tie0__Reg1_2__Reg1_3
    2663             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
    2664             :   // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0
    2665             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2666             :   // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0__Tie1__CondCode2_1__CCOut1_0
    2667             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
    2668             :   // Convert__Imm0_311_2
    2669             :   { CVT_95_addImmOperands, 3, CVT_Done },
    2670             :   // Convert__Imm0_311_1__CondCode2_0
    2671             :   { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2672             :   // Convert__Imm0_311_2__CondCode2_0
    2673             :   { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2674             :   // Convert__Imm0_311_3__CondCode2_0
    2675             :   { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2676             :   // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0
    2677             :   { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2678             :   // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0
    2679             :   { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2680             :   // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0
    2681             :   { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2682             :   // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0
    2683             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2684             :   // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0
    2685             :   { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2686             :   // Convert__MemNoOffset1_2__Reg1_1__Tie0__Imm1_3__CondCode2_0
    2687             :   { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2688             :   // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0
    2689             :   { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2690             :   // Convert__MemNoOffset1_2__Reg1_1__Tie0__AM2OffsetImm2_3__CondCode2_0
    2691             :   { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2692             :   // Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxRegShifted2_3__CondCode2_0
    2693             :   { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2694             :   // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0
    2695             :   { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2696             :   // Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0
    2697             :   { CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2698             :   // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
    2699             :   { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2700             :   // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0__Imm1_4__CondCode2_0
    2701             :   { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2702             :   // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
    2703             :   { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2704             :   // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0__AM3Offset2_4__CondCode2_0
    2705             :   { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2706             :   // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0
    2707             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2708             :   // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0
    2709             :   { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2710             :   // Convert__MemNoOffset1_2__Reg1_1__Tie0__AM3Offset2_3__CondCode2_0
    2711             :   { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2712             :   // Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxImm81_3__CondCode2_0
    2713             :   { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2714             :   // Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxReg2_3__CondCode2_0
    2715             :   { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2716             :   // Convert__Imm0_2551_3__CondCode2_0
    2717             :   { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2718             :   // Convert__Imm0_2551_1__CondCode2_0
    2719             :   { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2720             :   // Convert__Imm24bit1_1__CondCode2_0
    2721             :   { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2722             :   // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
    2723             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2724             :   // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0
    2725             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2726             :   // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
    2727             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2728             :   // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0
    2729             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2730             :   // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
    2731             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2732             :   // Convert__MemTBB2_1__CondCode2_0
    2733             :   { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2734             :   // Convert__MemTBH2_1__CondCode2_0
    2735             :   { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2736             :   // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0
    2737             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2738             :   // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0
    2739             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2740             :   // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0
    2741             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2742             :   // Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0
    2743             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2744             :   // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0
    2745             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2746             :   // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
    2747             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2748             :   // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0
    2749             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2750             :   // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0
    2751             :   { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2752             :   // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0
    2753             :   { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2754             :   // Convert__Reg1_2__NEONi16splatNot1_3__Tie0__CondCode2_0
    2755             :   { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2756             :   // Convert__Reg1_2__NEONi32splatNot1_3__Tie0__CondCode2_0
    2757             :   { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2758             :   // Convert__Reg1_2__NEONi16splat1_3__Tie0__CondCode2_0
    2759             :   { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2760             :   // Convert__Reg1_2__NEONi32splat1_3__Tie0__CondCode2_0
    2761             :   { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2762             :   // Convert__Reg1_1__Tie0__Reg1_2__Reg1_3__CondCode2_0
    2763             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2764             :   // Convert__Reg1_2__Reg1_2__CondCode2_0
    2765             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2766             :   // Convert__Reg1_2__CondCode2_0
    2767             :   { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2768             :   // Convert__Reg1_3__Reg1_4__CondCode2_0
    2769             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2770             :   // Convert__Reg1_3__Tie0__FBits161_5__CondCode2_0
    2771             :   { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2772             :   // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0
    2773             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2774             :   // Convert__Reg1_3__Tie0__FBits321_5__CondCode2_0
    2775             :   { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2776             :   // Convert__Reg1_2__Reg1_3
    2777             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
    2778             :   // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
    2779             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2780             :   // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
    2781             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2782             :   // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0
    2783             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2784             :   // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0
    2785             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2786             :   // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0
    2787             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2788             :   // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0
    2789             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2790             :   // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0
    2791             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2792             :   // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0
    2793             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2794             :   // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0
    2795             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2796             :   // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0
    2797             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2798             :   // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0
    2799             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2800             :   // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
    2801             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2802             :   // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0
    2803             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2804             :   // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0
    2805             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2806             :   // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
    2807             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2808             :   // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0
    2809             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2810             :   // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0
    2811             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2812             :   // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0
    2813             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2814             :   // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
    2815             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2816             :   // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
    2817             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2818             :   // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0
    2819             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2820             :   // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
    2821             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2822             :   // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
    2823             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2824             :   // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
    2825             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2826             :   // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
    2827             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2828             :   // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
    2829             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2830             :   // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
    2831             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2832             :   // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
    2833             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2834             :   // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0
    2835             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2836             :   // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
    2837             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2838             :   // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
    2839             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2840             :   // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
    2841             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2842             :   // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
    2843             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2844             :   // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
    2845             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2846             :   // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
    2847             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2848             :   // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
    2849             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2850             :   // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
    2851             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2852             :   // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
    2853             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2854             :   // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
    2855             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2856             :   // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
    2857             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2858             :   // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
    2859             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2860             :   // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
    2861             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2862             :   // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
    2863             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2864             :   // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2865             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2866             :   // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
    2867             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2868             :   // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2869             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2870             :   // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2871             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2872             :   // Convert__Reg1_3__AlignedMemory2_8__Tie0__Imm1_5__CondCode2_0
    2873             :   { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, 0, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2874             :   // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0__Imm1_5__CondCode2_0
    2875             :   { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, 0, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2876             :   // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0__Imm1_5__CondCode2_0
    2877             :   { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, 0, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2878             :   // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
    2879             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2880             :   // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0
    2881             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2882             :   // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
    2883             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2884             :   // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
    2885             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2886             :   // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
    2887             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2888             :   // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
    2889             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2890             :   // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0
    2891             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2892             :   // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0
    2893             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2894             :   // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
    2895             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2896             :   // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0
    2897             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2898             :   // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
    2899             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2900             :   // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
    2901             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2902             :   // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
    2903             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2904             :   // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
    2905             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2906             :   // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
    2907             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2908             :   // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
    2909             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2910             :   // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
    2911             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2912             :   // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
    2913             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2914             :   // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
    2915             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2916             :   // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
    2917             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2918             :   // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
    2919             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2920             :   // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
    2921             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2922             :   // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
    2923             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2924             :   // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
    2925             :   { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2926             :   // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
    2927             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2928             :   // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
    2929             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2930             :   // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
    2931             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2932             :   // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
    2933             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2934             :   // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0
    2935             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2936             :   // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
    2937             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2938             :   // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
    2939             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2940             :   // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
    2941             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2942             :   // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
    2943             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2944             :   // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2945             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2946             :   // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
    2947             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2948             :   // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2949             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2950             :   // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2951             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2952             :   // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
    2953             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2954             :   // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2955             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2956             :   // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2957             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2958             :   // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2959             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2960             :   // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
    2961             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2962             :   // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0
    2963             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2964             :   // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0
    2965             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2966             :   // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0
    2967             :   { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2968             :   // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0
    2969             :   { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2970             :   // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
    2971             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2972             :   // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
    2973             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2974             :   // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
    2975             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2976             :   // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0
    2977             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2978             :   // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
    2979             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2980             :   // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
    2981             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2982             :   // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
    2983             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2984             :   // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
    2985             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2986             :   // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
    2987             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2988             :   // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
    2989             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2990             :   // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0
    2991             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2992             :   // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
    2993             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2994             :   // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
    2995             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2996             :   // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
    2997             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    2998             :   // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
    2999             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3000             :   // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
    3001             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3002             :   // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
    3003             :   { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3004             :   // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
    3005             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3006             :   // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
    3007             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3008             :   // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
    3009             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3010             :   // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
    3011             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3012             :   // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
    3013             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3014             :   // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
    3015             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3016             :   // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
    3017             :   { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3018             :   // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
    3019             :   { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3020             :   // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0
    3021             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3022             :   // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0
    3023             :   { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3024             :   // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0
    3025             :   { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3026             :   // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0
    3027             :   { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3028             :   // Convert__Reg1_1__Tie0__CondCode2_0__SPRRegList1_3
    3029             :   { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done },
    3030             :   // Convert__Reg1_1__CondCode2_0__SPRRegList1_2
    3031             :   { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
    3032             :   // Convert__Reg1_1__AddrMode52_2__CondCode2_0
    3033             :   { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3034             :   // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0
    3035             :   { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3036             :   // Convert__Reg1_2__AddrMode52_3__CondCode2_0
    3037             :   { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3038             :   // Convert__Reg1_1__Reg1_2__Reg1_3
    3039             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
    3040             :   // Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
    3041             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3042             :   // Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
    3043             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3044             :   // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0
    3045             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3046             :   // Convert__Reg1_2__FPImm1_3__CondCode2_0
    3047             :   { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3048             :   // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0
    3049             :   { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3050             :   // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0
    3051             :   { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3052             :   // Convert__Reg1_2__NEONi16vmovByteReplicate1_3__CondCode2_0
    3053             :   { CVT_95_Reg, 3, CVT_95_addNEONvmovByteReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3054             :   // Convert__Reg1_2__NEONi32vmovByteReplicate1_3__CondCode2_0
    3055             :   { CVT_95_Reg, 3, CVT_95_addNEONvmovByteReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3056             :   // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0
    3057             :   { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3058             :   // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0
    3059             :   { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3060             :   // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0
    3061             :   { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3062             :   // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0
    3063             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3064             :   // Convert__Reg1_2__Tie0__Reg1_4__VectorIndex161_3__CondCode2_0
    3065             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3066             :   // Convert__Reg1_2__Tie0__Reg1_4__VectorIndex321_3__CondCode2_0
    3067             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3068             :   // Convert__Reg1_2__Tie0__Reg1_4__VectorIndex81_3__CondCode2_0
    3069             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3070             :   // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
    3071             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3072             :   // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
    3073             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3074             :   // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
    3075             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3076             :   // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
    3077             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3078             :   // Convert__Reg1_2__NEONi16invByteReplicate1_3__CondCode2_0
    3079             :   { CVT_95_Reg, 3, CVT_95_addNEONinvByteReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3080             :   // Convert__Reg1_2__NEONi32invByteReplicate1_3__CondCode2_0
    3081             :   { CVT_95_Reg, 3, CVT_95_addNEONinvByteReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3082             :   // Convert__Reg1_2__Tie0__Reg1_3__CondCode2_0
    3083             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3084             :   // Convert__regSP__Tie0__CondCode2_0__DPRRegList1_1
    3085             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done },
    3086             :   // Convert__regSP__Tie0__CondCode2_0__SPRRegList1_1
    3087             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done },
    3088             :   // Convert__regSP__Tie0__CondCode2_0__DPRRegList1_2
    3089             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
    3090             :   // Convert__regSP__Tie0__CondCode2_0__SPRRegList1_2
    3091             :   { CVT_regSP, 0, CVT_Tied, 0, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
    3092             :   // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0
    3093             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3094             :   // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0
    3095             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3096             :   // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0
    3097             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3098             :   // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0
    3099             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3100             :   // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0
    3101             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3102             :   // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0
    3103             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3104             :   // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0
    3105             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3106             :   // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0
    3107             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3108             :   // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0
    3109             :   { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3110             :   // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0
    3111             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3112             :   // Convert__Reg1_2__Tie0__Reg1_2__ShrImm161_3__CondCode2_0
    3113             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3114             :   // Convert__Reg1_2__Tie0__Reg1_2__ShrImm321_3__CondCode2_0
    3115             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3116             :   // Convert__Reg1_2__Tie0__Reg1_2__ShrImm641_3__CondCode2_0
    3117             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3118             :   // Convert__Reg1_2__Tie0__Reg1_2__ShrImm81_3__CondCode2_0
    3119             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3120             :   // Convert__Reg1_2__Tie0__Reg1_3__ShrImm161_4__CondCode2_0
    3121             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3122             :   // Convert__Reg1_2__Tie0__Reg1_3__ShrImm321_4__CondCode2_0
    3123             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3124             :   // Convert__Reg1_2__Tie0__Reg1_3__ShrImm641_4__CondCode2_0
    3125             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3126             :   // Convert__Reg1_2__Tie0__Reg1_3__ShrImm81_4__CondCode2_0
    3127             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3128             :   // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4
    3129             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
    3130             :   // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0
    3131             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3132             :   // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0
    3133             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3134             :   // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0
    3135             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3136             :   // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0
    3137             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3138             :   // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0
    3139             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3140             :   // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0
    3141             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3142             :   // Convert__Reg1_2__Tie0__Reg1_2__Imm1_3__CondCode2_0
    3143             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3144             :   // Convert__Reg1_2__Tie0__Reg1_3__Imm1_4__CondCode2_0
    3145             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3146             :   // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
    3147             :   { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3148             :   // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
    3149             :   { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3150             :   // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
    3151             :   { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3152             :   // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
    3153             :   { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3154             :   // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
    3155             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3156             :   // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0
    3157             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3158             :   // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
    3159             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3160             :   // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0
    3161             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3162             :   // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
    3163             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3164             :   // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0
    3165             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3166             :   // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
    3167             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3168             :   // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0
    3169             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3170             :   // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0
    3171             :   { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3172             :   // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
    3173             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3174             :   // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
    3175             :   { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3176             :   // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0
    3177             :   { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3178             :   // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
    3179             :   { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3180             :   // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
    3181             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3182             :   // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0
    3183             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3184             :   // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
    3185             :   { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3186             :   // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
    3187             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3188             :   // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
    3189             :   { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3190             :   // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
    3191             :   { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3192             :   // Convert__Reg1_1__Reg1_2__Tie0__Tie1__CondCode2_0
    3193             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3194             :   // Convert__Reg1_2__Reg1_3__Tie0__Tie1__CondCode2_0
    3195             :   { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3196             :   // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0
    3197             :   { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3198             :   // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0
    3199             :   { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3200             :   // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0
    3201             :   { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3202             :   // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0
    3203             :   { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3204             :   // Convert__Reg1_2__Tie0__VecListDPair1_3__Reg1_4__CondCode2_0
    3205             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3206             :   // Convert__Reg1_2__Tie0__VecListFourD1_3__Reg1_4__CondCode2_0
    3207             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3208             :   // Convert__Reg1_2__Tie0__VecListOneD1_3__Reg1_4__CondCode2_0
    3209             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3210             :   // Convert__Reg1_2__Tie0__VecListThreeD1_3__Reg1_4__CondCode2_0
    3211             :   { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3212             :   // Convert__imm_95_2__CondCode2_0
    3213             :   { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3214             :   // Convert__imm_95_3__CondCode2_0
    3215             :   { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3216             :   // Convert__imm_95_1__CondCode2_0
    3217             :   { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
    3218             : };
    3219             : 
    3220       20310 : void ARMAsmParser::
    3221             : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
    3222             :                 const OperandVector &Operands) {
    3223             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    3224       20310 :   const uint8_t *Converter = ConversionTable[Kind];
    3225             :   unsigned OpIdx;
    3226       40620 :   Inst.setOpcode(Opcode);
    3227       92795 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    3228       72485 :     OpIdx = *(p + 1);
    3229       72485 :     switch (*p) {
    3230           0 :     default: llvm_unreachable("invalid conversion entry!");
    3231           0 :     case CVT_Reg:
    3232           0 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    3233           0 :       break;
    3234        2197 :     case CVT_Tied:
    3235        2197 :       Inst.addOperand(Inst.getOperand(OpIdx));
    3236             :       break;
    3237       26843 :     case CVT_95_Reg:
    3238       80529 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    3239       26843 :       break;
    3240        4353 :     case CVT_95_addCCOutOperands:
    3241       13059 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addCCOutOperands(Inst, 1);
    3242        4353 :       break;
    3243       16078 :     case CVT_95_addCondCodeOperands:
    3244       48234 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2);
    3245       16078 :       break;
    3246         241 :     case CVT_95_addRegShiftedRegOperands:
    3247         723 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3);
    3248         241 :       break;
    3249        1066 :     case CVT_95_addModImmOperands:
    3250        3198 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmOperands(Inst, 1);
    3251        1066 :       break;
    3252          33 :     case CVT_95_addModImmNotOperands:
    3253          99 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1);
    3254          33 :       break;
    3255         618 :     case CVT_95_addRegShiftedImmOperands:
    3256        1854 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2);
    3257         618 :       break;
    3258        3423 :     case CVT_95_addImmOperands:
    3259       10269 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    3260             :       break;
    3261          17 :     case CVT_95_addT2SOImmNotOperands:
    3262          51 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1);
    3263          17 :       break;
    3264          35 :     case CVT_95_addImm0_95_508s4Operands:
    3265         105 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1);
    3266          35 :       break;
    3267         185 :     case CVT_regSP:
    3268         370 :       Inst.addOperand(MCOperand::createReg(ARM::SP));
    3269         185 :       break;
    3270           6 :     case CVT_95_addImm0_95_508s4NegOperands:
    3271          18 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1);
    3272           6 :       break;
    3273           8 :     case CVT_95_addImm0_95_4095NegOperands:
    3274          24 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1);
    3275           8 :       break;
    3276           2 :     case CVT_95_addThumbModImmNeg8_95_255Operands:
    3277           6 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1);
    3278           2 :       break;
    3279          14 :     case CVT_95_addT2SOImmNegOperands:
    3280          42 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1);
    3281          14 :       break;
    3282          18 :     case CVT_95_addModImmNegOperands:
    3283          54 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1);
    3284          18 :       break;
    3285          14 :     case CVT_95_addImm0_95_1020s4Operands:
    3286          42 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1);
    3287          14 :       break;
    3288           2 :     case CVT_95_addThumbModImmNeg1_95_7Operands:
    3289           6 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1);
    3290           2 :       break;
    3291          25 :     case CVT_95_addUnsignedOffset_95_b8s2Operands:
    3292          75 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1);
    3293          25 :       break;
    3294          26 :     case CVT_95_addAdrLabelOperands:
    3295          78 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
    3296          26 :       break;
    3297         167 :     case CVT_95_addARMBranchTargetOperands:
    3298         501 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1);
    3299             :       break;
    3300         307 :     case CVT_cvtThumbBranches:
    3301         307 :       cvtThumbBranches(Inst, Operands);
    3302         307 :       break;
    3303          34 :     case CVT_95_addBitfieldOperands:
    3304         102 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1);
    3305          34 :       break;
    3306         957 :     case CVT_imm_95_0:
    3307        1914 :       Inst.addOperand(MCOperand::createImm(0));
    3308         957 :       break;
    3309         122 :     case CVT_95_addThumbBranchTargetOperands:
    3310         366 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1);
    3311             :       break;
    3312         847 :     case CVT_95_addCoprocNumOperands:
    3313        2541 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1);
    3314             :       break;
    3315         944 :     case CVT_95_addCoprocRegOperands:
    3316        2832 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1);
    3317             :       break;
    3318          39 :     case CVT_95_addProcIFlagsOperands:
    3319         117 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1);
    3320             :       break;
    3321          24 :     case CVT_imm_95_15:
    3322          48 :       Inst.addOperand(MCOperand::createImm(15));
    3323          24 :       break;
    3324         254 :     case CVT_95_addMemBarrierOptOperands:
    3325         762 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1);
    3326             :       break;
    3327           2 :     case CVT_imm_95_16:
    3328           4 :       Inst.addOperand(MCOperand::createImm(16));
    3329           2 :       break;
    3330          35 :     case CVT_95_addFPImmOperands:
    3331         105 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
    3332          35 :       break;
    3333          72 :     case CVT_95_addDPRRegListOperands:
    3334         216 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1);
    3335             :       break;
    3336          16 :     case CVT_imm_95_1:
    3337          32 :       Inst.addOperand(MCOperand::createImm(1));
    3338          16 :       break;
    3339          18 :     case CVT_95_addInstSyncBarrierOptOperands:
    3340          54 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1);
    3341             :       break;
    3342        2766 :     case CVT_95_addITCondCodeOperands:
    3343        8298 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1);
    3344             :       break;
    3345        2766 :     case CVT_95_addITMaskOperands:
    3346        8298 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addITMaskOperands(Inst, 1);
    3347             :       break;
    3348         674 :     case CVT_95_addMemNoOffsetOperands:
    3349        2022 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1);
    3350         674 :       break;
    3351         457 :     case CVT_95_addAddrMode5Operands:
    3352        1371 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2);
    3353         457 :       break;
    3354          78 :     case CVT_95_addCoprocOptionOperands:
    3355         234 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1);
    3356             :       break;
    3357         208 :     case CVT_95_addPostIdxImm8s4Operands:
    3358         624 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1);
    3359         208 :       break;
    3360         589 :     case CVT_95_addRegListOperands:
    3361        1767 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
    3362         589 :       break;
    3363          35 :     case CVT_95_addThumbMemPCOperands:
    3364         105 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1);
    3365          35 :       break;
    3366         376 :     case CVT_95_addConstPoolAsmImmOperands:
    3367        1128 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1);
    3368             :       break;
    3369          31 :     case CVT_95_addMemThumbRIs4Operands:
    3370          93 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2);
    3371          31 :       break;
    3372          33 :     case CVT_95_addMemThumbRROperands:
    3373          99 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2);
    3374          33 :       break;
    3375          25 :     case CVT_95_addMemThumbSPIOperands:
    3376          75 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2);
    3377          25 :       break;
    3378          49 :     case CVT_95_addMemImm12OffsetOperands:
    3379         147 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2);
    3380          49 :       break;
    3381          33 :     case CVT_95_addMemNegImm8OffsetOperands:
    3382          99 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNegImm8OffsetOperands(Inst, 2);
    3383             :       break;
    3384          59 :     case CVT_95_addMemRegOffsetOperands:
    3385         177 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3);
    3386          59 :       break;
    3387         250 :     case CVT_95_addMemUImm12OffsetOperands:
    3388         750 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2);
    3389         250 :       break;
    3390         251 :     case CVT_95_addT2MemRegOffsetOperands:
    3391         753 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3);
    3392         251 :       break;
    3393          51 :     case CVT_95_addMemPCRelImm12Operands:
    3394         153 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1);
    3395             :       break;
    3396          74 :     case CVT_95_addMemImm8OffsetOperands:
    3397         222 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8OffsetOperands(Inst, 2);
    3398          74 :       break;
    3399          27 :     case CVT_95_addAM2OffsetImmOperands:
    3400          81 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2);
    3401          27 :       break;
    3402          36 :     case CVT_95_addPostIdxRegShiftedOperands:
    3403         108 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2);
    3404          36 :       break;
    3405          22 :     case CVT_95_addMemThumbRIs1Operands:
    3406          66 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2);
    3407          22 :       break;
    3408          40 :     case CVT_95_addMemPosImm8OffsetOperands:
    3409         120 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPosImm8OffsetOperands(Inst, 2);
    3410             :       break;
    3411          99 :     case CVT_95_addMemImm8s4OffsetOperands:
    3412         297 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2);
    3413          99 :       break;
    3414          85 :     case CVT_95_addAddrMode3Operands:
    3415         255 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3);
    3416          85 :       break;
    3417          52 :     case CVT_95_addAM3OffsetOperands:
    3418         156 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2);
    3419          52 :       break;
    3420          40 :     case CVT_95_addMemImm0_95_1020s4OffsetOperands:
    3421         120 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2);
    3422          40 :       break;
    3423          26 :     case CVT_95_addMemThumbRIs2Operands:
    3424          78 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2);
    3425          26 :       break;
    3426          12 :     case CVT_95_addPostIdxRegOperands:
    3427          36 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2);
    3428          12 :       break;
    3429          16 :     case CVT_95_addPostIdxImm8Operands:
    3430          48 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1);
    3431          16 :       break;
    3432          51 :     case CVT_reg0:
    3433         102 :       Inst.addOperand(MCOperand::createReg(0));
    3434          51 :       break;
    3435          75 :     case CVT_regCPSR:
    3436         150 :       Inst.addOperand(MCOperand::createReg(ARM::CPSR));
    3437          75 :       break;
    3438          61 :     case CVT_imm_95_14:
    3439         122 :       Inst.addOperand(MCOperand::createImm(14));
    3440          61 :       break;
    3441         132 :     case CVT_95_addBankedRegOperands:
    3442         396 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1);
    3443             :       break;
    3444         209 :     case CVT_95_addMSRMaskOperands:
    3445         627 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1);
    3446             :       break;
    3447          16 :     case CVT_cvtThumbMultiply:
    3448          16 :       cvtThumbMultiply(Inst, Operands);
    3449          16 :       break;
    3450          68 :     case CVT_regR8:
    3451         136 :       Inst.addOperand(MCOperand::createReg(ARM::R8));
    3452          68 :       break;
    3453           4 :     case CVT_regR0:
    3454           8 :       Inst.addOperand(MCOperand::createReg(ARM::R0));
    3455           4 :       break;
    3456           8 :     case CVT_95_addPKHASRImmOperands:
    3457          24 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1);
    3458           8 :       break;
    3459         122 :     case CVT_95_addImm1_95_32Operands:
    3460         366 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1);
    3461         122 :       break;
    3462          16 :     case CVT_imm_95_4:
    3463          32 :       Inst.addOperand(MCOperand::createImm(4));
    3464          16 :       break;
    3465           4 :     case CVT_imm_95_5:
    3466           8 :       Inst.addOperand(MCOperand::createImm(5));
    3467           4 :       break;
    3468          28 :     case CVT_95_addShifterImmOperands:
    3469          84 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1);
    3470             :       break;
    3471          11 :     case CVT_95_addImm1_95_16Operands:
    3472          33 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1);
    3473          11 :       break;
    3474         218 :     case CVT_95_addRotImmOperands:
    3475         654 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addRotImmOperands(Inst, 1);
    3476             :       break;
    3477           7 :     case CVT_95_addMemTBBOperands:
    3478          21 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2);
    3479           7 :       break;
    3480           7 :     case CVT_95_addMemTBHOperands:
    3481          21 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2);
    3482           7 :       break;
    3483           4 :     case CVT_95_addNEONi16splatNotOperands:
    3484          12 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1);
    3485           4 :       break;
    3486           8 :     case CVT_95_addNEONi32splatNotOperands:
    3487          24 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1);
    3488           8 :       break;
    3489          16 :     case CVT_95_addNEONi16splatOperands:
    3490          48 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1);
    3491          16 :       break;
    3492          11 :     case CVT_95_addNEONi32splatOperands:
    3493          33 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1);
    3494          11 :       break;
    3495          16 :     case CVT_95_addFBits16Operands:
    3496          48 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits16Operands(Inst, 1);
    3497          16 :       break;
    3498          16 :     case CVT_95_addFBits32Operands:
    3499          48 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits32Operands(Inst, 1);
    3500          16 :       break;
    3501          66 :     case CVT_95_addVectorIndex16Operands:
    3502         198 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1);
    3503             :       break;
    3504          79 :     case CVT_95_addVectorIndex32Operands:
    3505         237 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1);
    3506             :       break;
    3507          18 :     case CVT_95_addVectorIndex8Operands:
    3508          54 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1);
    3509             :       break;
    3510        1075 :     case CVT_95_addVecListOperands:
    3511        3225 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListOperands(Inst, 1);
    3512        1075 :       break;
    3513          24 :     case CVT_95_addDupAlignedMemory16Operands:
    3514          72 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2);
    3515             :       break;
    3516         289 :     case CVT_95_addAlignedMemory64or128Operands:
    3517         867 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2);
    3518             :       break;
    3519         393 :     case CVT_95_addAlignedMemory64or128or256Operands:
    3520        1179 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2);
    3521             :       break;
    3522         346 :     case CVT_95_addAlignedMemory64Operands:
    3523        1038 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2);
    3524             :       break;
    3525         327 :     case CVT_95_addVecListIndexedOperands:
    3526         981 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2);
    3527         327 :       break;
    3528          38 :     case CVT_95_addAlignedMemory16Operands:
    3529         114 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2);
    3530             :       break;
    3531          42 :     case CVT_95_addDupAlignedMemory32Operands:
    3532         126 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2);
    3533             :       break;
    3534          66 :     case CVT_95_addAlignedMemory32Operands:
    3535         198 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2);
    3536             :       break;
    3537          48 :     case CVT_95_addDupAlignedMemoryNoneOperands:
    3538         144 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2);
    3539             :       break;
    3540          80 :     case CVT_95_addAlignedMemoryNoneOperands:
    3541         240 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2);
    3542             :       break;
    3543           0 :     case CVT_95_addAlignedMemoryOperands:
    3544           0 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2);
    3545           0 :       break;
    3546          36 :     case CVT_95_addDupAlignedMemory64Operands:
    3547         108 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2);
    3548             :       break;
    3549          24 :     case CVT_95_addDupAlignedMemory64or128Operands:
    3550          72 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2);
    3551             :       break;
    3552          18 :     case CVT_95_addSPRRegListOperands:
    3553          54 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1);
    3554             :       break;
    3555          16 :     case CVT_95_addAddrMode5FP16Operands:
    3556          48 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2);
    3557          16 :       break;
    3558          38 :     case CVT_95_addNEONi32vmovOperands:
    3559         114 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1);
    3560          38 :       break;
    3561           6 :     case CVT_95_addNEONvmovByteReplicateOperands:
    3562          18 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovByteReplicateOperands(Inst, 1);
    3563           6 :       break;
    3564           0 :     case CVT_95_addNEONi32vmovNegOperands:
    3565           0 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1);
    3566           0 :       break;
    3567           4 :     case CVT_95_addNEONi64splatOperands:
    3568          12 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1);
    3569           4 :       break;
    3570           4 :     case CVT_95_addNEONi8splatOperands:
    3571          12 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1);
    3572           4 :       break;
    3573           6 :     case CVT_95_addNEONinvByteReplicateOperands:
    3574          18 :       static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONinvByteReplicateOperands(Inst, 1);
    3575           6 :       break;
    3576          16 :     case CVT_imm_95_2:
    3577          32 :       Inst.addOperand(MCOperand::createImm(2));
    3578          16 :       break;
    3579          16 :     case CVT_imm_95_3:
    3580          32 :       Inst.addOperand(MCOperand::createImm(3));
    3581          16 :       break;
    3582             :     }
    3583             :   }
    3584       20310 : }
    3585             : 
    3586           0 : void ARMAsmParser::
    3587             : convertToMapAndConstraints(unsigned Kind,
    3588             :                            const OperandVector &Operands) {
    3589             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    3590           0 :   unsigned NumMCOperands = 0;
    3591           0 :   const uint8_t *Converter = ConversionTable[Kind];
    3592           0 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    3593           0 :     switch (*p) {
    3594           0 :     default: llvm_unreachable("invalid conversion entry!");
    3595           0 :     case CVT_Reg:
    3596           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3597           0 :       Operands[*(p + 1)]->setConstraint("r");
    3598           0 :       ++NumMCOperands;
    3599           0 :       break;
    3600           0 :     case CVT_Tied:
    3601           0 :       ++NumMCOperands;
    3602           0 :       break;
    3603           0 :     case CVT_95_Reg:
    3604           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3605           0 :       Operands[*(p + 1)]->setConstraint("r");
    3606           0 :       NumMCOperands += 1;
    3607           0 :       break;
    3608           0 :     case CVT_95_addCCOutOperands:
    3609           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3610           0 :       Operands[*(p + 1)]->setConstraint("m");
    3611           0 :       NumMCOperands += 1;
    3612           0 :       break;
    3613           0 :     case CVT_95_addCondCodeOperands:
    3614           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3615           0 :       Operands[*(p + 1)]->setConstraint("m");
    3616           0 :       NumMCOperands += 2;
    3617           0 :       break;
    3618           0 :     case CVT_95_addRegShiftedRegOperands:
    3619           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3620           0 :       Operands[*(p + 1)]->setConstraint("m");
    3621           0 :       NumMCOperands += 3;
    3622           0 :       break;
    3623           0 :     case CVT_95_addModImmOperands:
    3624           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3625           0 :       Operands[*(p + 1)]->setConstraint("m");
    3626           0 :       NumMCOperands += 1;
    3627           0 :       break;
    3628           0 :     case CVT_95_addModImmNotOperands:
    3629           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3630           0 :       Operands[*(p + 1)]->setConstraint("m");
    3631           0 :       NumMCOperands += 1;
    3632           0 :       break;
    3633           0 :     case CVT_95_addRegShiftedImmOperands:
    3634           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3635           0 :       Operands[*(p + 1)]->setConstraint("m");
    3636           0 :       NumMCOperands += 2;
    3637           0 :       break;
    3638           0 :     case CVT_95_addImmOperands:
    3639           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3640           0 :       Operands[*(p + 1)]->setConstraint("m");
    3641           0 :       NumMCOperands += 1;
    3642           0 :       break;
    3643           0 :     case CVT_95_addT2SOImmNotOperands:
    3644           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3645           0 :       Operands[*(p + 1)]->setConstraint("m");
    3646           0 :       NumMCOperands += 1;
    3647           0 :       break;
    3648           0 :     case CVT_95_addImm0_95_508s4Operands:
    3649           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3650           0 :       Operands[*(p + 1)]->setConstraint("m");
    3651           0 :       NumMCOperands += 1;
    3652           0 :       break;
    3653           0 :     case CVT_regSP:
    3654           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3655           0 :       Operands[*(p + 1)]->setConstraint("m");
    3656           0 :       ++NumMCOperands;
    3657           0 :       break;
    3658           0 :     case CVT_95_addImm0_95_508s4NegOperands:
    3659           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3660           0 :       Operands[*(p + 1)]->setConstraint("m");
    3661           0 :       NumMCOperands += 1;
    3662           0 :       break;
    3663           0 :     case CVT_95_addImm0_95_4095NegOperands:
    3664           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3665           0 :       Operands[*(p + 1)]->setConstraint("m");
    3666           0 :       NumMCOperands += 1;
    3667           0 :       break;
    3668           0 :     case CVT_95_addThumbModImmNeg8_95_255Operands:
    3669           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3670           0 :       Operands[*(p + 1)]->setConstraint("m");
    3671           0 :       NumMCOperands += 1;
    3672           0 :       break;
    3673           0 :     case CVT_95_addT2SOImmNegOperands:
    3674           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3675           0 :       Operands[*(p + 1)]->setConstraint("m");
    3676           0 :       NumMCOperands += 1;
    3677           0 :       break;
    3678           0 :     case CVT_95_addModImmNegOperands:
    3679           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3680           0 :       Operands[*(p + 1)]->setConstraint("m");
    3681           0 :       NumMCOperands += 1;
    3682           0 :       break;
    3683           0 :     case CVT_95_addImm0_95_1020s4Operands:
    3684           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3685           0 :       Operands[*(p + 1)]->setConstraint("m");
    3686           0 :       NumMCOperands += 1;
    3687           0 :       break;
    3688           0 :     case CVT_95_addThumbModImmNeg1_95_7Operands:
    3689           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3690           0 :       Operands[*(p + 1)]->setConstraint("m");
    3691           0 :       NumMCOperands += 1;
    3692           0 :       break;
    3693           0 :     case CVT_95_addUnsignedOffset_95_b8s2Operands:
    3694           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3695           0 :       Operands[*(p + 1)]->setConstraint("m");
    3696           0 :       NumMCOperands += 1;
    3697           0 :       break;
    3698           0 :     case CVT_95_addAdrLabelOperands:
    3699           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3700           0 :       Operands[*(p + 1)]->setConstraint("m");
    3701           0 :       NumMCOperands += 1;
    3702           0 :       break;
    3703           0 :     case CVT_95_addARMBranchTargetOperands:
    3704           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3705           0 :       Operands[*(p + 1)]->setConstraint("m");
    3706           0 :       NumMCOperands += 1;
    3707           0 :       break;
    3708           0 :     case CVT_95_addBitfieldOperands:
    3709           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3710           0 :       Operands[*(p + 1)]->setConstraint("m");
    3711           0 :       NumMCOperands += 1;
    3712           0 :       break;
    3713           0 :     case CVT_imm_95_0:
    3714           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3715           0 :       Operands[*(p + 1)]->setConstraint("");
    3716           0 :       ++NumMCOperands;
    3717           0 :       break;
    3718           0 :     case CVT_95_addThumbBranchTargetOperands:
    3719           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3720           0 :       Operands[*(p + 1)]->setConstraint("m");
    3721           0 :       NumMCOperands += 1;
    3722           0 :       break;
    3723           0 :     case CVT_95_addCoprocNumOperands:
    3724           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3725           0 :       Operands[*(p + 1)]->setConstraint("m");
    3726           0 :       NumMCOperands += 1;
    3727           0 :       break;
    3728           0 :     case CVT_95_addCoprocRegOperands:
    3729           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3730           0 :       Operands[*(p + 1)]->setConstraint("m");
    3731           0 :       NumMCOperands += 1;
    3732           0 :       break;
    3733           0 :     case CVT_95_addProcIFlagsOperands:
    3734           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3735           0 :       Operands[*(p + 1)]->setConstraint("m");
    3736           0 :       NumMCOperands += 1;
    3737           0 :       break;
    3738           0 :     case CVT_imm_95_15:
    3739           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3740           0 :       Operands[*(p + 1)]->setConstraint("");
    3741           0 :       ++NumMCOperands;
    3742           0 :       break;
    3743           0 :     case CVT_95_addMemBarrierOptOperands:
    3744           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3745           0 :       Operands[*(p + 1)]->setConstraint("m");
    3746           0 :       NumMCOperands += 1;
    3747           0 :       break;
    3748           0 :     case CVT_imm_95_16:
    3749           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3750           0 :       Operands[*(p + 1)]->setConstraint("");
    3751           0 :       ++NumMCOperands;
    3752           0 :       break;
    3753           0 :     case CVT_95_addFPImmOperands:
    3754           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3755           0 :       Operands[*(p + 1)]->setConstraint("m");
    3756           0 :       NumMCOperands += 1;
    3757           0 :       break;
    3758           0 :     case CVT_95_addDPRRegListOperands:
    3759           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3760           0 :       Operands[*(p + 1)]->setConstraint("m");
    3761           0 :       NumMCOperands += 1;
    3762           0 :       break;
    3763           0 :     case CVT_imm_95_1:
    3764           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3765           0 :       Operands[*(p + 1)]->setConstraint("");
    3766           0 :       ++NumMCOperands;
    3767           0 :       break;
    3768           0 :     case CVT_95_addInstSyncBarrierOptOperands:
    3769           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3770           0 :       Operands[*(p + 1)]->setConstraint("m");
    3771           0 :       NumMCOperands += 1;
    3772           0 :       break;
    3773           0 :     case CVT_95_addITCondCodeOperands:
    3774           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3775           0 :       Operands[*(p + 1)]->setConstraint("m");
    3776           0 :       NumMCOperands += 1;
    3777           0 :       break;
    3778           0 :     case CVT_95_addITMaskOperands:
    3779           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3780           0 :       Operands[*(p + 1)]->setConstraint("m");
    3781           0 :       NumMCOperands += 1;
    3782           0 :       break;
    3783           0 :     case CVT_95_addMemNoOffsetOperands:
    3784           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3785           0 :       Operands[*(p + 1)]->setConstraint("m");
    3786           0 :       NumMCOperands += 1;
    3787           0 :       break;
    3788           0 :     case CVT_95_addAddrMode5Operands:
    3789           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3790           0 :       Operands[*(p + 1)]->setConstraint("m");
    3791           0 :       NumMCOperands += 2;
    3792           0 :       break;
    3793           0 :     case CVT_95_addCoprocOptionOperands:
    3794           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3795           0 :       Operands[*(p + 1)]->setConstraint("m");
    3796           0 :       NumMCOperands += 1;
    3797           0 :       break;
    3798           0 :     case CVT_95_addPostIdxImm8s4Operands:
    3799           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3800           0 :       Operands[*(p + 1)]->setConstraint("m");
    3801           0 :       NumMCOperands += 1;
    3802           0 :       break;
    3803           0 :     case CVT_95_addRegListOperands:
    3804           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3805           0 :       Operands[*(p + 1)]->setConstraint("m");
    3806           0 :       NumMCOperands += 1;
    3807           0 :       break;
    3808           0 :     case CVT_95_addThumbMemPCOperands:
    3809           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3810           0 :       Operands[*(p + 1)]->setConstraint("m");
    3811           0 :       NumMCOperands += 1;
    3812           0 :       break;
    3813           0 :     case CVT_95_addConstPoolAsmImmOperands:
    3814           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3815           0 :       Operands[*(p + 1)]->setConstraint("m");
    3816           0 :       NumMCOperands += 1;
    3817           0 :       break;
    3818           0 :     case CVT_95_addMemThumbRIs4Operands:
    3819           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3820           0 :       Operands[*(p + 1)]->setConstraint("m");
    3821           0 :       NumMCOperands += 2;
    3822           0 :       break;
    3823           0 :     case CVT_95_addMemThumbRROperands:
    3824           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3825           0 :       Operands[*(p + 1)]->setConstraint("m");
    3826           0 :       NumMCOperands += 2;
    3827           0 :       break;
    3828           0 :     case CVT_95_addMemThumbSPIOperands:
    3829           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3830           0 :       Operands[*(p + 1)]->setConstraint("m");
    3831           0 :       NumMCOperands += 2;
    3832           0 :       break;
    3833           0 :     case CVT_95_addMemImm12OffsetOperands:
    3834           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3835           0 :       Operands[*(p + 1)]->setConstraint("m");
    3836           0 :       NumMCOperands += 2;
    3837           0 :       break;
    3838           0 :     case CVT_95_addMemNegImm8OffsetOperands:
    3839           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3840           0 :       Operands[*(p + 1)]->setConstraint("m");
    3841           0 :       NumMCOperands += 2;
    3842           0 :       break;
    3843           0 :     case CVT_95_addMemRegOffsetOperands:
    3844           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3845           0 :       Operands[*(p + 1)]->setConstraint("m");
    3846           0 :       NumMCOperands += 3;
    3847           0 :       break;
    3848           0 :     case CVT_95_addMemUImm12OffsetOperands:
    3849           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3850           0 :       Operands[*(p + 1)]->setConstraint("m");
    3851           0 :       NumMCOperands += 2;
    3852           0 :       break;
    3853           0 :     case CVT_95_addT2MemRegOffsetOperands:
    3854           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3855           0 :       Operands[*(p + 1)]->setConstraint("m");
    3856           0 :       NumMCOperands += 3;
    3857           0 :       break;
    3858           0 :     case CVT_95_addMemPCRelImm12Operands:
    3859           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3860           0 :       Operands[*(p + 1)]->setConstraint("m");
    3861           0 :       NumMCOperands += 1;
    3862           0 :       break;
    3863           0 :     case CVT_95_addMemImm8OffsetOperands:
    3864           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3865           0 :       Operands[*(p + 1)]->setConstraint("m");
    3866           0 :       NumMCOperands += 2;
    3867           0 :       break;
    3868           0 :     case CVT_95_addAM2OffsetImmOperands:
    3869           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3870           0 :       Operands[*(p + 1)]->setConstraint("m");
    3871           0 :       NumMCOperands += 2;
    3872           0 :       break;
    3873           0 :     case CVT_95_addPostIdxRegShiftedOperands:
    3874           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3875           0 :       Operands[*(p + 1)]->setConstraint("m");
    3876           0 :       NumMCOperands += 2;
    3877           0 :       break;
    3878           0 :     case CVT_95_addMemThumbRIs1Operands:
    3879           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3880           0 :       Operands[*(p + 1)]->setConstraint("m");
    3881           0 :       NumMCOperands += 2;
    3882           0 :       break;
    3883           0 :     case CVT_95_addMemPosImm8OffsetOperands:
    3884           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3885           0 :       Operands[*(p + 1)]->setConstraint("m");
    3886           0 :       NumMCOperands += 2;
    3887           0 :       break;
    3888           0 :     case CVT_95_addMemImm8s4OffsetOperands:
    3889           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3890           0 :       Operands[*(p + 1)]->setConstraint("m");
    3891           0 :       NumMCOperands += 2;
    3892           0 :       break;
    3893           0 :     case CVT_95_addAddrMode3Operands:
    3894           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3895           0 :       Operands[*(p + 1)]->setConstraint("m");
    3896           0 :       NumMCOperands += 3;
    3897           0 :       break;
    3898           0 :     case CVT_95_addAM3OffsetOperands:
    3899           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3900           0 :       Operands[*(p + 1)]->setConstraint("m");
    3901           0 :       NumMCOperands += 2;
    3902           0 :       break;
    3903           0 :     case CVT_95_addMemImm0_95_1020s4OffsetOperands:
    3904           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3905           0 :       Operands[*(p + 1)]->setConstraint("m");
    3906           0 :       NumMCOperands += 2;
    3907           0 :       break;
    3908           0 :     case CVT_95_addMemThumbRIs2Operands:
    3909           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3910           0 :       Operands[*(p + 1)]->setConstraint("m");
    3911           0 :       NumMCOperands += 2;
    3912           0 :       break;
    3913           0 :     case CVT_95_addPostIdxRegOperands:
    3914           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3915           0 :       Operands[*(p + 1)]->setConstraint("m");
    3916           0 :       NumMCOperands += 2;
    3917           0 :       break;
    3918           0 :     case CVT_95_addPostIdxImm8Operands:
    3919           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3920           0 :       Operands[*(p + 1)]->setConstraint("m");
    3921           0 :       NumMCOperands += 1;
    3922           0 :       break;
    3923           0 :     case CVT_reg0:
    3924           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3925           0 :       Operands[*(p + 1)]->setConstraint("m");
    3926           0 :       ++NumMCOperands;
    3927           0 :       break;
    3928           0 :     case CVT_regCPSR:
    3929           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3930           0 :       Operands[*(p + 1)]->setConstraint("m");
    3931           0 :       ++NumMCOperands;
    3932           0 :       break;
    3933           0 :     case CVT_imm_95_14:
    3934           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3935           0 :       Operands[*(p + 1)]->setConstraint("");
    3936           0 :       ++NumMCOperands;
    3937           0 :       break;
    3938           0 :     case CVT_95_addBankedRegOperands:
    3939           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3940           0 :       Operands[*(p + 1)]->setConstraint("m");
    3941           0 :       NumMCOperands += 1;
    3942           0 :       break;
    3943           0 :     case CVT_95_addMSRMaskOperands:
    3944           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3945           0 :       Operands[*(p + 1)]->setConstraint("m");
    3946           0 :       NumMCOperands += 1;
    3947           0 :       break;
    3948           0 :     case CVT_regR8:
    3949           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3950           0 :       Operands[*(p + 1)]->setConstraint("m");
    3951           0 :       ++NumMCOperands;
    3952           0 :       break;
    3953           0 :     case CVT_regR0:
    3954           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3955           0 :       Operands[*(p + 1)]->setConstraint("m");
    3956           0 :       ++NumMCOperands;
    3957           0 :       break;
    3958           0 :     case CVT_95_addPKHASRImmOperands:
    3959           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3960           0 :       Operands[*(p + 1)]->setConstraint("m");
    3961           0 :       NumMCOperands += 1;
    3962           0 :       break;
    3963           0 :     case CVT_95_addImm1_95_32Operands:
    3964           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3965           0 :       Operands[*(p + 1)]->setConstraint("m");
    3966           0 :       NumMCOperands += 1;
    3967           0 :       break;
    3968           0 :     case CVT_imm_95_4:
    3969           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3970           0 :       Operands[*(p + 1)]->setConstraint("");
    3971           0 :       ++NumMCOperands;
    3972           0 :       break;
    3973           0 :     case CVT_imm_95_5:
    3974           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3975           0 :       Operands[*(p + 1)]->setConstraint("");
    3976           0 :       ++NumMCOperands;
    3977           0 :       break;
    3978           0 :     case CVT_95_addShifterImmOperands:
    3979           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3980           0 :       Operands[*(p + 1)]->setConstraint("m");
    3981           0 :       NumMCOperands += 1;
    3982           0 :       break;
    3983           0 :     case CVT_95_addImm1_95_16Operands:
    3984           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3985           0 :       Operands[*(p + 1)]->setConstraint("m");
    3986           0 :       NumMCOperands += 1;
    3987           0 :       break;
    3988           0 :     case CVT_95_addRotImmOperands:
    3989           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3990           0 :       Operands[*(p + 1)]->setConstraint("m");
    3991           0 :       NumMCOperands += 1;
    3992           0 :       break;
    3993           0 :     case CVT_95_addMemTBBOperands:
    3994           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    3995           0 :       Operands[*(p + 1)]->setConstraint("m");
    3996           0 :       NumMCOperands += 2;
    3997           0 :       break;
    3998           0 :     case CVT_95_addMemTBHOperands:
    3999           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4000           0 :       Operands[*(p + 1)]->setConstraint("m");
    4001           0 :       NumMCOperands += 2;
    4002           0 :       break;
    4003           0 :     case CVT_95_addNEONi16splatNotOperands:
    4004           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4005           0 :       Operands[*(p + 1)]->setConstraint("m");
    4006           0 :       NumMCOperands += 1;
    4007           0 :       break;
    4008           0 :     case CVT_95_addNEONi32splatNotOperands:
    4009           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4010           0 :       Operands[*(p + 1)]->setConstraint("m");
    4011           0 :       NumMCOperands += 1;
    4012           0 :       break;
    4013           0 :     case CVT_95_addNEONi16splatOperands:
    4014           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4015           0 :       Operands[*(p + 1)]->setConstraint("m");
    4016           0 :       NumMCOperands += 1;
    4017           0 :       break;
    4018           0 :     case CVT_95_addNEONi32splatOperands:
    4019           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4020           0 :       Operands[*(p + 1)]->setConstraint("m");
    4021           0 :       NumMCOperands += 1;
    4022           0 :       break;
    4023           0 :     case CVT_95_addFBits16Operands:
    4024           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4025           0 :       Operands[*(p + 1)]->setConstraint("m");
    4026           0 :       NumMCOperands += 1;
    4027           0 :       break;
    4028           0 :     case CVT_95_addFBits32Operands:
    4029           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4030           0 :       Operands[*(p + 1)]->setConstraint("m");
    4031           0 :       NumMCOperands += 1;
    4032           0 :       break;
    4033           0 :     case CVT_95_addVectorIndex16Operands:
    4034           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4035           0 :       Operands[*(p + 1)]->setConstraint("m");
    4036           0 :       NumMCOperands += 1;
    4037           0 :       break;
    4038           0 :     case CVT_95_addVectorIndex32Operands:
    4039           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4040           0 :       Operands[*(p + 1)]->setConstraint("m");
    4041           0 :       NumMCOperands += 1;
    4042           0 :       break;
    4043           0 :     case CVT_95_addVectorIndex8Operands:
    4044           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4045           0 :       Operands[*(p + 1)]->setConstraint("m");
    4046           0 :       NumMCOperands += 1;
    4047           0 :       break;
    4048           0 :     case CVT_95_addVecListOperands:
    4049           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4050           0 :       Operands[*(p + 1)]->setConstraint("m");
    4051           0 :       NumMCOperands += 1;
    4052           0 :       break;
    4053           0 :     case CVT_95_addDupAlignedMemory16Operands:
    4054           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4055           0 :       Operands[*(p + 1)]->setConstraint("m");
    4056           0 :       NumMCOperands += 2;
    4057           0 :       break;
    4058           0 :     case CVT_95_addAlignedMemory64or128Operands:
    4059           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4060           0 :       Operands[*(p + 1)]->setConstraint("m");
    4061           0 :       NumMCOperands += 2;
    4062           0 :       break;
    4063           0 :     case CVT_95_addAlignedMemory64or128or256Operands:
    4064           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4065           0 :       Operands[*(p + 1)]->setConstraint("m");
    4066           0 :       NumMCOperands += 2;
    4067           0 :       break;
    4068           0 :     case CVT_95_addAlignedMemory64Operands:
    4069           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4070           0 :       Operands[*(p + 1)]->setConstraint("m");
    4071           0 :       NumMCOperands += 2;
    4072           0 :       break;
    4073           0 :     case CVT_95_addVecListIndexedOperands:
    4074           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4075           0 :       Operands[*(p + 1)]->setConstraint("m");
    4076           0 :       NumMCOperands += 2;
    4077           0 :       break;
    4078           0 :     case CVT_95_addAlignedMemory16Operands:
    4079           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4080           0 :       Operands[*(p + 1)]->setConstraint("m");
    4081           0 :       NumMCOperands += 2;
    4082           0 :       break;
    4083           0 :     case CVT_95_addDupAlignedMemory32Operands:
    4084           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4085           0 :       Operands[*(p + 1)]->setConstraint("m");
    4086           0 :       NumMCOperands += 2;
    4087           0 :       break;
    4088           0 :     case CVT_95_addAlignedMemory32Operands:
    4089           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4090           0 :       Operands[*(p + 1)]->setConstraint("m");
    4091           0 :       NumMCOperands += 2;
    4092           0 :       break;
    4093           0 :     case CVT_95_addDupAlignedMemoryNoneOperands:
    4094           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4095           0 :       Operands[*(p + 1)]->setConstraint("m");
    4096           0 :       NumMCOperands += 2;
    4097           0 :       break;
    4098           0 :     case CVT_95_addAlignedMemoryNoneOperands:
    4099           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4100           0 :       Operands[*(p + 1)]->setConstraint("m");
    4101           0 :       NumMCOperands += 2;
    4102           0 :       break;
    4103           0 :     case CVT_95_addAlignedMemoryOperands:
    4104           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4105           0 :       Operands[*(p + 1)]->setConstraint("m");
    4106           0 :       NumMCOperands += 2;
    4107           0 :       break;
    4108           0 :     case CVT_95_addDupAlignedMemory64Operands:
    4109           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4110           0 :       Operands[*(p + 1)]->setConstraint("m");
    4111           0 :       NumMCOperands += 2;
    4112           0 :       break;
    4113           0 :     case CVT_95_addDupAlignedMemory64or128Operands:
    4114           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4115           0 :       Operands[*(p + 1)]->setConstraint("m");
    4116           0 :       NumMCOperands += 2;
    4117           0 :       break;
    4118           0 :     case CVT_95_addSPRRegListOperands:
    4119           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4120           0 :       Operands[*(p + 1)]->setConstraint("m");
    4121           0 :       NumMCOperands += 1;
    4122           0 :       break;
    4123           0 :     case CVT_95_addAddrMode5FP16Operands:
    4124           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4125           0 :       Operands[*(p + 1)]->setConstraint("m");
    4126           0 :       NumMCOperands += 2;
    4127           0 :       break;
    4128           0 :     case CVT_95_addNEONi32vmovOperands:
    4129           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4130           0 :       Operands[*(p + 1)]->setConstraint("m");
    4131           0 :       NumMCOperands += 1;
    4132           0 :       break;
    4133           0 :     case CVT_95_addNEONvmovByteReplicateOperands:
    4134           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4135           0 :       Operands[*(p + 1)]->setConstraint("m");
    4136           0 :       NumMCOperands += 1;
    4137           0 :       break;
    4138           0 :     case CVT_95_addNEONi32vmovNegOperands:
    4139           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4140           0 :       Operands[*(p + 1)]->setConstraint("m");
    4141           0 :       NumMCOperands += 1;
    4142           0 :       break;
    4143           0 :     case CVT_95_addNEONi64splatOperands:
    4144           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4145           0 :       Operands[*(p + 1)]->setConstraint("m");
    4146           0 :       NumMCOperands += 1;
    4147           0 :       break;
    4148           0 :     case CVT_95_addNEONi8splatOperands:
    4149           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4150           0 :       Operands[*(p + 1)]->setConstraint("m");
    4151           0 :       NumMCOperands += 1;
    4152           0 :       break;
    4153           0 :     case CVT_95_addNEONinvByteReplicateOperands:
    4154           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4155           0 :       Operands[*(p + 1)]->setConstraint("m");
    4156           0 :       NumMCOperands += 1;
    4157           0 :       break;
    4158           0 :     case CVT_imm_95_2:
    4159           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4160           0 :       Operands[*(p + 1)]->setConstraint("");
    4161           0 :       ++NumMCOperands;
    4162           0 :       break;
    4163           0 :     case CVT_imm_95_3:
    4164           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    4165           0 :       Operands[*(p + 1)]->setConstraint("");
    4166           0 :       ++NumMCOperands;
    4167           0 :       break;
    4168             :     }
    4169             :   }
    4170           0 : }
    4171             : 
    4172             : namespace {
    4173             : 
    4174             : /// MatchClassKind - The kinds of classes which participate in
    4175             : /// instruction matching.
    4176             : enum MatchClassKind {
    4177             :   InvalidMatchClass = 0,
    4178             :   OptionalMatchClass = 1,
    4179             :   MCK__DOT_d, // '.d'
    4180             :   MCK__DOT_f, // '.f'
    4181             :   MCK__DOT_s16, // '.s16'
    4182             :   MCK__DOT_s32, // '.s32'
    4183             :   MCK__DOT_s64, // '.s64'
    4184             :   MCK__DOT_s8, // '.s8'
    4185             :   MCK__DOT_u16, // '.u16'
    4186             :   MCK__DOT_u32, // '.u32'
    4187             :   MCK__DOT_u64, // '.u64'
    4188             :   MCK__DOT_u8, // '.u8'
    4189             :   MCK__DOT_f32, // '.f32'
    4190             :   MCK__DOT_f64, // '.f64'
    4191             :   MCK__DOT_i16, // '.i16'
    4192             :   MCK__DOT_i32, // '.i32'
    4193             :   MCK__DOT_i64, // '.i64'
    4194             :   MCK__DOT_i8, // '.i8'
    4195             :   MCK__DOT_p16, // '.p16'
    4196             :   MCK__DOT_p8, // '.p8'
    4197             :   MCK__EXCLAIM_, // '!'
    4198             :   MCK__35_0, // '#0'
    4199             :   MCK__DOT_16, // '.16'
    4200             :   MCK__DOT_32, // '.32'
    4201             :   MCK__DOT_64, // '.64'
    4202             :   MCK__DOT_8, // '.8'
    4203             :   MCK__DOT_f16, // '.f16'
    4204             :   MCK__DOT_p64, // '.p64'
    4205             :   MCK__DOT_w, // '.w'
    4206             :   MCK__91_, // '['
    4207             :   MCK__93_, // ']'
    4208             :   MCK__94_, // '^'
    4209             :   MCK__123_, // '{'
    4210             :   MCK__125_, // '}'
    4211             :   MCK_Reg11, // derived register class
    4212             :   MCK_Reg59, // derived register class
    4213             :   MCK_Reg75, // derived register class
    4214             :   MCK_APSR, // register class 'APSR'
    4215             :   MCK_APSR_NZCV, // register class 'APSR_NZCV'
    4216             :   MCK_CCR, // register class 'CCR,CPSR'
    4217             :   MCK_FPEXC, // register class 'FPEXC'
    4218             :   MCK_FPINST, // register class 'FPINST'
    4219             :   MCK_FPINST2, // register class 'FPINST2'
    4220             :   MCK_FPSCR, // register class 'FPSCR'
    4221             :   MCK_FPSID, // register class 'FPSID'
    4222             :   MCK_GPRsp, // register class 'GPRsp,SP'
    4223             :   MCK_LR, // register class 'LR'
    4224             :   MCK_MVFR0, // register class 'MVFR0'
    4225             :   MCK_MVFR1, // register class 'MVFR1'
    4226             :   MCK_MVFR2, // register class 'MVFR2'
    4227             :   MCK_PC, // register class 'PC'
    4228             :   MCK_SPSR, // register class 'SPSR'
    4229             :   MCK_Reg60, // derived register class
    4230             :   MCK_Reg68, // derived register class
    4231             :   MCK_Reg73, // derived register class
    4232             :   MCK_Reg100, // derived register class
    4233             :   MCK_Reg45, // derived register class
    4234             :   MCK_Reg61, // derived register class
    4235             :   MCK_Reg72, // derived register class
    4236             :   MCK_Reg74, // derived register class
    4237             :   MCK_Reg83, // derived register class
    4238             :   MCK_Reg88, // derived register class
    4239             :   MCK_Reg101, // derived register class
    4240             :   MCK_Reg0, // derived register class
    4241             :   MCK_Reg46, // derived register class
    4242             :   MCK_Reg62, // derived register class
    4243             :   MCK_Reg69, // derived register class
    4244             :   MCK_Reg84, // derived register class
    4245             :   MCK_Reg89, // derived register class
    4246             :   MCK_Reg93, // derived register class
    4247             :   MCK_Reg102, // derived register class
    4248             :   MCK_QPR_8, // register class 'QPR_8'
    4249             :   MCK_Reg57, // derived register class
    4250             :   MCK_Reg63, // derived register class
    4251             :   MCK_tcGPR, // register class 'tcGPR'
    4252             :   MCK_Reg10, // derived register class
    4253             :   MCK_Reg40, // derived register class
    4254             :   MCK_Reg58, // derived register class
    4255             :   MCK_Reg64, // derived register class
    4256             :   MCK_Reg70, // derived register class
    4257             :   MCK_Reg76, // derived register class
    4258             :   MCK_Reg94, // derived register class
    4259             :   MCK_Reg103, // derived register class
    4260             :   MCK_Reg8, // derived register class
    4261             :   MCK_Reg26, // derived register class
    4262             :   MCK_Reg47, // derived register class
    4263             :   MCK_Reg55, // derived register class
    4264             :   MCK_Reg65, // derived register class
    4265             :   MCK_Reg77, // derived register class
    4266             :   MCK_Reg85, // derived register class
    4267             :   MCK_Reg90, // derived register class
    4268             :   MCK_Reg104, // derived register class
    4269             :   MCK_GPRPair, // register class 'GPRPair'
    4270             :   MCK_Reg27, // derived register class
    4271             :   MCK_Reg41, // derived register class
    4272             :   MCK_Reg48, // derived register class
    4273             :   MCK_Reg56, // derived register class
    4274             :   MCK_Reg66, // derived register class
    4275             :   MCK_Reg78, // derived register class
    4276             :   MCK_Reg86, // derived register class
    4277             :   MCK_Reg91, // derived register class
    4278             :   MCK_Reg95, // derived register class
    4279             :   MCK_Reg105, // derived register class
    4280             :   MCK_DPR_8, // register class 'DPR_8'
    4281             :   MCK_QPR_VFP2, // register class 'QPR_VFP2'
    4282             :   MCK_hGPR, // register class 'hGPR'
    4283             :   MCK_tGPR, // register class 'tGPR'
    4284             :   MCK_tGPRwithpc, // register class 'tGPRwithpc'
    4285             :   MCK_Reg96, // derived register class
    4286             :   MCK_Reg53, // derived register class
    4287             :   MCK_QQQQPR, // register class 'QQQQPR'
    4288             :   MCK_Reg42, // derived register class
    4289             :   MCK_Reg54, // derived register class
    4290             :   MCK_Reg79, // derived register class
    4291             :   MCK_Reg97, // derived register class
    4292             :   MCK_Reg106, // derived register class
    4293             :   MCK_rGPR, // register class 'rGPR'
    4294             :   MCK_Reg24, // derived register class
    4295             :   MCK_Reg51, // derived register class
    4296             :   MCK_Reg80, // derived register class
    4297             :   MCK_Reg87, // derived register class
    4298             :   MCK_Reg92, // derived register class
    4299             :   MCK_GPRnopc, // register class 'GPRnopc'
    4300             :   MCK_QQPR, // register class 'QQPR'
    4301             :   MCK_Reg25, // derived register class
    4302             :   MCK_Reg43, // derived register class
    4303             :   MCK_Reg52, // derived register class
    4304             :   MCK_Reg81, // derived register class
    4305             :   MCK_Reg98, // derived register class
    4306             :   MCK_DPR_VFP2, // register class 'DPR_VFP2'
    4307             :   MCK_GPR, // register class 'GPR'
    4308             :   MCK_GPRwithAPSR, // register class 'GPRwithAPSR'
    4309             :   MCK_QPR, // register class 'QPR'
    4310             :   MCK_SPR_8, // register class 'SPR_8'
    4311             :   MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc'
    4312             :   MCK_DQuad, // register class 'DQuad'
    4313             :   MCK_DPairSpc, // register class 'DPairSpc'
    4314             :   MCK_DTriple, // register class 'DTriple'
    4315             :   MCK_DPair, // register class 'DPair'
    4316             :   MCK_DPR, // register class 'DPR'
    4317             :   MCK_SPR, // register class 'SPR'
    4318             :   MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand'
    4319             :   MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand'
    4320             :   MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget'
    4321             :   MCK_AddrMode2, // user defined class 'AddrMode2AsmOperand'
    4322             :   MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand'
    4323             :   MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand'
    4324             :   MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand'
    4325             :   MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand'
    4326             :   MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand'
    4327             :   MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand'
    4328             :   MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand'
    4329             :   MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand'
    4330             :   MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand'
    4331             :   MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand'
    4332             :   MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand'
    4333             :   MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand'
    4334             :   MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand'
    4335             :   MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand'
    4336             :   MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand'
    4337             :   MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand'
    4338             :   MCK_BankedReg, // user defined class 'BankedRegOperand'
    4339             :   MCK_Bitfield, // user defined class 'BitfieldAsmOperand'
    4340             :   MCK_CCOut, // user defined class 'CCOutOperand'
    4341             :   MCK_CondCode, // user defined class 'CondCodeOperand'
    4342             :   MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand'
    4343             :   MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand'
    4344             :   MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand'
    4345             :   MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand'
    4346             :   MCK_FPImm, // user defined class 'FPImmOperand'
    4347             :   MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand'
    4348             :   MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand'
    4349             :   MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand'
    4350             :   MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand'
    4351             :   MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand'
    4352             :   MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand'
    4353             :   MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand'
    4354             :   MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand'
    4355             :   MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand'
    4356             :   MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand'
    4357             :   MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand'
    4358             :   MCK_Imm16, // user defined class 'Imm16AsmOperand'
    4359             :   MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand'
    4360             :   MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand'
    4361             :   MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand'
    4362             :   MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand'
    4363             :   MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand'
    4364             :   MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand'
    4365             :   MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand'
    4366             :   MCK_Imm32, // user defined class 'Imm32AsmOperand'
    4367             :   MCK_Imm8, // user defined class 'Imm8AsmOperand'
    4368             :   MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand'
    4369             :   MCK_Imm, // user defined class 'ImmAsmOperand'
    4370             :   MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand'
    4371             :   MCK_MSRMask, // user defined class 'MSRMaskOperand'
    4372             :   MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand'
    4373             :   MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand'
    4374             :   MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand'
    4375             :   MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand'
    4376             :   MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand'
    4377             :   MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand'
    4378             :   MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand'
    4379             :   MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand'
    4380             :   MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand'
    4381             :   MCK_ModImm, // user defined class 'ModImmAsmOperand'
    4382             :   MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand'
    4383             :   MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand'
    4384             :   MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand'
    4385             :   MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand'
    4386             :   MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand'
    4387             :   MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand'
    4388             :   MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand'
    4389             :   MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand'
    4390             :   MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand'
    4391             :   MCK_RegList, // user defined class 'RegListAsmOperand'
    4392             :   MCK_RotImm, // user defined class 'RotImmAsmOperand'
    4393             :   MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand'
    4394             :   MCK_SetEndImm, // user defined class 'SetEndAsmOperand'
    4395             :   MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand'
    4396             :   MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand'
    4397             :   MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand'
    4398             :   MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget'
    4399             :   MCK_ThumbMemPC, // user defined class 'ThumbMemPC'
    4400             :   MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand'
    4401             :   MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand'
    4402             :   MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand'
    4403             :   MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2'
    4404             :   MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand'
    4405             :   MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand'
    4406             :   MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand'
    4407             :   MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand'
    4408             :   MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand'
    4409             :   MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand'
    4410             :   MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand'
    4411             :   MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand'
    4412             :   MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand'
    4413             :   MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand'
    4414             :   MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand'
    4415             :   MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand'
    4416             :   MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand'
    4417             :   MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand'
    4418             :   MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand'
    4419             :   MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand'
    4420             :   MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand'
    4421             :   MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand'
    4422             :   MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand'
    4423             :   MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand'
    4424             :   MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand'
    4425             :   MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand'
    4426             :   MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand'
    4427             :   MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand'
    4428             :   MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand'
    4429             :   MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand'
    4430             :   MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand'
    4431             :   MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand'
    4432             :   MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand'
    4433             :   MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand'
    4434             :   MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand'
    4435             :   MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand'
    4436             :   MCK_VectorIndex16, // user defined class 'VectorIndex16Operand'
    4437             :   MCK_VectorIndex32, // user defined class 'VectorIndex32Operand'
    4438             :   MCK_VectorIndex8, // user defined class 'VectorIndex8Operand'
    4439             :   MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand'
    4440             :   MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand'
    4441             :   MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand'
    4442             :   MCK_FBits16, // user defined class 'fbits16_asm_operand'
    4443             :   MCK_FBits32, // user defined class 'fbits32_asm_operand'
    4444             :   MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand'
    4445             :   MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand'
    4446             :   MCK_ITMask, // user defined class 'it_mask_asmoperand'
    4447             :   MCK_ITCondCode, // user defined class 'it_pred_asmoperand'
    4448             :   MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand'
    4449             :   MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand'
    4450             :   MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand'
    4451             :   MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand'
    4452             :   MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand'
    4453             :   MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand'
    4454             :   MCK_NEONi16vmovByteReplicate, // user defined class 'nImmVMOVI16AsmOperandByteReplicate'
    4455             :   MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand'
    4456             :   MCK_NEONi32vmovByteReplicate, // user defined class 'nImmVMOVI32AsmOperandByteReplicate'
    4457             :   MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand'
    4458             :   MCK_NEONi16invByteReplicate, // user defined class 'nImmVMVNI16AsmOperandByteReplicate'
    4459             :   MCK_NEONi32invByteReplicate, // user defined class 'nImmVMVNI32AsmOperandByteReplicate'
    4460             :   MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand'
    4461             :   MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand'
    4462             :   MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand'
    4463             :   MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand'
    4464             :   MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand'
    4465             :   MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand'
    4466             :   MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand'
    4467             :   MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand'
    4468             :   MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand'
    4469             :   MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand'
    4470             :   MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand'
    4471             :   MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand'
    4472             :   MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand'
    4473             :   MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand'
    4474             :   MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand'
    4475             :   MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand'
    4476             :   MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand'
    4477             :   MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand'
    4478             :   MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand'
    4479             :   NumMatchClassKinds
    4480             : };
    4481             : 
    4482             : }
    4483             : 
    4484      227254 : static MatchClassKind matchTokenString(StringRef Name) {
    4485      227254 :   switch (Name.size()) {
    4486             :   default: break;
    4487        2073 :   case 1:        // 6 strings to match.
    4488        4146 :     switch (Name[0]) {
    4489             :     default: break;
    4490             :     case '!':    // 1 string to match.
    4491             :       return MCK__EXCLAIM_;      // "!"
    4492           0 :     case '[':    // 1 string to match.
    4493           0 :       return MCK__91_;   // "["
    4494           0 :     case ']':    // 1 string to match.
    4495           0 :       return MCK__93_;   // "]"
    4496           8 :     case '^':    // 1 string to match.
    4497           8 :       return MCK__94_;   // "^"
    4498           0 :     case '{':    // 1 string to match.
    4499           0 :       return MCK__123_;  // "{"
    4500           0 :     case '}':    // 1 string to match.
    4501           0 :       return MCK__125_;  // "}"
    4502             :     }
    4503             :     break;
    4504       58666 :   case 2:        // 5 strings to match.
    4505      117332 :     switch (Name[0]) {
    4506             :     default: break;
    4507           0 :     case '#':    // 1 string to match.
    4508           0 :       if (Name[1] != '0')
    4509             :         break;
    4510             :       return MCK__35_0;  // "#0"
    4511       58666 :     case '.':    // 4 strings to match.
    4512      117332 :       switch (Name[1]) {
    4513             :       default: break;
    4514             :       case '8':  // 1 string to match.
    4515             :         return MCK__DOT_8;       // ".8"
    4516          72 :       case 'd':  // 1 string to match.
    4517          72 :         return MCK__DOT_d;       // ".d"
    4518          66 :       case 'f':  // 1 string to match.
    4519          66 :         return MCK__DOT_f;       // ".f"
    4520       17175 :       case 'w':  // 1 string to match.
    4521       17175 :         return MCK__DOT_w;       // ".w"
    4522             :       }
    4523             :       break;
    4524             :     }
    4525             :     break;
    4526       97746 :   case 3:        // 7 strings to match.
    4527      195492 :     if (Name[0] != '.')
    4528             :       break;
    4529      195492 :     switch (Name[1]) {
    4530             :     default: break;
    4531       35005 :     case '1':    // 1 string to match.
    4532       70010 :       if (Name[2] != '6')
    4533             :         break;
    4534             :       return MCK__DOT_16;        // ".16"
    4535       43814 :     case '3':    // 1 string to match.
    4536       87628 :       if (Name[2] != '2')
    4537             :         break;
    4538             :       return MCK__DOT_32;        // ".32"
    4539        9166 :     case '6':    // 1 string to match.
    4540       18332 :       if (Name[2] != '4')
    4541             :         break;
    4542             :       return MCK__DOT_64;        // ".64"
    4543        1411 :     case 'i':    // 1 string to match.
    4544        2822 :       if (Name[2] != '8')
    4545             :         break;
    4546             :       return MCK__DOT_i8;        // ".i8"
    4547         870 :     case 'p':    // 1 string to match.
    4548        1740 :       if (Name[2] != '8')
    4549             :         break;
    4550             :       return MCK__DOT_p8;        // ".p8"
    4551        3422 :     case 's':    // 1 string to match.
    4552        6844 :       if (Name[2] != '8')
    4553             :         break;
    4554             :       return MCK__DOT_s8;        // ".s8"
    4555        4058 :     case 'u':    // 1 string to match.
    4556        8116 :       if (Name[2] != '8')
    4557             :         break;
    4558             :       return MCK__DOT_u8;        // ".u8"
    4559             :     }
    4560             :     break;
    4561       68769 :   case 4:        // 14 strings to match.
    4562      137538 :     if (Name[0] != '.')
    4563             :       break;
    4564      137538 :     switch (Name[1]) {
    4565             :     default: break;
    4566       34849 :     case 'f':    // 3 strings to match.
    4567       69698 :       switch (Name[2]) {
    4568             :       default: break;
    4569       20358 :       case '1':  // 1 string to match.
    4570       40716 :         if (Name[3] != '6')
    4571             :           break;
    4572             :         return MCK__DOT_f16;     // ".f16"
    4573        8430 :       case '3':  // 1 string to match.
    4574       16860 :         if (Name[3] != '2')
    4575             :           break;
    4576             :         return MCK__DOT_f32;     // ".f32"
    4577        6061 :       case '6':  // 1 string to match.
    4578       12122 :         if (Name[3] != '4')
    4579             :           break;
    4580             :         return MCK__DOT_f64;     // ".f64"
    4581             :       }
    4582             :       break;
    4583        4632 :     case 'i':    // 3 strings to match.
    4584        9264 :       switch (Name[2]) {
    4585             :       default: break;
    4586        1564 :       case '1':  // 1 string to match.
    4587        3128 :         if (Name[3] != '6')
    4588             :           break;
    4589             :         return MCK__DOT_i16;     // ".i16"
    4590        2471 :       case '3':  // 1 string to match.
    4591        4942 :         if (Name[3] != '2')
    4592             :           break;
    4593             :         return MCK__DOT_i32;     // ".i32"
    4594         597 :       case '6':  // 1 string to match.
    4595        1194 :         if (Name[3] != '4')
    4596             :           break;
    4597             :         return MCK__DOT_i64;     // ".i64"
    4598             :       }
    4599             :       break;
    4600         368 :     case 'p':    // 2 strings to match.
    4601         736 :       switch (Name[2]) {
    4602             :       default: break;
    4603         256 :       case '1':  // 1 string to match.
    4604         512 :         if (Name[3] != '6')
    4605             :           break;
    4606             :         return MCK__DOT_p16;     // ".p16"
    4607         112 :       case '6':  // 1 string to match.
    4608         224 :         if (Name[3] != '4')
    4609             :           break;
    4610             :         return MCK__DOT_p64;     // ".p64"
    4611             :       }
    4612             :       break;
    4613       12525 :     case 's':    // 3 strings to match.
    4614       25050 :       switch (Name[2]) {
    4615             :       default: break;
    4616        5262 :       case '1':  // 1 string to match.
    4617       10524 :         if (Name[3] != '6')
    4618             :           break;
    4619             :         return MCK__DOT_s16;     // ".s16"
    4620        5922 :       case '3':  // 1 string to match.
    4621       11844 :         if (Name[3] != '2')
    4622             :           break;
    4623             :         return MCK__DOT_s32;     // ".s32"
    4624        1341 :       case '6':  // 1 string to match.
    4625        2682 :         if (Name[3] != '4')
    4626             :           break;
    4627             :         return MCK__DOT_s64;     // ".s64"
    4628             :       }
    4629             :       break;
    4630       16395 :     case 'u':    // 3 strings to match.
    4631       32790 :       switch (Name[2]) {
    4632             :       default: break;
    4633        6717 :       case '1':  // 1 string to match.
    4634       13434 :         if (Name[3] != '6')
    4635             :           break;
    4636             :         return MCK__DOT_u16;     // ".u16"
    4637        7677 :       case '3':  // 1 string to match.
    4638       15354 :         if (Name[3] != '2')
    4639             :           break;
    4640             :         return MCK__DOT_u32;     // ".u32"
    4641        2001 :       case '6':  // 1 string to match.
    4642        4002 :         if (Name[3] != '4')
    4643             :           break;
    4644             :         return MCK__DOT_u64;     // ".u64"
    4645             :       }
    4646             :       break;
    4647             :     }
    4648             :     break;
    4649             :   }
    4650             :   return InvalidMatchClass;
    4651             : }
    4652             : 
    4653             : /// isSubclass - Compute whether \p A is a subclass of \p B.
    4654      657552 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
    4655      657552 :   if (A == B)
    4656             :     return true;
    4657             : 
    4658      587159 :   switch (A) {
    4659             :   default:
    4660             :     return false;
    4661             : 
    4662          72 :   case MCK__DOT_d:
    4663          72 :     switch (B) {
    4664             :     default: return false;
    4665           0 :     case MCK__DOT_f64: return true;
    4666          12 :     case MCK__DOT_64: return true;
    4667             :     }
    4668             : 
    4669          66 :   case MCK__DOT_f:
    4670          66 :     switch (B) {
    4671             :     default: return false;
    4672           0 :     case MCK__DOT_f32: return true;
    4673          14 :     case MCK__DOT_32: return true;
    4674             :     }
    4675             : 
    4676       11325 :   case MCK__DOT_s16:
    4677       11325 :     switch (B) {
    4678             :     default: return false;
    4679          60 :     case MCK__DOT_i16: return true;
    4680          73 :     case MCK__DOT_16: return true;
    4681             :     }
    4682             : 
    4683       12081 :   case MCK__DOT_s32:
    4684       12081 :     switch (B) {
    4685             :     default: return false;
    4686          38 :     case MCK__DOT_i32: return true;
    4687          61 :     case MCK__DOT_32: return true;
    4688             :     }
    4689             : 
    4690        2682 :   case MCK__DOT_s64:
    4691        2682 :     switch (B) {
    4692             :     default: return false;
    4693           1 :     case MCK__DOT_i64: return true;
    4694          12 :     case MCK__DOT_64: return true;
    4695             :     }
    4696             : 
    4697        6110 :   case MCK__DOT_s8:
    4698        6110 :     switch (B) {
    4699             :     default: return false;
    4700          15 :     case MCK__DOT_i8: return true;
    4701          82 :     case MCK__DOT_8: return true;
    4702             :     }
    4703             : 
    4704       10491 :   case MCK__DOT_u16:
    4705       10491 :     switch (B) {
    4706             :     default: return false;
    4707          65 :     case MCK__DOT_i16: return true;
    4708         216 :     case MCK__DOT_16: return true;
    4709             :     }
    4710             : 
    4711       11349 :   case MCK__DOT_u32:
    4712       11349 :     switch (B) {
    4713             :     default: return false;
    4714          53 :     case MCK__DOT_i32: return true;
    4715         150 :     case MCK__DOT_32: return true;
    4716             :     }
    4717             : 
    4718        2703 :   case MCK__DOT_u64:
    4719        2703 :     switch (B) {
    4720             :     default: return false;
    4721          10 :     case MCK__DOT_i64: return true;
    4722          12 :     case MCK__DOT_64: return true;
    4723             :     }
    4724             : 
    4725        5175 :   case MCK__DOT_u8:
    4726        5175 :     switch (B) {
    4727             :     default: return false;
    4728          12 :     case MCK__DOT_i8: return true;
    4729          98 :     case MCK__DOT_8: return true;
    4730             :     }
    4731             : 
    4732       16099 :   case MCK__DOT_f32:
    4733       16099 :     return B == MCK__DOT_32;
    4734             : 
    4735        7894 :   case MCK__DOT_f64:
    4736        7894 :     return B == MCK__DOT_64;
    4737             : 
    4738        3478 :   case MCK__DOT_i16:
    4739        3478 :     return B == MCK__DOT_16;
    4740             : 
    4741        4200 :   case MCK__DOT_i32:
    4742        4200 :     return B == MCK__DOT_32;
    4743             : 
    4744        1062 :   case MCK__DOT_i64:
    4745        1062 :     return B == MCK__DOT_64;
    4746             : 
    4747        2391 :   case MCK__DOT_i8:
    4748        2391 :     return B == MCK__DOT_8;
    4749             : 
    4750         256 :   case MCK__DOT_p16:
    4751         256 :     return B == MCK__DOT_16;
    4752             : 
    4753        1095 :   case MCK__DOT_p8:
    4754        1095 :     return B == MCK__DOT_8;
    4755             : 
    4756        1043 :   case MCK_Reg11:
    4757             :     switch (B) {
    4758             :     default: return false;
    4759             :     case MCK_tcGPR: return true;
    4760             :     case MCK_Reg10: return true;
    4761             :     case MCK_Reg8: return true;
    4762             :     case MCK_hGPR: return true;
    4763             :     case MCK_rGPR: return true;
    4764             :     case MCK_GPRnopc: return true;
    4765             :     case MCK_GPR: return true;
    4766             :     case MCK_GPRwithAPSR: return true;
    4767             :     }
    4768             : 
    4769           0 :   case MCK_Reg59:
    4770             :     switch (B) {
    4771             :     default: return false;
    4772             :     case MCK_Reg60: return true;
    4773             :     case MCK_Reg61: return true;
    4774             :     case MCK_Reg62: return true;
    4775             :     case MCK_Reg63: return true;
    4776             :     case MCK_Reg64: return true;
    4777             :     case MCK_Reg65: return true;
    4778             :     case MCK_Reg66: return true;
    4779             :     case MCK_QQQQPR: return true;
    4780             :     }
    4781             : 
    4782           0 :   case MCK_Reg75:
    4783           0 :     switch (B) {
    4784             :     default: return false;
    4785           0 :     case MCK_Reg72: return true;
    4786           0 :     case MCK_Reg74: return true;
    4787           0 :     case MCK_GPRPair: return true;
    4788             :     }
    4789             : 
    4790          46 :   case MCK_APSR_NZCV:
    4791          46 :     return B == MCK_GPRwithAPSR;
    4792             : 
    4793        4820 :   case MCK_GPRsp:
    4794        4820 :     switch (B) {
    4795             :     default: return false;
    4796           0 :     case MCK_Reg8: return true;
    4797           0 :     case MCK_hGPR: return true;
    4798        1009 :     case MCK_GPRnopc: return true;
    4799        1192 :     case MCK_GPR: return true;
    4800           0 :     case MCK_GPRwithAPSR: return true;
    4801             :     }
    4802             : 
    4803        1157 :   case MCK_LR:
    4804             :     switch (B) {
    4805             :     default: return false;
    4806             :     case MCK_Reg10: return true;
    4807             :     case MCK_Reg8: return true;
    4808             :     case MCK_hGPR: return true;
    4809             :     case MCK_rGPR: return true;
    4810             :     case MCK_GPRnopc: return true;
    4811             :     case MCK_GPR: return true;
    4812             :     case MCK_GPRwithAPSR: return true;
    4813             :     }
    4814             : 
    4815        2125 :   case MCK_PC:
    4816        2125 :     switch (B) {
    4817             :     default: return false;
    4818           0 :     case MCK_hGPR: return true;
    4819           0 :     case MCK_tGPRwithpc: return true;
    4820         543 :     case MCK_GPR: return true;
    4821             :     }
    4822             : 
    4823           0 :   case MCK_Reg60:
    4824             :     switch (B) {
    4825             :     default: return false;
    4826             :     case MCK_Reg61: return true;
    4827             :     case MCK_Reg62: return true;
    4828             :     case MCK_Reg63: return true;
    4829             :     case MCK_Reg64: return true;
    4830             :     case MCK_Reg65: return true;
    4831             :     case MCK_Reg66: return true;
    4832             :     case MCK_QQQQPR: return true;
    4833             :     }
    4834             : 
    4835           7 :   case MCK_Reg68:
    4836           7 :     switch (B) {
    4837             :     default: return false;
    4838           0 :     case MCK_Reg72: return true;
    4839           0 :     case MCK_Reg69: return true;
    4840           0 :     case MCK_Reg70: return true;
    4841           6 :     case MCK_GPRPair: return true;
    4842             :     }
    4843             : 
    4844           4 :   case MCK_Reg73:
    4845           4 :     switch (B) {
    4846             :     default: return false;
    4847           0 :     case MCK_Reg74: return true;
    4848           0 :     case MCK_Reg70: return true;
    4849           4 :     case MCK_GPRPair: return true;
    4850             :     }
    4851             : 
    4852           0 :   case MCK_Reg100:
    4853             :     switch (B) {
    4854             :     default: return false;
    4855             :     case MCK_Reg101: return true;
    4856             :     case MCK_Reg102: return true;
    4857             :     case MCK_Reg57: return true;
    4858             :     case MCK_Reg58: return true;
    4859             :     case MCK_Reg103: return true;
    4860             :     case MCK_Reg55: return true;
    4861             :     case MCK_Reg104: return true;
    4862             :     case MCK_Reg56: return true;
    4863             :     case MCK_Reg105: return true;
    4864             :     case MCK_Reg53: return true;
    4865             :     case MCK_Reg54: return true;
    4866             :     case MCK_Reg106: return true;
    4867             :     case MCK_Reg51: return true;
    4868             :     case MCK_Reg52: return true;
    4869             :     case MCK_DQuad: return true;
    4870             :     }
    4871             : 
    4872           0 :   case MCK_Reg45:
    4873             :     switch (B) {
    4874             :     default: return false;
    4875             :     case MCK_Reg46: return true;
    4876             :     case MCK_Reg57: return true;
    4877             :     case MCK_Reg58: return true;
    4878             :     case MCK_Reg47: return true;
    4879             :     case MCK_Reg55: return true;
    4880             :     case MCK_Reg48: return true;
    4881             :     case MCK_Reg56: return true;
    4882             :     case MCK_Reg53: return true;
    4883             :     case MCK_Reg54: return true;
    4884             :     case MCK_Reg51: return true;
    4885             :     case MCK_QQPR: return true;
    4886             :     case MCK_Reg52: return true;
    4887             :     case MCK_DQuad: return true;
    4888             :     }
    4889             : 
    4890           0 :   case MCK_Reg61:
    4891             :     switch (B) {
    4892             :     default: return false;
    4893             :     case MCK_Reg62: return true;
    4894             :     case MCK_Reg63: return true;
    4895             :     case MCK_Reg64: return true;
    4896             :     case MCK_Reg65: return true;
    4897             :     case MCK_Reg66: return true;
    4898             :     case MCK_QQQQPR: return true;
    4899             :     }
    4900             : 
    4901           0 :   case MCK_Reg72:
    4902           0 :     return B == MCK_GPRPair;
    4903             : 
    4904           0 :   case MCK_Reg74:
    4905           0 :     return B == MCK_GPRPair;
    4906             : 
    4907           0 :   case MCK_Reg83:
    4908             :     switch (B) {
    4909             :     default: return false;
    4910             :     case MCK_Reg84: return true;
    4911             :     case MCK_Reg76: return true;
    4912             :     case MCK_Reg77: return true;
    4913             :     case MCK_Reg85: return true;
    4914             :     case MCK_Reg78: return true;
    4915             :     case MCK_Reg86: return true;
    4916             :     case MCK_Reg79: return true;
    4917             :     case MCK_Reg80: return true;
    4918             :     case MCK_Reg87: return true;
    4919             :     case MCK_Reg81: return true;
    4920             :     case MCK_DTriple: return true;
    4921             :     }
    4922             : 
    4923           0 :   case MCK_Reg88:
    4924             :     switch (B) {
    4925             :     default: return false;
    4926             :     case MCK_Reg89: return true;
    4927             :     case MCK_Reg76: return true;
    4928             :     case MCK_Reg77: return true;
    4929             :     case MCK_Reg90: return true;
    4930             :     case MCK_Reg78: return true;
    4931             :     case MCK_Reg91: return true;
    4932             :     case MCK_Reg79: return true;
    4933             :     case MCK_Reg80: return true;
    4934             :     case MCK_Reg92: return true;
    4935             :     case MCK_Reg81: return true;
    4936             :     case MCK_DTriple: return true;
    4937             :     }
    4938             : 
    4939           0 :   case MCK_Reg101:
    4940             :     switch (B) {
    4941             :     default: return false;
    4942             :     case MCK_Reg102: return true;
    4943             :     case MCK_Reg58: return true;
    4944             :     case MCK_Reg103: return true;
    4945             :     case MCK_Reg55: return true;
    4946             :     case MCK_Reg104: return true;
    4947             :     case MCK_Reg56: return true;
    4948             :     case MCK_Reg105: return true;
    4949             :     case MCK_Reg53: return true;
    4950             :     case MCK_Reg54: return true;
    4951             :     case MCK_Reg106: return true;
    4952             :     case MCK_Reg51: return true;
    4953             :     case MCK_Reg52: return true;
    4954             :     case MCK_DQuad: return true;
    4955             :     }
    4956             : 
    4957       70680 :   case MCK_Reg0:
    4958       70680 :     switch (B) {
    4959             :     default: return false;
    4960         112 :     case MCK_tcGPR: return true;
    4961       12558 :     case MCK_tGPR: return true;
    4962           0 :     case MCK_tGPRwithpc: return true;
    4963       15295 :     case MCK_rGPR: return true;
    4964       12227 :     case MCK_GPRnopc: return true;
    4965       15518 :     case MCK_GPR: return true;
    4966          55 :     case MCK_GPRwithAPSR: return true;
    4967             :     }
    4968             : 
    4969           0 :   case MCK_Reg46:
    4970             :     switch (B) {
    4971             :     default: return false;
    4972             :     case MCK_Reg47: return true;
    4973             :     case MCK_Reg55: return true;
    4974             :     case MCK_Reg48: return true;
    4975             :     case MCK_Reg56: return true;
    4976             :     case MCK_Reg53: return true;
    4977             :     case MCK_Reg54: return true;
    4978             :     case MCK_Reg51: return true;
    4979             :     case MCK_QQPR: return true;
    4980             :     case MCK_Reg52: return true;
    4981             :     case MCK_DQuad: return true;
    4982             :     }
    4983             : 
    4984           0 :   case MCK_Reg62:
    4985             :     switch (B) {
    4986             :     default: return false;
    4987             :     case MCK_Reg63: return true;
    4988             :     case MCK_Reg64: return true;
    4989             :     case MCK_Reg65: return true;
    4990             :     case MCK_Reg66: return true;
    4991             :     case MCK_QQQQPR: return true;
    4992             :     }
    4993             : 
    4994          13 :   case MCK_Reg69:
    4995          13 :     switch (B) {
    4996             :     default: return false;
    4997           0 :     case MCK_Reg70: return true;
    4998          12 :     case MCK_GPRPair: return true;
    4999             :     }
    5000             : 
    5001           0 :   case MCK_Reg84:
    5002             :     switch (B) {
    5003             :     default: return false;
    5004             :     case MCK_Reg77: return true;
    5005             :     case MCK_Reg85: return true;
    5006             :     case MCK_Reg78: return true;
    5007             :     case MCK_Reg86: return true;
    5008             :     case MCK_Reg79: return true;
    5009             :     case MCK_Reg80: return true;
    5010             :     case MCK_Reg87: return true;
    5011             :     case MCK_Reg81: return true;
    5012             :     case MCK_DTriple: return true;
    5013             :     }
    5014             : 
    5015           0 :   case MCK_Reg89:
    5016             :     switch (B) {
    5017             :     default: return false;
    5018             :     case MCK_Reg90: return true;
    5019             :     case MCK_Reg78: return true;
    5020             :     case MCK_Reg91: return true;
    5021             :     case MCK_Reg79: return true;
    5022             :     case MCK_Reg80: return true;
    5023             :     case MCK_Reg92: return true;
    5024             :     case MCK_Reg81: return true;
    5025             :     case MCK_DTriple: return true;
    5026             :     }
    5027             : 
    5028           0 :   case MCK_Reg93:
    5029           0 :     switch (B) {
    5030             :     default: return false;
    5031           0 :     case MCK_Reg94: return true;
    5032           0 :     case MCK_Reg95: return true;
    5033           0 :     case MCK_Reg96: return true;
    5034           0 :     case MCK_Reg97: return true;
    5035           0 :     case MCK_Reg98: return true;
    5036           0 :     case MCK_DTripleSpc: return true;
    5037             :     }
    5038             : 
    5039           0 :   case MCK_Reg102:
    5040             :     switch (B) {
    5041             :     default: return false;
    5042             :     case MCK_Reg103: return true;
    5043             :     case MCK_Reg104: return true;
    5044             :     case MCK_Reg56: return true;
    5045             :     case MCK_Reg105: return true;
    5046             :     case MCK_Reg53: return true;
    5047             :     case MCK_Reg54: return true;
    5048             :     case MCK_Reg106: return true;
    5049             :     case MCK_Reg51: return true;
    5050             :     case MCK_Reg52: return true;
    5051             :     case MCK_DQuad: return true;
    5052             :     }
    5053             : 
    5054        3353 :   case MCK_QPR_8:
    5055             :     switch (B) {
    5056             :     default: return false;
    5057             :     case MCK_Reg26: return true;
    5058             :     case MCK_Reg27: return true;
    5059             :     case MCK_QPR_VFP2: return true;
    5060             :     case MCK_Reg24: return true;
    5061             :     case MCK_Reg25: return true;
    5062             :     case MCK_QPR: return true;
    5063             :     case MCK_DPair: return true;
    5064             :     }
    5065             : 
    5066           0 :   case MCK_Reg57:
    5067             :     switch (B) {
    5068             :     default: return false;
    5069             :     case MCK_Reg58: return true;
    5070             :     case MCK_Reg55: return true;
    5071             :     case MCK_Reg56: return true;
    5072             :     case MCK_Reg53: return true;
    5073             :     case MCK_Reg54: return true;
    5074             :     case MCK_Reg51: return true;
    5075             :     case MCK_Reg52: return true;
    5076             :     case MCK_DQuad: return true;
    5077             :     }
    5078             : 
    5079           0 :   case MCK_Reg63:
    5080             :     switch (B) {
    5081             :     default: return false;
    5082             :     case MCK_Reg64: return true;
    5083             :     case MCK_Reg65: return true;
    5084             :     case MCK_Reg66: return true;
    5085             :     case MCK_QQQQPR: return true;
    5086             :     }
    5087             : 
    5088         119 :   case MCK_tcGPR:
    5089             :     switch (B) {
    5090             :     default: return false;
    5091             :     case MCK_rGPR: return true;
    5092             :     case MCK_GPRnopc: return true;
    5093             :     case MCK_GPR: return true;
    5094             :     case MCK_GPRwithAPSR: return true;
    5095             :     }
    5096             : 
    5097       11321 :   case MCK_Reg10:
    5098             :     switch (B) {
    5099             :     default: return false;
    5100             :     case MCK_Reg8: return true;
    5101             :     case MCK_hGPR: return true;
    5102             :     case MCK_rGPR: return true;
    5103             :     case MCK_GPRnopc: return true;
    5104             :     case MCK_GPR: return true;
    5105             :     case MCK_GPRwithAPSR: return true;
    5106             :     }
    5107             : 
    5108           0 :   case MCK_Reg40:
    5109           0 :     switch (B) {
    5110             :     default: return false;
    5111           0 :     case MCK_Reg41: return true;
    5112           0 :     case MCK_Reg42: return true;
    5113           0 :     case MCK_Reg43: return true;
    5114           0 :     case MCK_DPairSpc: return true;
    5115             :     }
    5116             : 
    5117           0 :   case MCK_Reg58:
    5118             :     switch (B) {
    5119             :     default: return false;
    5120             :     case MCK_Reg55: return true;
    5121             :     case MCK_Reg56: return true;
    5122             :     case MCK_Reg53: return true;
    5123             :     case MCK_Reg54: return true;
    5124             :     case MCK_Reg51: return true;
    5125             :     case MCK_Reg52: return true;
    5126             :     case MCK_DQuad: return true;
    5127             :     }
    5128             : 
    5129           0 :   case MCK_Reg64:
    5130             :     switch (B) {
    5131             :     default: return false;
    5132             :     case MCK_Reg65: return true;
    5133             :     case MCK_Reg66: return true;
    5134             :     case MCK_QQQQPR: return true;
    5135             :     }
    5136             : 
    5137           0 :   case MCK_Reg70:
    5138           0 :     return B == MCK_GPRPair;
    5139             : 
    5140           0 :   case MCK_Reg76:
    5141           0 :     switch (B) {
    5142             :     default: return false;
    5143           0 :     case MCK_Reg77: return true;
    5144           0 :     case MCK_Reg78: return true;
    5145           0 :     case MCK_Reg79: return true;
    5146           0 :     case MCK_Reg80: return true;
    5147           0 :     case MCK_Reg81: return true;
    5148           0 :     case MCK_DTriple: return true;
    5149             :     }
    5150             : 
    5151           0 :   case MCK_Reg94:
    5152             :     switch (B) {
    5153             :     default: return false;
    5154             :     case MCK_Reg95: return true;
    5155             :     case MCK_Reg96: return true;
    5156             :     case MCK_Reg97: return true;
    5157             :     case MCK_Reg98: return true;
    5158             :     case MCK_DTripleSpc: return true;
    5159             :     }
    5160             : 
    5161           0 :   case MCK_Reg103:
    5162             :     switch (B) {
    5163             :     default: return false;
    5164             :     case MCK_Reg104: return true;
    5165             :     case MCK_Reg105: return true;
    5166             :     case MCK_Reg53: return true;
    5167             :     case MCK_Reg54: return true;
    5168             :     case MCK_Reg106: return true;
    5169             :     case MCK_Reg51: return true;
    5170             :     case MCK_Reg52: return true;
    5171             :     case MCK_DQuad: return true;
    5172             :     }
    5173             : 
    5174           0 :   case MCK_Reg8:
    5175             :     switch (B) {
    5176             :     default: return false;
    5177             :     case MCK_hGPR: return true;
    5178             :     case MCK_GPRnopc: return true;
    5179             :     case MCK_GPR: return true;
    5180             :     case MCK_GPRwithAPSR: return true;
    5181             :     }
    5182             : 
    5183           0 :   case MCK_Reg26:
    5184           0 :     switch (B) {
    5185             :     default: return false;
    5186           0 :     case MCK_Reg27: return true;
    5187           0 :     case MCK_Reg24: return true;
    5188           0 :     case MCK_Reg25: return true;
    5189           0 :     case MCK_DPair: return true;
    5190             :     }
    5191             : 
    5192           0 :   case MCK_Reg47:
    5193             :     switch (B) {
    5194             :     default: return false;
    5195             :     case MCK_Reg48: return true;
    5196             :     case MCK_Reg53: return true;
    5197             :     case MCK_Reg54: return true;
    5198             :     case MCK_Reg51: return true;
    5199             :     case MCK_QQPR: return true;
    5200             :     case MCK_Reg52: return true;
    5201             :     case MCK_DQuad: return true;
    5202             :     }
    5203             : 
    5204           0 :   case MCK_Reg55:
    5205             :     switch (B) {
    5206             :     default: return false;
    5207             :     case MCK_Reg56: return true;
    5208             :     case MCK_Reg53: return true;
    5209             :     case MCK_Reg54: return true;
    5210             :     case MCK_Reg51: return true;
    5211             :     case MCK_Reg52: return true;
    5212             :     case MCK_DQuad: return true;
    5213             :     }
    5214             : 
    5215           0 :   case MCK_Reg65:
    5216           0 :     switch (B) {
    5217             :     default: return false;
    5218           0 :     case MCK_Reg66: return true;
    5219           0 :     case MCK_QQQQPR: return true;
    5220             :     }
    5221             : 
    5222           0 :   case MCK_Reg77:
    5223             :     switch (B) {
    5224             :     default: return false;
    5225             :     case MCK_Reg78: return true;
    5226             :     case MCK_Reg79: return true;
    5227             :     case MCK_Reg80: return true;
    5228             :     case MCK_Reg81: return true;
    5229             :     case MCK_DTriple: return true;
    5230             :     }
    5231             : 
    5232           0 :   case MCK_Reg85:
    5233             :     switch (B) {
    5234             :     default: return false;
    5235             :     case MCK_Reg86: return true;
    5236             :     case MCK_Reg79: return true;
    5237             :     case MCK_Reg80: return true;
    5238             :     case MCK_Reg87: return true;
    5239             :     case MCK_Reg81: return true;
    5240             :     case MCK_DTriple: return true;
    5241             :     }
    5242             : 
    5243           0 :   case MCK_Reg90:
    5244             :     switch (B) {
    5245             :     default: return false;
    5246             :     case MCK_Reg91: return true;
    5247             :     case MCK_Reg79: return true;
    5248             :     case MCK_Reg80: return true;
    5249             :     case MCK_Reg92: return true;
    5250             :     case MCK_Reg81: return true;
    5251             :     case MCK_DTriple: return true;
    5252             :     }
    5253             : 
    5254           0 :   case MCK_Reg104:
    5255             :     switch (B) {
    5256             :     default: return false;
    5257             :     case MCK_Reg105: return true;
    5258             :     case MCK_Reg54: return true;
    5259             :     case MCK_Reg106: return true;
    5260             :     case MCK_Reg51: return true;
    5261             :     case MCK_Reg52: return true;
    5262             :     case MCK_DQuad: return true;
    5263             :     }
    5264             : 
    5265           0 :   case MCK_Reg27:
    5266             :     switch (B) {
    5267             :     default: return false;
    5268             :     case MCK_Reg24: return true;
    5269             :     case MCK_Reg25: return true;
    5270             :     case MCK_DPair: return true;
    5271             :     }
    5272             : 
    5273           0 :   case MCK_Reg41:
    5274           0 :     switch (B) {
    5275             :     default: return false;
    5276           0 :     case MCK_Reg42: return true;
    5277           0 :     case MCK_Reg43: return true;
    5278           0 :     case MCK_DPairSpc: return true;
    5279             :     }
    5280             : 
    5281           0 :   case MCK_Reg48:
    5282             :     switch (B) {
    5283             :     default: return false;
    5284             :     case MCK_Reg51: return true;
    5285             :     case MCK_QQPR: return true;
    5286             :     case MCK_Reg52: return true;
    5287             :     case MCK_DQuad: return true;
    5288             :     }
    5289             : 
    5290           0 :   case MCK_Reg56:
    5291             :     switch (B) {
    5292             :     default: return false;
    5293             :     case MCK_Reg53: return true;
    5294             :     case MCK_Reg54: return true;
    5295             :     case MCK_Reg51: return true;
    5296             :     case MCK_Reg52: return true;
    5297             :     case MCK_DQuad: return true;
    5298             :     }
    5299             : 
    5300           0 :   case MCK_Reg66:
    5301           0 :     return B == MCK_QQQQPR;
    5302             : 
    5303           0 :   case MCK_Reg78:
    5304             :     switch (B) {
    5305             :     default: return false;
    5306             :     case MCK_Reg79: return true;
    5307             :     case MCK_Reg80: return true;
    5308             :     case MCK_Reg81: return true;
    5309             :     case MCK_DTriple: return true;
    5310             :     }
    5311             : 
    5312           0 :   case MCK_Reg86:
    5313             :     switch (B) {
    5314             :     default: return false;
    5315             :     case MCK_Reg80: return true;
    5316             :     case MCK_Reg87: return true;
    5317             :     case MCK_Reg81: return true;
    5318             :     case MCK_DTriple: return true;
    5319             :     }
    5320             : 
    5321           0 :   case MCK_Reg91:
    5322             :     switch (B) {
    5323             :     default: return false;
    5324             :     case MCK_Reg92: return true;
    5325             :     case MCK_Reg81: return true;
    5326             :     case MCK_DTriple: return true;
    5327             :     }
    5328             : 
    5329           0 :   case MCK_Reg95:
    5330             :     switch (B) {
    5331             :     default: return false;
    5332             :     case MCK_Reg96: return true;
    5333             :     case MCK_Reg97: return true;
    5334             :     case MCK_Reg98: return true;
    5335             :     case MCK_DTripleSpc: return true;
    5336             :     }
    5337             : 
    5338           0 :   case MCK_Reg105:
    5339             :     switch (B) {
    5340             :     default: return false;
    5341             :     case MCK_Reg106: return true;
    5342             :     case MCK_Reg52: return true;
    5343             :     case MCK_DQuad: return true;
    5344             :     }
    5345             : 
    5346        5631 :   case MCK_DPR_8:
    5347        5631 :     switch (B) {
    5348             :     default: return false;
    5349          42 :     case MCK_DPR_VFP2: return true;
    5350        3732 :     case MCK_DPR: return true;
    5351             :     }
    5352             : 
    5353         992 :   case MCK_QPR_VFP2:
    5354             :     switch (B) {
    5355             :     default: return false;
    5356             :     case MCK_Reg24: return true;
    5357             :     case MCK_Reg25: return true;
    5358             :     case MCK_QPR: return true;
    5359             :     case MCK_DPair: return true;
    5360             :     }
    5361             : 
    5362           0 :   case MCK_hGPR:
    5363           0 :     return B == MCK_GPR;
    5364             : 
    5365       31411 :   case MCK_tGPR:
    5366             :     switch (B) {
    5367             :     default: return false;
    5368             :     case MCK_tGPRwithpc: return true;
    5369             :     case MCK_rGPR: return true;
    5370             :     case MCK_GPRnopc: return true;
    5371             :     case MCK_GPR: return true;
    5372             :     case MCK_GPRwithAPSR: return true;
    5373             :     }
    5374             : 
    5375           0 :   case MCK_tGPRwithpc:
    5376           0 :     return B == MCK_GPR;
    5377             : 
    5378           0 :   case MCK_Reg96:
    5379             :     switch (B) {
    5380             :     default: return false;
    5381             :     case MCK_Reg97: return true;
    5382             :     case MCK_Reg98: return true;
    5383             :     case MCK_DTripleSpc: return true;
    5384             :     }
    5385             : 
    5386           0 :   case MCK_Reg53:
    5387             :     switch (B) {
    5388             :     default: return false;
    5389             :     case MCK_Reg54: return true;
    5390             :     case MCK_Reg51: return true;
    5391             :     case MCK_Reg52: return true;
    5392             :     case MCK_DQuad: return true;
    5393             :     }
    5394             : 
    5395           0 :   case MCK_Reg42:
    5396           0 :     switch (B) {
    5397             :     default: return false;
    5398           0 :     case MCK_Reg43: return true;
    5399           0 :     case MCK_DPairSpc: return true;
    5400             :     }
    5401             : 
    5402           0 :   case MCK_Reg54:
    5403             :     switch (B) {
    5404             :     default: return false;
    5405             :     case MCK_Reg51: return true;
    5406             :     case MCK_Reg52: return true;
    5407             :     case MCK_DQuad: return true;
    5408             :     }
    5409             : 
    5410           0 :   case MCK_Reg79:
    5411             :     switch (B) {
    5412             :     default: return false;
    5413             :     case MCK_Reg80: return true;
    5414             :     case MCK_Reg81: return true;
    5415             :     case MCK_DTriple: return true;
    5416             :     }
    5417             : 
    5418           0 :   case MCK_Reg97:
    5419           0 :     switch (B) {
    5420             :     default: return false;
    5421           0 :     case MCK_Reg98: return true;
    5422           0 :     case MCK_DTripleSpc: return true;
    5423             :     }
    5424             : 
    5425           0 :   case MCK_Reg106:
    5426           0 :     return B == MCK_DQuad;
    5427             : 
    5428        6228 :   case MCK_rGPR:
    5429             :     switch (B) {
    5430             :     default: return false;
    5431             :     case MCK_GPRnopc: return true;
    5432             :     case MCK_GPR: return true;
    5433             :     case MCK_GPRwithAPSR: return true;
    5434             :     }
    5435             : 
    5436           0 :   case MCK_Reg24:
    5437           0 :     switch (B) {
    5438             :     default: return false;
    5439           0 :     case MCK_Reg25: return true;
    5440           0 :     case MCK_DPair: return true;
    5441             :     }
    5442             : 
    5443           0 :   case MCK_Reg51:
    5444           0 :     switch (B) {
    5445             :     default: return false;
    5446           0 :     case MCK_Reg52: return true;
    5447           0 :     case MCK_DQuad: return true;
    5448             :     }
    5449             : 
    5450           0 :   case MCK_Reg80:
    5451           0 :     switch (B) {
    5452             :     default: return false;
    5453           0 :     case MCK_Reg81: return true;
    5454           0 :     case MCK_DTriple: return true;
    5455             :     }
    5456             : 
    5457           0 :   case MCK_Reg87:
    5458           0 :     return B == MCK_DTriple;
    5459             : 
    5460           0 :   case MCK_Reg92:
    5461           0 :     return B == MCK_DTriple;
    5462             : 
    5463        2957 :   case MCK_GPRnopc:
    5464        2957 :     switch (B) {
    5465             :     default: return false;
    5466           0 :     case MCK_GPR: return true;
    5467           0 :     case MCK_GPRwithAPSR: return true;
    5468             :     }
    5469             : 
    5470           0 :   case MCK_QQPR:
    5471           0 :     return B == MCK_DQuad;
    5472             : 
    5473           0 :   case MCK_Reg25:
    5474           0 :     return B == MCK_DPair;
    5475             : 
    5476           0 :   case MCK_Reg43:
    5477           0 :     return B == MCK_DPairSpc;
    5478             : 
    5479           0 :   case MCK_Reg52:
    5480           0 :     return B == MCK_DQuad;
    5481             : 
    5482           0 :   case MCK_Reg81:
    5483           0 :     return B == MCK_DTriple;
    5484             : 
    5485           0 :   case MCK_Reg98:
    5486           0 :     return B == MCK_DTripleSpc;
    5487             : 
    5488         862 :   case MCK_DPR_VFP2:
    5489         862 :     return B == MCK_DPR;
    5490             : 
    5491        4542 :   case MCK_QPR:
    5492        4542 :     return B == MCK_DPair;
    5493             : 
    5494        3544 :   case MCK_SPR_8:
    5495        3544 :     return B == MCK_SPR;
    5496             :   }
    5497             : }
    5498             : 
    5499      854864 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
    5500      854864 :   ARMOperand &Operand = (ARMOperand&)GOp;
    5501      854864 :   if (Kind == InvalidMatchClass)
    5502             :     return MCTargetAsmParser::Match_InvalidOperand;
    5503             : 
    5504     1685344 :   if (Operand.isToken())
    5505      454508 :     return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
    5506             :              MCTargetAsmParser::Match_Success :
    5507             :              MCTargetAsmParser::Match_InvalidOperand;
    5508             : 
    5509      615418 :   switch (Kind) {
    5510             :   default: break;
    5511             :   // 'AM2OffsetImm' class
    5512          75 :   case MCK_AM2OffsetImm:
    5513             :     if (Operand.isAM2OffsetImm())
    5514             :       return MCTargetAsmParser::Match_Success;
    5515             :     break;
    5516             :   // 'AM3Offset' class
    5517          71 :   case MCK_AM3Offset:
    5518          71 :     if (Operand.isAM3Offset())
    5519             :       return MCTargetAsmParser::Match_Success;
    5520             :     break;
    5521             :   // 'ARMBranchTarget' class
    5522         577 :   case MCK_ARMBranchTarget:
    5523         158 :     if (Operand.isARMBranchTarget())
    5524             :       return MCTargetAsmParser::Match_Success;
    5525             :     break;
    5526             :   // 'AddrMode2' class
    5527           0 :   case MCK_AddrMode2:
    5528           0 :     if (Operand.isAddrMode2())
    5529             :       return MCTargetAsmParser::Match_Success;
    5530             :     break;
    5531             :   // 'AddrMode3' class
    5532         469 :   case MCK_AddrMode3:
    5533         469 :     if (Operand.isAddrMode3())
    5534             :       return MCTargetAsmParser::Match_Success;
    5535             :     break;
    5536             :   // 'AddrMode5' class
    5537        2125 :   case MCK_AddrMode5:
    5538        2125 :     if (Operand.isAddrMode5())
    5539             :       return MCTargetAsmParser::Match_Success;
    5540             :     break;
    5541             :   // 'AddrMode5FP16' class
    5542          32 :   case MCK_AddrMode5FP16:
    5543          32 :     if (Operand.isAddrMode5FP16())
    5544             :       return MCTargetAsmParser::Match_Success;
    5545             :     break;
    5546             :   // 'AlignedMemory16' class
    5547         215 :   case MCK_AlignedMemory16:
    5548         215 :     if (Operand.isAlignedMemory16())
    5549             :       return MCTargetAsmParser::Match_Success;
    5550         144 :     return ARMAsmParser::Match_AlignedMemoryRequires16;
    5551             :   // 'AlignedMemory32' class
    5552         372 :   case MCK_AlignedMemory32:
    5553         372 :     if (Operand.isAlignedMemory32())
    5554             :       return MCTargetAsmParser::Match_Success;
    5555         252 :     return ARMAsmParser::Match_AlignedMemoryRequires32;
    5556             :   // 'AlignedMemory64' class
    5557        1949 :   case MCK_AlignedMemory64:
    5558        1949 :     if (Operand.isAlignedMemory64())
    5559             :       return MCTargetAsmParser::Match_Success;
    5560        1296 :     return ARMAsmParser::Match_AlignedMemoryRequires64;
    5561             :   // 'AlignedMemory64or128' class
    5562        1180 :   case MCK_AlignedMemory64or128:
    5563        1180 :     if (Operand.isAlignedMemory64or128())
    5564             :       return MCTargetAsmParser::Match_Success;
    5565         639 :     return ARMAsmParser::Match_AlignedMemoryRequires64or128;
    5566             :   // 'AlignedMemory64or128or256' class
    5567        1220 :   case MCK_AlignedMemory64or128or256:
    5568        1220 :     if (Operand.isAlignedMemory64or128or256())
    5569             :       return MCTargetAsmParser::Match_Success;
    5570         450 :     return ARMAsmParser::Match_AlignedMemoryRequires64or128or256;
    5571             :   // 'AlignedMemoryNone' class
    5572         689 :   case MCK_AlignedMemoryNone:
    5573         149 :     if (Operand.isAlignedMemoryNone())
    5574             :       return MCTargetAsmParser::Match_Success;
    5575             :     return ARMAsmParser::Match_AlignedMemoryRequiresNone;
    5576             :   // 'AlignedMemory' class
    5577           0 :   case MCK_AlignedMemory:
    5578             :     if (Operand.isAlignedMemory())
    5579             :       return MCTargetAsmParser::Match_Success;
    5580             :     break;
    5581             :   // 'DupAlignedMemory16' class
    5582         192 :   case MCK_DupAlignedMemory16:
    5583         192 :     if (Operand.isDupAlignedMemory16())
    5584             :       return MCTargetAsmParser::Match_Success;
    5585         144 :     return ARMAsmParser::Match_DupAlignedMemoryRequires16;
    5586             :   // 'DupAlignedMemory32' class
    5587         300 :   case MCK_DupAlignedMemory32:
    5588         300 :     if (Operand.isDupAlignedMemory32())
    5589             :       return MCTargetAsmParser::Match_Success;
    5590         216 :     return ARMAsmParser::Match_DupAlignedMemoryRequires32;
    5591             :   // 'DupAlignedMemory64' class
    5592         216 :   case MCK_DupAlignedMemory64:
    5593         216 :     if (Operand.isDupAlignedMemory64())
    5594             :       return MCTargetAsmParser::Match_Success;
    5595         144 :     return ARMAsmParser::Match_DupAlignedMemoryRequires64;
    5596             :   // 'DupAlignedMemory64or128' class
    5597         102 :   case MCK_DupAlignedMemory64or128:
    5598         102 :     if (Operand.isDupAlignedMemory64or128())
    5599             :       return MCTargetAsmParser::Match_Success;
    5600          54 :     return ARMAsmParser::Match_DupAlignedMemoryRequires64or128;
    5601             :   // 'DupAlignedMemoryNone' class
    5602         456 :   case MCK_DupAlignedMemoryNone:
    5603          96 :     if (Operand.isDupAlignedMemoryNone())
    5604             :       return MCTargetAsmParser::Match_Success;
    5605             :     return ARMAsmParser::Match_DupAlignedMemoryRequiresNone;
    5606             :   // 'AdrLabel' class
    5607          26 :   case MCK_AdrLabel:
    5608          26 :     if (Operand.isAdrLabel())
    5609             :       return MCTargetAsmParser::Match_Success;
    5610             :     break;
    5611             :   // 'BankedReg' class
    5612         645 :   case MCK_BankedReg:
    5613         645 :     if (Operand.isBankedReg())
    5614             :       return MCTargetAsmParser::Match_Success;
    5615             :     break;
    5616             :   // 'Bitfield' class
    5617          45 :   case MCK_Bitfield:
    5618          45 :     if (Operand.isBitfield())
    5619             :       return MCTargetAsmParser::Match_Success;
    5620             :     break;
    5621             :   // 'CCOut' class
    5622       61067 :   case MCK_CCOut:
    5623       61067 :     if (Operand.isCCOut())
    5624             :       return MCTargetAsmParser::Match_Success;
    5625             :     break;
    5626             :   // 'CondCode' class
    5627      301725 :   case MCK_CondCode:
    5628      301725 :     if (Operand.isCondCode())
    5629             :       return MCTargetAsmParser::Match_Success;
    5630             :     break;
    5631             :   // 'CoprocNum' class
    5632        3635 :   case MCK_CoprocNum:
    5633        3635 :     if (Operand.isCoprocNum())
    5634             :       return MCTargetAsmParser::Match_Success;
    5635             :     break;
    5636             :   // 'CoprocOption' class
    5637         526 :   case MCK_CoprocOption:
    5638         526 :     if (Operand.isCoprocOption())
    5639             :       return MCTargetAsmParser::Match_Success;
    5640             :     break;
    5641             :   // 'CoprocReg' class
    5642        3537 :   case MCK_CoprocReg:
    5643        3537 :     if (Operand.isCoprocReg())
    5644             :       return MCTargetAsmParser::Match_Success;
    5645             :     break;
    5646             :   // 'DPRRegList' class
    5647          90 :   case MCK_DPRRegList:
    5648          90 :     if (Operand.isDPRRegList())
    5649             :       return MCTargetAsmParser::Match_Success;
    5650             :     break;
    5651             :   // 'FPImm' class
    5652          47 :   case MCK_FPImm:
    5653          47 :     if (Operand.isFPImm())
    5654             :       return MCTargetAsmParser::Match_Success;
    5655             :     break;
    5656             :   // 'Imm0_15' class
    5657         274 :   case MCK_Imm0_15:
    5658         264 :     if (Operand.isImmediate<0,15>())
    5659             :       return MCTargetAsmParser::Match_Success;
    5660          43 :     return ARMAsmParser::Match_ImmRange0_15;
    5661             :   // 'Imm0_1' class
    5662          30 :   case MCK_Imm0_1:
    5663          30 :     if (Operand.isImmediate<0,1>())
    5664             :       return MCTargetAsmParser::Match_Success;
    5665          16 :     return ARMAsmParser::Match_ImmRange0_1;
    5666             :   // 'Imm0_239' class
    5667          40 :   case MCK_Imm0_239:
    5668          40 :     if (Operand.isImmediate<0,239>())
    5669             :       return MCTargetAsmParser::Match_Success;
    5670           8 :     return ARMAsmParser::Match_ImmRange0_239;
    5671             :   // 'Imm0_255' class
    5672        1515 :   case MCK_Imm0_255:
    5673         264 :     if (Operand.isImmediate<0,255>())
    5674             :       return MCTargetAsmParser::Match_Success;
    5675        1316 :     return ARMAsmParser::Match_ImmRange0_255;
    5676             :   // 'Imm0_31' class
    5677        1027 :   case MCK_Imm0_31:
    5678         565 :     if (Operand.isImmediate<0,31>())
    5679             :       return MCTargetAsmParser::Match_Success;
    5680         478 :     return ARMAsmParser::Match_ImmRange0_31;
    5681             :   // 'Imm0_32' class
    5682         147 :   case MCK_Imm0_32:
    5683          24 :     if (Operand.isImmediate<0,32>())
    5684             :       return MCTargetAsmParser::Match_Success;
    5685         127 :     return ARMAsmParser::Match_ImmRange0_32;
    5686             :   // 'Imm0_3' class
    5687           7 :   case MCK_Imm0_3:
    5688           4 :     if (Operand.isImmediate<0,3>())
    5689             :       return MCTargetAsmParser::Match_Success;
    5690           3 :     return ARMAsmParser::Match_ImmRange0_3;
    5691             :   // 'Imm0_63' class
    5692          26 :   case MCK_Imm0_63:
    5693          26 :     if (Operand.isImmediate<0,63>())
    5694             :       return MCTargetAsmParser::Match_Success;
    5695          14 :     return ARMAsmParser::Match_ImmRange0_63;
    5696             :   // 'Imm0_65535' class
    5697          73 :   case MCK_Imm0_65535:
    5698          73 :     if (Operand.isImmediate<0,65535>())
    5699             :       return MCTargetAsmParser::Match_Success;
    5700          20 :     return ARMAsmParser::Match_ImmRange0_65535;
    5701             :   // 'Imm0_65535Expr' class
    5702         439 :   case MCK_Imm0_65535Expr:
    5703         122 :     if (Operand.isImm0_65535Expr())
    5704             :       return MCTargetAsmParser::Match_Success;
    5705             :     break;
    5706             :   // 'Imm0_7' class
    5707        1196 :   case MCK_Imm0_7:
    5708         779 :     if (Operand.isImmediate<0,7>())
    5709             :       return MCTargetAsmParser::Match_Success;
    5710         513 :     return ARMAsmParser::Match_ImmRange0_7;
    5711             :   // 'Imm16' class
    5712           2 :   case MCK_Imm16:
    5713           2 :     if (Operand.isImmediate<16,16>())
    5714             :       return MCTargetAsmParser::Match_Success;
    5715           0 :     return ARMAsmParser::Match_ImmRange16_16;
    5716             :   // 'Imm1_15' class
    5717           4 :   case MCK_Imm1_15:
    5718           4 :     if (Operand.isImmediate<1,15>())
    5719             :       return MCTargetAsmParser::Match_Success;
    5720           0 :     return ARMAsmParser::Match_ImmRange1_15;
    5721             :   // 'Imm1_16' class
    5722          26 :   case MCK_Imm1_16:
    5723          26 :     if (Operand.isImmediate<1,16>())
    5724             :       return MCTargetAsmParser::Match_Success;
    5725           8 :     return ARMAsmParser::Match_ImmRange1_16;
    5726             :   // 'Imm1_31' class
    5727         161 :   case MCK_Imm1_31:
    5728          61 :     if (Operand.isImmediate<1,31>())
    5729             :       return MCTargetAsmParser::Match_Success;
    5730         130 :     return ARMAsmParser::Match_ImmRange1_31;
    5731             :   // 'Imm1_32' class
    5732         188 :   case MCK_Imm1_32:
    5733         188 :     if (Operand.isImmediate<1,32>())
    5734             :       return MCTargetAsmParser::Match_Success;
    5735          16 :     return ARMAsmParser::Match_ImmRange1_32;
    5736             :   // 'Imm1_7' class
    5737           4 :   case MCK_Imm1_7:
    5738           4 :     if (Operand.isImmediate<1,7>())
    5739             :       return MCTargetAsmParser::Match_Success;
    5740           0 :     return ARMAsmParser::Match_ImmRange1_7;
    5741             :   // 'Imm24bit' class
    5742          22 :   case MCK_Imm24bit:
    5743          22 :     if (Operand.isImmediate<0,16777215>())
    5744             :       return MCTargetAsmParser::Match_Success;
    5745           6 :     return ARMAsmParser::Match_ImmRange0_16777215;
    5746             :   // 'Imm256_65535Expr' class
    5747         115 :   case MCK_Imm256_65535Expr:
    5748          41 :     if (Operand.isImmediate<256,65535>())
    5749             :       return MCTargetAsmParser::Match_Success;
    5750         105 :     return ARMAsmParser::Match_ImmRange256_65535;
    5751             :   // 'Imm32' class
    5752           2 :   case MCK_Imm32:
    5753           2 :     if (Operand.isImmediate<32,32>())
    5754             :       return MCTargetAsmParser::Match_Success;
    5755           0 :     return ARMAsmParser::Match_ImmRange32_32;
    5756             :   // 'Imm8' class
    5757           2 :   case MCK_Imm8:
    5758           2 :     if (Operand.isImmediate<8,8>())
    5759             :       return MCTargetAsmParser::Match_Success;
    5760           0 :     return ARMAsmParser::Match_ImmRange8_8;
    5761             :   // 'Imm8_255' class
    5762           0 :   case MCK_Imm8_255:
    5763           0 :     if (Operand.isImmediate<8,255>())
    5764             :       return MCTargetAsmParser::Match_Success;
    5765           0 :     return ARMAsmParser::Match_ImmRange8_255;
    5766             :   // 'Imm' class
    5767        1881 :   case MCK_Imm:
    5768        1881 :     if (Operand.isImm())
    5769             :       return MCTargetAsmParser::Match_Success;
    5770             :     break;
    5771             :   // 'InstSyncBarrierOpt' class
    5772          36 :   case MCK_InstSyncBarrierOpt:
    5773          36 :     if (Operand.isInstSyncBarrierOpt())
    5774             :       return MCTargetAsmParser::Match_Success;
    5775             :     break;
    5776             :   // 'MSRMask' class
    5777         608 :   case MCK_MSRMask:
    5778         608 :     if (Operand.isMSRMask())
    5779             :       return MCTargetAsmParser::Match_Success;
    5780             :     break;
    5781             :   // 'MemBarrierOpt' class
    5782         416 :   case MCK_MemBarrierOpt:
    5783         416 :     if (Operand.isMemBarrierOpt())
    5784             :       return MCTargetAsmParser::Match_Success;
    5785             :     break;
    5786             :   // 'MemImm0_1020s4Offset' class
    5787          44 :   case MCK_MemImm0_1020s4Offset:
    5788             :     if (Operand.isMemImm0_1020s4Offset())
    5789             :       return MCTargetAsmParser::Match_Success;
    5790             :     break;
    5791             :   // 'MemImm12Offset' class
    5792         670 :   case MCK_MemImm12Offset:
    5793         670 :     if (Operand.isMemImm12Offset())
    5794             :       return MCTargetAsmParser::Match_Success;
    5795             :     break;
    5796             :   // 'MemImm8Offset' class
    5797         297 :   case MCK_MemImm8Offset:
    5798         297 :     if (Operand.isMemImm8Offset())
    5799             :       return MCTargetAsmParser::Match_Success;
    5800             :     break;
    5801             :   // 'MemImm8s4Offset' class
    5802         339 :   case MCK_MemImm8s4Offset:
    5803         339 :     if (Operand.isMemImm8s4Offset())
    5804             :       return MCTargetAsmParser::Match_Success;
    5805             :     break;
    5806             :   // 'MemNegImm8Offset' class
    5807         682 :   case MCK_MemNegImm8Offset:
    5808         682 :     if (Operand.isMemNegImm8Offset())
    5809             :       return MCTargetAsmParser::Match_Success;
    5810             :     break;
    5811             :   // 'MemNoOffset' class
    5812        1772 :   case MCK_MemNoOffset:
    5813             :     if (Operand.isMemNoOffset())
    5814             :       return MCTargetAsmParser::Match_Success;
    5815             :     break;
    5816             :   // 'MemPosImm8Offset' class
    5817          74 :   case MCK_MemPosImm8Offset:
    5818          30 :     if (Operand.isMemPosImm8Offset())
    5819             :       return MCTargetAsmParser::Match_Success;
    5820             :     break;
    5821             :   // 'MemRegOffset' class
    5822         540 :   case MCK_MemRegOffset:
    5823             :     if (Operand.isMemRegOffset())
    5824             :       return MCTargetAsmParser::Match_Success;
    5825             :     break;
    5826             :   // 'ModImm' class
    5827        3969 :   case MCK_ModImm:
    5828        3969 :     if (Operand.isModImm())
    5829             :       return MCTargetAsmParser::Match_Success;
    5830             :     break;
    5831             :   // 'ModImmNeg' class
    5832        1357 :   case MCK_ModImmNeg:
    5833        1357 :     if (Operand.isModImmNeg())
    5834             :       return MCTargetAsmParser::Match_Success;
    5835             :     break;
    5836             :   // 'ModImmNot' class
    5837        1125 :   case MCK_ModImmNot:
    5838        1125 :     if (Operand.isModImmNot())
    5839             :       return MCTargetAsmParser::Match_Success;
    5840             :     break;
    5841             :   // 'PKHASRImm' class
    5842          12 :   case MCK_PKHASRImm:
    5843          12 :     if (Operand.isPKHASRImm())
    5844             :       return MCTargetAsmParser::Match_Success;
    5845             :     break;
    5846             :   // 'PKHLSLImm' class
    5847          22 :   case MCK_PKHLSLImm:
    5848          22 :     if (Operand.isImmediate<0,31>())
    5849             :       return MCTargetAsmParser::Match_Success;
    5850           0 :     return ARMAsmParser::Match_ImmRange0_31;
    5851             :   // 'PostIdxImm8' class
    5852          19 :   case MCK_PostIdxImm8:
    5853             :     if (Operand.isPostIdxImm8())
    5854             :       return MCTargetAsmParser::Match_Success;
    5855             :     break;
    5856             :   // 'PostIdxImm8s4' class
    5857         352 :   case MCK_PostIdxImm8s4:
    5858             :     if (Operand.isPostIdxImm8s4())
    5859             :       return MCTargetAsmParser::Match_Success;
    5860             :     break;
    5861             :   // 'PostIdxReg' class
    5862          25 :   case MCK_PostIdxReg:
    5863          25 :     if (Operand.isPostIdxReg())
    5864             :       return MCTargetAsmParser::Match_Success;
    5865             :     break;
    5866             :   // 'PostIdxRegShifted' class
    5867          36 :   case MCK_PostIdxRegShifted:
    5868          36 :     if (Operand.isPostIdxRegShifted())
    5869             :       return MCTargetAsmParser::Match_Success;
    5870             :     break;
    5871             :   // 'ProcIFlags' class
    5872         105 :   case MCK_ProcIFlags:
    5873         105 :     if (Operand.isProcIFlags())
    5874             :       return MCTargetAsmParser::Match_Success;
    5875             :     break;
    5876             :   // 'RegList' class
    5877         967 :   case MCK_RegList:
    5878         967 :     if (Operand.isRegList())
    5879             :       return MCTargetAsmParser::Match_Success;
    5880             :     break;
    5881             :   // 'RotImm' class
    5882         334 :   case MCK_RotImm:
    5883         334 :     if (Operand.isRotImm())
    5884             :       return MCTargetAsmParser::Match_Success;
    5885             :     break;
    5886             :   // 'SPRRegList' class
    5887          18 :   case MCK_SPRRegList:
    5888          18 :     if (Operand.isSPRRegList())
    5889             :       return MCTargetAsmParser::Match_Success;
    5890             :     break;
    5891             :   // 'SetEndImm' class
    5892          41 :   case MCK_SetEndImm:
    5893          33 :     if (Operand.isImmediate<0,1>())
    5894             :       return MCTargetAsmParser::Match_Success;
    5895           8 :     return ARMAsmParser::Match_ImmRange0_1;
    5896             :   // 'RegShiftedImm' class
    5897        7756 :   case MCK_RegShiftedImm:
    5898        7756 :     if (Operand.isRegShiftedImm())
    5899             :       return MCTargetAsmParser::Match_Success;
    5900             :     break;
    5901             :   // 'RegShiftedReg' class
    5902        3170 :   case MCK_RegShiftedReg:
    5903        3170 :     if (Operand.isRegShiftedReg())
    5904             :       return MCTargetAsmParser::Match_Success;
    5905             :     break;
    5906             :   // 'ShifterImm' class
    5907          44 :   case MCK_ShifterImm:
    5908          44 :     if (Operand.isShifterImm())
    5909             :       return MCTargetAsmParser::Match_Success;
    5910             :     break;
    5911             :   // 'ThumbBranchTarget' class
    5912         194 :   case MCK_ThumbBranchTarget:
    5913          40 :     if (Operand.isThumbBranchTarget())
    5914             :       return MCTargetAsmParser::Match_Success;
    5915             :     break;
    5916             :   // 'ThumbMemPC' class
    5917         523 :   case MCK_ThumbMemPC:
    5918         523 :     if (Operand.isThumbMemPC())
    5919             :       return MCTargetAsmParser::Match_Success;
    5920             :     break;
    5921             :   // 'ThumbModImmNeg1_7' class
    5922         453 :   case MCK_ThumbModImmNeg1_7:
    5923          42 :     if (Operand.isThumbModImmNeg1_7())
    5924             :       return MCTargetAsmParser::Match_Success;
    5925             :     break;
    5926             :   // 'ThumbModImmNeg8_255' class
    5927        1162 :   case MCK_ThumbModImmNeg8_255:
    5928          49 :     if (Operand.isThumbModImmNeg8_255())
    5929             :       return MCTargetAsmParser::Match_Success;
    5930             :     break;
    5931             :   // 'ImmThumbSR' class
    5932         429 :   case MCK_ImmThumbSR:
    5933         149 :     if (Operand.isImmediate<1,32>())
    5934             :       return MCTargetAsmParser::Match_Success;
    5935         304 :     return ARMAsmParser::Match_ImmRange1_32;
    5936             :   // 'UnsignedOffset_b8s2' class
    5937          54 :   case MCK_UnsignedOffset_b8s2:
    5938             :     if (Operand.isUnsignedOffset<8, 2>())
    5939             :       return MCTargetAsmParser::Match_Success;
    5940             :     break;
    5941             :   // 'VecListDPairAllLanes' class
    5942        2268 :   case MCK_VecListDPairAllLanes:
    5943         462 :     if (Operand.isVecListDPairAllLanes())
    5944             :       return MCTargetAsmParser::Match_Success;
    5945             :     break;
    5946             :   // 'VecListDPair' class
    5947        3886 :   case MCK_VecListDPair:
    5948        2247 :     if (Operand.isVecListDPair())
    5949             :       return MCTargetAsmParser::Match_Success;
    5950             :     break;
    5951             :   // 'VecListDPairSpacedAllLanes' class
    5952         953 :   case MCK_VecListDPairSpacedAllLanes:
    5953         150 :     if (Operand.isVecListDPairSpacedAllLanes())
    5954             :       return MCTargetAsmParser::Match_Success;
    5955             :     break;
    5956             :   // 'VecListDPairSpaced' class
    5957        1365 :   case MCK_VecListDPairSpaced:
    5958         227 :     if (Operand.isVecListDPairSpaced())
    5959             :       return MCTargetAsmParser::Match_Success;
    5960             :     break;
    5961             :   // 'VecListFourDAllLanes' class
    5962         953 :   case MCK_VecListFourDAllLanes:
    5963         159 :     if (Operand.isVecListFourDAllLanes())
    5964             :       return MCTargetAsmParser::Match_Success;
    5965             :     break;
    5966             :   // 'VecListFourD' class
    5967        5075 :   case MCK_VecListFourD:
    5968        2250 :     if (Operand.isVecListFourD())
    5969             :       return MCTargetAsmParser::Match_Success;
    5970             :     break;
    5971             :   // 'VecListFourDByteIndexed' class
    5972         383 :   case MCK_VecListFourDByteIndexed:
    5973             :     if (Operand.isVecListFourDByteIndexed())
    5974             :       return MCTargetAsmParser::Match_Success;
    5975             :     break;
    5976             :   // 'VecListFourDHWordIndexed' class
    5977         499 :   case MCK_VecListFourDHWordIndexed:
    5978             :     if (Operand.isVecListFourDHWordIndexed())
    5979             :       return MCTargetAsmParser::Match_Success;
    5980             :     break;
    5981             :   // 'VecListFourDWordIndexed' class
    5982         561 :   case MCK_VecListFourDWordIndexed:
    5983             :     if (Operand.isVecListFourDWordIndexed())
    5984             :       return MCTargetAsmParser::Match_Success;
    5985             :     break;
    5986             :   // 'VecListFourQAllLanes' class
    5987         772 :   case MCK_VecListFourQAllLanes:
    5988         159 :     if (Operand.isVecListFourQAllLanes())
    5989             :       return MCTargetAsmParser::Match_Success;
    5990             :     break;
    5991             :   // 'VecListFourQ' class
    5992        1256 :   case MCK_VecListFourQ:
    5993         312 :     if (Operand.isVecListFourQ())
    5994             :       return MCTargetAsmParser::Match_Success;
    5995             :     break;
    5996             :   // 'VecListFourQHWordIndexed' class
    5997         394 :   case MCK_VecListFourQHWordIndexed:
    5998             :     if (Operand.isVecListFourQHWordIndexed())
    5999             :       return MCTargetAsmParser::Match_Success;
    6000             :     break;
    6001             :   // 'VecListFourQWordIndexed' class
    6002         429 :   case MCK_VecListFourQWordIndexed:
    6003             :     if (Operand.isVecListFourQWordIndexed())
    6004             :       return MCTargetAsmParser::Match_Success;
    6005             :     break;
    6006             :   // 'VecListOneDAllLanes' class
    6007        1041 :   case MCK_VecListOneDAllLanes:
    6008         282 :     if (Operand.isVecListOneDAllLanes())
    6009             :       return MCTargetAsmParser::Match_Success;
    6010             :     break;
    6011             :   // 'VecListOneD' class
    6012        2001 :   case MCK_VecListOneD:
    6013        1364 :     if (Operand.isVecListOneD())
    6014             :       return MCTargetAsmParser::Match_Success;
    6015             :     break;
    6016             :   // 'VecListOneDByteIndexed' class
    6017         526 :   case MCK_VecListOneDByteIndexed:
    6018             :     if (Operand.isVecListOneDByteIndexed())
    6019             :       return MCTargetAsmParser::Match_Success;
    6020             :     break;
    6021             :   // 'VecListOneDHWordIndexed' class
    6022         495 :   case MCK_VecListOneDHWordIndexed:
    6023             :     if (Operand.isVecListOneDHWordIndexed())
    6024             :       return MCTargetAsmParser::Match_Success;
    6025             :     break;
    6026             :   // 'VecListOneDWordIndexed' class
    6027         544 :   case MCK_VecListOneDWordIndexed:
    6028             :     if (Operand.isVecListOneDWordIndexed())
    6029             :       return MCTargetAsmParser::Match_Success;
    6030             :     break;
    6031             :   // 'VecListThreeDAllLanes' class
    6032        1011 :   case MCK_VecListThreeDAllLanes:
    6033         171 :     if (Operand.isVecListThreeDAllLanes())
    6034             :       return MCTargetAsmParser::Match_Success;
    6035             :     break;
    6036             :   // 'VecListThreeD' class
    6037        3431 :   case MCK_VecListThreeD:
    6038        1571 :     if (Operand.isVecListThreeD())
    6039             :       return MCTargetAsmParser::Match_Success;
    6040             :     break;
    6041             :   // 'VecListThreeDByteIndexed' class
    6042         434 :   case MCK_VecListThreeDByteIndexed:
    6043             :     if (Operand.isVecListThreeDByteIndexed())
    6044             :       return MCTargetAsmParser::Match_Success;
    6045             :     break;
    6046             :   // 'VecListThreeDHWordIndexed' class
    6047         554 :   case MCK_VecListThreeDHWordIndexed:
    6048             :     if (Operand.isVecListThreeDHWordIndexed())
    6049             :       return MCTargetAsmParser::Match_Success;
    6050             :     break;
    6051             :   // 'VecListThreeDWordIndexed' class
    6052         554 :   case MCK_VecListThreeDWordIndexed:
    6053             :     if (Operand.isVecListThreeDWordIndexed())
    6054             :       return MCTargetAsmParser::Match_Success;
    6055             :     break;
    6056             :   // 'VecListThreeQAllLanes' class
    6057         900 :   case MCK_VecListThreeQAllLanes:
    6058         171 :     if (Operand.isVecListThreeQAllLanes())
    6059             :       return MCTargetAsmParser::Match_Success;
    6060             :     break;
    6061             :   // 'VecListThreeQ' class
    6062        1428 :   case MCK_VecListThreeQ:
    6063         348 :     if (Operand.isVecListThreeQ())
    6064             :       return MCTargetAsmParser::Match_Success;
    6065             :     break;
    6066             :   // 'VecListThreeQHWordIndexed' class
    6067         484 :   case MCK_VecListThreeQHWordIndexed:
    6068             :     if (Operand.isVecListThreeQHWordIndexed())
    6069             :       return MCTargetAsmParser::Match_Success;
    6070             :     break;
    6071             :   // 'VecListThreeQWordIndexed' class
    6072         484 :   case MCK_VecListThreeQWordIndexed:
    6073             :     if (Operand.isVecListThreeQWordIndexed())
    6074             :       return MCTargetAsmParser::Match_Success;
    6075             :     break;
    6076             :   // 'VecListTwoDByteIndexed' class
    6077         382 :   case MCK_VecListTwoDByteIndexed:
    6078             :     if (Operand.isVecListTwoDByteIndexed())
    6079             :       return MCTargetAsmParser::Match_Success;
    6080             :     break;
    6081             :   // 'VecListTwoDHWordIndexed' class
    6082         291 :   case MCK_VecListTwoDHWordIndexed:
    6083             :     if (Operand.isVecListTwoDHWordIndexed())
    6084             :       return MCTargetAsmParser::Match_Success;
    6085             :     break;
    6086             :   // 'VecListTwoDWordIndexed' class
    6087         488 :   case MCK_VecListTwoDWordIndexed:
    6088             :     if (Operand.isVecListTwoDWordIndexed())
    6089             :       return MCTargetAsmParser::Match_Success;
    6090             :     break;
    6091             :   // 'VecListTwoQHWordIndexed' class
    6092         276 :   case MCK_VecListTwoQHWordIndexed:
    6093             :     if (Operand.isVecListTwoQHWordIndexed())
    6094             :       return MCTargetAsmParser::Match_Success;
    6095             :     break;
    6096             :   // 'VecListTwoQWordIndexed' class
    6097         462 :   case MCK_VecListTwoQWordIndexed:
    6098             :     if (Operand.isVecListTwoQWordIndexed())
    6099             :       return MCTargetAsmParser::Match_Success;
    6100             :     break;
    6101             :   // 'VectorIndex16' class
    6102         117 :   case MCK_VectorIndex16:
    6103         219 :     if (Operand.isVectorIndex16())
    6104             :       return MCTargetAsmParser::Match_Success;
    6105             :     break;
    6106             :   // 'VectorIndex32' class
    6107         132 :   case MCK_VectorIndex32:
    6108         259 :     if (Operand.isVectorIndex32())
    6109             :       return MCTargetAsmParser::Match_Success;
    6110             :     break;
    6111             :   // 'VectorIndex8' class
    6112          22 :   case MCK_VectorIndex8:
    6113          44 :     if (Operand.isVectorIndex8())
    6114             :       return MCTargetAsmParser::Match_Success;
    6115             :     break;
    6116             :   // 'MemTBB' class
    6117           7 :   case MCK_MemTBB:
    6118             :     if (Operand.isMemTBB())
    6119             :       return MCTargetAsmParser::Match_Success;
    6120             :     break;
    6121             :   // 'MemTBH' class
    6122           7 :   case MCK_MemTBH:
    6123             :     if (Operand.isMemTBH())
    6124             :       return MCTargetAsmParser::Match_Success;
    6125             :     break;
    6126             :   // 'ConstPoolAsmImm' class
    6127         892 :   case MCK_ConstPoolAsmImm:
    6128         892 :     if (Operand.isConstPoolAsmImm())
    6129             :       return MCTargetAsmParser::Match_Success;
    6130             :     break;
    6131             :   // 'FBits16' class
    6132          28 :   case MCK_FBits16:
    6133          28 :     if (Operand.isFBits16())
    6134             :       return MCTargetAsmParser::Match_Success;
    6135             :     break;
    6136             :   // 'FBits32' class
    6137          28 :   case MCK_FBits32:
    6138          28 :     if (Operand.isFBits32())
    6139             :       return MCTargetAsmParser::Match_Success;
    6140             :     break;
    6141             :   // 'Imm0_4095' class
    6142         266 :   case MCK_Imm0_4095:
    6143         116 :     if (Operand.isImmediate<0,4095>())
    6144             :       return MCTargetAsmParser::Match_Success;
    6145         160 :     return ARMAsmParser::Match_ImmRange0_4095;
    6146             :   // 'Imm0_4095Neg' class
    6147         198 :   case MCK_Imm0_4095Neg:
    6148          16 :     if (Operand.isImm0_4095Neg())
    6149             :       return MCTargetAsmParser::Match_Success;
    6150             :     break;
    6151             :   // 'ITMask' class
    6152        5488 :   case MCK_ITMask:
    6153        5488 :     if (Operand.isITMask())
    6154             :       return MCTargetAsmParser::Match_Success;
    6155             :     break;
    6156             :   // 'ITCondCode' class
    6157        5488 :   case MCK_ITCondCode:
    6158        5488 :     if (Operand.isITCondCode())
    6159             :       return MCTargetAsmParser::Match_Success;
    6160             :     break;
    6161             :   // 'NEONi16splat' class
    6162          37 :   case MCK_NEONi16splat:
    6163          37 :     if (Operand.isNEONi16splat())
    6164             :       return MCTargetAsmParser::Match_Success;
    6165             :     break;
    6166             :   // 'NEONi32splat' class
    6167          26 :   case MCK_NEONi32splat:
    6168          26 :     if (Operand.isNEONi32splat())
    6169             :       return MCTargetAsmParser::Match_Success;
    6170             :     break;
    6171             :   // 'NEONi64splat' class
    6172           5 :   case MCK_NEONi64splat:
    6173           5 :     if (Operand.isNEONi64splat())
    6174             :       return MCTargetAsmParser::Match_Success;
    6175             :     break;
    6176             :   // 'NEONi8splat' class
    6177           4 :   case MCK_NEONi8splat:
    6178           4 :     if (Operand.isNEONi8splat())
    6179             :       return MCTargetAsmParser::Match_Success;
    6180             :     break;
    6181             :   // 'NEONi16splatNot' class
    6182           8 :   case MCK_NEONi16splatNot:
    6183           8 :     if (Operand.isNEONi16splatNot())
    6184             :       return MCTargetAsmParser::Match_Success;
    6185             :     break;
    6186             :   // 'NEONi32splatNot' class
    6187          12 :   case MCK_NEONi32splatNot:
    6188          12 :     if (Operand.isNEONi32splatNot())
    6189             :       return MCTargetAsmParser::Match_Success;
    6190             :     break;
    6191             :   // 'NEONi16vmovByteReplicate' class
    6192           4 :   case MCK_NEONi16vmovByteReplicate:
    6193           4 :     if (Operand.isNEONi16ByteReplicate())
    6194             :       return MCTargetAsmParser::Match_Success;
    6195             :     break;
    6196             :   // 'NEONi32vmov' class
    6197          53 :   case MCK_NEONi32vmov:
    6198          53 :     if (Operand.isNEONi32vmov())
    6199             :       return MCTargetAsmParser::Match_Success;
    6200             :     break;
    6201             :   // 'NEONi32vmovByteReplicate' class
    6202           6 :   case MCK_NEONi32vmovByteReplicate:
    6203           6 :     if (Operand.isNEONi32ByteReplicate())
    6204             :       return MCTargetAsmParser::Match_Success;
    6205             :     break;
    6206             :   // 'NEONi32vmovNeg' class
    6207          11 :   case MCK_NEONi32vmovNeg:
    6208          11 :     if (Operand.isNEONi32vmovNeg())
    6209             :       return MCTargetAsmParser::Match_Success;
    6210             :     break;
    6211             :   // 'NEONi16invByteReplicate' class
    6212           7 :   case MCK_NEONi16invByteReplicate:
    6213           4 :     if (Operand.isNEONi16ByteReplicate())
    6214             :       return MCTargetAsmParser::Match_Success;
    6215             :     break;
    6216             :   // 'NEONi32invByteReplicate' class
    6217           9 :   case MCK_NEONi32invByteReplicate:
    6218           6 :     if (Operand.isNEONi32ByteReplicate())
    6219             :       return MCTargetAsmParser::Match_Success;
    6220             :     break;
    6221             :   // 'ShrImm16' class
    6222         140 :   case MCK_ShrImm16:
    6223          98 :     if (Operand.isImmediate<1,16>())
    6224             :       return MCTargetAsmParser::Match_Success;
    6225          42 :     return ARMAsmParser::Match_ImmRange1_16;
    6226             :   // 'ShrImm32' class
    6227         140 :   case MCK_ShrImm32:
    6228          98 :     if (Operand.isImmediate<1,32>())
    6229             :       return MCTargetAsmParser::Match_Success;
    6230          42 :     return ARMAsmParser::Match_ImmRange1_32;
    6231             :   // 'ShrImm64' class
    6232         122 :   case MCK_ShrImm64:
    6233          80 :     if (Operand.isImmediate<1,64>())
    6234             :       return MCTargetAsmParser::Match_Success;
    6235          42 :     return ARMAsmParser::Match_ImmRange1_64;
    6236             :   // 'ShrImm8' class
    6237         140 :   case MCK_ShrImm8:
    6238          98 :     if (Operand.isImmediate<1,8>())
    6239             :       return MCTargetAsmParser::Match_Success;
    6240          42 :     return ARMAsmParser::Match_ImmRange1_8;
    6241             :   // 'T2SOImm' class
    6242        4658 :   case MCK_T2SOImm:
    6243        4658 :     if (Operand.isT2SOImm())
    6244             :       return MCTargetAsmParser::Match_Success;
    6245             :     break;
    6246             :   // 'T2SOImmNeg' class
    6247        3076 :   case MCK_T2SOImmNeg:
    6248        3076 :     if (Operand.isT2SOImmNeg())
    6249             :       return MCTargetAsmParser::Match_Success;
    6250             :     break;
    6251             :   // 'T2SOImmNot' class
    6252        1253 :   case MCK_T2SOImmNot:
    6253        1253 :     if (Operand.isT2SOImmNot())
    6254             :       return MCTargetAsmParser::Match_Success;
    6255             :     break;
    6256             :   // 'MemUImm12Offset' class
    6257         861 :   case MCK_MemUImm12Offset:
    6258         289 :     if (Operand.isMemUImm12Offset())
    6259             :       return MCTargetAsmParser::Match_Success;
    6260             :     break;
    6261             :   // 'T2MemRegOffset' class
    6262         611 :   case MCK_T2MemRegOffset:
    6263         611 :     if (Operand.isT2MemRegOffset())
    6264             :       return MCTargetAsmParser::Match_Success;
    6265             :     break;
    6266             :   // 'Imm8s4' class
    6267           0 :   case MCK_Imm8s4:
    6268             :     if (Operand.isImm8s4())
    6269             :       return MCTargetAsmParser::Match_Success;
    6270             :     break;
    6271             :   // 'MemPCRelImm12' class
    6272         221 :   case MCK_MemPCRelImm12:
    6273         221 :     if (Operand.isMemPCRelImm12())
    6274             :       return MCTargetAsmParser::Match_Success;
    6275             :     break;
    6276             :   // 'MemThumbRIs1' class
    6277         125 :   case MCK_MemThumbRIs1:
    6278          46 :     if (Operand.isMemThumbRIs1())
    6279             :       return MCTargetAsmParser::Match_Success;
    6280             :     break;
    6281             :   // 'MemThumbRIs2' class
    6282         120 :   case MCK_MemThumbRIs2:
    6283         120 :     if (Operand.isMemThumbRIs2())
    6284             :       return MCTargetAsmParser::Match_Success;
    6285             :     break;
    6286             :   // 'MemThumbRIs4' class
    6287         380 :   case MCK_MemThumbRIs4:
    6288         380 :     if (Operand.isMemThumbRIs4())
    6289             :       return MCTargetAsmParser::Match_Success;
    6290             :     break;
    6291             :   // 'MemThumbRR' class
    6292         641 :   case MCK_MemThumbRR:
    6293         641 :     if (Operand.isMemThumbRR())
    6294             :       return MCTargetAsmParser::Match_Success;
    6295             :     break;
    6296             :   // 'MemThumbSPI' class
    6297         340 :   case MCK_MemThumbSPI:
    6298         340 :     if (Operand.isMemThumbSPI())
    6299             :       return MCTargetAsmParser::Match_Success;
    6300             :     break;
    6301             :   // 'Imm0_1020s4' class
    6302          30 :   case MCK_Imm0_1020s4:
    6303             :     if (Operand.isImm0_1020s4())
    6304             :       return MCTargetAsmParser::Match_Success;
    6305             :     break;
    6306             :   // 'Imm0_508s4' class
    6307          68 :   case MCK_Imm0_508s4:
    6308             :     if (Operand.isImm0_508s4())
    6309             :       return MCTargetAsmParser::Match_Success;
    6310             :     break;
    6311             :   // 'Imm0_508s4Neg' class
    6312          27 :   case MCK_Imm0_508s4Neg:
    6313             :     if (Operand.isImm0_508s4Neg())
    6314             :       return MCTargetAsmParser::Match_Success;
    6315             :     break;
    6316             :   } // end switch (Kind)
    6317             : 
    6318      435498 :   if (Operand.isReg()) {
    6319             :     MatchClassKind OpKind;
    6320      283892 :     switch (Operand.getReg()) {
    6321             :     default: OpKind = InvalidMatchClass; break;
    6322             :     case ARM::R0: OpKind = MCK_Reg0; break;
    6323             :     case ARM::R1: OpKind = MCK_Reg0; break;
    6324             :     case ARM::R2: OpKind = MCK_Reg0; break;
    6325             :     case ARM::R3: OpKind = MCK_Reg0; break;
    6326             :     case ARM::R4: OpKind = MCK_tGPR; break;
    6327             :     case ARM::R5: OpKind = MCK_tGPR; break;
    6328             :     case ARM::R6: OpKind = MCK_tGPR; break;
    6329             :     case ARM::R7: OpKind = MCK_tGPR; break;
    6330             :     case ARM::R8: OpKind = MCK_Reg10; break;
    6331             :     case ARM::R9: OpKind = MCK_Reg10; break;
    6332             :     case ARM::R10: OpKind = MCK_Reg10; break;
    6333             :     case ARM::R11: OpKind = MCK_Reg10; break;
    6334             :     case ARM::R12: OpKind = MCK_Reg11; break;
    6335             :     case ARM::SP: OpKind = MCK_GPRsp; break;
    6336             :     case ARM::LR: OpKind = MCK_LR; break;
    6337             :     case ARM::PC: OpKind = MCK_PC; break;
    6338             :     case ARM::S0: OpKind = MCK_SPR_8; break;
    6339             :     case ARM::S1: OpKind = MCK_SPR_8; break;
    6340             :     case ARM::S2: OpKind = MCK_SPR_8; break;
    6341             :     case ARM::S3: OpKind = MCK_SPR_8; break;
    6342             :     case ARM::S4: OpKind = MCK_SPR_8; break;
    6343             :     case ARM::S5: OpKind = MCK_SPR_8; break;
    6344             :     case ARM::S6: OpKind = MCK_SPR_8; break;
    6345             :     case ARM::S7: OpKind = MCK_SPR_8; break;
    6346             :     case ARM::S8: OpKind = MCK_SPR_8; break;
    6347             :     case ARM::S9: OpKind = MCK_SPR_8; break;
    6348             :     case ARM::S10: OpKind = MCK_SPR_8; break;
    6349             :     case ARM::S11: OpKind = MCK_SPR_8; break;
    6350             :     case ARM::S12: OpKind = MCK_SPR_8; break;
    6351             :     case ARM::S13: OpKind = MCK_SPR_8; break;
    6352             :     case ARM::S14: OpKind = MCK_SPR_8; break;
    6353             :     case ARM::S15: OpKind = MCK_SPR_8; break;
    6354             :     case ARM::S16: OpKind = MCK_SPR; break;
    6355             :     case ARM::S17: OpKind = MCK_SPR; break;
    6356             :     case ARM::S18: OpKind = MCK_SPR; break;
    6357             :     case ARM::S19: OpKind = MCK_SPR; break;
    6358             :     case ARM::S20: OpKind = MCK_SPR; break;
    6359             :     case ARM::S21: OpKind = MCK_SPR; break;
    6360             :     case ARM::S22: OpKind = MCK_SPR; break;
    6361             :     case ARM::S23: OpKind = MCK_SPR; break;
    6362             :     case ARM::S24: OpKind = MCK_SPR; break;
    6363             :     case ARM::S25: OpKind = MCK_SPR; break;
    6364             :     case ARM::S26: OpKind = MCK_SPR; break;
    6365             :     case ARM::S27: OpKind = MCK_SPR; break;
    6366             :     case ARM::S28: OpKind = MCK_SPR; break;
    6367             :     case ARM::S29: OpKind = MCK_SPR; break;
    6368             :     case ARM::S30: OpKind = MCK_SPR; break;
    6369             :     case ARM::S31: OpKind = MCK_SPR; break;
    6370             :     case ARM::D0: OpKind = MCK_DPR_8; break;
    6371             :     case ARM::D1: OpKind = MCK_DPR_8; break;
    6372             :     case ARM::D2: OpKind = MCK_DPR_8; break;
    6373             :     case ARM::D3: OpKind = MCK_DPR_8; break;
    6374             :     case ARM::D4: OpKind = MCK_DPR_8; break;
    6375             :     case ARM::D5: OpKind = MCK_DPR_8; break;
    6376             :     case ARM::D6: OpKind = MCK_DPR_8; break;
    6377             :     case ARM::D7: OpKind = MCK_DPR_8; break;
    6378             :     case ARM::D8: OpKind = MCK_DPR_VFP2; break;
    6379             :     case ARM::D9: OpKind = MCK_DPR_VFP2; break;
    6380             :     case ARM::D10: OpKind = MCK_DPR_VFP2; break;
    6381             :     case ARM::D11: OpKind = MCK_DPR_VFP2; break;
    6382             :     case ARM::D12: OpKind = MCK_DPR_VFP2; break;
    6383             :     case ARM::D13: OpKind = MCK_DPR_VFP2; break;
    6384             :     case ARM::D14: OpKind = MCK_DPR_VFP2; break;
    6385             :     case ARM::D15: OpKind = MCK_DPR_VFP2; break;
    6386             :     case ARM::D16: OpKind = MCK_DPR; break;
    6387             :     case ARM::D17: OpKind = MCK_DPR; break;
    6388             :     case ARM::D18: OpKind = MCK_DPR; break;
    6389             :     case ARM::D19: OpKind = MCK_DPR; break;
    6390             :     case ARM::D20: OpKind = MCK_DPR; break;
    6391             :     case ARM::D21: OpKind = MCK_DPR; break;
    6392             :     case ARM::D22: OpKind = MCK_DPR; break;
    6393             :     case ARM::D23: OpKind = MCK_DPR; break;
    6394             :     case ARM::D24: OpKind = MCK_DPR; break;
    6395             :     case ARM::D25: OpKind = MCK_DPR; break;
    6396             :     case ARM::D26: OpKind = MCK_DPR; break;
    6397             :     case ARM::D27: OpKind = MCK_DPR; break;
    6398             :     case ARM::D28: OpKind = MCK_DPR; break;
    6399             :     case ARM::D29: OpKind = MCK_DPR; break;
    6400             :     case ARM::D30: OpKind = MCK_DPR; break;
    6401             :     case ARM::D31: OpKind = MCK_DPR; break;
    6402             :     case ARM::Q0: OpKind = MCK_QPR_8; break;
    6403             :     case ARM::Q1: OpKind = MCK_QPR_8; break;
    6404             :     case ARM::Q2: OpKind = MCK_QPR_8; break;
    6405             :     case ARM::Q3: OpKind = MCK_QPR_8; break;
    6406             :     case ARM::Q4: OpKind = MCK_QPR_VFP2; break;
    6407             :     case ARM::Q5: OpKind = MCK_QPR_VFP2; break;
    6408             :     case ARM::Q6: OpKind = MCK_QPR_VFP2; break;
    6409             :     case ARM::Q7: OpKind = MCK_QPR_VFP2; break;
    6410             :     case ARM::Q8: OpKind = MCK_QPR; break;
    6411             :     case ARM::Q9: OpKind = MCK_QPR; break;
    6412             :     case ARM::Q10: OpKind = MCK_QPR; break;
    6413             :     case ARM::Q11: OpKind = MCK_QPR; break;
    6414             :     case ARM::Q12: OpKind = MCK_QPR; break;
    6415             :     case ARM::Q13: OpKind = MCK_QPR; break;
    6416             :     case ARM::Q14: OpKind = MCK_QPR; break;
    6417             :     case ARM::Q15: OpKind = MCK_QPR; break;
    6418             :     case ARM::CPSR: OpKind = MCK_CCR; break;
    6419             :     case ARM::APSR: OpKind = MCK_APSR; break;
    6420             :     case ARM::APSR_NZCV: OpKind = MCK_APSR_NZCV; break;
    6421             :     case ARM::SPSR: OpKind = MCK_SPSR; break;
    6422             :     case ARM::FPSCR: OpKind = MCK_FPSCR; break;
    6423             :     case ARM::FPSID: OpKind = MCK_FPSID; break;
    6424             :     case ARM::MVFR2: OpKind = MCK_MVFR2; break;
    6425             :     case ARM::MVFR1: OpKind = MCK_MVFR1; break;
    6426             :     case ARM::MVFR0: OpKind = MCK_MVFR0; break;
    6427             :     case ARM::FPEXC: OpKind = MCK_FPEXC; break;
    6428             :     case ARM::FPINST: OpKind = MCK_FPINST; break;
    6429             :     case ARM::FPINST2: OpKind = MCK_FPINST2; break;
    6430             :     case ARM::D0_D2: OpKind = MCK_Reg40; break;
    6431             :     case ARM::D1_D3: OpKind = MCK_Reg40; break;
    6432             :     case ARM::D2_D4: OpKind = MCK_Reg40; break;
    6433             :     case ARM::D3_D5: OpKind = MCK_Reg40; break;
    6434             :     case ARM::D4_D6: OpKind = MCK_Reg40; break;
    6435             :     case ARM::D5_D7: OpKind = MCK_Reg40; break;
    6436             :     case ARM::D6_D8: OpKind = MCK_Reg41; break;
    6437             :     case ARM::D7_D9: OpKind = MCK_Reg41; break;
    6438             :     case ARM::D8_D10: OpKind = MCK_Reg42; break;
    6439             :     case ARM::D9_D11: OpKind = MCK_Reg42; break;
    6440             :     case ARM::D10_D12: OpKind = MCK_Reg42; break;
    6441             :     case ARM::D11_D13: OpKind = MCK_Reg42; break;
    6442             :     case ARM::D12_D14: OpKind = MCK_Reg42; break;
    6443             :     case ARM::D13_D15: OpKind = MCK_Reg42; break;
    6444             :     case ARM::D14_D16: OpKind = MCK_Reg43; break;
    6445             :     case ARM::D15_D17: OpKind = MCK_Reg43; break;
    6446             :     case ARM::D16_D18: OpKind = MCK_DPairSpc; break;
    6447             :     case ARM::D17_D19: OpKind = MCK_DPairSpc; break;
    6448             :     case ARM::D18_D20: OpKind = MCK_DPairSpc; break;
    6449             :     case ARM::D19_D21: OpKind = MCK_DPairSpc; break;
    6450             :     case ARM::D20_D22: OpKind = MCK_DPairSpc; break;
    6451             :     case ARM::D21_D23: OpKind = MCK_DPairSpc; break;
    6452             :     case ARM::D22_D24: OpKind = MCK_DPairSpc; break;
    6453             :     case ARM::D23_D25: OpKind = MCK_DPairSpc; break;
    6454             :     case ARM::D24_D26: OpKind = MCK_DPairSpc; break;
    6455             :     case ARM::D25_D27: OpKind = MCK_DPairSpc; break;
    6456             :     case ARM::D26_D28: OpKind = MCK_DPairSpc; break;
    6457             :     case ARM::D27_D29: OpKind = MCK_DPairSpc; break;
    6458             :     case ARM::D28_D30: OpKind = MCK_DPairSpc; break;
    6459             :     case ARM::D29_D31: OpKind = MCK_DPairSpc; break;
    6460             :     case ARM::Q0_Q1: OpKind = MCK_Reg45; break;
    6461             :     case ARM::Q1_Q2: OpKind = MCK_Reg45; break;
    6462             :     case ARM::Q2_Q3: OpKind = MCK_Reg45; break;
    6463             :     case ARM::Q3_Q4: OpKind = MCK_Reg46; break;
    6464             :     case ARM::Q4_Q5: OpKind = MCK_Reg47; break;
    6465             :     case ARM::Q5_Q6: OpKind = MCK_Reg47; break;
    6466             :     case ARM::Q6_Q7: OpKind = MCK_Reg47; break;
    6467             :     case ARM::Q7_Q8: OpKind = MCK_Reg48; break;
    6468             :     case ARM::Q8_Q9: OpKind = MCK_QQPR; break;
    6469             :     case ARM::Q9_Q10: OpKind = MCK_QQPR; break;
    6470             :     case ARM::Q10_Q11: OpKind = MCK_QQPR; break;
    6471             :     case ARM::Q11_Q12: OpKind = MCK_QQPR; break;
    6472             :     case ARM::Q12_Q13: OpKind = MCK_QQPR; break;
    6473             :     case ARM::Q13_Q14: OpKind = MCK_QQPR; break;
    6474             :     case ARM::Q14_Q15: OpKind = MCK_QQPR; break;
    6475             :     case ARM::Q0_Q1_Q2_Q3: OpKind = MCK_Reg59; break;
    6476             :     case ARM::Q1_Q2_Q3_Q4: OpKind = MCK_Reg60; break;
    6477             :     case ARM::Q2_Q3_Q4_Q5: OpKind = MCK_Reg61; break;
    6478             :     case ARM::Q3_Q4_Q5_Q6: OpKind = MCK_Reg62; break;
    6479             :     case ARM::Q4_Q5_Q6_Q7: OpKind = MCK_Reg63; break;
    6480             :     case ARM::Q5_Q6_Q7_Q8: OpKind = MCK_Reg64; break;
    6481             :     case ARM::Q6_Q7_Q8_Q9: OpKind = MCK_Reg65; break;
    6482             :     case ARM::Q7_Q8_Q9_Q10: OpKind = MCK_Reg66; break;
    6483             :     case ARM::Q8_Q9_Q10_Q11: OpKind = MCK_QQQQPR; break;
    6484             :     case ARM::Q9_Q10_Q11_Q12: OpKind = MCK_QQQQPR; break;
    6485             :     case ARM::Q10_Q11_Q12_Q13: OpKind = MCK_QQQQPR; break;
    6486             :     case ARM::Q11_Q12_Q13_Q14: OpKind = MCK_QQQQPR; break;
    6487             :     case ARM::Q12_Q13_Q14_Q15: OpKind = MCK_QQQQPR; break;
    6488             :     case ARM::R0_R1: OpKind = MCK_Reg68; break;
    6489             :     case ARM::R2_R3: OpKind = MCK_Reg68; break;
    6490             :     case ARM::R4_R5: OpKind = MCK_Reg69; break;
    6491             :     case ARM::R6_R7: OpKind = MCK_Reg69; break;
    6492             :     case ARM::R8_R9: OpKind = MCK_Reg73; break;
    6493             :     case ARM::R10_R11: OpKind = MCK_Reg73; break;
    6494             :     case ARM::R12_SP: OpKind = MCK_Reg75; break;
    6495             :     case ARM::D0_D1_D2: OpKind = MCK_Reg83; break;
    6496             :     case ARM::D1_D2_D3: OpKind = MCK_Reg88; break;
    6497             :     case ARM::D2_D3_D4: OpKind = MCK_Reg83; break;
    6498             :     case ARM::D3_D4_D5: OpKind = MCK_Reg88; break;
    6499             :     case ARM::D4_D5_D6: OpKind = MCK_Reg83; break;
    6500             :     case ARM::D5_D6_D7: OpKind = MCK_Reg88; break;
    6501             :     case ARM::D6_D7_D8: OpKind = MCK_Reg84; break;
    6502             :     case ARM::D7_D8_D9: OpKind = MCK_Reg89; break;
    6503             :     case ARM::D8_D9_D10: OpKind = MCK_Reg85; break;
    6504             :     case ARM::D9_D10_D11: OpKind = MCK_Reg90; break;
    6505             :     case ARM::D10_D11_D12: OpKind = MCK_Reg85; break;
    6506             :     case ARM::D11_D12_D13: OpKind = MCK_Reg90; break;
    6507             :     case ARM::D12_D13_D14: OpKind = MCK_Reg85; break;
    6508             :     case ARM::D13_D14_D15: OpKind = MCK_Reg90; break;
    6509             :     case ARM::D14_D15_D16: OpKind = MCK_Reg86; break;
    6510             :     case ARM::D15_D16_D17: OpKind = MCK_Reg91; break;
    6511             :     case ARM::D16_D17_D18: OpKind = MCK_Reg87; break;
    6512             :     case ARM::D17_D18_D19: OpKind = MCK_Reg92; break;
    6513             :     case ARM::D18_D19_D20: OpKind = MCK_Reg87; break;
    6514             :     case ARM::D19_D20_D21: OpKind = MCK_Reg92; break;
    6515             :     case ARM::D20_D21_D22: OpKind = MCK_Reg87; break;
    6516             :     case ARM::D21_D22_D23: OpKind = MCK_Reg92; break;
    6517             :     case ARM::D22_D23_D24: OpKind = MCK_Reg87; break;
    6518             :     case ARM::D23_D24_D25: OpKind = MCK_Reg92; break;
    6519             :     case ARM::D24_D25_D26: OpKind = MCK_Reg87; break;
    6520             :     case ARM::D25_D26_D27: OpKind = MCK_Reg92; break;
    6521             :     case ARM::D26_D27_D28: OpKind = MCK_Reg87; break;
    6522             :     case ARM::D27_D28_D29: OpKind = MCK_Reg92; break;
    6523             :     case ARM::D28_D29_D30: OpKind = MCK_Reg87; break;
    6524             :     case ARM::D29_D30_D31: OpKind = MCK_Reg92; break;
    6525             :     case ARM::D0_D2_D4: OpKind = MCK_Reg93; break;
    6526             :     case ARM::D1_D3_D5: OpKind = MCK_Reg93; break;
    6527             :     case ARM::D2_D4_D6: OpKind = MCK_Reg93; break;
    6528             :     case ARM::D3_D5_D7: OpKind = MCK_Reg93; break;
    6529             :     case ARM::D4_D6_D8: OpKind = MCK_Reg94; break;
    6530             :     case ARM::D5_D7_D9: OpKind = MCK_Reg94; break;
    6531             :     case ARM::D6_D8_D10: OpKind = MCK_Reg95; break;
    6532             :     case ARM::D7_D9_D11: OpKind = MCK_Reg95; break;
    6533             :     case ARM::D8_D10_D12: OpKind = MCK_Reg96; break;
    6534             :     case ARM::D9_D11_D13: OpKind = MCK_Reg96; break;
    6535             :     case ARM::D10_D12_D14: OpKind = MCK_Reg96; break;
    6536             :     case ARM::D11_D13_D15: OpKind = MCK_Reg96; break;
    6537             :     case ARM::D12_D14_D16: OpKind = MCK_Reg97; break;
    6538             :     case ARM::D13_D15_D17: OpKind = MCK_Reg97; break;
    6539             :     case ARM::D14_D16_D18: OpKind = MCK_Reg98; break;
    6540             :     case ARM::D15_D17_D19: OpKind = MCK_Reg98; break;
    6541             :     case ARM::D16_D18_D20: OpKind = MCK_DTripleSpc; break;
    6542             :     case ARM::D17_D19_D21: OpKind = MCK_DTripleSpc; break;
    6543             :     case ARM::D18_D20_D22: OpKind = MCK_DTripleSpc; break;
    6544             :     case ARM::D19_D21_D23: OpKind = MCK_DTripleSpc; break;
    6545             :     case ARM::D20_D22_D24: OpKind = MCK_DTripleSpc; break;
    6546             :     case ARM::D21_D23_D25: OpKind = MCK_DTripleSpc; break;
    6547             :     case ARM::D22_D24_D26: OpKind = MCK_DTripleSpc; break;
    6548             :     case ARM::D23_D25_D27: OpKind = MCK_DTripleSpc; break;
    6549             :     case ARM::D24_D26_D28: OpKind = MCK_DTripleSpc; break;
    6550             :     case ARM::D25_D27_D29: OpKind = MCK_DTripleSpc; break;
    6551             :     case ARM::D26_D28_D30: OpKind = MCK_DTripleSpc; break;
    6552             :     case ARM::D27_D29_D31: OpKind = MCK_DTripleSpc; break;
    6553             :     case ARM::D1_D2: OpKind = MCK_Reg26; break;
    6554             :     case ARM::D3_D4: OpKind = MCK_Reg26; break;
    6555             :     case ARM::D5_D6: OpKind = MCK_Reg26; break;
    6556             :     case ARM::D7_D8: OpKind = MCK_Reg27; break;
    6557             :     case ARM::D9_D10: OpKind = MCK_Reg24; break;
    6558             :     case ARM::D11_D12: OpKind = MCK_Reg24; break;
    6559             :     case ARM::D13_D14: OpKind = MCK_Reg24; break;
    6560             :     case ARM::D15_D16: OpKind = MCK_Reg25; break;
    6561             :     case ARM::D17_D18: OpKind = MCK_DPair; break;
    6562             :     case ARM::D19_D20: OpKind = MCK_DPair; break;
    6563             :     case ARM::D21_D22: OpKind = MCK_DPair; break;
    6564             :     case ARM::D23_D24: OpKind = MCK_DPair; break;
    6565             :     case ARM::D25_D26: OpKind = MCK_DPair; break;
    6566             :     case ARM::D27_D28: OpKind = MCK_DPair; break;
    6567             :     case ARM::D29_D30: OpKind = MCK_DPair; break;
    6568             :     case ARM::D1_D2_D3_D4: OpKind = MCK_Reg100; break;
    6569             :     case ARM::D3_D4_D5_D6: OpKind = MCK_Reg100; break;
    6570             :     case ARM::D5_D6_D7_D8: OpKind = MCK_Reg101; break;
    6571             :     case ARM::D7_D8_D9_D10: OpKind = MCK_Reg102; break;
    6572             :     case ARM::D9_D10_D11_D12: OpKind = MCK_Reg103; break;
    6573             :     case ARM::D11_D12_D13_D14: OpKind = MCK_Reg103; break;
    6574             :     case ARM::D13_D14_D15_D16: OpKind = MCK_Reg104; break;
    6575             :     case ARM::D15_D16_D17_D18: OpKind = MCK_Reg105; break;
    6576             :     case ARM::D17_D18_D19_D20: OpKind = MCK_Reg106; break;
    6577             :     case ARM::D19_D20_D21_D22: OpKind = MCK_Reg106; break;
    6578             :     case ARM::D21_D22_D23_D24: OpKind = MCK_Reg106; break;
    6579             :     case ARM::D23_D24_D25_D26: OpKind = MCK_Reg106; break;
    6580             :     case ARM::D25_D26_D27_D28: OpKind = MCK_Reg106; break;
    6581             :     case ARM::D27_D28_D29_D30: OpKind = MCK_Reg106; break;
    6582             :     }
    6583      141946 :     return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success :
    6584             :                                       MCTargetAsmParser::Match_InvalidOperand;
    6585             :   }
    6586             : 
    6587             :   return MCTargetAsmParser::Match_InvalidOperand;
    6588             : }
    6589             : 
    6590        1466 : uint64_t ARMAsmParser::
    6591             : ComputeAvailableFeatures(const FeatureBitset& FB) const {
    6592        1466 :   uint64_t Features = 0;
    6593        2932 :   if ((FB[ARM::HasV4TOps]))
    6594        1304 :     Features |= Feature_HasV4T;
    6595        2932 :   if ((FB[ARM::HasV5TOps]))
    6596        1219 :     Features |= Feature_HasV5T;
    6597        2932 :   if ((FB[ARM::HasV5TEOps]))
    6598        1169 :     Features |= Feature_HasV5TE;
    6599        2932 :   if ((FB[ARM::HasV6Ops]))
    6600        1159 :     Features |= Feature_HasV6;
    6601        2932 :   if ((FB[ARM::HasV6MOps]))
    6602        1114 :     Features |= Feature_HasV6M;
    6603        2932 :   if ((FB[ARM::HasV8MBaselineOps]))
    6604        1085 :     Features |= Feature_HasV8MBaseline;
    6605        2932 :   if ((FB[ARM::HasV8MMainlineOps]))
    6606           4 :     Features |= Feature_HasV8MMainline;
    6607        2932 :   if ((FB[ARM::HasV6T2Ops]))
    6608        1077 :     Features |= Feature_HasV6T2;
    6609        2932 :   if ((FB[ARM::HasV6KOps]))
    6610        1089 :     Features |= Feature_HasV6K;
    6611        2932 :   if ((FB[ARM::HasV7Ops]))
    6612        1062 :     Features |= Feature_HasV7;
    6613        2932 :   if ((FB[ARM::HasV8Ops]))
    6614         114 :     Features |= Feature_HasV8;
    6615        2932 :   if ((!FB[ARM::HasV8Ops]))
    6616        1352 :     Features |= Feature_PreV8;
    6617        2932 :   if ((FB[ARM::HasV8_1aOps]))
    6618          16 :     Features |= Feature_HasV8_1a;
    6619        2932 :   if ((FB[ARM::HasV8_2aOps]))
    6620          12 :     Features |= Feature_HasV8_2a;
    6621        2932 :   if ((FB[ARM::HasV8_3aOps]))
    6622           3 :     Features |= Feature_HasV8_3a;
    6623        2932 :   if ((FB[ARM::FeatureVFP2]))
    6624        1035 :     Features |= Feature_HasVFP2;
    6625        2932 :   if ((FB[ARM::FeatureVFP3]))
    6626        1021 :     Features |= Feature_HasVFP3;
    6627        2932 :   if ((FB[ARM::FeatureVFP4]))
    6628         151 :     Features |= Feature_HasVFP4;
    6629        2932 :   if ((!FB[ARM::FeatureVFPOnlySP]))
    6630        1460 :     Features |= Feature_HasDPVFP;
    6631        2932 :   if ((FB[ARM::FeatureFPARMv8]))
    6632         109 :     Features |= Feature_HasFPARMv8;
    6633        2932 :   if ((FB[ARM::FeatureNEON]))
    6634         959 :     Features |= Feature_HasNEON;
    6635        2932 :   if ((FB[ARM::FeatureCrypto]))
    6636          85 :     Features |= Feature_HasCrypto;
    6637        2932 :   if ((FB[ARM::FeatureDotProd]))
    6638           8 :     Features |= Feature_HasDotProd;
    6639        2932 :   if ((FB[ARM::FeatureCRC]))
    6640          99 :     Features |= Feature_HasCRC;
    6641        2932 :   if ((FB[ARM::FeatureRAS]))
    6642           8 :     Features |= Feature_HasRAS;
    6643        2932 :   if ((FB[ARM::FeatureFP16]))
    6644         165 :     Features |= Feature_HasFP16;
    6645        2932 :   if ((FB[ARM::FeatureFullFP16]))
    6646           6 :     Features |= Feature_HasFullFP16;
    6647        2932 :   if ((FB[ARM::FeatureHWDivThumb]))
    6648         210 :     Features |= Feature_HasDivideInThumb;
    6649        2932 :   if ((FB[ARM::FeatureHWDivARM]))
    6650         134 :     Features |= Feature_HasDivideInARM;
    6651        2932 :   if ((FB[ARM::FeatureDSP]))
    6652        1008 :     Features |= Feature_HasDSP;
    6653        2932 :   if ((FB[ARM::FeatureDB]))
    6654        1083 :     Features |= Feature_HasDB;
    6655        2932 :   if ((FB[ARM::FeatureV7Clrex]))
    6656        1070 :     Features |= Feature_HasV7Clrex;
    6657        2932 :   if ((FB[ARM::FeatureAcquireRelease]))
    6658         126 :     Features |= Feature_HasAcquireRelease;
    6659        2932 :   if ((FB[ARM::FeatureMP]))
    6660         137 :     Features |= Feature_HasMP;
    6661        2932 :   if ((FB[ARM::FeatureVirtualization]))
    6662         119 :     Features |= Feature_HasVirtualization;
    6663        2932 :   if ((FB[ARM::FeatureTrustZone]))
    6664         239 :     Features |= Feature_HasTrustZone;
    6665        2932 :   if ((FB[ARM::Feature8MSecExt]))
    6666          12 :     Features |= Feature_Has8MSecExt;
    6667        2932 :   if ((FB[ARM::ModeThumb]))
    6668         611 :     Features |= Feature_IsThumb;
    6669        3543 :   if ((FB[ARM::ModeThumb]) && (FB[ARM::FeatureThumb2]))
    6670         451 :     Features |= Feature_IsThumb2;
    6671        2932 :   if ((FB[ARM::FeatureMClass]))
    6672          96 :     Features |= Feature_IsMClass;
    6673        2932 :   if ((!FB[ARM::FeatureMClass]))
    6674        1370 :     Features |= Feature_IsNotMClass;
    6675        2932 :   if ((!FB[ARM::ModeThumb]))
    6676         855 :     Features |= Feature_IsARM;
    6677        2932 :   if ((FB[ARM::FeatureNaClTrap]))
    6678           2 :     Features |= Feature_UseNaClTrap;
    6679        2932 :   if ((!FB[ARM::FeatureNoNegativeImmediates]))
    6680        1463 :     Features |= Feature_UseNegativeImmediates;
    6681        1466 :   return Features;
    6682             : }
    6683             : 
    6684             : static const char *const MnemonicTable =
    6685             :     "\t__brkdiv0\003adc\003add\004addw\003adr\004aesd\004aese\006aesimc\005a"
    6686             :     "esmc\003and\003asr\001b\003bfc\003bfi\003bic\004bkpt\002bl\003blx\005bl"
    6687             :     "xns\002bx\003bxj\004bxns\004cbnz\003cbz\003cdp\004cdp2\005clrex\003clz\003"
    6688             :     "cmn\003cmp\003cps\006crc32b\007crc32cb\007crc32ch\007crc32cw\006crc32h\006"
    6689             :     "crc32w\003dbg\005dcps1\005dcps2\005dcps3\003dmb\003dsb\003eor\004eret\003"
    6690             :     "esb\005faddd\005fadds\006fcmpzd\006fcmpzs\007fconstd\007fconsts\007fldm"
    6691             :     "dbx\007fldmiax\005fmdhr\005fmdlr\006fmstat\007fstmdbx\007fstmiax\005fsu"
    6692             :     "bd\005fsubs\004hint\003hlt\003hvc\003isb\002it\003lda\004ldab\005ldaex\006"
    6693             :     "ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ldc2\005ldc2l\004ldcl\003l"
    6694             :     "dm\005ldmda\005ldmdb\005ldmib\003ldr\004ldrb\005ldrbt\004ldrd\005ldrex\006"
    6695             :     "ldrexb\006ldrexd\006ldrexh\004ldrh\005ldrht\005ldrsb\006ldrsbt\005ldrsh"
    6696             :     "\006ldrsht\004ldrt\003lsl\003lsr\003mcr\004mcr2\004mcrr\005mcrr2\003mla"
    6697             :     "\003mls\003mov\004movs\004movt\004movw\003mrc\004mrc2\004mrrc\005mrrc2\003"
    6698             :     "mrs\003msr\003mul\003mvn\003neg\003nop\003orn\003orr\005pkhbt\005pkhtb\003"
    6699             :     "pld\004pldw\003pli\003pop\004push\004qadd\006qadd16\005qadd8\004qasx\005"
    6700             :     "qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub8\004rbit\003rev\005rev"
    6701             :     "16\005revsh\005rfeda\005rfedb\005rfeia\005rfeib\003ror\003rrx\003rsb\003"
    6702             :     "rsc\006sadd16\005sadd8\004sasx\003sbc\004sbfx\004sdiv\003sel\006setend\006"
    6703             :     "setpan\003sev\004sevl\002sg\005sha1c\005sha1h\005sha1m\005sha1p\007sha1"
    6704             :     "su0\007sha1su1\007sha256h\010sha256h2\tsha256su0\tsha256su1\007shadd16\006"
    6705             :     "shadd8\005shasx\005shsax\007shsub16\006shsub8\003smc\006smlabb\006smlab"
    6706             :     "t\005smlad\006smladx\005smlal\007smlalbb\007smlalbt\006smlald\007smlald"
    6707             :     "x\007smlaltb\007smlaltt\006smlatb\006smlatt\006smlawb\006smlawt\005smls"
    6708             :     "d\006smlsdx\006smlsld\007smlsldx\005smmla\006smmlar\005smmls\006smmlsr\005"
    6709             :     "smmul\006smmulr\005smuad\006smuadx\006smulbb\006smulbt\005smull\006smul"
    6710             :     "tb\006smultt\006smulwb\006smulwt\005smusd\006smusdx\005srsda\005srsdb\005"
    6711             :     "srsia\005srsib\004ssat\006ssat16\004ssax\006ssub16\005ssub8\003stc\004s"
    6712             :     "tc2\005stc2l\004stcl\003stl\004stlb\005stlex\006stlexb\006stlexd\006stl"
    6713             :     "exh\004stlh\003stm\005stmda\005stmdb\005stmib\003str\004strb\005strbt\004"
    6714             :     "strd\005strex\006strexb\006strexd\006strexh\004strh\005strht\004strt\003"
    6715             :     "sub\004subs\004subw\003svc\003swp\004swpb\005sxtab\007sxtab16\005sxtah\004"
    6716             :     "sxtb\006sxtb16\004sxth\003tbb\003tbh\003teq\004trap\003tst\002tt\003tta"
    6717             :     "\004ttat\003ttt\006uadd16\005uadd8\004uasx\004ubfx\003udf\004udiv\007uh"
    6718             :     "add16\006uhadd8\005uhasx\005uhsax\007uhsub16\006uhsub8\005umaal\005umla"
    6719             :     "l\005umull\007uqadd16\006uqadd8\005uqasx\005uqsax\007uqsub16\006uqsub8\005"
    6720             :     "usad8\006usada8\004usat\006usat16\004usax\006usub16\005usub8\005uxtab\007"
    6721             :     "uxtab16\005uxtah\004uxtb\006uxtb16\004uxth\004vaba\005vabal\004vabd\005"
    6722             :     "vabdl\004vabs\005vacge\005vacgt\005vacle\005vaclt\004vadd\006vaddhn\005"
    6723             :     "vaddl\005vaddw\004vand\004vbic\004vbif\004vbit\004vbsl\004vceq\004vcge\004"
    6724             :     "vcgt\004vcle\004vcls\004vclt\004vclz\004vcmp\005vcmpe\004vcnt\004vcvt\005"
    6725             :     "vcvta\005vcvtb\005vcvtm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\004vdiv\004"
    6726             :     "vdup\004veor\004vext\004vfma\004vfms\005vfnma\005vfnms\005vhadd\005vhsu"
    6727             :     "b\004vins\005vjcvt\004vld1\004vld2\004vld3\004vld4\006vldmdb\006vldmia\004"
    6728             :     "vldr\005vlldm\005vlstm\004vmax\006vmaxnm\004vmin\006vminnm\004vmla\005v"
    6729             :     "mlal\004vmls\005vmlsl\004vmov\005vmovl\005vmovn\005vmovx\004vmrs\004vms"
    6730             :     "r\004vmul\005vmull\004vmvn\004vneg\005vnmla\005vnmls\005vnmul\004vorn\004"
    6731             :     "vorr\006vpadal\005vpadd\006vpaddl\005vpmax\005vpmin\004vpop\005vpush\005"
    6732             :     "vqabs\005vqadd\007vqdmlal\007vqdmlsl\007vqdmulh\007vqdmull\006vqmovn\007"
    6733             :     "vqmovun\005vqneg\010vqrdmlah\010vqrdmlsh\010vqrdmulh\006vqrshl\007vqrsh"
    6734             :     "rn\010vqrshrun\005vqshl\006vqshlu\006vqshrn\007vqshrun\005vqsub\007vrad"
    6735             :     "dhn\006vrecpe\006vrecps\006vrev16\006vrev32\006vrev64\006vrhadd\006vrin"
    6736             :     "ta\006vrintm\006vrintn\006vrintp\006vrintr\006vrintx\006vrintz\005vrshl"
    6737             :     "\005vrshr\006vrshrn\007vrsqrte\007vrsqrts\005vrsra\007vrsubhn\005vsdot\006"
    6738             :     "vseleq\006vselge\006vselgt\006vselvs\004vshl\005vshll\004vshr\005vshrn\004"
    6739             :     "vsli\005vsqrt\004vsra\004vsri\004vst1\004vst2\004vst3\004vst4\006vstmdb"
    6740             :     "\006vstmia\004vstr\004vsub\006vsubhn\005vsubl\005vsubw\004vswp\004vtbl\004"
    6741             :     "vtbx\004vtrn\004vtst\005vudot\004vuzp\004vzip\003wfe\003wfi\005yield";
    6742             : 
    6743             : namespace {
    6744             :   struct MatchEntry {
    6745             :     uint16_t Mnemonic;
    6746             :     uint16_t Opcode;
    6747             :     uint16_t ConvertFn;
    6748             :     uint64_t RequiredFeatures;
    6749             :     uint16_t Classes[18];
    6750             :     StringRef getMnemonic() const {
    6751      529377 :       return StringRef(MnemonicTable + Mnemonic + 1,
    6752      529377 :                        MnemonicTable[Mnemonic]);
    6753             :     }
    6754             :   };
    6755             : 
    6756             :   // Predicate for searching for an opcode.
    6757             :   struct LessOpcode {
    6758             :     bool operator()(const MatchEntry &LHS, StringRef RHS) {
    6759      574340 :       return LHS.getMnemonic() < RHS;
    6760             :     }
    6761             :     bool operator()(StringRef LHS, const MatchEntry &RHS) {
    6762      453852 :       return LHS < RHS.getMnemonic();
    6763             :     }
    6764             :     bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
    6765             :       return LHS.getMnemonic() < RHS.getMnemonic();
    6766             :     }
    6767             :   };
    6768             : } // end anonymous namespace.
    6769             : 
    6770             : static const MatchEntry MatchTable0[] = {
    6771             :   { 0 /* __brkdiv0 */, ARM::t__brkdiv0, Convert_NoOperands, Feature_IsThumb, {  }, },
    6772             :   { 10 /* adc */, ARM::tADC, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    6773             :   { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
    6774             :   { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6775             :   { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    6776             :   { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
    6777             :   { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    6778             :   { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6779             :   { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    6780             :   { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    6781             :   { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
    6782             :   { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
    6783             :   { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    6784             :   { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    6785             :   { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
    6786             :   { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    6787             :   { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6788             :   { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    6789             :   { 14 /* add */, ARM::tADDspr, Convert__Reg1_1__Tie0__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPR }, },
    6790             :   { 14 /* add */, ARM::tADDspi, Convert__Reg1_1__Tie0__Imm0_508s41_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
    6791             :   { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0__Imm0_508s4Neg1_2__CondCode2_0, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
    6792             :   { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095 }, },
    6793             :   { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095Neg }, },
    6794             :   { 14 /* add */, ARM::tADDhirr, Convert__Reg1_1__Tie0__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6795             :   { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    6796             :   { 14 /* add */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
    6797             :   { 14 /* add */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0__ThumbModImmNeg8_2551_3__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
    6798             :   { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
    6799             :   { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
    6800             :   { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
    6801             :   { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImmNeg }, },
    6802             :   { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImmNeg }, },
    6803             :   { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6804             :   { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    6805             :   { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
    6806             :   { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    6807             :   { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    6808             :   { 14 /* add */, ARM::tADDspi, Convert__regSP__Tie0__Imm0_508s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
    6809             :   { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0__Imm0_508s4Neg1_3__CondCode2_0, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
    6810             :   { 14 /* add */, ARM::tADDrSPi, Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_GPRsp, MCK_Imm0_1020s4 }, },
    6811             :   { 14 /* add */, ARM::t2ADR, Convert__Reg1_1__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_PC, MCK_Imm0_4095 }, },
    6812             :   { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
    6813             :   { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, },
    6814             :   { 14 /* add */, ARM::tADDrSP, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPRsp, MCK_GPR }, },
    6815             :   { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImmNeg }, },
    6816             :   { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
    6817             :   { 14 /* add */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
    6818             :   { 14 /* add */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
    6819             :   { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
    6820             :   { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
    6821             :   { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
    6822             :   { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
    6823             :   { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
    6824             :   { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    6825             :   { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    6826             :   { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
    6827             :   { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    6828             :   { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
    6829             :   { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
    6830             :   { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
    6831             :   { 14 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
    6832             :   { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
    6833             :   { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
    6834             :   { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095Neg }, },
    6835             :   { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
    6836             :   { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, },
    6837             :   { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, },
    6838             :   { 23 /* adr */, ARM::tADR, Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_UnsignedOffset_b8s2 }, },
    6839             :   { 23 /* adr */, ARM::t2ADR, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
    6840             :   { 23 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, },
    6841             :   { 23 /* adr */, ARM::t2ADR, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm }, },
    6842             :   { 27 /* aesd */, ARM::AESD, Convert__Reg1_1__Tie0__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
    6843             :   { 32 /* aese */, ARM::AESE, Convert__Reg1_1__Tie0__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
    6844             :   { 37 /* aesimc */, ARM::AESIMC, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
    6845             :   { 44 /* aesmc */, ARM::AESMC, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
    6846             :   { 50 /* and */, ARM::tAND, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    6847             :   { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    6848             :   { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    6849             :   { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    6850             :   { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
    6851             :   { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6852             :   { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    6853             :   { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
    6854             :   { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    6855             :   { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    6856             :   { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    6857             :   { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
    6858             :   { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
    6859             :   { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6860             :   { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    6861             :   { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    6862             :   { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
    6863             :   { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    6864             :   { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    6865             :   { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
    6866             :   { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    6867             :   { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
    6868             :   { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6869             :   { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    6870             :   { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    6871             :   { 54 /* asr */, ARM::tASRrr, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    6872             :   { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
    6873             :   { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    6874             :   { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
    6875             :   { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    6876             :   { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
    6877             :   { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    6878             :   { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
    6879             :   { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
    6880             :   { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6881             :   { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
    6882             :   { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    6883             :   { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
    6884             :   { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6885             :   { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
    6886             :   { 58 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
    6887             :   { 58 /* b */, ARM::tB, ConvertCustom_cvtThumbBranches, Feature_IsThumb, { MCK_CondCode, MCK_Imm }, },
    6888             :   { 58 /* b */, ARM::tBcc, ConvertCustom_cvtThumbBranches, Feature_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
    6889             :   { 58 /* b */, ARM::t2Bcc, ConvertCustom_cvtThumbBranches, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
    6890             :   { 58 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, },
    6891             :   { 60 /* bfc */, ARM::t2BFC, Convert__Reg1_1__Tie0__Bitfield1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Bitfield }, },
    6892             :   { 60 /* bfc */, ARM::BFC, Convert__Reg1_1__Tie0__Bitfield1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Bitfield }, },
    6893             :   { 64 /* bfi */, ARM::t2BFI, Convert__Reg1_1__Tie0__Reg1_2__Bitfield1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Bitfield }, },
    6894             :   { 64 /* bfi */, ARM::BFI, Convert__Reg1_1__Tie0__Reg1_2__Bitfield1_3__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Bitfield }, },
    6895             :   { 68 /* bic */, ARM::tBIC, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    6896             :   { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    6897             :   { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    6898             :   { 68 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    6899             :   { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
    6900             :   { 68 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6901             :   { 68 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    6902             :   { 68 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
    6903             :   { 68 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    6904             :   { 68 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    6905             :   { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    6906             :   { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
    6907             :   { 68 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
    6908             :   { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6909             :   { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    6910             :   { 68 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    6911             :   { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
    6912             :   { 68 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    6913             :   { 68 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    6914             :   { 68 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
    6915             :   { 68 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    6916             :   { 68 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
    6917             :   { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6918             :   { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    6919             :   { 68 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    6920             :   { 72 /* bkpt */, ARM::BKPT, Convert__imm_95_0, Feature_IsARM, {  }, },
    6921             :   { 72 /* bkpt */, ARM::tBKPT, Convert__imm_95_0, Feature_IsThumb, {  }, },
    6922             :   { 72 /* bkpt */, ARM::tBKPT, Convert__Imm0_2551_0, Feature_IsThumb, { MCK_Imm0_255 }, },
    6923             :   { 72 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, Feature_IsARM, { MCK_Imm0_65535 }, },
    6924             :   { 77 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, Feature_IsARM, { MCK_ARMBranchTarget }, },
    6925             :   { 77 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
    6926             :   { 77 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_1, Feature_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
    6927             :   { 80 /* blx */, ARM::BLX, Convert__Reg1_0, Feature_IsARM|Feature_HasV5T, { MCK_GPR }, },
    6928             :   { 80 /* blx */, ARM::BLXi, Convert__ThumbBranchTarget1_0, Feature_IsARM|Feature_HasV5T, { MCK_ThumbBranchTarget }, },
    6929             :   { 80 /* blx */, ARM::BLX_pred, Convert__Reg1_1__CondCode2_0, Feature_IsARM|Feature_HasV5T, { MCK_CondCode, MCK_GPR }, },
    6930             :   { 80 /* blx */, ARM::tBLXr, Convert__CondCode2_0__Reg1_1, Feature_IsThumb|Feature_HasV5T, { MCK_CondCode, MCK_GPR }, },
    6931             :   { 80 /* blx */, ARM::tBLXi, Convert__CondCode2_0__ARMBranchTarget1_1, Feature_IsThumb|Feature_HasV5T|Feature_IsNotMClass, { MCK_CondCode, MCK_ARMBranchTarget }, },
    6932             :   { 84 /* blxns */, ARM::tBLXNSr, Convert__CondCode2_0__Reg1_1, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
    6933             :   { 90 /* bx */, ARM::BX, Convert__Reg1_0, Feature_IsARM|Feature_HasV4T, { MCK_GPR }, },
    6934             :   { 90 /* bx */, ARM::BX_RET, Convert__CondCode2_0, Feature_IsARM|Feature_HasV4T, { MCK_CondCode, MCK_LR }, },
    6935             :   { 90 /* bx */, ARM::BX_pred, Convert__Reg1_1__CondCode2_0, Feature_IsARM|Feature_HasV4T, { MCK_CondCode, MCK_GPR }, },
    6936             :   { 90 /* bx */, ARM::tBX, Convert__Reg1_1__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR }, },
    6937             :   { 93 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, },
    6938             :   { 93 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR }, },
    6939             :   { 97 /* bxns */, ARM::tBXNS, Convert__Reg1_1__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPR }, },
    6940             :   { 102 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
    6941             :   { 107 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
    6942             :   { 111 /* cdp */, ARM::CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    6943             :   { 111 /* cdp */, ARM::t2CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    6944             :   { 115 /* cdp2 */, ARM::CDP2, Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    6945             :   { 115 /* cdp2 */, ARM::t2CDP2, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    6946             :   { 120 /* clrex */, ARM::CLREX, Convert_NoOperands, Feature_IsARM|Feature_HasV6K, {  }, },
    6947             :   { 120 /* clrex */, ARM::t2CLREX, Convert__CondCode2_0, Feature_IsThumb|Feature_HasV7Clrex, { MCK_CondCode }, },
    6948             :   { 126 /* clz */, ARM::t2CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    6949             :   { 126 /* clz */, ARM::CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV5T, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6950             :   { 130 /* cmn */, ARM::tCMNz, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    6951             :   { 130 /* cmn */, ARM::CMPri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
    6952             :   { 130 /* cmn */, ARM::t2CMPri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
    6953             :   { 130 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
    6954             :   { 130 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
    6955             :   { 130 /* cmn */, ARM::CMNzrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
    6956             :   { 130 /* cmn */, ARM::t2CMNri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
    6957             :   { 130 /* cmn */, ARM::CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6958             :   { 130 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    6959             :   { 130 /* cmn */, ARM::CMNzrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    6960             :   { 130 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
    6961             :   { 130 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
    6962             :   { 130 /* cmn */, ARM::t2CMNri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
    6963             :   { 134 /* cmp */, ARM::tCMPr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    6964             :   { 134 /* cmp */, ARM::tCMPi8, Convert__Reg1_1__Imm0_2551_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
    6965             :   { 134 /* cmp */, ARM::CMNri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
    6966             :   { 134 /* cmp */, ARM::t2CMNri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
    6967             :   { 134 /* cmp */, ARM::t2CMPrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
    6968             :   { 134 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
    6969             :   { 134 /* cmp */, ARM::t2CMPri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
    6970             :   { 134 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6971             :   { 134 /* cmp */, ARM::tCMPhir, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    6972             :   { 134 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    6973             :   { 134 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    6974             :   { 134 /* cmp */, ARM::t2CMPrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
    6975             :   { 134 /* cmp */, ARM::t2CMPrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
    6976             :   { 134 /* cmp */, ARM::t2CMPri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
    6977             :   { 138 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm0_31 }, },
    6978             :   { 138 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
    6979             :   { 138 /* cps */, ARM::tCPS, Convert__Imm1_0__imm_95_0, Feature_IsThumb, { MCK_Imm }, },
    6980             :   { 138 /* cps */, ARM::tCPS, Convert__Imm1_0__imm_95_0, Feature_IsThumb, { MCK_Imm }, },
    6981             :   { 138 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_1, Feature_IsThumb2, { MCK__DOT_w, MCK_Imm0_31 }, },
    6982             :   { 138 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, Feature_IsARM, { MCK_Imm, MCK_ProcIFlags }, },
    6983             :   { 138 /* cps */, ARM::tCPS, Convert__Imm1_0__ProcIFlags1_1, Feature_IsThumb, { MCK_Imm, MCK_ProcIFlags }, },
    6984             :   { 138 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, },
    6985             :   { 138 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, Feature_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, },
    6986             :   { 138 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, },
    6987             :   { 138 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_2__Imm1_3, Feature_IsThumb2, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags, MCK_Imm }, },
    6988             :   { 142 /* crc32b */, ARM::t2CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6989             :   { 142 /* crc32b */, ARM::CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    6990             :   { 149 /* crc32cb */, ARM::t2CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6991             :   { 149 /* crc32cb */, ARM::CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    6992             :   { 157 /* crc32ch */, ARM::t2CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6993             :   { 157 /* crc32ch */, ARM::CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    6994             :   { 165 /* crc32cw */, ARM::t2CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6995             :   { 165 /* crc32cw */, ARM::CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    6996             :   { 173 /* crc32h */, ARM::t2CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6997             :   { 173 /* crc32h */, ARM::CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    6998             :   { 180 /* crc32w */, ARM::t2CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    6999             :   { 180 /* crc32w */, ARM::CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7000             :   { 187 /* dbg */, ARM::DBG, Convert__Imm0_151_1__CondCode2_0, Feature_IsARM|Feature_HasV7, { MCK_CondCode, MCK_Imm0_15 }, },
    7001             :   { 187 /* dbg */, ARM::t2DBG, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_15 }, },
    7002             :   { 191 /* dcps1 */, ARM::t2DCPS1, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, },
    7003             :   { 197 /* dcps2 */, ARM::t2DCPS2, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, },
    7004             :   { 203 /* dcps3 */, ARM::t2DCPS3, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, },
    7005             :   { 209 /* dmb */, ARM::DMB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, {  }, },
    7006             :   { 209 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, },
    7007             :   { 209 /* dmb */, ARM::DMB, Convert__MemBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_MemBarrierOpt }, },
    7008             :   { 209 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
    7009             :   { 213 /* dsb */, ARM::DSB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, {  }, },
    7010             :   { 213 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, },
    7011             :   { 213 /* dsb */, ARM::DSB, Convert__MemBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_MemBarrierOpt }, },
    7012             :   { 213 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
    7013             :   { 217 /* eor */, ARM::tEOR, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7014             :   { 217 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7015             :   { 217 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    7016             :   { 217 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    7017             :   { 217 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7018             :   { 217 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7019             :   { 217 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7020             :   { 217 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    7021             :   { 217 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7022             :   { 217 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
    7023             :   { 217 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
    7024             :   { 217 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7025             :   { 217 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    7026             :   { 217 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    7027             :   { 217 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7028             :   { 217 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    7029             :   { 217 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    7030             :   { 217 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
    7031             :   { 217 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7032             :   { 217 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    7033             :   { 217 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    7034             :   { 221 /* eret */, ARM::ERET, Convert__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode }, },
    7035             :   { 221 /* eret */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, Feature_IsThumb2|Feature_HasVirtualization, { MCK_CondCode }, },
    7036             :   { 226 /* esb */, ARM::HINT, Convert__imm_95_16__CondCode2_0, Feature_IsARM|Feature_HasRAS, { MCK_CondCode }, },
    7037             :   { 226 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, Feature_IsThumb2|Feature_HasRAS, { MCK_CondCode }, },
    7038             :   { 226 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, Feature_IsThumb2|Feature_HasRAS, { MCK_CondCode, MCK__DOT_w }, },
    7039             :   { 230 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
    7040             :   { 236 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_SPR, MCK_SPR, MCK_SPR }, },
    7041             :   { 242 /* fcmpzd */, ARM::VCMPZD, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR }, },
    7042             :   { 249 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_SPR }, },
    7043             :   { 256 /* fconstd */, ARM::FCONSTD, Convert__Reg1_1__FPImm1_2__CondCode2_0, Feature_HasVFP3, { MCK_CondCode, MCK_DPR, MCK_FPImm }, },
    7044             :   { 264 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, Feature_HasVFP3, { MCK_CondCode, MCK_SPR, MCK_FPImm }, },
    7045             :   { 272 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
    7046             :   { 280 /* fldmiax */, ARM::FLDMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
    7047             :   { 280 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
    7048             :   { 288 /* fmdhr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0__Reg1_2__imm_95_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
    7049             :   { 294 /* fmdlr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0__Reg1_2__imm_95_0__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
    7050             :   { 300 /* fmstat */, ARM::FMSTAT, Convert__CondCode2_0, Feature_HasVFP2, { MCK_CondCode }, },
    7051             :   { 307 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
    7052             :   { 315 /* fstmiax */, ARM::FSTMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
    7053             :   { 315 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
    7054             :   { 323 /* fsubd */, ARM::VSUBD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
    7055             :   { 329 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_SPR, MCK_SPR, MCK_SPR }, },
    7056             :   { 335 /* hint */, ARM::tHINT, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode, MCK_Imm0_15 }, },
    7057             :   { 335 /* hint */, ARM::HINT, Convert__Imm0_2391_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_Imm0_239 }, },
    7058             :   { 335 /* hint */, ARM::t2HINT, Convert__Imm0_2391_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_239 }, },
    7059             :   { 335 /* hint */, ARM::t2HINT, Convert__Imm0_2391_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_239 }, },
    7060             :   { 340 /* hlt */, ARM::tHLT, Convert__Imm0_631_0, Feature_IsThumb|Feature_HasV8, { MCK_Imm0_63 }, },
    7061             :   { 340 /* hlt */, ARM::HLT, Convert__Imm0_655351_0, Feature_IsARM|Feature_HasV8, { MCK_Imm0_65535 }, },
    7062             :   { 344 /* hvc */, ARM::HVC, Convert__Imm0_655351_0, Feature_IsARM|Feature_HasVirtualization, { MCK_Imm0_65535 }, },
    7063             :   { 344 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_0, Feature_IsThumb2, { MCK_Imm0_65535 }, },
    7064             :   { 344 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_1, Feature_IsThumb2|Feature_HasVirtualization, { MCK__DOT_w, MCK_Imm0_65535 }, },
    7065             :   { 348 /* isb */, ARM::ISB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, {  }, },
    7066             :   { 348 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, },
    7067             :   { 348 /* isb */, ARM::ISB, Convert__InstSyncBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_InstSyncBarrierOpt }, },
    7068             :   { 348 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_InstSyncBarrierOpt }, },
    7069             :   { 352 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, Feature_IsARM, { MCK_ITMask, MCK_ITCondCode }, },
    7070             :   { 352 /* it */, ARM::t2IT, Convert__ITCondCode1_1__ITMask1_0, Feature_IsThumb2, { MCK_ITMask, MCK_ITCondCode }, },
    7071             :   { 355 /* lda */, ARM::t2LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7072             :   { 355 /* lda */, ARM::LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7073             :   { 359 /* ldab */, ARM::t2LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7074             :   { 359 /* ldab */, ARM::LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7075             :   { 364 /* ldaex */, ARM::t2LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7076             :   { 364 /* ldaex */, ARM::LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7077             :   { 370 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7078             :   { 370 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7079             :   { 377 /* ldaexd */, ARM::LDAEXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
    7080             :   { 377 /* ldaexd */, ARM::t2LDAEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7081             :   { 384 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7082             :   { 384 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7083             :   { 391 /* ldah */, ARM::t2LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7084             :   { 391 /* ldah */, ARM::LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7085             :   { 396 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7086             :   { 396 /* ldc */, ARM::t2LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7087             :   { 396 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7088             :   { 396 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7089             :   { 396 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7090             :   { 396 /* ldc */, ARM::t2LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7091             :   { 396 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7092             :   { 396 /* ldc */, ARM::t2LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7093             :   { 400 /* ldc2 */, ARM::LDC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7094             :   { 400 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7095             :   { 400 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7096             :   { 400 /* ldc2 */, ARM::LDC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7097             :   { 400 /* ldc2 */, ARM::LDC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7098             :   { 400 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7099             :   { 400 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7100             :   { 400 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7101             :   { 405 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7102             :   { 405 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7103             :   { 405 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7104             :   { 405 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7105             :   { 405 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7106             :   { 405 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7107             :   { 405 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7108             :   { 405 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7109             :   { 411 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7110             :   { 411 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7111             :   { 411 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7112             :   { 411 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7113             :   { 411 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7114             :   { 411 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7115             :   { 411 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7116             :   { 411 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7117             :   { 416 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_RegList }, },
    7118             :   { 416 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7119             :   { 416 /* ldm */, ARM::t2LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7120             :   { 416 /* ldm */, ARM::t2LDMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
    7121             :   { 416 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
    7122             :   { 416 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7123             :   { 416 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7124             :   { 416 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
    7125             :   { 416 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7126             :   { 416 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
    7127             :   { 420 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7128             :   { 420 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7129             :   { 420 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
    7130             :   { 420 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
    7131             :   { 426 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7132             :   { 426 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7133             :   { 426 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
    7134             :   { 426 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7135             :   { 426 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7136             :   { 426 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
    7137             :   { 426 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7138             :   { 426 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
    7139             :   { 432 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7140             :   { 432 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7141             :   { 432 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
    7142             :   { 432 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
    7143             :   { 438 /* ldr */, ARM::tLDRpci, Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ThumbMemPC }, },
    7144             :   { 438 /* ldr */, ARM::tLDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ConstPoolAsmImm }, },
    7145             :   { 438 /* ldr */, ARM::tLDRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
    7146             :   { 438 /* ldr */, ARM::tLDRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
    7147             :   { 438 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
    7148             :   { 438 /* ldr */, ARM::t2LDRpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_Imm }, },
    7149             :   { 438 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
    7150             :   { 438 /* ldr */, ARM::t2LDRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
    7151             :   { 438 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
    7152             :   { 438 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
    7153             :   { 438 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
    7154             :   { 438 /* ldr */, ARM::t2LDRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
    7155             :   { 438 /* ldr */, ARM::t2LDRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
    7156             :   { 438 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemPCRelImm12 }, },
    7157             :   { 438 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_ConstPoolAsmImm }, },
    7158             :   { 438 /* ldr */, ARM::t2LDRpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_Imm }, },
    7159             :   { 438 /* ldr */, ARM::t2LDRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
    7160             :   { 438 /* ldr */, ARM::t2LDRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
    7161             :   { 438 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemPCRelImm12 }, },
    7162             :   { 438 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
    7163             :   { 438 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
    7164             :   { 438 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
    7165             :   { 438 /* ldr */, ARM::t2LDR_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
    7166             :   { 438 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
    7167             :   { 438 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
    7168             :   { 442 /* ldrb */, ARM::tLDRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
    7169             :   { 442 /* ldrb */, ARM::tLDRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
    7170             :   { 442 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
    7171             :   { 442 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
    7172             :   { 442 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
    7173             :   { 442 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
    7174             :   { 442 /* ldrb */, ARM::t2LDRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
    7175             :   { 442 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
    7176             :   { 442 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
    7177             :   { 442 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
    7178             :   { 442 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
    7179             :   { 442 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
    7180             :   { 442 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
    7181             :   { 442 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
    7182             :   { 442 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
    7183             :   { 442 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
    7184             :   { 442 /* ldrb */, ARM::t2LDRB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
    7185             :   { 442 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
    7186             :   { 442 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
    7187             :   { 447 /* ldrbt */, ARM::t2LDRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
    7188             :   { 447 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7189             :   { 447 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
    7190             :   { 447 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
    7191             :   { 453 /* ldrd */, ARM::t2LDRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
    7192             :   { 453 /* ldrd */, ARM::LDRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
    7193             :   { 453 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
    7194             :   { 453 /* ldrd */, ARM::t2LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2__Imm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
    7195             :   { 453 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
    7196             :   { 453 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2__AM3Offset2_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
    7197             :   { 458 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
    7198             :   { 458 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7199             :   { 464 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7200             :   { 464 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7201             :   { 471 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
    7202             :   { 471 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7203             :   { 478 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7204             :   { 478 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7205             :   { 485 /* ldrh */, ARM::tLDRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
    7206             :   { 485 /* ldrh */, ARM::tLDRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
    7207             :   { 485 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
    7208             :   { 485 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
    7209             :   { 485 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
    7210             :   { 485 /* ldrh */, ARM::t2LDRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
    7211             :   { 485 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
    7212             :   { 485 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
    7213             :   { 485 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
    7214             :   { 485 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
    7215             :   { 485 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
    7216             :   { 485 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
    7217             :   { 485 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
    7218             :   { 485 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
    7219             :   { 485 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
    7220             :   { 485 /* ldrh */, ARM::t2LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
    7221             :   { 490 /* ldrht */, ARM::t2LDRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
    7222             :   { 490 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
    7223             :   { 490 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
    7224             :   { 496 /* ldrsb */, ARM::tLDRSB, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
    7225             :   { 496 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
    7226             :   { 496 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
    7227             :   { 496 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
    7228             :   { 496 /* ldrsb */, ARM::t2LDRSBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
    7229             :   { 496 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
    7230             :   { 496 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
    7231             :   { 496 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
    7232             :   { 496 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
    7233             :   { 496 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
    7234             :   { 496 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
    7235             :   { 496 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
    7236             :   { 496 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
    7237             :   { 496 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
    7238             :   { 496 /* ldrsb */, ARM::t2LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
    7239             :   { 502 /* ldrsbt */, ARM::t2LDRSBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
    7240             :   { 502 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
    7241             :   { 502 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
    7242             :   { 509 /* ldrsh */, ARM::tLDRSH, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
    7243             :   { 509 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
    7244             :   { 509 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
    7245             :   { 509 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
    7246             :   { 509 /* ldrsh */, ARM::t2LDRSHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
    7247             :   { 509 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
    7248             :   { 509 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
    7249             :   { 509 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
    7250             :   { 509 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
    7251             :   { 509 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
    7252             :   { 509 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
    7253             :   { 509 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
    7254             :   { 509 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
    7255             :   { 509 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
    7256             :   { 509 /* ldrsh */, ARM::t2LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
    7257             :   { 515 /* ldrsht */, ARM::t2LDRSHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
    7258             :   { 515 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
    7259             :   { 515 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
    7260             :   { 522 /* ldrt */, ARM::t2LDRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
    7261             :   { 522 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7262             :   { 522 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
    7263             :   { 522 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
    7264             :   { 527 /* lsl */, ARM::tLSLrr, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7265             :   { 527 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, },
    7266             :   { 527 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7267             :   { 527 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, },
    7268             :   { 527 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    7269             :   { 527 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
    7270             :   { 527 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7271             :   { 527 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, },
    7272             :   { 527 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, },
    7273             :   { 527 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7274             :   { 527 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
    7275             :   { 527 /* lsl */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK__35_0 }, },
    7276             :   { 527 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7277             :   { 527 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
    7278             :   { 527 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7279             :   { 527 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
    7280             :   { 527 /* lsl */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK__35_0 }, },
    7281             :   { 531 /* lsr */, ARM::tLSRrr, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7282             :   { 531 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
    7283             :   { 531 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7284             :   { 531 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
    7285             :   { 531 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    7286             :   { 531 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
    7287             :   { 531 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7288             :   { 531 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
    7289             :   { 531 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
    7290             :   { 531 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7291             :   { 531 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
    7292             :   { 531 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7293             :   { 531 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
    7294             :   { 531 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7295             :   { 531 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
    7296             :   { 535 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
    7297             :   { 535 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
    7298             :   { 535 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    7299             :   { 535 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    7300             :   { 539 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, Feature_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
    7301             :   { 539 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
    7302             :   { 539 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    7303             :   { 539 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    7304             :   { 544 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
    7305             :   { 544 /* mcrr */, ARM::t2MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
    7306             :   { 549 /* mcrr2 */, ARM::MCRR2, Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
    7307             :   { 549 /* mcrr2 */, ARM::t2MCRR2, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
    7308             :   { 555 /* mla */, ARM::t2MLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7309             :   { 555 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7310             :   { 555 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7311             :   { 559 /* mls */, ARM::t2MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7312             :   { 559 /* mls */, ARM::MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7313             :   { 563 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_PC, MCK_LR }, },
    7314             :   { 563 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, },
    7315             :   { 563 /* mov */, ARM::t2MOVsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    7316             :   { 563 /* mov */, ARM::t2MOVsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
    7317             :   { 563 /* mov */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    7318             :   { 563 /* mov */, ARM::t2MVNi, Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
    7319             :   { 563 /* mov */, ARM::tMOVr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7320             :   { 563 /* mov */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
    7321             :   { 563 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, },
    7322             :   { 563 /* mov */, ARM::tMOVi8, Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
    7323             :   { 563 /* mov */, ARM::MVNi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
    7324             :   { 563 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
    7325             :   { 563 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7326             :   { 563 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7327             :   { 563 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7328             :   { 563 /* mov */, ARM::t2MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
    7329             :   { 563 /* mov */, ARM::t2MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
    7330             :   { 563 /* mov */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
    7331             :   { 563 /* mov */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
    7332             :   { 563 /* mov */, ARM::t2MOVi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
    7333             :   { 563 /* mov */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
    7334             :   { 567 /* movs */, ARM::tMOVSr, Convert__Reg1_0__Reg1_1, Feature_IsThumb, { MCK_tGPR, MCK_tGPR }, },
    7335             :   { 567 /* movs */, ARM::tMOVi8, Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0, Feature_IsThumb, { MCK_tGPR, MCK_Imm0_255 }, },
    7336             :   { 567 /* movs */, ARM::t2MOVSsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    7337             :   { 567 /* movs */, ARM::t2MOVSsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
    7338             :   { 567 /* movs */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    7339             :   { 567 /* movs */, ARM::t2MOVr, Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    7340             :   { 567 /* movs */, ARM::t2MOVSsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
    7341             :   { 567 /* movs */, ARM::t2MOVSsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
    7342             :   { 567 /* movs */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
    7343             :   { 567 /* movs */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
    7344             :   { 572 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0__Imm0_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
    7345             :   { 572 /* movt */, ARM::MOVTi16, Convert__Reg1_1__Tie0__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_65535Expr }, },
    7346             :   { 577 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
    7347             :   { 577 /* movw */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
    7348             :   { 582 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
    7349             :   { 582 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
    7350             :   { 582 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    7351             :   { 582 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    7352             :   { 586 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, Feature_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
    7353             :   { 586 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
    7354             :   { 586 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    7355             :   { 586 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
    7356             :   { 591 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
    7357             :   { 591 /* mrrc */, ARM::t2MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
    7358             :   { 596 /* mrrc2 */, ARM::MRRC2, Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
    7359             :   { 596 /* mrrc2 */, ARM::t2MRRC2, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
    7360             :   { 602 /* mrs */, ARM::t2MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, Feature_IsThumb|Feature_HasVirtualization, { MCK_CondCode, MCK_rGPR, MCK_BankedReg }, },
    7361             :   { 602 /* mrs */, ARM::t2MRS_M, Convert__Reg1_1__MSRMask1_2__CondCode2_0, Feature_IsThumb|Feature_IsMClass, { MCK_CondCode, MCK_rGPR, MCK_MSRMask }, },
    7362             :   { 602 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, },
    7363             :   { 602 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, },
    7364             :   { 602 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, },
    7365             :   { 602 /* mrs */, ARM::MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode, MCK_GPRnopc, MCK_BankedReg }, },
    7366             :   { 602 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, },
    7367             :   { 602 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_CCR }, },
    7368             :   { 602 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, },
    7369             :   { 606 /* msr */, ARM::t2MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_rGPR }, },
    7370             :   { 606 /* msr */, ARM::MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_GPRnopc }, },
    7371             :   { 606 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
    7372             :   { 606 /* msr */, ARM::t2MSR_M, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_IsMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
    7373             :   { 606 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, },
    7374             :   { 606 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, },
    7375             :   { 610 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7376             :   { 610 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7377             :   { 610 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    7378             :   { 610 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7379             :   { 610 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
    7380             :   { 610 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7381             :   { 610 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7382             :   { 614 /* mvn */, ARM::tMVN, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7383             :   { 614 /* mvn */, ARM::t2MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7384             :   { 614 /* mvn */, ARM::MOVi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
    7385             :   { 614 /* mvn */, ARM::t2MVNs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    7386             :   { 614 /* mvn */, ARM::t2MVNi, Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    7387             :   { 614 /* mvn */, ARM::t2MOVi, Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
    7388             :   { 614 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7389             :   { 614 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7390             :   { 614 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7391             :   { 614 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    7392             :   { 614 /* mvn */, ARM::t2MVNr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7393             :   { 614 /* mvn */, ARM::t2MVNs, Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
    7394             :   { 614 /* mvn */, ARM::t2MVNi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
    7395             :   { 618 /* neg */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7396             :   { 618 /* neg */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7397             :   { 618 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7398             :   { 622 /* nop */, ARM::tMOVr, Convert__regR8__regR8__imm_95_14__imm_95_0, Feature_IsThumb, {  }, },
    7399             :   { 622 /* nop */, ARM::HINT, Convert__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, },
    7400             :   { 622 /* nop */, ARM::tHINT, Convert__imm_95_0__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, },
    7401             :   { 622 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, Feature_IsARM, { MCK_CondCode }, },
    7402             :   { 622 /* nop */, ARM::t2HINT, Convert__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
    7403             :   { 626 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7404             :   { 626 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    7405             :   { 626 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    7406             :   { 626 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
    7407             :   { 626 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7408             :   { 626 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    7409             :   { 626 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    7410             :   { 626 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
    7411             :   { 630 /* orr */, ARM::tORR, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7412             :   { 630 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7413             :   { 630 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    7414             :   { 630 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    7415             :   { 630 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
    7416             :   { 630 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7417             :   { 630 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7418             :   { 630 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7419             :   { 630 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    7420             :   { 630 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7421             :   { 630 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
    7422             :   { 630 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
    7423             :   { 630 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7424             :   { 630 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    7425             :   { 630 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    7426             :   { 630 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
    7427             :   { 630 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7428             :   { 630 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    7429             :   { 630 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    7430             :   { 630 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
    7431             :   { 630 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7432             :   { 630 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    7433             :   { 630 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    7434             :   { 634 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7435             :   { 634 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7436             :   { 634 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHLSLImm }, },
    7437             :   { 634 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHLSLImm }, },
    7438             :   { 640 /* pkhtb */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7439             :   { 640 /* pkhtb */, ARM::PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7440             :   { 640 /* pkhtb */, ARM::t2PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHASRImm }, },
    7441             :   { 640 /* pkhtb */, ARM::PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHASRImm }, },
    7442             :   { 646 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, Feature_IsARM, { MCK_MemImm12Offset }, },
    7443             :   { 646 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, Feature_IsARM, { MCK_MemRegOffset }, },
    7444             :   { 646 /* pld */, ARM::t2PLDpci, Convert__Imm1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm }, },
    7445             :   { 646 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemNegImm8Offset }, },
    7446             :   { 646 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemUImm12Offset }, },
    7447             :   { 646 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_T2MemRegOffset }, },
    7448             :   { 646 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemPCRelImm12 }, },
    7449             :   { 650 /* pldw */, ARM::PLDWi12, Convert__MemImm12Offset2_0, Feature_IsARM|Feature_HasV7|Feature_HasMP, { MCK_MemImm12Offset }, },
    7450             :   { 650 /* pldw */, ARM::PLDWrs, Convert__MemRegOffset3_0, Feature_IsARM|Feature_HasV7|Feature_HasMP, { MCK_MemRegOffset }, },
    7451             :   { 650 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_MemNegImm8Offset }, },
    7452             :   { 650 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_MemUImm12Offset }, },
    7453             :   { 650 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_T2MemRegOffset }, },
    7454             :   { 655 /* pli */, ARM::PLIi12, Convert__MemImm12Offset2_0, Feature_IsARM|Feature_HasV7, { MCK_MemImm12Offset }, },
    7455             :   { 655 /* pli */, ARM::PLIrs, Convert__MemRegOffset3_0, Feature_IsARM|Feature_HasV7, { MCK_MemRegOffset }, },
    7456             :   { 655 /* pli */, ARM::t2PLIpci, Convert__Imm1_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_Imm }, },
    7457             :   { 655 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemNegImm8Offset }, },
    7458             :   { 655 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemUImm12Offset }, },
    7459             :   { 655 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_T2MemRegOffset }, },
    7460             :   { 655 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemPCRelImm12 }, },
    7461             :   { 659 /* pop */, ARM::tPOP, Convert__CondCode2_0__RegList1_1, Feature_IsThumb, { MCK_CondCode, MCK_RegList }, },
    7462             :   { 659 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0__CondCode2_0__RegList1_1, Feature_IsThumb2, { MCK_CondCode, MCK_RegList }, },
    7463             :   { 659 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0__CondCode2_0__RegList1_1, Feature_IsARM, { MCK_CondCode, MCK_RegList }, },
    7464             :   { 659 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
    7465             :   { 663 /* push */, ARM::tPUSH, Convert__CondCode2_0__RegList1_1, Feature_IsThumb, { MCK_CondCode, MCK_RegList }, },
    7466             :   { 663 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0__CondCode2_0__RegList1_1, Feature_IsThumb2, { MCK_CondCode, MCK_RegList }, },
    7467             :   { 663 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0__CondCode2_0__RegList1_1, Feature_IsARM, { MCK_CondCode, MCK_RegList }, },
    7468             :   { 663 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
    7469             :   { 668 /* qadd */, ARM::t2QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7470             :   { 668 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7471             :   { 673 /* qadd16 */, ARM::t2QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7472             :   { 673 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7473             :   { 680 /* qadd8 */, ARM::t2QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7474             :   { 680 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7475             :   { 686 /* qasx */, ARM::t2QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7476             :   { 686 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7477             :   { 691 /* qdadd */, ARM::t2QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7478             :   { 691 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7479             :   { 697 /* qdsub */, ARM::t2QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7480             :   { 697 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7481             :   { 703 /* qsax */, ARM::t2QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7482             :   { 703 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7483             :   { 708 /* qsub */, ARM::t2QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7484             :   { 708 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7485             :   { 713 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7486             :   { 713 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7487             :   { 720 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7488             :   { 720 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7489             :   { 726 /* rbit */, ARM::t2RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7490             :   { 726 /* rbit */, ARM::RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7491             :   { 731 /* rev */, ARM::tREV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7492             :   { 731 /* rev */, ARM::t2REV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7493             :   { 731 /* rev */, ARM::REV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7494             :   { 731 /* rev */, ARM::t2REV, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7495             :   { 735 /* rev16 */, ARM::tREV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7496             :   { 735 /* rev16 */, ARM::t2REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7497             :   { 735 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7498             :   { 735 /* rev16 */, ARM::t2REV16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7499             :   { 741 /* revsh */, ARM::tREVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7500             :   { 741 /* revsh */, ARM::t2REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7501             :   { 741 /* revsh */, ARM::REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7502             :   { 741 /* revsh */, ARM::t2REVSH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7503             :   { 747 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, },
    7504             :   { 747 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
    7505             :   { 753 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, },
    7506             :   { 753 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
    7507             :   { 753 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
    7508             :   { 753 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
    7509             :   { 759 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, },
    7510             :   { 759 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
    7511             :   { 759 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
    7512             :   { 759 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
    7513             :   { 765 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, },
    7514             :   { 765 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
    7515             :   { 771 /* ror */, ARM::tROR, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7516             :   { 771 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7517             :   { 771 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm0_31 }, },
    7518             :   { 771 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    7519             :   { 771 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
    7520             :   { 771 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7521             :   { 771 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm0_31 }, },
    7522             :   { 771 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7523             :   { 771 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31 }, },
    7524             :   { 771 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7525             :   { 771 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
    7526             :   { 771 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7527             :   { 771 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm0_31 }, },
    7528             :   { 775 /* rrx */, ARM::t2RRX, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7529             :   { 775 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7530             :   { 779 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7531             :   { 779 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
    7532             :   { 779 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
    7533             :   { 779 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7534             :   { 779 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7535             :   { 779 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7536             :   { 779 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    7537             :   { 779 /* rsb */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK__35_0 }, },
    7538             :   { 779 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7539             :   { 779 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    7540             :   { 779 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    7541             :   { 779 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7542             :   { 779 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    7543             :   { 779 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    7544             :   { 779 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
    7545             :   { 779 /* rsb */, ARM::t2RSBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    7546             :   { 783 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7547             :   { 783 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7548             :   { 783 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7549             :   { 783 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    7550             :   { 783 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7551             :   { 783 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    7552             :   { 783 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    7553             :   { 783 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
    7554             :   { 787 /* sadd16 */, ARM::t2SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7555             :   { 787 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7556             :   { 794 /* sadd8 */, ARM::t2SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7557             :   { 794 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7558             :   { 800 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7559             :   { 800 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7560             :   { 805 /* sbc */, ARM::tSBC, Convert__Reg1_2__CCOut1_0__Tie0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7561             :   { 805 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
    7562             :   { 805 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7563             :   { 805 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7564             :   { 805 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
    7565             :   { 805 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7566             :   { 805 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7567             :   { 805 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    7568             :   { 805 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
    7569             :   { 805 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
    7570             :   { 805 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
    7571             :   { 805 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7572             :   { 805 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    7573             :   { 805 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
    7574             :   { 805 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    7575             :   { 805 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7576             :   { 805 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
    7577             :   { 809 /* sbfx */, ARM::t2SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
    7578             :   { 809 /* sbfx */, ARM::SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
    7579             :   { 814 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasDivideInThumb|Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7580             :   { 814 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7581             :   { 819 /* sel */, ARM::SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7582             :   { 819 /* sel */, ARM::t2SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7583             :   { 823 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, Feature_IsARM, { MCK_SetEndImm }, },
    7584             :   { 823 /* setend */, ARM::tSETEND, Convert__SetEndImm1_0, Feature_IsNotMClass, { MCK_SetEndImm }, },
    7585             :   { 830 /* setpan */, ARM::SETPAN, Convert__Imm0_11_0, Feature_IsARM|Feature_HasV8|Feature_HasV8_1a, { MCK_Imm0_1 }, },
    7586             :   { 830 /* setpan */, ARM::t2SETPAN, Convert__Imm0_11_0, Feature_IsThumb2|Feature_HasV8|Feature_HasV8_1a, { MCK_Imm0_1 }, },
    7587             :   { 837 /* sev */, ARM::HINT, Convert__imm_95_4__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, },
    7588             :   { 837 /* sev */, ARM::tHINT, Convert__imm_95_4__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, },
    7589             :   { 837 /* sev */, ARM::t2HINT, Convert__imm_95_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
    7590             :   { 841 /* sevl */, ARM::HINT, Convert__imm_95_5__CondCode2_0, Feature_IsARM|Feature_HasV8, { MCK_CondCode }, },
    7591             :   { 841 /* sevl */, ARM::tHINT, Convert__imm_95_5__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, },
    7592             :   { 841 /* sevl */, ARM::t2HINT, Convert__imm_95_5__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode, MCK__DOT_w }, },
    7593             :   { 846 /* sg */, ARM::t2SG, Convert__CondCode2_0, Feature_Has8MSecExt, { MCK_CondCode }, },
    7594             :   { 849 /* sha1c */, ARM::SHA1C, Convert__Reg1_1__Tie0__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    7595             :   { 855 /* sha1h */, ARM::SHA1H, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
    7596             :   { 861 /* sha1m */, ARM::SHA1M, Convert__Reg1_1__Tie0__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    7597             :   { 867 /* sha1p */, ARM::SHA1P, Convert__Reg1_1__Tie0__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    7598             :   { 873 /* sha1su0 */, ARM::SHA1SU0, Convert__Reg1_1__Tie0__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    7599             :   { 881 /* sha1su1 */, ARM::SHA1SU1, Convert__Reg1_1__Tie0__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
    7600             :   { 889 /* sha256h */, ARM::SHA256H, Convert__Reg1_1__Tie0__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    7601             :   { 897 /* sha256h2 */, ARM::SHA256H2, Convert__Reg1_1__Tie0__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    7602             :   { 906 /* sha256su0 */, ARM::SHA256SU0, Convert__Reg1_1__Tie0__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
    7603             :   { 916 /* sha256su1 */, ARM::SHA256SU1, Convert__Reg1_1__Tie0__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    7604             :   { 926 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7605             :   { 926 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7606             :   { 934 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7607             :   { 934 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7608             :   { 941 /* shasx */, ARM::t2SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7609             :   { 941 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7610             :   { 947 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7611             :   { 947 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7612             :   { 953 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7613             :   { 953 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7614             :   { 961 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7615             :   { 961 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7616             :   { 968 /* smc */, ARM::SMC, Convert__Imm0_151_1__CondCode2_0, Feature_IsARM|Feature_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
    7617             :   { 968 /* smc */, ARM::t2SMC, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb2|Feature_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
    7618             :   { 972 /* smlabb */, ARM::t2SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7619             :   { 972 /* smlabb */, ARM::SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7620             :   { 979 /* smlabt */, ARM::t2SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7621             :   { 979 /* smlabt */, ARM::SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7622             :   { 986 /* smlad */, ARM::t2SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7623             :   { 986 /* smlad */, ARM::SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7624             :   { 992 /* smladx */, ARM::t2SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7625             :   { 992 /* smladx */, ARM::SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7626             :   { 999 /* smlal */, ARM::t2SMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7627             :   { 999 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0__Tie1__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7628             :   { 999 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0__Tie1__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7629             :   { 1005 /* smlalbb */, ARM::t2SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7630             :   { 1005 /* smlalbb */, ARM::SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7631             :   { 1013 /* smlalbt */, ARM::t2SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7632             :   { 1013 /* smlalbt */, ARM::SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7633             :   { 1021 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7634             :   { 1021 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7635             :   { 1028 /* smlaldx */, ARM::t2SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7636             :   { 1028 /* smlaldx */, ARM::SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7637             :   { 1036 /* smlaltb */, ARM::t2SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7638             :   { 1036 /* smlaltb */, ARM::SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7639             :   { 1044 /* smlaltt */, ARM::t2SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7640             :   { 1044 /* smlaltt */, ARM::SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7641             :   { 1052 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7642             :   { 1052 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7643             :   { 1059 /* smlatt */, ARM::t2SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7644             :   { 1059 /* smlatt */, ARM::SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7645             :   { 1066 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7646             :   { 1066 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7647             :   { 1073 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7648             :   { 1073 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7649             :   { 1080 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7650             :   { 1080 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7651             :   { 1086 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7652             :   { 1086 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
    7653             :   { 1093 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7654             :   { 1093 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7655             :   { 1100 /* smlsldx */, ARM::t2SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7656             :   { 1100 /* smlsldx */, ARM::SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7657             :   { 1108 /* smmla */, ARM::t2SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7658             :   { 1108 /* smmla */, ARM::SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7659             :   { 1114 /* smmlar */, ARM::t2SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7660             :   { 1114 /* smmlar */, ARM::SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7661             :   { 1121 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7662             :   { 1121 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7663             :   { 1127 /* smmlsr */, ARM::t2SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7664             :   { 1127 /* smmlsr */, ARM::SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7665             :   { 1134 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7666             :   { 1134 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7667             :   { 1140 /* smmulr */, ARM::t2SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7668             :   { 1140 /* smmulr */, ARM::SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7669             :   { 1147 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7670             :   { 1147 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7671             :   { 1153 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7672             :   { 1153 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7673             :   { 1160 /* smulbb */, ARM::t2SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7674             :   { 1160 /* smulbb */, ARM::SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7675             :   { 1167 /* smulbt */, ARM::t2SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7676             :   { 1167 /* smulbt */, ARM::SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7677             :   { 1174 /* smull */, ARM::t2SMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7678             :   { 1174 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7679             :   { 1174 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7680             :   { 1180 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7681             :   { 1180 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7682             :   { 1187 /* smultt */, ARM::t2SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7683             :   { 1187 /* smultt */, ARM::SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7684             :   { 1194 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7685             :   { 1194 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7686             :   { 1201 /* smulwt */, ARM::t2SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7687             :   { 1201 /* smulwt */, ARM::SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7688             :   { 1208 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7689             :   { 1208 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7690             :   { 1214 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7691             :   { 1214 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7692             :   { 1221 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
    7693             :   { 1221 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
    7694             :   { 1221 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
    7695             :   { 1221 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
    7696             :   { 1227 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
    7697             :   { 1227 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
    7698             :   { 1227 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
    7699             :   { 1227 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
    7700             :   { 1227 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
    7701             :   { 1227 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
    7702             :   { 1227 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
    7703             :   { 1227 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
    7704             :   { 1233 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
    7705             :   { 1233 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
    7706             :   { 1233 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
    7707             :   { 1233 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
    7708             :   { 1233 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
    7709             :   { 1233 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
    7710             :   { 1233 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
    7711             :   { 1233 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
    7712             :   { 1239 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
    7713             :   { 1239 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
    7714             :   { 1239 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
    7715             :   { 1239 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
    7716             :   { 1245 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR }, },
    7717             :   { 1245 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, },
    7718             :   { 1245 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR, MCK_ShifterImm }, },
    7719             :   { 1245 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc, MCK_ShifterImm }, },
    7720             :   { 1250 /* ssat16 */, ARM::t2SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm1_16, MCK_rGPR }, },
    7721             :   { 1250 /* ssat16 */, ARM::SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_16, MCK_GPRnopc }, },
    7722             :   { 1257 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7723             :   { 1257 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7724             :   { 1262 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7725             :   { 1262 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7726             :   { 1269 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7727             :   { 1269 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7728             :   { 1275 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7729             :   { 1275 /* stc */, ARM::t2STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7730             :   { 1275 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7731             :   { 1275 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7732             :   { 1275 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7733             :   { 1275 /* stc */, ARM::t2STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7734             :   { 1275 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7735             :   { 1275 /* stc */, ARM::t2STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7736             :   { 1279 /* stc2 */, ARM::STC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7737             :   { 1279 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7738             :   { 1279 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7739             :   { 1279 /* stc2 */, ARM::STC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7740             :   { 1279 /* stc2 */, ARM::STC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7741             :   { 1279 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7742             :   { 1279 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7743             :   { 1279 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7744             :   { 1284 /* stc2l */, ARM::STC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7745             :   { 1284 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7746             :   { 1284 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7747             :   { 1284 /* stc2l */, ARM::STC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7748             :   { 1284 /* stc2l */, ARM::STC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7749             :   { 1284 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7750             :   { 1284 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7751             :   { 1284 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7752             :   { 1290 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7753             :   { 1290 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
    7754             :   { 1290 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7755             :   { 1290 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
    7756             :   { 1290 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7757             :   { 1290 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
    7758             :   { 1290 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7759             :   { 1290 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
    7760             :   { 1295 /* stl */, ARM::t2STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7761             :   { 1295 /* stl */, ARM::STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7762             :   { 1299 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7763             :   { 1299 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7764             :   { 1304 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7765             :   { 1304 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
    7766             :   { 1310 /* stlexb */, ARM::t2STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7767             :   { 1310 /* stlexb */, ARM::STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
    7768             :   { 1317 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
    7769             :   { 1317 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7770             :   { 1324 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7771             :   { 1324 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
    7772             :   { 1331 /* stlh */, ARM::t2STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
    7773             :   { 1331 /* stlh */, ARM::STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7774             :   { 1336 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7775             :   { 1336 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7776             :   { 1336 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7777             :   { 1336 /* stm */, ARM::t2STMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
    7778             :   { 1336 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
    7779             :   { 1336 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7780             :   { 1336 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7781             :   { 1336 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
    7782             :   { 1336 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7783             :   { 1336 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
    7784             :   { 1340 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7785             :   { 1340 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7786             :   { 1340 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
    7787             :   { 1340 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
    7788             :   { 1346 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7789             :   { 1346 /* stmdb */, ARM::t2STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7790             :   { 1346 /* stmdb */, ARM::t2STMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
    7791             :   { 1346 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7792             :   { 1346 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7793             :   { 1346 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
    7794             :   { 1346 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7795             :   { 1346 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
    7796             :   { 1352 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
    7797             :   { 1352 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
    7798             :   { 1352 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
    7799             :   { 1352 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
    7800             :   { 1358 /* str */, ARM::tSTRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
    7801             :   { 1358 /* str */, ARM::tSTRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
    7802             :   { 1358 /* str */, ARM::tSTRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
    7803             :   { 1358 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
    7804             :   { 1358 /* str */, ARM::t2STRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
    7805             :   { 1358 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
    7806             :   { 1358 /* str */, ARM::t2STRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
    7807             :   { 1358 /* str */, ARM::t2STRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
    7808             :   { 1358 /* str */, ARM::t2STRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
    7809             :   { 1358 /* str */, ARM::t2STRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
    7810             :   { 1358 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
    7811             :   { 1358 /* str */, ARM::t2STR_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_Imm }, },
    7812             :   { 1358 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
    7813             :   { 1358 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
    7814             :   { 1358 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
    7815             :   { 1358 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
    7816             :   { 1362 /* strb */, ARM::tSTRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
    7817             :   { 1362 /* strb */, ARM::tSTRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
    7818             :   { 1362 /* strb */, ARM::t2STRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
    7819             :   { 1362 /* strb */, ARM::t2STRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
    7820             :   { 1362 /* strb */, ARM::t2STRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
    7821             :   { 1362 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
    7822             :   { 1362 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
    7823             :   { 1362 /* strb */, ARM::t2STRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
    7824             :   { 1362 /* strb */, ARM::t2STRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
    7825             :   { 1362 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
    7826             :   { 1362 /* strb */, ARM::t2STRB_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
    7827             :   { 1362 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
    7828             :   { 1362 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
    7829             :   { 1362 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
    7830             :   { 1362 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
    7831             :   { 1367 /* strbt */, ARM::t2STRBT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, },
    7832             :   { 1367 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7833             :   { 1367 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
    7834             :   { 1367 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
    7835             :   { 1373 /* strd */, ARM::t2STRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
    7836             :   { 1373 /* strd */, ARM::STRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
    7837             :   { 1373 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
    7838             :   { 1373 /* strd */, ARM::t2STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0__Imm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
    7839             :   { 1373 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
    7840             :   { 1373 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0__AM3Offset2_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
    7841             :   { 1378 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
    7842             :   { 1378 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
    7843             :   { 1384 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7844             :   { 1384 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
    7845             :   { 1391 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
    7846             :   { 1391 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7847             :   { 1398 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
    7848             :   { 1398 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
    7849             :   { 1405 /* strh */, ARM::tSTRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
    7850             :   { 1405 /* strh */, ARM::tSTRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
    7851             :   { 1405 /* strh */, ARM::t2STRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
    7852             :   { 1405 /* strh */, ARM::t2STRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
    7853             :   { 1405 /* strh */, ARM::t2STRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
    7854             :   { 1405 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
    7855             :   { 1405 /* strh */, ARM::t2STRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
    7856             :   { 1405 /* strh */, ARM::t2STRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
    7857             :   { 1405 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
    7858             :   { 1405 /* strh */, ARM::t2STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
    7859             :   { 1405 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
    7860             :   { 1405 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
    7861             :   { 1410 /* strht */, ARM::t2STRHT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, },
    7862             :   { 1410 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
    7863             :   { 1410 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, },
    7864             :   { 1416 /* strt */, ARM::t2STRT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, },
    7865             :   { 1416 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
    7866             :   { 1416 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
    7867             :   { 1416 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
    7868             :   { 1421 /* sub */, ARM::tSUBspi, Convert__Reg1_1__Tie0__Imm0_508s41_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
    7869             :   { 1421 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095 }, },
    7870             :   { 1421 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7871             :   { 1421 /* sub */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
    7872             :   { 1421 /* sub */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0__ThumbModImmNeg8_2551_3__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
    7873             :   { 1421 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
    7874             :   { 1421 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
    7875             :   { 1421 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
    7876             :   { 1421 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7877             :   { 1421 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7878             :   { 1421 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
    7879             :   { 1421 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7880             :   { 1421 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
    7881             :   { 1421 /* sub */, ARM::tSUBspi, Convert__regSP__Tie0__Imm0_508s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
    7882             :   { 1421 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
    7883             :   { 1421 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
    7884             :   { 1421 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
    7885             :   { 1421 /* sub */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
    7886             :   { 1421 /* sub */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
    7887             :   { 1421 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
    7888             :   { 1421 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
    7889             :   { 1421 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
    7890             :   { 1421 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7891             :   { 1421 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
    7892             :   { 1421 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
    7893             :   { 1421 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
    7894             :   { 1421 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
    7895             :   { 1421 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
    7896             :   { 1421 /* sub */, ARM::t2SUBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
    7897             :   { 1421 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
    7898             :   { 1421 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
    7899             :   { 1425 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_LR, MCK_Imm0_255 }, },
    7900             :   { 1430 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
    7901             :   { 1430 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, },
    7902             :   { 1435 /* svc */, ARM::tSVC, Convert__Imm0_2551_1__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_Imm0_255 }, },
    7903             :   { 1435 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_Imm24bit }, },
    7904             :   { 1439 /* swp */, ARM::SWP, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
    7905             :   { 1443 /* swpb */, ARM::SWPB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
    7906             :   { 1448 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7907             :   { 1448 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
    7908             :   { 1448 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7909             :   { 1448 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
    7910             :   { 1454 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7911             :   { 1454 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
    7912             :   { 1454 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7913             :   { 1454 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
    7914             :   { 1462 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7915             :   { 1462 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
    7916             :   { 1462 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7917             :   { 1462 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
    7918             :   { 1468 /* sxtb */, ARM::tSXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7919             :   { 1468 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7920             :   { 1468 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    7921             :   { 1468 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7922             :   { 1468 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7923             :   { 1468 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
    7924             :   { 1468 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7925             :   { 1473 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7926             :   { 1473 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    7927             :   { 1473 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7928             :   { 1473 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7929             :   { 1473 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
    7930             :   { 1480 /* sxth */, ARM::tSXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7931             :   { 1480 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    7932             :   { 1480 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    7933             :   { 1480 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    7934             :   { 1480 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7935             :   { 1480 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
    7936             :   { 1480 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    7937             :   { 1485 /* tbb */, ARM::t2TBB, Convert__MemTBB2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemTBB }, },
    7938             :   { 1489 /* tbh */, ARM::t2TBH, Convert__MemTBH2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemTBH }, },
    7939             :   { 1493 /* teq */, ARM::t2TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
    7940             :   { 1493 /* teq */, ARM::t2TEQrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
    7941             :   { 1493 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
    7942             :   { 1493 /* teq */, ARM::t2TEQri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
    7943             :   { 1493 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7944             :   { 1493 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7945             :   { 1493 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7946             :   { 1493 /* teq */, ARM::t2TEQrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
    7947             :   { 1493 /* teq */, ARM::t2TEQrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
    7948             :   { 1493 /* teq */, ARM::t2TEQri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
    7949             :   { 1497 /* trap */, ARM::TRAPNaCl, Convert_NoOperands, Feature_IsARM|Feature_UseNaClTrap, {  }, },
    7950             :   { 1497 /* trap */, ARM::TRAP, Convert_NoOperands, Feature_IsARM, {  }, },
    7951             :   { 1497 /* trap */, ARM::tTRAP, Convert_NoOperands, Feature_IsThumb, {  }, },
    7952             :   { 1502 /* tst */, ARM::tTST, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    7953             :   { 1502 /* tst */, ARM::t2TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
    7954             :   { 1502 /* tst */, ARM::t2TSTrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
    7955             :   { 1502 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
    7956             :   { 1502 /* tst */, ARM::t2TSTri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
    7957             :   { 1502 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
    7958             :   { 1502 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
    7959             :   { 1502 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
    7960             :   { 1502 /* tst */, ARM::t2TSTrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
    7961             :   { 1502 /* tst */, ARM::t2TSTrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
    7962             :   { 1502 /* tst */, ARM::t2TSTri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
    7963             :   { 1506 /* tt */, ARM::t2TT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
    7964             :   { 1509 /* tta */, ARM::t2TTA, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
    7965             :   { 1513 /* ttat */, ARM::t2TTAT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
    7966             :   { 1518 /* ttt */, ARM::t2TTT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
    7967             :   { 1522 /* uadd16 */, ARM::t2UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7968             :   { 1522 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7969             :   { 1529 /* uadd8 */, ARM::t2UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7970             :   { 1529 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7971             :   { 1535 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7972             :   { 1535 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7973             :   { 1540 /* ubfx */, ARM::t2UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
    7974             :   { 1540 /* ubfx */, ARM::UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
    7975             :   { 1545 /* udf */, ARM::tUDF, Convert__Imm0_2551_0, Feature_IsThumb, { MCK_Imm0_255 }, },
    7976             :   { 1545 /* udf */, ARM::UDF, Convert__Imm0_655351_0, Feature_IsARM, { MCK_Imm0_65535 }, },
    7977             :   { 1545 /* udf */, ARM::t2UDF, Convert__Imm0_655351_1, Feature_IsThumb2, { MCK__DOT_w, MCK_Imm0_65535 }, },
    7978             :   { 1549 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasDivideInThumb|Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7979             :   { 1549 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7980             :   { 1554 /* uhadd16 */, ARM::t2UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7981             :   { 1554 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7982             :   { 1562 /* uhadd8 */, ARM::t2UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7983             :   { 1562 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7984             :   { 1569 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7985             :   { 1569 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7986             :   { 1575 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7987             :   { 1575 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7988             :   { 1581 /* uhsub16 */, ARM::t2UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7989             :   { 1581 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7990             :   { 1589 /* uhsub8 */, ARM::t2UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7991             :   { 1589 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    7992             :   { 1596 /* umaal */, ARM::t2UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7993             :   { 1596 /* umaal */, ARM::UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7994             :   { 1602 /* umlal */, ARM::t2UMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0__Tie1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7995             :   { 1602 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0__Tie1__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7996             :   { 1602 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0__Tie1__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7997             :   { 1608 /* umull */, ARM::t2UMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    7998             :   { 1608 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    7999             :   { 1608 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    8000             :   { 1614 /* uqadd16 */, ARM::t2UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8001             :   { 1614 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8002             :   { 1622 /* uqadd8 */, ARM::t2UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8003             :   { 1622 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8004             :   { 1629 /* uqasx */, ARM::t2UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8005             :   { 1629 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8006             :   { 1635 /* uqsax */, ARM::t2UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8007             :   { 1635 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8008             :   { 1641 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8009             :   { 1641 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8010             :   { 1649 /* uqsub8 */, ARM::t2UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8011             :   { 1649 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8012             :   { 1656 /* usad8 */, ARM::t2USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8013             :   { 1656 /* usad8 */, ARM::USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    8014             :   { 1662 /* usada8 */, ARM::t2USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8015             :   { 1662 /* usada8 */, ARM::USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
    8016             :   { 1669 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR }, },
    8017             :   { 1669 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, },
    8018             :   { 1669 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR, MCK_ShifterImm }, },
    8019             :   { 1669 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc, MCK_ShifterImm }, },
    8020             :   { 1674 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm0_15, MCK_rGPR }, },
    8021             :   { 1674 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_15, MCK_GPRnopc }, },
    8022             :   { 1681 /* usax */, ARM::t2USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8023             :   { 1681 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8024             :   { 1686 /* usub16 */, ARM::t2USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8025             :   { 1686 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8026             :   { 1693 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8027             :   { 1693 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
    8028             :   { 1699 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8029             :   { 1699 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
    8030             :   { 1699 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8031             :   { 1699 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
    8032             :   { 1705 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8033             :   { 1705 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
    8034             :   { 1705 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8035             :   { 1705 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
    8036             :   { 1713 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
    8037             :   { 1713 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
    8038             :   { 1713 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8039             :   { 1713 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
    8040             :   { 1719 /* uxtb */, ARM::tUXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    8041             :   { 1719 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    8042             :   { 1719 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    8043             :   { 1719 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    8044             :   { 1719 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8045             :   { 1719 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
    8046             :   { 1719 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8047             :   { 1724 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    8048             :   { 1724 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    8049             :   { 1724 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8050             :   { 1724 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8051             :   { 1724 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
    8052             :   { 1731 /* uxth */, ARM::tUXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
    8053             :   { 1731 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
    8054             :   { 1731 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
    8055             :   { 1731 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
    8056             :   { 1731 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8057             :   { 1731 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
    8058             :   { 1731 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
    8059             :   { 1736 /* vaba */, ARM::VABAsv8i16, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8060             :   { 1736 /* vaba */, ARM::VABAsv4i16, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8061             :   { 1736 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8062             :   { 1736 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8063             :   { 1736 /* vaba */, ARM::VABAsv16i8, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8064             :   { 1736 /* vaba */, ARM::VABAsv8i8, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8065             :   { 1736 /* vaba */, ARM::VABAuv8i16, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8066             :   { 1736 /* vaba */, ARM::VABAuv4i16, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8067             :   { 1736 /* vaba */, ARM::VABAuv4i32, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8068             :   { 1736 /* vaba */, ARM::VABAuv2i32, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8069             :   { 1736 /* vaba */, ARM::VABAuv16i8, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8070             :   { 1736 /* vaba */, ARM::VABAuv8i8, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8071             :   { 1741 /* vabal */, ARM::VABALsv4i32, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8072             :   { 1741 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8073             :   { 1741 /* vabal */, ARM::VABALsv8i16, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8074             :   { 1741 /* vabal */, ARM::VABALuv4i32, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8075             :   { 1741 /* vabal */, ARM::VABALuv2i64, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8076             :   { 1741 /* vabal */, ARM::VABALuv8i16, Convert__Reg1_2__Tie0__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8077             :   { 1747 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
    8078             :   { 1747 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
    8079             :   { 1747 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
    8080             :   { 1747 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
    8081             :   { 1747 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
    8082             :   { 1747 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
    8083             :   { 1747 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
    8084             :   { 1747 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
    8085             :   { 1747 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
    8086             :   { 1747 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
    8087             :   { 1747 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
    8088             :   { 1747 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
    8089             :   { 1747 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
    8090             :   { 1747 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
    8091             :   { 1747 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
    8092             :   { 1747 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
    8093             :   { 1747 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8094             :   { 1747 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8095             :   { 1747 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8096             :   { 1747 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8097             :   { 1747 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8098             :   { 1747 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8099             :   { 1747 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8100             :   { 1747 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8101             :   { 1747 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8102             :   { 1747 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8103             :   { 1747 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8104             :   { 1747 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8105             :   { 1747 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8106             :   { 1747 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8107             :   { 1747 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8108             :   { 1747 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8109             :   { 1752 /* vabdl */, ARM::VABDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8110             :   { 1752 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8111             :   { 1752 /* vabdl */, ARM::VABDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8112             :   { 1752 /* vabdl */, ARM::VABDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8113             :   { 1752 /* vabdl */, ARM::VABDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8114             :   { 1752 /* vabdl */, ARM::VABDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8115             :   { 1758 /* vabs */, ARM::VABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
    8116             :   { 1758 /* vabs */, ARM::VABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
    8117             :   { 1758 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
    8118             :   { 1758 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
    8119             :   { 1758 /* vabs */, ARM::VABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
    8120             :   { 1758 /* vabs */, ARM::VABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
    8121             :   { 1758 /* vabs */, ARM::VABSfq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
    8122             :   { 1758 /* vabs */, ARM::VABSfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
    8123             :   { 1758 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_SPR, MCK_SPR }, },
    8124             :   { 1758 /* vabs */, ARM::VABSD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
    8125             :   { 1758 /* vabs */, ARM::VABShq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
    8126             :   { 1758 /* vabs */, ARM::VABShd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
    8127             :   { 1758 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_SPR, MCK_SPR }, },
    8128             :   { 1763 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
    8129             :   { 1763 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
    8130             :   { 1763 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
    8131             :   { 1763 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
    8132             :   { 1763 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8133             :   { 1763 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8134             :   { 1763 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8135             :   { 1763 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8136             :   { 1769 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
    8137             :   { 1769 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
    8138             :   { 1769 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
    8139             :   { 1769 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
    8140             :   { 1769 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8141             :   { 1769 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8142             :   { 1769 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8143             :   { 1769 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8144             :   { 1775 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
    8145             :   { 1775 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
    8146             :   { 1775 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
    8147             :   { 1775 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
    8148             :   { 1775 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8149             :   { 1775 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8150             :   { 1775 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8151             :   { 1775 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8152             :   { 1781 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
    8153             :   { 1781 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
    8154             :   { 1781 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
    8155             :   { 1781 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
    8156             :   { 1781 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8157             :   { 1781 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8158             :   { 1781 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8159             :   { 1781 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8160             :   { 1787 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
    8161             :   { 1787 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
    8162             :   { 1787 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_SPR, MCK_SPR }, },
    8163             :   { 1787 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
    8164             :   { 1787 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
    8165             :   { 1787 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
    8166             :   { 1787 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
    8167             :   { 1787 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
    8168             :   { 1787 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
    8169             :   { 1787 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
    8170             :   { 1787 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
    8171             :   { 1787 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
    8172             :   { 1787 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
    8173             :   { 1787 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
    8174             :   { 1787 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_SPR, MCK_SPR }, },
    8175             :   { 1787 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8176             :   { 1787 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8177             :   { 1787 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_SPR, MCK_SPR, MCK_SPR }, },
    8178             :   { 1787 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8179             :   { 1787 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8180             :   { 1787 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8181             :   { 1787 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8182             :   { 1787 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8183             :   { 1787 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8184             :   { 1787 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8185             :   { 1787 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8186             :   { 1787 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8187             :   { 1787 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
    8188             :   { 1787 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
    8189             :   { 1787 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_SPR, MCK_SPR, MCK_SPR }, },
    8190             :   { 1792 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
    8191             :   { 1792 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
    8192             :   { 1792 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
    8193             :   { 1799 /* vaddl */, ARM::VADDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8194             :   { 1799 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8195             :   { 1799 /* vaddl */, ARM::VADDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8196             :   { 1799 /* vaddl */, ARM::VADDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8197             :   { 1799 /* vaddl */, ARM::VADDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8198             :   { 1799 /* vaddl */, ARM::VADDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
    8199             :   { 1805 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
    8200             :   { 1805 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
    8201             :   { 1805 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
    8202             :   { 1805 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
    8203             :   { 1805 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
    8204             :   { 1805 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
    8205             :   { 1805 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
    8206             :   { 1805 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
    8207             :   { 1805 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
    8208             :   { 1805 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
    8209             :   { 1805 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
    8210             :   { 1805 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
    8211             :   { 1811 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
    8212             :   { 1811 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
    8213             :   { 1811 /* vand */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splatNot }, },
    8214             :   { 1811 /* vand */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splatNot }, },
    8215             :   { 1811 /* vand */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splatNot }, },
    8216             :   { 1811 /* vand */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0__CondCode2_0, Fea