LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/ARM - ARMGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 276 2667 10.3 %
Date: 2017-09-14 15:23:50 Functions: 53 297 17.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the ARM target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_mod_imm(int64_t Imm) {
      12             : 
      13         506 :     return ARM_AM::getSOImmVal(Imm) != -1;
      14             :   
      15             : }
      16             : static bool Predicate_imm0_65535(int64_t Imm) {
      17             : 
      18             :   return Imm >= 0 && Imm < 65536;
      19             : 
      20             : }
      21             : static bool Predicate_imm0_7(int64_t Imm) {
      22             : 
      23             :   return Imm >= 0 && Imm < 8;
      24             : 
      25             : }
      26             : static bool Predicate_imm8_255(int64_t Imm) {
      27             : 
      28         464 :   return Imm >= 8 && Imm < 256;
      29             : 
      30             : }
      31             : static bool Predicate_imm0_255(int64_t Imm) {
      32             :  return Imm >= 0 && Imm < 256; 
      33             : }
      34             : static bool Predicate_t2_so_imm(int64_t Imm) {
      35             : 
      36         464 :     return ARM_AM::getT2SOImmVal(Imm) != -1;
      37             :   
      38             : }
      39             : static bool Predicate_imm0_4095(int64_t Imm) {
      40             : 
      41             :   return Imm >= 0 && Imm < 4096;
      42             : 
      43             : }
      44             : static bool Predicate_imm1_31(int64_t Imm) {
      45          47 :  return Imm > 0 && Imm < 32; 
      46             : }
      47             : static bool Predicate_imm0_31(int64_t Imm) {
      48             : 
      49             :   return Imm >= 0 && Imm < 32;
      50             : 
      51             : }
      52             : static bool Predicate_shr_imm8(int64_t Imm) {
      53          41 :  return Imm > 0 && Imm <= 8; 
      54             : }
      55             : static bool Predicate_shr_imm16(int64_t Imm) {
      56          41 :  return Imm > 0 && Imm <= 16; 
      57             : }
      58             : static bool Predicate_shr_imm32(int64_t Imm) {
      59          41 :  return Imm > 0 && Imm <= 32; 
      60             : }
      61             : static bool Predicate_VectorIndex32(int64_t Imm) {
      62             : 
      63             :   return ((uint64_t)Imm) < 2;
      64             : 
      65             : }
      66             : static bool Predicate_t2_so_imm_neg(int64_t Imm) {
      67             : 
      68             :   return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
      69             : 
      70             : }
      71             : 
      72             : 
      73             : // FastEmit functions for ARMISD::CALL.
      74             : 
      75           0 : unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      76           0 :   if (RetVT.SimpleTy != MVT::isVoid)
      77             :     return 0;
      78           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
      79           0 :     return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill);
      80             :   }
      81             :   return 0;
      82             : }
      83             : 
      84             : unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
      85           0 :   switch (VT.SimpleTy) {
      86           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill);
      87             :   default: return 0;
      88             :   }
      89             : }
      90             : 
      91             : // FastEmit functions for ARMISD::CALL_NOLINK.
      92             : 
      93           0 : unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      94           0 :   if (RetVT.SimpleTy != MVT::isVoid)
      95             :     return 0;
      96           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
      97           0 :     return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
      98             :   }
      99           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
     100           0 :     return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
     101             :   }
     102           0 :   if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
     103           0 :     return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
     104             :   }
     105             :   return 0;
     106             : }
     107             : 
     108             : unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     109           0 :   switch (VT.SimpleTy) {
     110           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill);
     111             :   default: return 0;
     112             :   }
     113             : }
     114             : 
     115             : // FastEmit functions for ARMISD::CALL_PRED.
     116             : 
     117           0 : unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     118           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     119             :     return 0;
     120           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
     121           0 :     return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill);
     122             :   }
     123             :   return 0;
     124             : }
     125             : 
     126             : unsigned fastEmit_ARMISD_CALL_PRED_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     127           0 :   switch (VT.SimpleTy) {
     128           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_PRED_MVT_i32_r(RetVT, Op0, Op0IsKill);
     129             :   default: return 0;
     130             :   }
     131             : }
     132             : 
     133             : // FastEmit functions for ARMISD::RRX.
     134             : 
     135           0 : unsigned fastEmit_ARMISD_RRX_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     136           0 :   if (RetVT.SimpleTy != MVT::i32)
     137             :     return 0;
     138           0 :   if ((Subtarget->isThumb2())) {
     139           0 :     return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill);
     140             :   }
     141           0 :   if ((!Subtarget->isThumb())) {
     142           0 :     return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill);
     143             :   }
     144             :   return 0;
     145             : }
     146             : 
     147             : unsigned fastEmit_ARMISD_RRX_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     148           0 :   switch (VT.SimpleTy) {
     149           0 :   case MVT::i32: return fastEmit_ARMISD_RRX_MVT_i32_r(RetVT, Op0, Op0IsKill);
     150             :   default: return 0;
     151             :   }
     152             : }
     153             : 
     154             : // FastEmit functions for ARMISD::SRA_FLAG.
     155             : 
     156           0 : unsigned fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     157           0 :   if (RetVT.SimpleTy != MVT::i32)
     158             :     return 0;
     159           0 :   if ((Subtarget->isThumb2())) {
     160           0 :     return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
     161             :   }
     162           0 :   if ((!Subtarget->isThumb())) {
     163           0 :     return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
     164             :   }
     165             :   return 0;
     166             : }
     167             : 
     168             : unsigned fastEmit_ARMISD_SRA_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     169           0 :   switch (VT.SimpleTy) {
     170           0 :   case MVT::i32: return fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
     171             :   default: return 0;
     172             :   }
     173             : }
     174             : 
     175             : // FastEmit functions for ARMISD::SRL_FLAG.
     176             : 
     177           0 : unsigned fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     178           0 :   if (RetVT.SimpleTy != MVT::i32)
     179             :     return 0;
     180           0 :   if ((Subtarget->isThumb2())) {
     181           0 :     return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
     182             :   }
     183           0 :   if ((!Subtarget->isThumb())) {
     184           0 :     return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
     185             :   }
     186             :   return 0;
     187             : }
     188             : 
     189             : unsigned fastEmit_ARMISD_SRL_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     190           0 :   switch (VT.SimpleTy) {
     191           0 :   case MVT::i32: return fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
     192             :   default: return 0;
     193             :   }
     194             : }
     195             : 
     196             : // FastEmit functions for ARMISD::TC_RETURN.
     197             : 
     198             : unsigned fastEmit_ARMISD_TC_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     199           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     200             :     return 0;
     201           0 :   return fastEmitInst_r(ARM::TCRETURNri, &ARM::tcGPRRegClass, Op0, Op0IsKill);
     202             : }
     203             : 
     204             : unsigned fastEmit_ARMISD_TC_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     205           0 :   switch (VT.SimpleTy) {
     206           0 :   case MVT::i32: return fastEmit_ARMISD_TC_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill);
     207             :   default: return 0;
     208             :   }
     209             : }
     210             : 
     211             : // FastEmit functions for ARMISD::VCEQZ.
     212             : 
     213             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     214           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     215             :     return 0;
     216           0 :   if ((Subtarget->hasNEON())) {
     217           0 :     return fastEmitInst_r(ARM::VCEQzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     218             :   }
     219             :   return 0;
     220             : }
     221             : 
     222             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     223           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     224             :     return 0;
     225           0 :   if ((Subtarget->hasNEON())) {
     226           0 :     return fastEmitInst_r(ARM::VCEQzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     227             :   }
     228             :   return 0;
     229             : }
     230             : 
     231             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     232           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     233             :     return 0;
     234           0 :   if ((Subtarget->hasNEON())) {
     235           0 :     return fastEmitInst_r(ARM::VCEQzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     236             :   }
     237             :   return 0;
     238             : }
     239             : 
     240             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     241           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     242             :     return 0;
     243           0 :   if ((Subtarget->hasNEON())) {
     244           0 :     return fastEmitInst_r(ARM::VCEQzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     245             :   }
     246             :   return 0;
     247             : }
     248             : 
     249             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     250           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     251             :     return 0;
     252           0 :   if ((Subtarget->hasNEON())) {
     253           0 :     return fastEmitInst_r(ARM::VCEQzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     254             :   }
     255             :   return 0;
     256             : }
     257             : 
     258             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     259           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     260             :     return 0;
     261           0 :   if ((Subtarget->hasNEON())) {
     262           0 :     return fastEmitInst_r(ARM::VCEQzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     263             :   }
     264             :   return 0;
     265             : }
     266             : 
     267           0 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     268           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     269             :     return 0;
     270           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     271           0 :     return fastEmitInst_r(ARM::VCEQzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     272             :   }
     273             :   return 0;
     274             : }
     275             : 
     276           0 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     277           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     278             :     return 0;
     279           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     280           0 :     return fastEmitInst_r(ARM::VCEQzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     281             :   }
     282             :   return 0;
     283             : }
     284             : 
     285             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     286           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     287             :     return 0;
     288           0 :   if ((Subtarget->hasNEON())) {
     289           0 :     return fastEmitInst_r(ARM::VCEQzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     290             :   }
     291             :   return 0;
     292             : }
     293             : 
     294             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     295           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     296             :     return 0;
     297           0 :   if ((Subtarget->hasNEON())) {
     298           0 :     return fastEmitInst_r(ARM::VCEQzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     299             :   }
     300             :   return 0;
     301             : }
     302             : 
     303           0 : unsigned fastEmit_ARMISD_VCEQZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     304           0 :   switch (VT.SimpleTy) {
     305           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     306           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     307           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     308           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     309           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     310           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     311           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     312           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     313           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     314           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     315             :   default: return 0;
     316             :   }
     317             : }
     318             : 
     319             : // FastEmit functions for ARMISD::VCGEZ.
     320             : 
     321             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     322           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     323             :     return 0;
     324           0 :   if ((Subtarget->hasNEON())) {
     325           0 :     return fastEmitInst_r(ARM::VCGEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     326             :   }
     327             :   return 0;
     328             : }
     329             : 
     330             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     331           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     332             :     return 0;
     333           0 :   if ((Subtarget->hasNEON())) {
     334           0 :     return fastEmitInst_r(ARM::VCGEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     335             :   }
     336             :   return 0;
     337             : }
     338             : 
     339             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     340           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     341             :     return 0;
     342           0 :   if ((Subtarget->hasNEON())) {
     343           0 :     return fastEmitInst_r(ARM::VCGEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     344             :   }
     345             :   return 0;
     346             : }
     347             : 
     348             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     349           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     350             :     return 0;
     351           0 :   if ((Subtarget->hasNEON())) {
     352           0 :     return fastEmitInst_r(ARM::VCGEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     353             :   }
     354             :   return 0;
     355             : }
     356             : 
     357             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     358           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     359             :     return 0;
     360           0 :   if ((Subtarget->hasNEON())) {
     361           0 :     return fastEmitInst_r(ARM::VCGEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     362             :   }
     363             :   return 0;
     364             : }
     365             : 
     366             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     367           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     368             :     return 0;
     369           0 :   if ((Subtarget->hasNEON())) {
     370           0 :     return fastEmitInst_r(ARM::VCGEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     371             :   }
     372             :   return 0;
     373             : }
     374             : 
     375           0 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     376           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     377             :     return 0;
     378           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     379           0 :     return fastEmitInst_r(ARM::VCGEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     380             :   }
     381             :   return 0;
     382             : }
     383             : 
     384           0 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     385           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     386             :     return 0;
     387           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     388           0 :     return fastEmitInst_r(ARM::VCGEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     389             :   }
     390             :   return 0;
     391             : }
     392             : 
     393             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     394           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     395             :     return 0;
     396           0 :   if ((Subtarget->hasNEON())) {
     397           0 :     return fastEmitInst_r(ARM::VCGEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     398             :   }
     399             :   return 0;
     400             : }
     401             : 
     402             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     403           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     404             :     return 0;
     405           0 :   if ((Subtarget->hasNEON())) {
     406           0 :     return fastEmitInst_r(ARM::VCGEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     407             :   }
     408             :   return 0;
     409             : }
     410             : 
     411           0 : unsigned fastEmit_ARMISD_VCGEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     412           0 :   switch (VT.SimpleTy) {
     413           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     414           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     415           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     416           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     417           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     418           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     419           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     420           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     421           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     422           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     423             :   default: return 0;
     424             :   }
     425             : }
     426             : 
     427             : // FastEmit functions for ARMISD::VCGTZ.
     428             : 
     429             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     430           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     431             :     return 0;
     432           0 :   if ((Subtarget->hasNEON())) {
     433           0 :     return fastEmitInst_r(ARM::VCGTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     434             :   }
     435             :   return 0;
     436             : }
     437             : 
     438             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     439           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     440             :     return 0;
     441           0 :   if ((Subtarget->hasNEON())) {
     442           0 :     return fastEmitInst_r(ARM::VCGTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     443             :   }
     444             :   return 0;
     445             : }
     446             : 
     447             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     448           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     449             :     return 0;
     450           0 :   if ((Subtarget->hasNEON())) {
     451           0 :     return fastEmitInst_r(ARM::VCGTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     452             :   }
     453             :   return 0;
     454             : }
     455             : 
     456             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     457           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     458             :     return 0;
     459           0 :   if ((Subtarget->hasNEON())) {
     460           0 :     return fastEmitInst_r(ARM::VCGTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     461             :   }
     462             :   return 0;
     463             : }
     464             : 
     465             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     466           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     467             :     return 0;
     468           0 :   if ((Subtarget->hasNEON())) {
     469           0 :     return fastEmitInst_r(ARM::VCGTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     470             :   }
     471             :   return 0;
     472             : }
     473             : 
     474             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     475           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     476             :     return 0;
     477           0 :   if ((Subtarget->hasNEON())) {
     478           0 :     return fastEmitInst_r(ARM::VCGTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     479             :   }
     480             :   return 0;
     481             : }
     482             : 
     483           0 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     484           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     485             :     return 0;
     486           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     487           0 :     return fastEmitInst_r(ARM::VCGTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     488             :   }
     489             :   return 0;
     490             : }
     491             : 
     492           0 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     493           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     494             :     return 0;
     495           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     496           0 :     return fastEmitInst_r(ARM::VCGTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     497             :   }
     498             :   return 0;
     499             : }
     500             : 
     501             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     502           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     503             :     return 0;
     504           0 :   if ((Subtarget->hasNEON())) {
     505           0 :     return fastEmitInst_r(ARM::VCGTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     506             :   }
     507             :   return 0;
     508             : }
     509             : 
     510             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     511           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     512             :     return 0;
     513           0 :   if ((Subtarget->hasNEON())) {
     514           0 :     return fastEmitInst_r(ARM::VCGTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     515             :   }
     516             :   return 0;
     517             : }
     518             : 
     519           0 : unsigned fastEmit_ARMISD_VCGTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     520           0 :   switch (VT.SimpleTy) {
     521           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     522           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     523           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     524           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     525           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     526           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     527           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     528           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     529           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     530           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     531             :   default: return 0;
     532             :   }
     533             : }
     534             : 
     535             : // FastEmit functions for ARMISD::VCLEZ.
     536             : 
     537             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     538           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     539             :     return 0;
     540           0 :   if ((Subtarget->hasNEON())) {
     541           0 :     return fastEmitInst_r(ARM::VCLEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     542             :   }
     543             :   return 0;
     544             : }
     545             : 
     546             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     547           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     548             :     return 0;
     549           0 :   if ((Subtarget->hasNEON())) {
     550           0 :     return fastEmitInst_r(ARM::VCLEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     551             :   }
     552             :   return 0;
     553             : }
     554             : 
     555             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     556           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     557             :     return 0;
     558           0 :   if ((Subtarget->hasNEON())) {
     559           0 :     return fastEmitInst_r(ARM::VCLEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     560             :   }
     561             :   return 0;
     562             : }
     563             : 
     564             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     565           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     566             :     return 0;
     567           0 :   if ((Subtarget->hasNEON())) {
     568           0 :     return fastEmitInst_r(ARM::VCLEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     569             :   }
     570             :   return 0;
     571             : }
     572             : 
     573             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     574           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     575             :     return 0;
     576           0 :   if ((Subtarget->hasNEON())) {
     577           0 :     return fastEmitInst_r(ARM::VCLEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     578             :   }
     579             :   return 0;
     580             : }
     581             : 
     582             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     583           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     584             :     return 0;
     585           0 :   if ((Subtarget->hasNEON())) {
     586           0 :     return fastEmitInst_r(ARM::VCLEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     587             :   }
     588             :   return 0;
     589             : }
     590             : 
     591           0 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     592           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     593             :     return 0;
     594           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     595           0 :     return fastEmitInst_r(ARM::VCLEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     596             :   }
     597             :   return 0;
     598             : }
     599             : 
     600           0 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     601           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     602             :     return 0;
     603           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     604           0 :     return fastEmitInst_r(ARM::VCLEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     605             :   }
     606             :   return 0;
     607             : }
     608             : 
     609             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     610           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     611             :     return 0;
     612           0 :   if ((Subtarget->hasNEON())) {
     613           0 :     return fastEmitInst_r(ARM::VCLEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     614             :   }
     615             :   return 0;
     616             : }
     617             : 
     618             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     619           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     620             :     return 0;
     621           0 :   if ((Subtarget->hasNEON())) {
     622           0 :     return fastEmitInst_r(ARM::VCLEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     623             :   }
     624             :   return 0;
     625             : }
     626             : 
     627           0 : unsigned fastEmit_ARMISD_VCLEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     628           0 :   switch (VT.SimpleTy) {
     629           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     630           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     631           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     632           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     633           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     634           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     635           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     636           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     637           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     638           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     639             :   default: return 0;
     640             :   }
     641             : }
     642             : 
     643             : // FastEmit functions for ARMISD::VCLTZ.
     644             : 
     645             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     646           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     647             :     return 0;
     648           0 :   if ((Subtarget->hasNEON())) {
     649           0 :     return fastEmitInst_r(ARM::VCLTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     650             :   }
     651             :   return 0;
     652             : }
     653             : 
     654             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     655           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     656             :     return 0;
     657           0 :   if ((Subtarget->hasNEON())) {
     658           0 :     return fastEmitInst_r(ARM::VCLTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     659             :   }
     660             :   return 0;
     661             : }
     662             : 
     663             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     664           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     665             :     return 0;
     666           0 :   if ((Subtarget->hasNEON())) {
     667           0 :     return fastEmitInst_r(ARM::VCLTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     668             :   }
     669             :   return 0;
     670             : }
     671             : 
     672             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     673           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     674             :     return 0;
     675           0 :   if ((Subtarget->hasNEON())) {
     676           0 :     return fastEmitInst_r(ARM::VCLTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     677             :   }
     678             :   return 0;
     679             : }
     680             : 
     681             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     682           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     683             :     return 0;
     684           0 :   if ((Subtarget->hasNEON())) {
     685           0 :     return fastEmitInst_r(ARM::VCLTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     686             :   }
     687             :   return 0;
     688             : }
     689             : 
     690             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     691           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     692             :     return 0;
     693           0 :   if ((Subtarget->hasNEON())) {
     694           0 :     return fastEmitInst_r(ARM::VCLTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     695             :   }
     696             :   return 0;
     697             : }
     698             : 
     699           0 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     700           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     701             :     return 0;
     702           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     703           0 :     return fastEmitInst_r(ARM::VCLTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     704             :   }
     705             :   return 0;
     706             : }
     707             : 
     708           0 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     709           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     710             :     return 0;
     711           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     712           0 :     return fastEmitInst_r(ARM::VCLTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     713             :   }
     714             :   return 0;
     715             : }
     716             : 
     717             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     718           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     719             :     return 0;
     720           0 :   if ((Subtarget->hasNEON())) {
     721           0 :     return fastEmitInst_r(ARM::VCLTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     722             :   }
     723             :   return 0;
     724             : }
     725             : 
     726             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     727           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     728             :     return 0;
     729           0 :   if ((Subtarget->hasNEON())) {
     730           0 :     return fastEmitInst_r(ARM::VCLTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     731             :   }
     732             :   return 0;
     733             : }
     734             : 
     735           0 : unsigned fastEmit_ARMISD_VCLTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     736           0 :   switch (VT.SimpleTy) {
     737           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     738           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     739           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     740           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     741           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     742           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     743           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     744           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     745           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     746           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     747             :   default: return 0;
     748             :   }
     749             : }
     750             : 
     751             : // FastEmit functions for ARMISD::VDUP.
     752             : 
     753             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
     754           0 :   if ((Subtarget->hasNEON())) {
     755           0 :     return fastEmitInst_r(ARM::VDUP8d, &ARM::DPRRegClass, Op0, Op0IsKill);
     756             :   }
     757             :   return 0;
     758             : }
     759             : 
     760             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
     761           0 :   if ((Subtarget->hasNEON())) {
     762           0 :     return fastEmitInst_r(ARM::VDUP8q, &ARM::QPRRegClass, Op0, Op0IsKill);
     763             :   }
     764             :   return 0;
     765             : }
     766             : 
     767             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
     768           0 :   if ((Subtarget->hasNEON())) {
     769           0 :     return fastEmitInst_r(ARM::VDUP16d, &ARM::DPRRegClass, Op0, Op0IsKill);
     770             :   }
     771             :   return 0;
     772             : }
     773             : 
     774             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
     775           0 :   if ((Subtarget->hasNEON())) {
     776           0 :     return fastEmitInst_r(ARM::VDUP16q, &ARM::QPRRegClass, Op0, Op0IsKill);
     777             :   }
     778             :   return 0;
     779             : }
     780             : 
     781           0 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
     782           0 :   if ((!Subtarget->hasSlowVDUP32()) && (Subtarget->hasNEON())) {
     783           0 :     return fastEmitInst_r(ARM::VDUP32d, &ARM::DPRRegClass, Op0, Op0IsKill);
     784             :   }
     785             :   return 0;
     786             : }
     787             : 
     788             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
     789           0 :   if ((Subtarget->hasNEON())) {
     790           0 :     return fastEmitInst_r(ARM::VDUP32q, &ARM::QPRRegClass, Op0, Op0IsKill);
     791             :   }
     792             :   return 0;
     793             : }
     794             : 
     795           0 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     796           0 : switch (RetVT.SimpleTy) {
     797           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill);
     798           0 :   case MVT::v16i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill);
     799           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill);
     800           0 :   case MVT::v8i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill);
     801           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill);
     802           0 :   case MVT::v4i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill);
     803             :   default: return 0;
     804             : }
     805             : }
     806             : 
     807             : unsigned fastEmit_ARMISD_VDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     808           0 :   switch (VT.SimpleTy) {
     809           0 :   case MVT::i32: return fastEmit_ARMISD_VDUP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     810             :   default: return 0;
     811             :   }
     812             : }
     813             : 
     814             : // FastEmit functions for ARMISD::VREV16.
     815             : 
     816             : unsigned fastEmit_ARMISD_VREV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     817           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     818             :     return 0;
     819           0 :   if ((Subtarget->hasNEON())) {
     820           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     821             :   }
     822             :   return 0;
     823             : }
     824             : 
     825             : unsigned fastEmit_ARMISD_VREV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     826           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     827             :     return 0;
     828           0 :   if ((Subtarget->hasNEON())) {
     829           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     830             :   }
     831             :   return 0;
     832             : }
     833             : 
     834           0 : unsigned fastEmit_ARMISD_VREV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     835           0 :   switch (VT.SimpleTy) {
     836           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     837           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     838             :   default: return 0;
     839             :   }
     840             : }
     841             : 
     842             : // FastEmit functions for ARMISD::VREV32.
     843             : 
     844             : unsigned fastEmit_ARMISD_VREV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     845           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     846             :     return 0;
     847           0 :   if ((Subtarget->hasNEON())) {
     848           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     849             :   }
     850             :   return 0;
     851             : }
     852             : 
     853             : unsigned fastEmit_ARMISD_VREV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     854           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     855             :     return 0;
     856           0 :   if ((Subtarget->hasNEON())) {
     857           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     858             :   }
     859             :   return 0;
     860             : }
     861             : 
     862             : unsigned fastEmit_ARMISD_VREV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     863           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     864             :     return 0;
     865           0 :   if ((Subtarget->hasNEON())) {
     866           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
     867             :   }
     868             :   return 0;
     869             : }
     870             : 
     871             : unsigned fastEmit_ARMISD_VREV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     872           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     873             :     return 0;
     874           0 :   if ((Subtarget->hasNEON())) {
     875           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
     876             :   }
     877             :   return 0;
     878             : }
     879             : 
     880           0 : unsigned fastEmit_ARMISD_VREV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     881           0 :   switch (VT.SimpleTy) {
     882           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     883           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     884           0 :   case MVT::v4i16: return fastEmit_ARMISD_VREV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     885           0 :   case MVT::v8i16: return fastEmit_ARMISD_VREV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     886             :   default: return 0;
     887             :   }
     888             : }
     889             : 
     890             : // FastEmit functions for ARMISD::VREV64.
     891             : 
     892             : unsigned fastEmit_ARMISD_VREV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     893           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     894             :     return 0;
     895           0 :   if ((Subtarget->hasNEON())) {
     896           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     897             :   }
     898             :   return 0;
     899             : }
     900             : 
     901             : unsigned fastEmit_ARMISD_VREV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     902           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     903             :     return 0;
     904           0 :   if ((Subtarget->hasNEON())) {
     905           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     906             :   }
     907             :   return 0;
     908             : }
     909             : 
     910             : unsigned fastEmit_ARMISD_VREV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     911           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     912             :     return 0;
     913           0 :   if ((Subtarget->hasNEON())) {
     914           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
     915             :   }
     916             :   return 0;
     917             : }
     918             : 
     919             : unsigned fastEmit_ARMISD_VREV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     920           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     921             :     return 0;
     922           0 :   if ((Subtarget->hasNEON())) {
     923           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
     924             :   }
     925             :   return 0;
     926             : }
     927             : 
     928             : unsigned fastEmit_ARMISD_VREV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     929           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     930             :     return 0;
     931           0 :   if ((Subtarget->hasNEON())) {
     932           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
     933             :   }
     934             :   return 0;
     935             : }
     936             : 
     937             : unsigned fastEmit_ARMISD_VREV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     938           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     939             :     return 0;
     940           0 :   if ((Subtarget->hasNEON())) {
     941           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
     942             :   }
     943             :   return 0;
     944             : }
     945             : 
     946             : unsigned fastEmit_ARMISD_VREV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     947           0 :   if (RetVT.SimpleTy != MVT::v2f32)
     948             :     return 0;
     949           0 :   return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
     950             : }
     951             : 
     952             : unsigned fastEmit_ARMISD_VREV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     953           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     954             :     return 0;
     955           0 :   return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
     956             : }
     957             : 
     958           0 : unsigned fastEmit_ARMISD_VREV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     959           0 :   switch (VT.SimpleTy) {
     960           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     961           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     962           0 :   case MVT::v4i16: return fastEmit_ARMISD_VREV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     963           0 :   case MVT::v8i16: return fastEmit_ARMISD_VREV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     964           0 :   case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     965           0 :   case MVT::v4i32: return fastEmit_ARMISD_VREV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     966           0 :   case MVT::v2f32: return fastEmit_ARMISD_VREV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     967           0 :   case MVT::v4f32: return fastEmit_ARMISD_VREV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     968             :   default: return 0;
     969             :   }
     970             : }
     971             : 
     972             : // FastEmit functions for ARMISD::WIN__DBZCHK.
     973             : 
     974             : unsigned fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     975           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     976             :     return 0;
     977           0 :   return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill);
     978             : }
     979             : 
     980             : unsigned fastEmit_ARMISD_WIN__DBZCHK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     981           0 :   switch (VT.SimpleTy) {
     982           0 :   case MVT::i32: return fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(RetVT, Op0, Op0IsKill);
     983             :   default: return 0;
     984             :   }
     985             : }
     986             : 
     987             : // FastEmit functions for ISD::ABS.
     988             : 
     989             : unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     990           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     991             :     return 0;
     992           0 :   if ((Subtarget->hasNEON())) {
     993           0 :     return fastEmitInst_r(ARM::VABSv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     994             :   }
     995             :   return 0;
     996             : }
     997             : 
     998             : unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     999           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1000             :     return 0;
    1001           0 :   if ((Subtarget->hasNEON())) {
    1002           0 :     return fastEmitInst_r(ARM::VABSv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1003             :   }
    1004             :   return 0;
    1005             : }
    1006             : 
    1007             : unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1008           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    1009             :     return 0;
    1010           0 :   if ((Subtarget->hasNEON())) {
    1011           0 :     return fastEmitInst_r(ARM::VABSv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1012             :   }
    1013             :   return 0;
    1014             : }
    1015             : 
    1016             : unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1017           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1018             :     return 0;
    1019           0 :   if ((Subtarget->hasNEON())) {
    1020           0 :     return fastEmitInst_r(ARM::VABSv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1021             :   }
    1022             :   return 0;
    1023             : }
    1024             : 
    1025             : unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1026           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    1027             :     return 0;
    1028           0 :   if ((Subtarget->hasNEON())) {
    1029           0 :     return fastEmitInst_r(ARM::VABSv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1030             :   }
    1031             :   return 0;
    1032             : }
    1033             : 
    1034             : unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1035           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1036             :     return 0;
    1037           0 :   if ((Subtarget->hasNEON())) {
    1038           0 :     return fastEmitInst_r(ARM::VABSv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1039             :   }
    1040             :   return 0;
    1041             : }
    1042             : 
    1043           0 : unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1044           0 :   switch (VT.SimpleTy) {
    1045           0 :   case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1046           0 :   case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1047           0 :   case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1048           0 :   case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1049           0 :   case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1050           0 :   case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1051             :   default: return 0;
    1052             :   }
    1053             : }
    1054             : 
    1055             : // FastEmit functions for ISD::ANY_EXTEND.
    1056             : 
    1057             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1058           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1059             :     return 0;
    1060           0 :   return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1061             : }
    1062             : 
    1063             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1064           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1065             :     return 0;
    1066           0 :   return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1067             : }
    1068             : 
    1069             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1070           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1071             :     return 0;
    1072           0 :   return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    1073             : }
    1074             : 
    1075           0 : unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1076           0 :   switch (VT.SimpleTy) {
    1077           0 :   case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1078           0 :   case MVT::v4i16: return fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1079           0 :   case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1080             :   default: return 0;
    1081             :   }
    1082             : }
    1083             : 
    1084             : // FastEmit functions for ISD::BITCAST.
    1085             : 
    1086           0 : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1087           0 :   if (RetVT.SimpleTy != MVT::f32)
    1088             :     return 0;
    1089           0 :   if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
    1090           0 :     return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
    1091             :   }
    1092             :   return 0;
    1093             : }
    1094             : 
    1095             : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1096          81 :   if (RetVT.SimpleTy != MVT::i32)
    1097             :     return 0;
    1098          81 :   if ((Subtarget->hasVFP2())) {
    1099          81 :     return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill);
    1100             :   }
    1101             :   return 0;
    1102             : }
    1103             : 
    1104           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1105           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1106           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1107             :   }
    1108             :   return 0;
    1109             : }
    1110             : 
    1111           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1112           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1113           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1114             :   }
    1115             :   return 0;
    1116             : }
    1117             : 
    1118           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1119           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1120           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1121             :   }
    1122             :   return 0;
    1123             : }
    1124             : 
    1125           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1126           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1127           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1128             :   }
    1129             :   return 0;
    1130             : }
    1131             : 
    1132           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1133           0 : switch (RetVT.SimpleTy) {
    1134           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill);
    1135           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill);
    1136           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill);
    1137           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill);
    1138             :   default: return 0;
    1139             : }
    1140             : }
    1141             : 
    1142           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1143           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1144           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1145             :   }
    1146             :   return 0;
    1147             : }
    1148             : 
    1149           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1150           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1151           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1152             :   }
    1153             :   return 0;
    1154             : }
    1155             : 
    1156           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1157           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1158           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1159             :   }
    1160             :   return 0;
    1161             : }
    1162             : 
    1163           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1164           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1165           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1166             :   }
    1167             :   return 0;
    1168             : }
    1169             : 
    1170           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1171           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1172           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1173             :   }
    1174             :   return 0;
    1175             : }
    1176             : 
    1177           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1178           0 : switch (RetVT.SimpleTy) {
    1179           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill);
    1180           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill);
    1181           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill);
    1182           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill);
    1183           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill);
    1184             :   default: return 0;
    1185             : }
    1186             : }
    1187             : 
    1188           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1189           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1190           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1191             :   }
    1192             :   return 0;
    1193             : }
    1194             : 
    1195           2 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1196           2 :   if ((MF->getDataLayout().isBigEndian())) {
    1197           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1198             :   }
    1199             :   return 0;
    1200             : }
    1201             : 
    1202           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1203           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1204           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1205             :   }
    1206             :   return 0;
    1207             : }
    1208             : 
    1209           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1210           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1211           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1212             :   }
    1213             :   return 0;
    1214             : }
    1215             : 
    1216           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1217           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1218           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1219             :   }
    1220             :   return 0;
    1221             : }
    1222             : 
    1223           2 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1224           2 : switch (RetVT.SimpleTy) {
    1225           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill);
    1226           2 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
    1227           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
    1228           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill);
    1229           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill);
    1230             :   default: return 0;
    1231             : }
    1232             : }
    1233             : 
    1234           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1235           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1236           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1237             :   }
    1238             :   return 0;
    1239             : }
    1240             : 
    1241           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1242           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1243           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1244             :   }
    1245             :   return 0;
    1246             : }
    1247             : 
    1248           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1249           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1250           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1251             :   }
    1252             :   return 0;
    1253             : }
    1254             : 
    1255           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1256           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1257           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1258             :   }
    1259             :   return 0;
    1260             : }
    1261             : 
    1262           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1263           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1264           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1265             :   }
    1266             :   return 0;
    1267             : }
    1268             : 
    1269           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1270           0 : switch (RetVT.SimpleTy) {
    1271           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill);
    1272           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill);
    1273           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill);
    1274           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill);
    1275           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill);
    1276             :   default: return 0;
    1277             : }
    1278             : }
    1279             : 
    1280           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1281           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1282           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1283             :   }
    1284             :   return 0;
    1285             : }
    1286             : 
    1287           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1288           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1289           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1290             :   }
    1291             :   return 0;
    1292             : }
    1293             : 
    1294           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1295           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1296           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1297             :   }
    1298             :   return 0;
    1299             : }
    1300             : 
    1301           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1302           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1303           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1304             :   }
    1305             :   return 0;
    1306             : }
    1307             : 
    1308           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1309           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1310           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1311             :   }
    1312             :   return 0;
    1313             : }
    1314             : 
    1315           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1316           0 : switch (RetVT.SimpleTy) {
    1317           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill);
    1318           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
    1319           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
    1320           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill);
    1321           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill);
    1322             :   default: return 0;
    1323             : }
    1324             : }
    1325             : 
    1326           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1327           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1328           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1329             :   }
    1330             :   return 0;
    1331             : }
    1332             : 
    1333           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1334           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1335           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1336             :   }
    1337             :   return 0;
    1338             : }
    1339             : 
    1340           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1341           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1342           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1343             :   }
    1344             :   return 0;
    1345             : }
    1346             : 
    1347           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1348           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1349           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1350             :   }
    1351             :   return 0;
    1352             : }
    1353             : 
    1354           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1355           0 : switch (RetVT.SimpleTy) {
    1356           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill);
    1357           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill);
    1358           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill);
    1359           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill);
    1360             :   default: return 0;
    1361             : }
    1362             : }
    1363             : 
    1364           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1365           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1366           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1367             :   }
    1368             :   return 0;
    1369             : }
    1370             : 
    1371           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1372           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1373           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1374             :   }
    1375             :   return 0;
    1376             : }
    1377             : 
    1378           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1379           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1380           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1381             :   }
    1382             :   return 0;
    1383             : }
    1384             : 
    1385           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1386           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1387           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1388             :   }
    1389             :   return 0;
    1390             : }
    1391             : 
    1392           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1393           0 : switch (RetVT.SimpleTy) {
    1394           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill);
    1395           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill);
    1396           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill);
    1397           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill);
    1398             :   default: return 0;
    1399             : }
    1400             : }
    1401             : 
    1402           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1403           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1404           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1405             :   }
    1406             :   return 0;
    1407             : }
    1408             : 
    1409           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1410           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1411           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1412             :   }
    1413             :   return 0;
    1414             : }
    1415             : 
    1416           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1417           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1418           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1419             :   }
    1420             :   return 0;
    1421             : }
    1422             : 
    1423           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1424           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1425           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1426             :   }
    1427             :   return 0;
    1428             : }
    1429             : 
    1430           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1431           0 : switch (RetVT.SimpleTy) {
    1432           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill);
    1433           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill);
    1434           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill);
    1435           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill);
    1436             :   default: return 0;
    1437             : }
    1438             : }
    1439             : 
    1440           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1441           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1442           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1443             :   }
    1444             :   return 0;
    1445             : }
    1446             : 
    1447           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1448           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1449           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1450             :   }
    1451             :   return 0;
    1452             : }
    1453             : 
    1454           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1455           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1456           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1457             :   }
    1458             :   return 0;
    1459             : }
    1460             : 
    1461           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1462           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1463           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1464             :   }
    1465             :   return 0;
    1466             : }
    1467             : 
    1468           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1469           0 : switch (RetVT.SimpleTy) {
    1470           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill);
    1471           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill);
    1472           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill);
    1473           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill);
    1474             :   default: return 0;
    1475             : }
    1476             : }
    1477             : 
    1478           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1479           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1480           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1481             :   }
    1482             :   return 0;
    1483             : }
    1484             : 
    1485           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1486           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1487           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1488             :   }
    1489             :   return 0;
    1490             : }
    1491             : 
    1492           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1493           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1494           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1495             :   }
    1496             :   return 0;
    1497             : }
    1498             : 
    1499           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1500           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1501           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1502             :   }
    1503             :   return 0;
    1504             : }
    1505             : 
    1506           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1507           0 : switch (RetVT.SimpleTy) {
    1508           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill);
    1509           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill);
    1510           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill);
    1511           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill);
    1512             :   default: return 0;
    1513             : }
    1514             : }
    1515             : 
    1516           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1517           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1518           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1519             :   }
    1520             :   return 0;
    1521             : }
    1522             : 
    1523           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1524           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1525           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1526             :   }
    1527             :   return 0;
    1528             : }
    1529             : 
    1530           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1531           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1532           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1533             :   }
    1534             :   return 0;
    1535             : }
    1536             : 
    1537           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1538           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1539           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1540             :   }
    1541             :   return 0;
    1542             : }
    1543             : 
    1544           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1545           0 : switch (RetVT.SimpleTy) {
    1546           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill);
    1547           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill);
    1548           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill);
    1549           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill);
    1550             :   default: return 0;
    1551             : }
    1552             : }
    1553             : 
    1554           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1555           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1556           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1557             :   }
    1558             :   return 0;
    1559             : }
    1560             : 
    1561           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1562           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1563           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1564             :   }
    1565             :   return 0;
    1566             : }
    1567             : 
    1568           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1569           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1570           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1571             :   }
    1572             :   return 0;
    1573             : }
    1574             : 
    1575           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1576           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1577           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1578             :   }
    1579             :   return 0;
    1580             : }
    1581             : 
    1582           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1583           0 : switch (RetVT.SimpleTy) {
    1584           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill);
    1585           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill);
    1586           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill);
    1587           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill);
    1588             :   default: return 0;
    1589             : }
    1590             : }
    1591             : 
    1592          83 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1593          83 :   switch (VT.SimpleTy) {
    1594           0 :   case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1595          81 :   case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1596           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1597           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1598           2 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1599           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1600           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1601           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1602           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1603           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
    1604           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1605           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    1606           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1607           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1608             :   default: return 0;
    1609             :   }
    1610             : }
    1611             : 
    1612             : // FastEmit functions for ISD::BITREVERSE.
    1613             : 
    1614           0 : unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1615           0 :   if (RetVT.SimpleTy != MVT::i32)
    1616             :     return 0;
    1617           0 :   if ((Subtarget->isThumb2())) {
    1618           0 :     return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1619             :   }
    1620           0 :   if ((Subtarget->hasV6T2Ops()) && (!Subtarget->isThumb())) {
    1621           0 :     return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill);
    1622             :   }
    1623             :   return 0;
    1624             : }
    1625             : 
    1626             : unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1627           0 :   switch (VT.SimpleTy) {
    1628           0 :   case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1629             :   default: return 0;
    1630             :   }
    1631             : }
    1632             : 
    1633             : // FastEmit functions for ISD::BRIND.
    1634             : 
    1635           0 : unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1636           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1637             :     return 0;
    1638           0 :   if ((Subtarget->isThumb())) {
    1639           0 :     return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill);
    1640             :   }
    1641           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
    1642           0 :     return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill);
    1643             :   }
    1644           0 :   if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
    1645           0 :     return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill);
    1646             :   }
    1647             :   return 0;
    1648             : }
    1649             : 
    1650             : unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1651           0 :   switch (VT.SimpleTy) {
    1652           0 :   case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1653             :   default: return 0;
    1654             :   }
    1655             : }
    1656             : 
    1657             : // FastEmit functions for ISD::BSWAP.
    1658             : 
    1659           0 : unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1660           0 :   if (RetVT.SimpleTy != MVT::i32)
    1661             :     return 0;
    1662           0 :   if ((Subtarget->isThumb2())) {
    1663           0 :     return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1664             :   }
    1665           0 :   if ((Subtarget->hasV6Ops()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    1666           0 :     return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill);
    1667             :   }
    1668           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    1669           0 :     return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill);
    1670             :   }
    1671             :   return 0;
    1672             : }
    1673             : 
    1674             : unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1675           0 :   switch (VT.SimpleTy) {
    1676           0 :   case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1677             :   default: return 0;
    1678             :   }
    1679             : }
    1680             : 
    1681             : // FastEmit functions for ISD::CTLZ.
    1682             : 
    1683           0 : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1684           0 :   if (RetVT.SimpleTy != MVT::i32)
    1685             :     return 0;
    1686           0 :   if ((Subtarget->isThumb2())) {
    1687           0 :     return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1688             :   }
    1689           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
    1690           0 :     return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill);
    1691             :   }
    1692             :   return 0;
    1693             : }
    1694             : 
    1695             : unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1696           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    1697             :     return 0;
    1698           0 :   if ((Subtarget->hasNEON())) {
    1699           0 :     return fastEmitInst_r(ARM::VCLZv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1700             :   }
    1701             :   return 0;
    1702             : }
    1703             : 
    1704             : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1705           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1706             :     return 0;
    1707           0 :   if ((Subtarget->hasNEON())) {
    1708           0 :     return fastEmitInst_r(ARM::VCLZv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1709             :   }
    1710             :   return 0;
    1711             : }
    1712             : 
    1713             : unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1714           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    1715             :     return 0;
    1716           0 :   if ((Subtarget->hasNEON())) {
    1717           0 :     return fastEmitInst_r(ARM::VCLZv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1718             :   }
    1719             :   return 0;
    1720             : }
    1721             : 
    1722             : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1723           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1724             :     return 0;
    1725           0 :   if ((Subtarget->hasNEON())) {
    1726           0 :     return fastEmitInst_r(ARM::VCLZv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1727             :   }
    1728             :   return 0;
    1729             : }
    1730             : 
    1731             : unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1732           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    1733             :     return 0;
    1734           0 :   if ((Subtarget->hasNEON())) {
    1735           0 :     return fastEmitInst_r(ARM::VCLZv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1736             :   }
    1737             :   return 0;
    1738             : }
    1739             : 
    1740             : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1741           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1742             :     return 0;
    1743           0 :   if ((Subtarget->hasNEON())) {
    1744           0 :     return fastEmitInst_r(ARM::VCLZv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1745             :   }
    1746             :   return 0;
    1747             : }
    1748             : 
    1749           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1750           0 :   switch (VT.SimpleTy) {
    1751           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1752           0 :   case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1753           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1754           0 :   case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1755           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1756           0 :   case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1757           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1758             :   default: return 0;
    1759             :   }
    1760             : }
    1761             : 
    1762             : // FastEmit functions for ISD::CTPOP.
    1763             : 
    1764             : unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1765           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    1766             :     return 0;
    1767           0 :   if ((Subtarget->hasNEON())) {
    1768           0 :     return fastEmitInst_r(ARM::VCNTd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1769             :   }
    1770             :   return 0;
    1771             : }
    1772             : 
    1773             : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1774           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1775             :     return 0;
    1776           0 :   if ((Subtarget->hasNEON())) {
    1777           0 :     return fastEmitInst_r(ARM::VCNTq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1778             :   }
    1779             :   return 0;
    1780             : }
    1781             : 
    1782           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1783           0 :   switch (VT.SimpleTy) {
    1784           0 :   case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1785           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1786             :   default: return 0;
    1787             :   }
    1788             : }
    1789             : 
    1790             : // FastEmit functions for ISD::FABS.
    1791             : 
    1792           0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1793           0 :   if (RetVT.SimpleTy != MVT::f32)
    1794             :     return 0;
    1795           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    1796           0 :     return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1797             :   }
    1798             :   return 0;
    1799             : }
    1800             : 
    1801           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1802           0 :   if (RetVT.SimpleTy != MVT::f64)
    1803             :     return 0;
    1804           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    1805           0 :     return fastEmitInst_r(ARM::VABSD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1806             :   }
    1807             :   return 0;
    1808             : }
    1809             : 
    1810           0 : unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1811           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    1812             :     return 0;
    1813           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    1814           0 :     return fastEmitInst_r(ARM::VABShd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1815             :   }
    1816             :   return 0;
    1817             : }
    1818             : 
    1819           0 : unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1820           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    1821             :     return 0;
    1822           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    1823           0 :     return fastEmitInst_r(ARM::VABShq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1824             :   }
    1825             :   return 0;
    1826             : }
    1827             : 
    1828             : unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1829           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    1830             :     return 0;
    1831           0 :   if ((Subtarget->hasNEON())) {
    1832           0 :     return fastEmitInst_r(ARM::VABSfd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1833             :   }
    1834             :   return 0;
    1835             : }
    1836             : 
    1837             : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1838           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1839             :     return 0;
    1840           0 :   if ((Subtarget->hasNEON())) {
    1841           0 :     return fastEmitInst_r(ARM::VABSfq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1842             :   }
    1843             :   return 0;
    1844             : }
    1845             : 
    1846           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1847           0 :   switch (VT.SimpleTy) {
    1848           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1849           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1850           0 :   case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    1851           0 :   case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    1852           0 :   case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    1853           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1854             :   default: return 0;
    1855             :   }
    1856             : }
    1857             : 
    1858             : // FastEmit functions for ISD::FCEIL.
    1859             : 
    1860             : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1861           0 :   if (RetVT.SimpleTy != MVT::f32)
    1862             :     return 0;
    1863           0 :   if ((Subtarget->hasFPARMv8())) {
    1864           0 :     return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1865             :   }
    1866             :   return 0;
    1867             : }
    1868             : 
    1869           0 : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1870           0 :   if (RetVT.SimpleTy != MVT::f64)
    1871             :     return 0;
    1872           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    1873           0 :     return fastEmitInst_r(ARM::VRINTPD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1874             :   }
    1875             :   return 0;
    1876             : }
    1877             : 
    1878           0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1879           0 :   switch (VT.SimpleTy) {
    1880           0 :   case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1881           0 :   case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1882             :   default: return 0;
    1883             :   }
    1884             : }
    1885             : 
    1886             : // FastEmit functions for ISD::FFLOOR.
    1887             : 
    1888             : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1889           0 :   if (RetVT.SimpleTy != MVT::f32)
    1890             :     return 0;
    1891           0 :   if ((Subtarget->hasFPARMv8())) {
    1892           0 :     return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1893             :   }
    1894             :   return 0;
    1895             : }
    1896             : 
    1897           0 : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1898           0 :   if (RetVT.SimpleTy != MVT::f64)
    1899             :     return 0;
    1900           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    1901           0 :     return fastEmitInst_r(ARM::VRINTMD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1902             :   }
    1903             :   return 0;
    1904             : }
    1905             : 
    1906           0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1907           0 :   switch (VT.SimpleTy) {
    1908           0 :   case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1909           0 :   case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1910             :   default: return 0;
    1911             :   }
    1912             : }
    1913             : 
    1914             : // FastEmit functions for ISD::FNEARBYINT.
    1915             : 
    1916             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1917           0 :   if (RetVT.SimpleTy != MVT::f32)
    1918             :     return 0;
    1919           0 :   if ((Subtarget->hasFPARMv8())) {
    1920           0 :     return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1921             :   }
    1922             :   return 0;
    1923             : }
    1924             : 
    1925           0 : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1926           0 :   if (RetVT.SimpleTy != MVT::f64)
    1927             :     return 0;
    1928           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    1929           0 :     return fastEmitInst_r(ARM::VRINTRD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1930             :   }
    1931             :   return 0;
    1932             : }
    1933             : 
    1934           0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1935           0 :   switch (VT.SimpleTy) {
    1936           0 :   case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1937           0 :   case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1938             :   default: return 0;
    1939             :   }
    1940             : }
    1941             : 
    1942             : // FastEmit functions for ISD::FNEG.
    1943             : 
    1944           0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1945           0 :   if (RetVT.SimpleTy != MVT::f32)
    1946             :     return 0;
    1947           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    1948           0 :     return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1949             :   }
    1950             :   return 0;
    1951             : }
    1952             : 
    1953           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1954           0 :   if (RetVT.SimpleTy != MVT::f64)
    1955             :     return 0;
    1956           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    1957           0 :     return fastEmitInst_r(ARM::VNEGD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1958             :   }
    1959             :   return 0;
    1960             : }
    1961             : 
    1962           0 : unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1963           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    1964             :     return 0;
    1965           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    1966           0 :     return fastEmitInst_r(ARM::VNEGhd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1967             :   }
    1968             :   return 0;
    1969             : }
    1970             : 
    1971           0 : unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1972           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    1973             :     return 0;
    1974           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    1975           0 :     return fastEmitInst_r(ARM::VNEGhq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1976             :   }
    1977             :   return 0;
    1978             : }
    1979             : 
    1980             : unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1981           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    1982             :     return 0;
    1983           0 :   if ((Subtarget->hasNEON())) {
    1984           0 :     return fastEmitInst_r(ARM::VNEGfd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1985             :   }
    1986             :   return 0;
    1987             : }
    1988             : 
    1989             : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1990           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1991             :     return 0;
    1992           0 :   if ((Subtarget->hasNEON())) {
    1993           0 :     return fastEmitInst_r(ARM::VNEGf32q, &ARM::QPRRegClass, Op0, Op0IsKill);
    1994             :   }
    1995             :   return 0;
    1996             : }
    1997             : 
    1998           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1999           0 :   switch (VT.SimpleTy) {
    2000           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2001           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2002           0 :   case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2003           0 :   case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2004           0 :   case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2005           0 :   case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2006             :   default: return 0;
    2007             :   }
    2008             : }
    2009             : 
    2010             : // FastEmit functions for ISD::FP_EXTEND.
    2011             : 
    2012           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2013           0 :   if (RetVT.SimpleTy != MVT::f64)
    2014             :     return 0;
    2015           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2016           0 :     return fastEmitInst_r(ARM::VCVTDS, &ARM::DPRRegClass, Op0, Op0IsKill);
    2017             :   }
    2018             :   return 0;
    2019             : }
    2020             : 
    2021             : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2022           0 :   switch (VT.SimpleTy) {
    2023           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2024             :   default: return 0;
    2025             :   }
    2026             : }
    2027             : 
    2028             : // FastEmit functions for ISD::FP_ROUND.
    2029             : 
    2030           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2031           0 :   if (RetVT.SimpleTy != MVT::f32)
    2032             :     return 0;
    2033           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2034           0 :     return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill);
    2035             :   }
    2036             :   return 0;
    2037             : }
    2038             : 
    2039             : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2040           0 :   switch (VT.SimpleTy) {
    2041           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2042             :   default: return 0;
    2043             :   }
    2044             : }
    2045             : 
    2046             : // FastEmit functions for ISD::FP_TO_SINT.
    2047             : 
    2048           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2049           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2050             :     return 0;
    2051           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2052           0 :     return fastEmitInst_r(ARM::VCVTh2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2053             :   }
    2054             :   return 0;
    2055             : }
    2056             : 
    2057           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2058           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2059             :     return 0;
    2060           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2061           0 :     return fastEmitInst_r(ARM::VCVTh2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2062             :   }
    2063             :   return 0;
    2064             : }
    2065             : 
    2066             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2067           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2068             :     return 0;
    2069           0 :   if ((Subtarget->hasNEON())) {
    2070           0 :     return fastEmitInst_r(ARM::VCVTf2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2071             :   }
    2072             :   return 0;
    2073             : }
    2074             : 
    2075             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2076           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2077             :     return 0;
    2078           0 :   if ((Subtarget->hasNEON())) {
    2079           0 :     return fastEmitInst_r(ARM::VCVTf2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2080             :   }
    2081             :   return 0;
    2082             : }
    2083             : 
    2084           6 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2085           6 :   switch (VT.SimpleTy) {
    2086           0 :   case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2087           0 :   case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2088           0 :   case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2089           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2090             :   default: return 0;
    2091             :   }
    2092             : }
    2093             : 
    2094             : // FastEmit functions for ISD::FP_TO_UINT.
    2095             : 
    2096           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2097           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2098             :     return 0;
    2099           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2100           0 :     return fastEmitInst_r(ARM::VCVTh2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
    2101             :   }
    2102             :   return 0;
    2103             : }
    2104             : 
    2105           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2106           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2107             :     return 0;
    2108           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2109           0 :     return fastEmitInst_r(ARM::VCVTh2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2110             :   }
    2111             :   return 0;
    2112             : }
    2113             : 
    2114             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2115           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2116             :     return 0;
    2117           0 :   if ((Subtarget->hasNEON())) {
    2118           0 :     return fastEmitInst_r(ARM::VCVTf2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
    2119             :   }
    2120             :   return 0;
    2121             : }
    2122             : 
    2123             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2124           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2125             :     return 0;
    2126           0 :   if ((Subtarget->hasNEON())) {
    2127           0 :     return fastEmitInst_r(ARM::VCVTf2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2128             :   }
    2129             :   return 0;
    2130             : }
    2131             : 
    2132           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2133           0 :   switch (VT.SimpleTy) {
    2134           0 :   case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2135           0 :   case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2136           0 :   case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2137           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2138             :   default: return 0;
    2139             :   }
    2140             : }
    2141             : 
    2142             : // FastEmit functions for ISD::FRINT.
    2143             : 
    2144             : unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2145           0 :   if (RetVT.SimpleTy != MVT::f32)
    2146             :     return 0;
    2147           0 :   if ((Subtarget->hasFPARMv8())) {
    2148           0 :     return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2149             :   }
    2150             :   return 0;
    2151             : }
    2152             : 
    2153           0 : unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2154           0 :   if (RetVT.SimpleTy != MVT::f64)
    2155             :     return 0;
    2156           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2157           0 :     return fastEmitInst_r(ARM::VRINTXD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2158             :   }
    2159             :   return 0;
    2160             : }
    2161             : 
    2162           0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2163           0 :   switch (VT.SimpleTy) {
    2164           0 :   case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2165           0 :   case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2166             :   default: return 0;
    2167             :   }
    2168             : }
    2169             : 
    2170             : // FastEmit functions for ISD::FROUND.
    2171             : 
    2172             : unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2173           0 :   if (RetVT.SimpleTy != MVT::f32)
    2174             :     return 0;
    2175           0 :   if ((Subtarget->hasFPARMv8())) {
    2176           0 :     return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2177             :   }
    2178             :   return 0;
    2179             : }
    2180             : 
    2181           0 : unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2182           0 :   if (RetVT.SimpleTy != MVT::f64)
    2183             :     return 0;
    2184           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2185           0 :     return fastEmitInst_r(ARM::VRINTAD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2186             :   }
    2187             :   return 0;
    2188             : }
    2189             : 
    2190           0 : unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2191           0 :   switch (VT.SimpleTy) {
    2192           0 :   case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2193           0 :   case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2194             :   default: return 0;
    2195             :   }
    2196             : }
    2197             : 
    2198             : // FastEmit functions for ISD::FSQRT.
    2199             : 
    2200             : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2201           0 :   if (RetVT.SimpleTy != MVT::f32)
    2202             :     return 0;
    2203           0 :   if ((Subtarget->hasVFP2())) {
    2204           0 :     return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2205             :   }
    2206             :   return 0;
    2207             : }
    2208             : 
    2209           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2210           0 :   if (RetVT.SimpleTy != MVT::f64)
    2211             :     return 0;
    2212           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2213           0 :     return fastEmitInst_r(ARM::VSQRTD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2214             :   }
    2215             :   return 0;
    2216             : }
    2217             : 
    2218           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2219           0 :   switch (VT.SimpleTy) {
    2220           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2221           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2222             :   default: return 0;
    2223             :   }
    2224             : }
    2225             : 
    2226             : // FastEmit functions for ISD::FTRUNC.
    2227             : 
    2228             : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2229           0 :   if (RetVT.SimpleTy != MVT::f32)
    2230             :     return 0;
    2231           0 :   if ((Subtarget->hasFPARMv8())) {
    2232           0 :     return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2233             :   }
    2234             :   return 0;
    2235             : }
    2236             : 
    2237           0 : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2238           0 :   if (RetVT.SimpleTy != MVT::f64)
    2239             :     return 0;
    2240           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2241           0 :     return fastEmitInst_r(ARM::VRINTZD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2242             :   }
    2243             :   return 0;
    2244             : }
    2245             : 
    2246           0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2247           0 :   switch (VT.SimpleTy) {
    2248           0 :   case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2249           0 :   case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2250             :   default: return 0;
    2251             :   }
    2252             : }
    2253             : 
    2254             : // FastEmit functions for ISD::SIGN_EXTEND.
    2255             : 
    2256             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2257           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2258             :     return 0;
    2259           0 :   if ((Subtarget->hasNEON())) {
    2260           0 :     return fastEmitInst_r(ARM::VMOVLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    2261             :   }
    2262             :   return 0;
    2263             : }
    2264             : 
    2265             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2266           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2267             :     return 0;
    2268           0 :   if ((Subtarget->hasNEON())) {
    2269           0 :     return fastEmitInst_r(ARM::VMOVLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    2270             :   }
    2271             :   return 0;
    2272             : }
    2273             : 
    2274             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2275           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2276             :     return 0;
    2277           0 :   if ((Subtarget->hasNEON())) {
    2278           0 :     return fastEmitInst_r(ARM::VMOVLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    2279             :   }
    2280             :   return 0;
    2281             : }
    2282             : 
    2283           1 : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2284           1 :   switch (VT.SimpleTy) {
    2285           0 :   case MVT::v8i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    2286           0 :   case MVT::v4i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2287           0 :   case MVT::v2i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2288             :   default: return 0;
    2289             :   }
    2290             : }
    2291             : 
    2292             : // FastEmit functions for ISD::SINT_TO_FP.
    2293             : 
    2294           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2295           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    2296             :     return 0;
    2297           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2298           0 :     return fastEmitInst_r(ARM::VCVTs2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2299             :   }
    2300             :   return 0;
    2301             : }
    2302             : 
    2303           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2304           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    2305             :     return 0;
    2306           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2307           0 :     return fastEmitInst_r(ARM::VCVTs2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2308             :   }
    2309             :   return 0;
    2310             : }
    2311             : 
    2312             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2313           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    2314             :     return 0;
    2315           0 :   if ((Subtarget->hasNEON())) {
    2316           0 :     return fastEmitInst_r(ARM::VCVTs2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2317             :   }
    2318             :   return 0;
    2319             : }
    2320             : 
    2321             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2322           2 :   if (RetVT.SimpleTy != MVT::v4f32)
    2323             :     return 0;
    2324           2 :   if ((Subtarget->hasNEON())) {
    2325           2 :     return fastEmitInst_r(ARM::VCVTs2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2326             :   }
    2327             :   return 0;
    2328             : }
    2329             : 
    2330           9 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2331           9 :   switch (VT.SimpleTy) {
    2332           0 :   case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2333           0 :   case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2334           0 :   case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2335           2 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2336             :   default: return 0;
    2337             :   }
    2338             : }
    2339             : 
    2340             : // FastEmit functions for ISD::TRUNCATE.
    2341             : 
    2342             : unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2343           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2344             :     return 0;
    2345           0 :   if ((Subtarget->hasNEON())) {
    2346           0 :     return fastEmitInst_r(ARM::VMOVNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
    2347             :   }
    2348             :   return 0;
    2349             : }
    2350             : 
    2351             : unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2352           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2353             :     return 0;
    2354           0 :   if ((Subtarget->hasNEON())) {
    2355           0 :     return fastEmitInst_r(ARM::VMOVNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    2356             :   }
    2357             :   return 0;
    2358             : }
    2359             : 
    2360             : unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2361           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2362             :     return 0;
    2363           0 :   if ((Subtarget->hasNEON())) {
    2364           0 :     return fastEmitInst_r(ARM::VMOVNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    2365             :   }
    2366             :   return 0;
    2367             : }
    2368             : 
    2369           0 : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2370           0 :   switch (VT.SimpleTy) {
    2371           0 :   case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2372           0 :   case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2373           0 :   case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    2374             :   default: return 0;
    2375             :   }
    2376             : }
    2377             : 
    2378             : // FastEmit functions for ISD::UINT_TO_FP.
    2379             : 
    2380           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2381           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    2382             :     return 0;
    2383           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2384           0 :     return fastEmitInst_r(ARM::VCVTu2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2385             :   }
    2386             :   return 0;
    2387             : }
    2388             : 
    2389           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2390           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    2391             :     return 0;
    2392           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2393           0 :     return fastEmitInst_r(ARM::VCVTu2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2394             :   }
    2395             :   return 0;
    2396             : }
    2397             : 
    2398             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2399           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    2400             :     return 0;
    2401           0 :   if ((Subtarget->hasNEON())) {
    2402           0 :     return fastEmitInst_r(ARM::VCVTu2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2403             :   }
    2404             :   return 0;
    2405             : }
    2406             : 
    2407             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2408           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2409             :     return 0;
    2410           0 :   if ((Subtarget->hasNEON())) {
    2411           0 :     return fastEmitInst_r(ARM::VCVTu2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2412             :   }
    2413             :   return 0;
    2414             : }
    2415             : 
    2416           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2417           0 :   switch (VT.SimpleTy) {
    2418           0 :   case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2419           0 :   case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2420           0 :   case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2421           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2422             :   default: return 0;
    2423             :   }
    2424             : }
    2425             : 
    2426             : // FastEmit functions for ISD::ZERO_EXTEND.
    2427             : 
    2428             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2429           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2430             :     return 0;
    2431           0 :   if ((Subtarget->hasNEON())) {
    2432           0 :     return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    2433             :   }
    2434             :   return 0;
    2435             : }
    2436             : 
    2437             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2438           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2439             :     return 0;
    2440           0 :   if ((Subtarget->hasNEON())) {
    2441           0 :     return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    2442             :   }
    2443             :   return 0;
    2444             : }
    2445             : 
    2446             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2447           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2448             :     return 0;
    2449           0 :   if ((Subtarget->hasNEON())) {
    2450           0 :     return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    2451             :   }
    2452             :   return 0;
    2453             : }
    2454             : 
    2455           0 : unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2456           0 :   switch (VT.SimpleTy) {
    2457           0 :   case MVT::v8i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    2458           0 :   case MVT::v4i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2459           0 :   case MVT::v2i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2460             :   default: return 0;
    2461             :   }
    2462             : }
    2463             : 
    2464             : // Top-level FastEmit function.
    2465             : 
    2466          99 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    2467          99 :   switch (Opcode) {
    2468           0 :   case ARMISD::CALL: return fastEmit_ARMISD_CALL_r(VT, RetVT, Op0, Op0IsKill);
    2469           0 :   case ARMISD::CALL_NOLINK: return fastEmit_ARMISD_CALL_NOLINK_r(VT, RetVT, Op0, Op0IsKill);
    2470           0 :   case ARMISD::CALL_PRED: return fastEmit_ARMISD_CALL_PRED_r(VT, RetVT, Op0, Op0IsKill);
    2471           0 :   case ARMISD::RRX: return fastEmit_ARMISD_RRX_r(VT, RetVT, Op0, Op0IsKill);
    2472           0 :   case ARMISD::SRA_FLAG: return fastEmit_ARMISD_SRA_FLAG_r(VT, RetVT, Op0, Op0IsKill);
    2473           0 :   case ARMISD::SRL_FLAG: return fastEmit_ARMISD_SRL_FLAG_r(VT, RetVT, Op0, Op0IsKill);
    2474           0 :   case ARMISD::TC_RETURN: return fastEmit_ARMISD_TC_RETURN_r(VT, RetVT, Op0, Op0IsKill);
    2475           0 :   case ARMISD::VCEQZ: return fastEmit_ARMISD_VCEQZ_r(VT, RetVT, Op0, Op0IsKill);
    2476           0 :   case ARMISD::VCGEZ: return fastEmit_ARMISD_VCGEZ_r(VT, RetVT, Op0, Op0IsKill);
    2477           0 :   case ARMISD::VCGTZ: return fastEmit_ARMISD_VCGTZ_r(VT, RetVT, Op0, Op0IsKill);
    2478           0 :   case ARMISD::VCLEZ: return fastEmit_ARMISD_VCLEZ_r(VT, RetVT, Op0, Op0IsKill);
    2479           0 :   case ARMISD::VCLTZ: return fastEmit_ARMISD_VCLTZ_r(VT, RetVT, Op0, Op0IsKill);
    2480           0 :   case ARMISD::VDUP: return fastEmit_ARMISD_VDUP_r(VT, RetVT, Op0, Op0IsKill);
    2481           0 :   case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill);
    2482           0 :   case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill);
    2483           0 :   case ARMISD::VREV64: return fastEmit_ARMISD_VREV64_r(VT, RetVT, Op0, Op0IsKill);
    2484           0 :   case ARMISD::WIN__DBZCHK: return fastEmit_ARMISD_WIN__DBZCHK_r(VT, RetVT, Op0, Op0IsKill);
    2485           0 :   case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill);
    2486           0 :   case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2487          83 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    2488           0 :   case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill);
    2489           0 :   case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
    2490           0 :   case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill);
    2491           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    2492           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    2493           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    2494           0 :   case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
    2495           0 :   case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
    2496           0 :   case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
    2497           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    2498           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2499           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    2500           6 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    2501           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    2502           0 :   case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
    2503           0 :   case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill);
    2504           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    2505           0 :   case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
    2506           1 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2507           9 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    2508           0 :   case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
    2509           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    2510           0 :   case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2511             :   default: return 0;
    2512             :   }
    2513             : }
    2514             : 
    2515             : // FastEmit functions for ARMISD::CMP.
    2516             : 
    2517           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2518           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2519             :     return 0;
    2520           0 :   if ((Subtarget->isThumb2())) {
    2521           0 :     return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2522             :   }
    2523           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2524           0 :     return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2525             :   }
    2526           0 :   if ((!Subtarget->isThumb())) {
    2527           0 :     return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2528             :   }
    2529             :   return 0;
    2530             : }
    2531             : 
    2532             : unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2533           0 :   switch (VT.SimpleTy) {
    2534           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2535             :   default: return 0;
    2536             :   }
    2537             : }
    2538             : 
    2539             : // FastEmit functions for ARMISD::CMPZ.
    2540             : 
    2541           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2542           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2543             :     return 0;
    2544           0 :   if ((Subtarget->isThumb2())) {
    2545           0 :     return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2546             :   }
    2547           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2548           0 :     return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2549             :   }
    2550           0 :   if ((!Subtarget->isThumb())) {
    2551           0 :     return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2552             :   }
    2553             :   return 0;
    2554             : }
    2555             : 
    2556             : unsigned fastEmit_ARMISD_CMPZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2557           0 :   switch (VT.SimpleTy) {
    2558           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2559             :   default: return 0;
    2560             :   }
    2561             : }
    2562             : 
    2563             : // FastEmit functions for ARMISD::EH_SJLJ_LONGJMP.
    2564             : 
    2565           0 : unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2566           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2567             :     return 0;
    2568           0 :   if ((Subtarget->isThumb()) && (Subtarget->isTargetWindows())) {
    2569           0 :     return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2570             :   }
    2571           0 :   if ((!Subtarget->isTargetWindows()) && (Subtarget->isThumb())) {
    2572           0 :     return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2573             :   }
    2574           0 :   if ((!Subtarget->isThumb())) {
    2575           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2576             :   }
    2577             :   return 0;
    2578             : }
    2579             : 
    2580             : unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2581           0 :   switch (VT.SimpleTy) {
    2582           0 :   case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2583             :   default: return 0;
    2584             :   }
    2585             : }
    2586             : 
    2587             : // FastEmit functions for ARMISD::EH_SJLJ_SETJMP.
    2588             : 
    2589           0 : unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2590           0 :   if (RetVT.SimpleTy != MVT::i32)
    2591             :     return 0;
    2592           0 :   if ((Subtarget->isThumb2()) && (!Subtarget->hasVFP2())) {
    2593           0 :     return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2594             :   }
    2595           0 :   if ((Subtarget->hasVFP2()) && (Subtarget->isThumb2())) {
    2596           0 :     return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2597             :   }
    2598           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2599           0 :     return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2600             :   }
    2601           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasVFP2())) {
    2602           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2603             :   }
    2604           0 :   if ((Subtarget->hasVFP2()) && (!Subtarget->isThumb())) {
    2605           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2606             :   }
    2607             :   return 0;
    2608             : }
    2609             : 
    2610             : unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2611           0 :   switch (VT.SimpleTy) {
    2612           0 :   case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2613             :   default: return 0;
    2614             :   }
    2615             : }
    2616             : 
    2617             : // FastEmit functions for ARMISD::SMULWB.
    2618             : 
    2619           0 : unsigned fastEmit_ARMISD_SMULWB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2620           0 :   if (RetVT.SimpleTy != MVT::i32)
    2621             :     return 0;
    2622           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    2623           0 :     return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2624             :   }
    2625           0 :   if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
    2626           0 :     return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2627             :   }
    2628             :   return 0;
    2629             : }
    2630             : 
    2631             : unsigned fastEmit_ARMISD_SMULWB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2632           0 :   switch (VT.SimpleTy) {
    2633           0 :   case MVT::i32: return fastEmit_ARMISD_SMULWB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2634             :   default: return 0;
    2635             :   }
    2636             : }
    2637             : 
    2638             : // FastEmit functions for ARMISD::SMULWT.
    2639             : 
    2640           0 : unsigned fastEmit_ARMISD_SMULWT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2641           0 :   if (RetVT.SimpleTy != MVT::i32)
    2642             :     return 0;
    2643           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    2644           0 :     return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2645             :   }
    2646           0 :   if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
    2647           0 :     return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2648             :   }
    2649             :   return 0;
    2650             : }
    2651             : 
    2652             : unsigned fastEmit_ARMISD_SMULWT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2653           0 :   switch (VT.SimpleTy) {
    2654           0 :   case MVT::i32: return fastEmit_ARMISD_SMULWT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2655             :   default: return 0;
    2656             :   }
    2657             : }
    2658             : 
    2659             : // FastEmit functions for ARMISD::VCEQ.
    2660             : 
    2661             : unsigned fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2662           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2663             :     return 0;
    2664           0 :   if ((Subtarget->hasNEON())) {
    2665           0 :     return fastEmitInst_rr(ARM::VCEQv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2666             :   }
    2667             :   return 0;
    2668             : }
    2669             : 
    2670             : unsigned fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2671           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2672             :     return 0;
    2673           0 :   if ((Subtarget->hasNEON())) {
    2674           0 :     return fastEmitInst_rr(ARM::VCEQv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2675             :   }
    2676             :   return 0;
    2677             : }
    2678             : 
    2679             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2680           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2681             :     return 0;
    2682           0 :   if ((Subtarget->hasNEON())) {
    2683           0 :     return fastEmitInst_rr(ARM::VCEQv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2684             :   }
    2685             :   return 0;
    2686             : }
    2687             : 
    2688             : unsigned fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2689           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2690             :     return 0;
    2691           0 :   if ((Subtarget->hasNEON())) {
    2692           0 :     return fastEmitInst_rr(ARM::VCEQv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2693             :   }
    2694             :   return 0;
    2695             : }
    2696             : 
    2697             : unsigned fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2698           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2699             :     return 0;
    2700           0 :   if ((Subtarget->hasNEON())) {
    2701           0 :     return fastEmitInst_rr(ARM::VCEQv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2702             :   }
    2703             :   return 0;
    2704             : }
    2705             : 
    2706             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2707           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2708             :     return 0;
    2709           0 :   if ((Subtarget->hasNEON())) {
    2710           0 :     return fastEmitInst_rr(ARM::VCEQv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2711             :   }
    2712             :   return 0;
    2713             : }
    2714             : 
    2715           0 : unsigned fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2716           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2717             :     return 0;
    2718           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2719           0 :     return fastEmitInst_rr(ARM::VCEQhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2720             :   }
    2721             :   return 0;
    2722             : }
    2723             : 
    2724           0 : unsigned fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2725           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2726             :     return 0;
    2727           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2728           0 :     return fastEmitInst_rr(ARM::VCEQhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2729             :   }
    2730             :   return 0;
    2731             : }
    2732             : 
    2733             : unsigned fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2734           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2735             :     return 0;
    2736           0 :   if ((Subtarget->hasNEON())) {
    2737           0 :     return fastEmitInst_rr(ARM::VCEQfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2738             :   }
    2739             :   return 0;
    2740             : }
    2741             : 
    2742             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2743           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2744             :     return 0;
    2745           0 :   if ((Subtarget->hasNEON())) {
    2746           0 :     return fastEmitInst_rr(ARM::VCEQfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2747             :   }
    2748             :   return 0;
    2749             : }
    2750             : 
    2751           0 : unsigned fastEmit_ARMISD_VCEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2752           0 :   switch (VT.SimpleTy) {
    2753           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2754           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2755           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2756           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2757           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2758           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2759           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2760           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2761           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2762           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2763             :   default: return 0;
    2764             :   }
    2765             : }
    2766             : 
    2767             : // FastEmit functions for ARMISD::VCGE.
    2768             : 
    2769             : unsigned fastEmit_ARMISD_VCGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2770           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2771             :     return 0;
    2772           0 :   if ((Subtarget->hasNEON())) {
    2773           0 :     return fastEmitInst_rr(ARM::VCGEsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2774             :   }
    2775             :   return 0;
    2776             : }
    2777             : 
    2778             : unsigned fastEmit_ARMISD_VCGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2779           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2780             :     return 0;
    2781           0 :   if ((Subtarget->hasNEON())) {
    2782           0 :     return fastEmitInst_rr(ARM::VCGEsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2783             :   }
    2784             :   return 0;
    2785             : }
    2786             : 
    2787             : unsigned fastEmit_ARMISD_VCGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2788           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2789             :     return 0;
    2790           0 :   if ((Subtarget->hasNEON())) {
    2791           0 :     return fastEmitInst_rr(ARM::VCGEsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2792             :   }
    2793             :   return 0;
    2794             : }
    2795             : 
    2796             : unsigned fastEmit_ARMISD_VCGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2797           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2798             :     return 0;
    2799           0 :   if ((Subtarget->hasNEON())) {
    2800           0 :     return fastEmitInst_rr(ARM::VCGEsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2801             :   }
    2802             :   return 0;
    2803             : }
    2804             : 
    2805             : unsigned fastEmit_ARMISD_VCGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2806           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2807             :     return 0;
    2808           0 :   if ((Subtarget->hasNEON())) {
    2809           0 :     return fastEmitInst_rr(ARM::VCGEsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2810             :   }
    2811             :   return 0;
    2812             : }
    2813             : 
    2814             : unsigned fastEmit_ARMISD_VCGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2815           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2816             :     return 0;
    2817           0 :   if ((Subtarget->hasNEON())) {
    2818           0 :     return fastEmitInst_rr(ARM::VCGEsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2819             :   }
    2820             :   return 0;
    2821             : }
    2822             : 
    2823           0 : unsigned fastEmit_ARMISD_VCGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2824           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2825             :     return 0;
    2826           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2827           0 :     return fastEmitInst_rr(ARM::VCGEhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2828             :   }
    2829             :   return 0;
    2830             : }
    2831             : 
    2832           0 : unsigned fastEmit_ARMISD_VCGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2833           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2834             :     return 0;
    2835           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2836           0 :     return fastEmitInst_rr(ARM::VCGEhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2837             :   }
    2838             :   return 0;
    2839             : }
    2840             : 
    2841             : unsigned fastEmit_ARMISD_VCGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2842           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2843             :     return 0;
    2844           0 :   if ((Subtarget->hasNEON())) {
    2845           0 :     return fastEmitInst_rr(ARM::VCGEfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2846             :   }
    2847             :   return 0;
    2848             : }
    2849             : 
    2850             : unsigned fastEmit_ARMISD_VCGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2851           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2852             :     return 0;
    2853           0 :   if ((Subtarget->hasNEON())) {
    2854           0 :     return fastEmitInst_rr(ARM::VCGEfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2855             :   }
    2856             :   return 0;
    2857             : }
    2858             : 
    2859           0 : unsigned fastEmit_ARMISD_VCGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2860           0 :   switch (VT.SimpleTy) {
    2861           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2862           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2863           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2864           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2865           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2866           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2867           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2868           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2869           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2870           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2871             :   default: return 0;
    2872             :   }
    2873             : }
    2874             : 
    2875             : // FastEmit functions for ARMISD::VCGEU.
    2876             : 
    2877             : unsigned fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2878           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2879             :     return 0;
    2880           0 :   if ((Subtarget->hasNEON())) {
    2881           0 :     return fastEmitInst_rr(ARM::VCGEuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2882             :   }
    2883             :   return 0;
    2884             : }
    2885             : 
    2886             : unsigned fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2887           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2888             :     return 0;
    2889           0 :   if ((Subtarget->hasNEON())) {
    2890           0 :     return fastEmitInst_rr(ARM::VCGEuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2891             :   }
    2892             :   return 0;
    2893             : }
    2894             : 
    2895             : unsigned fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2896           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2897             :     return 0;
    2898           0 :   if ((Subtarget->hasNEON())) {
    2899           0 :     return fastEmitInst_rr(ARM::VCGEuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2900             :   }
    2901             :   return 0;
    2902             : }
    2903             : 
    2904             : unsigned fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2905           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2906             :     return 0;
    2907           0 :   if ((Subtarget->hasNEON())) {
    2908           0 :     return fastEmitInst_rr(ARM::VCGEuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2909             :   }
    2910             :   return 0;
    2911             : }
    2912             : 
    2913             : unsigned fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2914           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2915             :     return 0;
    2916           0 :   if ((Subtarget->hasNEON())) {
    2917           0 :     return fastEmitInst_rr(ARM::VCGEuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2918             :   }
    2919             :   return 0;
    2920             : }
    2921             : 
    2922             : unsigned fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2923           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2924             :     return 0;
    2925           0 :   if ((Subtarget->hasNEON())) {
    2926           0 :     return fastEmitInst_rr(ARM::VCGEuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2927             :   }
    2928             :   return 0;
    2929             : }
    2930             : 
    2931           0 : unsigned fastEmit_ARMISD_VCGEU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2932           0 :   switch (VT.SimpleTy) {
    2933           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2934           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2935           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2936           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2937           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2938           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2939             :   default: return 0;
    2940             :   }
    2941             : }
    2942             : 
    2943             : // FastEmit functions for ARMISD::VCGT.
    2944             : 
    2945             : unsigned fastEmit_ARMISD_VCGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2946           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2947             :     return 0;
    2948           0 :   if ((Subtarget->hasNEON())) {
    2949           0 :     return fastEmitInst_rr(ARM::VCGTsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2950             :   }
    2951             :   return 0;
    2952             : }
    2953             : 
    2954             : unsigned fastEmit_ARMISD_VCGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2955           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2956             :     return 0;
    2957           0 :   if ((Subtarget->hasNEON())) {
    2958           0 :     return fastEmitInst_rr(ARM::VCGTsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2959             :   }
    2960             :   return 0;
    2961             : }
    2962             : 
    2963             : unsigned fastEmit_ARMISD_VCGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2964           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2965             :     return 0;
    2966           0 :   if ((Subtarget->hasNEON())) {
    2967           0 :     return fastEmitInst_rr(ARM::VCGTsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2968             :   }
    2969             :   return 0;
    2970             : }
    2971             : 
    2972             : unsigned fastEmit_ARMISD_VCGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2973           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2974             :     return 0;
    2975           0 :   if ((Subtarget->hasNEON())) {
    2976           0 :     return fastEmitInst_rr(ARM::VCGTsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2977             :   }
    2978             :   return 0;
    2979             : }
    2980             : 
    2981             : unsigned fastEmit_ARMISD_VCGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2982           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2983             :     return 0;
    2984           0 :   if ((Subtarget->hasNEON())) {
    2985           0 :     return fastEmitInst_rr(ARM::VCGTsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2986             :   }
    2987             :   return 0;
    2988             : }
    2989             : 
    2990             : unsigned fastEmit_ARMISD_VCGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2991           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2992             :     return 0;
    2993           0 :   if ((Subtarget->hasNEON())) {
    2994           0 :     return fastEmitInst_rr(ARM::VCGTsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2995             :   }
    2996             :   return 0;
    2997             : }
    2998             : 
    2999           0 : unsigned fastEmit_ARMISD_VCGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3000           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3001             :     return 0;
    3002           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3003           0 :     return fastEmitInst_rr(ARM::VCGThd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3004             :   }
    3005             :   return 0;
    3006             : }
    3007             : 
    3008           0 : unsigned fastEmit_ARMISD_VCGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3009           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3010             :     return 0;
    3011           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3012           0 :     return fastEmitInst_rr(ARM::VCGThq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3013             :   }
    3014             :   return 0;
    3015             : }
    3016             : 
    3017             : unsigned fastEmit_ARMISD_VCGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3018           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3019             :     return 0;
    3020           0 :   if ((Subtarget->hasNEON())) {
    3021           0 :     return fastEmitInst_rr(ARM::VCGTfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3022             :   }
    3023             :   return 0;
    3024             : }
    3025             : 
    3026             : unsigned fastEmit_ARMISD_VCGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3027           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3028             :     return 0;
    3029           0 :   if ((Subtarget->hasNEON())) {
    3030           0 :     return fastEmitInst_rr(ARM::VCGTfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3031             :   }
    3032             :   return 0;
    3033             : }
    3034             : 
    3035           0 : unsigned fastEmit_ARMISD_VCGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3036           0 :   switch (VT.SimpleTy) {
    3037           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3038           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3039           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3040           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3041           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3042           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3043           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3044           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3045           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3046           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3047             :   default: return 0;
    3048             :   }
    3049             : }
    3050             : 
    3051             : // FastEmit functions for ARMISD::VCGTU.
    3052             : 
    3053             : unsigned fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3054           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3055             :     return 0;
    3056           0 :   if ((Subtarget->hasNEON())) {
    3057           0 :     return fastEmitInst_rr(ARM::VCGTuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3058             :   }
    3059             :   return 0;
    3060             : }
    3061             : 
    3062             : unsigned fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3063           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3064             :     return 0;
    3065           0 :   if ((Subtarget->hasNEON())) {
    3066           0 :     return fastEmitInst_rr(ARM::VCGTuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3067             :   }
    3068             :   return 0;
    3069             : }
    3070             : 
    3071             : unsigned fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3072           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3073             :     return 0;
    3074           0 :   if ((Subtarget->hasNEON())) {
    3075           0 :     return fastEmitInst_rr(ARM::VCGTuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3076             :   }
    3077             :   return 0;
    3078             : }
    3079             : 
    3080             : unsigned fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3081           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3082             :     return 0;
    3083           0 :   if ((Subtarget->hasNEON())) {
    3084           0 :     return fastEmitInst_rr(ARM::VCGTuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3085             :   }
    3086             :   return 0;
    3087             : }
    3088             : 
    3089             : unsigned fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3090           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3091             :     return 0;
    3092           0 :   if ((Subtarget->hasNEON())) {
    3093           0 :     return fastEmitInst_rr(ARM::VCGTuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3094             :   }
    3095             :   return 0;
    3096             : }
    3097             : 
    3098             : unsigned fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3099           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3100             :     return 0;
    3101           0 :   if ((Subtarget->hasNEON())) {
    3102           0 :     return fastEmitInst_rr(ARM::VCGTuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3103             :   }
    3104             :   return 0;
    3105             : }
    3106             : 
    3107           0 : unsigned fastEmit_ARMISD_VCGTU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3108           0 :   switch (VT.SimpleTy) {
    3109           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3110           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3111           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3112           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3113           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3114           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3115             :   default: return 0;
    3116             :   }
    3117             : }
    3118             : 
    3119             : // FastEmit functions for ARMISD::VMOVDRR.
    3120             : 
    3121             : unsigned fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3122           0 :   if (RetVT.SimpleTy != MVT::f64)
    3123             :     return 0;
    3124           0 :   if ((Subtarget->hasVFP2())) {
    3125           0 :     return fastEmitInst_rr(ARM::VMOVDRR, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3126             :   }
    3127             :   return 0;
    3128             : }
    3129             : 
    3130           0 : unsigned fastEmit_ARMISD_VMOVDRR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3131           0 :   switch (VT.SimpleTy) {
    3132           0 :   case MVT::i32: return fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3133             :   default: return 0;
    3134             :   }
    3135             : }
    3136             : 
    3137             : // FastEmit functions for ARMISD::VMULLs.
    3138             : 
    3139             : unsigned fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3140           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3141             :     return 0;
    3142           0 :   if ((Subtarget->hasNEON())) {
    3143           0 :     return fastEmitInst_rr(ARM::VMULLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3144             :   }
    3145             :   return 0;
    3146             : }
    3147             : 
    3148             : unsigned fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3149           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3150             :     return 0;
    3151           0 :   if ((Subtarget->hasNEON())) {
    3152           0 :     return fastEmitInst_rr(ARM::VMULLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3153             :   }
    3154             :   return 0;
    3155             : }
    3156             : 
    3157             : unsigned fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3158           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3159             :     return 0;
    3160           0 :   if ((Subtarget->hasNEON())) {
    3161           0 :     return fastEmitInst_rr(ARM::VMULLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3162             :   }
    3163             :   return 0;
    3164             : }
    3165             : 
    3166           0 : unsigned fastEmit_ARMISD_VMULLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3167           0 :   switch (VT.SimpleTy) {
    3168           0 :   case MVT::v8i8: return fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3169           0 :   case MVT::v4i16: return fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3170           0 :   case MVT::v2i32: return fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3171             :   default: return 0;
    3172             :   }
    3173             : }
    3174             : 
    3175             : // FastEmit functions for ARMISD::VMULLu.
    3176             : 
    3177             : unsigned fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3178           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3179             :     return 0;
    3180           0 :   if ((Subtarget->hasNEON())) {
    3181           0 :     return fastEmitInst_rr(ARM::VMULLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3182             :   }
    3183             :   return 0;
    3184             : }
    3185             : 
    3186             : unsigned fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3187           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3188             :     return 0;
    3189           0 :   if ((Subtarget->hasNEON())) {
    3190           0 :     return fastEmitInst_rr(ARM::VMULLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3191             :   }
    3192             :   return 0;
    3193             : }
    3194             : 
    3195             : unsigned fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3196           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3197             :     return 0;
    3198           0 :   if ((Subtarget->hasNEON())) {
    3199           0 :     return fastEmitInst_rr(ARM::VMULLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3200             :   }
    3201             :   return 0;
    3202             : }
    3203             : 
    3204           0 : unsigned fastEmit_ARMISD_VMULLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3205           0 :   switch (VT.SimpleTy) {
    3206           0 :   case MVT::v8i8: return fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3207           0 :   case MVT::v4i16: return fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3208           0 :   case MVT::v2i32: return fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3209             :   default: return 0;
    3210             :   }
    3211             : }
    3212             : 
    3213             : // FastEmit functions for ARMISD::VTBL1.
    3214             : 
    3215             : unsigned fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3216           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3217             :     return 0;
    3218           0 :   if ((Subtarget->hasNEON())) {
    3219           0 :     return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3220             :   }
    3221             :   return 0;
    3222             : }
    3223             : 
    3224           0 : unsigned fastEmit_ARMISD_VTBL1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3225           0 :   switch (VT.SimpleTy) {
    3226           0 :   case MVT::v8i8: return fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3227             :   default: return 0;
    3228             :   }
    3229             : }
    3230             : 
    3231             : // FastEmit functions for ARMISD::VTST.
    3232             : 
    3233             : unsigned fastEmit_ARMISD_VTST_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3234           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3235             :     return 0;
    3236           0 :   if ((Subtarget->hasNEON())) {
    3237           0 :     return fastEmitInst_rr(ARM::VTSTv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3238             :   }
    3239             :   return 0;
    3240             : }
    3241             : 
    3242             : unsigned fastEmit_ARMISD_VTST_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3243           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3244             :     return 0;
    3245           0 :   if ((Subtarget->hasNEON())) {
    3246           0 :     return fastEmitInst_rr(ARM::VTSTv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3247             :   }
    3248             :   return 0;
    3249             : }
    3250             : 
    3251             : unsigned fastEmit_ARMISD_VTST_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3252           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3253             :     return 0;
    3254           0 :   if ((Subtarget->hasNEON())) {
    3255           0 :     return fastEmitInst_rr(ARM::VTSTv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3256             :   }
    3257             :   return 0;
    3258             : }
    3259             : 
    3260             : unsigned fastEmit_ARMISD_VTST_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3261           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3262             :     return 0;
    3263           0 :   if ((Subtarget->hasNEON())) {
    3264           0 :     return fastEmitInst_rr(ARM::VTSTv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3265             :   }
    3266             :   return 0;
    3267             : }
    3268             : 
    3269             : unsigned fastEmit_ARMISD_VTST_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3270           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3271             :     return 0;
    3272           0 :   if ((Subtarget->hasNEON())) {
    3273           0 :     return fastEmitInst_rr(ARM::VTSTv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3274             :   }
    3275             :   return 0;
    3276             : }
    3277             : 
    3278             : unsigned fastEmit_ARMISD_VTST_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3279           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3280             :     return 0;
    3281           0 :   if ((Subtarget->hasNEON())) {
    3282           0 :     return fastEmitInst_rr(ARM::VTSTv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3283             :   }
    3284             :   return 0;
    3285             : }
    3286             : 
    3287           0 : unsigned fastEmit_ARMISD_VTST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3288           0 :   switch (VT.SimpleTy) {
    3289           0 :   case MVT::v8i8: return fastEmit_ARMISD_VTST_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3290           0 :   case MVT::v16i8: return fastEmit_ARMISD_VTST_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3291           0 :   case MVT::v4i16: return fastEmit_ARMISD_VTST_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3292           0 :   case MVT::v8i16: return fastEmit_ARMISD_VTST_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3293           0 :   case MVT::v2i32: return fastEmit_ARMISD_VTST_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3294           0 :   case MVT::v4i32: return fastEmit_ARMISD_VTST_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3295             :   default: return 0;
    3296             :   }
    3297             : }
    3298             : 
    3299             : // FastEmit functions for ISD::ADD.
    3300             : 
    3301          96 : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3302          96 :   if (RetVT.SimpleTy != MVT::i32)
    3303             :     return 0;
    3304          96 :   if ((Subtarget->isThumb2())) {
    3305          22 :     return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3306             :   }
    3307          74 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    3308           0 :     return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3309             :   }
    3310          74 :   if ((!Subtarget->isThumb())) {
    3311          74 :     return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3312             :   }
    3313             :   return 0;
    3314             : }
    3315             : 
    3316             : unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3317           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3318             :     return 0;
    3319           0 :   if ((Subtarget->hasNEON())) {
    3320           0 :     return fastEmitInst_rr(ARM::VADDv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3321             :   }
    3322             :   return 0;
    3323             : }
    3324             : 
    3325             : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3326           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3327             :     return 0;
    3328           0 :   if ((Subtarget->hasNEON())) {
    3329           0 :     return fastEmitInst_rr(ARM::VADDv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3330             :   }
    3331             :   return 0;
    3332             : }
    3333             : 
    3334             : unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3335           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3336             :     return 0;
    3337           0 :   if ((Subtarget->hasNEON())) {
    3338           0 :     return fastEmitInst_rr(ARM::VADDv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3339             :   }
    3340             :   return 0;
    3341             : }
    3342             : 
    3343             : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3344           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3345             :     return 0;
    3346           0 :   if ((Subtarget->hasNEON())) {
    3347           0 :     return fastEmitInst_rr(ARM::VADDv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3348             :   }
    3349             :   return 0;
    3350             : }
    3351             : 
    3352             : unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3353           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3354             :     return 0;
    3355           0 :   if ((Subtarget->hasNEON())) {
    3356           0 :     return fastEmitInst_rr(ARM::VADDv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3357             :   }
    3358             :   return 0;
    3359             : }
    3360             : 
    3361             : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3362           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3363             :     return 0;
    3364           0 :   if ((Subtarget->hasNEON())) {
    3365           0 :     return fastEmitInst_rr(ARM::VADDv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3366             :   }
    3367             :   return 0;
    3368             : }
    3369             : 
    3370             : unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3371           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    3372             :     return 0;
    3373           0 :   if ((Subtarget->hasNEON())) {
    3374           0 :     return fastEmitInst_rr(ARM::VADDv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3375             :   }
    3376             :   return 0;
    3377             : }
    3378             : 
    3379             : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3380           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3381             :     return 0;
    3382           0 :   if ((Subtarget->hasNEON())) {
    3383           0 :     return fastEmitInst_rr(ARM::VADDv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3384             :   }
    3385             :   return 0;
    3386             : }
    3387             : 
    3388          96 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3389          96 :   switch (VT.SimpleTy) {
    3390          96 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3391           0 :   case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3392           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3393           0 :   case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3394           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3395           0 :   case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3396           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3397           0 :   case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3398           0 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3399             :   default: return 0;
    3400             :   }
    3401             : }
    3402             : 
    3403             : // FastEmit functions for ISD::AND.
    3404             : 
    3405           0 : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3406           0 :   if (RetVT.SimpleTy != MVT::i32)
    3407             :     return 0;
    3408           0 :   if ((Subtarget->isThumb2())) {
    3409           0 :     return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3410             :   }
    3411           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    3412           0 :     return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3413             :   }
    3414           0 :   if ((!Subtarget->isThumb())) {
    3415           0 :     return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3416             :   }
    3417             :   return 0;
    3418             : }
    3419             : 
    3420             : unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3421           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3422             :     return 0;
    3423           0 :   if ((Subtarget->hasNEON())) {
    3424           0 :     return fastEmitInst_rr(ARM::VANDd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3425             :   }
    3426             :   return 0;
    3427             : }
    3428             : 
    3429             : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3430           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3431             :     return 0;
    3432           0 :   if ((Subtarget->hasNEON())) {
    3433           0 :     return fastEmitInst_rr(ARM::VANDq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3434             :   }
    3435             :   return 0;
    3436             : }
    3437             : 
    3438           0 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3439           0 :   switch (VT.SimpleTy) {
    3440           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3441           0 :   case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3442           0 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3443             :   default: return 0;
    3444             :   }
    3445             : }
    3446             : 
    3447             : // FastEmit functions for ISD::FADD.
    3448             : 
    3449          17 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3450          17 :   if (RetVT.SimpleTy != MVT::f32)
    3451             :     return 0;
    3452          34 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    3453          17 :     return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3454             :   }
    3455             :   return 0;
    3456             : }
    3457             : 
    3458          15 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3459          15 :   if (RetVT.SimpleTy != MVT::f64)
    3460             :     return 0;
    3461          15 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3462          14 :     return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3463             :   }
    3464             :   return 0;
    3465             : }
    3466             : 
    3467           0 : unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3468           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3469             :     return 0;
    3470           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3471           0 :     return fastEmitInst_rr(ARM::VADDhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3472             :   }
    3473             :   return 0;
    3474             : }
    3475             : 
    3476           0 : unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3477           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3478             :     return 0;
    3479           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3480           0 :     return fastEmitInst_rr(ARM::VADDhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3481             :   }
    3482             :   return 0;
    3483             : }
    3484             : 
    3485             : unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3486           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3487             :     return 0;
    3488           0 :   if ((Subtarget->hasNEON())) {
    3489           0 :     return fastEmitInst_rr(ARM::VADDfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3490             :   }
    3491             :   return 0;
    3492             : }
    3493             : 
    3494             : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3495           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3496             :     return 0;
    3497           0 :   if ((Subtarget->hasNEON())) {
    3498           0 :     return fastEmitInst_rr(ARM::VADDfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3499             :   }
    3500             :   return 0;
    3501             : }
    3502             : 
    3503          33 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3504          33 :   switch (VT.SimpleTy) {
    3505          17 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3506          15 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3507           0 :   case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3508           0 :   case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3509           0 :   case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3510           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3511             :   default: return 0;
    3512             :   }
    3513             : }
    3514             : 
    3515             : // FastEmit functions for ISD::FDIV.
    3516             : 
    3517             : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3518           0 :   if (RetVT.SimpleTy != MVT::f32)
    3519             :     return 0;
    3520           0 :   if ((Subtarget->hasVFP2())) {
    3521           0 :     return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3522             :   }
    3523             :   return 0;
    3524             : }
    3525             : 
    3526           0 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3527           0 :   if (RetVT.SimpleTy != MVT::f64)
    3528             :     return 0;
    3529           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3530           0 :     return fastEmitInst_rr(ARM::VDIVD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3531             :   }
    3532             :   return 0;
    3533             : }
    3534             : 
    3535           0 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3536           0 :   switch (VT.SimpleTy) {
    3537           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3538           0 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3539             :   default: return 0;
    3540             :   }
    3541             : }
    3542             : 
    3543             : // FastEmit functions for ISD::FMAXNAN.
    3544             : 
    3545           0 : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3546           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3547             :     return 0;
    3548           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3549           0 :     return fastEmitInst_rr(ARM::VMAXhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3550             :   }
    3551             :   return 0;
    3552             : }
    3553             : 
    3554           0 : unsigned fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3555           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3556             :     return 0;
    3557           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3558           0 :     return fastEmitInst_rr(ARM::VMAXhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3559             :   }
    3560             :   return 0;
    3561             : }
    3562             : 
    3563             : unsigned fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3564           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3565             :     return 0;
    3566           0 :   if ((Subtarget->hasNEON())) {
    3567           0 :     return fastEmitInst_rr(ARM::VMAXfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3568             :   }
    3569             :   return 0;
    3570             : }
    3571             : 
    3572             : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3573           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3574             :     return 0;
    3575           0 :   if ((Subtarget->hasNEON())) {
    3576           0 :     return fastEmitInst_rr(ARM::VMAXfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3577             :   }
    3578             :   return 0;
    3579             : }
    3580             : 
    3581           0 : unsigned fastEmit_ISD_FMAXNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3582           0 :   switch (VT.SimpleTy) {
    3583           0 :   case MVT::v4f16: return fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3584           0 :   case MVT::v8f16: return fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3585           0 :   case MVT::v2f32: return fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3586           0 :   case MVT::v4f32: return fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3587             :   default: return 0;
    3588             :   }
    3589             : }
    3590             : 
    3591             : // FastEmit functions for ISD::FMAXNUM.
    3592             : 
    3593             : unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3594           0 :   if (RetVT.SimpleTy != MVT::f32)
    3595             :     return 0;
    3596           0 :   if ((Subtarget->hasFPARMv8())) {
    3597           0 :     return fastEmitInst_rr(ARM::VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3598             :   }
    3599             :   return 0;
    3600             : }
    3601             : 
    3602           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3603           0 :   if (RetVT.SimpleTy != MVT::f64)
    3604             :     return 0;
    3605           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    3606           0 :     return fastEmitInst_rr(ARM::VMAXNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3607             :   }
    3608             :   return 0;
    3609             : }
    3610             : 
    3611           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3612           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3613             :     return 0;
    3614           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3615           0 :     return fastEmitInst_rr(ARM::VMAXNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3616             :   }
    3617             :   return 0;
    3618             : }
    3619             : 
    3620           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3621           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3622             :     return 0;
    3623           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3624           0 :     return fastEmitInst_rr(ARM::VMAXNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3625             :   }
    3626             :   return 0;
    3627             : }
    3628             : 
    3629           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3630           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3631             :     return 0;
    3632           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3633           0 :     return fastEmitInst_rr(ARM::VMAXNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3634             :   }
    3635             :   return 0;
    3636             : }
    3637             : 
    3638           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3639           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3640             :     return 0;
    3641           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3642           0 :     return fastEmitInst_rr(ARM::VMAXNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3643             :   }
    3644             :   return 0;
    3645             : }
    3646             : 
    3647           0 : unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3648           0 :   switch (VT.SimpleTy) {
    3649           0 :   case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3650           0 :   case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3651           0 :   case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3652           0 :   case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3653           0 :   case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3654           0 :   case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3655             :   default: return 0;
    3656             :   }
    3657             : }
    3658             : 
    3659             : // FastEmit functions for ISD::FMINNAN.
    3660             : 
    3661           0 : unsigned fastEmit_ISD_FMINNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3662           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3663             :     return 0;
    3664           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3665           0 :     return fastEmitInst_rr(ARM::VMINhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3666             :   }
    3667             :   return 0;
    3668             : }
    3669             : 
    3670           0 : unsigned fastEmit_ISD_FMINNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3671           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3672             :     return 0;
    3673           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3674           0 :     return fastEmitInst_rr(ARM::VMINhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3675             :   }
    3676             :   return 0;
    3677             : }
    3678             : 
    3679             : unsigned fastEmit_ISD_FMINNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3680           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3681             :     return 0;
    3682           0 :   if ((Subtarget->hasNEON())) {
    3683           0 :     return fastEmitInst_rr(ARM::VMINfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3684             :   }
    3685             :   return 0;
    3686             : }
    3687             : 
    3688             : unsigned fastEmit_ISD_FMINNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3689           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3690             :     return 0;
    3691           0 :   if ((Subtarget->hasNEON())) {
    3692           0 :     return fastEmitInst_rr(ARM::VMINfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3693             :   }
    3694             :   return 0;
    3695             : }
    3696             : 
    3697           0 : unsigned fastEmit_ISD_FMINNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3698           0 :   switch (VT.SimpleTy) {
    3699           0 :   case MVT::v4f16: return fastEmit_ISD_FMINNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3700           0 :   case MVT::v8f16: return fastEmit_ISD_FMINNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3701           0 :   case MVT::v2f32: return fastEmit_ISD_FMINNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3702           0 :   case MVT::v4f32: return fastEmit_ISD_FMINNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3703             :   default: return 0;
    3704             :   }
    3705             : }
    3706             : 
    3707             : // FastEmit functions for ISD::FMINNUM.
    3708             : 
    3709             : unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3710           0 :   if (RetVT.SimpleTy != MVT::f32)
    3711             :     return 0;
    3712           0 :   if ((Subtarget->hasFPARMv8())) {
    3713           0 :     return fastEmitInst_rr(ARM::VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3714             :   }
    3715             :   return 0;
    3716             : }
    3717             : 
    3718           0 : unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3719           0 :   if (RetVT.SimpleTy != MVT::f64)
    3720             :     return 0;
    3721           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    3722           0 :     return fastEmitInst_rr(ARM::VMINNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3723             :   }
    3724             :   return 0;
    3725             : }
    3726             : 
    3727           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3728           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3729             :     return 0;
    3730           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3731           0 :     return fastEmitInst_rr(ARM::VMINNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3732             :   }
    3733             :   return 0;
    3734             : }
    3735             : 
    3736           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3737           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3738             :     return 0;
    3739           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3740           0 :     return fastEmitInst_rr(ARM::VMINNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3741             :   }
    3742             :   return 0;
    3743             : }
    3744             : 
    3745           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3746           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3747             :     return 0;
    3748           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3749           0 :     return fastEmitInst_rr(ARM::VMINNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3750             :   }
    3751             :   return 0;
    3752             : }
    3753             : 
    3754           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3755           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3756             :     return 0;
    3757           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3758           0 :     return fastEmitInst_rr(ARM::VMINNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3759             :   }
    3760             :   return 0;
    3761             : }
    3762             : 
    3763           0 : unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3764           0 :   switch (VT.SimpleTy) {
    3765           0 :   case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3766           0 :   case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3767           0 :   case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3768           0 :   case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3769           0 :   case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3770           0 :   case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3771             :   default: return 0;
    3772             :   }
    3773             : }
    3774             : 
    3775             : // FastEmit functions for ISD::FMUL.
    3776             : 
    3777           1 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3778           1 :   if (RetVT.SimpleTy != MVT::f32)
    3779             :     return 0;
    3780           2 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    3781           1 :     return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3782             :   }
    3783             :   return 0;
    3784             : }
    3785             : 
    3786           0 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3787           0 :   if (RetVT.SimpleTy != MVT::f64)
    3788             :     return 0;
    3789           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3790           0 :     return fastEmitInst_rr(ARM::VMULD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3791             :   }
    3792             :   return 0;
    3793             : }
    3794             : 
    3795           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3796           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3797             :     return 0;
    3798           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3799           0 :     return fastEmitInst_rr(ARM::VMULhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3800             :   }
    3801             :   return 0;
    3802             : }
    3803             : 
    3804           0 : unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3805           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3806             :     return 0;
    3807           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3808           0 :     return fastEmitInst_rr(ARM::VMULhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3809             :   }
    3810             :   return 0;
    3811             : }
    3812             : 
    3813             : unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3814           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3815             :     return 0;
    3816           0 :   if ((Subtarget->hasNEON())) {
    3817           0 :     return fastEmitInst_rr(ARM::VMULfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3818             :   }
    3819             :   return 0;
    3820             : }
    3821             : 
    3822             : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3823           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3824             :     return 0;
    3825           0 :   if ((Subtarget->hasNEON())) {
    3826           0 :     return fastEmitInst_rr(ARM::VMULfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3827             :   }
    3828             :   return 0;
    3829             : }
    3830             : 
    3831           1 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3832           1 :   switch (VT.SimpleTy) {
    3833           1 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3834           0 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3835           0 :   case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3836           0 :   case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3837           0 :   case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3838           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3839             :   default: return 0;
    3840             :   }
    3841             : }
    3842             : 
    3843             : // FastEmit functions for ISD::FSUB.
    3844             : 
    3845           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3846           0 :   if (RetVT.SimpleTy != MVT::f32)
    3847             :     return 0;
    3848           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    3849           0 :     return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3850             :   }
    3851             :   return 0;
    3852             : }
    3853             : 
    3854           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3855           0 :   if (RetVT.SimpleTy != MVT::f64)
    3856             :     return 0;
    3857           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3858           0 :     return fastEmitInst_rr(ARM::VSUBD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3859             :   }
    3860             :   return 0;
    3861             : }
    3862             : 
    3863           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3864           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3865             :     return 0;
    3866           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3867           0 :     return fastEmitInst_rr(ARM::VSUBhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3868             :   }
    3869             :   return 0;
    3870             : }
    3871             : 
    3872           0 : unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3873           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3874             :     return 0;
    3875           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3876           0 :     return fastEmitInst_rr(ARM::VSUBhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3877             :   }
    3878             :   return 0;
    3879             : }
    3880             : 
    3881             : unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3882           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3883             :     return 0;
    3884           0 :   if ((Subtarget->hasNEON())) {
    3885           0 :     return fastEmitInst_rr(ARM::VSUBfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3886             :   }
    3887             :   return 0;
    3888             : }
    3889             : 
    3890             : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3891           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3892             :     return 0;
    3893           0 :   if ((Subtarget->hasNEON())) {
    3894           0 :     return fastEmitInst_rr(ARM::VSUBfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3895             :   }
    3896             :   return 0;
    3897             : }
    3898             : 
    3899           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3900           0 :   switch (VT.SimpleTy) {
    3901           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3902           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3903           0 :   case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3904           0 :   case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3905           0 :   case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3906           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3907             :   default: return 0;
    3908             :   }
    3909             : }
    3910             : 
    3911             : // FastEmit functions for ISD::MUL.
    3912             : 
    3913           3 : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3914           3 :   if (RetVT.SimpleTy != MVT::i32)
    3915             :     return 0;
    3916           3 :   if ((Subtarget->isThumb2())) {
    3917           3 :     return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3918             :   }
    3919           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    3920           0 :     return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3921             :   }
    3922           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV6Ops()) && (Subtarget->useMulOps())) {
    3923           0 :     return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3924             :   }
    3925           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    3926           0 :     return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3927             :   }
    3928             :   return 0;
    3929             : }
    3930             : 
    3931             : unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3932           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3933             :     return 0;
    3934           0 :   if ((Subtarget->hasNEON())) {
    3935           0 :     return fastEmitInst_rr(ARM::VMULv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3936             :   }
    3937             :   return 0;
    3938             : }
    3939             : 
    3940             : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3941           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3942             :     return 0;
    3943           0 :   if ((Subtarget->hasNEON())) {
    3944           0 :     return fastEmitInst_rr(ARM::VMULv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3945             :   }
    3946             :   return 0;
    3947             : }
    3948             : 
    3949             : unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3950           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3951             :     return 0;
    3952           0 :   if ((Subtarget->hasNEON())) {
    3953           0 :     return fastEmitInst_rr(ARM::VMULv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3954             :   }
    3955             :   return 0;
    3956             : }
    3957             : 
    3958             : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3959           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3960             :     return 0;
    3961           0 :   if ((Subtarget->hasNEON())) {
    3962           0 :     return fastEmitInst_rr(ARM::VMULv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3963             :   }
    3964             :   return 0;
    3965             : }
    3966             : 
    3967             : unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3968           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3969             :     return 0;
    3970           0 :   if ((Subtarget->hasNEON())) {
    3971           0 :     return fastEmitInst_rr(ARM::VMULv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3972             :   }
    3973             :   return 0;
    3974             : }
    3975             : 
    3976             : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3977           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3978             :     return 0;
    3979           0 :   if ((Subtarget->hasNEON())) {
    3980           0 :     return fastEmitInst_rr(ARM::VMULv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3981             :   }
    3982             :   return 0;
    3983             : }
    3984             : 
    3985           3 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3986           3 :   switch (VT.SimpleTy) {
    3987           3 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3988           0 :   case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3989           0 :   case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3990           0 :   case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3991           0 :   case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3992           0 :   case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3993           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3994             :   default: return 0;
    3995             :   }
    3996             : }
    3997             : 
    3998             : // FastEmit functions for ISD::MULHS.
    3999             : 
    4000           0 : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4001           0 :   if (RetVT.SimpleTy != MVT::i32)
    4002             :     return 0;
    4003           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    4004           0 :     return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4005             :   }
    4006           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    4007           0 :     return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4008             :   }
    4009             :   return 0;
    4010             : }
    4011             : 
    4012             : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4013           0 :   switch (VT.SimpleTy) {
    4014           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4015             :   default: return 0;
    4016             :   }
    4017             : }
    4018             : 
    4019             : // FastEmit functions for ISD::OR.
    4020             : 
    4021           3 : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4022           3 :   if (RetVT.SimpleTy != MVT::i32)
    4023             :     return 0;
    4024           3 :   if ((Subtarget->isThumb2())) {
    4025           1 :     return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4026             :   }
    4027           2 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4028           0 :     return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4029             :   }
    4030           2 :   if ((!Subtarget->isThumb())) {
    4031           2 :     return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4032             :   }
    4033             :   return 0;
    4034             : }
    4035             : 
    4036             : unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4037           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4038             :     return 0;
    4039           0 :   if ((Subtarget->hasNEON())) {
    4040           0 :     return fastEmitInst_rr(ARM::VORRd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4041             :   }
    4042             :   return 0;
    4043             : }
    4044             : 
    4045             : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4046           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4047             :     return 0;
    4048           0 :   if ((Subtarget->hasNEON())) {
    4049           0 :     return fastEmitInst_rr(ARM::VORRq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4050             :   }
    4051             :   return 0;
    4052             : }
    4053             : 
    4054           3 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4055           3 :   switch (VT.SimpleTy) {
    4056           3 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4057           0 :   case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4058           0 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4059             :   default: return 0;
    4060             :   }
    4061             : }
    4062             : 
    4063             : // FastEmit functions for ISD::ROTR.
    4064             : 
    4065           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4066           0 :   if (RetVT.SimpleTy != MVT::i32)
    4067             :     return 0;
    4068           0 :   if ((Subtarget->isThumb2())) {
    4069           0 :     return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4070             :   }
    4071           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4072           0 :     return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4073             :   }
    4074             :   return 0;
    4075             : }
    4076             : 
    4077             : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4078           0 :   switch (VT.SimpleTy) {
    4079           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4080             :   default: return 0;
    4081             :   }
    4082             : }
    4083             : 
    4084             : // FastEmit functions for ISD::SDIV.
    4085             : 
    4086           4 : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4087           4 :   if (RetVT.SimpleTy != MVT::i32)
    4088             :     return 0;
    4089           4 :   if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) {
    4090           0 :     return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4091             :   }
    4092           4 :   if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) {
    4093           0 :     return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4094             :   }
    4095             :   return 0;
    4096             : }
    4097             : 
    4098             : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4099           4 :   switch (VT.SimpleTy) {
    4100           4 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4101             :   default: return 0;
    4102             :   }
    4103             : }
    4104             : 
    4105             : // FastEmit functions for ISD::SHL.
    4106             : 
    4107           5 : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4108           5 :   if (RetVT.SimpleTy != MVT::i32)
    4109             :     return 0;
    4110           5 :   if ((Subtarget->isThumb2())) {
    4111           0 :     return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4112             :   }
    4113           5 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4114           0 :     return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4115             :   }
    4116             :   return 0;
    4117             : }
    4118             : 
    4119             : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4120           5 :   switch (VT.SimpleTy) {
    4121           5 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4122             :   default: return 0;
    4123             :   }
    4124             : }
    4125             : 
    4126             : // FastEmit functions for ISD::SMAX.
    4127             : 
    4128             : unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4129           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4130             :     return 0;
    4131           0 :   if ((Subtarget->hasNEON())) {
    4132           0 :     return fastEmitInst_rr(ARM::VMAXsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4133             :   }
    4134             :   return 0;
    4135             : }
    4136             : 
    4137             : unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4138           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4139             :     return 0;
    4140           0 :   if ((Subtarget->hasNEON())) {
    4141           0 :     return fastEmitInst_rr(ARM::VMAXsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4142             :   }
    4143             :   return 0;
    4144             : }
    4145             : 
    4146             : unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4147           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4148             :     return 0;
    4149           0 :   if ((Subtarget->hasNEON())) {
    4150           0 :     return fastEmitInst_rr(ARM::VMAXsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4151             :   }
    4152             :   return 0;
    4153             : }
    4154             : 
    4155             : unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4156           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4157             :     return 0;
    4158           0 :   if ((Subtarget->hasNEON())) {
    4159           0 :     return fastEmitInst_rr(ARM::VMAXsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4160             :   }
    4161             :   return 0;
    4162             : }
    4163             : 
    4164             : unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4165           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4166             :     return 0;
    4167           0 :   if ((Subtarget->hasNEON())) {
    4168           0 :     return fastEmitInst_rr(ARM::VMAXsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4169             :   }
    4170             :   return 0;
    4171             : }
    4172             : 
    4173             : unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4174           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4175             :     return 0;
    4176           0 :   if ((Subtarget->hasNEON())) {
    4177           0 :     return fastEmitInst_rr(ARM::VMAXsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4178             :   }
    4179             :   return 0;
    4180             : }
    4181             : 
    4182           0 : unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4183           0 :   switch (VT.SimpleTy) {
    4184           0 :   case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4185           0 :   case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4186           0 :   case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4187           0 :   case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4188           0 :   case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4189           0 :   case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4190             :   default: return 0;
    4191             :   }
    4192             : }
    4193             : 
    4194             : // FastEmit functions for ISD::SMIN.
    4195             : 
    4196             : unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4197           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4198             :     return 0;
    4199           0 :   if ((Subtarget->hasNEON())) {
    4200           0 :     return fastEmitInst_rr(ARM::VMINsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4201             :   }
    4202             :   return 0;
    4203             : }
    4204             : 
    4205             : unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4206           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4207             :     return 0;
    4208           0 :   if ((Subtarget->hasNEON())) {
    4209           0 :     return fastEmitInst_rr(ARM::VMINsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4210             :   }
    4211             :   return 0;
    4212             : }
    4213             : 
    4214             : unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4215           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4216             :     return 0;
    4217           0 :   if ((Subtarget->hasNEON())) {
    4218           0 :     return fastEmitInst_rr(ARM::VMINsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4219             :   }
    4220             :   return 0;
    4221             : }
    4222             : 
    4223             : unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4224           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4225             :     return 0;
    4226           0 :   if ((Subtarget->hasNEON())) {
    4227           0 :     return fastEmitInst_rr(ARM::VMINsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4228             :   }
    4229             :   return 0;
    4230             : }
    4231             : 
    4232             : unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4233           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4234             :     return 0;
    4235           0 :   if ((Subtarget->hasNEON())) {
    4236           0 :     return fastEmitInst_rr(ARM::VMINsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4237             :   }
    4238             :   return 0;
    4239             : }
    4240             : 
    4241             : unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4242           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4243             :     return 0;
    4244           0 :   if ((Subtarget->hasNEON())) {
    4245           0 :     return fastEmitInst_rr(ARM::VMINsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4246             :   }
    4247             :   return 0;
    4248             : }
    4249             : 
    4250           0 : unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4251           0 :   switch (VT.SimpleTy) {
    4252           0 :   case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4253           0 :   case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4254           0 :   case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4255           0 :   case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4256           0 :   case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4257           0 :   case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4258             :   default: return 0;
    4259             :   }
    4260             : }
    4261             : 
    4262             : // FastEmit functions for ISD::SRA.
    4263             : 
    4264           4 : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4265           4 :   if (RetVT.SimpleTy != MVT::i32)
    4266             :     return 0;
    4267           4 :   if ((Subtarget->isThumb2())) {
    4268           0 :     return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4269             :   }
    4270           4 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4271           0 :     return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4272             :   }
    4273             :   return 0;
    4274             : }
    4275             : 
    4276             : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4277           4 :   switch (VT.SimpleTy) {
    4278           4 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4279             :   default: return 0;
    4280             :   }
    4281             : }
    4282             : 
    4283             : // FastEmit functions for ISD::SRL.
    4284             : 
    4285           6 : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4286           6 :   if (RetVT.SimpleTy != MVT::i32)
    4287             :     return 0;
    4288           6 :   if ((Subtarget->isThumb2())) {
    4289           2 :     return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4290             :   }
    4291           4 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4292           0 :     return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4293             :   }
    4294             :   return 0;
    4295             : }
    4296             : 
    4297             : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4298           6 :   switch (VT.SimpleTy) {
    4299           6 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4300             :   default: return 0;
    4301             :   }
    4302             : }
    4303             : 
    4304             : // FastEmit functions for ISD::SUB.
    4305             : 
    4306           3 : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4307           3 :   if (RetVT.SimpleTy != MVT::i32)
    4308             :     return 0;
    4309           3 :   if ((Subtarget->isThumb2())) {
    4310           1 :     return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4311             :   }
    4312           2 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4313           0 :     return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4314             :   }
    4315           2 :   if ((!Subtarget->isThumb())) {
    4316           2 :     return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4317             :   }
    4318             :   return 0;
    4319             : }
    4320             : 
    4321             : unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4322           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4323             :     return 0;
    4324           0 :   if ((Subtarget->hasNEON())) {
    4325           0 :     return fastEmitInst_rr(ARM::VSUBv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4326             :   }
    4327             :   return 0;
    4328             : }
    4329             : 
    4330             : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4331           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4332             :     return 0;
    4333           0 :   if ((Subtarget->hasNEON())) {
    4334           0 :     return fastEmitInst_rr(ARM::VSUBv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4335             :   }
    4336             :   return 0;
    4337             : }
    4338             : 
    4339             : unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4340           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4341             :     return 0;
    4342           0 :   if ((Subtarget->hasNEON())) {
    4343           0 :     return fastEmitInst_rr(ARM::VSUBv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4344             :   }
    4345             :   return 0;
    4346             : }
    4347             : 
    4348             : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4349           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4350             :     return 0;
    4351           0 :   if ((Subtarget->hasNEON())) {
    4352           0 :     return fastEmitInst_rr(ARM::VSUBv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4353             :   }
    4354             :   return 0;
    4355             : }
    4356             : 
    4357             : unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4358           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4359             :     return 0;
    4360           0 :   if ((Subtarget->hasNEON())) {
    4361           0 :     return fastEmitInst_rr(ARM::VSUBv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4362             :   }
    4363             :   return 0;
    4364             : }
    4365             : 
    4366             : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4367           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4368             :     return 0;
    4369           0 :   if ((Subtarget->hasNEON())) {
    4370           0 :     return fastEmitInst_rr(ARM::VSUBv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4371             :   }
    4372             :   return 0;
    4373             : }
    4374             : 
    4375             : unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4376           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    4377             :     return 0;
    4378           0 :   if ((Subtarget->hasNEON())) {
    4379           0 :     return fastEmitInst_rr(ARM::VSUBv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4380             :   }
    4381             :   return 0;
    4382             : }
    4383             : 
    4384             : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4385           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    4386             :     return 0;
    4387           0 :   if ((Subtarget->hasNEON())) {
    4388           0 :     return fastEmitInst_rr(ARM::VSUBv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4389             :   }
    4390             :   return 0;
    4391             : }
    4392             : 
    4393           3 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4394           3 :   switch (VT.SimpleTy) {
    4395           3 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4396           0 :   case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4397           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4398           0 :   case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4399           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4400           0 :   case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4401           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4402           0 :   case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4403           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4404             :   default: return 0;
    4405             :   }
    4406             : }
    4407             : 
    4408             : // FastEmit functions for ISD::UDIV.
    4409             : 
    4410          10 : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4411          10 :   if (RetVT.SimpleTy != MVT::i32)
    4412             :     return 0;
    4413          10 :   if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) {
    4414           0 :     return fastEmitInst_rr(ARM::t2UDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4415             :   }
    4416          10 :   if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) {
    4417           0 :     return fastEmitInst_rr(ARM::UDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4418             :   }
    4419             :   return 0;
    4420             : }
    4421             : 
    4422             : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4423          10 :   switch (VT.SimpleTy) {
    4424          10 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4425             :   default: return 0;
    4426             :   }
    4427             : }
    4428             : 
    4429             : // FastEmit functions for ISD::UMAX.
    4430             : 
    4431             : unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4432           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4433             :     return 0;
    4434           0 :   if ((Subtarget->hasNEON())) {
    4435           0 :     return fastEmitInst_rr(ARM::VMAXuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4436             :   }
    4437             :   return 0;
    4438             : }
    4439             : 
    4440             : unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4441           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4442             :     return 0;
    4443           0 :   if ((Subtarget->hasNEON())) {
    4444           0 :     return fastEmitInst_rr(ARM::VMAXuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4445             :   }
    4446             :   return 0;
    4447             : }
    4448             : 
    4449             : unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4450           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4451             :     return 0;
    4452           0 :   if ((Subtarget->hasNEON())) {
    4453           0 :     return fastEmitInst_rr(ARM::VMAXuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4454             :   }
    4455             :   return 0;
    4456             : }
    4457             : 
    4458             : unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4459           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4460             :     return 0;
    4461           0 :   if ((Subtarget->hasNEON())) {
    4462           0 :     return fastEmitInst_rr(ARM::VMAXuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4463             :   }
    4464             :   return 0;
    4465             : }
    4466             : 
    4467             : unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4468           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4469             :     return 0;
    4470           0 :   if ((Subtarget->hasNEON())) {
    4471           0 :     return fastEmitInst_rr(ARM::VMAXuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4472             :   }
    4473             :   return 0;
    4474             : }
    4475             : 
    4476             : unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4477           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4478             :     return 0;
    4479           0 :   if ((Subtarget->hasNEON())) {
    4480           0 :     return fastEmitInst_rr(ARM::VMAXuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4481             :   }
    4482             :   return 0;
    4483             : }
    4484             : 
    4485           0 : unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4486           0 :   switch (VT.SimpleTy) {
    4487           0 :   case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4488           0 :   case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4489           0 :   case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4490           0 :   case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4491           0 :   case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4492           0 :   case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4493             :   default: return 0;
    4494             :   }
    4495             : }
    4496             : 
    4497             : // FastEmit functions for ISD::UMIN.
    4498             : 
    4499             : unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4500           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4501             :     return 0;
    4502           0 :   if ((Subtarget->hasNEON())) {
    4503           0 :     return fastEmitInst_rr(ARM::VMINuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4504             :   }
    4505             :   return 0;
    4506             : }
    4507             : 
    4508             : unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4509           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4510             :     return 0;
    4511           0 :   if ((Subtarget->hasNEON())) {
    4512           0 :     return fastEmitInst_rr(ARM::VMINuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4513             :   }
    4514             :   return 0;
    4515             : }
    4516             : 
    4517             : unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4518           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4519             :     return 0;
    4520           0 :   if ((Subtarget->hasNEON())) {
    4521           0 :     return fastEmitInst_rr(ARM::VMINuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4522             :   }
    4523             :   return 0;
    4524             : }
    4525             : 
    4526             : unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4527           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4528             :     return 0;
    4529           0 :   if ((Subtarget->hasNEON())) {
    4530           0 :     return fastEmitInst_rr(ARM::VMINuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4531             :   }
    4532             :   return 0;
    4533             : }
    4534             : 
    4535             : unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4536           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4537             :     return 0;
    4538           0 :   if ((Subtarget->hasNEON())) {
    4539           0 :     return fastEmitInst_rr(ARM::VMINuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4540             :   }
    4541             :   return 0;
    4542             : }
    4543             : 
    4544             : unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4545           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4546             :     return 0;
    4547           0 :   if ((Subtarget->hasNEON())) {
    4548           0 :     return fastEmitInst_rr(ARM::VMINuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4549             :   }
    4550             :   return 0;
    4551             : }
    4552             : 
    4553           0 : unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4554           0 :   switch (VT.SimpleTy) {
    4555           0 :   case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4556           0 :   case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4557           0 :   case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4558           0 :   case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4559           0 :   case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4560           0 :   case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4561             :   default: return 0;
    4562             :   }
    4563             : }
    4564             : 
    4565             : // FastEmit functions for ISD::XOR.
    4566             : 
    4567          11 : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4568          11 :   if (RetVT.SimpleTy != MVT::i32)
    4569             :     return 0;
    4570          11 :   if ((Subtarget->isThumb2())) {
    4571           8 :     return fastEmitInst_rr(ARM::t2EORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4572             :   }
    4573           3 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4574           0 :     return fastEmitInst_rr(ARM::tEOR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4575             :   }
    4576           3 :   if ((!Subtarget->isThumb())) {
    4577           3 :     return fastEmitInst_rr(ARM::EORrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4578             :   }
    4579             :   return 0;
    4580             : }
    4581             : 
    4582             : unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4583           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4584             :     return 0;
    4585           0 :   if ((Subtarget->hasNEON())) {
    4586           0 :     return fastEmitInst_rr(ARM::VEORd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4587             :   }
    4588             :   return 0;
    4589             : }
    4590             : 
    4591             : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4592           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4593             :     return 0;
    4594           0 :   if ((Subtarget->hasNEON())) {
    4595           0 :     return fastEmitInst_rr(ARM::VEORq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4596             :   }
    4597             :   return 0;
    4598             : }
    4599             : 
    4600          11 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4601          11 :   switch (VT.SimpleTy) {
    4602          11 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4603           0 :   case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4604           0 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4605             :   default: return 0;
    4606             :   }
    4607             : }
    4608             : 
    4609             : // Top-level FastEmit function.
    4610             : 
    4611         211 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    4612         211 :   switch (Opcode) {
    4613           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4614           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4615           0 :   case ARMISD::EH_SJLJ_LONGJMP: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4616           0 :   case ARMISD::EH_SJLJ_SETJMP: return fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4617           0 :   case ARMISD::SMULWB: return fastEmit_ARMISD_SMULWB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4618           0 :   case ARMISD::SMULWT: return fastEmit_ARMISD_SMULWT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4619           0 :   case ARMISD::VCEQ: return fastEmit_ARMISD_VCEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4620           0 :   case ARMISD::VCGE: return fastEmit_ARMISD_VCGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4621           0 :   case ARMISD::VCGEU: return fastEmit_ARMISD_VCGEU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4622           0 :   case ARMISD::VCGT: return fastEmit_ARMISD_VCGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4623           0 :   case ARMISD::VCGTU: return fastEmit_ARMISD_VCGTU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4624           0 :   case ARMISD::VMOVDRR: return fastEmit_ARMISD_VMOVDRR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4625           0 :   case ARMISD::VMULLs: return fastEmit_ARMISD_VMULLs_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4626           0 :   case ARMISD::VMULLu: return fastEmit_ARMISD_VMULLu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4627           0 :   case ARMISD::VTBL1: return fastEmit_ARMISD_VTBL1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4628           0 :   case ARMISD::VTST: return fastEmit_ARMISD_VTST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4629          96 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4630           0 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4631          33 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4632           0 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4633           0 :   case ISD::FMAXNAN: return fastEmit_ISD_FMAXNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4634           0 :   case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4635           0 :   case ISD::FMINNAN: return fastEmit_ISD_FMINNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4636           0 :   case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4637           1 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4638           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4639           3 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4640           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4641           3 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4642           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4643           4 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4644           5 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4645           0 :   case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4646           0 :   case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4647           4 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4648           6 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4649           3 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4650          10 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4651           0 :   case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4652           0 :   case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4653          11 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4654             :   default: return 0;
    4655             :   }
    4656             : }
    4657             : 
    4658             : // FastEmit functions for ARMISD::PIC_ADD.
    4659             : 
    4660           0 : unsigned fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4661           0 :   if (RetVT.SimpleTy != MVT::i32)
    4662             :     return 0;
    4663           0 :   if ((Subtarget->isThumb())) {
    4664           0 :     return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4665             :   }
    4666           0 :   if ((!Subtarget->isThumb())) {
    4667           0 :     return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4668             :   }
    4669             :   return 0;
    4670             : }
    4671             : 
    4672             : unsigned fastEmit_ARMISD_PIC_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4673           0 :   switch (VT.SimpleTy) {
    4674           0 :   case MVT::i32: return fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4675             :   default: return 0;
    4676             :   }
    4677             : }
    4678             : 
    4679             : // FastEmit functions for ARMISD::VDUPLANE.
    4680             : 
    4681             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4682           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4683             :     return 0;
    4684           0 :   if ((Subtarget->hasNEON())) {
    4685           0 :     return fastEmitInst_ri(ARM::VDUPLN8d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4686             :   }
    4687             :   return 0;
    4688             : }
    4689             : 
    4690             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4691           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4692             :     return 0;
    4693           0 :   if ((Subtarget->hasNEON())) {
    4694           0 :     return fastEmitInst_ri(ARM::VDUPLN16d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4695             :   }
    4696             :   return 0;
    4697             : }
    4698             : 
    4699             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4700           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4701             :     return 0;
    4702           0 :   if ((Subtarget->hasNEON())) {
    4703           0 :     return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4704             :   }
    4705             :   return 0;
    4706             : }
    4707             : 
    4708             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4709           0 :   return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4710             : }
    4711             : 
    4712             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4713           0 :   return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4714             : }
    4715             : 
    4716           0 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4717           0 : switch (RetVT.SimpleTy) {
    4718           0 :   case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(Op0, Op0IsKill, imm1);
    4719           0 :   case MVT::v4f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(Op0, Op0IsKill, imm1);
    4720             :   default: return 0;
    4721             : }
    4722             : }
    4723             : 
    4724           0 : unsigned fastEmit_ARMISD_VDUPLANE_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4725           0 :   switch (VT.SimpleTy) {
    4726           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4727           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4728           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4729           0 :   case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(RetVT, Op0, Op0IsKill, imm1);
    4730             :   default: return 0;
    4731             :   }
    4732             : }
    4733             : 
    4734             : // FastEmit functions for ARMISD::VGETLANEs.
    4735             : 
    4736             : unsigned fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4737           0 :   if (RetVT.SimpleTy != MVT::i32)
    4738             :     return 0;
    4739           0 :   if ((Subtarget->hasNEON())) {
    4740           0 :     return fastEmitInst_ri(ARM::VGETLNs8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4741             :   }
    4742             :   return 0;
    4743             : }
    4744             : 
    4745             : unsigned fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4746           0 :   if (RetVT.SimpleTy != MVT::i32)
    4747             :     return 0;
    4748           0 :   if ((Subtarget->hasNEON())) {
    4749           0 :     return fastEmitInst_ri(ARM::VGETLNs16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4750             :   }
    4751             :   return 0;
    4752             : }
    4753             : 
    4754           0 : unsigned fastEmit_ARMISD_VGETLANEs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4755           0 :   switch (VT.SimpleTy) {
    4756           0 :   case MVT::v8i8: return fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4757           0 :   case MVT::v4i16: return fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4758             :   default: return 0;
    4759             :   }
    4760             : }
    4761             : 
    4762             : // FastEmit functions for ARMISD::VGETLANEu.
    4763             : 
    4764             : unsigned fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4765           0 :   if (RetVT.SimpleTy != MVT::i32)
    4766             :     return 0;
    4767           0 :   if ((Subtarget->hasNEON())) {
    4768           0 :     return fastEmitInst_ri(ARM::VGETLNu8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4769             :   }
    4770             :   return 0;
    4771             : }
    4772             : 
    4773             : unsigned fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4774           0 :   if (RetVT.SimpleTy != MVT::i32)
    4775             :     return 0;
    4776           0 :   if ((Subtarget->hasNEON())) {
    4777           0 :     return fastEmitInst_ri(ARM::VGETLNu16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4778             :   }
    4779             :   return 0;
    4780             : }
    4781             : 
    4782           0 : unsigned fastEmit_ARMISD_VGETLANEu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4783           0 :   switch (VT.SimpleTy) {
    4784           0 :   case MVT::v8i8: return fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4785           0 :   case MVT::v4i16: return fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4786             :   default: return 0;
    4787             :   }
    4788             : }
    4789             : 
    4790             : // FastEmit functions for ARMISD::VQSHLs.
    4791             : 
    4792             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4793           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4794             :     return 0;
    4795           0 :   if ((Subtarget->hasNEON())) {
    4796           0 :     return fastEmitInst_ri(ARM::VQSHLsiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4797             :   }
    4798             :   return 0;
    4799             : }
    4800             : 
    4801             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4802           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4803             :     return 0;
    4804           0 :   if ((Subtarget->hasNEON())) {
    4805           0 :     return fastEmitInst_ri(ARM::VQSHLsiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4806             :   }
    4807             :   return 0;
    4808             : }
    4809             : 
    4810             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4811           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4812             :     return 0;
    4813           0 :   if ((Subtarget->hasNEON())) {
    4814           0 :     return fastEmitInst_ri(ARM::VQSHLsiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4815             :   }
    4816             :   return 0;
    4817             : }
    4818             : 
    4819             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4820           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4821             :     return 0;
    4822           0 :   if ((Subtarget->hasNEON())) {
    4823           0 :     return fastEmitInst_ri(ARM::VQSHLsiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4824             :   }
    4825             :   return 0;
    4826             : }
    4827             : 
    4828             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4829           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4830             :     return 0;
    4831           0 :   if ((Subtarget->hasNEON())) {
    4832           0 :     return fastEmitInst_ri(ARM::VQSHLsiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4833             :   }
    4834             :   return 0;
    4835             : }
    4836             : 
    4837             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4838           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4839             :     return 0;
    4840           0 :   if ((Subtarget->hasNEON())) {
    4841           0 :     return fastEmitInst_ri(ARM::VQSHLsiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4842             :   }
    4843             :   return 0;
    4844             : }
    4845             : 
    4846             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4847           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    4848             :     return 0;
    4849           0 :   if ((Subtarget->hasNEON())) {
    4850           0 :     return fastEmitInst_ri(ARM::VQSHLsiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4851             :   }
    4852             :   return 0;
    4853             : }
    4854             : 
    4855             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4856           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    4857             :     return 0;
    4858           0 :   if ((Subtarget->hasNEON())) {
    4859           0 :     return fastEmitInst_ri(ARM::VQSHLsiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4860             :   }
    4861             :   return 0;
    4862             : }
    4863             : 
    4864           0 : unsigned fastEmit_ARMISD_VQSHLs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4865           0 :   switch (VT.SimpleTy) {
    4866           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4867           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4868           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4869           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4870           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4871           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4872           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    4873           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    4874             :   default: return 0;
    4875             :   }
    4876             : }
    4877             : 
    4878             : // FastEmit functions for ARMISD::VQSHLsu.
    4879             : 
    4880             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4881           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4882             :     return 0;
    4883           0 :   if ((Subtarget->hasNEON())) {
    4884           0 :     return fastEmitInst_ri(ARM::VQSHLsuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4885             :   }
    4886             :   return 0;
    4887             : }
    4888             : 
    4889             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4890           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4891             :     return 0;
    4892           0 :   if ((Subtarget->hasNEON())) {
    4893           0 :     return fastEmitInst_ri(ARM::VQSHLsuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4894             :   }
    4895             :   return 0;
    4896             : }
    4897             : 
    4898             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4899           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4900             :     return 0;
    4901           0 :   if ((Subtarget->hasNEON())) {
    4902           0 :     return fastEmitInst_ri(ARM::VQSHLsuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4903             :   }
    4904             :   return 0;
    4905             : }
    4906             : 
    4907             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4908           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4909             :     return 0;
    4910           0 :   if ((Subtarget->hasNEON())) {
    4911           0 :     return fastEmitInst_ri(ARM::VQSHLsuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4912             :   }
    4913             :   return 0;
    4914             : }
    4915             : 
    4916             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4917           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4918             :     return 0;
    4919           0 :   if ((Subtarget->hasNEON())) {
    4920           0 :     return fastEmitInst_ri(ARM::VQSHLsuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4921             :   }
    4922             :   return 0;
    4923             : }
    4924             : 
    4925             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4926           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4927             :     return 0;
    4928           0 :   if ((Subtarget->hasNEON())) {
    4929           0 :     return fastEmitInst_ri(ARM::VQSHLsuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4930             :   }
    4931             :   return 0;
    4932             : }
    4933             : 
    4934             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4935           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    4936             :     return 0;
    4937           0 :   if ((Subtarget->hasNEON())) {
    4938           0 :     return fastEmitInst_ri(ARM::VQSHLsuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4939             :   }
    4940             :   return 0;
    4941             : }
    4942             : 
    4943             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4944           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    4945             :     return 0;
    4946           0 :   if ((Subtarget->hasNEON())) {
    4947           0 :     return fastEmitInst_ri(ARM::VQSHLsuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4948             :   }
    4949             :   return 0;
    4950             : }
    4951             : 
    4952           0 : unsigned fastEmit_ARMISD_VQSHLsu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4953           0 :   switch (VT.SimpleTy) {
    4954           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4955           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4956           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4957           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4958           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4959           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4960           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    4961           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    4962             :   default: return 0;
    4963             :   }
    4964             : }
    4965             : 
    4966             : // FastEmit functions for ARMISD::VQSHLu.
    4967             : 
    4968             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4969           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4970             :     return 0;
    4971           0 :   if ((Subtarget->hasNEON())) {
    4972           0 :     return fastEmitInst_ri(ARM::VQSHLuiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4973             :   }
    4974             :   return 0;
    4975             : }
    4976             : 
    4977             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4978           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4979             :     return 0;
    4980           0 :   if ((Subtarget->hasNEON())) {
    4981           0 :     return fastEmitInst_ri(ARM::VQSHLuiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4982             :   }
    4983             :   return 0;
    4984             : }
    4985             : 
    4986             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4987           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4988             :     return 0;
    4989           0 :   if ((Subtarget->hasNEON())) {
    4990           0 :     return fastEmitInst_ri(ARM::VQSHLuiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4991             :   }
    4992             :   return 0;
    4993             : }
    4994             : 
    4995             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4996           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4997             :     return 0;
    4998           0 :   if ((Subtarget->hasNEON())) {
    4999           0 :     return fastEmitInst_ri(ARM::VQSHLuiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5000             :   }
    5001             :   return 0;
    5002             : }
    5003             : 
    5004             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5005           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5006             :     return 0;
    5007           0 :   if ((Subtarget->hasNEON())) {
    5008           0 :     return fastEmitInst_ri(ARM::VQSHLuiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5009             :   }
    5010             :   return 0;
    5011             : }
    5012             : 
    5013             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5014           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5015             :     return 0;
    5016           0 :   if ((Subtarget->hasNEON())) {
    5017           0 :     return fastEmitInst_ri(ARM::VQSHLuiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5018             :   }
    5019             :   return 0;
    5020             : }
    5021             : 
    5022             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5023           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5024             :     return 0;
    5025           0 :   if ((Subtarget->hasNEON())) {
    5026           0 :     return fastEmitInst_ri(ARM::VQSHLuiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5027             :   }
    5028             :   return 0;
    5029             : }
    5030             : 
    5031             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5032           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5033             :     return 0;
    5034           0 :   if ((Subtarget->hasNEON())) {
    5035           0 :     return fastEmitInst_ri(ARM::VQSHLuiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5036             :   }
    5037             :   return 0;
    5038             : }
    5039             : 
    5040           0 : unsigned fastEmit_ARMISD_VQSHLu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5041           0 :   switch (VT.SimpleTy) {
    5042           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5043           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5044           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5045           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5046           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5047           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5048           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5049           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5050             :   default: return 0;
    5051             :   }
    5052             : }
    5053             : 
    5054             : // FastEmit functions for ARMISD::VRSHRs.
    5055             : 
    5056             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5057           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5058             :     return 0;
    5059           0 :   if ((Subtarget->hasNEON())) {
    5060           0 :     return fastEmitInst_ri(ARM::VRSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5061             :   }
    5062             :   return 0;
    5063             : }
    5064             : 
    5065             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5066           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5067             :     return 0;
    5068           0 :   if ((Subtarget->hasNEON())) {
    5069           0 :     return fastEmitInst_ri(ARM::VRSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5070             :   }
    5071             :   return 0;
    5072             : }
    5073             : 
    5074             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5075           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5076             :     return 0;
    5077           0 :   if ((Subtarget->hasNEON())) {
    5078           0 :     return fastEmitInst_ri(ARM::VRSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5079             :   }
    5080             :   return 0;
    5081             : }
    5082             : 
    5083             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5084           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5085             :     return 0;
    5086           0 :   if ((Subtarget->hasNEON())) {
    5087           0 :     return fastEmitInst_ri(ARM::VRSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5088             :   }
    5089             :   return 0;
    5090             : }
    5091             : 
    5092             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5093           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5094             :     return 0;
    5095           0 :   if ((Subtarget->hasNEON())) {
    5096           0 :     return fastEmitInst_ri(ARM::VRSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5097             :   }
    5098             :   return 0;
    5099             : }
    5100             : 
    5101             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5102           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5103             :     return 0;
    5104           0 :   if ((Subtarget->hasNEON())) {
    5105           0 :     return fastEmitInst_ri(ARM::VRSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5106             :   }
    5107             :   return 0;
    5108             : }
    5109             : 
    5110             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5111           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5112             :     return 0;
    5113           0 :   if ((Subtarget->hasNEON())) {
    5114           0 :     return fastEmitInst_ri(ARM::VRSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5115             :   }
    5116             :   return 0;
    5117             : }
    5118             : 
    5119             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5120           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5121             :     return 0;
    5122           0 :   if ((Subtarget->hasNEON())) {
    5123           0 :     return fastEmitInst_ri(ARM::VRSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5124             :   }
    5125             :   return 0;
    5126             : }
    5127             : 
    5128           0 : unsigned fastEmit_ARMISD_VRSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5129           0 :   switch (VT.SimpleTy) {
    5130           0 :   case MVT::v8i8: return fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5131           0 :   case MVT::v16i8: return fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5132           0 :   case MVT::v4i16: return fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5133           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5134           0 :   case MVT::v2i32: return fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5135           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5136           0 :   case MVT::v1i64: return fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5137           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5138             :   default: return 0;
    5139             :   }
    5140             : }
    5141             : 
    5142             : // FastEmit functions for ARMISD::VRSHRu.
    5143             : 
    5144             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5145           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5146             :     return 0;
    5147           0 :   if ((Subtarget->hasNEON())) {
    5148           0 :     return fastEmitInst_ri(ARM::VRSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5149             :   }
    5150             :   return 0;
    5151             : }
    5152             : 
    5153             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5154           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5155             :     return 0;
    5156           0 :   if ((Subtarget->hasNEON())) {
    5157           0 :     return fastEmitInst_ri(ARM::VRSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5158             :   }
    5159             :   return 0;
    5160             : }
    5161             : 
    5162             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5163           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5164             :     return 0;
    5165           0 :   if ((Subtarget->hasNEON())) {
    5166           0 :     return fastEmitInst_ri(ARM::VRSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5167             :   }
    5168             :   return 0;
    5169             : }
    5170             : 
    5171             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5172           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5173             :     return 0;
    5174           0 :   if ((Subtarget->hasNEON())) {
    5175           0 :     return fastEmitInst_ri(ARM::VRSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5176             :   }
    5177             :   return 0;
    5178             : }
    5179             : 
    5180             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5181           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5182             :     return 0;
    5183           0 :   if ((Subtarget->hasNEON())) {
    5184           0 :     return fastEmitInst_ri(ARM::VRSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5185             :   }
    5186             :   return 0;
    5187             : }
    5188             : 
    5189             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5190           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5191             :     return 0;
    5192           0 :   if ((Subtarget->hasNEON())) {
    5193           0 :     return fastEmitInst_ri(ARM::VRSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5194             :   }
    5195             :   return 0;
    5196             : }
    5197             : 
    5198             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5199           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5200             :     return 0;
    5201           0 :   if ((Subtarget->hasNEON())) {
    5202           0 :     return fastEmitInst_ri(ARM::VRSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5203             :   }
    5204             :   return 0;
    5205             : }
    5206             : 
    5207             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5208           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5209             :     return 0;
    5210           0 :   if ((Subtarget->hasNEON())) {
    5211           0 :     return fastEmitInst_ri(ARM::VRSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5212             :   }
    5213             :   return 0;
    5214             : }
    5215             : 
    5216           0 : unsigned fastEmit_ARMISD_VRSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5217           0 :   switch (VT.SimpleTy) {
    5218           0 :   case MVT::v8i8: return fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5219           0 :   case MVT::v16i8: return fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5220           0 :   case MVT::v4i16: return fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5221           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5222           0 :   case MVT::v2i32: return fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5223           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5224           0 :   case MVT::v1i64: return fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5225           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5226             :   default: return 0;
    5227             :   }
    5228             : }
    5229             : 
    5230             : // FastEmit functions for ARMISD::VSHL.
    5231             : 
    5232             : unsigned fastEmit_ARMISD_VSHL_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5233           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5234             :     return 0;
    5235           0 :   if ((Subtarget->hasNEON())) {
    5236           0 :     return fastEmitInst_ri(ARM::VSHLiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5237             :   }
    5238             :   return 0;
    5239             : }
    5240             : 
    5241             : unsigned fastEmit_ARMISD_VSHL_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5242           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5243             :     return 0;
    5244           0 :   if ((Subtarget->hasNEON())) {
    5245           0 :     return fastEmitInst_ri(ARM::VSHLiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5246             :   }
    5247             :   return 0;
    5248             : }
    5249             : 
    5250             : unsigned fastEmit_ARMISD_VSHL_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5251           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5252             :     return 0;
    5253           0 :   if ((Subtarget->hasNEON())) {
    5254           0 :     return fastEmitInst_ri(ARM::VSHLiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5255             :   }
    5256             :   return 0;
    5257             : }
    5258             : 
    5259             : unsigned fastEmit_ARMISD_VSHL_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5260           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5261             :     return 0;
    5262           0 :   if ((Subtarget->hasNEON())) {
    5263           0 :     return fastEmitInst_ri(ARM::VSHLiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5264             :   }
    5265             :   return 0;
    5266             : }
    5267             : 
    5268             : unsigned fastEmit_ARMISD_VSHL_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5269           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5270             :     return 0;
    5271           0 :   if ((Subtarget->hasNEON())) {
    5272           0 :     return fastEmitInst_ri(ARM::VSHLiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5273             :   }
    5274             :   return 0;
    5275             : }
    5276             : 
    5277             : unsigned fastEmit_ARMISD_VSHL_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5278           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5279             :     return 0;
    5280           0 :   if ((Subtarget->hasNEON())) {
    5281           0 :     return fastEmitInst_ri(ARM::VSHLiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5282             :   }
    5283             :   return 0;
    5284             : }
    5285             : 
    5286             : unsigned fastEmit_ARMISD_VSHL_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5287           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5288             :     return 0;
    5289           0 :   if ((Subtarget->hasNEON())) {
    5290           0 :     return fastEmitInst_ri(ARM::VSHLiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5291             :   }
    5292             :   return 0;
    5293             : }
    5294             : 
    5295             : unsigned fastEmit_ARMISD_VSHL_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5296           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5297             :     return 0;
    5298           0 :   if ((Subtarget->hasNEON())) {
    5299           0 :     return fastEmitInst_ri(ARM::VSHLiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5300             :   }
    5301             :   return 0;
    5302             : }
    5303             : 
    5304           0 : unsigned fastEmit_ARMISD_VSHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5305           0 :   switch (VT.SimpleTy) {
    5306           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHL_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5307           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHL_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5308           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHL_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5309           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHL_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5310           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHL_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5311           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHL_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5312           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHL_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5313           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHL_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5314             :   default: return 0;
    5315             :   }
    5316             : }
    5317             : 
    5318             : // FastEmit functions for ARMISD::VSHRs.
    5319             : 
    5320             : unsigned fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5321           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5322             :     return 0;
    5323           0 :   if ((Subtarget->hasNEON())) {
    5324           0 :     return fastEmitInst_ri(ARM::VSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5325             :   }
    5326             :   return 0;
    5327             : }
    5328             : 
    5329             : unsigned fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5330           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5331             :     return 0;
    5332           0 :   if ((Subtarget->hasNEON())) {
    5333           0 :     return fastEmitInst_ri(ARM::VSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5334             :   }
    5335             :   return 0;
    5336             : }
    5337             : 
    5338             : unsigned fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5339           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5340             :     return 0;
    5341           0 :   if ((Subtarget->hasNEON())) {
    5342           0 :     return fastEmitInst_ri(ARM::VSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5343             :   }
    5344             :   return 0;
    5345             : }
    5346             : 
    5347             : unsigned fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5348           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5349             :     return 0;
    5350           0 :   if ((Subtarget->hasNEON())) {
    5351           0 :     return fastEmitInst_ri(ARM::VSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5352             :   }
    5353             :   return 0;
    5354             : }
    5355             : 
    5356             : unsigned fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5357           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5358             :     return 0;
    5359           0 :   if ((Subtarget->hasNEON())) {
    5360           0 :     return fastEmitInst_ri(ARM::VSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5361             :   }
    5362             :   return 0;
    5363             : }
    5364             : 
    5365             : unsigned fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5366           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5367             :     return 0;
    5368           0 :   if ((Subtarget->hasNEON())) {
    5369           0 :     return fastEmitInst_ri(ARM::VSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5370             :   }
    5371             :   return 0;
    5372             : }
    5373             : 
    5374             : unsigned fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5375           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5376             :     return 0;
    5377           0 :   if ((Subtarget->hasNEON())) {
    5378           0 :     return fastEmitInst_ri(ARM::VSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5379             :   }
    5380             :   return 0;
    5381             : }
    5382             : 
    5383             : unsigned fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5384           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5385             :     return 0;
    5386           0 :   if ((Subtarget->hasNEON())) {
    5387           0 :     return fastEmitInst_ri(ARM::VSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5388             :   }
    5389             :   return 0;
    5390             : }
    5391             : 
    5392           0 : unsigned fastEmit_ARMISD_VSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5393           0 :   switch (VT.SimpleTy) {
    5394           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5395           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5396           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5397           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5398           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5399           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5400           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5401           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5402             :   default: return 0;
    5403             :   }
    5404             : }
    5405             : 
    5406             : // FastEmit functions for ARMISD::VSHRu.
    5407             : 
    5408             : unsigned fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5409           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5410             :     return 0;
    5411           0 :   if ((Subtarget->hasNEON())) {
    5412           0 :     return fastEmitInst_ri(ARM::VSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5413             :   }
    5414             :   return 0;
    5415             : }
    5416             : 
    5417             : unsigned fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5418           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5419             :     return 0;
    5420           0 :   if ((Subtarget->hasNEON())) {
    5421           0 :     return fastEmitInst_ri(ARM::VSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5422             :   }
    5423             :   return 0;
    5424             : }
    5425             : 
    5426             : unsigned fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5427           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5428             :     return 0;
    5429           0 :   if ((Subtarget->hasNEON())) {
    5430           0 :     return fastEmitInst_ri(ARM::VSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5431             :   }
    5432             :   return 0;
    5433             : }
    5434             : 
    5435             : unsigned fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5436           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5437             :     return 0;
    5438           0 :   if ((Subtarget->hasNEON())) {
    5439           0 :     return fastEmitInst_ri(ARM::VSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5440             :   }
    5441             :   return 0;
    5442             : }
    5443             : 
    5444             : unsigned fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5445           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5446             :     return 0;
    5447           0 :   if ((Subtarget->hasNEON())) {
    5448           0 :     return fastEmitInst_ri(ARM::VSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5449             :   }
    5450             :   return 0;
    5451             : }
    5452             : 
    5453             : unsigned fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5454           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5455             :     return 0;
    5456           0 :   if ((Subtarget->hasNEON())) {
    5457           0 :     return fastEmitInst_ri(ARM::VSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5458             :   }
    5459             :   return 0;
    5460             : }
    5461             : 
    5462             : unsigned fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5463           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5464             :     return 0;
    5465           0 :   if ((Subtarget->hasNEON())) {
    5466           0 :     return fastEmitInst_ri(ARM::VSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5467             :   }
    5468             :   return 0;
    5469             : }
    5470             : 
    5471             : unsigned fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5472           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5473             :     return 0;
    5474           0 :   if ((Subtarget->hasNEON())) {
    5475           0 :     return fastEmitInst_ri(ARM::VSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5476             :   }
    5477             :   return 0;
    5478             : }
    5479             : 
    5480           0 : unsigned fastEmit_ARMISD_VSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5481           0 :   switch (VT.SimpleTy) {
    5482           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5483           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5484           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5485           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5486           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5487           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5488           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5489           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5490             :   default: return 0;
    5491             :   }
    5492             : }
    5493             : 
    5494             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    5495             : 
    5496           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5497           0 :   if (RetVT.SimpleTy != MVT::i32)
    5498             :     return 0;
    5499           0 :   if ((!Subtarget->hasSlowVGETLNi32()) && (Subtarget->hasVFP2())) {
    5500           0 :     return fastEmitInst_ri(ARM::VGETLNi32, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5501             :   }
    5502             :   return 0;
    5503             : }
    5504             : 
    5505             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5506           0 :   switch (VT.SimpleTy) {
    5507           0 :   case MVT::v2i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5508             :   default: return 0;
    5509             :   }
    5510             : }
    5511             : 
    5512             : // FastEmit functions for ISD::SHL.
    5513             : 
    5514           3 : unsigned fastEmit_ISD_SHL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5515           3 :   if (RetVT.SimpleTy != MVT::i32)
    5516             :     return 0;
    5517           3 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5518           0 :     return fastEmitInst_ri(ARM::tLSLri, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5519             :   }
    5520             :   return 0;
    5521             : }
    5522             : 
    5523             : unsigned fastEmit_ISD_SHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5524           3 :   switch (VT.SimpleTy) {
    5525           3 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5526             :   default: return 0;
    5527             :   }
    5528             : }
    5529             : 
    5530             : // Top-level FastEmit function.
    5531             : 
    5532         506 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    5533        1012 :   if (VT == MVT::i32 && Predicate_mod_imm(imm1))
    5534         255 :     if (unsigned Reg = fastEmit_ri_Predicate_mod_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5535             :       return Reg;
    5536             : 
    5537         464 :   if (VT == MVT::i32 && Predicate_imm0_7(imm1))
    5538          27 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_7(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5539             :       return Reg;
    5540             : 
    5541         928 :   if (VT == MVT::i32 && Predicate_imm8_255(imm1))
    5542          13 :     if (unsigned Reg = fastEmit_ri_Predicate_imm8_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5543             :       return Reg;
    5544             : 
    5545         464 :   if (VT == MVT::i32 && Predicate_imm0_255(imm1))
    5546          40 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5547             :       return Reg;
    5548             : 
    5549         928 :   if (VT == MVT::i32 && Predicate_t2_so_imm(imm1))
    5550         243 :     if (unsigned Reg = fastEmit_ri_Predicate_t2_so_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5551             :       return Reg;
    5552             : 
    5553         236 :   if (VT == MVT::i32 && Predicate_imm0_4095(imm1))
    5554         210 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_4095(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5555             :       return Reg;
    5556             : 
    5557          94 :   if (VT == MVT::i32 && Predicate_imm1_31(imm1))
    5558          15 :     if (unsigned Reg = fastEmit_ri_Predicate_imm1_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5559             :       return Reg;
    5560             : 
    5561          41 :   if (VT == MVT::i32 && Predicate_imm0_31(imm1))
    5562           9 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5563             :       return Reg;
    5564             : 
    5565          82 :   if (VT == MVT::i32 && Predicate_shr_imm8(imm1))
    5566           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5567             :       return Reg;
    5568             : 
    5569          82 :   if (VT == MVT::i32 && Predicate_shr_imm16(imm1))
    5570           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5571             :       return Reg;
    5572             : 
    5573          82 :   if (VT == MVT::i32 && Predicate_shr_imm32(imm1))
    5574           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5575             :       return Reg;
    5576             : 
    5577          41 :   if (VT == MVT::i32 && Predicate_VectorIndex32(imm1))
    5578           0 :     if (unsigned Reg = fastEmit_ri_Predicate_VectorIndex32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5579             :       return Reg;
    5580             : 
    5581          41 :   switch (Opcode) {
    5582           0 :   case ARMISD::PIC_ADD: return fastEmit_ARMISD_PIC_ADD_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5583           0 :   case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5584           0 :   case ARMISD::VGETLANEs: return fastEmit_ARMISD_VGETLANEs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5585           0 :   case ARMISD::VGETLANEu: return fastEmit_ARMISD_VGETLANEu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5586           0 :   case ARMISD::VQSHLs: return fastEmit_ARMISD_VQSHLs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5587           0 :   case ARMISD::VQSHLsu: return fastEmit_ARMISD_VQSHLsu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5588           0 :   case ARMISD::VQSHLu: return fastEmit_ARMISD_VQSHLu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5589           0 :   case ARMISD::VRSHRs: return fastEmit_ARMISD_VRSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5590           0 :   case ARMISD::VRSHRu: return fastEmit_ARMISD_VRSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5591           0 :   case ARMISD::VSHL: return fastEmit_ARMISD_VSHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5592           0 :   case ARMISD::VSHRs: return fastEmit_ARMISD_VSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5593           0 :   case ARMISD::VSHRu: return fastEmit_ARMISD_VSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5594           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5595           3 :   case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5596             :   default: return 0;
    5597             :   }
    5598             : }
    5599             : 
    5600             : // FastEmit functions for ARMISD::CMN.
    5601             : 
    5602             : unsigned fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5603           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5604             :     return 0;
    5605           0 :   if ((!Subtarget->isThumb())) {
    5606           0 :     return fastEmitInst_ri(ARM::CMNri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5607             :   }
    5608             :   return 0;
    5609             : }
    5610             : 
    5611           0 : unsigned fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5612           0 :   switch (VT.SimpleTy) {
    5613           0 :   case MVT::i32: return fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5614             :   default: return 0;
    5615             :   }
    5616             : }
    5617             : 
    5618             : // FastEmit functions for ARMISD::CMP.
    5619             : 
    5620             : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5621           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5622             :     return 0;
    5623           0 :   if ((!Subtarget->isThumb())) {
    5624           0 :     return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5625             :   }
    5626             :   return 0;
    5627             : }
    5628             : 
    5629           0 : unsigned fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5630           0 :   switch (VT.SimpleTy) {
    5631           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5632             :   default: return 0;
    5633             :   }
    5634             : }
    5635             : 
    5636             : // FastEmit functions for ARMISD::CMPZ.
    5637             : 
    5638             : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5639           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5640             :     return 0;
    5641           0 :   if ((!Subtarget->isThumb())) {
    5642           0 :     return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5643             :   }
    5644             :   return 0;
    5645             : }
    5646             : 
    5647           0 : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5648           0 :   switch (VT.SimpleTy) {
    5649           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5650             :   default: return 0;
    5651             :   }
    5652             : }
    5653             : 
    5654             : // FastEmit functions for ISD::ADD.
    5655             : 
    5656             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5657         234 :   if (RetVT.SimpleTy != MVT::i32)
    5658             :     return 0;
    5659         234 :   if ((!Subtarget->isThumb())) {
    5660          38 :     return fastEmitInst_ri(ARM::ADDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5661             :   }
    5662             :   return 0;
    5663             : }
    5664             : 
    5665         234 : unsigned fastEmit_ISD_ADD_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5666         234 :   switch (VT.SimpleTy) {
    5667         234 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5668             :   default: return 0;
    5669             :   }
    5670             : }
    5671             : 
    5672             : // FastEmit functions for ISD::AND.
    5673             : 
    5674             : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5675           3 :   if (RetVT.SimpleTy != MVT::i32)
    5676             :     return 0;
    5677           3 :   if ((!Subtarget->isThumb())) {
    5678           2 :     return fastEmitInst_ri(ARM::ANDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5679             :   }
    5680             :   return 0;
    5681             : }
    5682             : 
    5683           3 : unsigned fastEmit_ISD_AND_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5684           3 :   switch (VT.SimpleTy) {
    5685           3 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5686             :   default: return 0;
    5687             :   }
    5688             : }
    5689             : 
    5690             : // FastEmit functions for ISD::OR.
    5691             : 
    5692             : unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5693           3 :   if (RetVT.SimpleTy != MVT::i32)
    5694             :     return 0;
    5695           3 :   if ((!Subtarget->isThumb())) {
    5696           2 :     return fastEmitInst_ri(ARM::ORRri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5697             :   }
    5698             :   return 0;
    5699             : }
    5700             : 
    5701           3 : unsigned fastEmit_ISD_OR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5702           3 :   switch (VT.SimpleTy) {
    5703           3 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5704             :   default: return 0;
    5705             :   }
    5706             : }
    5707             : 
    5708             : // FastEmit functions for ISD::SUB.
    5709             : 
    5710             : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5711           0 :   if (RetVT.SimpleTy != MVT::i32)
    5712             :     return 0;
    5713           0 :   if ((!Subtarget->isThumb())) {
    5714           0 :     return fastEmitInst_ri(ARM::SUBri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5715             :   }
    5716             :   return 0;
    5717             : }
    5718             : 
    5719           0 : unsigned fastEmit_ISD_SUB_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5720           0 :   switch (VT.SimpleTy) {
    5721           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5722             :   default: return 0;
    5723             :   }
    5724             : }
    5725             : 
    5726             : // FastEmit functions for ISD::XOR.
    5727             : 
    5728             : unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5729           0 :   if (RetVT.SimpleTy != MVT::i32)
    5730             :     return 0;
    5731           0 :   if ((!Subtarget->isThumb())) {
    5732           0 :     return fastEmitInst_ri(ARM::EORri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5733             :   }
    5734             :   return 0;
    5735             : }
    5736             : 
    5737           0 : unsigned fastEmit_ISD_XOR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5738           0 :   switch (VT.SimpleTy) {
    5739           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5740             :   default: return 0;
    5741             :   }
    5742             : }
    5743             : 
    5744             : // Top-level FastEmit function.
    5745             : 
    5746         255 : unsigned fastEmit_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5747         255 :   switch (Opcode) {
    5748           0 :   case ARMISD::CMN: return fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5749           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5750           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5751         234 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5752           3 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5753           3 :   case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5754           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5755           0 :   case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5756             :   default: return 0;
    5757             :   }
    5758             : }
    5759             : 
    5760             : // FastEmit functions for ISD::ADD.
    5761             : 
    5762          11 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5763          11 :   if (RetVT.SimpleTy != MVT::i32)
    5764             :     return 0;
    5765          11 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5766           0 :     return fastEmitInst_ri(ARM::tADDi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5767             :   }
    5768             :   return 0;
    5769             : }
    5770             : 
    5771             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5772          11 :   switch (VT.SimpleTy) {
    5773          11 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1);
    5774             :   default: return 0;
    5775             :   }
    5776             : }
    5777             : 
    5778             : // Top-level FastEmit function.
    5779             : 
    5780          27 : unsigned fastEmit_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5781          27 :   switch (Opcode) {
    5782          11 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1);
    5783             :   default: return 0;
    5784             :   }
    5785             : }
    5786             : 
    5787             : // FastEmit functions for ISD::ADD.
    5788             : 
    5789          12 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5790          12 :   if (RetVT.SimpleTy != MVT::i32)
    5791             :     return 0;
    5792          12 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5793           0 :     return fastEmitInst_ri(ARM::tADDi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5794             :   }
    5795             :   return 0;
    5796             : }
    5797             : 
    5798             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5799          12 :   switch (VT.SimpleTy) {
    5800          12 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(RetVT, Op0, Op0IsKill, imm1);
    5801             :   default: return 0;
    5802             :   }
    5803             : }
    5804             : 
    5805             : // Top-level FastEmit function.
    5806             : 
    5807          13 : unsigned fastEmit_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5808          13 :   switch (Opcode) {
    5809          12 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm8_255(VT, RetVT, Op0, Op0IsKill, imm1);
    5810             :   default: return 0;
    5811             :   }
    5812             : }
    5813             : 
    5814             : // FastEmit functions for ARMISD::CMP.
    5815             : 
    5816           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5817           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5818             :     return 0;
    5819           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5820           0 :     return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5821             :   }
    5822             :   return 0;
    5823             : }
    5824             : 
    5825             : unsigned fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5826           0 :   switch (VT.SimpleTy) {
    5827           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1);
    5828             :   default: return 0;
    5829             :   }
    5830             : }
    5831             : 
    5832             : // FastEmit functions for ARMISD::CMPZ.
    5833             : 
    5834           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5835           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5836             :     return 0;
    5837           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5838           0 :     return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5839             :   }
    5840             :   return 0;
    5841             : }
    5842             : 
    5843             : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5844           0 :   switch (VT.SimpleTy) {
    5845           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1);
    5846             :   default: return 0;
    5847             :   }
    5848             : }
    5849             : 
    5850             : // Top-level FastEmit function.
    5851             : 
    5852          40 : unsigned fastEmit_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5853          40 :   switch (Opcode) {
    5854           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1);
    5855           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1);
    5856             :   default: return 0;
    5857             :   }
    5858             : }
    5859             : 
    5860             : // FastEmit functions for ARMISD::CMP.
    5861             : 
    5862           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5863           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5864             :     return 0;
    5865           0 :   if ((Subtarget->isThumb2())) {
    5866           0 :     return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    5867             :   }
    5868             :   return 0;
    5869             : }
    5870             : 
    5871             : unsigned fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5872           0 :   switch (VT.SimpleTy) {
    5873           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5874             :   default: return 0;
    5875             :   }
    5876             : }
    5877             : 
    5878             : // FastEmit functions for ARMISD::CMPZ.
    5879             : 
    5880           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5881           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5882             :     return 0;
    5883           0 :   if ((Subtarget->isThumb2())) {
    5884           0 :     return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    5885             :   }
    5886             :   return 0;
    5887             : }
    5888             : 
    5889             : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5890           0 :   switch (VT.SimpleTy) {
    5891           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5892             :   default: return 0;
    5893             :   }
    5894             : }
    5895             : 
    5896             : // FastEmit functions for ISD::ADD.
    5897             : 
    5898         226 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5899         226 :   if (RetVT.SimpleTy != MVT::i32)
    5900             :     return 0;
    5901         226 :   if ((Subtarget->isThumb2())) {
    5902         226 :     return fastEmitInst_ri(ARM::t2ADDri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    5903             :   }
    5904             :   return 0;
    5905             : }
    5906             : 
    5907             : unsigned fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5908         226 :   switch (VT.SimpleTy) {
    5909         226 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5910             :   default: return 0;
    5911             :   }
    5912             : }
    5913             : 
    5914             : // FastEmit functions for ISD::AND.
    5915             : 
    5916           1 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5917           1 :   if (RetVT.SimpleTy != MVT::i32)
    5918             :     return 0;
    5919           1 :   if ((Subtarget->isThumb2())) {
    5920           1 :     return fastEmitInst_ri(ARM::t2ANDri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    5921             :   }
    5922             :   return 0;
    5923             : }
    5924             : 
    5925             : unsigned fastEmit_ISD_AND_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5926           1 :   switch (VT.SimpleTy) {
    5927           1 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5928             :   default: return 0;
    5929             :   }
    5930             : }
    5931             : 
    5932             : // FastEmit functions for ISD::OR.
    5933             : 
    5934           1 : unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5935           1 :   if (RetVT.SimpleTy != MVT::i32)
    5936             :     return 0;
    5937           1 :   if ((Subtarget->isThumb2())) {
    5938           1 :     return fastEmitInst_ri(ARM::t2ORRri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    5939             :   }
    5940             :   return 0;
    5941             : }
    5942             : 
    5943             : unsigned fastEmit_ISD_OR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5944           1 :   switch (VT.SimpleTy) {
    5945           1 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5946             :   default: return 0;
    5947             :   }
    5948             : }
    5949             : 
    5950             : // FastEmit functions for ISD::SUB.
    5951             : 
    5952           0 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5953           0 :   if (RetVT.SimpleTy != MVT::i32)
    5954             :     return 0;
    5955           0 :   if ((Subtarget->isThumb2())) {
    5956           0 :     return fastEmitInst_ri(ARM::t2SUBri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    5957             :   }
    5958             :   return 0;
    5959             : }
    5960             : 
    5961             : unsigned fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5962           0 :   switch (VT.SimpleTy) {
    5963           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5964             :   default: return 0;
    5965             :   }
    5966             : }
    5967             : 
    5968             : // FastEmit functions for ISD::XOR.
    5969             : 
    5970           0 : unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5971           0 :   if (RetVT.SimpleTy != MVT::i32)
    5972             :     return 0;
    5973           0 :   if ((Subtarget->isThumb2())) {
    5974           0 :     return fastEmitInst_ri(ARM::t2EORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    5975             :   }
    5976             :   return 0;
    5977             : }
    5978             : 
    5979             : unsigned fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5980           0 :   switch (VT.SimpleTy) {
    5981           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5982             :   default: return 0;
    5983             :   }
    5984             : }
    5985             : 
    5986             : // Top-level FastEmit function.
    5987             : 
    5988         243 : unsigned fastEmit_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5989         243 :   switch (Opcode) {
    5990           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5991           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5992         226 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5993           1 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5994           1 :   case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5995           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5996           0 :   case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5997             :   default: return 0;
    5998             :   }
    5999             : }
    6000             : 
    6001             : // FastEmit functions for ISD::ADD.
    6002             : 
    6003         195 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6004         195 :   if (RetVT.SimpleTy != MVT::i32)
    6005             :     return 0;
    6006         195 :   if ((Subtarget->isThumb2())) {
    6007         189 :     return fastEmitInst_ri(ARM::t2ADDri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6008             :   }
    6009             :   return 0;
    6010             : }
    6011             : 
    6012             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6013         195 :   switch (VT.SimpleTy) {
    6014         195 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1);
    6015             :   default: return 0;
    6016             :   }
    6017             : }
    6018             : 
    6019             : // FastEmit functions for ISD::SUB.
    6020             : 
    6021           0 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6022           0 :   if (RetVT.SimpleTy != MVT::i32)
    6023             :     return 0;
    6024           0 :   if ((Subtarget->isThumb2())) {
    6025           0 :     return fastEmitInst_ri(ARM::t2SUBri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6026             :   }
    6027             :   return 0;
    6028             : }
    6029             : 
    6030             : unsigned fastEmit_ISD_SUB_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6031           0 :   switch (VT.SimpleTy) {
    6032           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1);
    6033             :   default: return 0;
    6034             :   }
    6035             : }
    6036             : 
    6037             : // Top-level FastEmit function.
    6038             : 
    6039         210 : unsigned fastEmit_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6040         210 :   switch (Opcode) {
    6041         195 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
    6042           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
    6043             :   default: return 0;
    6044             :   }
    6045             : }
    6046             : 
    6047             : // FastEmit functions for ISD::SHL.
    6048             : 
    6049           9 : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6050           9 :   if (RetVT.SimpleTy != MVT::i32)
    6051             :     return 0;
    6052           9 :   if ((Subtarget->isThumb2())) {
    6053           6 :     return fastEmitInst_ri(ARM::t2LSLri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6054             :   }
    6055             :   return 0;
    6056             : }
    6057             : 
    6058             : unsigned fastEmit_ISD_SHL_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6059           9 :   switch (VT.SimpleTy) {
    6060           9 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(RetVT, Op0, Op0IsKill, imm1);
    6061             :   default: return 0;
    6062             :   }
    6063             : }
    6064             : 
    6065             : // Top-level FastEmit function.
    6066             : 
    6067          15 : unsigned fastEmit_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6068          15 :   switch (Opcode) {
    6069           9 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_imm1_31(VT, RetVT, Op0, Op0IsKill, imm1);
    6070             :   default: return 0;
    6071             :   }
    6072             : }
    6073             : 
    6074             : // FastEmit functions for ISD::ROTR.
    6075             : 
    6076           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6077           0 :   if (RetVT.SimpleTy != MVT::i32)
    6078             :     return 0;
    6079           0 :   if ((Subtarget->isThumb2())) {
    6080           0 :     return fastEmitInst_ri(ARM::t2RORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6081             :   }
    6082             :   return 0;
    6083             : }
    6084             : 
    6085             : unsigned fastEmit_ISD_ROTR_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6086           0 :   switch (VT.SimpleTy) {
    6087           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1);
    6088             :   default: return 0;
    6089             :   }
    6090             : }
    6091             : 
    6092             : // Top-level FastEmit function.
    6093             : 
    6094           9 : unsigned fastEmit_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6095           9 :   switch (Opcode) {
    6096           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1);
    6097             :   default: return 0;
    6098             :   }
    6099             : }
    6100             : 
    6101             : // FastEmit functions for ARMISD::VQRSHRNs.
    6102             : 
    6103             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6104           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6105             :     return 0;
    6106           0 :   if ((Subtarget->hasNEON())) {
    6107           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6108             :   }
    6109             :   return 0;
    6110             : }
    6111             : 
    6112           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6113           0 :   switch (VT.SimpleTy) {
    6114           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6115             :   default: return 0;
    6116             :   }
    6117             : }
    6118             : 
    6119             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6120             : 
    6121             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6122           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6123             :     return 0;
    6124           0 :   if ((Subtarget->hasNEON())) {
    6125           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6126             :   }
    6127             :   return 0;
    6128             : }
    6129             : 
    6130           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6131           0 :   switch (VT.SimpleTy) {
    6132           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6133             :   default: return 0;
    6134             :   }
    6135             : }
    6136             : 
    6137             : // FastEmit functions for ARMISD::VQRSHRNu.
    6138             : 
    6139             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6140           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6141             :     return 0;
    6142           0 :   if ((Subtarget->hasNEON())) {
    6143           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6144             :   }
    6145             :   return 0;
    6146             : }
    6147             : 
    6148           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6149           0 :   switch (VT.SimpleTy) {
    6150           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6151             :   default: return 0;
    6152             :   }
    6153             : }
    6154             : 
    6155             : // FastEmit functions for ARMISD::VQSHRNs.
    6156             : 
    6157             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6158           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6159             :     return 0;
    6160           0 :   if ((Subtarget->hasNEON())) {
    6161           0 :     return fastEmitInst_ri(ARM::VQSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6162             :   }
    6163             :   return 0;
    6164             : }
    6165             : 
    6166           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6167           0 :   switch (VT.SimpleTy) {
    6168           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6169             :   default: return 0;
    6170             :   }
    6171             : }
    6172             : 
    6173             : // FastEmit functions for ARMISD::VQSHRNsu.
    6174             : 
    6175             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6176           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6177             :     return 0;
    6178           0 :   if ((Subtarget->hasNEON())) {
    6179           0 :     return fastEmitInst_ri(ARM::VQSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6180             :   }
    6181             :   return 0;
    6182             : }
    6183             : 
    6184           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6185           0 :   switch (VT.SimpleTy) {
    6186           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6187             :   default: return 0;
    6188             :   }
    6189             : }
    6190             : 
    6191             : // FastEmit functions for ARMISD::VQSHRNu.
    6192             : 
    6193             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6194           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6195             :     return 0;
    6196           0 :   if ((Subtarget->hasNEON())) {
    6197           0 :     return fastEmitInst_ri(ARM::VQSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6198             :   }
    6199             :   return 0;
    6200             : }
    6201             : 
    6202           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6203           0 :   switch (VT.SimpleTy) {
    6204           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6205             :   default: return 0;
    6206             :   }
    6207             : }
    6208             : 
    6209             : // FastEmit functions for ARMISD::VRSHRN.
    6210             : 
    6211             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6212           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6213             :     return 0;
    6214           0 :   if ((Subtarget->hasNEON())) {
    6215           0 :     return fastEmitInst_ri(ARM::VRSHRNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6216             :   }
    6217             :   return 0;
    6218             : }
    6219             : 
    6220           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6221           0 :   switch (VT.SimpleTy) {
    6222           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6223             :   default: return 0;
    6224             :   }
    6225             : }
    6226             : 
    6227             : // Top-level FastEmit function.
    6228             : 
    6229           9 : unsigned fastEmit_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6230           9 :   switch (Opcode) {
    6231           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6232           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6233           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6234           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6235           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6236           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6237           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6238             :   default: return 0;
    6239             :   }
    6240             : }
    6241             : 
    6242             : // FastEmit functions for ARMISD::VQRSHRNs.
    6243             : 
    6244             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6245           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6246             :     return 0;
    6247           0 :   if ((Subtarget->hasNEON())) {
    6248           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6249             :   }
    6250             :   return 0;
    6251             : }
    6252             : 
    6253           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6254           0 :   switch (VT.SimpleTy) {
    6255           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6256             :   default: return 0;
    6257             :   }
    6258             : }
    6259             : 
    6260             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6261             : 
    6262             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6263           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6264             :     return 0;
    6265           0 :   if ((Subtarget->hasNEON())) {
    6266           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6267             :   }
    6268             :   return 0;
    6269             : }
    6270             : 
    6271           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6272           0 :   switch (VT.SimpleTy) {
    6273           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6274             :   default: return 0;
    6275             :   }
    6276             : }
    6277             : 
    6278             : // FastEmit functions for ARMISD::VQRSHRNu.
    6279             : 
    6280             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6281           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6282             :     return 0;
    6283           0 :   if ((Subtarget->hasNEON())) {
    6284           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6285             :   }
    6286             :   return 0;
    6287             : }
    6288             : 
    6289           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6290           0 :   switch (VT.SimpleTy) {
    6291           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6292             :   default: return 0;
    6293             :   }
    6294             : }
    6295             : 
    6296             : // FastEmit functions for ARMISD::VQSHRNs.
    6297             : 
    6298             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6299           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6300             :     return 0;
    6301           0 :   if ((Subtarget->hasNEON())) {
    6302           0 :     return fastEmitInst_ri(ARM::VQSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6303             :   }
    6304             :   return 0;
    6305             : }
    6306             : 
    6307           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6308           0 :   switch (VT.SimpleTy) {
    6309           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6310             :   default: return 0;
    6311             :   }
    6312             : }
    6313             : 
    6314             : // FastEmit functions for ARMISD::VQSHRNsu.
    6315             : 
    6316             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6317           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6318             :     return 0;
    6319           0 :   if ((Subtarget->hasNEON())) {
    6320           0 :     return fastEmitInst_ri(ARM::VQSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6321             :   }
    6322             :   return 0;
    6323             : }
    6324             : 
    6325           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6326           0 :   switch (VT.SimpleTy) {
    6327           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6328             :   default: return 0;
    6329             :   }
    6330             : }
    6331             : 
    6332             : // FastEmit functions for ARMISD::VQSHRNu.
    6333             : 
    6334             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6335           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6336             :     return 0;
    6337           0 :   if ((Subtarget->hasNEON())) {
    6338           0 :     return fastEmitInst_ri(ARM::VQSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6339             :   }
    6340             :   return 0;
    6341             : }
    6342             : 
    6343           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6344           0 :   switch (VT.SimpleTy) {
    6345           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6346             :   default: return 0;
    6347             :   }
    6348             : }
    6349             : 
    6350             : // FastEmit functions for ARMISD::VRSHRN.
    6351             : 
    6352             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6353           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6354             :     return 0;
    6355           0 :   if ((Subtarget->hasNEON())) {
    6356           0 :     return fastEmitInst_ri(ARM::VRSHRNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6357             :   }
    6358             :   return 0;
    6359             : }
    6360             : 
    6361           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6362           0 :   switch (VT.SimpleTy) {
    6363           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6364             :   default: return 0;
    6365             :   }
    6366             : }
    6367             : 
    6368             : // Top-level FastEmit function.
    6369             : 
    6370           9 : unsigned fastEmit_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6371           9 :   switch (Opcode) {
    6372           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6373           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6374           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6375           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6376           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6377           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6378           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6379             :   default: return 0;
    6380             :   }
    6381             : }
    6382             : 
    6383             : // FastEmit functions for ARMISD::VQRSHRNs.
    6384             : 
    6385             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6386           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6387             :     return 0;
    6388           0 :   if ((Subtarget->hasNEON())) {
    6389           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6390             :   }
    6391             :   return 0;
    6392             : }
    6393             : 
    6394           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6395           0 :   switch (VT.SimpleTy) {
    6396           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6397             :   default: return 0;
    6398             :   }
    6399             : }
    6400             : 
    6401             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6402             : 
    6403             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6404           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6405             :     return 0;
    6406           0 :   if ((Subtarget->hasNEON())) {
    6407           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6408             :   }
    6409             :   return 0;
    6410             : }
    6411             : 
    6412           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6413           0 :   switch (VT.SimpleTy) {
    6414           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6415             :   default: return 0;
    6416             :   }
    6417             : }
    6418             : 
    6419             : // FastEmit functions for ARMISD::VQRSHRNu.
    6420             : 
    6421             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6422           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6423             :     return 0;
    6424           0 :   if ((Subtarget->hasNEON())) {
    6425           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6426             :   }
    6427             :   return 0;
    6428             : }
    6429             : 
    6430           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6431           0 :   switch (VT.SimpleTy) {
    6432           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6433             :   default: return 0;
    6434             :   }
    6435             : }
    6436             : 
    6437             : // FastEmit functions for ARMISD::VQSHRNs.
    6438             : 
    6439             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6440           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6441             :     return 0;
    6442           0 :   if ((Subtarget->hasNEON())) {
    6443           0 :     return fastEmitInst_ri(ARM::VQSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6444             :   }
    6445             :   return 0;
    6446             : }
    6447             : 
    6448           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6449           0 :   switch (VT.SimpleTy) {
    6450           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6451             :   default: return 0;
    6452             :   }
    6453             : }
    6454             : 
    6455             : // FastEmit functions for ARMISD::VQSHRNsu.
    6456             : 
    6457             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6458           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6459             :     return 0;
    6460           0 :   if ((Subtarget->hasNEON())) {
    6461           0 :     return fastEmitInst_ri(ARM::VQSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6462             :   }
    6463             :   return 0;
    6464             : }
    6465             : 
    6466           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6467           0 :   switch (VT.SimpleTy) {
    6468           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6469             :   default: return 0;
    6470             :   }
    6471             : }
    6472             : 
    6473             : // FastEmit functions for ARMISD::VQSHRNu.
    6474             : 
    6475             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6476           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6477             :     return 0;
    6478           0 :   if ((Subtarget->hasNEON())) {
    6479           0 :     return fastEmitInst_ri(ARM::VQSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6480             :   }
    6481             :   return 0;
    6482             : }
    6483             : 
    6484           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6485           0 :   switch (VT.SimpleTy) {
    6486           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6487             :   default: return 0;
    6488             :   }
    6489             : }
    6490             : 
    6491             : // FastEmit functions for ARMISD::VRSHRN.
    6492             : 
    6493             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6494           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6495             :     return 0;
    6496           0 :   if ((Subtarget->hasNEON())) {
    6497           0 :     return fastEmitInst_ri(ARM::VRSHRNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6498             :   }
    6499             :   return 0;
    6500             : }
    6501             : 
    6502           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6503           0 :   switch (VT.SimpleTy) {
    6504           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6505             :   default: return 0;
    6506             :   }
    6507             : }
    6508             : 
    6509             : // Top-level FastEmit function.
    6510             : 
    6511           9 : unsigned fastEmit_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6512           9 :   switch (Opcode) {
    6513           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6514           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6515           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6516           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6517           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6518           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6519           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6520             :   default: return 0;
    6521             :   }
    6522             : }
    6523             : 
    6524             : // FastEmit functions for ARMISD::VDUPLANE.
    6525             : 
    6526             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6527           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    6528             :     return 0;
    6529           0 :   if ((Subtarget->hasNEON())) {
    6530           0 :     return fastEmitInst_ri(ARM::VDUPLN8q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6531             :   }
    6532             :   return 0;
    6533             : }
    6534             : 
    6535             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6536           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    6537             :     return 0;
    6538           0 :   if ((Subtarget->hasNEON())) {
    6539           0 :     return fastEmitInst_ri(ARM::VDUPLN16q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6540             :   }
    6541             :   return 0;
    6542             : }
    6543             : 
    6544             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6545           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    6546             :     return 0;
    6547           0 :   if ((Subtarget->hasNEON())) {
    6548           0 :     return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6549             :   }
    6550             :   return 0;
    6551             : }
    6552             : 
    6553           0 : unsigned fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6554           0 :   switch (VT.SimpleTy) {
    6555           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6556           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6557           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6558             :   default: return 0;
    6559             :   }
    6560             : }
    6561             : 
    6562             : // Top-level FastEmit function.
    6563             : 
    6564             : unsigned fastEmit_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6565           0 :   switch (Opcode) {
    6566           0 :   case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(VT, RetVT, Op0, Op0IsKill, imm1);
    6567             :   default: return 0;
    6568             :   }
    6569             : }
    6570             : 
    6571             : // FastEmit functions for ISD::Constant.
    6572             : 
    6573          47 : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    6574          47 :   if (RetVT.SimpleTy != MVT::i32)
    6575             :     return 0;
    6576          47 :   if ((Subtarget->isThumb()) && (Subtarget->useMovt(*MF))) {
    6577          15 :     return fastEmitInst_i(ARM::t2MOVi32imm, &ARM::rGPRRegClass, imm0);
    6578             :   }
    6579             :   return 0;
    6580             : }
    6581             : 
    6582             : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
    6583          47 :   switch (VT.SimpleTy) {
    6584          47 :   case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
    6585             :   default: return 0;
    6586             :   }
    6587             : }
    6588             : 
    6589             : // Top-level FastEmit function.
    6590             : 
    6591          41 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
    6592          41 :   switch (Opcode) {
    6593          47 :   case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
    6594             :   default: return 0;
    6595             :   }
    6596             : }
    6597             : 

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