LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/ARM - ARMGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 276 2700 10.2 %
Date: 2018-02-19 17:12:42 Functions: 53 299 17.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the ARM target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_mod_imm(int64_t Imm) {
      12             : 
      13         506 :     return ARM_AM::getSOImmVal(Imm) != -1;
      14             :   
      15             : }
      16             : static bool Predicate_imm0_65535(int64_t Imm) {
      17             : 
      18             :   return Imm >= 0 && Imm < 65536;
      19             : 
      20             : }
      21             : static bool Predicate_imm0_7(int64_t Imm) {
      22             : 
      23             :   return Imm >= 0 && Imm < 8;
      24             : 
      25             : }
      26             : static bool Predicate_imm8_255(int64_t Imm) {
      27             : 
      28         464 :   return Imm >= 8 && Imm < 256;
      29             : 
      30             : }
      31             : static bool Predicate_imm0_255(int64_t Imm) {
      32             :  return Imm >= 0 && Imm < 256; 
      33             : }
      34             : static bool Predicate_t2_so_imm(int64_t Imm) {
      35             : 
      36         464 :     return ARM_AM::getT2SOImmVal(Imm) != -1;
      37             :   
      38             : }
      39             : static bool Predicate_imm0_4095(int64_t Imm) {
      40             : 
      41             :   return Imm >= 0 && Imm < 4096;
      42             : 
      43             : }
      44             : static bool Predicate_imm1_31(int64_t Imm) {
      45          47 :  return Imm > 0 && Imm < 32; 
      46             : }
      47             : static bool Predicate_imm0_31(int64_t Imm) {
      48             : 
      49             :   return Imm >= 0 && Imm < 32;
      50             : 
      51             : }
      52             : static bool Predicate_shr_imm8(int64_t Imm) {
      53          41 :  return Imm > 0 && Imm <= 8; 
      54             : }
      55             : static bool Predicate_shr_imm16(int64_t Imm) {
      56          41 :  return Imm > 0 && Imm <= 16; 
      57             : }
      58             : static bool Predicate_shr_imm32(int64_t Imm) {
      59          41 :  return Imm > 0 && Imm <= 32; 
      60             : }
      61             : static bool Predicate_VectorIndex32(int64_t Imm) {
      62             : 
      63             :   return ((uint64_t)Imm) < 2;
      64             : 
      65             : }
      66             : static bool Predicate_t2_so_imm_neg(int64_t Imm) {
      67             : 
      68             :   return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
      69             : 
      70             : }
      71             : 
      72             : 
      73             : // FastEmit functions for ARMISD::CALL.
      74             : 
      75           0 : unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      76           0 :   if (RetVT.SimpleTy != MVT::isVoid)
      77             :     return 0;
      78           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
      79           0 :     return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill);
      80             :   }
      81             :   return 0;
      82             : }
      83             : 
      84             : unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
      85           0 :   switch (VT.SimpleTy) {
      86           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill);
      87             :   default: return 0;
      88             :   }
      89             : }
      90             : 
      91             : // FastEmit functions for ARMISD::CALL_NOLINK.
      92             : 
      93           0 : unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      94           0 :   if (RetVT.SimpleTy != MVT::isVoid)
      95             :     return 0;
      96           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
      97           0 :     return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
      98             :   }
      99           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
     100           0 :     return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
     101             :   }
     102           0 :   if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
     103           0 :     return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
     104             :   }
     105             :   return 0;
     106             : }
     107             : 
     108             : unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     109           0 :   switch (VT.SimpleTy) {
     110           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill);
     111             :   default: return 0;
     112             :   }
     113             : }
     114             : 
     115             : // FastEmit functions for ARMISD::CALL_PRED.
     116             : 
     117           0 : unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     118           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     119             :     return 0;
     120           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
     121           0 :     return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill);
     122             :   }
     123             :   return 0;
     124             : }
     125             : 
     126             : unsigned fastEmit_ARMISD_CALL_PRED_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     127           0 :   switch (VT.SimpleTy) {
     128           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_PRED_MVT_i32_r(RetVT, Op0, Op0IsKill);
     129             :   default: return 0;
     130             :   }
     131             : }
     132             : 
     133             : // FastEmit functions for ARMISD::RRX.
     134             : 
     135           0 : unsigned fastEmit_ARMISD_RRX_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     136           0 :   if (RetVT.SimpleTy != MVT::i32)
     137             :     return 0;
     138           0 :   if ((Subtarget->isThumb2())) {
     139           0 :     return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill);
     140             :   }
     141           0 :   if ((!Subtarget->isThumb())) {
     142           0 :     return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill);
     143             :   }
     144             :   return 0;
     145             : }
     146             : 
     147             : unsigned fastEmit_ARMISD_RRX_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     148           0 :   switch (VT.SimpleTy) {
     149           0 :   case MVT::i32: return fastEmit_ARMISD_RRX_MVT_i32_r(RetVT, Op0, Op0IsKill);
     150             :   default: return 0;
     151             :   }
     152             : }
     153             : 
     154             : // FastEmit functions for ARMISD::SRA_FLAG.
     155             : 
     156           0 : unsigned fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     157           0 :   if (RetVT.SimpleTy != MVT::i32)
     158             :     return 0;
     159           0 :   if ((Subtarget->isThumb2())) {
     160           0 :     return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
     161             :   }
     162           0 :   if ((!Subtarget->isThumb())) {
     163           0 :     return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
     164             :   }
     165             :   return 0;
     166             : }
     167             : 
     168             : unsigned fastEmit_ARMISD_SRA_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     169           0 :   switch (VT.SimpleTy) {
     170           0 :   case MVT::i32: return fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
     171             :   default: return 0;
     172             :   }
     173             : }
     174             : 
     175             : // FastEmit functions for ARMISD::SRL_FLAG.
     176             : 
     177           0 : unsigned fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     178           0 :   if (RetVT.SimpleTy != MVT::i32)
     179             :     return 0;
     180           0 :   if ((Subtarget->isThumb2())) {
     181           0 :     return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
     182             :   }
     183           0 :   if ((!Subtarget->isThumb())) {
     184           0 :     return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
     185             :   }
     186             :   return 0;
     187             : }
     188             : 
     189             : unsigned fastEmit_ARMISD_SRL_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     190           0 :   switch (VT.SimpleTy) {
     191           0 :   case MVT::i32: return fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
     192             :   default: return 0;
     193             :   }
     194             : }
     195             : 
     196             : // FastEmit functions for ARMISD::TC_RETURN.
     197             : 
     198             : unsigned fastEmit_ARMISD_TC_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     199           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     200             :     return 0;
     201           0 :   return fastEmitInst_r(ARM::TCRETURNri, &ARM::tcGPRRegClass, Op0, Op0IsKill);
     202             : }
     203             : 
     204             : unsigned fastEmit_ARMISD_TC_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     205           0 :   switch (VT.SimpleTy) {
     206           0 :   case MVT::i32: return fastEmit_ARMISD_TC_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill);
     207             :   default: return 0;
     208             :   }
     209             : }
     210             : 
     211             : // FastEmit functions for ARMISD::VCEQZ.
     212             : 
     213             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     214           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     215             :     return 0;
     216           0 :   if ((Subtarget->hasNEON())) {
     217           0 :     return fastEmitInst_r(ARM::VCEQzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     218             :   }
     219             :   return 0;
     220             : }
     221             : 
     222             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     223           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     224             :     return 0;
     225           0 :   if ((Subtarget->hasNEON())) {
     226           0 :     return fastEmitInst_r(ARM::VCEQzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     227             :   }
     228             :   return 0;
     229             : }
     230             : 
     231             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     232           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     233             :     return 0;
     234           0 :   if ((Subtarget->hasNEON())) {
     235           0 :     return fastEmitInst_r(ARM::VCEQzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     236             :   }
     237             :   return 0;
     238             : }
     239             : 
     240             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     241           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     242             :     return 0;
     243           0 :   if ((Subtarget->hasNEON())) {
     244           0 :     return fastEmitInst_r(ARM::VCEQzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     245             :   }
     246             :   return 0;
     247             : }
     248             : 
     249             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     250           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     251             :     return 0;
     252           0 :   if ((Subtarget->hasNEON())) {
     253           0 :     return fastEmitInst_r(ARM::VCEQzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     254             :   }
     255             :   return 0;
     256             : }
     257             : 
     258             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     259           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     260             :     return 0;
     261           0 :   if ((Subtarget->hasNEON())) {
     262           0 :     return fastEmitInst_r(ARM::VCEQzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     263             :   }
     264             :   return 0;
     265             : }
     266             : 
     267           0 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     268           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     269             :     return 0;
     270           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     271           0 :     return fastEmitInst_r(ARM::VCEQzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     272             :   }
     273             :   return 0;
     274             : }
     275             : 
     276           0 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     277           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     278             :     return 0;
     279           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     280           0 :     return fastEmitInst_r(ARM::VCEQzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     281             :   }
     282             :   return 0;
     283             : }
     284             : 
     285             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     286           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     287             :     return 0;
     288           0 :   if ((Subtarget->hasNEON())) {
     289           0 :     return fastEmitInst_r(ARM::VCEQzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     290             :   }
     291             :   return 0;
     292             : }
     293             : 
     294             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     295           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     296             :     return 0;
     297           0 :   if ((Subtarget->hasNEON())) {
     298           0 :     return fastEmitInst_r(ARM::VCEQzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     299             :   }
     300             :   return 0;
     301             : }
     302             : 
     303           0 : unsigned fastEmit_ARMISD_VCEQZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     304           0 :   switch (VT.SimpleTy) {
     305           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     306           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     307           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     308           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     309           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     310           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     311           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     312           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     313           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     314           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     315             :   default: return 0;
     316             :   }
     317             : }
     318             : 
     319             : // FastEmit functions for ARMISD::VCGEZ.
     320             : 
     321             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     322           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     323             :     return 0;
     324           0 :   if ((Subtarget->hasNEON())) {
     325           0 :     return fastEmitInst_r(ARM::VCGEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     326             :   }
     327             :   return 0;
     328             : }
     329             : 
     330             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     331           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     332             :     return 0;
     333           0 :   if ((Subtarget->hasNEON())) {
     334           0 :     return fastEmitInst_r(ARM::VCGEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     335             :   }
     336             :   return 0;
     337             : }
     338             : 
     339             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     340           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     341             :     return 0;
     342           0 :   if ((Subtarget->hasNEON())) {
     343           0 :     return fastEmitInst_r(ARM::VCGEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     344             :   }
     345             :   return 0;
     346             : }
     347             : 
     348             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     349           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     350             :     return 0;
     351           0 :   if ((Subtarget->hasNEON())) {
     352           0 :     return fastEmitInst_r(ARM::VCGEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     353             :   }
     354             :   return 0;
     355             : }
     356             : 
     357             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     358           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     359             :     return 0;
     360           0 :   if ((Subtarget->hasNEON())) {
     361           0 :     return fastEmitInst_r(ARM::VCGEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     362             :   }
     363             :   return 0;
     364             : }
     365             : 
     366             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     367           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     368             :     return 0;
     369           0 :   if ((Subtarget->hasNEON())) {
     370           0 :     return fastEmitInst_r(ARM::VCGEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     371             :   }
     372             :   return 0;
     373             : }
     374             : 
     375           0 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     376           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     377             :     return 0;
     378           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     379           0 :     return fastEmitInst_r(ARM::VCGEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     380             :   }
     381             :   return 0;
     382             : }
     383             : 
     384           0 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     385           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     386             :     return 0;
     387           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     388           0 :     return fastEmitInst_r(ARM::VCGEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     389             :   }
     390             :   return 0;
     391             : }
     392             : 
     393             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     394           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     395             :     return 0;
     396           0 :   if ((Subtarget->hasNEON())) {
     397           0 :     return fastEmitInst_r(ARM::VCGEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     398             :   }
     399             :   return 0;
     400             : }
     401             : 
     402             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     403           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     404             :     return 0;
     405           0 :   if ((Subtarget->hasNEON())) {
     406           0 :     return fastEmitInst_r(ARM::VCGEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     407             :   }
     408             :   return 0;
     409             : }
     410             : 
     411           0 : unsigned fastEmit_ARMISD_VCGEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     412           0 :   switch (VT.SimpleTy) {
     413           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     414           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     415           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     416           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     417           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     418           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     419           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     420           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     421           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     422           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     423             :   default: return 0;
     424             :   }
     425             : }
     426             : 
     427             : // FastEmit functions for ARMISD::VCGTZ.
     428             : 
     429             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     430           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     431             :     return 0;
     432           0 :   if ((Subtarget->hasNEON())) {
     433           0 :     return fastEmitInst_r(ARM::VCGTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     434             :   }
     435             :   return 0;
     436             : }
     437             : 
     438             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     439           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     440             :     return 0;
     441           0 :   if ((Subtarget->hasNEON())) {
     442           0 :     return fastEmitInst_r(ARM::VCGTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     443             :   }
     444             :   return 0;
     445             : }
     446             : 
     447             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     448           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     449             :     return 0;
     450           0 :   if ((Subtarget->hasNEON())) {
     451           0 :     return fastEmitInst_r(ARM::VCGTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     452             :   }
     453             :   return 0;
     454             : }
     455             : 
     456             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     457           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     458             :     return 0;
     459           0 :   if ((Subtarget->hasNEON())) {
     460           0 :     return fastEmitInst_r(ARM::VCGTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     461             :   }
     462             :   return 0;
     463             : }
     464             : 
     465             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     466           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     467             :     return 0;
     468           0 :   if ((Subtarget->hasNEON())) {
     469           0 :     return fastEmitInst_r(ARM::VCGTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     470             :   }
     471             :   return 0;
     472             : }
     473             : 
     474             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     475           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     476             :     return 0;
     477           0 :   if ((Subtarget->hasNEON())) {
     478           0 :     return fastEmitInst_r(ARM::VCGTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     479             :   }
     480             :   return 0;
     481             : }
     482             : 
     483           0 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     484           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     485             :     return 0;
     486           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     487           0 :     return fastEmitInst_r(ARM::VCGTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     488             :   }
     489             :   return 0;
     490             : }
     491             : 
     492           0 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     493           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     494             :     return 0;
     495           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     496           0 :     return fastEmitInst_r(ARM::VCGTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     497             :   }
     498             :   return 0;
     499             : }
     500             : 
     501             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     502           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     503             :     return 0;
     504           0 :   if ((Subtarget->hasNEON())) {
     505           0 :     return fastEmitInst_r(ARM::VCGTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     506             :   }
     507             :   return 0;
     508             : }
     509             : 
     510             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     511           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     512             :     return 0;
     513           0 :   if ((Subtarget->hasNEON())) {
     514           0 :     return fastEmitInst_r(ARM::VCGTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     515             :   }
     516             :   return 0;
     517             : }
     518             : 
     519           0 : unsigned fastEmit_ARMISD_VCGTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     520           0 :   switch (VT.SimpleTy) {
     521           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     522           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     523           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     524           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     525           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     526           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     527           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     528           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     529           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     530           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     531             :   default: return 0;
     532             :   }
     533             : }
     534             : 
     535             : // FastEmit functions for ARMISD::VCLEZ.
     536             : 
     537             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     538           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     539             :     return 0;
     540           0 :   if ((Subtarget->hasNEON())) {
     541           0 :     return fastEmitInst_r(ARM::VCLEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     542             :   }
     543             :   return 0;
     544             : }
     545             : 
     546             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     547           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     548             :     return 0;
     549           0 :   if ((Subtarget->hasNEON())) {
     550           0 :     return fastEmitInst_r(ARM::VCLEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     551             :   }
     552             :   return 0;
     553             : }
     554             : 
     555             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     556           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     557             :     return 0;
     558           0 :   if ((Subtarget->hasNEON())) {
     559           0 :     return fastEmitInst_r(ARM::VCLEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     560             :   }
     561             :   return 0;
     562             : }
     563             : 
     564             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     565           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     566             :     return 0;
     567           0 :   if ((Subtarget->hasNEON())) {
     568           0 :     return fastEmitInst_r(ARM::VCLEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     569             :   }
     570             :   return 0;
     571             : }
     572             : 
     573             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     574           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     575             :     return 0;
     576           0 :   if ((Subtarget->hasNEON())) {
     577           0 :     return fastEmitInst_r(ARM::VCLEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     578             :   }
     579             :   return 0;
     580             : }
     581             : 
     582             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     583           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     584             :     return 0;
     585           0 :   if ((Subtarget->hasNEON())) {
     586           0 :     return fastEmitInst_r(ARM::VCLEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     587             :   }
     588             :   return 0;
     589             : }
     590             : 
     591           0 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     592           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     593             :     return 0;
     594           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     595           0 :     return fastEmitInst_r(ARM::VCLEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     596             :   }
     597             :   return 0;
     598             : }
     599             : 
     600           0 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     601           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     602             :     return 0;
     603           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     604           0 :     return fastEmitInst_r(ARM::VCLEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     605             :   }
     606             :   return 0;
     607             : }
     608             : 
     609             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     610           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     611             :     return 0;
     612           0 :   if ((Subtarget->hasNEON())) {
     613           0 :     return fastEmitInst_r(ARM::VCLEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     614             :   }
     615             :   return 0;
     616             : }
     617             : 
     618             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     619           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     620             :     return 0;
     621           0 :   if ((Subtarget->hasNEON())) {
     622           0 :     return fastEmitInst_r(ARM::VCLEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     623             :   }
     624             :   return 0;
     625             : }
     626             : 
     627           0 : unsigned fastEmit_ARMISD_VCLEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     628           0 :   switch (VT.SimpleTy) {
     629           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     630           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     631           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     632           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     633           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     634           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     635           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     636           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     637           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     638           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     639             :   default: return 0;
     640             :   }
     641             : }
     642             : 
     643             : // FastEmit functions for ARMISD::VCLTZ.
     644             : 
     645             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     646           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     647             :     return 0;
     648           0 :   if ((Subtarget->hasNEON())) {
     649           0 :     return fastEmitInst_r(ARM::VCLTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     650             :   }
     651             :   return 0;
     652             : }
     653             : 
     654             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     655           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     656             :     return 0;
     657           0 :   if ((Subtarget->hasNEON())) {
     658           0 :     return fastEmitInst_r(ARM::VCLTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     659             :   }
     660             :   return 0;
     661             : }
     662             : 
     663             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     664           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     665             :     return 0;
     666           0 :   if ((Subtarget->hasNEON())) {
     667           0 :     return fastEmitInst_r(ARM::VCLTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     668             :   }
     669             :   return 0;
     670             : }
     671             : 
     672             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     673           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     674             :     return 0;
     675           0 :   if ((Subtarget->hasNEON())) {
     676           0 :     return fastEmitInst_r(ARM::VCLTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     677             :   }
     678             :   return 0;
     679             : }
     680             : 
     681             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     682           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     683             :     return 0;
     684           0 :   if ((Subtarget->hasNEON())) {
     685           0 :     return fastEmitInst_r(ARM::VCLTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     686             :   }
     687             :   return 0;
     688             : }
     689             : 
     690             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     691           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     692             :     return 0;
     693           0 :   if ((Subtarget->hasNEON())) {
     694           0 :     return fastEmitInst_r(ARM::VCLTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     695             :   }
     696             :   return 0;
     697             : }
     698             : 
     699           0 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     700           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     701             :     return 0;
     702           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     703           0 :     return fastEmitInst_r(ARM::VCLTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     704             :   }
     705             :   return 0;
     706             : }
     707             : 
     708           0 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     709           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     710             :     return 0;
     711           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     712           0 :     return fastEmitInst_r(ARM::VCLTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     713             :   }
     714             :   return 0;
     715             : }
     716             : 
     717             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     718           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     719             :     return 0;
     720           0 :   if ((Subtarget->hasNEON())) {
     721           0 :     return fastEmitInst_r(ARM::VCLTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     722             :   }
     723             :   return 0;
     724             : }
     725             : 
     726             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     727           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     728             :     return 0;
     729           0 :   if ((Subtarget->hasNEON())) {
     730           0 :     return fastEmitInst_r(ARM::VCLTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     731             :   }
     732             :   return 0;
     733             : }
     734             : 
     735           0 : unsigned fastEmit_ARMISD_VCLTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     736           0 :   switch (VT.SimpleTy) {
     737           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     738           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     739           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     740           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     741           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     742           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     743           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     744           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     745           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     746           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     747             :   default: return 0;
     748             :   }
     749             : }
     750             : 
     751             : // FastEmit functions for ARMISD::VDUP.
     752             : 
     753             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
     754           0 :   if ((Subtarget->hasNEON())) {
     755           0 :     return fastEmitInst_r(ARM::VDUP8d, &ARM::DPRRegClass, Op0, Op0IsKill);
     756             :   }
     757             :   return 0;
     758             : }
     759             : 
     760             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
     761           0 :   if ((Subtarget->hasNEON())) {
     762           0 :     return fastEmitInst_r(ARM::VDUP8q, &ARM::QPRRegClass, Op0, Op0IsKill);
     763             :   }
     764             :   return 0;
     765             : }
     766             : 
     767             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
     768           0 :   if ((Subtarget->hasNEON())) {
     769           0 :     return fastEmitInst_r(ARM::VDUP16d, &ARM::DPRRegClass, Op0, Op0IsKill);
     770             :   }
     771             :   return 0;
     772             : }
     773             : 
     774             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
     775           0 :   if ((Subtarget->hasNEON())) {
     776           0 :     return fastEmitInst_r(ARM::VDUP16q, &ARM::QPRRegClass, Op0, Op0IsKill);
     777             :   }
     778             :   return 0;
     779             : }
     780             : 
     781           0 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
     782           0 :   if ((!Subtarget->hasSlowVDUP32()) && (Subtarget->hasNEON())) {
     783           0 :     return fastEmitInst_r(ARM::VDUP32d, &ARM::DPRRegClass, Op0, Op0IsKill);
     784             :   }
     785             :   return 0;
     786             : }
     787             : 
     788             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
     789           0 :   if ((Subtarget->hasNEON())) {
     790           0 :     return fastEmitInst_r(ARM::VDUP32q, &ARM::QPRRegClass, Op0, Op0IsKill);
     791             :   }
     792             :   return 0;
     793             : }
     794             : 
     795           0 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     796           0 : switch (RetVT.SimpleTy) {
     797           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill);
     798           0 :   case MVT::v16i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill);
     799           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill);
     800           0 :   case MVT::v8i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill);
     801           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill);
     802           0 :   case MVT::v4i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill);
     803             :   default: return 0;
     804             : }
     805             : }
     806             : 
     807             : unsigned fastEmit_ARMISD_VDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     808           0 :   switch (VT.SimpleTy) {
     809           0 :   case MVT::i32: return fastEmit_ARMISD_VDUP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     810             :   default: return 0;
     811             :   }
     812             : }
     813             : 
     814             : // FastEmit functions for ARMISD::VMOVhr.
     815             : 
     816             : unsigned fastEmit_ARMISD_VMOVhr_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     817           0 :   if (RetVT.SimpleTy != MVT::f16)
     818             :     return 0;
     819           0 :   if ((Subtarget->hasFullFP16())) {
     820           0 :     return fastEmitInst_r(ARM::VMOVHR, &ARM::HPRRegClass, Op0, Op0IsKill);
     821             :   }
     822             :   return 0;
     823             : }
     824             : 
     825           0 : unsigned fastEmit_ARMISD_VMOVhr_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     826           0 :   switch (VT.SimpleTy) {
     827           0 :   case MVT::i32: return fastEmit_ARMISD_VMOVhr_MVT_i32_r(RetVT, Op0, Op0IsKill);
     828             :   default: return 0;
     829             :   }
     830             : }
     831             : 
     832             : // FastEmit functions for ARMISD::VMOVrh.
     833             : 
     834             : unsigned fastEmit_ARMISD_VMOVrh_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     835           0 :   if (RetVT.SimpleTy != MVT::i32)
     836             :     return 0;
     837           0 :   if ((Subtarget->hasFullFP16())) {
     838           0 :     return fastEmitInst_r(ARM::VMOVRH, &ARM::GPRRegClass, Op0, Op0IsKill);
     839             :   }
     840             :   return 0;
     841             : }
     842             : 
     843           0 : unsigned fastEmit_ARMISD_VMOVrh_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     844           0 :   switch (VT.SimpleTy) {
     845           0 :   case MVT::f16: return fastEmit_ARMISD_VMOVrh_MVT_f16_r(RetVT, Op0, Op0IsKill);
     846             :   default: return 0;
     847             :   }
     848             : }
     849             : 
     850             : // FastEmit functions for ARMISD::VREV16.
     851             : 
     852             : unsigned fastEmit_ARMISD_VREV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     853           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     854             :     return 0;
     855           0 :   if ((Subtarget->hasNEON())) {
     856           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     857             :   }
     858             :   return 0;
     859             : }
     860             : 
     861             : unsigned fastEmit_ARMISD_VREV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     862           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     863             :     return 0;
     864           0 :   if ((Subtarget->hasNEON())) {
     865           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     866             :   }
     867             :   return 0;
     868             : }
     869             : 
     870           0 : unsigned fastEmit_ARMISD_VREV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     871           0 :   switch (VT.SimpleTy) {
     872           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     873           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     874             :   default: return 0;
     875             :   }
     876             : }
     877             : 
     878             : // FastEmit functions for ARMISD::VREV32.
     879             : 
     880             : unsigned fastEmit_ARMISD_VREV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     881           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     882             :     return 0;
     883           0 :   if ((Subtarget->hasNEON())) {
     884           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     885             :   }
     886             :   return 0;
     887             : }
     888             : 
     889             : unsigned fastEmit_ARMISD_VREV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     890           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     891             :     return 0;
     892           0 :   if ((Subtarget->hasNEON())) {
     893           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     894             :   }
     895             :   return 0;
     896             : }
     897             : 
     898             : unsigned fastEmit_ARMISD_VREV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     899           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     900             :     return 0;
     901           0 :   if ((Subtarget->hasNEON())) {
     902           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
     903             :   }
     904             :   return 0;
     905             : }
     906             : 
     907             : unsigned fastEmit_ARMISD_VREV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     908           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     909             :     return 0;
     910           0 :   if ((Subtarget->hasNEON())) {
     911           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
     912             :   }
     913             :   return 0;
     914             : }
     915             : 
     916           0 : unsigned fastEmit_ARMISD_VREV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     917           0 :   switch (VT.SimpleTy) {
     918           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     919           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     920           0 :   case MVT::v4i16: return fastEmit_ARMISD_VREV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     921           0 :   case MVT::v8i16: return fastEmit_ARMISD_VREV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     922             :   default: return 0;
     923             :   }
     924             : }
     925             : 
     926             : // FastEmit functions for ARMISD::VREV64.
     927             : 
     928             : unsigned fastEmit_ARMISD_VREV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     929           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     930             :     return 0;
     931           0 :   if ((Subtarget->hasNEON())) {
     932           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     933             :   }
     934             :   return 0;
     935             : }
     936             : 
     937             : unsigned fastEmit_ARMISD_VREV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     938           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     939             :     return 0;
     940           0 :   if ((Subtarget->hasNEON())) {
     941           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     942             :   }
     943             :   return 0;
     944             : }
     945             : 
     946             : unsigned fastEmit_ARMISD_VREV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     947           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     948             :     return 0;
     949           0 :   if ((Subtarget->hasNEON())) {
     950           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
     951             :   }
     952             :   return 0;
     953             : }
     954             : 
     955             : unsigned fastEmit_ARMISD_VREV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     956           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     957             :     return 0;
     958           0 :   if ((Subtarget->hasNEON())) {
     959           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
     960             :   }
     961             :   return 0;
     962             : }
     963             : 
     964             : unsigned fastEmit_ARMISD_VREV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     965           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     966             :     return 0;
     967           0 :   if ((Subtarget->hasNEON())) {
     968           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
     969             :   }
     970             :   return 0;
     971             : }
     972             : 
     973             : unsigned fastEmit_ARMISD_VREV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     974           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     975             :     return 0;
     976           0 :   if ((Subtarget->hasNEON())) {
     977           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
     978             :   }
     979             :   return 0;
     980             : }
     981             : 
     982             : unsigned fastEmit_ARMISD_VREV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     983           0 :   if (RetVT.SimpleTy != MVT::v2f32)
     984             :     return 0;
     985           0 :   return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
     986             : }
     987             : 
     988             : unsigned fastEmit_ARMISD_VREV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     989           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     990             :     return 0;
     991           0 :   return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
     992             : }
     993             : 
     994           0 : unsigned fastEmit_ARMISD_VREV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     995           0 :   switch (VT.SimpleTy) {
     996           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     997           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     998           0 :   case MVT::v4i16: return fastEmit_ARMISD_VREV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     999           0 :   case MVT::v8i16: return fastEmit_ARMISD_VREV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1000           0 :   case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1001           0 :   case MVT::v4i32: return fastEmit_ARMISD_VREV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1002           0 :   case MVT::v2f32: return fastEmit_ARMISD_VREV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    1003           0 :   case MVT::v4f32: return fastEmit_ARMISD_VREV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1004             :   default: return 0;
    1005             :   }
    1006             : }
    1007             : 
    1008             : // FastEmit functions for ARMISD::WIN__DBZCHK.
    1009             : 
    1010             : unsigned fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1011           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1012             :     return 0;
    1013           0 :   return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill);
    1014             : }
    1015             : 
    1016             : unsigned fastEmit_ARMISD_WIN__DBZCHK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1017           0 :   switch (VT.SimpleTy) {
    1018           0 :   case MVT::i32: return fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1019             :   default: return 0;
    1020             :   }
    1021             : }
    1022             : 
    1023             : // FastEmit functions for ISD::ABS.
    1024             : 
    1025             : unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1026           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    1027             :     return 0;
    1028           0 :   if ((Subtarget->hasNEON())) {
    1029           0 :     return fastEmitInst_r(ARM::VABSv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1030             :   }
    1031             :   return 0;
    1032             : }
    1033             : 
    1034             : unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1035           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1036             :     return 0;
    1037           0 :   if ((Subtarget->hasNEON())) {
    1038           0 :     return fastEmitInst_r(ARM::VABSv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1039             :   }
    1040             :   return 0;
    1041             : }
    1042             : 
    1043             : unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1044           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    1045             :     return 0;
    1046           0 :   if ((Subtarget->hasNEON())) {
    1047           0 :     return fastEmitInst_r(ARM::VABSv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1048             :   }
    1049             :   return 0;
    1050             : }
    1051             : 
    1052             : unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1053           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1054             :     return 0;
    1055           0 :   if ((Subtarget->hasNEON())) {
    1056           0 :     return fastEmitInst_r(ARM::VABSv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1057             :   }
    1058             :   return 0;
    1059             : }
    1060             : 
    1061             : unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1062           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    1063             :     return 0;
    1064           0 :   if ((Subtarget->hasNEON())) {
    1065           0 :     return fastEmitInst_r(ARM::VABSv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1066             :   }
    1067             :   return 0;
    1068             : }
    1069             : 
    1070             : unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1071           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1072             :     return 0;
    1073           0 :   if ((Subtarget->hasNEON())) {
    1074           0 :     return fastEmitInst_r(ARM::VABSv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1075             :   }
    1076             :   return 0;
    1077             : }
    1078             : 
    1079           0 : unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1080           0 :   switch (VT.SimpleTy) {
    1081           0 :   case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1082           0 :   case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1083           0 :   case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1084           0 :   case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1085           0 :   case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1086           0 :   case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1087             :   default: return 0;
    1088             :   }
    1089             : }
    1090             : 
    1091             : // FastEmit functions for ISD::ANY_EXTEND.
    1092             : 
    1093             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1094           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1095             :     return 0;
    1096           0 :   return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1097             : }
    1098             : 
    1099             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1100           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1101             :     return 0;
    1102           0 :   return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1103             : }
    1104             : 
    1105             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1106           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1107             :     return 0;
    1108           0 :   return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    1109             : }
    1110             : 
    1111           0 : unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1112           0 :   switch (VT.SimpleTy) {
    1113           0 :   case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1114           0 :   case MVT::v4i16: return fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1115           0 :   case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1116             :   default: return 0;
    1117             :   }
    1118             : }
    1119             : 
    1120             : // FastEmit functions for ISD::BITCAST.
    1121             : 
    1122           0 : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1123           0 :   if (RetVT.SimpleTy != MVT::f32)
    1124             :     return 0;
    1125           0 :   if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
    1126           0 :     return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
    1127             :   }
    1128             :   return 0;
    1129             : }
    1130             : 
    1131             : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1132          81 :   if (RetVT.SimpleTy != MVT::i32)
    1133             :     return 0;
    1134          81 :   if ((Subtarget->hasVFP2())) {
    1135          81 :     return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill);
    1136             :   }
    1137             :   return 0;
    1138             : }
    1139             : 
    1140           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1141           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1142           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1143             :   }
    1144             :   return 0;
    1145             : }
    1146             : 
    1147           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1148           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1149           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1150             :   }
    1151             :   return 0;
    1152             : }
    1153             : 
    1154           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1155           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1156           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1157             :   }
    1158             :   return 0;
    1159             : }
    1160             : 
    1161           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1162           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1163           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1164             :   }
    1165             :   return 0;
    1166             : }
    1167             : 
    1168           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1169           0 : switch (RetVT.SimpleTy) {
    1170           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill);
    1171           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill);
    1172           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill);
    1173           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill);
    1174             :   default: return 0;
    1175             : }
    1176             : }
    1177             : 
    1178           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1179           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1180           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1181             :   }
    1182             :   return 0;
    1183             : }
    1184             : 
    1185           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1186           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1187           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1188             :   }
    1189             :   return 0;
    1190             : }
    1191             : 
    1192           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1193           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1194           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1195             :   }
    1196             :   return 0;
    1197             : }
    1198             : 
    1199           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1200           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1201           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1202             :   }
    1203             :   return 0;
    1204             : }
    1205             : 
    1206           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1207           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1208           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1209             :   }
    1210             :   return 0;
    1211             : }
    1212             : 
    1213           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1214           0 : switch (RetVT.SimpleTy) {
    1215           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill);
    1216           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill);
    1217           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill);
    1218           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill);
    1219           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill);
    1220             :   default: return 0;
    1221             : }
    1222             : }
    1223             : 
    1224           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1225           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1226           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1227             :   }
    1228             :   return 0;
    1229             : }
    1230             : 
    1231           2 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1232           2 :   if ((MF->getDataLayout().isBigEndian())) {
    1233           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1234             :   }
    1235             :   return 0;
    1236             : }
    1237             : 
    1238           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1239           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1240           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1241             :   }
    1242             :   return 0;
    1243             : }
    1244             : 
    1245           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1246           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1247           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1248             :   }
    1249             :   return 0;
    1250             : }
    1251             : 
    1252           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1253           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1254           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1255             :   }
    1256             :   return 0;
    1257             : }
    1258             : 
    1259           2 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1260           2 : switch (RetVT.SimpleTy) {
    1261           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill);
    1262           2 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
    1263           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
    1264           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill);
    1265           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill);
    1266             :   default: return 0;
    1267             : }
    1268             : }
    1269             : 
    1270           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1271           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1272           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1273             :   }
    1274             :   return 0;
    1275             : }
    1276             : 
    1277           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1278           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1279           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1280             :   }
    1281             :   return 0;
    1282             : }
    1283             : 
    1284           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1285           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1286           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1287             :   }
    1288             :   return 0;
    1289             : }
    1290             : 
    1291           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1292           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1293           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1294             :   }
    1295             :   return 0;
    1296             : }
    1297             : 
    1298           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1299           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1300           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1301             :   }
    1302             :   return 0;
    1303             : }
    1304             : 
    1305           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1306           0 : switch (RetVT.SimpleTy) {
    1307           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill);
    1308           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill);
    1309           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill);
    1310           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill);
    1311           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill);
    1312             :   default: return 0;
    1313             : }
    1314             : }
    1315             : 
    1316           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1317           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1318           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1319             :   }
    1320             :   return 0;
    1321             : }
    1322             : 
    1323           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1324           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1325           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1326             :   }
    1327             :   return 0;
    1328             : }
    1329             : 
    1330           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1331           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1332           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1333             :   }
    1334             :   return 0;
    1335             : }
    1336             : 
    1337           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1338           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1339           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1340             :   }
    1341             :   return 0;
    1342             : }
    1343             : 
    1344           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1345           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1346           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1347             :   }
    1348             :   return 0;
    1349             : }
    1350             : 
    1351           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1352           0 : switch (RetVT.SimpleTy) {
    1353           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill);
    1354           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
    1355           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
    1356           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill);
    1357           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill);
    1358             :   default: return 0;
    1359             : }
    1360             : }
    1361             : 
    1362           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1363           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1364           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1365             :   }
    1366             :   return 0;
    1367             : }
    1368             : 
    1369           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1370           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1371           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1372             :   }
    1373             :   return 0;
    1374             : }
    1375             : 
    1376           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1377           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1378           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1379             :   }
    1380             :   return 0;
    1381             : }
    1382             : 
    1383           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1384           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1385           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1386             :   }
    1387             :   return 0;
    1388             : }
    1389             : 
    1390           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1391           0 : switch (RetVT.SimpleTy) {
    1392           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill);
    1393           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill);
    1394           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill);
    1395           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill);
    1396             :   default: return 0;
    1397             : }
    1398             : }
    1399             : 
    1400           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1401           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1402           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1403             :   }
    1404             :   return 0;
    1405             : }
    1406             : 
    1407           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1408           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1409           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1410             :   }
    1411             :   return 0;
    1412             : }
    1413             : 
    1414           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1415           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1416           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1417             :   }
    1418             :   return 0;
    1419             : }
    1420             : 
    1421           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1422           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1423           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1424             :   }
    1425             :   return 0;
    1426             : }
    1427             : 
    1428           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1429           0 : switch (RetVT.SimpleTy) {
    1430           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill);
    1431           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill);
    1432           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill);
    1433           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill);
    1434             :   default: return 0;
    1435             : }
    1436             : }
    1437             : 
    1438           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1439           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1440           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1441             :   }
    1442             :   return 0;
    1443             : }
    1444             : 
    1445           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1446           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1447           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1448             :   }
    1449             :   return 0;
    1450             : }
    1451             : 
    1452           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1453           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1454           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1455             :   }
    1456             :   return 0;
    1457             : }
    1458             : 
    1459           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1460           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1461           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1462             :   }
    1463             :   return 0;
    1464             : }
    1465             : 
    1466           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1467           0 : switch (RetVT.SimpleTy) {
    1468           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill);
    1469           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill);
    1470           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill);
    1471           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill);
    1472             :   default: return 0;
    1473             : }
    1474             : }
    1475             : 
    1476           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1477           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1478           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1479             :   }
    1480             :   return 0;
    1481             : }
    1482             : 
    1483           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1484           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1485           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1486             :   }
    1487             :   return 0;
    1488             : }
    1489             : 
    1490           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1491           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1492           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1493             :   }
    1494             :   return 0;
    1495             : }
    1496             : 
    1497           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1498           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1499           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1500             :   }
    1501             :   return 0;
    1502             : }
    1503             : 
    1504           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1505           0 : switch (RetVT.SimpleTy) {
    1506           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill);
    1507           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill);
    1508           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill);
    1509           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill);
    1510             :   default: return 0;
    1511             : }
    1512             : }
    1513             : 
    1514           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1515           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1516           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1517             :   }
    1518             :   return 0;
    1519             : }
    1520             : 
    1521           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1522           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1523           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1524             :   }
    1525             :   return 0;
    1526             : }
    1527             : 
    1528           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1529           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1530           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1531             :   }
    1532             :   return 0;
    1533             : }
    1534             : 
    1535           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1536           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1537           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1538             :   }
    1539             :   return 0;
    1540             : }
    1541             : 
    1542           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1543           0 : switch (RetVT.SimpleTy) {
    1544           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill);
    1545           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill);
    1546           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill);
    1547           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill);
    1548             :   default: return 0;
    1549             : }
    1550             : }
    1551             : 
    1552           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1553           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1554           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1555             :   }
    1556             :   return 0;
    1557             : }
    1558             : 
    1559           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1560           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1561           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1562             :   }
    1563             :   return 0;
    1564             : }
    1565             : 
    1566           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1567           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1568           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1569             :   }
    1570             :   return 0;
    1571             : }
    1572             : 
    1573           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1574           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1575           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1576             :   }
    1577             :   return 0;
    1578             : }
    1579             : 
    1580           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1581           0 : switch (RetVT.SimpleTy) {
    1582           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill);
    1583           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill);
    1584           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill);
    1585           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill);
    1586             :   default: return 0;
    1587             : }
    1588             : }
    1589             : 
    1590           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1591           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1592           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1593             :   }
    1594             :   return 0;
    1595             : }
    1596             : 
    1597           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1598           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1599           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1600             :   }
    1601             :   return 0;
    1602             : }
    1603             : 
    1604           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1605           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1606           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1607             :   }
    1608             :   return 0;
    1609             : }
    1610             : 
    1611           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1612           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1613           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1614             :   }
    1615             :   return 0;
    1616             : }
    1617             : 
    1618           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1619           0 : switch (RetVT.SimpleTy) {
    1620           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill);
    1621           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill);
    1622           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill);
    1623           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill);
    1624             :   default: return 0;
    1625             : }
    1626             : }
    1627             : 
    1628          83 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1629          83 :   switch (VT.SimpleTy) {
    1630           0 :   case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1631          81 :   case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1632           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1633           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1634           2 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1635           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1636           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1637           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1638           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1639           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
    1640           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1641           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    1642           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1643           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1644             :   default: return 0;
    1645             :   }
    1646             : }
    1647             : 
    1648             : // FastEmit functions for ISD::BITREVERSE.
    1649             : 
    1650           0 : unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1651           0 :   if (RetVT.SimpleTy != MVT::i32)
    1652             :     return 0;
    1653           0 :   if ((Subtarget->isThumb2())) {
    1654           0 :     return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1655             :   }
    1656           0 :   if ((Subtarget->hasV6T2Ops()) && (!Subtarget->isThumb())) {
    1657           0 :     return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill);
    1658             :   }
    1659             :   return 0;
    1660             : }
    1661             : 
    1662             : unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1663           0 :   switch (VT.SimpleTy) {
    1664           0 :   case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1665             :   default: return 0;
    1666             :   }
    1667             : }
    1668             : 
    1669             : // FastEmit functions for ISD::BRIND.
    1670             : 
    1671           0 : unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1672           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1673             :     return 0;
    1674           0 :   if ((Subtarget->isThumb())) {
    1675           0 :     return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill);
    1676             :   }
    1677           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
    1678           0 :     return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill);
    1679             :   }
    1680           0 :   if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
    1681           0 :     return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill);
    1682             :   }
    1683             :   return 0;
    1684             : }
    1685             : 
    1686             : unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1687           0 :   switch (VT.SimpleTy) {
    1688           0 :   case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1689             :   default: return 0;
    1690             :   }
    1691             : }
    1692             : 
    1693             : // FastEmit functions for ISD::BSWAP.
    1694             : 
    1695           0 : unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1696           0 :   if (RetVT.SimpleTy != MVT::i32)
    1697             :     return 0;
    1698           0 :   if ((Subtarget->isThumb2())) {
    1699           0 :     return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1700             :   }
    1701           0 :   if ((Subtarget->hasV6Ops()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    1702           0 :     return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill);
    1703             :   }
    1704           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    1705           0 :     return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill);
    1706             :   }
    1707             :   return 0;
    1708             : }
    1709             : 
    1710             : unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1711           0 :   switch (VT.SimpleTy) {
    1712           0 :   case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1713             :   default: return 0;
    1714             :   }
    1715             : }
    1716             : 
    1717             : // FastEmit functions for ISD::CTLZ.
    1718             : 
    1719           0 : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1720           0 :   if (RetVT.SimpleTy != MVT::i32)
    1721             :     return 0;
    1722           0 :   if ((Subtarget->isThumb2())) {
    1723           0 :     return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1724             :   }
    1725           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
    1726           0 :     return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill);
    1727             :   }
    1728             :   return 0;
    1729             : }
    1730             : 
    1731             : unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1732           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    1733             :     return 0;
    1734           0 :   if ((Subtarget->hasNEON())) {
    1735           0 :     return fastEmitInst_r(ARM::VCLZv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1736             :   }
    1737             :   return 0;
    1738             : }
    1739             : 
    1740             : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1741           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1742             :     return 0;
    1743           0 :   if ((Subtarget->hasNEON())) {
    1744           0 :     return fastEmitInst_r(ARM::VCLZv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1745             :   }
    1746             :   return 0;
    1747             : }
    1748             : 
    1749             : unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1750           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    1751             :     return 0;
    1752           0 :   if ((Subtarget->hasNEON())) {
    1753           0 :     return fastEmitInst_r(ARM::VCLZv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1754             :   }
    1755             :   return 0;
    1756             : }
    1757             : 
    1758             : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1759           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1760             :     return 0;
    1761           0 :   if ((Subtarget->hasNEON())) {
    1762           0 :     return fastEmitInst_r(ARM::VCLZv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1763             :   }
    1764             :   return 0;
    1765             : }
    1766             : 
    1767             : unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1768           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    1769             :     return 0;
    1770           0 :   if ((Subtarget->hasNEON())) {
    1771           0 :     return fastEmitInst_r(ARM::VCLZv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1772             :   }
    1773             :   return 0;
    1774             : }
    1775             : 
    1776             : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1777           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1778             :     return 0;
    1779           0 :   if ((Subtarget->hasNEON())) {
    1780           0 :     return fastEmitInst_r(ARM::VCLZv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1781             :   }
    1782             :   return 0;
    1783             : }
    1784             : 
    1785           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1786           0 :   switch (VT.SimpleTy) {
    1787           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1788           0 :   case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1789           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1790           0 :   case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1791           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1792           0 :   case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1793           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1794             :   default: return 0;
    1795             :   }
    1796             : }
    1797             : 
    1798             : // FastEmit functions for ISD::CTPOP.
    1799             : 
    1800             : unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1801           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    1802             :     return 0;
    1803           0 :   if ((Subtarget->hasNEON())) {
    1804           0 :     return fastEmitInst_r(ARM::VCNTd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1805             :   }
    1806             :   return 0;
    1807             : }
    1808             : 
    1809             : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1810           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1811             :     return 0;
    1812           0 :   if ((Subtarget->hasNEON())) {
    1813           0 :     return fastEmitInst_r(ARM::VCNTq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1814             :   }
    1815             :   return 0;
    1816             : }
    1817             : 
    1818           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1819           0 :   switch (VT.SimpleTy) {
    1820           0 :   case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1821           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1822             :   default: return 0;
    1823             :   }
    1824             : }
    1825             : 
    1826             : // FastEmit functions for ISD::FABS.
    1827             : 
    1828           0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1829           0 :   if (RetVT.SimpleTy != MVT::f32)
    1830             :     return 0;
    1831           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    1832           0 :     return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1833             :   }
    1834             :   return 0;
    1835             : }
    1836             : 
    1837           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1838           0 :   if (RetVT.SimpleTy != MVT::f64)
    1839             :     return 0;
    1840           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    1841           0 :     return fastEmitInst_r(ARM::VABSD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1842             :   }
    1843             :   return 0;
    1844             : }
    1845             : 
    1846           0 : unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1847           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    1848             :     return 0;
    1849           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    1850           0 :     return fastEmitInst_r(ARM::VABShd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1851             :   }
    1852             :   return 0;
    1853             : }
    1854             : 
    1855           0 : unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1856           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    1857             :     return 0;
    1858           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    1859           0 :     return fastEmitInst_r(ARM::VABShq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1860             :   }
    1861             :   return 0;
    1862             : }
    1863             : 
    1864             : unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1865           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    1866             :     return 0;
    1867           0 :   if ((Subtarget->hasNEON())) {
    1868           0 :     return fastEmitInst_r(ARM::VABSfd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1869             :   }
    1870             :   return 0;
    1871             : }
    1872             : 
    1873             : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1874           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1875             :     return 0;
    1876           0 :   if ((Subtarget->hasNEON())) {
    1877           0 :     return fastEmitInst_r(ARM::VABSfq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1878             :   }
    1879             :   return 0;
    1880             : }
    1881             : 
    1882           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1883           0 :   switch (VT.SimpleTy) {
    1884           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1885           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1886           0 :   case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    1887           0 :   case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    1888           0 :   case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    1889           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1890             :   default: return 0;
    1891             :   }
    1892             : }
    1893             : 
    1894             : // FastEmit functions for ISD::FCEIL.
    1895             : 
    1896             : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1897           0 :   if (RetVT.SimpleTy != MVT::f32)
    1898             :     return 0;
    1899           0 :   if ((Subtarget->hasFPARMv8())) {
    1900           0 :     return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1901             :   }
    1902             :   return 0;
    1903             : }
    1904             : 
    1905           0 : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1906           0 :   if (RetVT.SimpleTy != MVT::f64)
    1907             :     return 0;
    1908           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    1909           0 :     return fastEmitInst_r(ARM::VRINTPD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1910             :   }
    1911             :   return 0;
    1912             : }
    1913             : 
    1914           0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1915           0 :   switch (VT.SimpleTy) {
    1916           0 :   case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1917           0 :   case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1918             :   default: return 0;
    1919             :   }
    1920             : }
    1921             : 
    1922             : // FastEmit functions for ISD::FFLOOR.
    1923             : 
    1924             : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1925           0 :   if (RetVT.SimpleTy != MVT::f32)
    1926             :     return 0;
    1927           0 :   if ((Subtarget->hasFPARMv8())) {
    1928           0 :     return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1929             :   }
    1930             :   return 0;
    1931             : }
    1932             : 
    1933           0 : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1934           0 :   if (RetVT.SimpleTy != MVT::f64)
    1935             :     return 0;
    1936           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    1937           0 :     return fastEmitInst_r(ARM::VRINTMD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1938             :   }
    1939             :   return 0;
    1940             : }
    1941             : 
    1942           0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1943           0 :   switch (VT.SimpleTy) {
    1944           0 :   case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1945           0 :   case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1946             :   default: return 0;
    1947             :   }
    1948             : }
    1949             : 
    1950             : // FastEmit functions for ISD::FNEARBYINT.
    1951             : 
    1952             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1953           0 :   if (RetVT.SimpleTy != MVT::f32)
    1954             :     return 0;
    1955           0 :   if ((Subtarget->hasFPARMv8())) {
    1956           0 :     return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1957             :   }
    1958             :   return 0;
    1959             : }
    1960             : 
    1961           0 : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1962           0 :   if (RetVT.SimpleTy != MVT::f64)
    1963             :     return 0;
    1964           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    1965           0 :     return fastEmitInst_r(ARM::VRINTRD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1966             :   }
    1967             :   return 0;
    1968             : }
    1969             : 
    1970           0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1971           0 :   switch (VT.SimpleTy) {
    1972           0 :   case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1973           0 :   case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1974             :   default: return 0;
    1975             :   }
    1976             : }
    1977             : 
    1978             : // FastEmit functions for ISD::FNEG.
    1979             : 
    1980             : unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1981           0 :   if (RetVT.SimpleTy != MVT::f16)
    1982             :     return 0;
    1983           0 :   if ((Subtarget->hasFullFP16())) {
    1984           0 :     return fastEmitInst_r(ARM::VNEGH, &ARM::HPRRegClass, Op0, Op0IsKill);
    1985             :   }
    1986             :   return 0;
    1987             : }
    1988             : 
    1989           0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1990           0 :   if (RetVT.SimpleTy != MVT::f32)
    1991             :     return 0;
    1992           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    1993           0 :     return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1994             :   }
    1995             :   return 0;
    1996             : }
    1997             : 
    1998           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1999           0 :   if (RetVT.SimpleTy != MVT::f64)
    2000             :     return 0;
    2001           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2002           0 :     return fastEmitInst_r(ARM::VNEGD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2003             :   }
    2004             :   return 0;
    2005             : }
    2006             : 
    2007           0 : unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2008           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    2009             :     return 0;
    2010           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2011           0 :     return fastEmitInst_r(ARM::VNEGhd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2012             :   }
    2013             :   return 0;
    2014             : }
    2015             : 
    2016           0 : unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2017           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    2018             :     return 0;
    2019           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2020           0 :     return fastEmitInst_r(ARM::VNEGhq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2021             :   }
    2022             :   return 0;
    2023             : }
    2024             : 
    2025             : unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2026           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    2027             :     return 0;
    2028           0 :   if ((Subtarget->hasNEON())) {
    2029           0 :     return fastEmitInst_r(ARM::VNEGfd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2030             :   }
    2031             :   return 0;
    2032             : }
    2033             : 
    2034             : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2035           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2036             :     return 0;
    2037           0 :   if ((Subtarget->hasNEON())) {
    2038           0 :     return fastEmitInst_r(ARM::VNEGf32q, &ARM::QPRRegClass, Op0, Op0IsKill);
    2039             :   }
    2040             :   return 0;
    2041             : }
    2042             : 
    2043           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2044           0 :   switch (VT.SimpleTy) {
    2045           0 :   case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill);
    2046           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2047           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2048           0 :   case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2049           0 :   case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2050           0 :   case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2051           0 :   case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2052             :   default: return 0;
    2053             :   }
    2054             : }
    2055             : 
    2056             : // FastEmit functions for ISD::FP_EXTEND.
    2057             : 
    2058           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2059           0 :   if (RetVT.SimpleTy != MVT::f64)
    2060             :     return 0;
    2061           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2062           0 :     return fastEmitInst_r(ARM::VCVTDS, &ARM::DPRRegClass, Op0, Op0IsKill);
    2063             :   }
    2064             :   return 0;
    2065             : }
    2066             : 
    2067             : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2068           0 :   switch (VT.SimpleTy) {
    2069           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2070             :   default: return 0;
    2071             :   }
    2072             : }
    2073             : 
    2074             : // FastEmit functions for ISD::FP_ROUND.
    2075             : 
    2076           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2077           0 :   if (RetVT.SimpleTy != MVT::f32)
    2078             :     return 0;
    2079           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2080           0 :     return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill);
    2081             :   }
    2082             :   return 0;
    2083             : }
    2084             : 
    2085             : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2086           0 :   switch (VT.SimpleTy) {
    2087           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2088             :   default: return 0;
    2089             :   }
    2090             : }
    2091             : 
    2092             : // FastEmit functions for ISD::FP_TO_SINT.
    2093             : 
    2094           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2095           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2096             :     return 0;
    2097           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2098           0 :     return fastEmitInst_r(ARM::VCVTh2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2099             :   }
    2100             :   return 0;
    2101             : }
    2102             : 
    2103           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2104           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2105             :     return 0;
    2106           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2107           0 :     return fastEmitInst_r(ARM::VCVTh2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2108             :   }
    2109             :   return 0;
    2110             : }
    2111             : 
    2112             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2113           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2114             :     return 0;
    2115           0 :   if ((Subtarget->hasNEON())) {
    2116           0 :     return fastEmitInst_r(ARM::VCVTf2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2117             :   }
    2118             :   return 0;
    2119             : }
    2120             : 
    2121             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2122           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2123             :     return 0;
    2124           0 :   if ((Subtarget->hasNEON())) {
    2125           0 :     return fastEmitInst_r(ARM::VCVTf2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2126             :   }
    2127             :   return 0;
    2128             : }
    2129             : 
    2130           6 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2131           6 :   switch (VT.SimpleTy) {
    2132           0 :   case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2133           0 :   case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2134           0 :   case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2135           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2136             :   default: return 0;
    2137             :   }
    2138             : }
    2139             : 
    2140             : // FastEmit functions for ISD::FP_TO_UINT.
    2141             : 
    2142           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2143           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2144             :     return 0;
    2145           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2146           0 :     return fastEmitInst_r(ARM::VCVTh2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
    2147             :   }
    2148             :   return 0;
    2149             : }
    2150             : 
    2151           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2152           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2153             :     return 0;
    2154           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2155           0 :     return fastEmitInst_r(ARM::VCVTh2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2156             :   }
    2157             :   return 0;
    2158             : }
    2159             : 
    2160             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2161           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2162             :     return 0;
    2163           0 :   if ((Subtarget->hasNEON())) {
    2164           0 :     return fastEmitInst_r(ARM::VCVTf2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
    2165             :   }
    2166             :   return 0;
    2167             : }
    2168             : 
    2169             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2170           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2171             :     return 0;
    2172           0 :   if ((Subtarget->hasNEON())) {
    2173           0 :     return fastEmitInst_r(ARM::VCVTf2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2174             :   }
    2175             :   return 0;
    2176             : }
    2177             : 
    2178           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2179           0 :   switch (VT.SimpleTy) {
    2180           0 :   case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2181           0 :   case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2182           0 :   case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2183           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2184             :   default: return 0;
    2185             :   }
    2186             : }
    2187             : 
    2188             : // FastEmit functions for ISD::FRINT.
    2189             : 
    2190             : unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2191           0 :   if (RetVT.SimpleTy != MVT::f32)
    2192             :     return 0;
    2193           0 :   if ((Subtarget->hasFPARMv8())) {
    2194           0 :     return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2195             :   }
    2196             :   return 0;
    2197             : }
    2198             : 
    2199           0 : unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2200           0 :   if (RetVT.SimpleTy != MVT::f64)
    2201             :     return 0;
    2202           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2203           0 :     return fastEmitInst_r(ARM::VRINTXD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2204             :   }
    2205             :   return 0;
    2206             : }
    2207             : 
    2208           0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2209           0 :   switch (VT.SimpleTy) {
    2210           0 :   case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2211           0 :   case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2212             :   default: return 0;
    2213             :   }
    2214             : }
    2215             : 
    2216             : // FastEmit functions for ISD::FROUND.
    2217             : 
    2218             : unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2219           0 :   if (RetVT.SimpleTy != MVT::f32)
    2220             :     return 0;
    2221           0 :   if ((Subtarget->hasFPARMv8())) {
    2222           0 :     return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2223             :   }
    2224             :   return 0;
    2225             : }
    2226             : 
    2227           0 : unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2228           0 :   if (RetVT.SimpleTy != MVT::f64)
    2229             :     return 0;
    2230           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2231           0 :     return fastEmitInst_r(ARM::VRINTAD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2232             :   }
    2233             :   return 0;
    2234             : }
    2235             : 
    2236           0 : unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2237           0 :   switch (VT.SimpleTy) {
    2238           0 :   case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2239           0 :   case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2240             :   default: return 0;
    2241             :   }
    2242             : }
    2243             : 
    2244             : // FastEmit functions for ISD::FSQRT.
    2245             : 
    2246             : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2247           0 :   if (RetVT.SimpleTy != MVT::f32)
    2248             :     return 0;
    2249           0 :   if ((Subtarget->hasVFP2())) {
    2250           0 :     return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2251             :   }
    2252             :   return 0;
    2253             : }
    2254             : 
    2255           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2256           0 :   if (RetVT.SimpleTy != MVT::f64)
    2257             :     return 0;
    2258           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2259           0 :     return fastEmitInst_r(ARM::VSQRTD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2260             :   }
    2261             :   return 0;
    2262             : }
    2263             : 
    2264           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2265           0 :   switch (VT.SimpleTy) {
    2266           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2267           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2268             :   default: return 0;
    2269             :   }
    2270             : }
    2271             : 
    2272             : // FastEmit functions for ISD::FTRUNC.
    2273             : 
    2274             : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2275           0 :   if (RetVT.SimpleTy != MVT::f32)
    2276             :     return 0;
    2277           0 :   if ((Subtarget->hasFPARMv8())) {
    2278           0 :     return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2279             :   }
    2280             :   return 0;
    2281             : }
    2282             : 
    2283           0 : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2284           0 :   if (RetVT.SimpleTy != MVT::f64)
    2285             :     return 0;
    2286           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2287           0 :     return fastEmitInst_r(ARM::VRINTZD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2288             :   }
    2289             :   return 0;
    2290             : }
    2291             : 
    2292           0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2293           0 :   switch (VT.SimpleTy) {
    2294           0 :   case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2295           0 :   case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2296             :   default: return 0;
    2297             :   }
    2298             : }
    2299             : 
    2300             : // FastEmit functions for ISD::SIGN_EXTEND.
    2301             : 
    2302             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2303           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2304             :     return 0;
    2305           0 :   if ((Subtarget->hasNEON())) {
    2306           0 :     return fastEmitInst_r(ARM::VMOVLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    2307             :   }
    2308             :   return 0;
    2309             : }
    2310             : 
    2311             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2312           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2313             :     return 0;
    2314           0 :   if ((Subtarget->hasNEON())) {
    2315           0 :     return fastEmitInst_r(ARM::VMOVLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    2316             :   }
    2317             :   return 0;
    2318             : }
    2319             : 
    2320             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2321           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2322             :     return 0;
    2323           0 :   if ((Subtarget->hasNEON())) {
    2324           0 :     return fastEmitInst_r(ARM::VMOVLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    2325             :   }
    2326             :   return 0;
    2327             : }
    2328             : 
    2329           1 : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2330           1 :   switch (VT.SimpleTy) {
    2331           0 :   case MVT::v8i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    2332           0 :   case MVT::v4i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2333           0 :   case MVT::v2i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2334             :   default: return 0;
    2335             :   }
    2336             : }
    2337             : 
    2338             : // FastEmit functions for ISD::SINT_TO_FP.
    2339             : 
    2340           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2341           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    2342             :     return 0;
    2343           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2344           0 :     return fastEmitInst_r(ARM::VCVTs2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2345             :   }
    2346             :   return 0;
    2347             : }
    2348             : 
    2349           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2350           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    2351             :     return 0;
    2352           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2353           0 :     return fastEmitInst_r(ARM::VCVTs2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2354             :   }
    2355             :   return 0;
    2356             : }
    2357             : 
    2358             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2359           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    2360             :     return 0;
    2361           0 :   if ((Subtarget->hasNEON())) {
    2362           0 :     return fastEmitInst_r(ARM::VCVTs2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2363             :   }
    2364             :   return 0;
    2365             : }
    2366             : 
    2367             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2368           2 :   if (RetVT.SimpleTy != MVT::v4f32)
    2369             :     return 0;
    2370           2 :   if ((Subtarget->hasNEON())) {
    2371           2 :     return fastEmitInst_r(ARM::VCVTs2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2372             :   }
    2373             :   return 0;
    2374             : }
    2375             : 
    2376           9 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2377           9 :   switch (VT.SimpleTy) {
    2378           0 :   case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2379           0 :   case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2380           0 :   case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2381           2 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2382             :   default: return 0;
    2383             :   }
    2384             : }
    2385             : 
    2386             : // FastEmit functions for ISD::TRUNCATE.
    2387             : 
    2388             : unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2389           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2390             :     return 0;
    2391           0 :   if ((Subtarget->hasNEON())) {
    2392           0 :     return fastEmitInst_r(ARM::VMOVNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
    2393             :   }
    2394             :   return 0;
    2395             : }
    2396             : 
    2397             : unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2398           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2399             :     return 0;
    2400           0 :   if ((Subtarget->hasNEON())) {
    2401           0 :     return fastEmitInst_r(ARM::VMOVNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    2402             :   }
    2403             :   return 0;
    2404             : }
    2405             : 
    2406             : unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2407           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2408             :     return 0;
    2409           0 :   if ((Subtarget->hasNEON())) {
    2410           0 :     return fastEmitInst_r(ARM::VMOVNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    2411             :   }
    2412             :   return 0;
    2413             : }
    2414             : 
    2415           0 : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2416           0 :   switch (VT.SimpleTy) {
    2417           0 :   case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2418           0 :   case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2419           0 :   case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    2420             :   default: return 0;
    2421             :   }
    2422             : }
    2423             : 
    2424             : // FastEmit functions for ISD::UINT_TO_FP.
    2425             : 
    2426           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2427           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    2428             :     return 0;
    2429           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2430           0 :     return fastEmitInst_r(ARM::VCVTu2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2431             :   }
    2432             :   return 0;
    2433             : }
    2434             : 
    2435           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2436           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    2437             :     return 0;
    2438           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2439           0 :     return fastEmitInst_r(ARM::VCVTu2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2440             :   }
    2441             :   return 0;
    2442             : }
    2443             : 
    2444             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2445           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    2446             :     return 0;
    2447           0 :   if ((Subtarget->hasNEON())) {
    2448           0 :     return fastEmitInst_r(ARM::VCVTu2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2449             :   }
    2450             :   return 0;
    2451             : }
    2452             : 
    2453             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2454           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2455             :     return 0;
    2456           0 :   if ((Subtarget->hasNEON())) {
    2457           0 :     return fastEmitInst_r(ARM::VCVTu2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2458             :   }
    2459             :   return 0;
    2460             : }
    2461             : 
    2462           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2463           0 :   switch (VT.SimpleTy) {
    2464           0 :   case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2465           0 :   case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2466           0 :   case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2467           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2468             :   default: return 0;
    2469             :   }
    2470             : }
    2471             : 
    2472             : // FastEmit functions for ISD::ZERO_EXTEND.
    2473             : 
    2474             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2475           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2476             :     return 0;
    2477           0 :   if ((Subtarget->hasNEON())) {
    2478           0 :     return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    2479             :   }
    2480             :   return 0;
    2481             : }
    2482             : 
    2483             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2484           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2485             :     return 0;
    2486           0 :   if ((Subtarget->hasNEON())) {
    2487           0 :     return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    2488             :   }
    2489             :   return 0;
    2490             : }
    2491             : 
    2492             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2493           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2494             :     return 0;
    2495           0 :   if ((Subtarget->hasNEON())) {
    2496           0 :     return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    2497             :   }
    2498             :   return 0;
    2499             : }
    2500             : 
    2501           0 : unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2502           0 :   switch (VT.SimpleTy) {
    2503           0 :   case MVT::v8i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    2504           0 :   case MVT::v4i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2505           0 :   case MVT::v2i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2506             :   default: return 0;
    2507             :   }
    2508             : }
    2509             : 
    2510             : // Top-level FastEmit function.
    2511             : 
    2512          99 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    2513          99 :   switch (Opcode) {
    2514           0 :   case ARMISD::CALL: return fastEmit_ARMISD_CALL_r(VT, RetVT, Op0, Op0IsKill);
    2515           0 :   case ARMISD::CALL_NOLINK: return fastEmit_ARMISD_CALL_NOLINK_r(VT, RetVT, Op0, Op0IsKill);
    2516           0 :   case ARMISD::CALL_PRED: return fastEmit_ARMISD_CALL_PRED_r(VT, RetVT, Op0, Op0IsKill);
    2517           0 :   case ARMISD::RRX: return fastEmit_ARMISD_RRX_r(VT, RetVT, Op0, Op0IsKill);
    2518           0 :   case ARMISD::SRA_FLAG: return fastEmit_ARMISD_SRA_FLAG_r(VT, RetVT, Op0, Op0IsKill);
    2519           0 :   case ARMISD::SRL_FLAG: return fastEmit_ARMISD_SRL_FLAG_r(VT, RetVT, Op0, Op0IsKill);
    2520           0 :   case ARMISD::TC_RETURN: return fastEmit_ARMISD_TC_RETURN_r(VT, RetVT, Op0, Op0IsKill);
    2521           0 :   case ARMISD::VCEQZ: return fastEmit_ARMISD_VCEQZ_r(VT, RetVT, Op0, Op0IsKill);
    2522           0 :   case ARMISD::VCGEZ: return fastEmit_ARMISD_VCGEZ_r(VT, RetVT, Op0, Op0IsKill);
    2523           0 :   case ARMISD::VCGTZ: return fastEmit_ARMISD_VCGTZ_r(VT, RetVT, Op0, Op0IsKill);
    2524           0 :   case ARMISD::VCLEZ: return fastEmit_ARMISD_VCLEZ_r(VT, RetVT, Op0, Op0IsKill);
    2525           0 :   case ARMISD::VCLTZ: return fastEmit_ARMISD_VCLTZ_r(VT, RetVT, Op0, Op0IsKill);
    2526           0 :   case ARMISD::VDUP: return fastEmit_ARMISD_VDUP_r(VT, RetVT, Op0, Op0IsKill);
    2527           0 :   case ARMISD::VMOVhr: return fastEmit_ARMISD_VMOVhr_r(VT, RetVT, Op0, Op0IsKill);
    2528           0 :   case ARMISD::VMOVrh: return fastEmit_ARMISD_VMOVrh_r(VT, RetVT, Op0, Op0IsKill);
    2529           0 :   case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill);
    2530           0 :   case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill);
    2531           0 :   case ARMISD::VREV64: return fastEmit_ARMISD_VREV64_r(VT, RetVT, Op0, Op0IsKill);
    2532           0 :   case ARMISD::WIN__DBZCHK: return fastEmit_ARMISD_WIN__DBZCHK_r(VT, RetVT, Op0, Op0IsKill);
    2533           0 :   case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill);
    2534           0 :   case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2535          83 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    2536           0 :   case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill);
    2537           0 :   case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
    2538           0 :   case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill);
    2539           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    2540           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    2541           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    2542           0 :   case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
    2543           0 :   case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
    2544           0 :   case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
    2545           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    2546           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2547           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    2548           6 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    2549           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    2550           0 :   case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
    2551           0 :   case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill);
    2552           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    2553           0 :   case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
    2554           1 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2555           9 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    2556           0 :   case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
    2557           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    2558           0 :   case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2559             :   default: return 0;
    2560             :   }
    2561             : }
    2562             : 
    2563             : // FastEmit functions for ARMISD::CMP.
    2564             : 
    2565           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2566           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2567             :     return 0;
    2568           0 :   if ((Subtarget->isThumb2())) {
    2569           0 :     return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2570             :   }
    2571           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2572           0 :     return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2573             :   }
    2574           0 :   if ((!Subtarget->isThumb())) {
    2575           0 :     return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2576             :   }
    2577             :   return 0;
    2578             : }
    2579             : 
    2580             : unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2581           0 :   switch (VT.SimpleTy) {
    2582           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2583             :   default: return 0;
    2584             :   }
    2585             : }
    2586             : 
    2587             : // FastEmit functions for ARMISD::CMPZ.
    2588             : 
    2589           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2590           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2591             :     return 0;
    2592           0 :   if ((Subtarget->isThumb2())) {
    2593           0 :     return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2594             :   }
    2595           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2596           0 :     return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2597             :   }
    2598           0 :   if ((!Subtarget->isThumb())) {
    2599           0 :     return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2600             :   }
    2601             :   return 0;
    2602             : }
    2603             : 
    2604             : unsigned fastEmit_ARMISD_CMPZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2605           0 :   switch (VT.SimpleTy) {
    2606           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2607             :   default: return 0;
    2608             :   }
    2609             : }
    2610             : 
    2611             : // FastEmit functions for ARMISD::EH_SJLJ_LONGJMP.
    2612             : 
    2613           0 : unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2614           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2615             :     return 0;
    2616           0 :   if ((Subtarget->isThumb()) && (Subtarget->isTargetWindows())) {
    2617           0 :     return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2618             :   }
    2619           0 :   if ((!Subtarget->isTargetWindows()) && (Subtarget->isThumb())) {
    2620           0 :     return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2621             :   }
    2622           0 :   if ((!Subtarget->isThumb())) {
    2623           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2624             :   }
    2625             :   return 0;
    2626             : }
    2627             : 
    2628             : unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2629           0 :   switch (VT.SimpleTy) {
    2630           0 :   case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2631             :   default: return 0;
    2632             :   }
    2633             : }
    2634             : 
    2635             : // FastEmit functions for ARMISD::EH_SJLJ_SETJMP.
    2636             : 
    2637           0 : unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2638           0 :   if (RetVT.SimpleTy != MVT::i32)
    2639             :     return 0;
    2640           0 :   if ((Subtarget->isThumb2()) && (!Subtarget->hasVFP2())) {
    2641           0 :     return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2642             :   }
    2643           0 :   if ((Subtarget->hasVFP2()) && (Subtarget->isThumb2())) {
    2644           0 :     return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2645             :   }
    2646           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2647           0 :     return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2648             :   }
    2649           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasVFP2())) {
    2650           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2651             :   }
    2652           0 :   if ((Subtarget->hasVFP2()) && (!Subtarget->isThumb())) {
    2653           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2654             :   }
    2655             :   return 0;
    2656             : }
    2657             : 
    2658             : unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2659           0 :   switch (VT.SimpleTy) {
    2660           0 :   case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2661             :   default: return 0;
    2662             :   }
    2663             : }
    2664             : 
    2665             : // FastEmit functions for ARMISD::SMULWB.
    2666             : 
    2667           0 : unsigned fastEmit_ARMISD_SMULWB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2668           0 :   if (RetVT.SimpleTy != MVT::i32)
    2669             :     return 0;
    2670           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    2671           0 :     return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2672             :   }
    2673           0 :   if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
    2674           0 :     return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2675             :   }
    2676             :   return 0;
    2677             : }
    2678             : 
    2679             : unsigned fastEmit_ARMISD_SMULWB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2680           0 :   switch (VT.SimpleTy) {
    2681           0 :   case MVT::i32: return fastEmit_ARMISD_SMULWB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2682             :   default: return 0;
    2683             :   }
    2684             : }
    2685             : 
    2686             : // FastEmit functions for ARMISD::SMULWT.
    2687             : 
    2688           0 : unsigned fastEmit_ARMISD_SMULWT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2689           0 :   if (RetVT.SimpleTy != MVT::i32)
    2690             :     return 0;
    2691           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    2692           0 :     return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2693             :   }
    2694           0 :   if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
    2695           0 :     return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2696             :   }
    2697             :   return 0;
    2698             : }
    2699             : 
    2700             : unsigned fastEmit_ARMISD_SMULWT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2701           0 :   switch (VT.SimpleTy) {
    2702           0 :   case MVT::i32: return fastEmit_ARMISD_SMULWT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2703             :   default: return 0;
    2704             :   }
    2705             : }
    2706             : 
    2707             : // FastEmit functions for ARMISD::VCEQ.
    2708             : 
    2709             : unsigned fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2710           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2711             :     return 0;
    2712           0 :   if ((Subtarget->hasNEON())) {
    2713           0 :     return fastEmitInst_rr(ARM::VCEQv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2714             :   }
    2715             :   return 0;
    2716             : }
    2717             : 
    2718             : unsigned fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2719           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2720             :     return 0;
    2721           0 :   if ((Subtarget->hasNEON())) {
    2722           0 :     return fastEmitInst_rr(ARM::VCEQv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2723             :   }
    2724             :   return 0;
    2725             : }
    2726             : 
    2727             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2728           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2729             :     return 0;
    2730           0 :   if ((Subtarget->hasNEON())) {
    2731           0 :     return fastEmitInst_rr(ARM::VCEQv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2732             :   }
    2733             :   return 0;
    2734             : }
    2735             : 
    2736             : unsigned fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2737           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2738             :     return 0;
    2739           0 :   if ((Subtarget->hasNEON())) {
    2740           0 :     return fastEmitInst_rr(ARM::VCEQv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2741             :   }
    2742             :   return 0;
    2743             : }
    2744             : 
    2745             : unsigned fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2746           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2747             :     return 0;
    2748           0 :   if ((Subtarget->hasNEON())) {
    2749           0 :     return fastEmitInst_rr(ARM::VCEQv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2750             :   }
    2751             :   return 0;
    2752             : }
    2753             : 
    2754             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2755           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2756             :     return 0;
    2757           0 :   if ((Subtarget->hasNEON())) {
    2758           0 :     return fastEmitInst_rr(ARM::VCEQv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2759             :   }
    2760             :   return 0;
    2761             : }
    2762             : 
    2763           0 : unsigned fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2764           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2765             :     return 0;
    2766           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2767           0 :     return fastEmitInst_rr(ARM::VCEQhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2768             :   }
    2769             :   return 0;
    2770             : }
    2771             : 
    2772           0 : unsigned fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2773           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2774             :     return 0;
    2775           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2776           0 :     return fastEmitInst_rr(ARM::VCEQhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2777             :   }
    2778             :   return 0;
    2779             : }
    2780             : 
    2781             : unsigned fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2782           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2783             :     return 0;
    2784           0 :   if ((Subtarget->hasNEON())) {
    2785           0 :     return fastEmitInst_rr(ARM::VCEQfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2786             :   }
    2787             :   return 0;
    2788             : }
    2789             : 
    2790             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2791           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2792             :     return 0;
    2793           0 :   if ((Subtarget->hasNEON())) {
    2794           0 :     return fastEmitInst_rr(ARM::VCEQfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2795             :   }
    2796             :   return 0;
    2797             : }
    2798             : 
    2799           0 : unsigned fastEmit_ARMISD_VCEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2800           0 :   switch (VT.SimpleTy) {
    2801           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2802           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2803           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2804           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2805           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2806           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2807           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2808           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2809           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2810           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2811             :   default: return 0;
    2812             :   }
    2813             : }
    2814             : 
    2815             : // FastEmit functions for ARMISD::VCGE.
    2816             : 
    2817             : unsigned fastEmit_ARMISD_VCGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2818           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2819             :     return 0;
    2820           0 :   if ((Subtarget->hasNEON())) {
    2821           0 :     return fastEmitInst_rr(ARM::VCGEsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2822             :   }
    2823             :   return 0;
    2824             : }
    2825             : 
    2826             : unsigned fastEmit_ARMISD_VCGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2827           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2828             :     return 0;
    2829           0 :   if ((Subtarget->hasNEON())) {
    2830           0 :     return fastEmitInst_rr(ARM::VCGEsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2831             :   }
    2832             :   return 0;
    2833             : }
    2834             : 
    2835             : unsigned fastEmit_ARMISD_VCGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2836           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2837             :     return 0;
    2838           0 :   if ((Subtarget->hasNEON())) {
    2839           0 :     return fastEmitInst_rr(ARM::VCGEsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2840             :   }
    2841             :   return 0;
    2842             : }
    2843             : 
    2844             : unsigned fastEmit_ARMISD_VCGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2845           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2846             :     return 0;
    2847           0 :   if ((Subtarget->hasNEON())) {
    2848           0 :     return fastEmitInst_rr(ARM::VCGEsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2849             :   }
    2850             :   return 0;
    2851             : }
    2852             : 
    2853             : unsigned fastEmit_ARMISD_VCGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2854           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2855             :     return 0;
    2856           0 :   if ((Subtarget->hasNEON())) {
    2857           0 :     return fastEmitInst_rr(ARM::VCGEsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2858             :   }
    2859             :   return 0;
    2860             : }
    2861             : 
    2862             : unsigned fastEmit_ARMISD_VCGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2863           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2864             :     return 0;
    2865           0 :   if ((Subtarget->hasNEON())) {
    2866           0 :     return fastEmitInst_rr(ARM::VCGEsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2867             :   }
    2868             :   return 0;
    2869             : }
    2870             : 
    2871           0 : unsigned fastEmit_ARMISD_VCGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2872           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2873             :     return 0;
    2874           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2875           0 :     return fastEmitInst_rr(ARM::VCGEhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2876             :   }
    2877             :   return 0;
    2878             : }
    2879             : 
    2880           0 : unsigned fastEmit_ARMISD_VCGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2881           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2882             :     return 0;
    2883           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2884           0 :     return fastEmitInst_rr(ARM::VCGEhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2885             :   }
    2886             :   return 0;
    2887             : }
    2888             : 
    2889             : unsigned fastEmit_ARMISD_VCGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2890           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2891             :     return 0;
    2892           0 :   if ((Subtarget->hasNEON())) {
    2893           0 :     return fastEmitInst_rr(ARM::VCGEfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2894             :   }
    2895             :   return 0;
    2896             : }
    2897             : 
    2898             : unsigned fastEmit_ARMISD_VCGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2899           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2900             :     return 0;
    2901           0 :   if ((Subtarget->hasNEON())) {
    2902           0 :     return fastEmitInst_rr(ARM::VCGEfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2903             :   }
    2904             :   return 0;
    2905             : }
    2906             : 
    2907           0 : unsigned fastEmit_ARMISD_VCGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2908           0 :   switch (VT.SimpleTy) {
    2909           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2910           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2911           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2912           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2913           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2914           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2915           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2916           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2917           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2918           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2919             :   default: return 0;
    2920             :   }
    2921             : }
    2922             : 
    2923             : // FastEmit functions for ARMISD::VCGEU.
    2924             : 
    2925             : unsigned fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2926           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2927             :     return 0;
    2928           0 :   if ((Subtarget->hasNEON())) {
    2929           0 :     return fastEmitInst_rr(ARM::VCGEuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2930             :   }
    2931             :   return 0;
    2932             : }
    2933             : 
    2934             : unsigned fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2935           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2936             :     return 0;
    2937           0 :   if ((Subtarget->hasNEON())) {
    2938           0 :     return fastEmitInst_rr(ARM::VCGEuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2939             :   }
    2940             :   return 0;
    2941             : }
    2942             : 
    2943             : unsigned fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2944           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2945             :     return 0;
    2946           0 :   if ((Subtarget->hasNEON())) {
    2947           0 :     return fastEmitInst_rr(ARM::VCGEuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2948             :   }
    2949             :   return 0;
    2950             : }
    2951             : 
    2952             : unsigned fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2953           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2954             :     return 0;
    2955           0 :   if ((Subtarget->hasNEON())) {
    2956           0 :     return fastEmitInst_rr(ARM::VCGEuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2957             :   }
    2958             :   return 0;
    2959             : }
    2960             : 
    2961             : unsigned fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2962           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2963             :     return 0;
    2964           0 :   if ((Subtarget->hasNEON())) {
    2965           0 :     return fastEmitInst_rr(ARM::VCGEuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2966             :   }
    2967             :   return 0;
    2968             : }
    2969             : 
    2970             : unsigned fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2971           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2972             :     return 0;
    2973           0 :   if ((Subtarget->hasNEON())) {
    2974           0 :     return fastEmitInst_rr(ARM::VCGEuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2975             :   }
    2976             :   return 0;
    2977             : }
    2978             : 
    2979           0 : unsigned fastEmit_ARMISD_VCGEU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2980           0 :   switch (VT.SimpleTy) {
    2981           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2982           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2983           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2984           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2985           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2986           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2987             :   default: return 0;
    2988             :   }
    2989             : }
    2990             : 
    2991             : // FastEmit functions for ARMISD::VCGT.
    2992             : 
    2993             : unsigned fastEmit_ARMISD_VCGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2994           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2995             :     return 0;
    2996           0 :   if ((Subtarget->hasNEON())) {
    2997           0 :     return fastEmitInst_rr(ARM::VCGTsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2998             :   }
    2999             :   return 0;
    3000             : }
    3001             : 
    3002             : unsigned fastEmit_ARMISD_VCGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3003           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3004             :     return 0;
    3005           0 :   if ((Subtarget->hasNEON())) {
    3006           0 :     return fastEmitInst_rr(ARM::VCGTsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3007             :   }
    3008             :   return 0;
    3009             : }
    3010             : 
    3011             : unsigned fastEmit_ARMISD_VCGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3012           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3013             :     return 0;
    3014           0 :   if ((Subtarget->hasNEON())) {
    3015           0 :     return fastEmitInst_rr(ARM::VCGTsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3016             :   }
    3017             :   return 0;
    3018             : }
    3019             : 
    3020             : unsigned fastEmit_ARMISD_VCGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3021           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3022             :     return 0;
    3023           0 :   if ((Subtarget->hasNEON())) {
    3024           0 :     return fastEmitInst_rr(ARM::VCGTsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3025             :   }
    3026             :   return 0;
    3027             : }
    3028             : 
    3029             : unsigned fastEmit_ARMISD_VCGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3030           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3031             :     return 0;
    3032           0 :   if ((Subtarget->hasNEON())) {
    3033           0 :     return fastEmitInst_rr(ARM::VCGTsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3034             :   }
    3035             :   return 0;
    3036             : }
    3037             : 
    3038             : unsigned fastEmit_ARMISD_VCGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3039           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3040             :     return 0;
    3041           0 :   if ((Subtarget->hasNEON())) {
    3042           0 :     return fastEmitInst_rr(ARM::VCGTsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3043             :   }
    3044             :   return 0;
    3045             : }
    3046             : 
    3047           0 : unsigned fastEmit_ARMISD_VCGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3048           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3049             :     return 0;
    3050           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3051           0 :     return fastEmitInst_rr(ARM::VCGThd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3052             :   }
    3053             :   return 0;
    3054             : }
    3055             : 
    3056           0 : unsigned fastEmit_ARMISD_VCGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3057           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3058             :     return 0;
    3059           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3060           0 :     return fastEmitInst_rr(ARM::VCGThq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3061             :   }
    3062             :   return 0;
    3063             : }
    3064             : 
    3065             : unsigned fastEmit_ARMISD_VCGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3066           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3067             :     return 0;
    3068           0 :   if ((Subtarget->hasNEON())) {
    3069           0 :     return fastEmitInst_rr(ARM::VCGTfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3070             :   }
    3071             :   return 0;
    3072             : }
    3073             : 
    3074             : unsigned fastEmit_ARMISD_VCGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3075           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3076             :     return 0;
    3077           0 :   if ((Subtarget->hasNEON())) {
    3078           0 :     return fastEmitInst_rr(ARM::VCGTfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3079             :   }
    3080             :   return 0;
    3081             : }
    3082             : 
    3083           0 : unsigned fastEmit_ARMISD_VCGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3084           0 :   switch (VT.SimpleTy) {
    3085           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3086           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3087           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3088           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3089           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3090           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3091           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3092           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3093           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3094           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3095             :   default: return 0;
    3096             :   }
    3097             : }
    3098             : 
    3099             : // FastEmit functions for ARMISD::VCGTU.
    3100             : 
    3101             : unsigned fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3102           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3103             :     return 0;
    3104           0 :   if ((Subtarget->hasNEON())) {
    3105           0 :     return fastEmitInst_rr(ARM::VCGTuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3106             :   }
    3107             :   return 0;
    3108             : }
    3109             : 
    3110             : unsigned fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3111           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3112             :     return 0;
    3113           0 :   if ((Subtarget->hasNEON())) {
    3114           0 :     return fastEmitInst_rr(ARM::VCGTuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3115             :   }
    3116             :   return 0;
    3117             : }
    3118             : 
    3119             : unsigned fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3120           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3121             :     return 0;
    3122           0 :   if ((Subtarget->hasNEON())) {
    3123           0 :     return fastEmitInst_rr(ARM::VCGTuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3124             :   }
    3125             :   return 0;
    3126             : }
    3127             : 
    3128             : unsigned fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3129           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3130             :     return 0;
    3131           0 :   if ((Subtarget->hasNEON())) {
    3132           0 :     return fastEmitInst_rr(ARM::VCGTuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3133             :   }
    3134             :   return 0;
    3135             : }
    3136             : 
    3137             : unsigned fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3138           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3139             :     return 0;
    3140           0 :   if ((Subtarget->hasNEON())) {
    3141           0 :     return fastEmitInst_rr(ARM::VCGTuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3142             :   }
    3143             :   return 0;
    3144             : }
    3145             : 
    3146             : unsigned fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3147           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3148             :     return 0;
    3149           0 :   if ((Subtarget->hasNEON())) {
    3150           0 :     return fastEmitInst_rr(ARM::VCGTuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3151             :   }
    3152             :   return 0;
    3153             : }
    3154             : 
    3155           0 : unsigned fastEmit_ARMISD_VCGTU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3156           0 :   switch (VT.SimpleTy) {
    3157           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3158           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3159           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3160           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3161           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3162           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3163             :   default: return 0;
    3164             :   }
    3165             : }
    3166             : 
    3167             : // FastEmit functions for ARMISD::VMOVDRR.
    3168             : 
    3169             : unsigned fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3170           0 :   if (RetVT.SimpleTy != MVT::f64)
    3171             :     return 0;
    3172           0 :   if ((Subtarget->hasVFP2())) {
    3173           0 :     return fastEmitInst_rr(ARM::VMOVDRR, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3174             :   }
    3175             :   return 0;
    3176             : }
    3177             : 
    3178           0 : unsigned fastEmit_ARMISD_VMOVDRR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3179           0 :   switch (VT.SimpleTy) {
    3180           0 :   case MVT::i32: return fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3181             :   default: return 0;
    3182             :   }
    3183             : }
    3184             : 
    3185             : // FastEmit functions for ARMISD::VMULLs.
    3186             : 
    3187             : unsigned fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3188           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3189             :     return 0;
    3190           0 :   if ((Subtarget->hasNEON())) {
    3191           0 :     return fastEmitInst_rr(ARM::VMULLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3192             :   }
    3193             :   return 0;
    3194             : }
    3195             : 
    3196             : unsigned fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3197           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3198             :     return 0;
    3199           0 :   if ((Subtarget->hasNEON())) {
    3200           0 :     return fastEmitInst_rr(ARM::VMULLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3201             :   }
    3202             :   return 0;
    3203             : }
    3204             : 
    3205             : unsigned fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3206           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3207             :     return 0;
    3208           0 :   if ((Subtarget->hasNEON())) {
    3209           0 :     return fastEmitInst_rr(ARM::VMULLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3210             :   }
    3211             :   return 0;
    3212             : }
    3213             : 
    3214           0 : unsigned fastEmit_ARMISD_VMULLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3215           0 :   switch (VT.SimpleTy) {
    3216           0 :   case MVT::v8i8: return fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3217           0 :   case MVT::v4i16: return fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3218           0 :   case MVT::v2i32: return fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3219             :   default: return 0;
    3220             :   }
    3221             : }
    3222             : 
    3223             : // FastEmit functions for ARMISD::VMULLu.
    3224             : 
    3225             : unsigned fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3226           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3227             :     return 0;
    3228           0 :   if ((Subtarget->hasNEON())) {
    3229           0 :     return fastEmitInst_rr(ARM::VMULLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3230             :   }
    3231             :   return 0;
    3232             : }
    3233             : 
    3234             : unsigned fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3235           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3236             :     return 0;
    3237           0 :   if ((Subtarget->hasNEON())) {
    3238           0 :     return fastEmitInst_rr(ARM::VMULLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3239             :   }
    3240             :   return 0;
    3241             : }
    3242             : 
    3243             : unsigned fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3244           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3245             :     return 0;
    3246           0 :   if ((Subtarget->hasNEON())) {
    3247           0 :     return fastEmitInst_rr(ARM::VMULLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3248             :   }
    3249             :   return 0;
    3250             : }
    3251             : 
    3252           0 : unsigned fastEmit_ARMISD_VMULLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3253           0 :   switch (VT.SimpleTy) {
    3254           0 :   case MVT::v8i8: return fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3255           0 :   case MVT::v4i16: return fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3256           0 :   case MVT::v2i32: return fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3257             :   default: return 0;
    3258             :   }
    3259             : }
    3260             : 
    3261             : // FastEmit functions for ARMISD::VTBL1.
    3262             : 
    3263             : unsigned fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3264           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3265             :     return 0;
    3266           0 :   if ((Subtarget->hasNEON())) {
    3267           0 :     return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3268             :   }
    3269             :   return 0;
    3270             : }
    3271             : 
    3272           0 : unsigned fastEmit_ARMISD_VTBL1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3273           0 :   switch (VT.SimpleTy) {
    3274           0 :   case MVT::v8i8: return fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3275             :   default: return 0;
    3276             :   }
    3277             : }
    3278             : 
    3279             : // FastEmit functions for ARMISD::VTST.
    3280             : 
    3281             : unsigned fastEmit_ARMISD_VTST_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3282           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3283             :     return 0;
    3284           0 :   if ((Subtarget->hasNEON())) {
    3285           0 :     return fastEmitInst_rr(ARM::VTSTv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3286             :   }
    3287             :   return 0;
    3288             : }
    3289             : 
    3290             : unsigned fastEmit_ARMISD_VTST_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3291           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3292             :     return 0;
    3293           0 :   if ((Subtarget->hasNEON())) {
    3294           0 :     return fastEmitInst_rr(ARM::VTSTv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3295             :   }
    3296             :   return 0;
    3297             : }
    3298             : 
    3299             : unsigned fastEmit_ARMISD_VTST_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3300           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3301             :     return 0;
    3302           0 :   if ((Subtarget->hasNEON())) {
    3303           0 :     return fastEmitInst_rr(ARM::VTSTv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3304             :   }
    3305             :   return 0;
    3306             : }
    3307             : 
    3308             : unsigned fastEmit_ARMISD_VTST_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3309           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3310             :     return 0;
    3311           0 :   if ((Subtarget->hasNEON())) {
    3312           0 :     return fastEmitInst_rr(ARM::VTSTv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3313             :   }
    3314             :   return 0;
    3315             : }
    3316             : 
    3317             : unsigned fastEmit_ARMISD_VTST_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3318           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3319             :     return 0;
    3320           0 :   if ((Subtarget->hasNEON())) {
    3321           0 :     return fastEmitInst_rr(ARM::VTSTv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3322             :   }
    3323             :   return 0;
    3324             : }
    3325             : 
    3326             : unsigned fastEmit_ARMISD_VTST_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3327           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3328             :     return 0;
    3329           0 :   if ((Subtarget->hasNEON())) {
    3330           0 :     return fastEmitInst_rr(ARM::VTSTv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3331             :   }
    3332             :   return 0;
    3333             : }
    3334             : 
    3335           0 : unsigned fastEmit_ARMISD_VTST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3336           0 :   switch (VT.SimpleTy) {
    3337           0 :   case MVT::v8i8: return fastEmit_ARMISD_VTST_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3338           0 :   case MVT::v16i8: return fastEmit_ARMISD_VTST_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3339           0 :   case MVT::v4i16: return fastEmit_ARMISD_VTST_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3340           0 :   case MVT::v8i16: return fastEmit_ARMISD_VTST_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3341           0 :   case MVT::v2i32: return fastEmit_ARMISD_VTST_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3342           0 :   case MVT::v4i32: return fastEmit_ARMISD_VTST_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3343             :   default: return 0;
    3344             :   }
    3345             : }
    3346             : 
    3347             : // FastEmit functions for ISD::ADD.
    3348             : 
    3349          96 : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3350          96 :   if (RetVT.SimpleTy != MVT::i32)
    3351             :     return 0;
    3352          96 :   if ((Subtarget->isThumb2())) {
    3353          22 :     return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3354             :   }
    3355          74 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    3356           0 :     return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3357             :   }
    3358          74 :   if ((!Subtarget->isThumb())) {
    3359          74 :     return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3360             :   }
    3361             :   return 0;
    3362             : }
    3363             : 
    3364             : unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3365           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3366             :     return 0;
    3367           0 :   if ((Subtarget->hasNEON())) {
    3368           0 :     return fastEmitInst_rr(ARM::VADDv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3369             :   }
    3370             :   return 0;
    3371             : }
    3372             : 
    3373             : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3374           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3375             :     return 0;
    3376           0 :   if ((Subtarget->hasNEON())) {
    3377           0 :     return fastEmitInst_rr(ARM::VADDv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3378             :   }
    3379             :   return 0;
    3380             : }
    3381             : 
    3382             : unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3383           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3384             :     return 0;
    3385           0 :   if ((Subtarget->hasNEON())) {
    3386           0 :     return fastEmitInst_rr(ARM::VADDv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3387             :   }
    3388             :   return 0;
    3389             : }
    3390             : 
    3391             : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3392           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3393             :     return 0;
    3394           0 :   if ((Subtarget->hasNEON())) {
    3395           0 :     return fastEmitInst_rr(ARM::VADDv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3396             :   }
    3397             :   return 0;
    3398             : }
    3399             : 
    3400             : unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3401           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3402             :     return 0;
    3403           0 :   if ((Subtarget->hasNEON())) {
    3404           0 :     return fastEmitInst_rr(ARM::VADDv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3405             :   }
    3406             :   return 0;
    3407             : }
    3408             : 
    3409             : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3410           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3411             :     return 0;
    3412           0 :   if ((Subtarget->hasNEON())) {
    3413           0 :     return fastEmitInst_rr(ARM::VADDv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3414             :   }
    3415             :   return 0;
    3416             : }
    3417             : 
    3418             : unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3419           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    3420             :     return 0;
    3421           0 :   if ((Subtarget->hasNEON())) {
    3422           0 :     return fastEmitInst_rr(ARM::VADDv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3423             :   }
    3424             :   return 0;
    3425             : }
    3426             : 
    3427             : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3428           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3429             :     return 0;
    3430           0 :   if ((Subtarget->hasNEON())) {
    3431           0 :     return fastEmitInst_rr(ARM::VADDv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3432             :   }
    3433             :   return 0;
    3434             : }
    3435             : 
    3436          96 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3437          96 :   switch (VT.SimpleTy) {
    3438          96 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3439           0 :   case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3440           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3441           0 :   case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3442           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3443           0 :   case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3444           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3445           0 :   case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3446           0 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3447             :   default: return 0;
    3448             :   }
    3449             : }
    3450             : 
    3451             : // FastEmit functions for ISD::AND.
    3452             : 
    3453           0 : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3454           0 :   if (RetVT.SimpleTy != MVT::i32)
    3455             :     return 0;
    3456           0 :   if ((Subtarget->isThumb2())) {
    3457           0 :     return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3458             :   }
    3459           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    3460           0 :     return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3461             :   }
    3462           0 :   if ((!Subtarget->isThumb())) {
    3463           0 :     return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3464             :   }
    3465             :   return 0;
    3466             : }
    3467             : 
    3468             : unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3469           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3470             :     return 0;
    3471           0 :   if ((Subtarget->hasNEON())) {
    3472           0 :     return fastEmitInst_rr(ARM::VANDd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3473             :   }
    3474             :   return 0;
    3475             : }
    3476             : 
    3477             : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3478           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3479             :     return 0;
    3480           0 :   if ((Subtarget->hasNEON())) {
    3481           0 :     return fastEmitInst_rr(ARM::VANDq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3482             :   }
    3483             :   return 0;
    3484             : }
    3485             : 
    3486           0 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3487           0 :   switch (VT.SimpleTy) {
    3488           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3489           0 :   case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3490           0 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3491             :   default: return 0;
    3492             :   }
    3493             : }
    3494             : 
    3495             : // FastEmit functions for ISD::FADD.
    3496             : 
    3497             : unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3498           0 :   if (RetVT.SimpleTy != MVT::f16)
    3499             :     return 0;
    3500           0 :   if ((Subtarget->hasFullFP16())) {
    3501           0 :     return fastEmitInst_rr(ARM::VADDH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3502             :   }
    3503             :   return 0;
    3504             : }
    3505             : 
    3506          17 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3507          17 :   if (RetVT.SimpleTy != MVT::f32)
    3508             :     return 0;
    3509          34 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    3510          17 :     return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3511             :   }
    3512             :   return 0;
    3513             : }
    3514             : 
    3515          15 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3516          15 :   if (RetVT.SimpleTy != MVT::f64)
    3517             :     return 0;
    3518          15 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3519          14 :     return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3520             :   }
    3521             :   return 0;
    3522             : }
    3523             : 
    3524           0 : unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3525           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3526             :     return 0;
    3527           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3528           0 :     return fastEmitInst_rr(ARM::VADDhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3529             :   }
    3530             :   return 0;
    3531             : }
    3532             : 
    3533           0 : unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3534           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3535             :     return 0;
    3536           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3537           0 :     return fastEmitInst_rr(ARM::VADDhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3538             :   }
    3539             :   return 0;
    3540             : }
    3541             : 
    3542             : unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3543           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3544             :     return 0;
    3545           0 :   if ((Subtarget->hasNEON())) {
    3546           0 :     return fastEmitInst_rr(ARM::VADDfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3547             :   }
    3548             :   return 0;
    3549             : }
    3550             : 
    3551             : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3552           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3553             :     return 0;
    3554           0 :   if ((Subtarget->hasNEON())) {
    3555           0 :     return fastEmitInst_rr(ARM::VADDfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3556             :   }
    3557             :   return 0;
    3558             : }
    3559             : 
    3560          33 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3561          33 :   switch (VT.SimpleTy) {
    3562           0 :   case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3563          17 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3564          15 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3565           0 :   case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3566           0 :   case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3567           0 :   case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3568           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3569             :   default: return 0;
    3570             :   }
    3571             : }
    3572             : 
    3573             : // FastEmit functions for ISD::FDIV.
    3574             : 
    3575             : unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3576           0 :   if (RetVT.SimpleTy != MVT::f16)
    3577             :     return 0;
    3578           0 :   if ((Subtarget->hasFullFP16())) {
    3579           0 :     return fastEmitInst_rr(ARM::VDIVH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3580             :   }
    3581             :   return 0;
    3582             : }
    3583             : 
    3584             : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3585           0 :   if (RetVT.SimpleTy != MVT::f32)
    3586             :     return 0;
    3587           0 :   if ((Subtarget->hasVFP2())) {
    3588           0 :     return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3589             :   }
    3590             :   return 0;
    3591             : }
    3592             : 
    3593           0 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3594           0 :   if (RetVT.SimpleTy != MVT::f64)
    3595             :     return 0;
    3596           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3597           0 :     return fastEmitInst_rr(ARM::VDIVD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3598             :   }
    3599             :   return 0;
    3600             : }
    3601             : 
    3602           0 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3603           0 :   switch (VT.SimpleTy) {
    3604           0 :   case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3605           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3606           0 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3607             :   default: return 0;
    3608             :   }
    3609             : }
    3610             : 
    3611             : // FastEmit functions for ISD::FMAXNAN.
    3612             : 
    3613           0 : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3614           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3615             :     return 0;
    3616           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3617           0 :     return fastEmitInst_rr(ARM::VMAXhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3618             :   }
    3619             :   return 0;
    3620             : }
    3621             : 
    3622           0 : unsigned fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3623           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3624             :     return 0;
    3625           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3626           0 :     return fastEmitInst_rr(ARM::VMAXhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3627             :   }
    3628             :   return 0;
    3629             : }
    3630             : 
    3631             : unsigned fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3632           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3633             :     return 0;
    3634           0 :   if ((Subtarget->hasNEON())) {
    3635           0 :     return fastEmitInst_rr(ARM::VMAXfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3636             :   }
    3637             :   return 0;
    3638             : }
    3639             : 
    3640             : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3641           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3642             :     return 0;
    3643           0 :   if ((Subtarget->hasNEON())) {
    3644           0 :     return fastEmitInst_rr(ARM::VMAXfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3645             :   }
    3646             :   return 0;
    3647             : }
    3648             : 
    3649           0 : unsigned fastEmit_ISD_FMAXNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3650           0 :   switch (VT.SimpleTy) {
    3651           0 :   case MVT::v4f16: return fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3652           0 :   case MVT::v8f16: return fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3653           0 :   case MVT::v2f32: return fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3654           0 :   case MVT::v4f32: return fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3655             :   default: return 0;
    3656             :   }
    3657             : }
    3658             : 
    3659             : // FastEmit functions for ISD::FMAXNUM.
    3660             : 
    3661             : unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3662           0 :   if (RetVT.SimpleTy != MVT::f32)
    3663             :     return 0;
    3664           0 :   if ((Subtarget->hasFPARMv8())) {
    3665           0 :     return fastEmitInst_rr(ARM::VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3666             :   }
    3667             :   return 0;
    3668             : }
    3669             : 
    3670           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3671           0 :   if (RetVT.SimpleTy != MVT::f64)
    3672             :     return 0;
    3673           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    3674           0 :     return fastEmitInst_rr(ARM::VMAXNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3675             :   }
    3676             :   return 0;
    3677             : }
    3678             : 
    3679           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3680           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3681             :     return 0;
    3682           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3683           0 :     return fastEmitInst_rr(ARM::VMAXNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3684             :   }
    3685             :   return 0;
    3686             : }
    3687             : 
    3688           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3689           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3690             :     return 0;
    3691           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3692           0 :     return fastEmitInst_rr(ARM::VMAXNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3693             :   }
    3694             :   return 0;
    3695             : }
    3696             : 
    3697           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3698           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3699             :     return 0;
    3700           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3701           0 :     return fastEmitInst_rr(ARM::VMAXNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3702             :   }
    3703             :   return 0;
    3704             : }
    3705             : 
    3706           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3707           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3708             :     return 0;
    3709           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3710           0 :     return fastEmitInst_rr(ARM::VMAXNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3711             :   }
    3712             :   return 0;
    3713             : }
    3714             : 
    3715           0 : unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3716           0 :   switch (VT.SimpleTy) {
    3717           0 :   case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3718           0 :   case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3719           0 :   case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3720           0 :   case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3721           0 :   case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3722           0 :   case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3723             :   default: return 0;
    3724             :   }
    3725             : }
    3726             : 
    3727             : // FastEmit functions for ISD::FMINNAN.
    3728             : 
    3729           0 : unsigned fastEmit_ISD_FMINNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3730           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3731             :     return 0;
    3732           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3733           0 :     return fastEmitInst_rr(ARM::VMINhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3734             :   }
    3735             :   return 0;
    3736             : }
    3737             : 
    3738           0 : unsigned fastEmit_ISD_FMINNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3739           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3740             :     return 0;
    3741           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3742           0 :     return fastEmitInst_rr(ARM::VMINhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3743             :   }
    3744             :   return 0;
    3745             : }
    3746             : 
    3747             : unsigned fastEmit_ISD_FMINNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3748           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3749             :     return 0;
    3750           0 :   if ((Subtarget->hasNEON())) {
    3751           0 :     return fastEmitInst_rr(ARM::VMINfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3752             :   }
    3753             :   return 0;
    3754             : }
    3755             : 
    3756             : unsigned fastEmit_ISD_FMINNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3757           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3758             :     return 0;
    3759           0 :   if ((Subtarget->hasNEON())) {
    3760           0 :     return fastEmitInst_rr(ARM::VMINfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3761             :   }
    3762             :   return 0;
    3763             : }
    3764             : 
    3765           0 : unsigned fastEmit_ISD_FMINNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3766           0 :   switch (VT.SimpleTy) {
    3767           0 :   case MVT::v4f16: return fastEmit_ISD_FMINNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3768           0 :   case MVT::v8f16: return fastEmit_ISD_FMINNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3769           0 :   case MVT::v2f32: return fastEmit_ISD_FMINNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3770           0 :   case MVT::v4f32: return fastEmit_ISD_FMINNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3771             :   default: return 0;
    3772             :   }
    3773             : }
    3774             : 
    3775             : // FastEmit functions for ISD::FMINNUM.
    3776             : 
    3777             : unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3778           0 :   if (RetVT.SimpleTy != MVT::f32)
    3779             :     return 0;
    3780           0 :   if ((Subtarget->hasFPARMv8())) {
    3781           0 :     return fastEmitInst_rr(ARM::VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3782             :   }
    3783             :   return 0;
    3784             : }
    3785             : 
    3786           0 : unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3787           0 :   if (RetVT.SimpleTy != MVT::f64)
    3788             :     return 0;
    3789           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    3790           0 :     return fastEmitInst_rr(ARM::VMINNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3791             :   }
    3792             :   return 0;
    3793             : }
    3794             : 
    3795           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3796           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3797             :     return 0;
    3798           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3799           0 :     return fastEmitInst_rr(ARM::VMINNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3800             :   }
    3801             :   return 0;
    3802             : }
    3803             : 
    3804           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3805           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3806             :     return 0;
    3807           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3808           0 :     return fastEmitInst_rr(ARM::VMINNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3809             :   }
    3810             :   return 0;
    3811             : }
    3812             : 
    3813           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3814           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3815             :     return 0;
    3816           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3817           0 :     return fastEmitInst_rr(ARM::VMINNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3818             :   }
    3819             :   return 0;
    3820             : }
    3821             : 
    3822           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3823           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3824             :     return 0;
    3825           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3826           0 :     return fastEmitInst_rr(ARM::VMINNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3827             :   }
    3828             :   return 0;
    3829             : }
    3830             : 
    3831           0 : unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3832           0 :   switch (VT.SimpleTy) {
    3833           0 :   case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3834           0 :   case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3835           0 :   case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3836           0 :   case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3837           0 :   case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3838           0 :   case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3839             :   default: return 0;
    3840             :   }
    3841             : }
    3842             : 
    3843             : // FastEmit functions for ISD::FMUL.
    3844             : 
    3845             : unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3846           0 :   if (RetVT.SimpleTy != MVT::f16)
    3847             :     return 0;
    3848           0 :   if ((Subtarget->hasFullFP16())) {
    3849           0 :     return fastEmitInst_rr(ARM::VMULH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3850             :   }
    3851             :   return 0;
    3852             : }
    3853             : 
    3854           1 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3855           1 :   if (RetVT.SimpleTy != MVT::f32)
    3856             :     return 0;
    3857           2 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    3858           1 :     return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3859             :   }
    3860             :   return 0;
    3861             : }
    3862             : 
    3863           0 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3864           0 :   if (RetVT.SimpleTy != MVT::f64)
    3865             :     return 0;
    3866           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3867           0 :     return fastEmitInst_rr(ARM::VMULD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3868             :   }
    3869             :   return 0;
    3870             : }
    3871             : 
    3872           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3873           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3874             :     return 0;
    3875           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3876           0 :     return fastEmitInst_rr(ARM::VMULhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3877             :   }
    3878             :   return 0;
    3879             : }
    3880             : 
    3881           0 : unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3882           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3883             :     return 0;
    3884           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3885           0 :     return fastEmitInst_rr(ARM::VMULhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3886             :   }
    3887             :   return 0;
    3888             : }
    3889             : 
    3890             : unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3891           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3892             :     return 0;
    3893           0 :   if ((Subtarget->hasNEON())) {
    3894           0 :     return fastEmitInst_rr(ARM::VMULfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3895             :   }
    3896             :   return 0;
    3897             : }
    3898             : 
    3899             : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3900           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3901             :     return 0;
    3902           0 :   if ((Subtarget->hasNEON())) {
    3903           0 :     return fastEmitInst_rr(ARM::VMULfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3904             :   }
    3905             :   return 0;
    3906             : }
    3907             : 
    3908           1 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3909           1 :   switch (VT.SimpleTy) {
    3910           0 :   case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3911           1 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3912           0 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3913           0 :   case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3914           0 :   case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3915           0 :   case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3916           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3917             :   default: return 0;
    3918             :   }
    3919             : }
    3920             : 
    3921             : // FastEmit functions for ISD::FSUB.
    3922             : 
    3923             : unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3924           0 :   if (RetVT.SimpleTy != MVT::f16)
    3925             :     return 0;
    3926           0 :   if ((Subtarget->hasFullFP16())) {
    3927           0 :     return fastEmitInst_rr(ARM::VSUBH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3928             :   }
    3929             :   return 0;
    3930             : }
    3931             : 
    3932           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3933           0 :   if (RetVT.SimpleTy != MVT::f32)
    3934             :     return 0;
    3935           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    3936           0 :     return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3937             :   }
    3938             :   return 0;
    3939             : }
    3940             : 
    3941           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3942           0 :   if (RetVT.SimpleTy != MVT::f64)
    3943             :     return 0;
    3944           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3945           0 :     return fastEmitInst_rr(ARM::VSUBD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3946             :   }
    3947             :   return 0;
    3948             : }
    3949             : 
    3950           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3951           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3952             :     return 0;
    3953           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3954           0 :     return fastEmitInst_rr(ARM::VSUBhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3955             :   }
    3956             :   return 0;
    3957             : }
    3958             : 
    3959           0 : unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3960           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3961             :     return 0;
    3962           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3963           0 :     return fastEmitInst_rr(ARM::VSUBhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3964             :   }
    3965             :   return 0;
    3966             : }
    3967             : 
    3968             : unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3969           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3970             :     return 0;
    3971           0 :   if ((Subtarget->hasNEON())) {
    3972           0 :     return fastEmitInst_rr(ARM::VSUBfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3973             :   }
    3974             :   return 0;
    3975             : }
    3976             : 
    3977             : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3978           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3979             :     return 0;
    3980           0 :   if ((Subtarget->hasNEON())) {
    3981           0 :     return fastEmitInst_rr(ARM::VSUBfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3982             :   }
    3983             :   return 0;
    3984             : }
    3985             : 
    3986           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3987           0 :   switch (VT.SimpleTy) {
    3988           0 :   case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3989           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3990           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3991           0 :   case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3992           0 :   case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3993           0 :   case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3994           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3995             :   default: return 0;
    3996             :   }
    3997             : }
    3998             : 
    3999             : // FastEmit functions for ISD::MUL.
    4000             : 
    4001           3 : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4002           3 :   if (RetVT.SimpleTy != MVT::i32)
    4003             :     return 0;
    4004           3 :   if ((Subtarget->isThumb2())) {
    4005           3 :     return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4006             :   }
    4007           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4008           0 :     return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4009             :   }
    4010           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV6Ops()) && (Subtarget->useMulOps())) {
    4011           0 :     return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4012             :   }
    4013           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    4014           0 :     return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4015             :   }
    4016             :   return 0;
    4017             : }
    4018             : 
    4019             : unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4020           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4021             :     return 0;
    4022           0 :   if ((Subtarget->hasNEON())) {
    4023           0 :     return fastEmitInst_rr(ARM::VMULv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4024             :   }
    4025             :   return 0;
    4026             : }
    4027             : 
    4028             : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4029           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4030             :     return 0;
    4031           0 :   if ((Subtarget->hasNEON())) {
    4032           0 :     return fastEmitInst_rr(ARM::VMULv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4033             :   }
    4034             :   return 0;
    4035             : }
    4036             : 
    4037             : unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4038           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4039             :     return 0;
    4040           0 :   if ((Subtarget->hasNEON())) {
    4041           0 :     return fastEmitInst_rr(ARM::VMULv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4042             :   }
    4043             :   return 0;
    4044             : }
    4045             : 
    4046             : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4047           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4048             :     return 0;
    4049           0 :   if ((Subtarget->hasNEON())) {
    4050           0 :     return fastEmitInst_rr(ARM::VMULv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4051             :   }
    4052             :   return 0;
    4053             : }
    4054             : 
    4055             : unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4056           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4057             :     return 0;
    4058           0 :   if ((Subtarget->hasNEON())) {
    4059           0 :     return fastEmitInst_rr(ARM::VMULv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4060             :   }
    4061             :   return 0;
    4062             : }
    4063             : 
    4064             : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4065           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4066             :     return 0;
    4067           0 :   if ((Subtarget->hasNEON())) {
    4068           0 :     return fastEmitInst_rr(ARM::VMULv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4069             :   }
    4070             :   return 0;
    4071             : }
    4072             : 
    4073           3 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4074           3 :   switch (VT.SimpleTy) {
    4075           3 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4076           0 :   case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4077           0 :   case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4078           0 :   case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4079           0 :   case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4080           0 :   case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4081           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4082             :   default: return 0;
    4083             :   }
    4084             : }
    4085             : 
    4086             : // FastEmit functions for ISD::MULHS.
    4087             : 
    4088           0 : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4089           0 :   if (RetVT.SimpleTy != MVT::i32)
    4090             :     return 0;
    4091           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    4092           0 :     return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4093             :   }
    4094           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    4095           0 :     return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4096             :   }
    4097             :   return 0;
    4098             : }
    4099             : 
    4100             : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4101           0 :   switch (VT.SimpleTy) {
    4102           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4103             :   default: return 0;
    4104             :   }
    4105             : }
    4106             : 
    4107             : // FastEmit functions for ISD::OR.
    4108             : 
    4109           3 : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4110           3 :   if (RetVT.SimpleTy != MVT::i32)
    4111             :     return 0;
    4112           3 :   if ((Subtarget->isThumb2())) {
    4113           1 :     return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4114             :   }
    4115           2 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4116           0 :     return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4117             :   }
    4118           2 :   if ((!Subtarget->isThumb())) {
    4119           2 :     return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4120             :   }
    4121             :   return 0;
    4122             : }
    4123             : 
    4124             : unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4125           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4126             :     return 0;
    4127           0 :   if ((Subtarget->hasNEON())) {
    4128           0 :     return fastEmitInst_rr(ARM::VORRd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4129             :   }
    4130             :   return 0;
    4131             : }
    4132             : 
    4133             : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4134           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4135             :     return 0;
    4136           0 :   if ((Subtarget->hasNEON())) {
    4137           0 :     return fastEmitInst_rr(ARM::VORRq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4138             :   }
    4139             :   return 0;
    4140             : }
    4141             : 
    4142           3 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4143           3 :   switch (VT.SimpleTy) {
    4144           3 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4145           0 :   case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4146           0 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4147             :   default: return 0;
    4148             :   }
    4149             : }
    4150             : 
    4151             : // FastEmit functions for ISD::ROTR.
    4152             : 
    4153           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4154           0 :   if (RetVT.SimpleTy != MVT::i32)
    4155             :     return 0;
    4156           0 :   if ((Subtarget->isThumb2())) {
    4157           0 :     return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4158             :   }
    4159           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4160           0 :     return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4161             :   }
    4162             :   return 0;
    4163             : }
    4164             : 
    4165             : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4166           0 :   switch (VT.SimpleTy) {
    4167           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4168             :   default: return 0;
    4169             :   }
    4170             : }
    4171             : 
    4172             : // FastEmit functions for ISD::SDIV.
    4173             : 
    4174           4 : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4175           4 :   if (RetVT.SimpleTy != MVT::i32)
    4176             :     return 0;
    4177           4 :   if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) {
    4178           0 :     return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4179             :   }
    4180           4 :   if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) {
    4181           0 :     return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4182             :   }
    4183             :   return 0;
    4184             : }
    4185             : 
    4186             : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4187           4 :   switch (VT.SimpleTy) {
    4188           4 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4189             :   default: return 0;
    4190             :   }
    4191             : }
    4192             : 
    4193             : // FastEmit functions for ISD::SHL.
    4194             : 
    4195           5 : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4196           5 :   if (RetVT.SimpleTy != MVT::i32)
    4197             :     return 0;
    4198           5 :   if ((Subtarget->isThumb2())) {
    4199           0 :     return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4200             :   }
    4201           5 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4202           0 :     return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4203             :   }
    4204             :   return 0;
    4205             : }
    4206             : 
    4207             : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4208           5 :   switch (VT.SimpleTy) {
    4209           5 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4210             :   default: return 0;
    4211             :   }
    4212             : }
    4213             : 
    4214             : // FastEmit functions for ISD::SMAX.
    4215             : 
    4216             : unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4217           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4218             :     return 0;
    4219           0 :   if ((Subtarget->hasNEON())) {
    4220           0 :     return fastEmitInst_rr(ARM::VMAXsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4221             :   }
    4222             :   return 0;
    4223             : }
    4224             : 
    4225             : unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4226           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4227             :     return 0;
    4228           0 :   if ((Subtarget->hasNEON())) {
    4229           0 :     return fastEmitInst_rr(ARM::VMAXsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4230             :   }
    4231             :   return 0;
    4232             : }
    4233             : 
    4234             : unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4235           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4236             :     return 0;
    4237           0 :   if ((Subtarget->hasNEON())) {
    4238           0 :     return fastEmitInst_rr(ARM::VMAXsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4239             :   }
    4240             :   return 0;
    4241             : }
    4242             : 
    4243             : unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4244           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4245             :     return 0;
    4246           0 :   if ((Subtarget->hasNEON())) {
    4247           0 :     return fastEmitInst_rr(ARM::VMAXsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4248             :   }
    4249             :   return 0;
    4250             : }
    4251             : 
    4252             : unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4253           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4254             :     return 0;
    4255           0 :   if ((Subtarget->hasNEON())) {
    4256           0 :     return fastEmitInst_rr(ARM::VMAXsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4257             :   }
    4258             :   return 0;
    4259             : }
    4260             : 
    4261             : unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4262           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4263             :     return 0;
    4264           0 :   if ((Subtarget->hasNEON())) {
    4265           0 :     return fastEmitInst_rr(ARM::VMAXsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4266             :   }
    4267             :   return 0;
    4268             : }
    4269             : 
    4270           0 : unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4271           0 :   switch (VT.SimpleTy) {
    4272           0 :   case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4273           0 :   case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4274           0 :   case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4275           0 :   case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4276           0 :   case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4277           0 :   case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4278             :   default: return 0;
    4279             :   }
    4280             : }
    4281             : 
    4282             : // FastEmit functions for ISD::SMIN.
    4283             : 
    4284             : unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4285           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4286             :     return 0;
    4287           0 :   if ((Subtarget->hasNEON())) {
    4288           0 :     return fastEmitInst_rr(ARM::VMINsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4289             :   }
    4290             :   return 0;
    4291             : }
    4292             : 
    4293             : unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4294           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4295             :     return 0;
    4296           0 :   if ((Subtarget->hasNEON())) {
    4297           0 :     return fastEmitInst_rr(ARM::VMINsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4298             :   }
    4299             :   return 0;
    4300             : }
    4301             : 
    4302             : unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4303           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4304             :     return 0;
    4305           0 :   if ((Subtarget->hasNEON())) {
    4306           0 :     return fastEmitInst_rr(ARM::VMINsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4307             :   }
    4308             :   return 0;
    4309             : }
    4310             : 
    4311             : unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4312           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4313             :     return 0;
    4314           0 :   if ((Subtarget->hasNEON())) {
    4315           0 :     return fastEmitInst_rr(ARM::VMINsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4316             :   }
    4317             :   return 0;
    4318             : }
    4319             : 
    4320             : unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4321           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4322             :     return 0;
    4323           0 :   if ((Subtarget->hasNEON())) {
    4324           0 :     return fastEmitInst_rr(ARM::VMINsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4325             :   }
    4326             :   return 0;
    4327             : }
    4328             : 
    4329             : unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4330           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4331             :     return 0;
    4332           0 :   if ((Subtarget->hasNEON())) {
    4333           0 :     return fastEmitInst_rr(ARM::VMINsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4334             :   }
    4335             :   return 0;
    4336             : }
    4337             : 
    4338           0 : unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4339           0 :   switch (VT.SimpleTy) {
    4340           0 :   case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4341           0 :   case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4342           0 :   case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4343           0 :   case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4344           0 :   case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4345           0 :   case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4346             :   default: return 0;
    4347             :   }
    4348             : }
    4349             : 
    4350             : // FastEmit functions for ISD::SRA.
    4351             : 
    4352           4 : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4353           4 :   if (RetVT.SimpleTy != MVT::i32)
    4354             :     return 0;
    4355           4 :   if ((Subtarget->isThumb2())) {
    4356           0 :     return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4357             :   }
    4358           4 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4359           0 :     return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4360             :   }
    4361             :   return 0;
    4362             : }
    4363             : 
    4364             : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4365           4 :   switch (VT.SimpleTy) {
    4366           4 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4367             :   default: return 0;
    4368             :   }
    4369             : }
    4370             : 
    4371             : // FastEmit functions for ISD::SRL.
    4372             : 
    4373           6 : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4374           6 :   if (RetVT.SimpleTy != MVT::i32)
    4375             :     return 0;
    4376           6 :   if ((Subtarget->isThumb2())) {
    4377           2 :     return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4378             :   }
    4379           4 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4380           0 :     return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4381             :   }
    4382             :   return 0;
    4383             : }
    4384             : 
    4385             : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4386           6 :   switch (VT.SimpleTy) {
    4387           6 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4388             :   default: return 0;
    4389             :   }
    4390             : }
    4391             : 
    4392             : // FastEmit functions for ISD::SUB.
    4393             : 
    4394           3 : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4395           3 :   if (RetVT.SimpleTy != MVT::i32)
    4396             :     return 0;
    4397           3 :   if ((Subtarget->isThumb2())) {
    4398           1 :     return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4399             :   }
    4400           2 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4401           0 :     return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4402             :   }
    4403           2 :   if ((!Subtarget->isThumb())) {
    4404           2 :     return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4405             :   }
    4406             :   return 0;
    4407             : }
    4408             : 
    4409             : unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4410           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4411             :     return 0;
    4412           0 :   if ((Subtarget->hasNEON())) {
    4413           0 :     return fastEmitInst_rr(ARM::VSUBv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4414             :   }
    4415             :   return 0;
    4416             : }
    4417             : 
    4418             : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4419           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4420             :     return 0;
    4421           0 :   if ((Subtarget->hasNEON())) {
    4422           0 :     return fastEmitInst_rr(ARM::VSUBv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4423             :   }
    4424             :   return 0;
    4425             : }
    4426             : 
    4427             : unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4428           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4429             :     return 0;
    4430           0 :   if ((Subtarget->hasNEON())) {
    4431           0 :     return fastEmitInst_rr(ARM::VSUBv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4432             :   }
    4433             :   return 0;
    4434             : }
    4435             : 
    4436             : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4437           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4438             :     return 0;
    4439           0 :   if ((Subtarget->hasNEON())) {
    4440           0 :     return fastEmitInst_rr(ARM::VSUBv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4441             :   }
    4442             :   return 0;
    4443             : }
    4444             : 
    4445             : unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4446           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4447             :     return 0;
    4448           0 :   if ((Subtarget->hasNEON())) {
    4449           0 :     return fastEmitInst_rr(ARM::VSUBv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4450             :   }
    4451             :   return 0;
    4452             : }
    4453             : 
    4454             : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4455           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4456             :     return 0;
    4457           0 :   if ((Subtarget->hasNEON())) {
    4458           0 :     return fastEmitInst_rr(ARM::VSUBv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4459             :   }
    4460             :   return 0;
    4461             : }
    4462             : 
    4463             : unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4464           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    4465             :     return 0;
    4466           0 :   if ((Subtarget->hasNEON())) {
    4467           0 :     return fastEmitInst_rr(ARM::VSUBv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4468             :   }
    4469             :   return 0;
    4470             : }
    4471             : 
    4472             : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4473           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    4474             :     return 0;
    4475           0 :   if ((Subtarget->hasNEON())) {
    4476           0 :     return fastEmitInst_rr(ARM::VSUBv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4477             :   }
    4478             :   return 0;
    4479             : }
    4480             : 
    4481           3 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4482           3 :   switch (VT.SimpleTy) {
    4483           3 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4484           0 :   case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4485           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4486           0 :   case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4487           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4488           0 :   case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4489           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4490           0 :   case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4491           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4492             :   default: return 0;
    4493             :   }
    4494             : }
    4495             : 
    4496             : // FastEmit functions for ISD::UDIV.
    4497             : 
    4498          10 : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4499          10 :   if (RetVT.SimpleTy != MVT::i32)
    4500             :     return 0;
    4501          10 :   if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) {
    4502           0 :     return fastEmitInst_rr(ARM::t2UDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4503             :   }
    4504          10 :   if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) {
    4505           0 :     return fastEmitInst_rr(ARM::UDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4506             :   }
    4507             :   return 0;
    4508             : }
    4509             : 
    4510             : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4511          10 :   switch (VT.SimpleTy) {
    4512          10 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4513             :   default: return 0;
    4514             :   }
    4515             : }
    4516             : 
    4517             : // FastEmit functions for ISD::UMAX.
    4518             : 
    4519             : unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4520           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4521             :     return 0;
    4522           0 :   if ((Subtarget->hasNEON())) {
    4523           0 :     return fastEmitInst_rr(ARM::VMAXuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4524             :   }
    4525             :   return 0;
    4526             : }
    4527             : 
    4528             : unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4529           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4530             :     return 0;
    4531           0 :   if ((Subtarget->hasNEON())) {
    4532           0 :     return fastEmitInst_rr(ARM::VMAXuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4533             :   }
    4534             :   return 0;
    4535             : }
    4536             : 
    4537             : unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4538           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4539             :     return 0;
    4540           0 :   if ((Subtarget->hasNEON())) {
    4541           0 :     return fastEmitInst_rr(ARM::VMAXuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4542             :   }
    4543             :   return 0;
    4544             : }
    4545             : 
    4546             : unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4547           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4548             :     return 0;
    4549           0 :   if ((Subtarget->hasNEON())) {
    4550           0 :     return fastEmitInst_rr(ARM::VMAXuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4551             :   }
    4552             :   return 0;
    4553             : }
    4554             : 
    4555             : unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4556           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4557             :     return 0;
    4558           0 :   if ((Subtarget->hasNEON())) {
    4559           0 :     return fastEmitInst_rr(ARM::VMAXuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4560             :   }
    4561             :   return 0;
    4562             : }
    4563             : 
    4564             : unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4565           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4566             :     return 0;
    4567           0 :   if ((Subtarget->hasNEON())) {
    4568           0 :     return fastEmitInst_rr(ARM::VMAXuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4569             :   }
    4570             :   return 0;
    4571             : }
    4572             : 
    4573           0 : unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4574           0 :   switch (VT.SimpleTy) {
    4575           0 :   case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4576           0 :   case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4577           0 :   case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4578           0 :   case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4579           0 :   case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4580           0 :   case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4581             :   default: return 0;
    4582             :   }
    4583             : }
    4584             : 
    4585             : // FastEmit functions for ISD::UMIN.
    4586             : 
    4587             : unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4588           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4589             :     return 0;
    4590           0 :   if ((Subtarget->hasNEON())) {
    4591           0 :     return fastEmitInst_rr(ARM::VMINuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4592             :   }
    4593             :   return 0;
    4594             : }
    4595             : 
    4596             : unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4597           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4598             :     return 0;
    4599           0 :   if ((Subtarget->hasNEON())) {
    4600           0 :     return fastEmitInst_rr(ARM::VMINuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4601             :   }
    4602             :   return 0;
    4603             : }
    4604             : 
    4605             : unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4606           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4607             :     return 0;
    4608           0 :   if ((Subtarget->hasNEON())) {
    4609           0 :     return fastEmitInst_rr(ARM::VMINuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4610             :   }
    4611             :   return 0;
    4612             : }
    4613             : 
    4614             : unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4615           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4616             :     return 0;
    4617           0 :   if ((Subtarget->hasNEON())) {
    4618           0 :     return fastEmitInst_rr(ARM::VMINuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4619             :   }
    4620             :   return 0;
    4621             : }
    4622             : 
    4623             : unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4624           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4625             :     return 0;
    4626           0 :   if ((Subtarget->hasNEON())) {
    4627           0 :     return fastEmitInst_rr(ARM::VMINuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4628             :   }
    4629             :   return 0;
    4630             : }
    4631             : 
    4632             : unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4633           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4634             :     return 0;
    4635           0 :   if ((Subtarget->hasNEON())) {
    4636           0 :     return fastEmitInst_rr(ARM::VMINuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4637             :   }
    4638             :   return 0;
    4639             : }
    4640             : 
    4641           0 : unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4642           0 :   switch (VT.SimpleTy) {
    4643           0 :   case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4644           0 :   case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4645           0 :   case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4646           0 :   case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4647           0 :   case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4648           0 :   case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4649             :   default: return 0;
    4650             :   }
    4651             : }
    4652             : 
    4653             : // FastEmit functions for ISD::XOR.
    4654             : 
    4655          11 : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4656          11 :   if (RetVT.SimpleTy != MVT::i32)
    4657             :     return 0;
    4658          11 :   if ((Subtarget->isThumb2())) {
    4659           8 :     return fastEmitInst_rr(ARM::t2EORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4660             :   }
    4661           3 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4662           0 :     return fastEmitInst_rr(ARM::tEOR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4663             :   }
    4664           3 :   if ((!Subtarget->isThumb())) {
    4665           3 :     return fastEmitInst_rr(ARM::EORrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4666             :   }
    4667             :   return 0;
    4668             : }
    4669             : 
    4670             : unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4671           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4672             :     return 0;
    4673           0 :   if ((Subtarget->hasNEON())) {
    4674           0 :     return fastEmitInst_rr(ARM::VEORd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4675             :   }
    4676             :   return 0;
    4677             : }
    4678             : 
    4679             : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4680           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4681             :     return 0;
    4682           0 :   if ((Subtarget->hasNEON())) {
    4683           0 :     return fastEmitInst_rr(ARM::VEORq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4684             :   }
    4685             :   return 0;
    4686             : }
    4687             : 
    4688          11 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4689          11 :   switch (VT.SimpleTy) {
    4690          11 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4691           0 :   case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4692           0 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4693             :   default: return 0;
    4694             :   }
    4695             : }
    4696             : 
    4697             : // Top-level FastEmit function.
    4698             : 
    4699         211 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    4700         211 :   switch (Opcode) {
    4701           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4702           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4703           0 :   case ARMISD::EH_SJLJ_LONGJMP: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4704           0 :   case ARMISD::EH_SJLJ_SETJMP: return fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4705           0 :   case ARMISD::SMULWB: return fastEmit_ARMISD_SMULWB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4706           0 :   case ARMISD::SMULWT: return fastEmit_ARMISD_SMULWT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4707           0 :   case ARMISD::VCEQ: return fastEmit_ARMISD_VCEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4708           0 :   case ARMISD::VCGE: return fastEmit_ARMISD_VCGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4709           0 :   case ARMISD::VCGEU: return fastEmit_ARMISD_VCGEU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4710           0 :   case ARMISD::VCGT: return fastEmit_ARMISD_VCGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4711           0 :   case ARMISD::VCGTU: return fastEmit_ARMISD_VCGTU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4712           0 :   case ARMISD::VMOVDRR: return fastEmit_ARMISD_VMOVDRR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4713           0 :   case ARMISD::VMULLs: return fastEmit_ARMISD_VMULLs_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4714           0 :   case ARMISD::VMULLu: return fastEmit_ARMISD_VMULLu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4715           0 :   case ARMISD::VTBL1: return fastEmit_ARMISD_VTBL1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4716           0 :   case ARMISD::VTST: return fastEmit_ARMISD_VTST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4717          96 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4718           0 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4719          33 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4720           0 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4721           0 :   case ISD::FMAXNAN: return fastEmit_ISD_FMAXNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4722           0 :   case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4723           0 :   case ISD::FMINNAN: return fastEmit_ISD_FMINNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4724           0 :   case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4725           1 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4726           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4727           3 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4728           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4729           3 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4730           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4731           4 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4732           5 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4733           0 :   case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4734           0 :   case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4735           4 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4736           6 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4737           3 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4738          10 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4739           0 :   case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4740           0 :   case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4741          11 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4742             :   default: return 0;
    4743             :   }
    4744             : }
    4745             : 
    4746             : // FastEmit functions for ARMISD::PIC_ADD.
    4747             : 
    4748           0 : unsigned fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4749           0 :   if (RetVT.SimpleTy != MVT::i32)
    4750             :     return 0;
    4751           0 :   if ((Subtarget->isThumb())) {
    4752           0 :     return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4753             :   }
    4754             :   if ((!Subtarget->isThumb())) {
    4755           0 :     return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4756             :   }
    4757             :   return 0;
    4758             : }
    4759             : 
    4760             : unsigned fastEmit_ARMISD_PIC_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4761           0 :   switch (VT.SimpleTy) {
    4762           0 :   case MVT::i32: return fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4763             :   default: return 0;
    4764             :   }
    4765             : }
    4766             : 
    4767             : // FastEmit functions for ARMISD::VDUPLANE.
    4768             : 
    4769             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4770           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4771             :     return 0;
    4772           0 :   if ((Subtarget->hasNEON())) {
    4773           0 :     return fastEmitInst_ri(ARM::VDUPLN8d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4774             :   }
    4775             :   return 0;
    4776             : }
    4777             : 
    4778             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4779           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4780             :     return 0;
    4781           0 :   if ((Subtarget->hasNEON())) {
    4782           0 :     return fastEmitInst_ri(ARM::VDUPLN16d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4783             :   }
    4784             :   return 0;
    4785             : }
    4786             : 
    4787             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4788           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4789             :     return 0;
    4790           0 :   if ((Subtarget->hasNEON())) {
    4791           0 :     return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4792             :   }
    4793             :   return 0;
    4794             : }
    4795             : 
    4796             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4797           0 :   return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4798             : }
    4799             : 
    4800             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4801           0 :   return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4802             : }
    4803             : 
    4804           0 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4805           0 : switch (RetVT.SimpleTy) {
    4806           0 :   case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(Op0, Op0IsKill, imm1);
    4807           0 :   case MVT::v4f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(Op0, Op0IsKill, imm1);
    4808             :   default: return 0;
    4809             : }
    4810             : }
    4811             : 
    4812           0 : unsigned fastEmit_ARMISD_VDUPLANE_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4813           0 :   switch (VT.SimpleTy) {
    4814           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4815           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4816           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4817           0 :   case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(RetVT, Op0, Op0IsKill, imm1);
    4818             :   default: return 0;
    4819             :   }
    4820             : }
    4821             : 
    4822             : // FastEmit functions for ARMISD::VGETLANEs.
    4823             : 
    4824             : unsigned fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4825           0 :   if (RetVT.SimpleTy != MVT::i32)
    4826             :     return 0;
    4827           0 :   if ((Subtarget->hasNEON())) {
    4828           0 :     return fastEmitInst_ri(ARM::VGETLNs8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4829             :   }
    4830             :   return 0;
    4831             : }
    4832             : 
    4833             : unsigned fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4834           0 :   if (RetVT.SimpleTy != MVT::i32)
    4835             :     return 0;
    4836           0 :   if ((Subtarget->hasNEON())) {
    4837           0 :     return fastEmitInst_ri(ARM::VGETLNs16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4838             :   }
    4839             :   return 0;
    4840             : }
    4841             : 
    4842           0 : unsigned fastEmit_ARMISD_VGETLANEs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4843           0 :   switch (VT.SimpleTy) {
    4844           0 :   case MVT::v8i8: return fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4845           0 :   case MVT::v4i16: return fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4846             :   default: return 0;
    4847             :   }
    4848             : }
    4849             : 
    4850             : // FastEmit functions for ARMISD::VGETLANEu.
    4851             : 
    4852             : unsigned fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4853           0 :   if (RetVT.SimpleTy != MVT::i32)
    4854             :     return 0;
    4855           0 :   if ((Subtarget->hasNEON())) {
    4856           0 :     return fastEmitInst_ri(ARM::VGETLNu8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4857             :   }
    4858             :   return 0;
    4859             : }
    4860             : 
    4861             : unsigned fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4862           0 :   if (RetVT.SimpleTy != MVT::i32)
    4863             :     return 0;
    4864           0 :   if ((Subtarget->hasNEON())) {
    4865           0 :     return fastEmitInst_ri(ARM::VGETLNu16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4866             :   }
    4867             :   return 0;
    4868             : }
    4869             : 
    4870           0 : unsigned fastEmit_ARMISD_VGETLANEu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4871           0 :   switch (VT.SimpleTy) {
    4872           0 :   case MVT::v8i8: return fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4873           0 :   case MVT::v4i16: return fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4874             :   default: return 0;
    4875             :   }
    4876             : }
    4877             : 
    4878             : // FastEmit functions for ARMISD::VQSHLs.
    4879             : 
    4880             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4881           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4882             :     return 0;
    4883           0 :   if ((Subtarget->hasNEON())) {
    4884           0 :     return fastEmitInst_ri(ARM::VQSHLsiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4885             :   }
    4886             :   return 0;
    4887             : }
    4888             : 
    4889             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4890           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4891             :     return 0;
    4892           0 :   if ((Subtarget->hasNEON())) {
    4893           0 :     return fastEmitInst_ri(ARM::VQSHLsiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4894             :   }
    4895             :   return 0;
    4896             : }
    4897             : 
    4898             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4899           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4900             :     return 0;
    4901           0 :   if ((Subtarget->hasNEON())) {
    4902           0 :     return fastEmitInst_ri(ARM::VQSHLsiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4903             :   }
    4904             :   return 0;
    4905             : }
    4906             : 
    4907             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4908           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4909             :     return 0;
    4910           0 :   if ((Subtarget->hasNEON())) {
    4911           0 :     return fastEmitInst_ri(ARM::VQSHLsiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4912             :   }
    4913             :   return 0;
    4914             : }
    4915             : 
    4916             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4917           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4918             :     return 0;
    4919           0 :   if ((Subtarget->hasNEON())) {
    4920           0 :     return fastEmitInst_ri(ARM::VQSHLsiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4921             :   }
    4922             :   return 0;
    4923             : }
    4924             : 
    4925             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4926           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4927             :     return 0;
    4928           0 :   if ((Subtarget->hasNEON())) {
    4929           0 :     return fastEmitInst_ri(ARM::VQSHLsiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4930             :   }
    4931             :   return 0;
    4932             : }
    4933             : 
    4934             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4935           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    4936             :     return 0;
    4937           0 :   if ((Subtarget->hasNEON())) {
    4938           0 :     return fastEmitInst_ri(ARM::VQSHLsiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4939             :   }
    4940             :   return 0;
    4941             : }
    4942             : 
    4943             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4944           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    4945             :     return 0;
    4946           0 :   if ((Subtarget->hasNEON())) {
    4947           0 :     return fastEmitInst_ri(ARM::VQSHLsiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4948             :   }
    4949             :   return 0;
    4950             : }
    4951             : 
    4952           0 : unsigned fastEmit_ARMISD_VQSHLs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4953           0 :   switch (VT.SimpleTy) {
    4954           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4955           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4956           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4957           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4958           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4959           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4960           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    4961           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    4962             :   default: return 0;
    4963             :   }
    4964             : }
    4965             : 
    4966             : // FastEmit functions for ARMISD::VQSHLsu.
    4967             : 
    4968             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4969           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4970             :     return 0;
    4971           0 :   if ((Subtarget->hasNEON())) {
    4972           0 :     return fastEmitInst_ri(ARM::VQSHLsuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4973             :   }
    4974             :   return 0;
    4975             : }
    4976             : 
    4977             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4978           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4979             :     return 0;
    4980           0 :   if ((Subtarget->hasNEON())) {
    4981           0 :     return fastEmitInst_ri(ARM::VQSHLsuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4982             :   }
    4983             :   return 0;
    4984             : }
    4985             : 
    4986             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4987           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4988             :     return 0;
    4989           0 :   if ((Subtarget->hasNEON())) {
    4990           0 :     return fastEmitInst_ri(ARM::VQSHLsuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4991             :   }
    4992             :   return 0;
    4993             : }
    4994             : 
    4995             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4996           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4997             :     return 0;
    4998           0 :   if ((Subtarget->hasNEON())) {
    4999           0 :     return fastEmitInst_ri(ARM::VQSHLsuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5000             :   }
    5001             :   return 0;
    5002             : }
    5003             : 
    5004             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5005           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5006             :     return 0;
    5007           0 :   if ((Subtarget->hasNEON())) {
    5008           0 :     return fastEmitInst_ri(ARM::VQSHLsuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5009             :   }
    5010             :   return 0;
    5011             : }
    5012             : 
    5013             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5014           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5015             :     return 0;
    5016           0 :   if ((Subtarget->hasNEON())) {
    5017           0 :     return fastEmitInst_ri(ARM::VQSHLsuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5018             :   }
    5019             :   return 0;
    5020             : }
    5021             : 
    5022             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5023           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5024             :     return 0;
    5025           0 :   if ((Subtarget->hasNEON())) {
    5026           0 :     return fastEmitInst_ri(ARM::VQSHLsuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5027             :   }
    5028             :   return 0;
    5029             : }
    5030             : 
    5031             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5032           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5033             :     return 0;
    5034           0 :   if ((Subtarget->hasNEON())) {
    5035           0 :     return fastEmitInst_ri(ARM::VQSHLsuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5036             :   }
    5037             :   return 0;
    5038             : }
    5039             : 
    5040           0 : unsigned fastEmit_ARMISD_VQSHLsu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5041           0 :   switch (VT.SimpleTy) {
    5042           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5043           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5044           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5045           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5046           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5047           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5048           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5049           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5050             :   default: return 0;
    5051             :   }
    5052             : }
    5053             : 
    5054             : // FastEmit functions for ARMISD::VQSHLu.
    5055             : 
    5056             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5057           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5058             :     return 0;
    5059           0 :   if ((Subtarget->hasNEON())) {
    5060           0 :     return fastEmitInst_ri(ARM::VQSHLuiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5061             :   }
    5062             :   return 0;
    5063             : }
    5064             : 
    5065             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5066           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5067             :     return 0;
    5068           0 :   if ((Subtarget->hasNEON())) {
    5069           0 :     return fastEmitInst_ri(ARM::VQSHLuiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5070             :   }
    5071             :   return 0;
    5072             : }
    5073             : 
    5074             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5075           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5076             :     return 0;
    5077           0 :   if ((Subtarget->hasNEON())) {
    5078           0 :     return fastEmitInst_ri(ARM::VQSHLuiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5079             :   }
    5080             :   return 0;
    5081             : }
    5082             : 
    5083             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5084           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5085             :     return 0;
    5086           0 :   if ((Subtarget->hasNEON())) {
    5087           0 :     return fastEmitInst_ri(ARM::VQSHLuiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5088             :   }
    5089             :   return 0;
    5090             : }
    5091             : 
    5092             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5093           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5094             :     return 0;
    5095           0 :   if ((Subtarget->hasNEON())) {
    5096           0 :     return fastEmitInst_ri(ARM::VQSHLuiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5097             :   }
    5098             :   return 0;
    5099             : }
    5100             : 
    5101             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5102           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5103             :     return 0;
    5104           0 :   if ((Subtarget->hasNEON())) {
    5105           0 :     return fastEmitInst_ri(ARM::VQSHLuiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5106             :   }
    5107             :   return 0;
    5108             : }
    5109             : 
    5110             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5111           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5112             :     return 0;
    5113           0 :   if ((Subtarget->hasNEON())) {
    5114           0 :     return fastEmitInst_ri(ARM::VQSHLuiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5115             :   }
    5116             :   return 0;
    5117             : }
    5118             : 
    5119             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5120           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5121             :     return 0;
    5122           0 :   if ((Subtarget->hasNEON())) {
    5123           0 :     return fastEmitInst_ri(ARM::VQSHLuiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5124             :   }
    5125             :   return 0;
    5126             : }
    5127             : 
    5128           0 : unsigned fastEmit_ARMISD_VQSHLu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5129           0 :   switch (VT.SimpleTy) {
    5130           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5131           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5132           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5133           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5134           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5135           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5136           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5137           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5138             :   default: return 0;
    5139             :   }
    5140             : }
    5141             : 
    5142             : // FastEmit functions for ARMISD::VRSHRs.
    5143             : 
    5144             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5145           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5146             :     return 0;
    5147           0 :   if ((Subtarget->hasNEON())) {
    5148           0 :     return fastEmitInst_ri(ARM::VRSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5149             :   }
    5150             :   return 0;
    5151             : }
    5152             : 
    5153             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5154           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5155             :     return 0;
    5156           0 :   if ((Subtarget->hasNEON())) {
    5157           0 :     return fastEmitInst_ri(ARM::VRSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5158             :   }
    5159             :   return 0;
    5160             : }
    5161             : 
    5162             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5163           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5164             :     return 0;
    5165           0 :   if ((Subtarget->hasNEON())) {
    5166           0 :     return fastEmitInst_ri(ARM::VRSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5167             :   }
    5168             :   return 0;
    5169             : }
    5170             : 
    5171             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5172           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5173             :     return 0;
    5174           0 :   if ((Subtarget->hasNEON())) {
    5175           0 :     return fastEmitInst_ri(ARM::VRSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5176             :   }
    5177             :   return 0;
    5178             : }
    5179             : 
    5180             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5181           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5182             :     return 0;
    5183           0 :   if ((Subtarget->hasNEON())) {
    5184           0 :     return fastEmitInst_ri(ARM::VRSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5185             :   }
    5186             :   return 0;
    5187             : }
    5188             : 
    5189             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5190           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5191             :     return 0;
    5192           0 :   if ((Subtarget->hasNEON())) {
    5193           0 :     return fastEmitInst_ri(ARM::VRSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5194             :   }
    5195             :   return 0;
    5196             : }
    5197             : 
    5198             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5199           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5200             :     return 0;
    5201           0 :   if ((Subtarget->hasNEON())) {
    5202           0 :     return fastEmitInst_ri(ARM::VRSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5203             :   }
    5204             :   return 0;
    5205             : }
    5206             : 
    5207             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5208           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5209             :     return 0;
    5210           0 :   if ((Subtarget->hasNEON())) {
    5211           0 :     return fastEmitInst_ri(ARM::VRSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5212             :   }
    5213             :   return 0;
    5214             : }
    5215             : 
    5216           0 : unsigned fastEmit_ARMISD_VRSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5217           0 :   switch (VT.SimpleTy) {
    5218           0 :   case MVT::v8i8: return fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5219           0 :   case MVT::v16i8: return fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5220           0 :   case MVT::v4i16: return fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5221           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5222           0 :   case MVT::v2i32: return fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5223           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5224           0 :   case MVT::v1i64: return fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5225           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5226             :   default: return 0;
    5227             :   }
    5228             : }
    5229             : 
    5230             : // FastEmit functions for ARMISD::VRSHRu.
    5231             : 
    5232             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5233           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5234             :     return 0;
    5235           0 :   if ((Subtarget->hasNEON())) {
    5236           0 :     return fastEmitInst_ri(ARM::VRSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5237             :   }
    5238             :   return 0;
    5239             : }
    5240             : 
    5241             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5242           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5243             :     return 0;
    5244           0 :   if ((Subtarget->hasNEON())) {
    5245           0 :     return fastEmitInst_ri(ARM::VRSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5246             :   }
    5247             :   return 0;
    5248             : }
    5249             : 
    5250             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5251           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5252             :     return 0;
    5253           0 :   if ((Subtarget->hasNEON())) {
    5254           0 :     return fastEmitInst_ri(ARM::VRSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5255             :   }
    5256             :   return 0;
    5257             : }
    5258             : 
    5259             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5260           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5261             :     return 0;
    5262           0 :   if ((Subtarget->hasNEON())) {
    5263           0 :     return fastEmitInst_ri(ARM::VRSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5264             :   }
    5265             :   return 0;
    5266             : }
    5267             : 
    5268             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5269           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5270             :     return 0;
    5271           0 :   if ((Subtarget->hasNEON())) {
    5272           0 :     return fastEmitInst_ri(ARM::VRSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5273             :   }
    5274             :   return 0;
    5275             : }
    5276             : 
    5277             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5278           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5279             :     return 0;
    5280           0 :   if ((Subtarget->hasNEON())) {
    5281           0 :     return fastEmitInst_ri(ARM::VRSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5282             :   }
    5283             :   return 0;
    5284             : }
    5285             : 
    5286             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5287           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5288             :     return 0;
    5289           0 :   if ((Subtarget->hasNEON())) {
    5290           0 :     return fastEmitInst_ri(ARM::VRSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5291             :   }
    5292             :   return 0;
    5293             : }
    5294             : 
    5295             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5296           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5297             :     return 0;
    5298           0 :   if ((Subtarget->hasNEON())) {
    5299           0 :     return fastEmitInst_ri(ARM::VRSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5300             :   }
    5301             :   return 0;
    5302             : }
    5303             : 
    5304           0 : unsigned fastEmit_ARMISD_VRSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5305           0 :   switch (VT.SimpleTy) {
    5306           0 :   case MVT::v8i8: return fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5307           0 :   case MVT::v16i8: return fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5308           0 :   case MVT::v4i16: return fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5309           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5310           0 :   case MVT::v2i32: return fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5311           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5312           0 :   case MVT::v1i64: return fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5313           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5314             :   default: return 0;
    5315             :   }
    5316             : }
    5317             : 
    5318             : // FastEmit functions for ARMISD::VSHL.
    5319             : 
    5320             : unsigned fastEmit_ARMISD_VSHL_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5321           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5322             :     return 0;
    5323           0 :   if ((Subtarget->hasNEON())) {
    5324           0 :     return fastEmitInst_ri(ARM::VSHLiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5325             :   }
    5326             :   return 0;
    5327             : }
    5328             : 
    5329             : unsigned fastEmit_ARMISD_VSHL_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5330           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5331             :     return 0;
    5332           0 :   if ((Subtarget->hasNEON())) {
    5333           0 :     return fastEmitInst_ri(ARM::VSHLiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5334             :   }
    5335             :   return 0;
    5336             : }
    5337             : 
    5338             : unsigned fastEmit_ARMISD_VSHL_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5339           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5340             :     return 0;
    5341           0 :   if ((Subtarget->hasNEON())) {
    5342           0 :     return fastEmitInst_ri(ARM::VSHLiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5343             :   }
    5344             :   return 0;
    5345             : }
    5346             : 
    5347             : unsigned fastEmit_ARMISD_VSHL_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5348           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5349             :     return 0;
    5350           0 :   if ((Subtarget->hasNEON())) {
    5351           0 :     return fastEmitInst_ri(ARM::VSHLiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5352             :   }
    5353             :   return 0;
    5354             : }
    5355             : 
    5356             : unsigned fastEmit_ARMISD_VSHL_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5357           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5358             :     return 0;
    5359           0 :   if ((Subtarget->hasNEON())) {
    5360           0 :     return fastEmitInst_ri(ARM::VSHLiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5361             :   }
    5362             :   return 0;
    5363             : }
    5364             : 
    5365             : unsigned fastEmit_ARMISD_VSHL_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5366           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5367             :     return 0;
    5368           0 :   if ((Subtarget->hasNEON())) {
    5369           0 :     return fastEmitInst_ri(ARM::VSHLiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5370             :   }
    5371             :   return 0;
    5372             : }
    5373             : 
    5374             : unsigned fastEmit_ARMISD_VSHL_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5375           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5376             :     return 0;
    5377           0 :   if ((Subtarget->hasNEON())) {
    5378           0 :     return fastEmitInst_ri(ARM::VSHLiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5379             :   }
    5380             :   return 0;
    5381             : }
    5382             : 
    5383             : unsigned fastEmit_ARMISD_VSHL_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5384           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5385             :     return 0;
    5386           0 :   if ((Subtarget->hasNEON())) {
    5387           0 :     return fastEmitInst_ri(ARM::VSHLiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5388             :   }
    5389             :   return 0;
    5390             : }
    5391             : 
    5392           0 : unsigned fastEmit_ARMISD_VSHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5393           0 :   switch (VT.SimpleTy) {
    5394           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHL_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5395           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHL_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5396           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHL_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5397           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHL_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5398           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHL_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5399           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHL_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5400           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHL_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5401           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHL_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5402             :   default: return 0;
    5403             :   }
    5404             : }
    5405             : 
    5406             : // FastEmit functions for ARMISD::VSHRs.
    5407             : 
    5408             : unsigned fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5409           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5410             :     return 0;
    5411           0 :   if ((Subtarget->hasNEON())) {
    5412           0 :     return fastEmitInst_ri(ARM::VSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5413             :   }
    5414             :   return 0;
    5415             : }
    5416             : 
    5417             : unsigned fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5418           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5419             :     return 0;
    5420           0 :   if ((Subtarget->hasNEON())) {
    5421           0 :     return fastEmitInst_ri(ARM::VSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5422             :   }
    5423             :   return 0;
    5424             : }
    5425             : 
    5426             : unsigned fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5427           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5428             :     return 0;
    5429           0 :   if ((Subtarget->hasNEON())) {
    5430           0 :     return fastEmitInst_ri(ARM::VSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5431             :   }
    5432             :   return 0;
    5433             : }
    5434             : 
    5435             : unsigned fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5436           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5437             :     return 0;
    5438           0 :   if ((Subtarget->hasNEON())) {
    5439           0 :     return fastEmitInst_ri(ARM::VSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5440             :   }
    5441             :   return 0;
    5442             : }
    5443             : 
    5444             : unsigned fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5445           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5446             :     return 0;
    5447           0 :   if ((Subtarget->hasNEON())) {
    5448           0 :     return fastEmitInst_ri(ARM::VSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5449             :   }
    5450             :   return 0;
    5451             : }
    5452             : 
    5453             : unsigned fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5454           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5455             :     return 0;
    5456           0 :   if ((Subtarget->hasNEON())) {
    5457           0 :     return fastEmitInst_ri(ARM::VSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5458             :   }
    5459             :   return 0;
    5460             : }
    5461             : 
    5462             : unsigned fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5463           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5464             :     return 0;
    5465           0 :   if ((Subtarget->hasNEON())) {
    5466           0 :     return fastEmitInst_ri(ARM::VSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5467             :   }
    5468             :   return 0;
    5469             : }
    5470             : 
    5471             : unsigned fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5472           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5473             :     return 0;
    5474           0 :   if ((Subtarget->hasNEON())) {
    5475           0 :     return fastEmitInst_ri(ARM::VSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5476             :   }
    5477             :   return 0;
    5478             : }
    5479             : 
    5480           0 : unsigned fastEmit_ARMISD_VSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5481           0 :   switch (VT.SimpleTy) {
    5482           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5483           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5484           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5485           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5486           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5487           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5488           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5489           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5490             :   default: return 0;
    5491             :   }
    5492             : }
    5493             : 
    5494             : // FastEmit functions for ARMISD::VSHRu.
    5495             : 
    5496             : unsigned fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5497           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5498             :     return 0;
    5499           0 :   if ((Subtarget->hasNEON())) {
    5500           0 :     return fastEmitInst_ri(ARM::VSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5501             :   }
    5502             :   return 0;
    5503             : }
    5504             : 
    5505             : unsigned fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5506           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5507             :     return 0;
    5508           0 :   if ((Subtarget->hasNEON())) {
    5509           0 :     return fastEmitInst_ri(ARM::VSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5510             :   }
    5511             :   return 0;
    5512             : }
    5513             : 
    5514             : unsigned fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5515           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5516             :     return 0;
    5517           0 :   if ((Subtarget->hasNEON())) {
    5518           0 :     return fastEmitInst_ri(ARM::VSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5519             :   }
    5520             :   return 0;
    5521             : }
    5522             : 
    5523             : unsigned fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5524           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5525             :     return 0;
    5526           0 :   if ((Subtarget->hasNEON())) {
    5527           0 :     return fastEmitInst_ri(ARM::VSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5528             :   }
    5529             :   return 0;
    5530             : }
    5531             : 
    5532             : unsigned fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5533           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5534             :     return 0;
    5535           0 :   if ((Subtarget->hasNEON())) {
    5536           0 :     return fastEmitInst_ri(ARM::VSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5537             :   }
    5538             :   return 0;
    5539             : }
    5540             : 
    5541             : unsigned fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5542           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5543             :     return 0;
    5544           0 :   if ((Subtarget->hasNEON())) {
    5545           0 :     return fastEmitInst_ri(ARM::VSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5546             :   }
    5547             :   return 0;
    5548             : }
    5549             : 
    5550             : unsigned fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5551           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5552             :     return 0;
    5553           0 :   if ((Subtarget->hasNEON())) {
    5554           0 :     return fastEmitInst_ri(ARM::VSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5555             :   }
    5556             :   return 0;
    5557             : }
    5558             : 
    5559             : unsigned fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5560           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5561             :     return 0;
    5562           0 :   if ((Subtarget->hasNEON())) {
    5563           0 :     return fastEmitInst_ri(ARM::VSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5564             :   }
    5565             :   return 0;
    5566             : }
    5567             : 
    5568           0 : unsigned fastEmit_ARMISD_VSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5569           0 :   switch (VT.SimpleTy) {
    5570           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5571           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5572           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5573           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5574           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5575           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5576           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5577           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5578             :   default: return 0;
    5579             :   }
    5580             : }
    5581             : 
    5582             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    5583             : 
    5584           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5585           0 :   if (RetVT.SimpleTy != MVT::i32)
    5586             :     return 0;
    5587           0 :   if ((!Subtarget->hasSlowVGETLNi32()) && (Subtarget->hasVFP2())) {
    5588           0 :     return fastEmitInst_ri(ARM::VGETLNi32, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5589             :   }
    5590             :   return 0;
    5591             : }
    5592             : 
    5593             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5594           0 :   switch (VT.SimpleTy) {
    5595           0 :   case MVT::v2i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5596             :   default: return 0;
    5597             :   }
    5598             : }
    5599             : 
    5600             : // FastEmit functions for ISD::SHL.
    5601             : 
    5602           3 : unsigned fastEmit_ISD_SHL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5603           3 :   if (RetVT.SimpleTy != MVT::i32)
    5604             :     return 0;
    5605           3 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5606           0 :     return fastEmitInst_ri(ARM::tLSLri, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5607             :   }
    5608             :   return 0;
    5609             : }
    5610             : 
    5611             : unsigned fastEmit_ISD_SHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5612           3 :   switch (VT.SimpleTy) {
    5613           3 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5614             :   default: return 0;
    5615             :   }
    5616             : }
    5617             : 
    5618             : // Top-level FastEmit function.
    5619             : 
    5620         506 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    5621        1012 :   if (VT == MVT::i32 && Predicate_mod_imm(imm1))
    5622         255 :     if (unsigned Reg = fastEmit_ri_Predicate_mod_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5623             :       return Reg;
    5624             : 
    5625         464 :   if (VT == MVT::i32 && Predicate_imm0_7(imm1))
    5626          27 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_7(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5627             :       return Reg;
    5628             : 
    5629         928 :   if (VT == MVT::i32 && Predicate_imm8_255(imm1))
    5630          13 :     if (unsigned Reg = fastEmit_ri_Predicate_imm8_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5631             :       return Reg;
    5632             : 
    5633         464 :   if (VT == MVT::i32 && Predicate_imm0_255(imm1))
    5634          40 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5635             :       return Reg;
    5636             : 
    5637         928 :   if (VT == MVT::i32 && Predicate_t2_so_imm(imm1))
    5638         243 :     if (unsigned Reg = fastEmit_ri_Predicate_t2_so_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5639             :       return Reg;
    5640             : 
    5641         236 :   if (VT == MVT::i32 && Predicate_imm0_4095(imm1))
    5642         210 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_4095(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5643             :       return Reg;
    5644             : 
    5645          94 :   if (VT == MVT::i32 && Predicate_imm1_31(imm1))
    5646          15 :     if (unsigned Reg = fastEmit_ri_Predicate_imm1_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5647             :       return Reg;
    5648             : 
    5649          41 :   if (VT == MVT::i32 && Predicate_imm0_31(imm1))
    5650           9 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5651             :       return Reg;
    5652             : 
    5653          82 :   if (VT == MVT::i32 && Predicate_shr_imm8(imm1))
    5654           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5655             :       return Reg;
    5656             : 
    5657          82 :   if (VT == MVT::i32 && Predicate_shr_imm16(imm1))
    5658           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5659             :       return Reg;
    5660             : 
    5661          82 :   if (VT == MVT::i32 && Predicate_shr_imm32(imm1))
    5662           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5663             :       return Reg;
    5664             : 
    5665          41 :   if (VT == MVT::i32 && Predicate_VectorIndex32(imm1))
    5666           0 :     if (unsigned Reg = fastEmit_ri_Predicate_VectorIndex32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5667             :       return Reg;
    5668             : 
    5669          41 :   switch (Opcode) {
    5670           0 :   case ARMISD::PIC_ADD: return fastEmit_ARMISD_PIC_ADD_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5671           0 :   case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5672           0 :   case ARMISD::VGETLANEs: return fastEmit_ARMISD_VGETLANEs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5673           0 :   case ARMISD::VGETLANEu: return fastEmit_ARMISD_VGETLANEu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5674           0 :   case ARMISD::VQSHLs: return fastEmit_ARMISD_VQSHLs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5675           0 :   case ARMISD::VQSHLsu: return fastEmit_ARMISD_VQSHLsu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5676           0 :   case ARMISD::VQSHLu: return fastEmit_ARMISD_VQSHLu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5677           0 :   case ARMISD::VRSHRs: return fastEmit_ARMISD_VRSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5678           0 :   case ARMISD::VRSHRu: return fastEmit_ARMISD_VRSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5679           0 :   case ARMISD::VSHL: return fastEmit_ARMISD_VSHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5680           0 :   case ARMISD::VSHRs: return fastEmit_ARMISD_VSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5681           0 :   case ARMISD::VSHRu: return fastEmit_ARMISD_VSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5682           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5683           3 :   case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5684             :   default: return 0;
    5685             :   }
    5686             : }
    5687             : 
    5688             : // FastEmit functions for ARMISD::CMN.
    5689             : 
    5690             : unsigned fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5691           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5692             :     return 0;
    5693           0 :   if ((!Subtarget->isThumb())) {
    5694           0 :     return fastEmitInst_ri(ARM::CMNri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5695             :   }
    5696             :   return 0;
    5697             : }
    5698             : 
    5699           0 : unsigned fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5700           0 :   switch (VT.SimpleTy) {
    5701           0 :   case MVT::i32: return fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5702             :   default: return 0;
    5703             :   }
    5704             : }
    5705             : 
    5706             : // FastEmit functions for ARMISD::CMP.
    5707             : 
    5708             : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5709           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5710             :     return 0;
    5711           0 :   if ((!Subtarget->isThumb())) {
    5712           0 :     return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5713             :   }
    5714             :   return 0;
    5715             : }
    5716             : 
    5717           0 : unsigned fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5718           0 :   switch (VT.SimpleTy) {
    5719           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5720             :   default: return 0;
    5721             :   }
    5722             : }
    5723             : 
    5724             : // FastEmit functions for ARMISD::CMPZ.
    5725             : 
    5726             : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5727           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5728             :     return 0;
    5729           0 :   if ((!Subtarget->isThumb())) {
    5730           0 :     return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5731             :   }
    5732             :   return 0;
    5733             : }
    5734             : 
    5735           0 : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5736           0 :   switch (VT.SimpleTy) {
    5737           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5738             :   default: return 0;
    5739             :   }
    5740             : }
    5741             : 
    5742             : // FastEmit functions for ISD::ADD.
    5743             : 
    5744             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5745         234 :   if (RetVT.SimpleTy != MVT::i32)
    5746             :     return 0;
    5747         234 :   if ((!Subtarget->isThumb())) {
    5748          38 :     return fastEmitInst_ri(ARM::ADDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5749             :   }
    5750             :   return 0;
    5751             : }
    5752             : 
    5753         234 : unsigned fastEmit_ISD_ADD_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5754         234 :   switch (VT.SimpleTy) {
    5755         234 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5756             :   default: return 0;
    5757             :   }
    5758             : }
    5759             : 
    5760             : // FastEmit functions for ISD::AND.
    5761             : 
    5762             : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5763           3 :   if (RetVT.SimpleTy != MVT::i32)
    5764             :     return 0;
    5765           3 :   if ((!Subtarget->isThumb())) {
    5766           2 :     return fastEmitInst_ri(ARM::ANDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5767             :   }
    5768             :   return 0;
    5769             : }
    5770             : 
    5771           3 : unsigned fastEmit_ISD_AND_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5772           3 :   switch (VT.SimpleTy) {
    5773           3 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5774             :   default: return 0;
    5775             :   }
    5776             : }
    5777             : 
    5778             : // FastEmit functions for ISD::OR.
    5779             : 
    5780             : unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5781           3 :   if (RetVT.SimpleTy != MVT::i32)
    5782             :     return 0;
    5783           3 :   if ((!Subtarget->isThumb())) {
    5784           2 :     return fastEmitInst_ri(ARM::ORRri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5785             :   }
    5786             :   return 0;
    5787             : }
    5788             : 
    5789           3 : unsigned fastEmit_ISD_OR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5790           3 :   switch (VT.SimpleTy) {
    5791           3 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5792             :   default: return 0;
    5793             :   }
    5794             : }
    5795             : 
    5796             : // FastEmit functions for ISD::SUB.
    5797             : 
    5798             : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5799           0 :   if (RetVT.SimpleTy != MVT::i32)
    5800             :     return 0;
    5801           0 :   if ((!Subtarget->isThumb())) {
    5802           0 :     return fastEmitInst_ri(ARM::SUBri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5803             :   }
    5804             :   return 0;
    5805             : }
    5806             : 
    5807           0 : unsigned fastEmit_ISD_SUB_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5808           0 :   switch (VT.SimpleTy) {
    5809           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5810             :   default: return 0;
    5811             :   }
    5812             : }
    5813             : 
    5814             : // FastEmit functions for ISD::XOR.
    5815             : 
    5816             : unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5817           0 :   if (RetVT.SimpleTy != MVT::i32)
    5818             :     return 0;
    5819           0 :   if ((!Subtarget->isThumb())) {
    5820           0 :     return fastEmitInst_ri(ARM::EORri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5821             :   }
    5822             :   return 0;
    5823             : }
    5824             : 
    5825           0 : unsigned fastEmit_ISD_XOR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5826           0 :   switch (VT.SimpleTy) {
    5827           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5828             :   default: return 0;
    5829             :   }
    5830             : }
    5831             : 
    5832             : // Top-level FastEmit function.
    5833             : 
    5834         255 : unsigned fastEmit_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5835         255 :   switch (Opcode) {
    5836           0 :   case ARMISD::CMN: return fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5837           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5838           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5839         234 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5840           3 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5841           3 :   case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5842           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5843           0 :   case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5844             :   default: return 0;
    5845             :   }
    5846             : }
    5847             : 
    5848             : // FastEmit functions for ISD::ADD.
    5849             : 
    5850          11 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5851          11 :   if (RetVT.SimpleTy != MVT::i32)
    5852             :     return 0;
    5853          11 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5854           0 :     return fastEmitInst_ri(ARM::tADDi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5855             :   }
    5856             :   return 0;
    5857             : }
    5858             : 
    5859             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5860          11 :   switch (VT.SimpleTy) {
    5861          11 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1);
    5862             :   default: return 0;
    5863             :   }
    5864             : }
    5865             : 
    5866             : // Top-level FastEmit function.
    5867             : 
    5868          27 : unsigned fastEmit_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5869          27 :   switch (Opcode) {
    5870          11 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1);
    5871             :   default: return 0;
    5872             :   }
    5873             : }
    5874             : 
    5875             : // FastEmit functions for ISD::ADD.
    5876             : 
    5877          12 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5878          12 :   if (RetVT.SimpleTy != MVT::i32)
    5879             :     return 0;
    5880          12 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5881           0 :     return fastEmitInst_ri(ARM::tADDi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5882             :   }
    5883             :   return 0;
    5884             : }
    5885             : 
    5886             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5887          12 :   switch (VT.SimpleTy) {
    5888          12 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(RetVT, Op0, Op0IsKill, imm1);
    5889             :   default: return 0;
    5890             :   }
    5891             : }
    5892             : 
    5893             : // Top-level FastEmit function.
    5894             : 
    5895          13 : unsigned fastEmit_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5896          13 :   switch (Opcode) {
    5897          12 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm8_255(VT, RetVT, Op0, Op0IsKill, imm1);
    5898             :   default: return 0;
    5899             :   }
    5900             : }
    5901             : 
    5902             : // FastEmit functions for ARMISD::CMP.
    5903             : 
    5904           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5905           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5906             :     return 0;
    5907           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5908           0 :     return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5909             :   }
    5910             :   return 0;
    5911             : }
    5912             : 
    5913             : unsigned fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5914           0 :   switch (VT.SimpleTy) {
    5915           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1);
    5916             :   default: return 0;
    5917             :   }
    5918             : }
    5919             : 
    5920             : // FastEmit functions for ARMISD::CMPZ.
    5921             : 
    5922           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5923           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5924             :     return 0;
    5925           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5926           0 :     return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5927             :   }
    5928             :   return 0;
    5929             : }
    5930             : 
    5931             : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5932           0 :   switch (VT.SimpleTy) {
    5933           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1);
    5934             :   default: return 0;
    5935             :   }
    5936             : }
    5937             : 
    5938             : // Top-level FastEmit function.
    5939             : 
    5940          40 : unsigned fastEmit_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5941          40 :   switch (Opcode) {
    5942           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1);
    5943           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1);
    5944             :   default: return 0;
    5945             :   }
    5946             : }
    5947             : 
    5948             : // FastEmit functions for ARMISD::CMP.
    5949             : 
    5950           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5951           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5952             :     return 0;
    5953           0 :   if ((Subtarget->isThumb2())) {
    5954           0 :     return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    5955             :   }
    5956             :   return 0;
    5957             : }
    5958             : 
    5959             : unsigned fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5960           0 :   switch (VT.SimpleTy) {
    5961           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5962             :   default: return 0;
    5963             :   }
    5964             : }
    5965             : 
    5966             : // FastEmit functions for ARMISD::CMPZ.
    5967             : 
    5968           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5969           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5970             :     return 0;
    5971           0 :   if ((Subtarget->isThumb2())) {
    5972           0 :     return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    5973             :   }
    5974             :   return 0;
    5975             : }
    5976             : 
    5977             : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5978           0 :   switch (VT.SimpleTy) {
    5979           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5980             :   default: return 0;
    5981             :   }
    5982             : }
    5983             : 
    5984             : // FastEmit functions for ISD::ADD.
    5985             : 
    5986         226 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5987         226 :   if (RetVT.SimpleTy != MVT::i32)
    5988             :     return 0;
    5989         226 :   if ((Subtarget->isThumb2())) {
    5990         226 :     return fastEmitInst_ri(ARM::t2ADDri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    5991             :   }
    5992             :   return 0;
    5993             : }
    5994             : 
    5995             : unsigned fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5996         226 :   switch (VT.SimpleTy) {
    5997         226 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    5998             :   default: return 0;
    5999             :   }
    6000             : }
    6001             : 
    6002             : // FastEmit functions for ISD::AND.
    6003             : 
    6004           1 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6005           1 :   if (RetVT.SimpleTy != MVT::i32)
    6006             :     return 0;
    6007           1 :   if ((Subtarget->isThumb2())) {
    6008           1 :     return fastEmitInst_ri(ARM::t2ANDri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6009             :   }
    6010             :   return 0;
    6011             : }
    6012             : 
    6013             : unsigned fastEmit_ISD_AND_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6014           1 :   switch (VT.SimpleTy) {
    6015           1 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6016             :   default: return 0;
    6017             :   }
    6018             : }
    6019             : 
    6020             : // FastEmit functions for ISD::OR.
    6021             : 
    6022           1 : unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6023           1 :   if (RetVT.SimpleTy != MVT::i32)
    6024             :     return 0;
    6025           1 :   if ((Subtarget->isThumb2())) {
    6026           1 :     return fastEmitInst_ri(ARM::t2ORRri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6027             :   }
    6028             :   return 0;
    6029             : }
    6030             : 
    6031             : unsigned fastEmit_ISD_OR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6032           1 :   switch (VT.SimpleTy) {
    6033           1 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6034             :   default: return 0;
    6035             :   }
    6036             : }
    6037             : 
    6038             : // FastEmit functions for ISD::SUB.
    6039             : 
    6040           0 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6041           0 :   if (RetVT.SimpleTy != MVT::i32)
    6042             :     return 0;
    6043           0 :   if ((Subtarget->isThumb2())) {
    6044           0 :     return fastEmitInst_ri(ARM::t2SUBri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6045             :   }
    6046             :   return 0;
    6047             : }
    6048             : 
    6049             : unsigned fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6050           0 :   switch (VT.SimpleTy) {
    6051           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6052             :   default: return 0;
    6053             :   }
    6054             : }
    6055             : 
    6056             : // FastEmit functions for ISD::XOR.
    6057             : 
    6058           0 : unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6059           0 :   if (RetVT.SimpleTy != MVT::i32)
    6060             :     return 0;
    6061           0 :   if ((Subtarget->isThumb2())) {
    6062           0 :     return fastEmitInst_ri(ARM::t2EORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6063             :   }
    6064             :   return 0;
    6065             : }
    6066             : 
    6067             : unsigned fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6068           0 :   switch (VT.SimpleTy) {
    6069           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6070             :   default: return 0;
    6071             :   }
    6072             : }
    6073             : 
    6074             : // Top-level FastEmit function.
    6075             : 
    6076         243 : unsigned fastEmit_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6077         243 :   switch (Opcode) {
    6078           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6079           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6080         226 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6081           1 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6082           1 :   case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6083           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6084           0 :   case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6085             :   default: return 0;
    6086             :   }
    6087             : }
    6088             : 
    6089             : // FastEmit functions for ISD::ADD.
    6090             : 
    6091         195 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6092         195 :   if (RetVT.SimpleTy != MVT::i32)
    6093             :     return 0;
    6094         195 :   if ((Subtarget->isThumb2())) {
    6095         189 :     return fastEmitInst_ri(ARM::t2ADDri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6096             :   }
    6097             :   return 0;
    6098             : }
    6099             : 
    6100             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6101         195 :   switch (VT.SimpleTy) {
    6102         195 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1);
    6103             :   default: return 0;
    6104             :   }
    6105             : }
    6106             : 
    6107             : // FastEmit functions for ISD::SUB.
    6108             : 
    6109           0 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6110           0 :   if (RetVT.SimpleTy != MVT::i32)
    6111             :     return 0;
    6112           0 :   if ((Subtarget->isThumb2())) {
    6113           0 :     return fastEmitInst_ri(ARM::t2SUBri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6114             :   }
    6115             :   return 0;
    6116             : }
    6117             : 
    6118             : unsigned fastEmit_ISD_SUB_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6119           0 :   switch (VT.SimpleTy) {
    6120           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1);
    6121             :   default: return 0;
    6122             :   }
    6123             : }
    6124             : 
    6125             : // Top-level FastEmit function.
    6126             : 
    6127         210 : unsigned fastEmit_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6128         210 :   switch (Opcode) {
    6129         195 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
    6130           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
    6131             :   default: return 0;
    6132             :   }
    6133             : }
    6134             : 
    6135             : // FastEmit functions for ISD::SHL.
    6136             : 
    6137           9 : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6138           9 :   if (RetVT.SimpleTy != MVT::i32)
    6139             :     return 0;
    6140           9 :   if ((Subtarget->isThumb2())) {
    6141           6 :     return fastEmitInst_ri(ARM::t2LSLri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6142             :   }
    6143             :   return 0;
    6144             : }
    6145             : 
    6146             : unsigned fastEmit_ISD_SHL_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6147           9 :   switch (VT.SimpleTy) {
    6148           9 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(RetVT, Op0, Op0IsKill, imm1);
    6149             :   default: return 0;
    6150             :   }
    6151             : }
    6152             : 
    6153             : // Top-level FastEmit function.
    6154             : 
    6155          15 : unsigned fastEmit_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6156          15 :   switch (Opcode) {
    6157           9 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_imm1_31(VT, RetVT, Op0, Op0IsKill, imm1);
    6158             :   default: return 0;
    6159             :   }
    6160             : }
    6161             : 
    6162             : // FastEmit functions for ISD::ROTR.
    6163             : 
    6164           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6165           0 :   if (RetVT.SimpleTy != MVT::i32)
    6166             :     return 0;
    6167           0 :   if ((Subtarget->isThumb2())) {
    6168           0 :     return fastEmitInst_ri(ARM::t2RORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6169             :   }
    6170             :   return 0;
    6171             : }
    6172             : 
    6173             : unsigned fastEmit_ISD_ROTR_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6174           0 :   switch (VT.SimpleTy) {
    6175           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1);
    6176             :   default: return 0;
    6177             :   }
    6178             : }
    6179             : 
    6180             : // Top-level FastEmit function.
    6181             : 
    6182           9 : unsigned fastEmit_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6183           9 :   switch (Opcode) {
    6184           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1);
    6185             :   default: return 0;
    6186             :   }
    6187             : }
    6188             : 
    6189             : // FastEmit functions for ARMISD::VQRSHRNs.
    6190             : 
    6191             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6192           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6193             :     return 0;
    6194           0 :   if ((Subtarget->hasNEON())) {
    6195           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6196             :   }
    6197             :   return 0;
    6198             : }
    6199             : 
    6200           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6201           0 :   switch (VT.SimpleTy) {
    6202           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6203             :   default: return 0;
    6204             :   }
    6205             : }
    6206             : 
    6207             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6208             : 
    6209             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6210           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6211             :     return 0;
    6212           0 :   if ((Subtarget->hasNEON())) {
    6213           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6214             :   }
    6215             :   return 0;
    6216             : }
    6217             : 
    6218           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6219           0 :   switch (VT.SimpleTy) {
    6220           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6221             :   default: return 0;
    6222             :   }
    6223             : }
    6224             : 
    6225             : // FastEmit functions for ARMISD::VQRSHRNu.
    6226             : 
    6227             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6228           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6229             :     return 0;
    6230           0 :   if ((Subtarget->hasNEON())) {
    6231           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6232             :   }
    6233             :   return 0;
    6234             : }
    6235             : 
    6236           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6237           0 :   switch (VT.SimpleTy) {
    6238           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6239             :   default: return 0;
    6240             :   }
    6241             : }
    6242             : 
    6243             : // FastEmit functions for ARMISD::VQSHRNs.
    6244             : 
    6245             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6246           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6247             :     return 0;
    6248           0 :   if ((Subtarget->hasNEON())) {
    6249           0 :     return fastEmitInst_ri(ARM::VQSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6250             :   }
    6251             :   return 0;
    6252             : }
    6253             : 
    6254           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6255           0 :   switch (VT.SimpleTy) {
    6256           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6257             :   default: return 0;
    6258             :   }
    6259             : }
    6260             : 
    6261             : // FastEmit functions for ARMISD::VQSHRNsu.
    6262             : 
    6263             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6264           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6265             :     return 0;
    6266           0 :   if ((Subtarget->hasNEON())) {
    6267           0 :     return fastEmitInst_ri(ARM::VQSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6268             :   }
    6269             :   return 0;
    6270             : }
    6271             : 
    6272           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6273           0 :   switch (VT.SimpleTy) {
    6274           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6275             :   default: return 0;
    6276             :   }
    6277             : }
    6278             : 
    6279             : // FastEmit functions for ARMISD::VQSHRNu.
    6280             : 
    6281             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6282           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6283             :     return 0;
    6284           0 :   if ((Subtarget->hasNEON())) {
    6285           0 :     return fastEmitInst_ri(ARM::VQSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6286             :   }
    6287             :   return 0;
    6288             : }
    6289             : 
    6290           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6291           0 :   switch (VT.SimpleTy) {
    6292           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6293             :   default: return 0;
    6294             :   }
    6295             : }
    6296             : 
    6297             : // FastEmit functions for ARMISD::VRSHRN.
    6298             : 
    6299             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6300           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6301             :     return 0;
    6302           0 :   if ((Subtarget->hasNEON())) {
    6303           0 :     return fastEmitInst_ri(ARM::VRSHRNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6304             :   }
    6305             :   return 0;
    6306             : }
    6307             : 
    6308           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6309           0 :   switch (VT.SimpleTy) {
    6310           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6311             :   default: return 0;
    6312             :   }
    6313             : }
    6314             : 
    6315             : // Top-level FastEmit function.
    6316             : 
    6317           9 : unsigned fastEmit_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6318           9 :   switch (Opcode) {
    6319           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6320           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6321           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6322           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6323           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6324           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6325           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6326             :   default: return 0;
    6327             :   }
    6328             : }
    6329             : 
    6330             : // FastEmit functions for ARMISD::VQRSHRNs.
    6331             : 
    6332             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6333           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6334             :     return 0;
    6335           0 :   if ((Subtarget->hasNEON())) {
    6336           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6337             :   }
    6338             :   return 0;
    6339             : }
    6340             : 
    6341           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6342           0 :   switch (VT.SimpleTy) {
    6343           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6344             :   default: return 0;
    6345             :   }
    6346             : }
    6347             : 
    6348             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6349             : 
    6350             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6351           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6352             :     return 0;
    6353           0 :   if ((Subtarget->hasNEON())) {
    6354           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6355             :   }
    6356             :   return 0;
    6357             : }
    6358             : 
    6359           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6360           0 :   switch (VT.SimpleTy) {
    6361           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6362             :   default: return 0;
    6363             :   }
    6364             : }
    6365             : 
    6366             : // FastEmit functions for ARMISD::VQRSHRNu.
    6367             : 
    6368             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6369           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6370             :     return 0;
    6371           0 :   if ((Subtarget->hasNEON())) {
    6372           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6373             :   }
    6374             :   return 0;
    6375             : }
    6376             : 
    6377           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6378           0 :   switch (VT.SimpleTy) {
    6379           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6380             :   default: return 0;
    6381             :   }
    6382             : }
    6383             : 
    6384             : // FastEmit functions for ARMISD::VQSHRNs.
    6385             : 
    6386             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6387           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6388             :     return 0;
    6389           0 :   if ((Subtarget->hasNEON())) {
    6390           0 :     return fastEmitInst_ri(ARM::VQSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6391             :   }
    6392             :   return 0;
    6393             : }
    6394             : 
    6395           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6396           0 :   switch (VT.SimpleTy) {
    6397           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6398             :   default: return 0;
    6399             :   }
    6400             : }
    6401             : 
    6402             : // FastEmit functions for ARMISD::VQSHRNsu.
    6403             : 
    6404             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6405           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6406             :     return 0;
    6407           0 :   if ((Subtarget->hasNEON())) {
    6408           0 :     return fastEmitInst_ri(ARM::VQSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6409             :   }
    6410             :   return 0;
    6411             : }
    6412             : 
    6413           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6414           0 :   switch (VT.SimpleTy) {
    6415           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6416             :   default: return 0;
    6417             :   }
    6418             : }
    6419             : 
    6420             : // FastEmit functions for ARMISD::VQSHRNu.
    6421             : 
    6422             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6423           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6424             :     return 0;
    6425           0 :   if ((Subtarget->hasNEON())) {
    6426           0 :     return fastEmitInst_ri(ARM::VQSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6427             :   }
    6428             :   return 0;
    6429             : }
    6430             : 
    6431           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6432           0 :   switch (VT.SimpleTy) {
    6433           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6434             :   default: return 0;
    6435             :   }
    6436             : }
    6437             : 
    6438             : // FastEmit functions for ARMISD::VRSHRN.
    6439             : 
    6440             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6441           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6442             :     return 0;
    6443           0 :   if ((Subtarget->hasNEON())) {
    6444           0 :     return fastEmitInst_ri(ARM::VRSHRNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6445             :   }
    6446             :   return 0;
    6447             : }
    6448             : 
    6449           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6450           0 :   switch (VT.SimpleTy) {
    6451           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6452             :   default: return 0;
    6453             :   }
    6454             : }
    6455             : 
    6456             : // Top-level FastEmit function.
    6457             : 
    6458           9 : unsigned fastEmit_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6459           9 :   switch (Opcode) {
    6460           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6461           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6462           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6463           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6464           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6465           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6466           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6467             :   default: return 0;
    6468             :   }
    6469             : }
    6470             : 
    6471             : // FastEmit functions for ARMISD::VQRSHRNs.
    6472             : 
    6473             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6474           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6475             :     return 0;
    6476           0 :   if ((Subtarget->hasNEON())) {
    6477           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6478             :   }
    6479             :   return 0;
    6480             : }
    6481             : 
    6482           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6483           0 :   switch (VT.SimpleTy) {
    6484           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6485             :   default: return 0;
    6486             :   }
    6487             : }
    6488             : 
    6489             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6490             : 
    6491             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6492           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6493             :     return 0;
    6494           0 :   if ((Subtarget->hasNEON())) {
    6495           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6496             :   }
    6497             :   return 0;
    6498             : }
    6499             : 
    6500           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6501           0 :   switch (VT.SimpleTy) {
    6502           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6503             :   default: return 0;
    6504             :   }
    6505             : }
    6506             : 
    6507             : // FastEmit functions for ARMISD::VQRSHRNu.
    6508             : 
    6509             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6510           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6511             :     return 0;
    6512           0 :   if ((Subtarget->hasNEON())) {
    6513           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6514             :   }
    6515             :   return 0;
    6516             : }
    6517             : 
    6518           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6519           0 :   switch (VT.SimpleTy) {
    6520           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6521             :   default: return 0;
    6522             :   }
    6523             : }
    6524             : 
    6525             : // FastEmit functions for ARMISD::VQSHRNs.
    6526             : 
    6527             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6528           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6529             :     return 0;
    6530           0 :   if ((Subtarget->hasNEON())) {
    6531           0 :     return fastEmitInst_ri(ARM::VQSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6532             :   }
    6533             :   return 0;
    6534             : }
    6535             : 
    6536           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6537           0 :   switch (VT.SimpleTy) {
    6538           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6539             :   default: return 0;
    6540             :   }
    6541             : }
    6542             : 
    6543             : // FastEmit functions for ARMISD::VQSHRNsu.
    6544             : 
    6545             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6546           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6547             :     return 0;
    6548           0 :   if ((Subtarget->hasNEON())) {
    6549           0 :     return fastEmitInst_ri(ARM::VQSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6550             :   }
    6551             :   return 0;
    6552             : }
    6553             : 
    6554           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6555           0 :   switch (VT.SimpleTy) {
    6556           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6557             :   default: return 0;
    6558             :   }
    6559             : }
    6560             : 
    6561             : // FastEmit functions for ARMISD::VQSHRNu.
    6562             : 
    6563             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6564           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6565             :     return 0;
    6566           0 :   if ((Subtarget->hasNEON())) {
    6567           0 :     return fastEmitInst_ri(ARM::VQSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6568             :   }
    6569             :   return 0;
    6570             : }
    6571             : 
    6572           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6573           0 :   switch (VT.SimpleTy) {
    6574           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6575             :   default: return 0;
    6576             :   }
    6577             : }
    6578             : 
    6579             : // FastEmit functions for ARMISD::VRSHRN.
    6580             : 
    6581             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6582           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6583             :     return 0;
    6584           0 :   if ((Subtarget->hasNEON())) {
    6585           0 :     return fastEmitInst_ri(ARM::VRSHRNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6586             :   }
    6587             :   return 0;
    6588             : }
    6589             : 
    6590           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6591           0 :   switch (VT.SimpleTy) {
    6592           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6593             :   default: return 0;
    6594             :   }
    6595             : }
    6596             : 
    6597             : // Top-level FastEmit function.
    6598             : 
    6599           9 : unsigned fastEmit_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6600           9 :   switch (Opcode) {
    6601           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6602           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6603           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6604           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6605           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6606           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6607           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6608             :   default: return 0;
    6609             :   }
    6610             : }
    6611             : 
    6612             : // FastEmit functions for ARMISD::VDUPLANE.
    6613             : 
    6614             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6615           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    6616             :     return 0;
    6617           0 :   if ((Subtarget->hasNEON())) {
    6618           0 :     return fastEmitInst_ri(ARM::VDUPLN8q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6619             :   }
    6620             :   return 0;
    6621             : }
    6622             : 
    6623             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6624           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    6625             :     return 0;
    6626           0 :   if ((Subtarget->hasNEON())) {
    6627           0 :     return fastEmitInst_ri(ARM::VDUPLN16q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6628             :   }
    6629             :   return 0;
    6630             : }
    6631             : 
    6632             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6633           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    6634             :     return 0;
    6635           0 :   if ((Subtarget->hasNEON())) {
    6636           0 :     return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6637             :   }
    6638             :   return 0;
    6639             : }
    6640             : 
    6641           0 : unsigned fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6642           0 :   switch (VT.SimpleTy) {
    6643           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6644           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6645           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6646             :   default: return 0;
    6647             :   }
    6648             : }
    6649             : 
    6650             : // Top-level FastEmit function.
    6651             : 
    6652             : unsigned fastEmit_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6653           0 :   switch (Opcode) {
    6654           0 :   case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(VT, RetVT, Op0, Op0IsKill, imm1);
    6655             :   default: return 0;
    6656             :   }
    6657             : }
    6658             : 
    6659             : // FastEmit functions for ISD::Constant.
    6660             : 
    6661          47 : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    6662          47 :   if (RetVT.SimpleTy != MVT::i32)
    6663             :     return 0;
    6664          47 :   if ((Subtarget->isThumb()) && (Subtarget->useMovt(*MF))) {
    6665          15 :     return fastEmitInst_i(ARM::t2MOVi32imm, &ARM::rGPRRegClass, imm0);
    6666             :   }
    6667             :   return 0;
    6668             : }
    6669             : 
    6670             : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
    6671          47 :   switch (VT.SimpleTy) {
    6672          47 :   case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
    6673             :   default: return 0;
    6674             :   }
    6675             : }
    6676             : 
    6677             : // Top-level FastEmit function.
    6678             : 
    6679          41 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
    6680          41 :   switch (Opcode) {
    6681          41 :   case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
    6682             :   default: return 0;
    6683             :   }
    6684             : }
    6685             : 

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