LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/ARM - ARMGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 276 2735 10.1 %
Date: 2018-05-20 00:06:23 Functions: 53 305 17.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the ARM target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_mod_imm(int64_t Imm) {
      12             : 
      13         504 :     return ARM_AM::getSOImmVal(Imm) != -1;
      14             :   
      15             : }
      16             : static bool Predicate_imm0_65535(int64_t Imm) {
      17             : 
      18             :   return Imm >= 0 && Imm < 65536;
      19             : 
      20             : }
      21             : static bool Predicate_imm0_7(int64_t Imm) {
      22             : 
      23             :   return Imm >= 0 && Imm < 8;
      24             : 
      25             : }
      26             : static bool Predicate_imm8_255(int64_t Imm) {
      27             : 
      28         462 :   return Imm >= 8 && Imm < 256;
      29             : 
      30             : }
      31             : static bool Predicate_imm0_255(int64_t Imm) {
      32             :  return Imm >= 0 && Imm < 256; 
      33             : }
      34             : static bool Predicate_t2_so_imm(int64_t Imm) {
      35             : 
      36         462 :     return ARM_AM::getT2SOImmVal(Imm) != -1;
      37             :   
      38             : }
      39             : static bool Predicate_imm0_4095(int64_t Imm) {
      40             : 
      41             :   return Imm >= 0 && Imm < 4096;
      42             : 
      43             : }
      44             : static bool Predicate_imm1_31(int64_t Imm) {
      45          45 :  return Imm > 0 && Imm < 32; 
      46             : }
      47             : static bool Predicate_imm0_31(int64_t Imm) {
      48             : 
      49             :   return Imm >= 0 && Imm < 32;
      50             : 
      51             : }
      52             : static bool Predicate_shr_imm8(int64_t Imm) {
      53          39 :  return Imm > 0 && Imm <= 8; 
      54             : }
      55             : static bool Predicate_shr_imm16(int64_t Imm) {
      56          39 :  return Imm > 0 && Imm <= 16; 
      57             : }
      58             : static bool Predicate_shr_imm32(int64_t Imm) {
      59          39 :  return Imm > 0 && Imm <= 32; 
      60             : }
      61             : static bool Predicate_VectorIndex32(int64_t Imm) {
      62             : 
      63             :   return ((uint64_t)Imm) < 2;
      64             : 
      65             : }
      66             : static bool Predicate_t2_so_imm_neg(int64_t Imm) {
      67             : 
      68             :   return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
      69             : 
      70             : }
      71             : 
      72             : 
      73             : // FastEmit functions for ARMISD::CALL.
      74             : 
      75           0 : unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      76           0 :   if (RetVT.SimpleTy != MVT::isVoid)
      77             :     return 0;
      78           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
      79           0 :     return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill);
      80             :   }
      81             :   return 0;
      82             : }
      83             : 
      84             : unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
      85           0 :   switch (VT.SimpleTy) {
      86           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill);
      87             :   default: return 0;
      88             :   }
      89             : }
      90             : 
      91             : // FastEmit functions for ARMISD::CALL_NOLINK.
      92             : 
      93           0 : unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      94           0 :   if (RetVT.SimpleTy != MVT::isVoid)
      95             :     return 0;
      96           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
      97           0 :     return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
      98             :   }
      99           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
     100           0 :     return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
     101             :   }
     102           0 :   if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
     103           0 :     return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
     104             :   }
     105             :   return 0;
     106             : }
     107             : 
     108             : unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     109           0 :   switch (VT.SimpleTy) {
     110           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill);
     111             :   default: return 0;
     112             :   }
     113             : }
     114             : 
     115             : // FastEmit functions for ARMISD::CALL_PRED.
     116             : 
     117           0 : unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     118           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     119             :     return 0;
     120           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
     121           0 :     return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill);
     122             :   }
     123             :   return 0;
     124             : }
     125             : 
     126             : unsigned fastEmit_ARMISD_CALL_PRED_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     127           0 :   switch (VT.SimpleTy) {
     128           0 :   case MVT::i32: return fastEmit_ARMISD_CALL_PRED_MVT_i32_r(RetVT, Op0, Op0IsKill);
     129             :   default: return 0;
     130             :   }
     131             : }
     132             : 
     133             : // FastEmit functions for ARMISD::RRX.
     134             : 
     135           0 : unsigned fastEmit_ARMISD_RRX_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     136           0 :   if (RetVT.SimpleTy != MVT::i32)
     137             :     return 0;
     138           0 :   if ((Subtarget->isThumb2())) {
     139           0 :     return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill);
     140             :   }
     141           0 :   if ((!Subtarget->isThumb())) {
     142           0 :     return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill);
     143             :   }
     144             :   return 0;
     145             : }
     146             : 
     147             : unsigned fastEmit_ARMISD_RRX_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     148           0 :   switch (VT.SimpleTy) {
     149           0 :   case MVT::i32: return fastEmit_ARMISD_RRX_MVT_i32_r(RetVT, Op0, Op0IsKill);
     150             :   default: return 0;
     151             :   }
     152             : }
     153             : 
     154             : // FastEmit functions for ARMISD::SRA_FLAG.
     155             : 
     156           0 : unsigned fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     157           0 :   if (RetVT.SimpleTy != MVT::i32)
     158             :     return 0;
     159           0 :   if ((Subtarget->isThumb2())) {
     160           0 :     return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
     161             :   }
     162           0 :   if ((!Subtarget->isThumb())) {
     163           0 :     return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
     164             :   }
     165             :   return 0;
     166             : }
     167             : 
     168             : unsigned fastEmit_ARMISD_SRA_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     169           0 :   switch (VT.SimpleTy) {
     170           0 :   case MVT::i32: return fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
     171             :   default: return 0;
     172             :   }
     173             : }
     174             : 
     175             : // FastEmit functions for ARMISD::SRL_FLAG.
     176             : 
     177           0 : unsigned fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     178           0 :   if (RetVT.SimpleTy != MVT::i32)
     179             :     return 0;
     180           0 :   if ((Subtarget->isThumb2())) {
     181           0 :     return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
     182             :   }
     183           0 :   if ((!Subtarget->isThumb())) {
     184           0 :     return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
     185             :   }
     186             :   return 0;
     187             : }
     188             : 
     189             : unsigned fastEmit_ARMISD_SRL_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     190           0 :   switch (VT.SimpleTy) {
     191           0 :   case MVT::i32: return fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
     192             :   default: return 0;
     193             :   }
     194             : }
     195             : 
     196             : // FastEmit functions for ARMISD::TC_RETURN.
     197             : 
     198             : unsigned fastEmit_ARMISD_TC_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     199           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     200             :     return 0;
     201           0 :   return fastEmitInst_r(ARM::TCRETURNri, &ARM::tcGPRRegClass, Op0, Op0IsKill);
     202             : }
     203             : 
     204             : unsigned fastEmit_ARMISD_TC_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     205           0 :   switch (VT.SimpleTy) {
     206           0 :   case MVT::i32: return fastEmit_ARMISD_TC_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill);
     207             :   default: return 0;
     208             :   }
     209             : }
     210             : 
     211             : // FastEmit functions for ARMISD::VCEQZ.
     212             : 
     213             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     214           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     215             :     return 0;
     216           0 :   if ((Subtarget->hasNEON())) {
     217           0 :     return fastEmitInst_r(ARM::VCEQzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     218             :   }
     219             :   return 0;
     220             : }
     221             : 
     222             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     223           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     224             :     return 0;
     225           0 :   if ((Subtarget->hasNEON())) {
     226           0 :     return fastEmitInst_r(ARM::VCEQzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     227             :   }
     228             :   return 0;
     229             : }
     230             : 
     231             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     232           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     233             :     return 0;
     234           0 :   if ((Subtarget->hasNEON())) {
     235           0 :     return fastEmitInst_r(ARM::VCEQzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     236             :   }
     237             :   return 0;
     238             : }
     239             : 
     240             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     241           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     242             :     return 0;
     243           0 :   if ((Subtarget->hasNEON())) {
     244           0 :     return fastEmitInst_r(ARM::VCEQzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     245             :   }
     246             :   return 0;
     247             : }
     248             : 
     249             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     250           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     251             :     return 0;
     252           0 :   if ((Subtarget->hasNEON())) {
     253           0 :     return fastEmitInst_r(ARM::VCEQzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     254             :   }
     255             :   return 0;
     256             : }
     257             : 
     258             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     259           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     260             :     return 0;
     261           0 :   if ((Subtarget->hasNEON())) {
     262           0 :     return fastEmitInst_r(ARM::VCEQzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     263             :   }
     264             :   return 0;
     265             : }
     266             : 
     267           0 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     268           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     269             :     return 0;
     270           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     271           0 :     return fastEmitInst_r(ARM::VCEQzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     272             :   }
     273             :   return 0;
     274             : }
     275             : 
     276           0 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     277           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     278             :     return 0;
     279           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     280           0 :     return fastEmitInst_r(ARM::VCEQzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     281             :   }
     282             :   return 0;
     283             : }
     284             : 
     285             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     286           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     287             :     return 0;
     288           0 :   if ((Subtarget->hasNEON())) {
     289           0 :     return fastEmitInst_r(ARM::VCEQzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     290             :   }
     291             :   return 0;
     292             : }
     293             : 
     294             : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     295           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     296             :     return 0;
     297           0 :   if ((Subtarget->hasNEON())) {
     298           0 :     return fastEmitInst_r(ARM::VCEQzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     299             :   }
     300             :   return 0;
     301             : }
     302             : 
     303           0 : unsigned fastEmit_ARMISD_VCEQZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     304           0 :   switch (VT.SimpleTy) {
     305           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     306           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     307           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     308           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     309           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     310           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     311           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     312           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     313           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     314           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     315             :   default: return 0;
     316             :   }
     317             : }
     318             : 
     319             : // FastEmit functions for ARMISD::VCGEZ.
     320             : 
     321             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     322           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     323             :     return 0;
     324           0 :   if ((Subtarget->hasNEON())) {
     325           0 :     return fastEmitInst_r(ARM::VCGEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     326             :   }
     327             :   return 0;
     328             : }
     329             : 
     330             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     331           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     332             :     return 0;
     333           0 :   if ((Subtarget->hasNEON())) {
     334           0 :     return fastEmitInst_r(ARM::VCGEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     335             :   }
     336             :   return 0;
     337             : }
     338             : 
     339             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     340           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     341             :     return 0;
     342           0 :   if ((Subtarget->hasNEON())) {
     343           0 :     return fastEmitInst_r(ARM::VCGEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     344             :   }
     345             :   return 0;
     346             : }
     347             : 
     348             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     349           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     350             :     return 0;
     351           0 :   if ((Subtarget->hasNEON())) {
     352           0 :     return fastEmitInst_r(ARM::VCGEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     353             :   }
     354             :   return 0;
     355             : }
     356             : 
     357             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     358           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     359             :     return 0;
     360           0 :   if ((Subtarget->hasNEON())) {
     361           0 :     return fastEmitInst_r(ARM::VCGEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     362             :   }
     363             :   return 0;
     364             : }
     365             : 
     366             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     367           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     368             :     return 0;
     369           0 :   if ((Subtarget->hasNEON())) {
     370           0 :     return fastEmitInst_r(ARM::VCGEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     371             :   }
     372             :   return 0;
     373             : }
     374             : 
     375           0 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     376           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     377             :     return 0;
     378           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     379           0 :     return fastEmitInst_r(ARM::VCGEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     380             :   }
     381             :   return 0;
     382             : }
     383             : 
     384           0 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     385           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     386             :     return 0;
     387           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     388           0 :     return fastEmitInst_r(ARM::VCGEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     389             :   }
     390             :   return 0;
     391             : }
     392             : 
     393             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     394           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     395             :     return 0;
     396           0 :   if ((Subtarget->hasNEON())) {
     397           0 :     return fastEmitInst_r(ARM::VCGEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     398             :   }
     399             :   return 0;
     400             : }
     401             : 
     402             : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     403           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     404             :     return 0;
     405           0 :   if ((Subtarget->hasNEON())) {
     406           0 :     return fastEmitInst_r(ARM::VCGEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     407             :   }
     408             :   return 0;
     409             : }
     410             : 
     411           0 : unsigned fastEmit_ARMISD_VCGEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     412           0 :   switch (VT.SimpleTy) {
     413           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     414           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     415           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     416           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     417           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     418           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     419           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     420           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     421           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     422           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     423             :   default: return 0;
     424             :   }
     425             : }
     426             : 
     427             : // FastEmit functions for ARMISD::VCGTZ.
     428             : 
     429             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     430           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     431             :     return 0;
     432           0 :   if ((Subtarget->hasNEON())) {
     433           0 :     return fastEmitInst_r(ARM::VCGTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     434             :   }
     435             :   return 0;
     436             : }
     437             : 
     438             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     439           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     440             :     return 0;
     441           0 :   if ((Subtarget->hasNEON())) {
     442           0 :     return fastEmitInst_r(ARM::VCGTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     443             :   }
     444             :   return 0;
     445             : }
     446             : 
     447             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     448           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     449             :     return 0;
     450           0 :   if ((Subtarget->hasNEON())) {
     451           0 :     return fastEmitInst_r(ARM::VCGTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     452             :   }
     453             :   return 0;
     454             : }
     455             : 
     456             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     457           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     458             :     return 0;
     459           0 :   if ((Subtarget->hasNEON())) {
     460           0 :     return fastEmitInst_r(ARM::VCGTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     461             :   }
     462             :   return 0;
     463             : }
     464             : 
     465             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     466           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     467             :     return 0;
     468           0 :   if ((Subtarget->hasNEON())) {
     469           0 :     return fastEmitInst_r(ARM::VCGTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     470             :   }
     471             :   return 0;
     472             : }
     473             : 
     474             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     475           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     476             :     return 0;
     477           0 :   if ((Subtarget->hasNEON())) {
     478           0 :     return fastEmitInst_r(ARM::VCGTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     479             :   }
     480             :   return 0;
     481             : }
     482             : 
     483           0 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     484           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     485             :     return 0;
     486           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     487           0 :     return fastEmitInst_r(ARM::VCGTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     488             :   }
     489             :   return 0;
     490             : }
     491             : 
     492           0 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     493           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     494             :     return 0;
     495           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     496           0 :     return fastEmitInst_r(ARM::VCGTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     497             :   }
     498             :   return 0;
     499             : }
     500             : 
     501             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     502           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     503             :     return 0;
     504           0 :   if ((Subtarget->hasNEON())) {
     505           0 :     return fastEmitInst_r(ARM::VCGTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     506             :   }
     507             :   return 0;
     508             : }
     509             : 
     510             : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     511           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     512             :     return 0;
     513           0 :   if ((Subtarget->hasNEON())) {
     514           0 :     return fastEmitInst_r(ARM::VCGTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     515             :   }
     516             :   return 0;
     517             : }
     518             : 
     519           0 : unsigned fastEmit_ARMISD_VCGTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     520           0 :   switch (VT.SimpleTy) {
     521           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     522           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     523           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     524           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     525           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     526           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     527           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     528           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     529           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     530           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     531             :   default: return 0;
     532             :   }
     533             : }
     534             : 
     535             : // FastEmit functions for ARMISD::VCLEZ.
     536             : 
     537             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     538           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     539             :     return 0;
     540           0 :   if ((Subtarget->hasNEON())) {
     541           0 :     return fastEmitInst_r(ARM::VCLEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     542             :   }
     543             :   return 0;
     544             : }
     545             : 
     546             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     547           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     548             :     return 0;
     549           0 :   if ((Subtarget->hasNEON())) {
     550           0 :     return fastEmitInst_r(ARM::VCLEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     551             :   }
     552             :   return 0;
     553             : }
     554             : 
     555             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     556           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     557             :     return 0;
     558           0 :   if ((Subtarget->hasNEON())) {
     559           0 :     return fastEmitInst_r(ARM::VCLEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     560             :   }
     561             :   return 0;
     562             : }
     563             : 
     564             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     565           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     566             :     return 0;
     567           0 :   if ((Subtarget->hasNEON())) {
     568           0 :     return fastEmitInst_r(ARM::VCLEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     569             :   }
     570             :   return 0;
     571             : }
     572             : 
     573             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     574           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     575             :     return 0;
     576           0 :   if ((Subtarget->hasNEON())) {
     577           0 :     return fastEmitInst_r(ARM::VCLEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     578             :   }
     579             :   return 0;
     580             : }
     581             : 
     582             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     583           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     584             :     return 0;
     585           0 :   if ((Subtarget->hasNEON())) {
     586           0 :     return fastEmitInst_r(ARM::VCLEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     587             :   }
     588             :   return 0;
     589             : }
     590             : 
     591           0 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     592           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     593             :     return 0;
     594           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     595           0 :     return fastEmitInst_r(ARM::VCLEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     596             :   }
     597             :   return 0;
     598             : }
     599             : 
     600           0 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     601           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     602             :     return 0;
     603           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     604           0 :     return fastEmitInst_r(ARM::VCLEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     605             :   }
     606             :   return 0;
     607             : }
     608             : 
     609             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     610           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     611             :     return 0;
     612           0 :   if ((Subtarget->hasNEON())) {
     613           0 :     return fastEmitInst_r(ARM::VCLEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     614             :   }
     615             :   return 0;
     616             : }
     617             : 
     618             : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     619           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     620             :     return 0;
     621           0 :   if ((Subtarget->hasNEON())) {
     622           0 :     return fastEmitInst_r(ARM::VCLEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     623             :   }
     624             :   return 0;
     625             : }
     626             : 
     627           0 : unsigned fastEmit_ARMISD_VCLEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     628           0 :   switch (VT.SimpleTy) {
     629           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     630           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     631           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     632           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     633           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     634           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     635           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     636           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     637           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     638           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     639             :   default: return 0;
     640             :   }
     641             : }
     642             : 
     643             : // FastEmit functions for ARMISD::VCLTZ.
     644             : 
     645             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     646           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     647             :     return 0;
     648           0 :   if ((Subtarget->hasNEON())) {
     649           0 :     return fastEmitInst_r(ARM::VCLTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
     650             :   }
     651             :   return 0;
     652             : }
     653             : 
     654             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     655           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     656             :     return 0;
     657           0 :   if ((Subtarget->hasNEON())) {
     658           0 :     return fastEmitInst_r(ARM::VCLTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
     659             :   }
     660             :   return 0;
     661             : }
     662             : 
     663             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     664           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     665             :     return 0;
     666           0 :   if ((Subtarget->hasNEON())) {
     667           0 :     return fastEmitInst_r(ARM::VCLTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
     668             :   }
     669             :   return 0;
     670             : }
     671             : 
     672             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     673           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     674             :     return 0;
     675           0 :   if ((Subtarget->hasNEON())) {
     676           0 :     return fastEmitInst_r(ARM::VCLTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
     677             :   }
     678             :   return 0;
     679             : }
     680             : 
     681             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     682           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     683             :     return 0;
     684           0 :   if ((Subtarget->hasNEON())) {
     685           0 :     return fastEmitInst_r(ARM::VCLTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
     686             :   }
     687             :   return 0;
     688             : }
     689             : 
     690             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     691           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     692             :     return 0;
     693           0 :   if ((Subtarget->hasNEON())) {
     694           0 :     return fastEmitInst_r(ARM::VCLTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
     695             :   }
     696             :   return 0;
     697             : }
     698             : 
     699           0 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     700           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     701             :     return 0;
     702           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     703           0 :     return fastEmitInst_r(ARM::VCLTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
     704             :   }
     705             :   return 0;
     706             : }
     707             : 
     708           0 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     709           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     710             :     return 0;
     711           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
     712           0 :     return fastEmitInst_r(ARM::VCLTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
     713             :   }
     714             :   return 0;
     715             : }
     716             : 
     717             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     718           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     719             :     return 0;
     720           0 :   if ((Subtarget->hasNEON())) {
     721           0 :     return fastEmitInst_r(ARM::VCLTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
     722             :   }
     723             :   return 0;
     724             : }
     725             : 
     726             : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     727           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     728             :     return 0;
     729           0 :   if ((Subtarget->hasNEON())) {
     730           0 :     return fastEmitInst_r(ARM::VCLTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
     731             :   }
     732             :   return 0;
     733             : }
     734             : 
     735           0 : unsigned fastEmit_ARMISD_VCLTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     736           0 :   switch (VT.SimpleTy) {
     737           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     738           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     739           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     740           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     741           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
     742           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     743           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
     744           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
     745           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
     746           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     747             :   default: return 0;
     748             :   }
     749             : }
     750             : 
     751             : // FastEmit functions for ARMISD::VDUP.
     752             : 
     753             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
     754           0 :   if ((Subtarget->hasNEON())) {
     755           0 :     return fastEmitInst_r(ARM::VDUP8d, &ARM::DPRRegClass, Op0, Op0IsKill);
     756             :   }
     757             :   return 0;
     758             : }
     759             : 
     760             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
     761           0 :   if ((Subtarget->hasNEON())) {
     762           0 :     return fastEmitInst_r(ARM::VDUP8q, &ARM::QPRRegClass, Op0, Op0IsKill);
     763             :   }
     764             :   return 0;
     765             : }
     766             : 
     767             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
     768           0 :   if ((Subtarget->hasNEON())) {
     769           0 :     return fastEmitInst_r(ARM::VDUP16d, &ARM::DPRRegClass, Op0, Op0IsKill);
     770             :   }
     771             :   return 0;
     772             : }
     773             : 
     774             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
     775           0 :   if ((Subtarget->hasNEON())) {
     776           0 :     return fastEmitInst_r(ARM::VDUP16q, &ARM::QPRRegClass, Op0, Op0IsKill);
     777             :   }
     778             :   return 0;
     779             : }
     780             : 
     781           0 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
     782           0 :   if ((!Subtarget->hasSlowVDUP32()) && (Subtarget->hasNEON())) {
     783           0 :     return fastEmitInst_r(ARM::VDUP32d, &ARM::DPRRegClass, Op0, Op0IsKill);
     784             :   }
     785             :   return 0;
     786             : }
     787             : 
     788             : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
     789           0 :   if ((Subtarget->hasNEON())) {
     790           0 :     return fastEmitInst_r(ARM::VDUP32q, &ARM::QPRRegClass, Op0, Op0IsKill);
     791             :   }
     792             :   return 0;
     793             : }
     794             : 
     795           0 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     796           0 : switch (RetVT.SimpleTy) {
     797           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill);
     798           0 :   case MVT::v16i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill);
     799           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill);
     800           0 :   case MVT::v8i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill);
     801           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill);
     802           0 :   case MVT::v4i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill);
     803             :   default: return 0;
     804             : }
     805             : }
     806             : 
     807             : unsigned fastEmit_ARMISD_VDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     808           0 :   switch (VT.SimpleTy) {
     809           0 :   case MVT::i32: return fastEmit_ARMISD_VDUP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     810             :   default: return 0;
     811             :   }
     812             : }
     813             : 
     814             : // FastEmit functions for ARMISD::VMOVSR.
     815             : 
     816           0 : unsigned fastEmit_ARMISD_VMOVSR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     817           0 :   if (RetVT.SimpleTy != MVT::f32)
     818             :     return 0;
     819           0 :   if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
     820           0 :     return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
     821             :   }
     822             :   return 0;
     823             : }
     824             : 
     825             : unsigned fastEmit_ARMISD_VMOVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     826           0 :   switch (VT.SimpleTy) {
     827           0 :   case MVT::i32: return fastEmit_ARMISD_VMOVSR_MVT_i32_r(RetVT, Op0, Op0IsKill);
     828             :   default: return 0;
     829             :   }
     830             : }
     831             : 
     832             : // FastEmit functions for ARMISD::VMOVhr.
     833             : 
     834             : unsigned fastEmit_ARMISD_VMOVhr_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     835           0 :   if (RetVT.SimpleTy != MVT::f16)
     836             :     return 0;
     837           0 :   if ((Subtarget->hasFullFP16())) {
     838           0 :     return fastEmitInst_r(ARM::VMOVHR, &ARM::HPRRegClass, Op0, Op0IsKill);
     839             :   }
     840             :   return 0;
     841             : }
     842             : 
     843           0 : unsigned fastEmit_ARMISD_VMOVhr_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     844           0 :   switch (VT.SimpleTy) {
     845           0 :   case MVT::i32: return fastEmit_ARMISD_VMOVhr_MVT_i32_r(RetVT, Op0, Op0IsKill);
     846             :   default: return 0;
     847             :   }
     848             : }
     849             : 
     850             : // FastEmit functions for ARMISD::VMOVrh.
     851             : 
     852             : unsigned fastEmit_ARMISD_VMOVrh_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     853           0 :   if (RetVT.SimpleTy != MVT::i32)
     854             :     return 0;
     855           0 :   if ((Subtarget->hasFullFP16())) {
     856           0 :     return fastEmitInst_r(ARM::VMOVRH, &ARM::GPRRegClass, Op0, Op0IsKill);
     857             :   }
     858             :   return 0;
     859             : }
     860             : 
     861           0 : unsigned fastEmit_ARMISD_VMOVrh_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     862           0 :   switch (VT.SimpleTy) {
     863           0 :   case MVT::f16: return fastEmit_ARMISD_VMOVrh_MVT_f16_r(RetVT, Op0, Op0IsKill);
     864             :   default: return 0;
     865             :   }
     866             : }
     867             : 
     868             : // FastEmit functions for ARMISD::VREV16.
     869             : 
     870             : unsigned fastEmit_ARMISD_VREV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     871           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     872             :     return 0;
     873           0 :   if ((Subtarget->hasNEON())) {
     874           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     875             :   }
     876             :   return 0;
     877             : }
     878             : 
     879             : unsigned fastEmit_ARMISD_VREV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     880           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     881             :     return 0;
     882           0 :   if ((Subtarget->hasNEON())) {
     883           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     884             :   }
     885             :   return 0;
     886             : }
     887             : 
     888           0 : unsigned fastEmit_ARMISD_VREV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     889           0 :   switch (VT.SimpleTy) {
     890           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     891           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     892             :   default: return 0;
     893             :   }
     894             : }
     895             : 
     896             : // FastEmit functions for ARMISD::VREV32.
     897             : 
     898             : unsigned fastEmit_ARMISD_VREV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     899           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     900             :     return 0;
     901           0 :   if ((Subtarget->hasNEON())) {
     902           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     903             :   }
     904             :   return 0;
     905             : }
     906             : 
     907             : unsigned fastEmit_ARMISD_VREV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     908           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     909             :     return 0;
     910           0 :   if ((Subtarget->hasNEON())) {
     911           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     912             :   }
     913             :   return 0;
     914             : }
     915             : 
     916             : unsigned fastEmit_ARMISD_VREV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     917           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     918             :     return 0;
     919           0 :   if ((Subtarget->hasNEON())) {
     920           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
     921             :   }
     922             :   return 0;
     923             : }
     924             : 
     925             : unsigned fastEmit_ARMISD_VREV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     926           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     927             :     return 0;
     928           0 :   if ((Subtarget->hasNEON())) {
     929           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
     930             :   }
     931             :   return 0;
     932             : }
     933             : 
     934           0 : unsigned fastEmit_ARMISD_VREV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     935           0 :   switch (VT.SimpleTy) {
     936           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
     937           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     938           0 :   case MVT::v4i16: return fastEmit_ARMISD_VREV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
     939           0 :   case MVT::v8i16: return fastEmit_ARMISD_VREV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     940             :   default: return 0;
     941             :   }
     942             : }
     943             : 
     944             : // FastEmit functions for ARMISD::VREV64.
     945             : 
     946             : unsigned fastEmit_ARMISD_VREV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     947           0 :   if (RetVT.SimpleTy != MVT::v8i8)
     948             :     return 0;
     949           0 :   if ((Subtarget->hasNEON())) {
     950           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
     951             :   }
     952             :   return 0;
     953             : }
     954             : 
     955             : unsigned fastEmit_ARMISD_VREV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     956           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     957             :     return 0;
     958           0 :   if ((Subtarget->hasNEON())) {
     959           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
     960             :   }
     961             :   return 0;
     962             : }
     963             : 
     964             : unsigned fastEmit_ARMISD_VREV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     965           0 :   if (RetVT.SimpleTy != MVT::v4i16)
     966             :     return 0;
     967           0 :   if ((Subtarget->hasNEON())) {
     968           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
     969             :   }
     970             :   return 0;
     971             : }
     972             : 
     973             : unsigned fastEmit_ARMISD_VREV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     974           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     975             :     return 0;
     976           0 :   if ((Subtarget->hasNEON())) {
     977           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
     978             :   }
     979             :   return 0;
     980             : }
     981             : 
     982             : unsigned fastEmit_ARMISD_VREV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     983           0 :   if (RetVT.SimpleTy != MVT::v2i32)
     984             :     return 0;
     985           0 :   if ((Subtarget->hasNEON())) {
     986           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
     987             :   }
     988             :   return 0;
     989             : }
     990             : 
     991             : unsigned fastEmit_ARMISD_VREV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     992           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     993             :     return 0;
     994           0 :   if ((Subtarget->hasNEON())) {
     995           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
     996             :   }
     997             :   return 0;
     998             : }
     999             : 
    1000             : unsigned fastEmit_ARMISD_VREV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1001           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    1002             :     return 0;
    1003           0 :   return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1004             : }
    1005             : 
    1006             : unsigned fastEmit_ARMISD_VREV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1007           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1008             :     return 0;
    1009           0 :   return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1010             : }
    1011             : 
    1012           0 : unsigned fastEmit_ARMISD_VREV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1013           0 :   switch (VT.SimpleTy) {
    1014           0 :   case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1015           0 :   case MVT::v16i8: return fastEmit_ARMISD_VREV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1016           0 :   case MVT::v4i16: return fastEmit_ARMISD_VREV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1017           0 :   case MVT::v8i16: return fastEmit_ARMISD_VREV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1018           0 :   case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1019           0 :   case MVT::v4i32: return fastEmit_ARMISD_VREV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1020           0 :   case MVT::v2f32: return fastEmit_ARMISD_VREV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    1021           0 :   case MVT::v4f32: return fastEmit_ARMISD_VREV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1022             :   default: return 0;
    1023             :   }
    1024             : }
    1025             : 
    1026             : // FastEmit functions for ARMISD::WIN__DBZCHK.
    1027             : 
    1028             : unsigned fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1029           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1030             :     return 0;
    1031           0 :   return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill);
    1032             : }
    1033             : 
    1034             : unsigned fastEmit_ARMISD_WIN__DBZCHK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1035           0 :   switch (VT.SimpleTy) {
    1036           0 :   case MVT::i32: return fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1037             :   default: return 0;
    1038             :   }
    1039             : }
    1040             : 
    1041             : // FastEmit functions for ISD::ABS.
    1042             : 
    1043             : unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1044           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    1045             :     return 0;
    1046           0 :   if ((Subtarget->hasNEON())) {
    1047           0 :     return fastEmitInst_r(ARM::VABSv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1048             :   }
    1049             :   return 0;
    1050             : }
    1051             : 
    1052             : unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1053           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1054             :     return 0;
    1055           0 :   if ((Subtarget->hasNEON())) {
    1056           0 :     return fastEmitInst_r(ARM::VABSv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1057             :   }
    1058             :   return 0;
    1059             : }
    1060             : 
    1061             : unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1062           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    1063             :     return 0;
    1064           0 :   if ((Subtarget->hasNEON())) {
    1065           0 :     return fastEmitInst_r(ARM::VABSv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1066             :   }
    1067             :   return 0;
    1068             : }
    1069             : 
    1070             : unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1071           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1072             :     return 0;
    1073           0 :   if ((Subtarget->hasNEON())) {
    1074           0 :     return fastEmitInst_r(ARM::VABSv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1075             :   }
    1076             :   return 0;
    1077             : }
    1078             : 
    1079             : unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1080           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    1081             :     return 0;
    1082           0 :   if ((Subtarget->hasNEON())) {
    1083           0 :     return fastEmitInst_r(ARM::VABSv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1084             :   }
    1085             :   return 0;
    1086             : }
    1087             : 
    1088             : unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1089           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1090             :     return 0;
    1091           0 :   if ((Subtarget->hasNEON())) {
    1092           0 :     return fastEmitInst_r(ARM::VABSv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1093             :   }
    1094             :   return 0;
    1095             : }
    1096             : 
    1097           0 : unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1098           0 :   switch (VT.SimpleTy) {
    1099           0 :   case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1100           0 :   case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1101           0 :   case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1102           0 :   case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1103           0 :   case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1104           0 :   case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1105             :   default: return 0;
    1106             :   }
    1107             : }
    1108             : 
    1109             : // FastEmit functions for ISD::ANY_EXTEND.
    1110             : 
    1111             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1112           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1113             :     return 0;
    1114           0 :   return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1115             : }
    1116             : 
    1117             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1118           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1119             :     return 0;
    1120           0 :   return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1121             : }
    1122             : 
    1123             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1124           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1125             :     return 0;
    1126           0 :   return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    1127             : }
    1128             : 
    1129           0 : unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1130           0 :   switch (VT.SimpleTy) {
    1131           0 :   case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1132           0 :   case MVT::v4i16: return fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1133           0 :   case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1134             :   default: return 0;
    1135             :   }
    1136             : }
    1137             : 
    1138             : // FastEmit functions for ISD::BITCAST.
    1139             : 
    1140           0 : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1141           0 :   if (RetVT.SimpleTy != MVT::f32)
    1142             :     return 0;
    1143           0 :   if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
    1144           0 :     return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
    1145             :   }
    1146             :   return 0;
    1147             : }
    1148             : 
    1149             : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1150          81 :   if (RetVT.SimpleTy != MVT::i32)
    1151             :     return 0;
    1152          81 :   if ((Subtarget->hasVFP2())) {
    1153          81 :     return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill);
    1154             :   }
    1155             :   return 0;
    1156             : }
    1157             : 
    1158           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1159           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1160           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1161             :   }
    1162             :   return 0;
    1163             : }
    1164             : 
    1165           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1166           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1167           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1168             :   }
    1169             :   return 0;
    1170             : }
    1171             : 
    1172           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1173           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1174           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1175             :   }
    1176             :   return 0;
    1177             : }
    1178             : 
    1179           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1180           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1181           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1182             :   }
    1183             :   return 0;
    1184             : }
    1185             : 
    1186           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1187           0 : switch (RetVT.SimpleTy) {
    1188           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill);
    1189           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill);
    1190           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill);
    1191           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill);
    1192             :   default: return 0;
    1193             : }
    1194             : }
    1195             : 
    1196           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1197           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1198           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1199             :   }
    1200             :   return 0;
    1201             : }
    1202             : 
    1203           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1204           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1205           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1206             :   }
    1207             :   return 0;
    1208             : }
    1209             : 
    1210           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1211           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1212           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1213             :   }
    1214             :   return 0;
    1215             : }
    1216             : 
    1217           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1218           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1219           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1220             :   }
    1221             :   return 0;
    1222             : }
    1223             : 
    1224           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1225           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1226           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1227             :   }
    1228             :   return 0;
    1229             : }
    1230             : 
    1231           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1232           0 : switch (RetVT.SimpleTy) {
    1233           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill);
    1234           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill);
    1235           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill);
    1236           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill);
    1237           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill);
    1238             :   default: return 0;
    1239             : }
    1240             : }
    1241             : 
    1242           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1243           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1244           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1245             :   }
    1246             :   return 0;
    1247             : }
    1248             : 
    1249           2 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1250           2 :   if ((MF->getDataLayout().isBigEndian())) {
    1251           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1252             :   }
    1253             :   return 0;
    1254             : }
    1255             : 
    1256           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1257           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1258           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1259             :   }
    1260             :   return 0;
    1261             : }
    1262             : 
    1263           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1264           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1265           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1266             :   }
    1267             :   return 0;
    1268             : }
    1269             : 
    1270           0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1271           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1272           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1273             :   }
    1274             :   return 0;
    1275             : }
    1276             : 
    1277           2 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1278           2 : switch (RetVT.SimpleTy) {
    1279           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill);
    1280           2 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
    1281           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
    1282           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill);
    1283           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill);
    1284             :   default: return 0;
    1285             : }
    1286             : }
    1287             : 
    1288           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1289           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1290           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1291             :   }
    1292             :   return 0;
    1293             : }
    1294             : 
    1295           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1296           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1297           0 :     return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1298             :   }
    1299             :   return 0;
    1300             : }
    1301             : 
    1302           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1303           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1304           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1305             :   }
    1306             :   return 0;
    1307             : }
    1308             : 
    1309           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1310           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1311           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1312             :   }
    1313             :   return 0;
    1314             : }
    1315             : 
    1316           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1317           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1318           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1319             :   }
    1320             :   return 0;
    1321             : }
    1322             : 
    1323           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1324           0 : switch (RetVT.SimpleTy) {
    1325           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill);
    1326           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill);
    1327           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill);
    1328           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill);
    1329           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill);
    1330             :   default: return 0;
    1331             : }
    1332             : }
    1333             : 
    1334           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1335           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1336           0 :     return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1337             :   }
    1338             :   return 0;
    1339             : }
    1340             : 
    1341           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1342           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1343           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1344             :   }
    1345             :   return 0;
    1346             : }
    1347             : 
    1348           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1349           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1350           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1351             :   }
    1352             :   return 0;
    1353             : }
    1354             : 
    1355           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1356           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1357           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1358             :   }
    1359             :   return 0;
    1360             : }
    1361             : 
    1362           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1363           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1364           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1365             :   }
    1366             :   return 0;
    1367             : }
    1368             : 
    1369           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1370           0 : switch (RetVT.SimpleTy) {
    1371           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill);
    1372           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
    1373           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
    1374           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill);
    1375           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill);
    1376             :   default: return 0;
    1377             : }
    1378             : }
    1379             : 
    1380           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1381           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1382           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1383             :   }
    1384             :   return 0;
    1385             : }
    1386             : 
    1387           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1388           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1389           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1390             :   }
    1391             :   return 0;
    1392             : }
    1393             : 
    1394           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1395           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1396           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1397             :   }
    1398             :   return 0;
    1399             : }
    1400             : 
    1401           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1402           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1403           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1404             :   }
    1405             :   return 0;
    1406             : }
    1407             : 
    1408           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1409           0 : switch (RetVT.SimpleTy) {
    1410           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill);
    1411           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill);
    1412           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill);
    1413           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill);
    1414             :   default: return 0;
    1415             : }
    1416             : }
    1417             : 
    1418           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1419           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1420           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1421             :   }
    1422             :   return 0;
    1423             : }
    1424             : 
    1425           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1426           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1427           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1428             :   }
    1429             :   return 0;
    1430             : }
    1431             : 
    1432           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1433           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1434           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1435             :   }
    1436             :   return 0;
    1437             : }
    1438             : 
    1439           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1440           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1441           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1442             :   }
    1443             :   return 0;
    1444             : }
    1445             : 
    1446           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1447           0 : switch (RetVT.SimpleTy) {
    1448           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill);
    1449           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill);
    1450           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill);
    1451           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill);
    1452             :   default: return 0;
    1453             : }
    1454             : }
    1455             : 
    1456           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1457           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1458           0 :     return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1459             :   }
    1460             :   return 0;
    1461             : }
    1462             : 
    1463           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1464           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1465           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1466             :   }
    1467             :   return 0;
    1468             : }
    1469             : 
    1470           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
    1471           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1472           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1473             :   }
    1474             :   return 0;
    1475             : }
    1476             : 
    1477           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
    1478           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1479           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1480             :   }
    1481             :   return 0;
    1482             : }
    1483             : 
    1484           0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1485           0 : switch (RetVT.SimpleTy) {
    1486           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill);
    1487           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill);
    1488           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill);
    1489           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill);
    1490             :   default: return 0;
    1491             : }
    1492             : }
    1493             : 
    1494           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1495           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1496           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1497             :   }
    1498             :   return 0;
    1499             : }
    1500             : 
    1501           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1502           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1503           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1504             :   }
    1505             :   return 0;
    1506             : }
    1507             : 
    1508           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1509           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1510           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1511             :   }
    1512             :   return 0;
    1513             : }
    1514             : 
    1515           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1516           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1517           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1518             :   }
    1519             :   return 0;
    1520             : }
    1521             : 
    1522           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1523           0 : switch (RetVT.SimpleTy) {
    1524           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill);
    1525           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill);
    1526           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill);
    1527           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill);
    1528             :   default: return 0;
    1529             : }
    1530             : }
    1531             : 
    1532           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1533           0 :   if (RetVT.SimpleTy != MVT::f64)
    1534             :     return 0;
    1535           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1536           0 :     return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1537             :   }
    1538             :   return 0;
    1539             : }
    1540             : 
    1541           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1542           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1543           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1544             :   }
    1545             :   return 0;
    1546             : }
    1547             : 
    1548           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1549           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1550           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1551             :   }
    1552             :   return 0;
    1553             : }
    1554             : 
    1555           0 : unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1556           0 : switch (RetVT.SimpleTy) {
    1557           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0, Op0IsKill);
    1558           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0, Op0IsKill);
    1559             :   default: return 0;
    1560             : }
    1561             : }
    1562             : 
    1563           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1564           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1565           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1566             :   }
    1567             :   return 0;
    1568             : }
    1569             : 
    1570           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
    1571           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1572           0 :     return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1573             :   }
    1574             :   return 0;
    1575             : }
    1576             : 
    1577           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
    1578           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1579           0 :     return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1580             :   }
    1581             :   return 0;
    1582             : }
    1583             : 
    1584           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
    1585           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1586           0 :     return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1587             :   }
    1588             :   return 0;
    1589             : }
    1590             : 
    1591           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1592           0 : switch (RetVT.SimpleTy) {
    1593           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill);
    1594           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill);
    1595           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill);
    1596           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill);
    1597             :   default: return 0;
    1598             : }
    1599             : }
    1600             : 
    1601           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1602           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1603           0 :     return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1604             :   }
    1605             :   return 0;
    1606             : }
    1607             : 
    1608           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1609           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1610           0 :     return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1611             :   }
    1612             :   return 0;
    1613             : }
    1614             : 
    1615           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1616           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1617           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1618             :   }
    1619             :   return 0;
    1620             : }
    1621             : 
    1622           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
    1623           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1624           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1625             :   }
    1626             :   return 0;
    1627             : }
    1628             : 
    1629           0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1630           0 : switch (RetVT.SimpleTy) {
    1631           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill);
    1632           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill);
    1633           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill);
    1634           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill);
    1635             :   default: return 0;
    1636             : }
    1637             : }
    1638             : 
    1639           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
    1640           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1641           0 :     return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1642             :   }
    1643             :   return 0;
    1644             : }
    1645             : 
    1646           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
    1647           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1648           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1649             :   }
    1650             :   return 0;
    1651             : }
    1652             : 
    1653           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1654           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1655           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1656             :   }
    1657             :   return 0;
    1658             : }
    1659             : 
    1660           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) {
    1661           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1662           0 :     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1663             :   }
    1664             :   return 0;
    1665             : }
    1666             : 
    1667           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
    1668           0 :   if ((MF->getDataLayout().isBigEndian())) {
    1669           0 :     return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1670             :   }
    1671             :   return 0;
    1672             : }
    1673             : 
    1674           0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1675           0 : switch (RetVT.SimpleTy) {
    1676           0 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill);
    1677           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill);
    1678           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill);
    1679           0 :   case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill);
    1680           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill);
    1681             :   default: return 0;
    1682             : }
    1683             : }
    1684             : 
    1685          83 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1686          83 :   switch (VT.SimpleTy) {
    1687           0 :   case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1688          81 :   case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1689           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1690           0 :   case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1691           2 :   case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1692           0 :   case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1693           0 :   case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1694           0 :   case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1695           0 :   case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1696           0 :   case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
    1697           0 :   case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1698           0 :   case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    1699           0 :   case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    1700           0 :   case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    1701           0 :   case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1702           0 :   case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1703             :   default: return 0;
    1704             :   }
    1705             : }
    1706             : 
    1707             : // FastEmit functions for ISD::BITREVERSE.
    1708             : 
    1709           0 : unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1710           0 :   if (RetVT.SimpleTy != MVT::i32)
    1711             :     return 0;
    1712           0 :   if ((Subtarget->isThumb2())) {
    1713           0 :     return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1714             :   }
    1715           0 :   if ((Subtarget->hasV6T2Ops()) && (!Subtarget->isThumb())) {
    1716           0 :     return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill);
    1717             :   }
    1718             :   return 0;
    1719             : }
    1720             : 
    1721             : unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1722           0 :   switch (VT.SimpleTy) {
    1723           0 :   case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1724             :   default: return 0;
    1725             :   }
    1726             : }
    1727             : 
    1728             : // FastEmit functions for ISD::BRIND.
    1729             : 
    1730           0 : unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1731           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1732             :     return 0;
    1733           0 :   if ((Subtarget->isThumb())) {
    1734           0 :     return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill);
    1735             :   }
    1736           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
    1737           0 :     return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill);
    1738             :   }
    1739           0 :   if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
    1740           0 :     return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill);
    1741             :   }
    1742             :   return 0;
    1743             : }
    1744             : 
    1745             : unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1746           0 :   switch (VT.SimpleTy) {
    1747           0 :   case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1748             :   default: return 0;
    1749             :   }
    1750             : }
    1751             : 
    1752             : // FastEmit functions for ISD::BSWAP.
    1753             : 
    1754           0 : unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1755           0 :   if (RetVT.SimpleTy != MVT::i32)
    1756             :     return 0;
    1757           0 :   if ((Subtarget->isThumb2())) {
    1758           0 :     return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1759             :   }
    1760           0 :   if ((Subtarget->hasV6Ops()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    1761           0 :     return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill);
    1762             :   }
    1763           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    1764           0 :     return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill);
    1765             :   }
    1766             :   return 0;
    1767             : }
    1768             : 
    1769             : unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1770           0 :   switch (VT.SimpleTy) {
    1771           0 :   case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1772             :   default: return 0;
    1773             :   }
    1774             : }
    1775             : 
    1776             : // FastEmit functions for ISD::CTLZ.
    1777             : 
    1778           0 : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1779           0 :   if (RetVT.SimpleTy != MVT::i32)
    1780             :     return 0;
    1781           0 :   if ((Subtarget->isThumb2())) {
    1782           0 :     return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill);
    1783             :   }
    1784           0 :   if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
    1785           0 :     return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill);
    1786             :   }
    1787             :   return 0;
    1788             : }
    1789             : 
    1790             : unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1791           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    1792             :     return 0;
    1793           0 :   if ((Subtarget->hasNEON())) {
    1794           0 :     return fastEmitInst_r(ARM::VCLZv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
    1795             :   }
    1796             :   return 0;
    1797             : }
    1798             : 
    1799             : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1800           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1801             :     return 0;
    1802           0 :   if ((Subtarget->hasNEON())) {
    1803           0 :     return fastEmitInst_r(ARM::VCLZv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
    1804             :   }
    1805             :   return 0;
    1806             : }
    1807             : 
    1808             : unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1809           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    1810             :     return 0;
    1811           0 :   if ((Subtarget->hasNEON())) {
    1812           0 :     return fastEmitInst_r(ARM::VCLZv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    1813             :   }
    1814             :   return 0;
    1815             : }
    1816             : 
    1817             : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1818           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1819             :     return 0;
    1820           0 :   if ((Subtarget->hasNEON())) {
    1821           0 :     return fastEmitInst_r(ARM::VCLZv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    1822             :   }
    1823             :   return 0;
    1824             : }
    1825             : 
    1826             : unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1827           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    1828             :     return 0;
    1829           0 :   if ((Subtarget->hasNEON())) {
    1830           0 :     return fastEmitInst_r(ARM::VCLZv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    1831             :   }
    1832             :   return 0;
    1833             : }
    1834             : 
    1835             : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1836           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1837             :     return 0;
    1838           0 :   if ((Subtarget->hasNEON())) {
    1839           0 :     return fastEmitInst_r(ARM::VCLZv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    1840             :   }
    1841             :   return 0;
    1842             : }
    1843             : 
    1844           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1845           0 :   switch (VT.SimpleTy) {
    1846           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1847           0 :   case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1848           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1849           0 :   case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    1850           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1851           0 :   case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    1852           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1853             :   default: return 0;
    1854             :   }
    1855             : }
    1856             : 
    1857             : // FastEmit functions for ISD::CTPOP.
    1858             : 
    1859             : unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1860           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    1861             :     return 0;
    1862           0 :   if ((Subtarget->hasNEON())) {
    1863           0 :     return fastEmitInst_r(ARM::VCNTd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1864             :   }
    1865             :   return 0;
    1866             : }
    1867             : 
    1868             : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1869           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1870             :     return 0;
    1871           0 :   if ((Subtarget->hasNEON())) {
    1872           0 :     return fastEmitInst_r(ARM::VCNTq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1873             :   }
    1874             :   return 0;
    1875             : }
    1876             : 
    1877           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1878           0 :   switch (VT.SimpleTy) {
    1879           0 :   case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    1880           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1881             :   default: return 0;
    1882             :   }
    1883             : }
    1884             : 
    1885             : // FastEmit functions for ISD::FABS.
    1886             : 
    1887           0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1888           0 :   if (RetVT.SimpleTy != MVT::f32)
    1889             :     return 0;
    1890           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    1891           0 :     return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1892             :   }
    1893             :   return 0;
    1894             : }
    1895             : 
    1896           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1897           0 :   if (RetVT.SimpleTy != MVT::f64)
    1898             :     return 0;
    1899           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    1900           0 :     return fastEmitInst_r(ARM::VABSD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1901             :   }
    1902             :   return 0;
    1903             : }
    1904             : 
    1905           0 : unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1906           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    1907             :     return 0;
    1908           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    1909           0 :     return fastEmitInst_r(ARM::VABShd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1910             :   }
    1911             :   return 0;
    1912             : }
    1913             : 
    1914           0 : unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1915           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    1916             :     return 0;
    1917           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    1918           0 :     return fastEmitInst_r(ARM::VABShq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1919             :   }
    1920             :   return 0;
    1921             : }
    1922             : 
    1923             : unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1924           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    1925             :     return 0;
    1926           0 :   if ((Subtarget->hasNEON())) {
    1927           0 :     return fastEmitInst_r(ARM::VABSfd, &ARM::DPRRegClass, Op0, Op0IsKill);
    1928             :   }
    1929             :   return 0;
    1930             : }
    1931             : 
    1932             : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1933           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1934             :     return 0;
    1935           0 :   if ((Subtarget->hasNEON())) {
    1936           0 :     return fastEmitInst_r(ARM::VABSfq, &ARM::QPRRegClass, Op0, Op0IsKill);
    1937             :   }
    1938             :   return 0;
    1939             : }
    1940             : 
    1941           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1942           0 :   switch (VT.SimpleTy) {
    1943           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1944           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1945           0 :   case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    1946           0 :   case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    1947           0 :   case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    1948           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1949             :   default: return 0;
    1950             :   }
    1951             : }
    1952             : 
    1953             : // FastEmit functions for ISD::FCEIL.
    1954             : 
    1955             : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1956           0 :   if (RetVT.SimpleTy != MVT::f32)
    1957             :     return 0;
    1958           0 :   if ((Subtarget->hasFPARMv8())) {
    1959           0 :     return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1960             :   }
    1961             :   return 0;
    1962             : }
    1963             : 
    1964           0 : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1965           0 :   if (RetVT.SimpleTy != MVT::f64)
    1966             :     return 0;
    1967           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    1968           0 :     return fastEmitInst_r(ARM::VRINTPD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1969             :   }
    1970             :   return 0;
    1971             : }
    1972             : 
    1973           0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1974           0 :   switch (VT.SimpleTy) {
    1975           0 :   case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1976           0 :   case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1977             :   default: return 0;
    1978             :   }
    1979             : }
    1980             : 
    1981             : // FastEmit functions for ISD::FFLOOR.
    1982             : 
    1983             : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1984           0 :   if (RetVT.SimpleTy != MVT::f32)
    1985             :     return 0;
    1986           0 :   if ((Subtarget->hasFPARMv8())) {
    1987           0 :     return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill);
    1988             :   }
    1989             :   return 0;
    1990             : }
    1991             : 
    1992           0 : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1993           0 :   if (RetVT.SimpleTy != MVT::f64)
    1994             :     return 0;
    1995           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    1996           0 :     return fastEmitInst_r(ARM::VRINTMD, &ARM::DPRRegClass, Op0, Op0IsKill);
    1997             :   }
    1998             :   return 0;
    1999             : }
    2000             : 
    2001           0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2002           0 :   switch (VT.SimpleTy) {
    2003           0 :   case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2004           0 :   case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2005             :   default: return 0;
    2006             :   }
    2007             : }
    2008             : 
    2009             : // FastEmit functions for ISD::FNEARBYINT.
    2010             : 
    2011             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2012           0 :   if (RetVT.SimpleTy != MVT::f32)
    2013             :     return 0;
    2014           0 :   if ((Subtarget->hasFPARMv8())) {
    2015           0 :     return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2016             :   }
    2017             :   return 0;
    2018             : }
    2019             : 
    2020           0 : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2021           0 :   if (RetVT.SimpleTy != MVT::f64)
    2022             :     return 0;
    2023           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2024           0 :     return fastEmitInst_r(ARM::VRINTRD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2025             :   }
    2026             :   return 0;
    2027             : }
    2028             : 
    2029           0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2030           0 :   switch (VT.SimpleTy) {
    2031           0 :   case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2032           0 :   case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2033             :   default: return 0;
    2034             :   }
    2035             : }
    2036             : 
    2037             : // FastEmit functions for ISD::FNEG.
    2038             : 
    2039             : unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2040           0 :   if (RetVT.SimpleTy != MVT::f16)
    2041             :     return 0;
    2042           0 :   if ((Subtarget->hasFullFP16())) {
    2043           0 :     return fastEmitInst_r(ARM::VNEGH, &ARM::HPRRegClass, Op0, Op0IsKill);
    2044             :   }
    2045             :   return 0;
    2046             : }
    2047             : 
    2048           0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2049           0 :   if (RetVT.SimpleTy != MVT::f32)
    2050             :     return 0;
    2051           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    2052           0 :     return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2053             :   }
    2054             :   return 0;
    2055             : }
    2056             : 
    2057           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2058           0 :   if (RetVT.SimpleTy != MVT::f64)
    2059             :     return 0;
    2060           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2061           0 :     return fastEmitInst_r(ARM::VNEGD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2062             :   }
    2063             :   return 0;
    2064             : }
    2065             : 
    2066           0 : unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2067           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    2068             :     return 0;
    2069           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2070           0 :     return fastEmitInst_r(ARM::VNEGhd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2071             :   }
    2072             :   return 0;
    2073             : }
    2074             : 
    2075           0 : unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2076           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    2077             :     return 0;
    2078           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2079           0 :     return fastEmitInst_r(ARM::VNEGhq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2080             :   }
    2081             :   return 0;
    2082             : }
    2083             : 
    2084             : unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2085           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    2086             :     return 0;
    2087           0 :   if ((Subtarget->hasNEON())) {
    2088           0 :     return fastEmitInst_r(ARM::VNEGfd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2089             :   }
    2090             :   return 0;
    2091             : }
    2092             : 
    2093             : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2094           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2095             :     return 0;
    2096           0 :   if ((Subtarget->hasNEON())) {
    2097           0 :     return fastEmitInst_r(ARM::VNEGf32q, &ARM::QPRRegClass, Op0, Op0IsKill);
    2098             :   }
    2099             :   return 0;
    2100             : }
    2101             : 
    2102           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2103           0 :   switch (VT.SimpleTy) {
    2104           0 :   case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill);
    2105           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2106           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2107           0 :   case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2108           0 :   case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2109           0 :   case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2110           0 :   case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2111             :   default: return 0;
    2112             :   }
    2113             : }
    2114             : 
    2115             : // FastEmit functions for ISD::FP_EXTEND.
    2116             : 
    2117           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2118           0 :   if (RetVT.SimpleTy != MVT::f64)
    2119             :     return 0;
    2120           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2121           0 :     return fastEmitInst_r(ARM::VCVTDS, &ARM::DPRRegClass, Op0, Op0IsKill);
    2122             :   }
    2123             :   return 0;
    2124             : }
    2125             : 
    2126             : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2127           0 :   switch (VT.SimpleTy) {
    2128           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2129             :   default: return 0;
    2130             :   }
    2131             : }
    2132             : 
    2133             : // FastEmit functions for ISD::FP_ROUND.
    2134             : 
    2135           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2136           0 :   if (RetVT.SimpleTy != MVT::f32)
    2137             :     return 0;
    2138           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2139           0 :     return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill);
    2140             :   }
    2141             :   return 0;
    2142             : }
    2143             : 
    2144             : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2145           0 :   switch (VT.SimpleTy) {
    2146           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2147             :   default: return 0;
    2148             :   }
    2149             : }
    2150             : 
    2151             : // FastEmit functions for ISD::FP_TO_SINT.
    2152             : 
    2153           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2154           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2155             :     return 0;
    2156           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2157           0 :     return fastEmitInst_r(ARM::VCVTh2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2158             :   }
    2159             :   return 0;
    2160             : }
    2161             : 
    2162           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2163           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2164             :     return 0;
    2165           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2166           0 :     return fastEmitInst_r(ARM::VCVTh2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2167             :   }
    2168             :   return 0;
    2169             : }
    2170             : 
    2171             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2172           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2173             :     return 0;
    2174           0 :   if ((Subtarget->hasNEON())) {
    2175           0 :     return fastEmitInst_r(ARM::VCVTf2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2176             :   }
    2177             :   return 0;
    2178             : }
    2179             : 
    2180             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2181           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2182             :     return 0;
    2183           0 :   if ((Subtarget->hasNEON())) {
    2184           0 :     return fastEmitInst_r(ARM::VCVTf2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2185             :   }
    2186             :   return 0;
    2187             : }
    2188             : 
    2189           6 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2190           6 :   switch (VT.SimpleTy) {
    2191           0 :   case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2192           0 :   case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2193           0 :   case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2194           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2195             :   default: return 0;
    2196             :   }
    2197             : }
    2198             : 
    2199             : // FastEmit functions for ISD::FP_TO_UINT.
    2200             : 
    2201           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2202           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2203             :     return 0;
    2204           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2205           0 :     return fastEmitInst_r(ARM::VCVTh2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
    2206             :   }
    2207             :   return 0;
    2208             : }
    2209             : 
    2210           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2211           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2212             :     return 0;
    2213           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2214           0 :     return fastEmitInst_r(ARM::VCVTh2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2215             :   }
    2216             :   return 0;
    2217             : }
    2218             : 
    2219             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2220           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2221             :     return 0;
    2222           0 :   if ((Subtarget->hasNEON())) {
    2223           0 :     return fastEmitInst_r(ARM::VCVTf2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
    2224             :   }
    2225             :   return 0;
    2226             : }
    2227             : 
    2228             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2229           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2230             :     return 0;
    2231           0 :   if ((Subtarget->hasNEON())) {
    2232           0 :     return fastEmitInst_r(ARM::VCVTf2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2233             :   }
    2234             :   return 0;
    2235             : }
    2236             : 
    2237           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2238           0 :   switch (VT.SimpleTy) {
    2239           0 :   case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
    2240           0 :   case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
    2241           0 :   case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
    2242           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    2243             :   default: return 0;
    2244             :   }
    2245             : }
    2246             : 
    2247             : // FastEmit functions for ISD::FRINT.
    2248             : 
    2249             : unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2250           0 :   if (RetVT.SimpleTy != MVT::f32)
    2251             :     return 0;
    2252           0 :   if ((Subtarget->hasFPARMv8())) {
    2253           0 :     return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2254             :   }
    2255             :   return 0;
    2256             : }
    2257             : 
    2258           0 : unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2259           0 :   if (RetVT.SimpleTy != MVT::f64)
    2260             :     return 0;
    2261           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2262           0 :     return fastEmitInst_r(ARM::VRINTXD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2263             :   }
    2264             :   return 0;
    2265             : }
    2266             : 
    2267           0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2268           0 :   switch (VT.SimpleTy) {
    2269           0 :   case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2270           0 :   case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2271             :   default: return 0;
    2272             :   }
    2273             : }
    2274             : 
    2275             : // FastEmit functions for ISD::FROUND.
    2276             : 
    2277             : unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2278           0 :   if (RetVT.SimpleTy != MVT::f32)
    2279             :     return 0;
    2280           0 :   if ((Subtarget->hasFPARMv8())) {
    2281           0 :     return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2282             :   }
    2283             :   return 0;
    2284             : }
    2285             : 
    2286           0 : unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2287           0 :   if (RetVT.SimpleTy != MVT::f64)
    2288             :     return 0;
    2289           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2290           0 :     return fastEmitInst_r(ARM::VRINTAD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2291             :   }
    2292             :   return 0;
    2293             : }
    2294             : 
    2295           0 : unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2296           0 :   switch (VT.SimpleTy) {
    2297           0 :   case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2298           0 :   case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2299             :   default: return 0;
    2300             :   }
    2301             : }
    2302             : 
    2303             : // FastEmit functions for ISD::FSQRT.
    2304             : 
    2305             : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2306           0 :   if (RetVT.SimpleTy != MVT::f32)
    2307             :     return 0;
    2308           0 :   if ((Subtarget->hasVFP2())) {
    2309           0 :     return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2310             :   }
    2311             :   return 0;
    2312             : }
    2313             : 
    2314           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2315           0 :   if (RetVT.SimpleTy != MVT::f64)
    2316             :     return 0;
    2317           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    2318           0 :     return fastEmitInst_r(ARM::VSQRTD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2319             :   }
    2320             :   return 0;
    2321             : }
    2322             : 
    2323           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2324           0 :   switch (VT.SimpleTy) {
    2325           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2326           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2327             :   default: return 0;
    2328             :   }
    2329             : }
    2330             : 
    2331             : // FastEmit functions for ISD::FTRUNC.
    2332             : 
    2333             : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2334           0 :   if (RetVT.SimpleTy != MVT::f32)
    2335             :     return 0;
    2336           0 :   if ((Subtarget->hasFPARMv8())) {
    2337           0 :     return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill);
    2338             :   }
    2339             :   return 0;
    2340             : }
    2341             : 
    2342           0 : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2343           0 :   if (RetVT.SimpleTy != MVT::f64)
    2344             :     return 0;
    2345           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    2346           0 :     return fastEmitInst_r(ARM::VRINTZD, &ARM::DPRRegClass, Op0, Op0IsKill);
    2347             :   }
    2348             :   return 0;
    2349             : }
    2350             : 
    2351           0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2352           0 :   switch (VT.SimpleTy) {
    2353           0 :   case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
    2354           0 :   case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
    2355             :   default: return 0;
    2356             :   }
    2357             : }
    2358             : 
    2359             : // FastEmit functions for ISD::SIGN_EXTEND.
    2360             : 
    2361             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2362           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2363             :     return 0;
    2364           0 :   if ((Subtarget->hasNEON())) {
    2365           0 :     return fastEmitInst_r(ARM::VMOVLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    2366             :   }
    2367             :   return 0;
    2368             : }
    2369             : 
    2370             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2371           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2372             :     return 0;
    2373           0 :   if ((Subtarget->hasNEON())) {
    2374           0 :     return fastEmitInst_r(ARM::VMOVLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    2375             :   }
    2376             :   return 0;
    2377             : }
    2378             : 
    2379             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2380           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2381             :     return 0;
    2382           0 :   if ((Subtarget->hasNEON())) {
    2383           0 :     return fastEmitInst_r(ARM::VMOVLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    2384             :   }
    2385             :   return 0;
    2386             : }
    2387             : 
    2388           1 : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2389           1 :   switch (VT.SimpleTy) {
    2390           0 :   case MVT::v8i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    2391           0 :   case MVT::v4i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2392           0 :   case MVT::v2i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2393             :   default: return 0;
    2394             :   }
    2395             : }
    2396             : 
    2397             : // FastEmit functions for ISD::SINT_TO_FP.
    2398             : 
    2399           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2400           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    2401             :     return 0;
    2402           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2403           0 :     return fastEmitInst_r(ARM::VCVTs2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2404             :   }
    2405             :   return 0;
    2406             : }
    2407             : 
    2408           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2409           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    2410             :     return 0;
    2411           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2412           0 :     return fastEmitInst_r(ARM::VCVTs2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2413             :   }
    2414             :   return 0;
    2415             : }
    2416             : 
    2417             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2418           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    2419             :     return 0;
    2420           0 :   if ((Subtarget->hasNEON())) {
    2421           0 :     return fastEmitInst_r(ARM::VCVTs2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2422             :   }
    2423             :   return 0;
    2424             : }
    2425             : 
    2426             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2427           2 :   if (RetVT.SimpleTy != MVT::v4f32)
    2428             :     return 0;
    2429           2 :   if ((Subtarget->hasNEON())) {
    2430           2 :     return fastEmitInst_r(ARM::VCVTs2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2431             :   }
    2432             :   return 0;
    2433             : }
    2434             : 
    2435           9 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2436           9 :   switch (VT.SimpleTy) {
    2437           0 :   case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2438           0 :   case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2439           0 :   case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2440           2 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2441             :   default: return 0;
    2442             :   }
    2443             : }
    2444             : 
    2445             : // FastEmit functions for ISD::TRUNCATE.
    2446             : 
    2447             : unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2448           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2449             :     return 0;
    2450           0 :   if ((Subtarget->hasNEON())) {
    2451           0 :     return fastEmitInst_r(ARM::VMOVNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
    2452             :   }
    2453             :   return 0;
    2454             : }
    2455             : 
    2456             : unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2457           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2458             :     return 0;
    2459           0 :   if ((Subtarget->hasNEON())) {
    2460           0 :     return fastEmitInst_r(ARM::VMOVNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
    2461             :   }
    2462             :   return 0;
    2463             : }
    2464             : 
    2465             : unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2466           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2467             :     return 0;
    2468           0 :   if ((Subtarget->hasNEON())) {
    2469           0 :     return fastEmitInst_r(ARM::VMOVNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
    2470             :   }
    2471             :   return 0;
    2472             : }
    2473             : 
    2474           0 : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2475           0 :   switch (VT.SimpleTy) {
    2476           0 :   case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2477           0 :   case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2478           0 :   case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    2479             :   default: return 0;
    2480             :   }
    2481             : }
    2482             : 
    2483             : // FastEmit functions for ISD::UINT_TO_FP.
    2484             : 
    2485           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2486           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    2487             :     return 0;
    2488           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2489           0 :     return fastEmitInst_r(ARM::VCVTu2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2490             :   }
    2491             :   return 0;
    2492             : }
    2493             : 
    2494           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2495           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    2496             :     return 0;
    2497           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2498           0 :     return fastEmitInst_r(ARM::VCVTu2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2499             :   }
    2500             :   return 0;
    2501             : }
    2502             : 
    2503             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2504           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    2505             :     return 0;
    2506           0 :   if ((Subtarget->hasNEON())) {
    2507           0 :     return fastEmitInst_r(ARM::VCVTu2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
    2508             :   }
    2509             :   return 0;
    2510             : }
    2511             : 
    2512             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2513           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2514             :     return 0;
    2515           0 :   if ((Subtarget->hasNEON())) {
    2516           0 :     return fastEmitInst_r(ARM::VCVTu2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
    2517             :   }
    2518             :   return 0;
    2519             : }
    2520             : 
    2521           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2522           0 :   switch (VT.SimpleTy) {
    2523           0 :   case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2524           0 :   case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    2525           0 :   case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2526           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    2527             :   default: return 0;
    2528             :   }
    2529             : }
    2530             : 
    2531             : // FastEmit functions for ISD::ZERO_EXTEND.
    2532             : 
    2533             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2534           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2535             :     return 0;
    2536           0 :   if ((Subtarget->hasNEON())) {
    2537           0 :     return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
    2538             :   }
    2539             :   return 0;
    2540             : }
    2541             : 
    2542             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2543           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2544             :     return 0;
    2545           0 :   if ((Subtarget->hasNEON())) {
    2546           0 :     return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
    2547             :   }
    2548             :   return 0;
    2549             : }
    2550             : 
    2551             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2552           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2553             :     return 0;
    2554           0 :   if ((Subtarget->hasNEON())) {
    2555           0 :     return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
    2556             :   }
    2557             :   return 0;
    2558             : }
    2559             : 
    2560           0 : unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    2561           0 :   switch (VT.SimpleTy) {
    2562           0 :   case MVT::v8i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
    2563           0 :   case MVT::v4i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
    2564           0 :   case MVT::v2i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
    2565             :   default: return 0;
    2566             :   }
    2567             : }
    2568             : 
    2569             : // Top-level FastEmit function.
    2570             : 
    2571          99 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    2572          99 :   switch (Opcode) {
    2573           0 :   case ARMISD::CALL: return fastEmit_ARMISD_CALL_r(VT, RetVT, Op0, Op0IsKill);
    2574           0 :   case ARMISD::CALL_NOLINK: return fastEmit_ARMISD_CALL_NOLINK_r(VT, RetVT, Op0, Op0IsKill);
    2575           0 :   case ARMISD::CALL_PRED: return fastEmit_ARMISD_CALL_PRED_r(VT, RetVT, Op0, Op0IsKill);
    2576           0 :   case ARMISD::RRX: return fastEmit_ARMISD_RRX_r(VT, RetVT, Op0, Op0IsKill);
    2577           0 :   case ARMISD::SRA_FLAG: return fastEmit_ARMISD_SRA_FLAG_r(VT, RetVT, Op0, Op0IsKill);
    2578           0 :   case ARMISD::SRL_FLAG: return fastEmit_ARMISD_SRL_FLAG_r(VT, RetVT, Op0, Op0IsKill);
    2579           0 :   case ARMISD::TC_RETURN: return fastEmit_ARMISD_TC_RETURN_r(VT, RetVT, Op0, Op0IsKill);
    2580           0 :   case ARMISD::VCEQZ: return fastEmit_ARMISD_VCEQZ_r(VT, RetVT, Op0, Op0IsKill);
    2581           0 :   case ARMISD::VCGEZ: return fastEmit_ARMISD_VCGEZ_r(VT, RetVT, Op0, Op0IsKill);
    2582           0 :   case ARMISD::VCGTZ: return fastEmit_ARMISD_VCGTZ_r(VT, RetVT, Op0, Op0IsKill);
    2583           0 :   case ARMISD::VCLEZ: return fastEmit_ARMISD_VCLEZ_r(VT, RetVT, Op0, Op0IsKill);
    2584           0 :   case ARMISD::VCLTZ: return fastEmit_ARMISD_VCLTZ_r(VT, RetVT, Op0, Op0IsKill);
    2585           0 :   case ARMISD::VDUP: return fastEmit_ARMISD_VDUP_r(VT, RetVT, Op0, Op0IsKill);
    2586           0 :   case ARMISD::VMOVSR: return fastEmit_ARMISD_VMOVSR_r(VT, RetVT, Op0, Op0IsKill);
    2587           0 :   case ARMISD::VMOVhr: return fastEmit_ARMISD_VMOVhr_r(VT, RetVT, Op0, Op0IsKill);
    2588           0 :   case ARMISD::VMOVrh: return fastEmit_ARMISD_VMOVrh_r(VT, RetVT, Op0, Op0IsKill);
    2589           0 :   case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill);
    2590           0 :   case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill);
    2591           0 :   case ARMISD::VREV64: return fastEmit_ARMISD_VREV64_r(VT, RetVT, Op0, Op0IsKill);
    2592           0 :   case ARMISD::WIN__DBZCHK: return fastEmit_ARMISD_WIN__DBZCHK_r(VT, RetVT, Op0, Op0IsKill);
    2593           0 :   case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill);
    2594           0 :   case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2595          83 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    2596           0 :   case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill);
    2597           0 :   case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
    2598           0 :   case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill);
    2599           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    2600           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    2601           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    2602           0 :   case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
    2603           0 :   case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
    2604           0 :   case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
    2605           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    2606           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2607           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    2608           6 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    2609           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    2610           0 :   case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
    2611           0 :   case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill);
    2612           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    2613           0 :   case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
    2614           1 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2615           9 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    2616           0 :   case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
    2617           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    2618           0 :   case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    2619             :   default: return 0;
    2620             :   }
    2621             : }
    2622             : 
    2623             : // FastEmit functions for ARMISD::CMP.
    2624             : 
    2625           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2626           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2627             :     return 0;
    2628           0 :   if ((Subtarget->isThumb2())) {
    2629           0 :     return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2630             :   }
    2631           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2632           0 :     return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2633             :   }
    2634           0 :   if ((!Subtarget->isThumb())) {
    2635           0 :     return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2636             :   }
    2637             :   return 0;
    2638             : }
    2639             : 
    2640             : unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2641           0 :   switch (VT.SimpleTy) {
    2642           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2643             :   default: return 0;
    2644             :   }
    2645             : }
    2646             : 
    2647             : // FastEmit functions for ARMISD::CMPZ.
    2648             : 
    2649           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2650           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2651             :     return 0;
    2652           0 :   if ((Subtarget->isThumb2())) {
    2653           0 :     return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2654             :   }
    2655           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2656           0 :     return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2657             :   }
    2658           0 :   if ((!Subtarget->isThumb())) {
    2659           0 :     return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2660             :   }
    2661             :   return 0;
    2662             : }
    2663             : 
    2664             : unsigned fastEmit_ARMISD_CMPZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2665           0 :   switch (VT.SimpleTy) {
    2666           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2667             :   default: return 0;
    2668             :   }
    2669             : }
    2670             : 
    2671             : // FastEmit functions for ARMISD::EH_SJLJ_LONGJMP.
    2672             : 
    2673           0 : unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2674           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2675             :     return 0;
    2676           0 :   if ((Subtarget->isThumb()) && (Subtarget->isTargetWindows())) {
    2677           0 :     return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2678             :   }
    2679           0 :   if ((!Subtarget->isTargetWindows()) && (Subtarget->isThumb())) {
    2680           0 :     return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2681             :   }
    2682           0 :   if ((!Subtarget->isThumb())) {
    2683           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2684             :   }
    2685             :   return 0;
    2686             : }
    2687             : 
    2688             : unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2689           0 :   switch (VT.SimpleTy) {
    2690           0 :   case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2691             :   default: return 0;
    2692             :   }
    2693             : }
    2694             : 
    2695             : // FastEmit functions for ARMISD::EH_SJLJ_SETJMP.
    2696             : 
    2697           0 : unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2698           0 :   if (RetVT.SimpleTy != MVT::i32)
    2699             :     return 0;
    2700           0 :   if ((Subtarget->isThumb2()) && (!Subtarget->hasVFP2())) {
    2701           0 :     return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2702             :   }
    2703           0 :   if ((Subtarget->hasVFP2()) && (Subtarget->isThumb2())) {
    2704           0 :     return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2705             :   }
    2706           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    2707           0 :     return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2708             :   }
    2709           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasVFP2())) {
    2710           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2711             :   }
    2712           0 :   if ((Subtarget->hasVFP2()) && (!Subtarget->isThumb())) {
    2713           0 :     return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2714             :   }
    2715             :   return 0;
    2716             : }
    2717             : 
    2718             : unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2719           0 :   switch (VT.SimpleTy) {
    2720           0 :   case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2721             :   default: return 0;
    2722             :   }
    2723             : }
    2724             : 
    2725             : // FastEmit functions for ARMISD::SMULWB.
    2726             : 
    2727           0 : unsigned fastEmit_ARMISD_SMULWB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2728           0 :   if (RetVT.SimpleTy != MVT::i32)
    2729             :     return 0;
    2730           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    2731           0 :     return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2732             :   }
    2733           0 :   if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
    2734           0 :     return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2735             :   }
    2736             :   return 0;
    2737             : }
    2738             : 
    2739             : unsigned fastEmit_ARMISD_SMULWB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2740           0 :   switch (VT.SimpleTy) {
    2741           0 :   case MVT::i32: return fastEmit_ARMISD_SMULWB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2742             :   default: return 0;
    2743             :   }
    2744             : }
    2745             : 
    2746             : // FastEmit functions for ARMISD::SMULWT.
    2747             : 
    2748           0 : unsigned fastEmit_ARMISD_SMULWT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2749           0 :   if (RetVT.SimpleTy != MVT::i32)
    2750             :     return 0;
    2751           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    2752           0 :     return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2753             :   }
    2754           0 :   if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
    2755           0 :     return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2756             :   }
    2757             :   return 0;
    2758             : }
    2759             : 
    2760             : unsigned fastEmit_ARMISD_SMULWT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2761           0 :   switch (VT.SimpleTy) {
    2762           0 :   case MVT::i32: return fastEmit_ARMISD_SMULWT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2763             :   default: return 0;
    2764             :   }
    2765             : }
    2766             : 
    2767             : // FastEmit functions for ARMISD::VCEQ.
    2768             : 
    2769             : unsigned fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2770           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2771             :     return 0;
    2772           0 :   if ((Subtarget->hasNEON())) {
    2773           0 :     return fastEmitInst_rr(ARM::VCEQv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2774             :   }
    2775             :   return 0;
    2776             : }
    2777             : 
    2778             : unsigned fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2779           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2780             :     return 0;
    2781           0 :   if ((Subtarget->hasNEON())) {
    2782           0 :     return fastEmitInst_rr(ARM::VCEQv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2783             :   }
    2784             :   return 0;
    2785             : }
    2786             : 
    2787             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2788           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2789             :     return 0;
    2790           0 :   if ((Subtarget->hasNEON())) {
    2791           0 :     return fastEmitInst_rr(ARM::VCEQv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2792             :   }
    2793             :   return 0;
    2794             : }
    2795             : 
    2796             : unsigned fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2797           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2798             :     return 0;
    2799           0 :   if ((Subtarget->hasNEON())) {
    2800           0 :     return fastEmitInst_rr(ARM::VCEQv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2801             :   }
    2802             :   return 0;
    2803             : }
    2804             : 
    2805             : unsigned fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2806           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2807             :     return 0;
    2808           0 :   if ((Subtarget->hasNEON())) {
    2809           0 :     return fastEmitInst_rr(ARM::VCEQv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2810             :   }
    2811             :   return 0;
    2812             : }
    2813             : 
    2814             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2815           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2816             :     return 0;
    2817           0 :   if ((Subtarget->hasNEON())) {
    2818           0 :     return fastEmitInst_rr(ARM::VCEQv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2819             :   }
    2820             :   return 0;
    2821             : }
    2822             : 
    2823           0 : unsigned fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2824           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2825             :     return 0;
    2826           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2827           0 :     return fastEmitInst_rr(ARM::VCEQhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2828             :   }
    2829             :   return 0;
    2830             : }
    2831             : 
    2832           0 : unsigned fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2833           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2834             :     return 0;
    2835           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2836           0 :     return fastEmitInst_rr(ARM::VCEQhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2837             :   }
    2838             :   return 0;
    2839             : }
    2840             : 
    2841             : unsigned fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2842           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2843             :     return 0;
    2844           0 :   if ((Subtarget->hasNEON())) {
    2845           0 :     return fastEmitInst_rr(ARM::VCEQfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2846             :   }
    2847             :   return 0;
    2848             : }
    2849             : 
    2850             : unsigned fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2851           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2852             :     return 0;
    2853           0 :   if ((Subtarget->hasNEON())) {
    2854           0 :     return fastEmitInst_rr(ARM::VCEQfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2855             :   }
    2856             :   return 0;
    2857             : }
    2858             : 
    2859           0 : unsigned fastEmit_ARMISD_VCEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2860           0 :   switch (VT.SimpleTy) {
    2861           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2862           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2863           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2864           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2865           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2866           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2867           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2868           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2869           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2870           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2871             :   default: return 0;
    2872             :   }
    2873             : }
    2874             : 
    2875             : // FastEmit functions for ARMISD::VCGE.
    2876             : 
    2877             : unsigned fastEmit_ARMISD_VCGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2878           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2879             :     return 0;
    2880           0 :   if ((Subtarget->hasNEON())) {
    2881           0 :     return fastEmitInst_rr(ARM::VCGEsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2882             :   }
    2883             :   return 0;
    2884             : }
    2885             : 
    2886             : unsigned fastEmit_ARMISD_VCGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2887           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2888             :     return 0;
    2889           0 :   if ((Subtarget->hasNEON())) {
    2890           0 :     return fastEmitInst_rr(ARM::VCGEsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2891             :   }
    2892             :   return 0;
    2893             : }
    2894             : 
    2895             : unsigned fastEmit_ARMISD_VCGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2896           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2897             :     return 0;
    2898           0 :   if ((Subtarget->hasNEON())) {
    2899           0 :     return fastEmitInst_rr(ARM::VCGEsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2900             :   }
    2901             :   return 0;
    2902             : }
    2903             : 
    2904             : unsigned fastEmit_ARMISD_VCGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2905           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2906             :     return 0;
    2907           0 :   if ((Subtarget->hasNEON())) {
    2908           0 :     return fastEmitInst_rr(ARM::VCGEsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2909             :   }
    2910             :   return 0;
    2911             : }
    2912             : 
    2913             : unsigned fastEmit_ARMISD_VCGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2914           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2915             :     return 0;
    2916           0 :   if ((Subtarget->hasNEON())) {
    2917           0 :     return fastEmitInst_rr(ARM::VCGEsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2918             :   }
    2919             :   return 0;
    2920             : }
    2921             : 
    2922             : unsigned fastEmit_ARMISD_VCGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2923           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2924             :     return 0;
    2925           0 :   if ((Subtarget->hasNEON())) {
    2926           0 :     return fastEmitInst_rr(ARM::VCGEsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2927             :   }
    2928             :   return 0;
    2929             : }
    2930             : 
    2931           0 : unsigned fastEmit_ARMISD_VCGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2932           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    2933             :     return 0;
    2934           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2935           0 :     return fastEmitInst_rr(ARM::VCGEhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2936             :   }
    2937             :   return 0;
    2938             : }
    2939             : 
    2940           0 : unsigned fastEmit_ARMISD_VCGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2941           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2942             :     return 0;
    2943           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    2944           0 :     return fastEmitInst_rr(ARM::VCGEhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2945             :   }
    2946             :   return 0;
    2947             : }
    2948             : 
    2949             : unsigned fastEmit_ARMISD_VCGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2950           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    2951             :     return 0;
    2952           0 :   if ((Subtarget->hasNEON())) {
    2953           0 :     return fastEmitInst_rr(ARM::VCGEfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2954             :   }
    2955             :   return 0;
    2956             : }
    2957             : 
    2958             : unsigned fastEmit_ARMISD_VCGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2959           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2960             :     return 0;
    2961           0 :   if ((Subtarget->hasNEON())) {
    2962           0 :     return fastEmitInst_rr(ARM::VCGEfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2963             :   }
    2964             :   return 0;
    2965             : }
    2966             : 
    2967           0 : unsigned fastEmit_ARMISD_VCGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2968           0 :   switch (VT.SimpleTy) {
    2969           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2970           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2971           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2972           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2973           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2974           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2975           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2976           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2977           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2978           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2979             :   default: return 0;
    2980             :   }
    2981             : }
    2982             : 
    2983             : // FastEmit functions for ARMISD::VCGEU.
    2984             : 
    2985             : unsigned fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2986           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    2987             :     return 0;
    2988           0 :   if ((Subtarget->hasNEON())) {
    2989           0 :     return fastEmitInst_rr(ARM::VCGEuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2990             :   }
    2991             :   return 0;
    2992             : }
    2993             : 
    2994             : unsigned fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2995           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2996             :     return 0;
    2997           0 :   if ((Subtarget->hasNEON())) {
    2998           0 :     return fastEmitInst_rr(ARM::VCGEuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2999             :   }
    3000             :   return 0;
    3001             : }
    3002             : 
    3003             : unsigned fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3004           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3005             :     return 0;
    3006           0 :   if ((Subtarget->hasNEON())) {
    3007           0 :     return fastEmitInst_rr(ARM::VCGEuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3008             :   }
    3009             :   return 0;
    3010             : }
    3011             : 
    3012             : unsigned fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3013           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3014             :     return 0;
    3015           0 :   if ((Subtarget->hasNEON())) {
    3016           0 :     return fastEmitInst_rr(ARM::VCGEuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3017             :   }
    3018             :   return 0;
    3019             : }
    3020             : 
    3021             : unsigned fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3022           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3023             :     return 0;
    3024           0 :   if ((Subtarget->hasNEON())) {
    3025           0 :     return fastEmitInst_rr(ARM::VCGEuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3026             :   }
    3027             :   return 0;
    3028             : }
    3029             : 
    3030             : unsigned fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3031           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3032             :     return 0;
    3033           0 :   if ((Subtarget->hasNEON())) {
    3034           0 :     return fastEmitInst_rr(ARM::VCGEuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3035             :   }
    3036             :   return 0;
    3037             : }
    3038             : 
    3039           0 : unsigned fastEmit_ARMISD_VCGEU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3040           0 :   switch (VT.SimpleTy) {
    3041           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3042           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3043           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3044           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3045           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3046           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3047             :   default: return 0;
    3048             :   }
    3049             : }
    3050             : 
    3051             : // FastEmit functions for ARMISD::VCGT.
    3052             : 
    3053             : unsigned fastEmit_ARMISD_VCGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3054           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3055             :     return 0;
    3056           0 :   if ((Subtarget->hasNEON())) {
    3057           0 :     return fastEmitInst_rr(ARM::VCGTsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3058             :   }
    3059             :   return 0;
    3060             : }
    3061             : 
    3062             : unsigned fastEmit_ARMISD_VCGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3063           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3064             :     return 0;
    3065           0 :   if ((Subtarget->hasNEON())) {
    3066           0 :     return fastEmitInst_rr(ARM::VCGTsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3067             :   }
    3068             :   return 0;
    3069             : }
    3070             : 
    3071             : unsigned fastEmit_ARMISD_VCGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3072           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3073             :     return 0;
    3074           0 :   if ((Subtarget->hasNEON())) {
    3075           0 :     return fastEmitInst_rr(ARM::VCGTsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3076             :   }
    3077             :   return 0;
    3078             : }
    3079             : 
    3080             : unsigned fastEmit_ARMISD_VCGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3081           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3082             :     return 0;
    3083           0 :   if ((Subtarget->hasNEON())) {
    3084           0 :     return fastEmitInst_rr(ARM::VCGTsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3085             :   }
    3086             :   return 0;
    3087             : }
    3088             : 
    3089             : unsigned fastEmit_ARMISD_VCGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3090           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3091             :     return 0;
    3092           0 :   if ((Subtarget->hasNEON())) {
    3093           0 :     return fastEmitInst_rr(ARM::VCGTsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3094             :   }
    3095             :   return 0;
    3096             : }
    3097             : 
    3098             : unsigned fastEmit_ARMISD_VCGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3099           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3100             :     return 0;
    3101           0 :   if ((Subtarget->hasNEON())) {
    3102           0 :     return fastEmitInst_rr(ARM::VCGTsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3103             :   }
    3104             :   return 0;
    3105             : }
    3106             : 
    3107           0 : unsigned fastEmit_ARMISD_VCGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3108           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3109             :     return 0;
    3110           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3111           0 :     return fastEmitInst_rr(ARM::VCGThd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3112             :   }
    3113             :   return 0;
    3114             : }
    3115             : 
    3116           0 : unsigned fastEmit_ARMISD_VCGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3117           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3118             :     return 0;
    3119           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3120           0 :     return fastEmitInst_rr(ARM::VCGThq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3121             :   }
    3122             :   return 0;
    3123             : }
    3124             : 
    3125             : unsigned fastEmit_ARMISD_VCGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3126           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3127             :     return 0;
    3128           0 :   if ((Subtarget->hasNEON())) {
    3129           0 :     return fastEmitInst_rr(ARM::VCGTfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3130             :   }
    3131             :   return 0;
    3132             : }
    3133             : 
    3134             : unsigned fastEmit_ARMISD_VCGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3135           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3136             :     return 0;
    3137           0 :   if ((Subtarget->hasNEON())) {
    3138           0 :     return fastEmitInst_rr(ARM::VCGTfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3139             :   }
    3140             :   return 0;
    3141             : }
    3142             : 
    3143           0 : unsigned fastEmit_ARMISD_VCGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3144           0 :   switch (VT.SimpleTy) {
    3145           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3146           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3147           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3148           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3149           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3150           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3151           0 :   case MVT::v4f16: return fastEmit_ARMISD_VCGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3152           0 :   case MVT::v8f16: return fastEmit_ARMISD_VCGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3153           0 :   case MVT::v2f32: return fastEmit_ARMISD_VCGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3154           0 :   case MVT::v4f32: return fastEmit_ARMISD_VCGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3155             :   default: return 0;
    3156             :   }
    3157             : }
    3158             : 
    3159             : // FastEmit functions for ARMISD::VCGTU.
    3160             : 
    3161             : unsigned fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3162           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3163             :     return 0;
    3164           0 :   if ((Subtarget->hasNEON())) {
    3165           0 :     return fastEmitInst_rr(ARM::VCGTuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3166             :   }
    3167             :   return 0;
    3168             : }
    3169             : 
    3170             : unsigned fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3171           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3172             :     return 0;
    3173           0 :   if ((Subtarget->hasNEON())) {
    3174           0 :     return fastEmitInst_rr(ARM::VCGTuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3175             :   }
    3176             :   return 0;
    3177             : }
    3178             : 
    3179             : unsigned fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3180           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3181             :     return 0;
    3182           0 :   if ((Subtarget->hasNEON())) {
    3183           0 :     return fastEmitInst_rr(ARM::VCGTuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3184             :   }
    3185             :   return 0;
    3186             : }
    3187             : 
    3188             : unsigned fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3189           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3190             :     return 0;
    3191           0 :   if ((Subtarget->hasNEON())) {
    3192           0 :     return fastEmitInst_rr(ARM::VCGTuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3193             :   }
    3194             :   return 0;
    3195             : }
    3196             : 
    3197             : unsigned fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3198           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3199             :     return 0;
    3200           0 :   if ((Subtarget->hasNEON())) {
    3201           0 :     return fastEmitInst_rr(ARM::VCGTuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3202             :   }
    3203             :   return 0;
    3204             : }
    3205             : 
    3206             : unsigned fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3207           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3208             :     return 0;
    3209           0 :   if ((Subtarget->hasNEON())) {
    3210           0 :     return fastEmitInst_rr(ARM::VCGTuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3211             :   }
    3212             :   return 0;
    3213             : }
    3214             : 
    3215           0 : unsigned fastEmit_ARMISD_VCGTU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3216           0 :   switch (VT.SimpleTy) {
    3217           0 :   case MVT::v8i8: return fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3218           0 :   case MVT::v16i8: return fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3219           0 :   case MVT::v4i16: return fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3220           0 :   case MVT::v8i16: return fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3221           0 :   case MVT::v2i32: return fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3222           0 :   case MVT::v4i32: return fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3223             :   default: return 0;
    3224             :   }
    3225             : }
    3226             : 
    3227             : // FastEmit functions for ARMISD::VMOVDRR.
    3228             : 
    3229             : unsigned fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3230           0 :   if (RetVT.SimpleTy != MVT::f64)
    3231             :     return 0;
    3232           0 :   if ((Subtarget->hasVFP2())) {
    3233           0 :     return fastEmitInst_rr(ARM::VMOVDRR, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3234             :   }
    3235             :   return 0;
    3236             : }
    3237             : 
    3238           0 : unsigned fastEmit_ARMISD_VMOVDRR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3239           0 :   switch (VT.SimpleTy) {
    3240           0 :   case MVT::i32: return fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3241             :   default: return 0;
    3242             :   }
    3243             : }
    3244             : 
    3245             : // FastEmit functions for ARMISD::VMULLs.
    3246             : 
    3247             : unsigned fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3248           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3249             :     return 0;
    3250           0 :   if ((Subtarget->hasNEON())) {
    3251           0 :     return fastEmitInst_rr(ARM::VMULLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3252             :   }
    3253             :   return 0;
    3254             : }
    3255             : 
    3256             : unsigned fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3257           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3258             :     return 0;
    3259           0 :   if ((Subtarget->hasNEON())) {
    3260           0 :     return fastEmitInst_rr(ARM::VMULLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3261             :   }
    3262             :   return 0;
    3263             : }
    3264             : 
    3265             : unsigned fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3266           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3267             :     return 0;
    3268           0 :   if ((Subtarget->hasNEON())) {
    3269           0 :     return fastEmitInst_rr(ARM::VMULLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3270             :   }
    3271             :   return 0;
    3272             : }
    3273             : 
    3274           0 : unsigned fastEmit_ARMISD_VMULLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3275           0 :   switch (VT.SimpleTy) {
    3276           0 :   case MVT::v8i8: return fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3277           0 :   case MVT::v4i16: return fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3278           0 :   case MVT::v2i32: return fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3279             :   default: return 0;
    3280             :   }
    3281             : }
    3282             : 
    3283             : // FastEmit functions for ARMISD::VMULLu.
    3284             : 
    3285             : unsigned fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3286           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3287             :     return 0;
    3288           0 :   if ((Subtarget->hasNEON())) {
    3289           0 :     return fastEmitInst_rr(ARM::VMULLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3290             :   }
    3291             :   return 0;
    3292             : }
    3293             : 
    3294             : unsigned fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3295           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3296             :     return 0;
    3297           0 :   if ((Subtarget->hasNEON())) {
    3298           0 :     return fastEmitInst_rr(ARM::VMULLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3299             :   }
    3300             :   return 0;
    3301             : }
    3302             : 
    3303             : unsigned fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3304           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3305             :     return 0;
    3306           0 :   if ((Subtarget->hasNEON())) {
    3307           0 :     return fastEmitInst_rr(ARM::VMULLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3308             :   }
    3309             :   return 0;
    3310             : }
    3311             : 
    3312           0 : unsigned fastEmit_ARMISD_VMULLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3313           0 :   switch (VT.SimpleTy) {
    3314           0 :   case MVT::v8i8: return fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3315           0 :   case MVT::v4i16: return fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3316           0 :   case MVT::v2i32: return fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3317             :   default: return 0;
    3318             :   }
    3319             : }
    3320             : 
    3321             : // FastEmit functions for ARMISD::VTBL1.
    3322             : 
    3323             : unsigned fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3324           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3325             :     return 0;
    3326           0 :   if ((Subtarget->hasNEON())) {
    3327           0 :     return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3328             :   }
    3329             :   return 0;
    3330             : }
    3331             : 
    3332           0 : unsigned fastEmit_ARMISD_VTBL1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3333           0 :   switch (VT.SimpleTy) {
    3334           0 :   case MVT::v8i8: return fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3335             :   default: return 0;
    3336             :   }
    3337             : }
    3338             : 
    3339             : // FastEmit functions for ARMISD::VTST.
    3340             : 
    3341             : unsigned fastEmit_ARMISD_VTST_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3342           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3343             :     return 0;
    3344           0 :   if ((Subtarget->hasNEON())) {
    3345           0 :     return fastEmitInst_rr(ARM::VTSTv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3346             :   }
    3347             :   return 0;
    3348             : }
    3349             : 
    3350             : unsigned fastEmit_ARMISD_VTST_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3351           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3352             :     return 0;
    3353           0 :   if ((Subtarget->hasNEON())) {
    3354           0 :     return fastEmitInst_rr(ARM::VTSTv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3355             :   }
    3356             :   return 0;
    3357             : }
    3358             : 
    3359             : unsigned fastEmit_ARMISD_VTST_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3360           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3361             :     return 0;
    3362           0 :   if ((Subtarget->hasNEON())) {
    3363           0 :     return fastEmitInst_rr(ARM::VTSTv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3364             :   }
    3365             :   return 0;
    3366             : }
    3367             : 
    3368             : unsigned fastEmit_ARMISD_VTST_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3369           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3370             :     return 0;
    3371           0 :   if ((Subtarget->hasNEON())) {
    3372           0 :     return fastEmitInst_rr(ARM::VTSTv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3373             :   }
    3374             :   return 0;
    3375             : }
    3376             : 
    3377             : unsigned fastEmit_ARMISD_VTST_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3378           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3379             :     return 0;
    3380           0 :   if ((Subtarget->hasNEON())) {
    3381           0 :     return fastEmitInst_rr(ARM::VTSTv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3382             :   }
    3383             :   return 0;
    3384             : }
    3385             : 
    3386             : unsigned fastEmit_ARMISD_VTST_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3387           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3388             :     return 0;
    3389           0 :   if ((Subtarget->hasNEON())) {
    3390           0 :     return fastEmitInst_rr(ARM::VTSTv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3391             :   }
    3392             :   return 0;
    3393             : }
    3394             : 
    3395           0 : unsigned fastEmit_ARMISD_VTST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3396           0 :   switch (VT.SimpleTy) {
    3397           0 :   case MVT::v8i8: return fastEmit_ARMISD_VTST_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3398           0 :   case MVT::v16i8: return fastEmit_ARMISD_VTST_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3399           0 :   case MVT::v4i16: return fastEmit_ARMISD_VTST_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3400           0 :   case MVT::v8i16: return fastEmit_ARMISD_VTST_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3401           0 :   case MVT::v2i32: return fastEmit_ARMISD_VTST_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3402           0 :   case MVT::v4i32: return fastEmit_ARMISD_VTST_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3403             :   default: return 0;
    3404             :   }
    3405             : }
    3406             : 
    3407             : // FastEmit functions for ISD::ADD.
    3408             : 
    3409          94 : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3410          94 :   if (RetVT.SimpleTy != MVT::i32)
    3411             :     return 0;
    3412          94 :   if ((Subtarget->isThumb2())) {
    3413          20 :     return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3414             :   }
    3415          74 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    3416           0 :     return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3417             :   }
    3418          74 :   if ((!Subtarget->isThumb())) {
    3419          74 :     return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3420             :   }
    3421             :   return 0;
    3422             : }
    3423             : 
    3424             : unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3425           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    3426             :     return 0;
    3427           0 :   if ((Subtarget->hasNEON())) {
    3428           0 :     return fastEmitInst_rr(ARM::VADDv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3429             :   }
    3430             :   return 0;
    3431             : }
    3432             : 
    3433             : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3434           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3435             :     return 0;
    3436           0 :   if ((Subtarget->hasNEON())) {
    3437           0 :     return fastEmitInst_rr(ARM::VADDv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3438             :   }
    3439             :   return 0;
    3440             : }
    3441             : 
    3442             : unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3443           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    3444             :     return 0;
    3445           0 :   if ((Subtarget->hasNEON())) {
    3446           0 :     return fastEmitInst_rr(ARM::VADDv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3447             :   }
    3448             :   return 0;
    3449             : }
    3450             : 
    3451             : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3452           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3453             :     return 0;
    3454           0 :   if ((Subtarget->hasNEON())) {
    3455           0 :     return fastEmitInst_rr(ARM::VADDv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3456             :   }
    3457             :   return 0;
    3458             : }
    3459             : 
    3460             : unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3461           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3462             :     return 0;
    3463           0 :   if ((Subtarget->hasNEON())) {
    3464           0 :     return fastEmitInst_rr(ARM::VADDv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3465             :   }
    3466             :   return 0;
    3467             : }
    3468             : 
    3469             : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3470           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3471             :     return 0;
    3472           0 :   if ((Subtarget->hasNEON())) {
    3473           0 :     return fastEmitInst_rr(ARM::VADDv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3474             :   }
    3475             :   return 0;
    3476             : }
    3477             : 
    3478             : unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3479           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    3480             :     return 0;
    3481           0 :   if ((Subtarget->hasNEON())) {
    3482           0 :     return fastEmitInst_rr(ARM::VADDv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3483             :   }
    3484             :   return 0;
    3485             : }
    3486             : 
    3487             : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3488           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3489             :     return 0;
    3490           0 :   if ((Subtarget->hasNEON())) {
    3491           0 :     return fastEmitInst_rr(ARM::VADDv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3492             :   }
    3493             :   return 0;
    3494             : }
    3495             : 
    3496          94 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3497          94 :   switch (VT.SimpleTy) {
    3498          94 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3499           0 :   case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3500           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3501           0 :   case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3502           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3503           0 :   case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3504           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3505           0 :   case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3506           0 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3507             :   default: return 0;
    3508             :   }
    3509             : }
    3510             : 
    3511             : // FastEmit functions for ISD::AND.
    3512             : 
    3513           0 : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3514           0 :   if (RetVT.SimpleTy != MVT::i32)
    3515             :     return 0;
    3516           0 :   if ((Subtarget->isThumb2())) {
    3517           0 :     return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3518             :   }
    3519           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    3520           0 :     return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3521             :   }
    3522           0 :   if ((!Subtarget->isThumb())) {
    3523           0 :     return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3524             :   }
    3525             :   return 0;
    3526             : }
    3527             : 
    3528             : unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3529           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    3530             :     return 0;
    3531           0 :   if ((Subtarget->hasNEON())) {
    3532           0 :     return fastEmitInst_rr(ARM::VANDd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3533             :   }
    3534             :   return 0;
    3535             : }
    3536             : 
    3537             : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3538           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3539             :     return 0;
    3540           0 :   if ((Subtarget->hasNEON())) {
    3541           0 :     return fastEmitInst_rr(ARM::VANDq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3542             :   }
    3543             :   return 0;
    3544             : }
    3545             : 
    3546           0 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3547           0 :   switch (VT.SimpleTy) {
    3548           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3549           0 :   case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3550           0 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3551             :   default: return 0;
    3552             :   }
    3553             : }
    3554             : 
    3555             : // FastEmit functions for ISD::FADD.
    3556             : 
    3557             : unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3558           0 :   if (RetVT.SimpleTy != MVT::f16)
    3559             :     return 0;
    3560           0 :   if ((Subtarget->hasFullFP16())) {
    3561           0 :     return fastEmitInst_rr(ARM::VADDH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3562             :   }
    3563             :   return 0;
    3564             : }
    3565             : 
    3566          17 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3567          17 :   if (RetVT.SimpleTy != MVT::f32)
    3568             :     return 0;
    3569          34 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    3570          17 :     return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3571             :   }
    3572             :   return 0;
    3573             : }
    3574             : 
    3575          15 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3576          15 :   if (RetVT.SimpleTy != MVT::f64)
    3577             :     return 0;
    3578          15 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3579          14 :     return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3580             :   }
    3581             :   return 0;
    3582             : }
    3583             : 
    3584           0 : unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3585           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3586             :     return 0;
    3587           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3588           0 :     return fastEmitInst_rr(ARM::VADDhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3589             :   }
    3590             :   return 0;
    3591             : }
    3592             : 
    3593           0 : unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3594           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3595             :     return 0;
    3596           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3597           0 :     return fastEmitInst_rr(ARM::VADDhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3598             :   }
    3599             :   return 0;
    3600             : }
    3601             : 
    3602             : unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3603           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3604             :     return 0;
    3605           0 :   if ((Subtarget->hasNEON())) {
    3606           0 :     return fastEmitInst_rr(ARM::VADDfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3607             :   }
    3608             :   return 0;
    3609             : }
    3610             : 
    3611             : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3612           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3613             :     return 0;
    3614           0 :   if ((Subtarget->hasNEON())) {
    3615           0 :     return fastEmitInst_rr(ARM::VADDfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3616             :   }
    3617             :   return 0;
    3618             : }
    3619             : 
    3620          33 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3621          33 :   switch (VT.SimpleTy) {
    3622           0 :   case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3623          17 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3624          15 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3625           0 :   case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3626           0 :   case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3627           0 :   case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3628           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3629             :   default: return 0;
    3630             :   }
    3631             : }
    3632             : 
    3633             : // FastEmit functions for ISD::FDIV.
    3634             : 
    3635             : unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3636           0 :   if (RetVT.SimpleTy != MVT::f16)
    3637             :     return 0;
    3638           0 :   if ((Subtarget->hasFullFP16())) {
    3639           0 :     return fastEmitInst_rr(ARM::VDIVH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3640             :   }
    3641             :   return 0;
    3642             : }
    3643             : 
    3644             : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3645           0 :   if (RetVT.SimpleTy != MVT::f32)
    3646             :     return 0;
    3647           0 :   if ((Subtarget->hasVFP2())) {
    3648           0 :     return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3649             :   }
    3650             :   return 0;
    3651             : }
    3652             : 
    3653           0 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3654           0 :   if (RetVT.SimpleTy != MVT::f64)
    3655             :     return 0;
    3656           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3657           0 :     return fastEmitInst_rr(ARM::VDIVD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3658             :   }
    3659             :   return 0;
    3660             : }
    3661             : 
    3662           0 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3663           0 :   switch (VT.SimpleTy) {
    3664           0 :   case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3665           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3666           0 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3667             :   default: return 0;
    3668             :   }
    3669             : }
    3670             : 
    3671             : // FastEmit functions for ISD::FMAXNAN.
    3672             : 
    3673           0 : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3674           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3675             :     return 0;
    3676           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3677           0 :     return fastEmitInst_rr(ARM::VMAXhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3678             :   }
    3679             :   return 0;
    3680             : }
    3681             : 
    3682           0 : unsigned fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3683           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3684             :     return 0;
    3685           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3686           0 :     return fastEmitInst_rr(ARM::VMAXhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3687             :   }
    3688             :   return 0;
    3689             : }
    3690             : 
    3691             : unsigned fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3692           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3693             :     return 0;
    3694           0 :   if ((Subtarget->hasNEON())) {
    3695           0 :     return fastEmitInst_rr(ARM::VMAXfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3696             :   }
    3697             :   return 0;
    3698             : }
    3699             : 
    3700             : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3701           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3702             :     return 0;
    3703           0 :   if ((Subtarget->hasNEON())) {
    3704           0 :     return fastEmitInst_rr(ARM::VMAXfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3705             :   }
    3706             :   return 0;
    3707             : }
    3708             : 
    3709           0 : unsigned fastEmit_ISD_FMAXNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3710           0 :   switch (VT.SimpleTy) {
    3711           0 :   case MVT::v4f16: return fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3712           0 :   case MVT::v8f16: return fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3713           0 :   case MVT::v2f32: return fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3714           0 :   case MVT::v4f32: return fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3715             :   default: return 0;
    3716             :   }
    3717             : }
    3718             : 
    3719             : // FastEmit functions for ISD::FMAXNUM.
    3720             : 
    3721             : unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3722           0 :   if (RetVT.SimpleTy != MVT::f16)
    3723             :     return 0;
    3724           0 :   if ((Subtarget->hasFullFP16())) {
    3725           0 :     return fastEmitInst_rr(ARM::VMAXNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3726             :   }
    3727             :   return 0;
    3728             : }
    3729             : 
    3730             : unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3731           0 :   if (RetVT.SimpleTy != MVT::f32)
    3732             :     return 0;
    3733           0 :   if ((Subtarget->hasFPARMv8())) {
    3734           0 :     return fastEmitInst_rr(ARM::VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3735             :   }
    3736             :   return 0;
    3737             : }
    3738             : 
    3739           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3740           0 :   if (RetVT.SimpleTy != MVT::f64)
    3741             :     return 0;
    3742           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    3743           0 :     return fastEmitInst_rr(ARM::VMAXNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3744             :   }
    3745             :   return 0;
    3746             : }
    3747             : 
    3748           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3749           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3750             :     return 0;
    3751           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3752           0 :     return fastEmitInst_rr(ARM::VMAXNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3753             :   }
    3754             :   return 0;
    3755             : }
    3756             : 
    3757           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3758           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3759             :     return 0;
    3760           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3761           0 :     return fastEmitInst_rr(ARM::VMAXNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3762             :   }
    3763             :   return 0;
    3764             : }
    3765             : 
    3766           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3767           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3768             :     return 0;
    3769           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3770           0 :     return fastEmitInst_rr(ARM::VMAXNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3771             :   }
    3772             :   return 0;
    3773             : }
    3774             : 
    3775           0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3776           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3777             :     return 0;
    3778           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3779           0 :     return fastEmitInst_rr(ARM::VMAXNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3780             :   }
    3781             :   return 0;
    3782             : }
    3783             : 
    3784           0 : unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3785           0 :   switch (VT.SimpleTy) {
    3786           0 :   case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3787           0 :   case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3788           0 :   case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3789           0 :   case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3790           0 :   case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3791           0 :   case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3792           0 :   case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3793             :   default: return 0;
    3794             :   }
    3795             : }
    3796             : 
    3797             : // FastEmit functions for ISD::FMINNAN.
    3798             : 
    3799           0 : unsigned fastEmit_ISD_FMINNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3800           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3801             :     return 0;
    3802           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3803           0 :     return fastEmitInst_rr(ARM::VMINhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3804             :   }
    3805             :   return 0;
    3806             : }
    3807             : 
    3808           0 : unsigned fastEmit_ISD_FMINNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3809           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3810             :     return 0;
    3811           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3812           0 :     return fastEmitInst_rr(ARM::VMINhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3813             :   }
    3814             :   return 0;
    3815             : }
    3816             : 
    3817             : unsigned fastEmit_ISD_FMINNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3818           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3819             :     return 0;
    3820           0 :   if ((Subtarget->hasNEON())) {
    3821           0 :     return fastEmitInst_rr(ARM::VMINfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3822             :   }
    3823             :   return 0;
    3824             : }
    3825             : 
    3826             : unsigned fastEmit_ISD_FMINNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3827           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3828             :     return 0;
    3829           0 :   if ((Subtarget->hasNEON())) {
    3830           0 :     return fastEmitInst_rr(ARM::VMINfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3831             :   }
    3832             :   return 0;
    3833             : }
    3834             : 
    3835           0 : unsigned fastEmit_ISD_FMINNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3836           0 :   switch (VT.SimpleTy) {
    3837           0 :   case MVT::v4f16: return fastEmit_ISD_FMINNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3838           0 :   case MVT::v8f16: return fastEmit_ISD_FMINNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3839           0 :   case MVT::v2f32: return fastEmit_ISD_FMINNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3840           0 :   case MVT::v4f32: return fastEmit_ISD_FMINNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3841             :   default: return 0;
    3842             :   }
    3843             : }
    3844             : 
    3845             : // FastEmit functions for ISD::FMINNUM.
    3846             : 
    3847             : unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3848           0 :   if (RetVT.SimpleTy != MVT::f16)
    3849             :     return 0;
    3850           0 :   if ((Subtarget->hasFullFP16())) {
    3851           0 :     return fastEmitInst_rr(ARM::VMINNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3852             :   }
    3853             :   return 0;
    3854             : }
    3855             : 
    3856             : unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3857           0 :   if (RetVT.SimpleTy != MVT::f32)
    3858             :     return 0;
    3859           0 :   if ((Subtarget->hasFPARMv8())) {
    3860           0 :     return fastEmitInst_rr(ARM::VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3861             :   }
    3862             :   return 0;
    3863             : }
    3864             : 
    3865           0 : unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3866           0 :   if (RetVT.SimpleTy != MVT::f64)
    3867             :     return 0;
    3868           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
    3869           0 :     return fastEmitInst_rr(ARM::VMINNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3870             :   }
    3871             :   return 0;
    3872             : }
    3873             : 
    3874           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3875           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3876             :     return 0;
    3877           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3878           0 :     return fastEmitInst_rr(ARM::VMINNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3879             :   }
    3880             :   return 0;
    3881             : }
    3882             : 
    3883           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3884           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3885             :     return 0;
    3886           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3887           0 :     return fastEmitInst_rr(ARM::VMINNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3888             :   }
    3889             :   return 0;
    3890             : }
    3891             : 
    3892           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3893           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3894             :     return 0;
    3895           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3896           0 :     return fastEmitInst_rr(ARM::VMINNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3897             :   }
    3898             :   return 0;
    3899             : }
    3900             : 
    3901           0 : unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3902           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3903             :     return 0;
    3904           0 :   if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
    3905           0 :     return fastEmitInst_rr(ARM::VMINNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3906             :   }
    3907             :   return 0;
    3908             : }
    3909             : 
    3910           0 : unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3911           0 :   switch (VT.SimpleTy) {
    3912           0 :   case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3913           0 :   case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3914           0 :   case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3915           0 :   case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3916           0 :   case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3917           0 :   case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3918           0 :   case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3919             :   default: return 0;
    3920             :   }
    3921             : }
    3922             : 
    3923             : // FastEmit functions for ISD::FMUL.
    3924             : 
    3925             : unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3926           0 :   if (RetVT.SimpleTy != MVT::f16)
    3927             :     return 0;
    3928           0 :   if ((Subtarget->hasFullFP16())) {
    3929           0 :     return fastEmitInst_rr(ARM::VMULH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3930             :   }
    3931             :   return 0;
    3932             : }
    3933             : 
    3934           1 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3935           1 :   if (RetVT.SimpleTy != MVT::f32)
    3936             :     return 0;
    3937           2 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    3938           1 :     return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3939             :   }
    3940             :   return 0;
    3941             : }
    3942             : 
    3943           0 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3944           0 :   if (RetVT.SimpleTy != MVT::f64)
    3945             :     return 0;
    3946           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    3947           0 :     return fastEmitInst_rr(ARM::VMULD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3948             :   }
    3949             :   return 0;
    3950             : }
    3951             : 
    3952           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3953           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    3954             :     return 0;
    3955           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3956           0 :     return fastEmitInst_rr(ARM::VMULhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3957             :   }
    3958             :   return 0;
    3959             : }
    3960             : 
    3961           0 : unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3962           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    3963             :     return 0;
    3964           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    3965           0 :     return fastEmitInst_rr(ARM::VMULhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3966             :   }
    3967             :   return 0;
    3968             : }
    3969             : 
    3970             : unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3971           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    3972             :     return 0;
    3973           0 :   if ((Subtarget->hasNEON())) {
    3974           0 :     return fastEmitInst_rr(ARM::VMULfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3975             :   }
    3976             :   return 0;
    3977             : }
    3978             : 
    3979             : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3980           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3981             :     return 0;
    3982           0 :   if ((Subtarget->hasNEON())) {
    3983           0 :     return fastEmitInst_rr(ARM::VMULfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3984             :   }
    3985             :   return 0;
    3986             : }
    3987             : 
    3988           1 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3989           1 :   switch (VT.SimpleTy) {
    3990           0 :   case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3991           1 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3992           0 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3993           0 :   case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3994           0 :   case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3995           0 :   case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3996           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3997             :   default: return 0;
    3998             :   }
    3999             : }
    4000             : 
    4001             : // FastEmit functions for ISD::FSUB.
    4002             : 
    4003             : unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4004           0 :   if (RetVT.SimpleTy != MVT::f16)
    4005             :     return 0;
    4006           0 :   if ((Subtarget->hasFullFP16())) {
    4007           0 :     return fastEmitInst_rr(ARM::VSUBH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4008             :   }
    4009             :   return 0;
    4010             : }
    4011             : 
    4012           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4013           0 :   if (RetVT.SimpleTy != MVT::f32)
    4014             :     return 0;
    4015           0 :   if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
    4016           0 :     return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4017             :   }
    4018             :   return 0;
    4019             : }
    4020             : 
    4021           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4022           0 :   if (RetVT.SimpleTy != MVT::f64)
    4023             :     return 0;
    4024           0 :   if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
    4025           0 :     return fastEmitInst_rr(ARM::VSUBD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4026             :   }
    4027             :   return 0;
    4028             : }
    4029             : 
    4030           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4031           0 :   if (RetVT.SimpleTy != MVT::v4f16)
    4032             :     return 0;
    4033           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    4034           0 :     return fastEmitInst_rr(ARM::VSUBhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4035             :   }
    4036             :   return 0;
    4037             : }
    4038             : 
    4039           0 : unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4040           0 :   if (RetVT.SimpleTy != MVT::v8f16)
    4041             :     return 0;
    4042           0 :   if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
    4043           0 :     return fastEmitInst_rr(ARM::VSUBhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4044             :   }
    4045             :   return 0;
    4046             : }
    4047             : 
    4048             : unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4049           0 :   if (RetVT.SimpleTy != MVT::v2f32)
    4050             :     return 0;
    4051           0 :   if ((Subtarget->hasNEON())) {
    4052           0 :     return fastEmitInst_rr(ARM::VSUBfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4053             :   }
    4054             :   return 0;
    4055             : }
    4056             : 
    4057             : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4058           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    4059             :     return 0;
    4060           0 :   if ((Subtarget->hasNEON())) {
    4061           0 :     return fastEmitInst_rr(ARM::VSUBfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4062             :   }
    4063             :   return 0;
    4064             : }
    4065             : 
    4066           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4067           0 :   switch (VT.SimpleTy) {
    4068           0 :   case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4069           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4070           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4071           0 :   case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4072           0 :   case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4073           0 :   case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4074           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4075             :   default: return 0;
    4076             :   }
    4077             : }
    4078             : 
    4079             : // FastEmit functions for ISD::MUL.
    4080             : 
    4081           3 : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4082           3 :   if (RetVT.SimpleTy != MVT::i32)
    4083             :     return 0;
    4084           3 :   if ((Subtarget->isThumb2())) {
    4085           3 :     return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4086             :   }
    4087           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4088           0 :     return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4089             :   }
    4090           0 :   if ((!Subtarget->isThumb()) && (!Subtarget->hasV6Ops()) && (Subtarget->useMulOps())) {
    4091           0 :     return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4092             :   }
    4093           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    4094           0 :     return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4095             :   }
    4096             :   return 0;
    4097             : }
    4098             : 
    4099             : unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4100           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4101             :     return 0;
    4102           0 :   if ((Subtarget->hasNEON())) {
    4103           0 :     return fastEmitInst_rr(ARM::VMULv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4104             :   }
    4105             :   return 0;
    4106             : }
    4107             : 
    4108             : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4109           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4110             :     return 0;
    4111           0 :   if ((Subtarget->hasNEON())) {
    4112           0 :     return fastEmitInst_rr(ARM::VMULv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4113             :   }
    4114             :   return 0;
    4115             : }
    4116             : 
    4117             : unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4118           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4119             :     return 0;
    4120           0 :   if ((Subtarget->hasNEON())) {
    4121           0 :     return fastEmitInst_rr(ARM::VMULv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4122             :   }
    4123             :   return 0;
    4124             : }
    4125             : 
    4126             : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4127           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4128             :     return 0;
    4129           0 :   if ((Subtarget->hasNEON())) {
    4130           0 :     return fastEmitInst_rr(ARM::VMULv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4131             :   }
    4132             :   return 0;
    4133             : }
    4134             : 
    4135             : unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4136           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4137             :     return 0;
    4138           0 :   if ((Subtarget->hasNEON())) {
    4139           0 :     return fastEmitInst_rr(ARM::VMULv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4140             :   }
    4141             :   return 0;
    4142             : }
    4143             : 
    4144             : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4145           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4146             :     return 0;
    4147           0 :   if ((Subtarget->hasNEON())) {
    4148           0 :     return fastEmitInst_rr(ARM::VMULv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4149             :   }
    4150             :   return 0;
    4151             : }
    4152             : 
    4153           3 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4154           3 :   switch (VT.SimpleTy) {
    4155           3 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4156           0 :   case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4157           0 :   case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4158           0 :   case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4159           0 :   case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4160           0 :   case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4161           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4162             :   default: return 0;
    4163             :   }
    4164             : }
    4165             : 
    4166             : // FastEmit functions for ISD::MULHS.
    4167             : 
    4168           0 : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4169           0 :   if (RetVT.SimpleTy != MVT::i32)
    4170             :     return 0;
    4171           0 :   if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
    4172           0 :     return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4173             :   }
    4174           0 :   if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
    4175           0 :     return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4176             :   }
    4177             :   return 0;
    4178             : }
    4179             : 
    4180             : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4181           0 :   switch (VT.SimpleTy) {
    4182           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4183             :   default: return 0;
    4184             :   }
    4185             : }
    4186             : 
    4187             : // FastEmit functions for ISD::OR.
    4188             : 
    4189           3 : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4190           3 :   if (RetVT.SimpleTy != MVT::i32)
    4191             :     return 0;
    4192           3 :   if ((Subtarget->isThumb2())) {
    4193           1 :     return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4194             :   }
    4195           2 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4196           0 :     return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4197             :   }
    4198           2 :   if ((!Subtarget->isThumb())) {
    4199           2 :     return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4200             :   }
    4201             :   return 0;
    4202             : }
    4203             : 
    4204             : unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4205           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4206             :     return 0;
    4207           0 :   if ((Subtarget->hasNEON())) {
    4208           0 :     return fastEmitInst_rr(ARM::VORRd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4209             :   }
    4210             :   return 0;
    4211             : }
    4212             : 
    4213             : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4214           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4215             :     return 0;
    4216           0 :   if ((Subtarget->hasNEON())) {
    4217           0 :     return fastEmitInst_rr(ARM::VORRq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4218             :   }
    4219             :   return 0;
    4220             : }
    4221             : 
    4222           3 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4223           3 :   switch (VT.SimpleTy) {
    4224           3 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4225           0 :   case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4226           0 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4227             :   default: return 0;
    4228             :   }
    4229             : }
    4230             : 
    4231             : // FastEmit functions for ISD::ROTR.
    4232             : 
    4233           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4234           0 :   if (RetVT.SimpleTy != MVT::i32)
    4235             :     return 0;
    4236           0 :   if ((Subtarget->isThumb2())) {
    4237           0 :     return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4238             :   }
    4239           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4240           0 :     return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4241             :   }
    4242             :   return 0;
    4243             : }
    4244             : 
    4245             : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4246           0 :   switch (VT.SimpleTy) {
    4247           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4248             :   default: return 0;
    4249             :   }
    4250             : }
    4251             : 
    4252             : // FastEmit functions for ISD::SDIV.
    4253             : 
    4254           4 : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4255           4 :   if (RetVT.SimpleTy != MVT::i32)
    4256             :     return 0;
    4257           4 :   if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) {
    4258           0 :     return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4259             :   }
    4260           4 :   if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) {
    4261           0 :     return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4262             :   }
    4263             :   return 0;
    4264             : }
    4265             : 
    4266             : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4267           4 :   switch (VT.SimpleTy) {
    4268           4 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4269             :   default: return 0;
    4270             :   }
    4271             : }
    4272             : 
    4273             : // FastEmit functions for ISD::SHL.
    4274             : 
    4275           5 : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4276           5 :   if (RetVT.SimpleTy != MVT::i32)
    4277             :     return 0;
    4278           5 :   if ((Subtarget->isThumb2())) {
    4279           0 :     return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4280             :   }
    4281           5 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4282           0 :     return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4283             :   }
    4284             :   return 0;
    4285             : }
    4286             : 
    4287             : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4288           5 :   switch (VT.SimpleTy) {
    4289           5 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4290             :   default: return 0;
    4291             :   }
    4292             : }
    4293             : 
    4294             : // FastEmit functions for ISD::SMAX.
    4295             : 
    4296             : unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4297           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4298             :     return 0;
    4299           0 :   if ((Subtarget->hasNEON())) {
    4300           0 :     return fastEmitInst_rr(ARM::VMAXsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4301             :   }
    4302             :   return 0;
    4303             : }
    4304             : 
    4305             : unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4306           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4307             :     return 0;
    4308           0 :   if ((Subtarget->hasNEON())) {
    4309           0 :     return fastEmitInst_rr(ARM::VMAXsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4310             :   }
    4311             :   return 0;
    4312             : }
    4313             : 
    4314             : unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4315           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4316             :     return 0;
    4317           0 :   if ((Subtarget->hasNEON())) {
    4318           0 :     return fastEmitInst_rr(ARM::VMAXsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4319             :   }
    4320             :   return 0;
    4321             : }
    4322             : 
    4323             : unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4324           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4325             :     return 0;
    4326           0 :   if ((Subtarget->hasNEON())) {
    4327           0 :     return fastEmitInst_rr(ARM::VMAXsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4328             :   }
    4329             :   return 0;
    4330             : }
    4331             : 
    4332             : unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4333           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4334             :     return 0;
    4335           0 :   if ((Subtarget->hasNEON())) {
    4336           0 :     return fastEmitInst_rr(ARM::VMAXsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4337             :   }
    4338             :   return 0;
    4339             : }
    4340             : 
    4341             : unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4342           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4343             :     return 0;
    4344           0 :   if ((Subtarget->hasNEON())) {
    4345           0 :     return fastEmitInst_rr(ARM::VMAXsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4346             :   }
    4347             :   return 0;
    4348             : }
    4349             : 
    4350           0 : unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4351           0 :   switch (VT.SimpleTy) {
    4352           0 :   case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4353           0 :   case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4354           0 :   case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4355           0 :   case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4356           0 :   case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4357           0 :   case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4358             :   default: return 0;
    4359             :   }
    4360             : }
    4361             : 
    4362             : // FastEmit functions for ISD::SMIN.
    4363             : 
    4364             : unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4365           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4366             :     return 0;
    4367           0 :   if ((Subtarget->hasNEON())) {
    4368           0 :     return fastEmitInst_rr(ARM::VMINsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4369             :   }
    4370             :   return 0;
    4371             : }
    4372             : 
    4373             : unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4374           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4375             :     return 0;
    4376           0 :   if ((Subtarget->hasNEON())) {
    4377           0 :     return fastEmitInst_rr(ARM::VMINsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4378             :   }
    4379             :   return 0;
    4380             : }
    4381             : 
    4382             : unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4383           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4384             :     return 0;
    4385           0 :   if ((Subtarget->hasNEON())) {
    4386           0 :     return fastEmitInst_rr(ARM::VMINsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4387             :   }
    4388             :   return 0;
    4389             : }
    4390             : 
    4391             : unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4392           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4393             :     return 0;
    4394           0 :   if ((Subtarget->hasNEON())) {
    4395           0 :     return fastEmitInst_rr(ARM::VMINsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4396             :   }
    4397             :   return 0;
    4398             : }
    4399             : 
    4400             : unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4401           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4402             :     return 0;
    4403           0 :   if ((Subtarget->hasNEON())) {
    4404           0 :     return fastEmitInst_rr(ARM::VMINsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4405             :   }
    4406             :   return 0;
    4407             : }
    4408             : 
    4409             : unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4410           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4411             :     return 0;
    4412           0 :   if ((Subtarget->hasNEON())) {
    4413           0 :     return fastEmitInst_rr(ARM::VMINsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4414             :   }
    4415             :   return 0;
    4416             : }
    4417             : 
    4418           0 : unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4419           0 :   switch (VT.SimpleTy) {
    4420           0 :   case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4421           0 :   case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4422           0 :   case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4423           0 :   case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4424           0 :   case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4425           0 :   case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4426             :   default: return 0;
    4427             :   }
    4428             : }
    4429             : 
    4430             : // FastEmit functions for ISD::SRA.
    4431             : 
    4432           4 : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4433           4 :   if (RetVT.SimpleTy != MVT::i32)
    4434             :     return 0;
    4435           4 :   if ((Subtarget->isThumb2())) {
    4436           0 :     return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4437             :   }
    4438           4 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4439           0 :     return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4440             :   }
    4441             :   return 0;
    4442             : }
    4443             : 
    4444             : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4445           4 :   switch (VT.SimpleTy) {
    4446           4 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4447             :   default: return 0;
    4448             :   }
    4449             : }
    4450             : 
    4451             : // FastEmit functions for ISD::SRL.
    4452             : 
    4453           6 : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4454           6 :   if (RetVT.SimpleTy != MVT::i32)
    4455             :     return 0;
    4456           6 :   if ((Subtarget->isThumb2())) {
    4457           2 :     return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4458             :   }
    4459           4 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4460           0 :     return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4461             :   }
    4462             :   return 0;
    4463             : }
    4464             : 
    4465             : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4466           6 :   switch (VT.SimpleTy) {
    4467           6 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4468             :   default: return 0;
    4469             :   }
    4470             : }
    4471             : 
    4472             : // FastEmit functions for ISD::SUB.
    4473             : 
    4474           3 : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4475           3 :   if (RetVT.SimpleTy != MVT::i32)
    4476             :     return 0;
    4477           3 :   if ((Subtarget->isThumb2())) {
    4478           1 :     return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4479             :   }
    4480           2 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4481           0 :     return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4482             :   }
    4483           2 :   if ((!Subtarget->isThumb())) {
    4484           2 :     return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4485             :   }
    4486             :   return 0;
    4487             : }
    4488             : 
    4489             : unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4490           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4491             :     return 0;
    4492           0 :   if ((Subtarget->hasNEON())) {
    4493           0 :     return fastEmitInst_rr(ARM::VSUBv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4494             :   }
    4495             :   return 0;
    4496             : }
    4497             : 
    4498             : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4499           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4500             :     return 0;
    4501           0 :   if ((Subtarget->hasNEON())) {
    4502           0 :     return fastEmitInst_rr(ARM::VSUBv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4503             :   }
    4504             :   return 0;
    4505             : }
    4506             : 
    4507             : unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4508           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4509             :     return 0;
    4510           0 :   if ((Subtarget->hasNEON())) {
    4511           0 :     return fastEmitInst_rr(ARM::VSUBv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4512             :   }
    4513             :   return 0;
    4514             : }
    4515             : 
    4516             : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4517           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4518             :     return 0;
    4519           0 :   if ((Subtarget->hasNEON())) {
    4520           0 :     return fastEmitInst_rr(ARM::VSUBv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4521             :   }
    4522             :   return 0;
    4523             : }
    4524             : 
    4525             : unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4526           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4527             :     return 0;
    4528           0 :   if ((Subtarget->hasNEON())) {
    4529           0 :     return fastEmitInst_rr(ARM::VSUBv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4530             :   }
    4531             :   return 0;
    4532             : }
    4533             : 
    4534             : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4535           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4536             :     return 0;
    4537           0 :   if ((Subtarget->hasNEON())) {
    4538           0 :     return fastEmitInst_rr(ARM::VSUBv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4539             :   }
    4540             :   return 0;
    4541             : }
    4542             : 
    4543             : unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4544           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    4545             :     return 0;
    4546           0 :   if ((Subtarget->hasNEON())) {
    4547           0 :     return fastEmitInst_rr(ARM::VSUBv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4548             :   }
    4549             :   return 0;
    4550             : }
    4551             : 
    4552             : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4553           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    4554             :     return 0;
    4555           0 :   if ((Subtarget->hasNEON())) {
    4556           0 :     return fastEmitInst_rr(ARM::VSUBv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4557             :   }
    4558             :   return 0;
    4559             : }
    4560             : 
    4561           3 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4562           3 :   switch (VT.SimpleTy) {
    4563           3 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4564           0 :   case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4565           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4566           0 :   case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4567           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4568           0 :   case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4569           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4570           0 :   case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4571           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4572             :   default: return 0;
    4573             :   }
    4574             : }
    4575             : 
    4576             : // FastEmit functions for ISD::UDIV.
    4577             : 
    4578          10 : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4579          10 :   if (RetVT.SimpleTy != MVT::i32)
    4580             :     return 0;
    4581          10 :   if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) {
    4582           0 :     return fastEmitInst_rr(ARM::t2UDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4583             :   }
    4584          10 :   if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) {
    4585           0 :     return fastEmitInst_rr(ARM::UDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4586             :   }
    4587             :   return 0;
    4588             : }
    4589             : 
    4590             : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4591          10 :   switch (VT.SimpleTy) {
    4592          10 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4593             :   default: return 0;
    4594             :   }
    4595             : }
    4596             : 
    4597             : // FastEmit functions for ISD::UMAX.
    4598             : 
    4599             : unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4600           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4601             :     return 0;
    4602           0 :   if ((Subtarget->hasNEON())) {
    4603           0 :     return fastEmitInst_rr(ARM::VMAXuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4604             :   }
    4605             :   return 0;
    4606             : }
    4607             : 
    4608             : unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4609           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4610             :     return 0;
    4611           0 :   if ((Subtarget->hasNEON())) {
    4612           0 :     return fastEmitInst_rr(ARM::VMAXuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4613             :   }
    4614             :   return 0;
    4615             : }
    4616             : 
    4617             : unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4618           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4619             :     return 0;
    4620           0 :   if ((Subtarget->hasNEON())) {
    4621           0 :     return fastEmitInst_rr(ARM::VMAXuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4622             :   }
    4623             :   return 0;
    4624             : }
    4625             : 
    4626             : unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4627           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4628             :     return 0;
    4629           0 :   if ((Subtarget->hasNEON())) {
    4630           0 :     return fastEmitInst_rr(ARM::VMAXuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4631             :   }
    4632             :   return 0;
    4633             : }
    4634             : 
    4635             : unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4636           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4637             :     return 0;
    4638           0 :   if ((Subtarget->hasNEON())) {
    4639           0 :     return fastEmitInst_rr(ARM::VMAXuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4640             :   }
    4641             :   return 0;
    4642             : }
    4643             : 
    4644             : unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4645           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4646             :     return 0;
    4647           0 :   if ((Subtarget->hasNEON())) {
    4648           0 :     return fastEmitInst_rr(ARM::VMAXuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4649             :   }
    4650             :   return 0;
    4651             : }
    4652             : 
    4653           0 : unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4654           0 :   switch (VT.SimpleTy) {
    4655           0 :   case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4656           0 :   case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4657           0 :   case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4658           0 :   case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4659           0 :   case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4660           0 :   case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4661             :   default: return 0;
    4662             :   }
    4663             : }
    4664             : 
    4665             : // FastEmit functions for ISD::UMIN.
    4666             : 
    4667             : unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4668           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4669             :     return 0;
    4670           0 :   if ((Subtarget->hasNEON())) {
    4671           0 :     return fastEmitInst_rr(ARM::VMINuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4672             :   }
    4673             :   return 0;
    4674             : }
    4675             : 
    4676             : unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4677           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4678             :     return 0;
    4679           0 :   if ((Subtarget->hasNEON())) {
    4680           0 :     return fastEmitInst_rr(ARM::VMINuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4681             :   }
    4682             :   return 0;
    4683             : }
    4684             : 
    4685             : unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4686           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4687             :     return 0;
    4688           0 :   if ((Subtarget->hasNEON())) {
    4689           0 :     return fastEmitInst_rr(ARM::VMINuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4690             :   }
    4691             :   return 0;
    4692             : }
    4693             : 
    4694             : unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4695           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4696             :     return 0;
    4697           0 :   if ((Subtarget->hasNEON())) {
    4698           0 :     return fastEmitInst_rr(ARM::VMINuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4699             :   }
    4700             :   return 0;
    4701             : }
    4702             : 
    4703             : unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4704           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4705             :     return 0;
    4706           0 :   if ((Subtarget->hasNEON())) {
    4707           0 :     return fastEmitInst_rr(ARM::VMINuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4708             :   }
    4709             :   return 0;
    4710             : }
    4711             : 
    4712             : unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4713           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4714             :     return 0;
    4715           0 :   if ((Subtarget->hasNEON())) {
    4716           0 :     return fastEmitInst_rr(ARM::VMINuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4717             :   }
    4718             :   return 0;
    4719             : }
    4720             : 
    4721           0 : unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4722           0 :   switch (VT.SimpleTy) {
    4723           0 :   case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4724           0 :   case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4725           0 :   case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4726           0 :   case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4727           0 :   case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4728           0 :   case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4729             :   default: return 0;
    4730             :   }
    4731             : }
    4732             : 
    4733             : // FastEmit functions for ISD::XOR.
    4734             : 
    4735          11 : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4736          11 :   if (RetVT.SimpleTy != MVT::i32)
    4737             :     return 0;
    4738          11 :   if ((Subtarget->isThumb2())) {
    4739           8 :     return fastEmitInst_rr(ARM::t2EORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4740             :   }
    4741           3 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    4742           0 :     return fastEmitInst_rr(ARM::tEOR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4743             :   }
    4744           3 :   if ((!Subtarget->isThumb())) {
    4745           3 :     return fastEmitInst_rr(ARM::EORrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4746             :   }
    4747             :   return 0;
    4748             : }
    4749             : 
    4750             : unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4751           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4752             :     return 0;
    4753           0 :   if ((Subtarget->hasNEON())) {
    4754           0 :     return fastEmitInst_rr(ARM::VEORd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4755             :   }
    4756             :   return 0;
    4757             : }
    4758             : 
    4759             : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4760           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    4761             :     return 0;
    4762           0 :   if ((Subtarget->hasNEON())) {
    4763           0 :     return fastEmitInst_rr(ARM::VEORq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    4764             :   }
    4765             :   return 0;
    4766             : }
    4767             : 
    4768          11 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    4769          11 :   switch (VT.SimpleTy) {
    4770          11 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4771           0 :   case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4772           0 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4773             :   default: return 0;
    4774             :   }
    4775             : }
    4776             : 
    4777             : // Top-level FastEmit function.
    4778             : 
    4779         209 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    4780         209 :   switch (Opcode) {
    4781           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4782           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4783           0 :   case ARMISD::EH_SJLJ_LONGJMP: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4784           0 :   case ARMISD::EH_SJLJ_SETJMP: return fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4785           0 :   case ARMISD::SMULWB: return fastEmit_ARMISD_SMULWB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4786           0 :   case ARMISD::SMULWT: return fastEmit_ARMISD_SMULWT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4787           0 :   case ARMISD::VCEQ: return fastEmit_ARMISD_VCEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4788           0 :   case ARMISD::VCGE: return fastEmit_ARMISD_VCGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4789           0 :   case ARMISD::VCGEU: return fastEmit_ARMISD_VCGEU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4790           0 :   case ARMISD::VCGT: return fastEmit_ARMISD_VCGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4791           0 :   case ARMISD::VCGTU: return fastEmit_ARMISD_VCGTU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4792           0 :   case ARMISD::VMOVDRR: return fastEmit_ARMISD_VMOVDRR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4793           0 :   case ARMISD::VMULLs: return fastEmit_ARMISD_VMULLs_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4794           0 :   case ARMISD::VMULLu: return fastEmit_ARMISD_VMULLu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4795           0 :   case ARMISD::VTBL1: return fastEmit_ARMISD_VTBL1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4796           0 :   case ARMISD::VTST: return fastEmit_ARMISD_VTST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4797          94 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4798           0 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4799          33 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4800           0 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4801           0 :   case ISD::FMAXNAN: return fastEmit_ISD_FMAXNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4802           0 :   case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4803           0 :   case ISD::FMINNAN: return fastEmit_ISD_FMINNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4804           0 :   case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4805           1 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4806           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4807           3 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4808           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4809           3 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4810           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4811           4 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4812           5 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4813           0 :   case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4814           0 :   case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4815           4 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4816           6 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4817           3 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4818          10 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4819           0 :   case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4820           0 :   case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4821          11 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    4822             :   default: return 0;
    4823             :   }
    4824             : }
    4825             : 
    4826             : // FastEmit functions for ARMISD::PIC_ADD.
    4827             : 
    4828           0 : unsigned fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4829           0 :   if (RetVT.SimpleTy != MVT::i32)
    4830             :     return 0;
    4831           0 :   if ((Subtarget->isThumb())) {
    4832           0 :     return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4833             :   }
    4834             :   if ((!Subtarget->isThumb())) {
    4835           0 :     return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4836             :   }
    4837             :   return 0;
    4838             : }
    4839             : 
    4840             : unsigned fastEmit_ARMISD_PIC_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4841           0 :   switch (VT.SimpleTy) {
    4842           0 :   case MVT::i32: return fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4843             :   default: return 0;
    4844             :   }
    4845             : }
    4846             : 
    4847             : // FastEmit functions for ARMISD::VDUPLANE.
    4848             : 
    4849             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4850           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4851             :     return 0;
    4852           0 :   if ((Subtarget->hasNEON())) {
    4853           0 :     return fastEmitInst_ri(ARM::VDUPLN8d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4854             :   }
    4855             :   return 0;
    4856             : }
    4857             : 
    4858             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4859           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4860             :     return 0;
    4861           0 :   if ((Subtarget->hasNEON())) {
    4862           0 :     return fastEmitInst_ri(ARM::VDUPLN16d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4863             :   }
    4864             :   return 0;
    4865             : }
    4866             : 
    4867             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4868           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4869             :     return 0;
    4870           0 :   if ((Subtarget->hasNEON())) {
    4871           0 :     return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4872             :   }
    4873             :   return 0;
    4874             : }
    4875             : 
    4876             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4877           0 :   return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4878             : }
    4879             : 
    4880             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4881           0 :   return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4882             : }
    4883             : 
    4884           0 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4885           0 : switch (RetVT.SimpleTy) {
    4886           0 :   case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(Op0, Op0IsKill, imm1);
    4887           0 :   case MVT::v4f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(Op0, Op0IsKill, imm1);
    4888             :   default: return 0;
    4889             : }
    4890             : }
    4891             : 
    4892           0 : unsigned fastEmit_ARMISD_VDUPLANE_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4893           0 :   switch (VT.SimpleTy) {
    4894           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4895           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4896           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    4897           0 :   case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(RetVT, Op0, Op0IsKill, imm1);
    4898             :   default: return 0;
    4899             :   }
    4900             : }
    4901             : 
    4902             : // FastEmit functions for ARMISD::VGETLANEs.
    4903             : 
    4904             : unsigned fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4905           0 :   if (RetVT.SimpleTy != MVT::i32)
    4906             :     return 0;
    4907           0 :   if ((Subtarget->hasNEON())) {
    4908           0 :     return fastEmitInst_ri(ARM::VGETLNs8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4909             :   }
    4910             :   return 0;
    4911             : }
    4912             : 
    4913             : unsigned fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4914           0 :   if (RetVT.SimpleTy != MVT::i32)
    4915             :     return 0;
    4916           0 :   if ((Subtarget->hasNEON())) {
    4917           0 :     return fastEmitInst_ri(ARM::VGETLNs16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4918             :   }
    4919             :   return 0;
    4920             : }
    4921             : 
    4922           0 : unsigned fastEmit_ARMISD_VGETLANEs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4923           0 :   switch (VT.SimpleTy) {
    4924           0 :   case MVT::v8i8: return fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4925           0 :   case MVT::v4i16: return fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4926             :   default: return 0;
    4927             :   }
    4928             : }
    4929             : 
    4930             : // FastEmit functions for ARMISD::VGETLANEu.
    4931             : 
    4932             : unsigned fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4933           0 :   if (RetVT.SimpleTy != MVT::i32)
    4934             :     return 0;
    4935           0 :   if ((Subtarget->hasNEON())) {
    4936           0 :     return fastEmitInst_ri(ARM::VGETLNu8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4937             :   }
    4938             :   return 0;
    4939             : }
    4940             : 
    4941             : unsigned fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4942           0 :   if (RetVT.SimpleTy != MVT::i32)
    4943             :     return 0;
    4944           0 :   if ((Subtarget->hasNEON())) {
    4945           0 :     return fastEmitInst_ri(ARM::VGETLNu16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    4946             :   }
    4947             :   return 0;
    4948             : }
    4949             : 
    4950           0 : unsigned fastEmit_ARMISD_VGETLANEu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4951           0 :   switch (VT.SimpleTy) {
    4952           0 :   case MVT::v8i8: return fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    4953           0 :   case MVT::v4i16: return fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    4954             :   default: return 0;
    4955             :   }
    4956             : }
    4957             : 
    4958             : // FastEmit functions for ARMISD::VQSHLs.
    4959             : 
    4960             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4961           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    4962             :     return 0;
    4963           0 :   if ((Subtarget->hasNEON())) {
    4964           0 :     return fastEmitInst_ri(ARM::VQSHLsiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4965             :   }
    4966             :   return 0;
    4967             : }
    4968             : 
    4969             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4970           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    4971             :     return 0;
    4972           0 :   if ((Subtarget->hasNEON())) {
    4973           0 :     return fastEmitInst_ri(ARM::VQSHLsiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4974             :   }
    4975             :   return 0;
    4976             : }
    4977             : 
    4978             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4979           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    4980             :     return 0;
    4981           0 :   if ((Subtarget->hasNEON())) {
    4982           0 :     return fastEmitInst_ri(ARM::VQSHLsiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    4983             :   }
    4984             :   return 0;
    4985             : }
    4986             : 
    4987             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4988           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    4989             :     return 0;
    4990           0 :   if ((Subtarget->hasNEON())) {
    4991           0 :     return fastEmitInst_ri(ARM::VQSHLsiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    4992             :   }
    4993             :   return 0;
    4994             : }
    4995             : 
    4996             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4997           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    4998             :     return 0;
    4999           0 :   if ((Subtarget->hasNEON())) {
    5000           0 :     return fastEmitInst_ri(ARM::VQSHLsiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5001             :   }
    5002             :   return 0;
    5003             : }
    5004             : 
    5005             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5006           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5007             :     return 0;
    5008           0 :   if ((Subtarget->hasNEON())) {
    5009           0 :     return fastEmitInst_ri(ARM::VQSHLsiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5010             :   }
    5011             :   return 0;
    5012             : }
    5013             : 
    5014             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5015           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5016             :     return 0;
    5017           0 :   if ((Subtarget->hasNEON())) {
    5018           0 :     return fastEmitInst_ri(ARM::VQSHLsiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5019             :   }
    5020             :   return 0;
    5021             : }
    5022             : 
    5023             : unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5024           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5025             :     return 0;
    5026           0 :   if ((Subtarget->hasNEON())) {
    5027           0 :     return fastEmitInst_ri(ARM::VQSHLsiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5028             :   }
    5029             :   return 0;
    5030             : }
    5031             : 
    5032           0 : unsigned fastEmit_ARMISD_VQSHLs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5033           0 :   switch (VT.SimpleTy) {
    5034           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5035           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5036           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5037           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5038           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5039           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5040           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5041           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5042             :   default: return 0;
    5043             :   }
    5044             : }
    5045             : 
    5046             : // FastEmit functions for ARMISD::VQSHLsu.
    5047             : 
    5048             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5049           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5050             :     return 0;
    5051           0 :   if ((Subtarget->hasNEON())) {
    5052           0 :     return fastEmitInst_ri(ARM::VQSHLsuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5053             :   }
    5054             :   return 0;
    5055             : }
    5056             : 
    5057             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5058           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5059             :     return 0;
    5060           0 :   if ((Subtarget->hasNEON())) {
    5061           0 :     return fastEmitInst_ri(ARM::VQSHLsuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5062             :   }
    5063             :   return 0;
    5064             : }
    5065             : 
    5066             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5067           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5068             :     return 0;
    5069           0 :   if ((Subtarget->hasNEON())) {
    5070           0 :     return fastEmitInst_ri(ARM::VQSHLsuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5071             :   }
    5072             :   return 0;
    5073             : }
    5074             : 
    5075             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5076           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5077             :     return 0;
    5078           0 :   if ((Subtarget->hasNEON())) {
    5079           0 :     return fastEmitInst_ri(ARM::VQSHLsuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5080             :   }
    5081             :   return 0;
    5082             : }
    5083             : 
    5084             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5085           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5086             :     return 0;
    5087           0 :   if ((Subtarget->hasNEON())) {
    5088           0 :     return fastEmitInst_ri(ARM::VQSHLsuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5089             :   }
    5090             :   return 0;
    5091             : }
    5092             : 
    5093             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5094           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5095             :     return 0;
    5096           0 :   if ((Subtarget->hasNEON())) {
    5097           0 :     return fastEmitInst_ri(ARM::VQSHLsuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5098             :   }
    5099             :   return 0;
    5100             : }
    5101             : 
    5102             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5103           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5104             :     return 0;
    5105           0 :   if ((Subtarget->hasNEON())) {
    5106           0 :     return fastEmitInst_ri(ARM::VQSHLsuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5107             :   }
    5108             :   return 0;
    5109             : }
    5110             : 
    5111             : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5112           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5113             :     return 0;
    5114           0 :   if ((Subtarget->hasNEON())) {
    5115           0 :     return fastEmitInst_ri(ARM::VQSHLsuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5116             :   }
    5117             :   return 0;
    5118             : }
    5119             : 
    5120           0 : unsigned fastEmit_ARMISD_VQSHLsu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5121           0 :   switch (VT.SimpleTy) {
    5122           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5123           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5124           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5125           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5126           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5127           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5128           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5129           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5130             :   default: return 0;
    5131             :   }
    5132             : }
    5133             : 
    5134             : // FastEmit functions for ARMISD::VQSHLu.
    5135             : 
    5136             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5137           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5138             :     return 0;
    5139           0 :   if ((Subtarget->hasNEON())) {
    5140           0 :     return fastEmitInst_ri(ARM::VQSHLuiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5141             :   }
    5142             :   return 0;
    5143             : }
    5144             : 
    5145             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5146           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5147             :     return 0;
    5148           0 :   if ((Subtarget->hasNEON())) {
    5149           0 :     return fastEmitInst_ri(ARM::VQSHLuiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5150             :   }
    5151             :   return 0;
    5152             : }
    5153             : 
    5154             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5155           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5156             :     return 0;
    5157           0 :   if ((Subtarget->hasNEON())) {
    5158           0 :     return fastEmitInst_ri(ARM::VQSHLuiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5159             :   }
    5160             :   return 0;
    5161             : }
    5162             : 
    5163             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5164           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5165             :     return 0;
    5166           0 :   if ((Subtarget->hasNEON())) {
    5167           0 :     return fastEmitInst_ri(ARM::VQSHLuiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5168             :   }
    5169             :   return 0;
    5170             : }
    5171             : 
    5172             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5173           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5174             :     return 0;
    5175           0 :   if ((Subtarget->hasNEON())) {
    5176           0 :     return fastEmitInst_ri(ARM::VQSHLuiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5177             :   }
    5178             :   return 0;
    5179             : }
    5180             : 
    5181             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5182           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5183             :     return 0;
    5184           0 :   if ((Subtarget->hasNEON())) {
    5185           0 :     return fastEmitInst_ri(ARM::VQSHLuiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5186             :   }
    5187             :   return 0;
    5188             : }
    5189             : 
    5190             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5191           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5192             :     return 0;
    5193           0 :   if ((Subtarget->hasNEON())) {
    5194           0 :     return fastEmitInst_ri(ARM::VQSHLuiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5195             :   }
    5196             :   return 0;
    5197             : }
    5198             : 
    5199             : unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5200           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5201             :     return 0;
    5202           0 :   if ((Subtarget->hasNEON())) {
    5203           0 :     return fastEmitInst_ri(ARM::VQSHLuiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5204             :   }
    5205             :   return 0;
    5206             : }
    5207             : 
    5208           0 : unsigned fastEmit_ARMISD_VQSHLu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5209           0 :   switch (VT.SimpleTy) {
    5210           0 :   case MVT::v8i8: return fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5211           0 :   case MVT::v16i8: return fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5212           0 :   case MVT::v4i16: return fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5213           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5214           0 :   case MVT::v2i32: return fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5215           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5216           0 :   case MVT::v1i64: return fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5217           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5218             :   default: return 0;
    5219             :   }
    5220             : }
    5221             : 
    5222             : // FastEmit functions for ARMISD::VRSHRs.
    5223             : 
    5224             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5225           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5226             :     return 0;
    5227           0 :   if ((Subtarget->hasNEON())) {
    5228           0 :     return fastEmitInst_ri(ARM::VRSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5229             :   }
    5230             :   return 0;
    5231             : }
    5232             : 
    5233             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5234           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5235             :     return 0;
    5236           0 :   if ((Subtarget->hasNEON())) {
    5237           0 :     return fastEmitInst_ri(ARM::VRSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5238             :   }
    5239             :   return 0;
    5240             : }
    5241             : 
    5242             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5243           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5244             :     return 0;
    5245           0 :   if ((Subtarget->hasNEON())) {
    5246           0 :     return fastEmitInst_ri(ARM::VRSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5247             :   }
    5248             :   return 0;
    5249             : }
    5250             : 
    5251             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5252           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5253             :     return 0;
    5254           0 :   if ((Subtarget->hasNEON())) {
    5255           0 :     return fastEmitInst_ri(ARM::VRSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5256             :   }
    5257             :   return 0;
    5258             : }
    5259             : 
    5260             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5261           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5262             :     return 0;
    5263           0 :   if ((Subtarget->hasNEON())) {
    5264           0 :     return fastEmitInst_ri(ARM::VRSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5265             :   }
    5266             :   return 0;
    5267             : }
    5268             : 
    5269             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5270           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5271             :     return 0;
    5272           0 :   if ((Subtarget->hasNEON())) {
    5273           0 :     return fastEmitInst_ri(ARM::VRSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5274             :   }
    5275             :   return 0;
    5276             : }
    5277             : 
    5278             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5279           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5280             :     return 0;
    5281           0 :   if ((Subtarget->hasNEON())) {
    5282           0 :     return fastEmitInst_ri(ARM::VRSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5283             :   }
    5284             :   return 0;
    5285             : }
    5286             : 
    5287             : unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5288           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5289             :     return 0;
    5290           0 :   if ((Subtarget->hasNEON())) {
    5291           0 :     return fastEmitInst_ri(ARM::VRSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5292             :   }
    5293             :   return 0;
    5294             : }
    5295             : 
    5296           0 : unsigned fastEmit_ARMISD_VRSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5297           0 :   switch (VT.SimpleTy) {
    5298           0 :   case MVT::v8i8: return fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5299           0 :   case MVT::v16i8: return fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5300           0 :   case MVT::v4i16: return fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5301           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5302           0 :   case MVT::v2i32: return fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5303           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5304           0 :   case MVT::v1i64: return fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5305           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5306             :   default: return 0;
    5307             :   }
    5308             : }
    5309             : 
    5310             : // FastEmit functions for ARMISD::VRSHRu.
    5311             : 
    5312             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5313           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5314             :     return 0;
    5315           0 :   if ((Subtarget->hasNEON())) {
    5316           0 :     return fastEmitInst_ri(ARM::VRSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5317             :   }
    5318             :   return 0;
    5319             : }
    5320             : 
    5321             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5322           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5323             :     return 0;
    5324           0 :   if ((Subtarget->hasNEON())) {
    5325           0 :     return fastEmitInst_ri(ARM::VRSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5326             :   }
    5327             :   return 0;
    5328             : }
    5329             : 
    5330             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5331           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5332             :     return 0;
    5333           0 :   if ((Subtarget->hasNEON())) {
    5334           0 :     return fastEmitInst_ri(ARM::VRSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5335             :   }
    5336             :   return 0;
    5337             : }
    5338             : 
    5339             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5340           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5341             :     return 0;
    5342           0 :   if ((Subtarget->hasNEON())) {
    5343           0 :     return fastEmitInst_ri(ARM::VRSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5344             :   }
    5345             :   return 0;
    5346             : }
    5347             : 
    5348             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5349           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5350             :     return 0;
    5351           0 :   if ((Subtarget->hasNEON())) {
    5352           0 :     return fastEmitInst_ri(ARM::VRSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5353             :   }
    5354             :   return 0;
    5355             : }
    5356             : 
    5357             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5358           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5359             :     return 0;
    5360           0 :   if ((Subtarget->hasNEON())) {
    5361           0 :     return fastEmitInst_ri(ARM::VRSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5362             :   }
    5363             :   return 0;
    5364             : }
    5365             : 
    5366             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5367           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5368             :     return 0;
    5369           0 :   if ((Subtarget->hasNEON())) {
    5370           0 :     return fastEmitInst_ri(ARM::VRSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5371             :   }
    5372             :   return 0;
    5373             : }
    5374             : 
    5375             : unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5376           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5377             :     return 0;
    5378           0 :   if ((Subtarget->hasNEON())) {
    5379           0 :     return fastEmitInst_ri(ARM::VRSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5380             :   }
    5381             :   return 0;
    5382             : }
    5383             : 
    5384           0 : unsigned fastEmit_ARMISD_VRSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5385           0 :   switch (VT.SimpleTy) {
    5386           0 :   case MVT::v8i8: return fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5387           0 :   case MVT::v16i8: return fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5388           0 :   case MVT::v4i16: return fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5389           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5390           0 :   case MVT::v2i32: return fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5391           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5392           0 :   case MVT::v1i64: return fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5393           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5394             :   default: return 0;
    5395             :   }
    5396             : }
    5397             : 
    5398             : // FastEmit functions for ARMISD::VSHL.
    5399             : 
    5400             : unsigned fastEmit_ARMISD_VSHL_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5401           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5402             :     return 0;
    5403           0 :   if ((Subtarget->hasNEON())) {
    5404           0 :     return fastEmitInst_ri(ARM::VSHLiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5405             :   }
    5406             :   return 0;
    5407             : }
    5408             : 
    5409             : unsigned fastEmit_ARMISD_VSHL_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5410           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5411             :     return 0;
    5412           0 :   if ((Subtarget->hasNEON())) {
    5413           0 :     return fastEmitInst_ri(ARM::VSHLiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5414             :   }
    5415             :   return 0;
    5416             : }
    5417             : 
    5418             : unsigned fastEmit_ARMISD_VSHL_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5419           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5420             :     return 0;
    5421           0 :   if ((Subtarget->hasNEON())) {
    5422           0 :     return fastEmitInst_ri(ARM::VSHLiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5423             :   }
    5424             :   return 0;
    5425             : }
    5426             : 
    5427             : unsigned fastEmit_ARMISD_VSHL_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5428           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5429             :     return 0;
    5430           0 :   if ((Subtarget->hasNEON())) {
    5431           0 :     return fastEmitInst_ri(ARM::VSHLiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5432             :   }
    5433             :   return 0;
    5434             : }
    5435             : 
    5436             : unsigned fastEmit_ARMISD_VSHL_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5437           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5438             :     return 0;
    5439           0 :   if ((Subtarget->hasNEON())) {
    5440           0 :     return fastEmitInst_ri(ARM::VSHLiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5441             :   }
    5442             :   return 0;
    5443             : }
    5444             : 
    5445             : unsigned fastEmit_ARMISD_VSHL_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5446           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5447             :     return 0;
    5448           0 :   if ((Subtarget->hasNEON())) {
    5449           0 :     return fastEmitInst_ri(ARM::VSHLiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5450             :   }
    5451             :   return 0;
    5452             : }
    5453             : 
    5454             : unsigned fastEmit_ARMISD_VSHL_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5455           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5456             :     return 0;
    5457           0 :   if ((Subtarget->hasNEON())) {
    5458           0 :     return fastEmitInst_ri(ARM::VSHLiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5459             :   }
    5460             :   return 0;
    5461             : }
    5462             : 
    5463             : unsigned fastEmit_ARMISD_VSHL_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5464           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5465             :     return 0;
    5466           0 :   if ((Subtarget->hasNEON())) {
    5467           0 :     return fastEmitInst_ri(ARM::VSHLiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5468             :   }
    5469             :   return 0;
    5470             : }
    5471             : 
    5472           0 : unsigned fastEmit_ARMISD_VSHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5473           0 :   switch (VT.SimpleTy) {
    5474           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHL_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5475           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHL_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5476           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHL_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5477           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHL_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5478           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHL_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5479           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHL_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5480           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHL_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5481           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHL_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5482             :   default: return 0;
    5483             :   }
    5484             : }
    5485             : 
    5486             : // FastEmit functions for ARMISD::VSHRs.
    5487             : 
    5488             : unsigned fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5489           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5490             :     return 0;
    5491           0 :   if ((Subtarget->hasNEON())) {
    5492           0 :     return fastEmitInst_ri(ARM::VSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5493             :   }
    5494             :   return 0;
    5495             : }
    5496             : 
    5497             : unsigned fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5498           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5499             :     return 0;
    5500           0 :   if ((Subtarget->hasNEON())) {
    5501           0 :     return fastEmitInst_ri(ARM::VSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5502             :   }
    5503             :   return 0;
    5504             : }
    5505             : 
    5506             : unsigned fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5507           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5508             :     return 0;
    5509           0 :   if ((Subtarget->hasNEON())) {
    5510           0 :     return fastEmitInst_ri(ARM::VSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5511             :   }
    5512             :   return 0;
    5513             : }
    5514             : 
    5515             : unsigned fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5516           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5517             :     return 0;
    5518           0 :   if ((Subtarget->hasNEON())) {
    5519           0 :     return fastEmitInst_ri(ARM::VSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5520             :   }
    5521             :   return 0;
    5522             : }
    5523             : 
    5524             : unsigned fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5525           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5526             :     return 0;
    5527           0 :   if ((Subtarget->hasNEON())) {
    5528           0 :     return fastEmitInst_ri(ARM::VSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5529             :   }
    5530             :   return 0;
    5531             : }
    5532             : 
    5533             : unsigned fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5534           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5535             :     return 0;
    5536           0 :   if ((Subtarget->hasNEON())) {
    5537           0 :     return fastEmitInst_ri(ARM::VSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5538             :   }
    5539             :   return 0;
    5540             : }
    5541             : 
    5542             : unsigned fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5543           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5544             :     return 0;
    5545           0 :   if ((Subtarget->hasNEON())) {
    5546           0 :     return fastEmitInst_ri(ARM::VSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5547             :   }
    5548             :   return 0;
    5549             : }
    5550             : 
    5551             : unsigned fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5552           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5553             :     return 0;
    5554           0 :   if ((Subtarget->hasNEON())) {
    5555           0 :     return fastEmitInst_ri(ARM::VSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5556             :   }
    5557             :   return 0;
    5558             : }
    5559             : 
    5560           0 : unsigned fastEmit_ARMISD_VSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5561           0 :   switch (VT.SimpleTy) {
    5562           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5563           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5564           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5565           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5566           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5567           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5568           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5569           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5570             :   default: return 0;
    5571             :   }
    5572             : }
    5573             : 
    5574             : // FastEmit functions for ARMISD::VSHRu.
    5575             : 
    5576             : unsigned fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5577           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    5578             :     return 0;
    5579           0 :   if ((Subtarget->hasNEON())) {
    5580           0 :     return fastEmitInst_ri(ARM::VSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5581             :   }
    5582             :   return 0;
    5583             : }
    5584             : 
    5585             : unsigned fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5586           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    5587             :     return 0;
    5588           0 :   if ((Subtarget->hasNEON())) {
    5589           0 :     return fastEmitInst_ri(ARM::VSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5590             :   }
    5591             :   return 0;
    5592             : }
    5593             : 
    5594             : unsigned fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5595           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    5596             :     return 0;
    5597           0 :   if ((Subtarget->hasNEON())) {
    5598           0 :     return fastEmitInst_ri(ARM::VSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5599             :   }
    5600             :   return 0;
    5601             : }
    5602             : 
    5603             : unsigned fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5604           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    5605             :     return 0;
    5606           0 :   if ((Subtarget->hasNEON())) {
    5607           0 :     return fastEmitInst_ri(ARM::VSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5608             :   }
    5609             :   return 0;
    5610             : }
    5611             : 
    5612             : unsigned fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5613           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    5614             :     return 0;
    5615           0 :   if ((Subtarget->hasNEON())) {
    5616           0 :     return fastEmitInst_ri(ARM::VSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5617             :   }
    5618             :   return 0;
    5619             : }
    5620             : 
    5621             : unsigned fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5622           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    5623             :     return 0;
    5624           0 :   if ((Subtarget->hasNEON())) {
    5625           0 :     return fastEmitInst_ri(ARM::VSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5626             :   }
    5627             :   return 0;
    5628             : }
    5629             : 
    5630             : unsigned fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5631           0 :   if (RetVT.SimpleTy != MVT::v1i64)
    5632             :     return 0;
    5633           0 :   if ((Subtarget->hasNEON())) {
    5634           0 :     return fastEmitInst_ri(ARM::VSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    5635             :   }
    5636             :   return 0;
    5637             : }
    5638             : 
    5639             : unsigned fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5640           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    5641             :     return 0;
    5642           0 :   if ((Subtarget->hasNEON())) {
    5643           0 :     return fastEmitInst_ri(ARM::VSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    5644             :   }
    5645             :   return 0;
    5646             : }
    5647             : 
    5648           0 : unsigned fastEmit_ARMISD_VSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5649           0 :   switch (VT.SimpleTy) {
    5650           0 :   case MVT::v8i8: return fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5651           0 :   case MVT::v16i8: return fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
    5652           0 :   case MVT::v4i16: return fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5653           0 :   case MVT::v8i16: return fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
    5654           0 :   case MVT::v2i32: return fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5655           0 :   case MVT::v4i32: return fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5656           0 :   case MVT::v1i64: return fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5657           0 :   case MVT::v2i64: return fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
    5658             :   default: return 0;
    5659             :   }
    5660             : }
    5661             : 
    5662             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    5663             : 
    5664           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5665           0 :   if (RetVT.SimpleTy != MVT::i32)
    5666             :     return 0;
    5667           0 :   if ((!Subtarget->hasSlowVGETLNi32()) && (Subtarget->hasVFP2())) {
    5668           0 :     return fastEmitInst_ri(ARM::VGETLNi32, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5669             :   }
    5670             :   return 0;
    5671             : }
    5672             : 
    5673             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5674           0 :   switch (VT.SimpleTy) {
    5675           0 :   case MVT::v2i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5676             :   default: return 0;
    5677             :   }
    5678             : }
    5679             : 
    5680             : // FastEmit functions for ISD::SHL.
    5681             : 
    5682           3 : unsigned fastEmit_ISD_SHL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5683           3 :   if (RetVT.SimpleTy != MVT::i32)
    5684             :     return 0;
    5685           3 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5686           0 :     return fastEmitInst_ri(ARM::tLSLri, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5687             :   }
    5688             :   return 0;
    5689             : }
    5690             : 
    5691             : unsigned fastEmit_ISD_SHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5692           3 :   switch (VT.SimpleTy) {
    5693           3 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    5694             :   default: return 0;
    5695             :   }
    5696             : }
    5697             : 
    5698             : // Top-level FastEmit function.
    5699             : 
    5700         504 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    5701        1008 :   if (VT == MVT::i32 && Predicate_mod_imm(imm1))
    5702         255 :     if (unsigned Reg = fastEmit_ri_Predicate_mod_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5703             :       return Reg;
    5704             : 
    5705         462 :   if (VT == MVT::i32 && Predicate_imm0_7(imm1))
    5706          27 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_7(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5707             :       return Reg;
    5708             : 
    5709         924 :   if (VT == MVT::i32 && Predicate_imm8_255(imm1))
    5710          13 :     if (unsigned Reg = fastEmit_ri_Predicate_imm8_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5711             :       return Reg;
    5712             : 
    5713         462 :   if (VT == MVT::i32 && Predicate_imm0_255(imm1))
    5714          40 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5715             :       return Reg;
    5716             : 
    5717         924 :   if (VT == MVT::i32 && Predicate_t2_so_imm(imm1))
    5718         243 :     if (unsigned Reg = fastEmit_ri_Predicate_t2_so_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5719             :       return Reg;
    5720             : 
    5721         234 :   if (VT == MVT::i32 && Predicate_imm0_4095(imm1))
    5722         210 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_4095(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5723             :       return Reg;
    5724             : 
    5725          90 :   if (VT == MVT::i32 && Predicate_imm1_31(imm1))
    5726          15 :     if (unsigned Reg = fastEmit_ri_Predicate_imm1_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5727             :       return Reg;
    5728             : 
    5729          39 :   if (VT == MVT::i32 && Predicate_imm0_31(imm1))
    5730           9 :     if (unsigned Reg = fastEmit_ri_Predicate_imm0_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5731             :       return Reg;
    5732             : 
    5733          78 :   if (VT == MVT::i32 && Predicate_shr_imm8(imm1))
    5734           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5735             :       return Reg;
    5736             : 
    5737          78 :   if (VT == MVT::i32 && Predicate_shr_imm16(imm1))
    5738           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5739             :       return Reg;
    5740             : 
    5741          78 :   if (VT == MVT::i32 && Predicate_shr_imm32(imm1))
    5742           9 :     if (unsigned Reg = fastEmit_ri_Predicate_shr_imm32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5743             :       return Reg;
    5744             : 
    5745          39 :   if (VT == MVT::i32 && Predicate_VectorIndex32(imm1))
    5746           0 :     if (unsigned Reg = fastEmit_ri_Predicate_VectorIndex32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    5747             :       return Reg;
    5748             : 
    5749          39 :   switch (Opcode) {
    5750           0 :   case ARMISD::PIC_ADD: return fastEmit_ARMISD_PIC_ADD_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5751           0 :   case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5752           0 :   case ARMISD::VGETLANEs: return fastEmit_ARMISD_VGETLANEs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5753           0 :   case ARMISD::VGETLANEu: return fastEmit_ARMISD_VGETLANEu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5754           0 :   case ARMISD::VQSHLs: return fastEmit_ARMISD_VQSHLs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5755           0 :   case ARMISD::VQSHLsu: return fastEmit_ARMISD_VQSHLsu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5756           0 :   case ARMISD::VQSHLu: return fastEmit_ARMISD_VQSHLu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5757           0 :   case ARMISD::VRSHRs: return fastEmit_ARMISD_VRSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5758           0 :   case ARMISD::VRSHRu: return fastEmit_ARMISD_VRSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5759           0 :   case ARMISD::VSHL: return fastEmit_ARMISD_VSHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5760           0 :   case ARMISD::VSHRs: return fastEmit_ARMISD_VSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5761           0 :   case ARMISD::VSHRu: return fastEmit_ARMISD_VSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5762           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5763           3 :   case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    5764             :   default: return 0;
    5765             :   }
    5766             : }
    5767             : 
    5768             : // FastEmit functions for ARMISD::CMN.
    5769             : 
    5770             : unsigned fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5771           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5772             :     return 0;
    5773           0 :   if ((!Subtarget->isThumb())) {
    5774           0 :     return fastEmitInst_ri(ARM::CMNri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5775             :   }
    5776             :   return 0;
    5777             : }
    5778             : 
    5779           0 : unsigned fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5780           0 :   switch (VT.SimpleTy) {
    5781           0 :   case MVT::i32: return fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5782             :   default: return 0;
    5783             :   }
    5784             : }
    5785             : 
    5786             : // FastEmit functions for ARMISD::CMP.
    5787             : 
    5788             : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5789           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5790             :     return 0;
    5791           0 :   if ((!Subtarget->isThumb())) {
    5792           0 :     return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5793             :   }
    5794             :   return 0;
    5795             : }
    5796             : 
    5797           0 : unsigned fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5798           0 :   switch (VT.SimpleTy) {
    5799           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5800             :   default: return 0;
    5801             :   }
    5802             : }
    5803             : 
    5804             : // FastEmit functions for ARMISD::CMPZ.
    5805             : 
    5806             : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5807           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5808             :     return 0;
    5809           0 :   if ((!Subtarget->isThumb())) {
    5810           0 :     return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5811             :   }
    5812             :   return 0;
    5813             : }
    5814             : 
    5815           0 : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5816           0 :   switch (VT.SimpleTy) {
    5817           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5818             :   default: return 0;
    5819             :   }
    5820             : }
    5821             : 
    5822             : // FastEmit functions for ISD::ADD.
    5823             : 
    5824             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5825         234 :   if (RetVT.SimpleTy != MVT::i32)
    5826             :     return 0;
    5827         234 :   if ((!Subtarget->isThumb())) {
    5828          38 :     return fastEmitInst_ri(ARM::ADDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5829             :   }
    5830             :   return 0;
    5831             : }
    5832             : 
    5833         234 : unsigned fastEmit_ISD_ADD_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5834         234 :   switch (VT.SimpleTy) {
    5835         234 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5836             :   default: return 0;
    5837             :   }
    5838             : }
    5839             : 
    5840             : // FastEmit functions for ISD::AND.
    5841             : 
    5842             : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5843           3 :   if (RetVT.SimpleTy != MVT::i32)
    5844             :     return 0;
    5845           3 :   if ((!Subtarget->isThumb())) {
    5846           2 :     return fastEmitInst_ri(ARM::ANDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5847             :   }
    5848             :   return 0;
    5849             : }
    5850             : 
    5851           3 : unsigned fastEmit_ISD_AND_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5852           3 :   switch (VT.SimpleTy) {
    5853           3 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5854             :   default: return 0;
    5855             :   }
    5856             : }
    5857             : 
    5858             : // FastEmit functions for ISD::OR.
    5859             : 
    5860             : unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5861           3 :   if (RetVT.SimpleTy != MVT::i32)
    5862             :     return 0;
    5863           3 :   if ((!Subtarget->isThumb())) {
    5864           2 :     return fastEmitInst_ri(ARM::ORRri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5865             :   }
    5866             :   return 0;
    5867             : }
    5868             : 
    5869           3 : unsigned fastEmit_ISD_OR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5870           3 :   switch (VT.SimpleTy) {
    5871           3 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5872             :   default: return 0;
    5873             :   }
    5874             : }
    5875             : 
    5876             : // FastEmit functions for ISD::SUB.
    5877             : 
    5878             : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5879           0 :   if (RetVT.SimpleTy != MVT::i32)
    5880             :     return 0;
    5881           0 :   if ((!Subtarget->isThumb())) {
    5882           0 :     return fastEmitInst_ri(ARM::SUBri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5883             :   }
    5884             :   return 0;
    5885             : }
    5886             : 
    5887           0 : unsigned fastEmit_ISD_SUB_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5888           0 :   switch (VT.SimpleTy) {
    5889           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5890             :   default: return 0;
    5891             :   }
    5892             : }
    5893             : 
    5894             : // FastEmit functions for ISD::XOR.
    5895             : 
    5896             : unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5897           0 :   if (RetVT.SimpleTy != MVT::i32)
    5898             :     return 0;
    5899           0 :   if ((!Subtarget->isThumb())) {
    5900           0 :     return fastEmitInst_ri(ARM::EORri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
    5901             :   }
    5902             :   return 0;
    5903             : }
    5904             : 
    5905           0 : unsigned fastEmit_ISD_XOR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5906           0 :   switch (VT.SimpleTy) {
    5907           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
    5908             :   default: return 0;
    5909             :   }
    5910             : }
    5911             : 
    5912             : // Top-level FastEmit function.
    5913             : 
    5914         255 : unsigned fastEmit_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5915         255 :   switch (Opcode) {
    5916           0 :   case ARMISD::CMN: return fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5917           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5918           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5919         234 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5920           3 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5921           3 :   case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5922           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5923           0 :   case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    5924             :   default: return 0;
    5925             :   }
    5926             : }
    5927             : 
    5928             : // FastEmit functions for ISD::ADD.
    5929             : 
    5930          11 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5931          11 :   if (RetVT.SimpleTy != MVT::i32)
    5932             :     return 0;
    5933          11 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5934           0 :     return fastEmitInst_ri(ARM::tADDi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5935             :   }
    5936             :   return 0;
    5937             : }
    5938             : 
    5939             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5940          11 :   switch (VT.SimpleTy) {
    5941          11 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1);
    5942             :   default: return 0;
    5943             :   }
    5944             : }
    5945             : 
    5946             : // Top-level FastEmit function.
    5947             : 
    5948          27 : unsigned fastEmit_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5949          27 :   switch (Opcode) {
    5950          11 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1);
    5951             :   default: return 0;
    5952             :   }
    5953             : }
    5954             : 
    5955             : // FastEmit functions for ISD::ADD.
    5956             : 
    5957          12 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5958          12 :   if (RetVT.SimpleTy != MVT::i32)
    5959             :     return 0;
    5960          12 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5961           0 :     return fastEmitInst_ri(ARM::tADDi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5962             :   }
    5963             :   return 0;
    5964             : }
    5965             : 
    5966             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5967          12 :   switch (VT.SimpleTy) {
    5968          12 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(RetVT, Op0, Op0IsKill, imm1);
    5969             :   default: return 0;
    5970             :   }
    5971             : }
    5972             : 
    5973             : // Top-level FastEmit function.
    5974             : 
    5975          13 : unsigned fastEmit_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5976          13 :   switch (Opcode) {
    5977          12 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm8_255(VT, RetVT, Op0, Op0IsKill, imm1);
    5978             :   default: return 0;
    5979             :   }
    5980             : }
    5981             : 
    5982             : // FastEmit functions for ARMISD::CMP.
    5983             : 
    5984           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5985           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    5986             :     return 0;
    5987           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    5988           0 :     return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    5989             :   }
    5990             :   return 0;
    5991             : }
    5992             : 
    5993             : unsigned fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    5994           0 :   switch (VT.SimpleTy) {
    5995           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1);
    5996             :   default: return 0;
    5997             :   }
    5998             : }
    5999             : 
    6000             : // FastEmit functions for ARMISD::CMPZ.
    6001             : 
    6002           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6003           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    6004             :     return 0;
    6005           0 :   if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
    6006           0 :     return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
    6007             :   }
    6008             :   return 0;
    6009             : }
    6010             : 
    6011             : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6012           0 :   switch (VT.SimpleTy) {
    6013           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1);
    6014             :   default: return 0;
    6015             :   }
    6016             : }
    6017             : 
    6018             : // Top-level FastEmit function.
    6019             : 
    6020          40 : unsigned fastEmit_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6021          40 :   switch (Opcode) {
    6022           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1);
    6023           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1);
    6024             :   default: return 0;
    6025             :   }
    6026             : }
    6027             : 
    6028             : // FastEmit functions for ARMISD::CMP.
    6029             : 
    6030           0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6031           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    6032             :     return 0;
    6033           0 :   if ((Subtarget->isThumb2())) {
    6034           0 :     return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6035             :   }
    6036             :   return 0;
    6037             : }
    6038             : 
    6039             : unsigned fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6040           0 :   switch (VT.SimpleTy) {
    6041           0 :   case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6042             :   default: return 0;
    6043             :   }
    6044             : }
    6045             : 
    6046             : // FastEmit functions for ARMISD::CMPZ.
    6047             : 
    6048           0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6049           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    6050             :     return 0;
    6051           0 :   if ((Subtarget->isThumb2())) {
    6052           0 :     return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6053             :   }
    6054             :   return 0;
    6055             : }
    6056             : 
    6057             : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6058           0 :   switch (VT.SimpleTy) {
    6059           0 :   case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6060             :   default: return 0;
    6061             :   }
    6062             : }
    6063             : 
    6064             : // FastEmit functions for ISD::ADD.
    6065             : 
    6066         226 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6067         226 :   if (RetVT.SimpleTy != MVT::i32)
    6068             :     return 0;
    6069         226 :   if ((Subtarget->isThumb2())) {
    6070         226 :     return fastEmitInst_ri(ARM::t2ADDri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6071             :   }
    6072             :   return 0;
    6073             : }
    6074             : 
    6075             : unsigned fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6076         226 :   switch (VT.SimpleTy) {
    6077         226 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6078             :   default: return 0;
    6079             :   }
    6080             : }
    6081             : 
    6082             : // FastEmit functions for ISD::AND.
    6083             : 
    6084           1 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6085           1 :   if (RetVT.SimpleTy != MVT::i32)
    6086             :     return 0;
    6087           1 :   if ((Subtarget->isThumb2())) {
    6088           1 :     return fastEmitInst_ri(ARM::t2ANDri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6089             :   }
    6090             :   return 0;
    6091             : }
    6092             : 
    6093             : unsigned fastEmit_ISD_AND_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6094           1 :   switch (VT.SimpleTy) {
    6095           1 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6096             :   default: return 0;
    6097             :   }
    6098             : }
    6099             : 
    6100             : // FastEmit functions for ISD::OR.
    6101             : 
    6102           1 : unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6103           1 :   if (RetVT.SimpleTy != MVT::i32)
    6104             :     return 0;
    6105           1 :   if ((Subtarget->isThumb2())) {
    6106           1 :     return fastEmitInst_ri(ARM::t2ORRri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6107             :   }
    6108             :   return 0;
    6109             : }
    6110             : 
    6111             : unsigned fastEmit_ISD_OR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6112           1 :   switch (VT.SimpleTy) {
    6113           1 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6114             :   default: return 0;
    6115             :   }
    6116             : }
    6117             : 
    6118             : // FastEmit functions for ISD::SUB.
    6119             : 
    6120           0 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6121           0 :   if (RetVT.SimpleTy != MVT::i32)
    6122             :     return 0;
    6123           0 :   if ((Subtarget->isThumb2())) {
    6124           0 :     return fastEmitInst_ri(ARM::t2SUBri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6125             :   }
    6126             :   return 0;
    6127             : }
    6128             : 
    6129             : unsigned fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6130           0 :   switch (VT.SimpleTy) {
    6131           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6132             :   default: return 0;
    6133             :   }
    6134             : }
    6135             : 
    6136             : // FastEmit functions for ISD::XOR.
    6137             : 
    6138           0 : unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6139           0 :   if (RetVT.SimpleTy != MVT::i32)
    6140             :     return 0;
    6141           0 :   if ((Subtarget->isThumb2())) {
    6142           0 :     return fastEmitInst_ri(ARM::t2EORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6143             :   }
    6144             :   return 0;
    6145             : }
    6146             : 
    6147             : unsigned fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6148           0 :   switch (VT.SimpleTy) {
    6149           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
    6150             :   default: return 0;
    6151             :   }
    6152             : }
    6153             : 
    6154             : // Top-level FastEmit function.
    6155             : 
    6156         243 : unsigned fastEmit_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6157         243 :   switch (Opcode) {
    6158           0 :   case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6159           0 :   case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6160         226 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6161           1 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6162           1 :   case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6163           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6164           0 :   case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
    6165             :   default: return 0;
    6166             :   }
    6167             : }
    6168             : 
    6169             : // FastEmit functions for ISD::ADD.
    6170             : 
    6171         195 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6172         195 :   if (RetVT.SimpleTy != MVT::i32)
    6173             :     return 0;
    6174         195 :   if ((Subtarget->isThumb2())) {
    6175         189 :     return fastEmitInst_ri(ARM::t2ADDri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6176             :   }
    6177             :   return 0;
    6178             : }
    6179             : 
    6180             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6181         195 :   switch (VT.SimpleTy) {
    6182         195 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1);
    6183             :   default: return 0;
    6184             :   }
    6185             : }
    6186             : 
    6187             : // FastEmit functions for ISD::SUB.
    6188             : 
    6189           0 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6190           0 :   if (RetVT.SimpleTy != MVT::i32)
    6191             :     return 0;
    6192           0 :   if ((Subtarget->isThumb2())) {
    6193           0 :     return fastEmitInst_ri(ARM::t2SUBri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
    6194             :   }
    6195             :   return 0;
    6196             : }
    6197             : 
    6198             : unsigned fastEmit_ISD_SUB_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6199           0 :   switch (VT.SimpleTy) {
    6200           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1);
    6201             :   default: return 0;
    6202             :   }
    6203             : }
    6204             : 
    6205             : // Top-level FastEmit function.
    6206             : 
    6207         210 : unsigned fastEmit_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6208         210 :   switch (Opcode) {
    6209         195 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
    6210           0 :   case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
    6211             :   default: return 0;
    6212             :   }
    6213             : }
    6214             : 
    6215             : // FastEmit functions for ISD::SHL.
    6216             : 
    6217           9 : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6218           9 :   if (RetVT.SimpleTy != MVT::i32)
    6219             :     return 0;
    6220           9 :   if ((Subtarget->isThumb2())) {
    6221           6 :     return fastEmitInst_ri(ARM::t2LSLri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6222             :   }
    6223             :   return 0;
    6224             : }
    6225             : 
    6226             : unsigned fastEmit_ISD_SHL_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6227           9 :   switch (VT.SimpleTy) {
    6228           9 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(RetVT, Op0, Op0IsKill, imm1);
    6229             :   default: return 0;
    6230             :   }
    6231             : }
    6232             : 
    6233             : // Top-level FastEmit function.
    6234             : 
    6235          15 : unsigned fastEmit_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6236          15 :   switch (Opcode) {
    6237           9 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_imm1_31(VT, RetVT, Op0, Op0IsKill, imm1);
    6238             :   default: return 0;
    6239             :   }
    6240             : }
    6241             : 
    6242             : // FastEmit functions for ISD::ROTR.
    6243             : 
    6244           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6245           0 :   if (RetVT.SimpleTy != MVT::i32)
    6246             :     return 0;
    6247           0 :   if ((Subtarget->isThumb2())) {
    6248           0 :     return fastEmitInst_ri(ARM::t2RORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
    6249             :   }
    6250             :   return 0;
    6251             : }
    6252             : 
    6253             : unsigned fastEmit_ISD_ROTR_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6254           0 :   switch (VT.SimpleTy) {
    6255           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1);
    6256             :   default: return 0;
    6257             :   }
    6258             : }
    6259             : 
    6260             : // Top-level FastEmit function.
    6261             : 
    6262           9 : unsigned fastEmit_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6263           9 :   switch (Opcode) {
    6264           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1);
    6265             :   default: return 0;
    6266             :   }
    6267             : }
    6268             : 
    6269             : // FastEmit functions for ARMISD::VQRSHRNs.
    6270             : 
    6271             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6272           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6273             :     return 0;
    6274           0 :   if ((Subtarget->hasNEON())) {
    6275           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6276             :   }
    6277             :   return 0;
    6278             : }
    6279             : 
    6280           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6281           0 :   switch (VT.SimpleTy) {
    6282           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6283             :   default: return 0;
    6284             :   }
    6285             : }
    6286             : 
    6287             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6288             : 
    6289             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6290           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6291             :     return 0;
    6292           0 :   if ((Subtarget->hasNEON())) {
    6293           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6294             :   }
    6295             :   return 0;
    6296             : }
    6297             : 
    6298           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6299           0 :   switch (VT.SimpleTy) {
    6300           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6301             :   default: return 0;
    6302             :   }
    6303             : }
    6304             : 
    6305             : // FastEmit functions for ARMISD::VQRSHRNu.
    6306             : 
    6307             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6308           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6309             :     return 0;
    6310           0 :   if ((Subtarget->hasNEON())) {
    6311           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6312             :   }
    6313             :   return 0;
    6314             : }
    6315             : 
    6316           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6317           0 :   switch (VT.SimpleTy) {
    6318           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6319             :   default: return 0;
    6320             :   }
    6321             : }
    6322             : 
    6323             : // FastEmit functions for ARMISD::VQSHRNs.
    6324             : 
    6325             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6326           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6327             :     return 0;
    6328           0 :   if ((Subtarget->hasNEON())) {
    6329           0 :     return fastEmitInst_ri(ARM::VQSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6330             :   }
    6331             :   return 0;
    6332             : }
    6333             : 
    6334           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6335           0 :   switch (VT.SimpleTy) {
    6336           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6337             :   default: return 0;
    6338             :   }
    6339             : }
    6340             : 
    6341             : // FastEmit functions for ARMISD::VQSHRNsu.
    6342             : 
    6343             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6344           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6345             :     return 0;
    6346           0 :   if ((Subtarget->hasNEON())) {
    6347           0 :     return fastEmitInst_ri(ARM::VQSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6348             :   }
    6349             :   return 0;
    6350             : }
    6351             : 
    6352           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6353           0 :   switch (VT.SimpleTy) {
    6354           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6355             :   default: return 0;
    6356             :   }
    6357             : }
    6358             : 
    6359             : // FastEmit functions for ARMISD::VQSHRNu.
    6360             : 
    6361             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6362           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6363             :     return 0;
    6364           0 :   if ((Subtarget->hasNEON())) {
    6365           0 :     return fastEmitInst_ri(ARM::VQSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6366             :   }
    6367             :   return 0;
    6368             : }
    6369             : 
    6370           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6371           0 :   switch (VT.SimpleTy) {
    6372           0 :   case MVT::v8i16: return fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6373             :   default: return 0;
    6374             :   }
    6375             : }
    6376             : 
    6377             : // FastEmit functions for ARMISD::VRSHRN.
    6378             : 
    6379             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6380           0 :   if (RetVT.SimpleTy != MVT::v8i8)
    6381             :     return 0;
    6382           0 :   if ((Subtarget->hasNEON())) {
    6383           0 :     return fastEmitInst_ri(ARM::VRSHRNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6384             :   }
    6385             :   return 0;
    6386             : }
    6387             : 
    6388           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6389           0 :   switch (VT.SimpleTy) {
    6390           0 :   case MVT::v8i16: return fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
    6391             :   default: return 0;
    6392             :   }
    6393             : }
    6394             : 
    6395             : // Top-level FastEmit function.
    6396             : 
    6397           9 : unsigned fastEmit_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6398           9 :   switch (Opcode) {
    6399           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6400           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6401           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6402           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6403           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6404           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6405           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
    6406             :   default: return 0;
    6407             :   }
    6408             : }
    6409             : 
    6410             : // FastEmit functions for ARMISD::VQRSHRNs.
    6411             : 
    6412             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6413           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6414             :     return 0;
    6415           0 :   if ((Subtarget->hasNEON())) {
    6416           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6417             :   }
    6418             :   return 0;
    6419             : }
    6420             : 
    6421           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6422           0 :   switch (VT.SimpleTy) {
    6423           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6424             :   default: return 0;
    6425             :   }
    6426             : }
    6427             : 
    6428             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6429             : 
    6430             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6431           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6432             :     return 0;
    6433           0 :   if ((Subtarget->hasNEON())) {
    6434           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6435             :   }
    6436             :   return 0;
    6437             : }
    6438             : 
    6439           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6440           0 :   switch (VT.SimpleTy) {
    6441           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6442             :   default: return 0;
    6443             :   }
    6444             : }
    6445             : 
    6446             : // FastEmit functions for ARMISD::VQRSHRNu.
    6447             : 
    6448             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6449           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6450             :     return 0;
    6451           0 :   if ((Subtarget->hasNEON())) {
    6452           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6453             :   }
    6454             :   return 0;
    6455             : }
    6456             : 
    6457           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6458           0 :   switch (VT.SimpleTy) {
    6459           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6460             :   default: return 0;
    6461             :   }
    6462             : }
    6463             : 
    6464             : // FastEmit functions for ARMISD::VQSHRNs.
    6465             : 
    6466             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6467           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6468             :     return 0;
    6469           0 :   if ((Subtarget->hasNEON())) {
    6470           0 :     return fastEmitInst_ri(ARM::VQSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6471             :   }
    6472             :   return 0;
    6473             : }
    6474             : 
    6475           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6476           0 :   switch (VT.SimpleTy) {
    6477           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6478             :   default: return 0;
    6479             :   }
    6480             : }
    6481             : 
    6482             : // FastEmit functions for ARMISD::VQSHRNsu.
    6483             : 
    6484             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6485           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6486             :     return 0;
    6487           0 :   if ((Subtarget->hasNEON())) {
    6488           0 :     return fastEmitInst_ri(ARM::VQSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6489             :   }
    6490             :   return 0;
    6491             : }
    6492             : 
    6493           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6494           0 :   switch (VT.SimpleTy) {
    6495           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6496             :   default: return 0;
    6497             :   }
    6498             : }
    6499             : 
    6500             : // FastEmit functions for ARMISD::VQSHRNu.
    6501             : 
    6502             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6503           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6504             :     return 0;
    6505           0 :   if ((Subtarget->hasNEON())) {
    6506           0 :     return fastEmitInst_ri(ARM::VQSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6507             :   }
    6508             :   return 0;
    6509             : }
    6510             : 
    6511           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6512           0 :   switch (VT.SimpleTy) {
    6513           0 :   case MVT::v4i32: return fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6514             :   default: return 0;
    6515             :   }
    6516             : }
    6517             : 
    6518             : // FastEmit functions for ARMISD::VRSHRN.
    6519             : 
    6520             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6521           0 :   if (RetVT.SimpleTy != MVT::v4i16)
    6522             :     return 0;
    6523           0 :   if ((Subtarget->hasNEON())) {
    6524           0 :     return fastEmitInst_ri(ARM::VRSHRNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6525             :   }
    6526             :   return 0;
    6527             : }
    6528             : 
    6529           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6530           0 :   switch (VT.SimpleTy) {
    6531           0 :   case MVT::v4i32: return fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
    6532             :   default: return 0;
    6533             :   }
    6534             : }
    6535             : 
    6536             : // Top-level FastEmit function.
    6537             : 
    6538           9 : unsigned fastEmit_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6539           9 :   switch (Opcode) {
    6540           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6541           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6542           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6543           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6544           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6545           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6546           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
    6547             :   default: return 0;
    6548             :   }
    6549             : }
    6550             : 
    6551             : // FastEmit functions for ARMISD::VQRSHRNs.
    6552             : 
    6553             : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6554           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6555             :     return 0;
    6556           0 :   if ((Subtarget->hasNEON())) {
    6557           0 :     return fastEmitInst_ri(ARM::VQRSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6558             :   }
    6559             :   return 0;
    6560             : }
    6561             : 
    6562           0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6563           0 :   switch (VT.SimpleTy) {
    6564           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6565             :   default: return 0;
    6566             :   }
    6567             : }
    6568             : 
    6569             : // FastEmit functions for ARMISD::VQRSHRNsu.
    6570             : 
    6571             : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6572           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6573             :     return 0;
    6574           0 :   if ((Subtarget->hasNEON())) {
    6575           0 :     return fastEmitInst_ri(ARM::VQRSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6576             :   }
    6577             :   return 0;
    6578             : }
    6579             : 
    6580           0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6581           0 :   switch (VT.SimpleTy) {
    6582           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6583             :   default: return 0;
    6584             :   }
    6585             : }
    6586             : 
    6587             : // FastEmit functions for ARMISD::VQRSHRNu.
    6588             : 
    6589             : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6590           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6591             :     return 0;
    6592           0 :   if ((Subtarget->hasNEON())) {
    6593           0 :     return fastEmitInst_ri(ARM::VQRSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6594             :   }
    6595             :   return 0;
    6596             : }
    6597             : 
    6598           0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6599           0 :   switch (VT.SimpleTy) {
    6600           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6601             :   default: return 0;
    6602             :   }
    6603             : }
    6604             : 
    6605             : // FastEmit functions for ARMISD::VQSHRNs.
    6606             : 
    6607             : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6608           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6609             :     return 0;
    6610           0 :   if ((Subtarget->hasNEON())) {
    6611           0 :     return fastEmitInst_ri(ARM::VQSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6612             :   }
    6613             :   return 0;
    6614             : }
    6615             : 
    6616           0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6617           0 :   switch (VT.SimpleTy) {
    6618           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6619             :   default: return 0;
    6620             :   }
    6621             : }
    6622             : 
    6623             : // FastEmit functions for ARMISD::VQSHRNsu.
    6624             : 
    6625             : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6626           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6627             :     return 0;
    6628           0 :   if ((Subtarget->hasNEON())) {
    6629           0 :     return fastEmitInst_ri(ARM::VQSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6630             :   }
    6631             :   return 0;
    6632             : }
    6633             : 
    6634           0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6635           0 :   switch (VT.SimpleTy) {
    6636           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6637             :   default: return 0;
    6638             :   }
    6639             : }
    6640             : 
    6641             : // FastEmit functions for ARMISD::VQSHRNu.
    6642             : 
    6643             : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6644           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6645             :     return 0;
    6646           0 :   if ((Subtarget->hasNEON())) {
    6647           0 :     return fastEmitInst_ri(ARM::VQSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6648             :   }
    6649             :   return 0;
    6650             : }
    6651             : 
    6652           0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6653           0 :   switch (VT.SimpleTy) {
    6654           0 :   case MVT::v2i64: return fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6655             :   default: return 0;
    6656             :   }
    6657             : }
    6658             : 
    6659             : // FastEmit functions for ARMISD::VRSHRN.
    6660             : 
    6661             : unsigned fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6662           0 :   if (RetVT.SimpleTy != MVT::v2i32)
    6663             :     return 0;
    6664           0 :   if ((Subtarget->hasNEON())) {
    6665           0 :     return fastEmitInst_ri(ARM::VRSHRNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
    6666             :   }
    6667             :   return 0;
    6668             : }
    6669             : 
    6670           0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6671           0 :   switch (VT.SimpleTy) {
    6672           0 :   case MVT::v2i64: return fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
    6673             :   default: return 0;
    6674             :   }
    6675             : }
    6676             : 
    6677             : // Top-level FastEmit function.
    6678             : 
    6679           9 : unsigned fastEmit_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6680           9 :   switch (Opcode) {
    6681           0 :   case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6682           0 :   case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6683           0 :   case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6684           0 :   case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6685           0 :   case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6686           0 :   case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6687           0 :   case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
    6688             :   default: return 0;
    6689             :   }
    6690             : }
    6691             : 
    6692             : // FastEmit functions for ARMISD::VDUPLANE.
    6693             : 
    6694             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6695           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    6696             :     return 0;
    6697           0 :   if ((Subtarget->hasNEON())) {
    6698           0 :     return fastEmitInst_ri(ARM::VDUPLN8q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6699             :   }
    6700             :   return 0;
    6701             : }
    6702             : 
    6703             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6704           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    6705             :     return 0;
    6706           0 :   if ((Subtarget->hasNEON())) {
    6707           0 :     return fastEmitInst_ri(ARM::VDUPLN16q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6708             :   }
    6709             :   return 0;
    6710             : }
    6711             : 
    6712             : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6713           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    6714             :     return 0;
    6715           0 :   if ((Subtarget->hasNEON())) {
    6716           0 :     return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
    6717             :   }
    6718             :   return 0;
    6719             : }
    6720             : 
    6721           0 : unsigned fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6722           0 :   switch (VT.SimpleTy) {
    6723           0 :   case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6724           0 :   case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6725           0 :   case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
    6726             :   default: return 0;
    6727             :   }
    6728             : }
    6729             : 
    6730             : // Top-level FastEmit function.
    6731             : 
    6732             : unsigned fastEmit_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    6733           0 :   switch (Opcode) {
    6734           0 :   case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(VT, RetVT, Op0, Op0IsKill, imm1);
    6735             :   default: return 0;
    6736             :   }
    6737             : }
    6738             : 
    6739             : // FastEmit functions for ISD::Constant.
    6740             : 
    6741          45 : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    6742          45 :   if (RetVT.SimpleTy != MVT::i32)
    6743             :     return 0;
    6744          45 :   if ((Subtarget->isThumb()) && (Subtarget->useMovt(*MF))) {
    6745          15 :     return fastEmitInst_i(ARM::t2MOVi32imm, &ARM::rGPRRegClass, imm0);
    6746             :   }
    6747             :   return 0;
    6748             : }
    6749             : 
    6750             : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
    6751          45 :   switch (VT.SimpleTy) {
    6752          45 :   case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
    6753             :   default: return 0;
    6754             :   }
    6755             : }
    6756             : 
    6757             : // Top-level FastEmit function.
    6758             : 
    6759          39 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
    6760          39 :   switch (Opcode) {
    6761          39 :   case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
    6762             :   default: return 0;
    6763             :   }
    6764             : }
    6765             : 

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